diff options
author | Vipul Kumar Samar <vipulkumar.samar@st.com> | 2012-07-10 07:42:46 -0400 |
---|---|---|
committer | Shiraz Hashim <shiraz.hashim@st.com> | 2012-07-18 00:34:42 -0400 |
commit | a8f4bf0eb4ca7a0a578079fb5807e59b7111a1e2 (patch) | |
tree | f105486f3be03f9163b480ea0cc6240b5dde3922 /drivers/clk | |
parent | 5cfc545f50c4b6c0800e578b51019f2ecf490f1e (diff) |
Clk:spear6xx:Fix: Rename clk ids within predefined limit
The max limit of con_id is 16 and dev_id is 20. As of now for spear6xx, many clk
ids are exceeding this predefined limit.
This patch is intended to rename clk ids like:
mux_clk -> _mclk
gate_clk -> _gclk
synth_clk -> syn_clk
ras_gen1_synth_gate_clk -> ras_syn1_gclk
pll3_48m -> pll3_
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers/clk')
-rw-r--r-- | drivers/clk/spear/spear6xx_clock.c | 122 |
1 files changed, 60 insertions, 62 deletions
diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c index 61026ae564ab..a98d0866f541 100644 --- a/drivers/clk/spear/spear6xx_clock.c +++ b/drivers/clk/spear/spear6xx_clock.c | |||
@@ -97,13 +97,12 @@ static struct aux_rate_tbl aux_rtbl[] = { | |||
97 | {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */ | 97 | {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */ |
98 | }; | 98 | }; |
99 | 99 | ||
100 | static const char *clcd_parents[] = { "pll3_48m_clk", "clcd_synth_gate_clk", }; | 100 | static const char *clcd_parents[] = { "pll3_clk", "clcd_syn_gclk", }; |
101 | static const char *firda_parents[] = { "pll3_48m_clk", "firda_synth_gate_clk", | 101 | static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", }; |
102 | }; | 102 | static const char *uart_parents[] = { "pll3_clk", "uart_syn_gclk", }; |
103 | static const char *uart_parents[] = { "pll3_48m_clk", "uart_synth_gate_clk", }; | 103 | static const char *gpt0_1_parents[] = { "pll3_clk", "gpt0_1_syn_clk", }; |
104 | static const char *gpt0_1_parents[] = { "pll3_48m_clk", "gpt0_1_synth_clk", }; | 104 | static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", }; |
105 | static const char *gpt2_parents[] = { "pll3_48m_clk", "gpt2_synth_clk", }; | 105 | static const char *gpt3_parents[] = { "pll3_clk", "gpt3_syn_clk", }; |
106 | static const char *gpt3_parents[] = { "pll3_48m_clk", "gpt3_synth_clk", }; | ||
107 | static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none", | 106 | static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none", |
108 | "pll2_clk", }; | 107 | "pll2_clk", }; |
109 | 108 | ||
@@ -136,9 +135,9 @@ void __init spear6xx_clk_init(void) | |||
136 | clk_register_clkdev(clk, NULL, "rtc-spear"); | 135 | clk_register_clkdev(clk, NULL, "rtc-spear"); |
137 | 136 | ||
138 | /* clock derived from 30 MHz osc clk */ | 137 | /* clock derived from 30 MHz osc clk */ |
139 | clk = clk_register_fixed_rate(NULL, "pll3_48m_clk", "osc_24m_clk", 0, | 138 | clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0, |
140 | 48000000); | 139 | 48000000); |
141 | clk_register_clkdev(clk, "pll3_48m_clk", NULL); | 140 | clk_register_clkdev(clk, "pll3_clk", NULL); |
142 | 141 | ||
143 | clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk", | 142 | clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk", |
144 | 0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), | 143 | 0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), |
@@ -146,9 +145,9 @@ void __init spear6xx_clk_init(void) | |||
146 | clk_register_clkdev(clk, "vco1_clk", NULL); | 145 | clk_register_clkdev(clk, "vco1_clk", NULL); |
147 | clk_register_clkdev(clk1, "pll1_clk", NULL); | 146 | clk_register_clkdev(clk1, "pll1_clk", NULL); |
148 | 147 | ||
149 | clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, | 148 | clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk", |
150 | "osc_30m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl, | 149 | 0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), |
151 | ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); | 150 | &_lock, &clk1, NULL); |
152 | clk_register_clkdev(clk, "vco2_clk", NULL); | 151 | clk_register_clkdev(clk, "vco2_clk", NULL); |
153 | clk_register_clkdev(clk1, "pll2_clk", NULL); | 152 | clk_register_clkdev(clk1, "pll2_clk", NULL); |
154 | 153 | ||
@@ -165,111 +164,111 @@ void __init spear6xx_clk_init(void) | |||
165 | HCLK_RATIO_MASK, 0, &_lock); | 164 | HCLK_RATIO_MASK, 0, &_lock); |
166 | clk_register_clkdev(clk, "ahb_clk", NULL); | 165 | clk_register_clkdev(clk, "ahb_clk", NULL); |
167 | 166 | ||
168 | clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk", | 167 | clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0, |
169 | "pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl, | 168 | UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), |
170 | ARRAY_SIZE(aux_rtbl), &_lock, &clk1); | 169 | &_lock, &clk1); |
171 | clk_register_clkdev(clk, "uart_synth_clk", NULL); | 170 | clk_register_clkdev(clk, "uart_syn_clk", NULL); |
172 | clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL); | 171 | clk_register_clkdev(clk1, "uart_syn_gclk", NULL); |
173 | 172 | ||
174 | clk = clk_register_mux(NULL, "uart_mux_clk", uart_parents, | 173 | clk = clk_register_mux(NULL, "uart_mclk", uart_parents, |
175 | ARRAY_SIZE(uart_parents), 0, PERIP_CLK_CFG, | 174 | ARRAY_SIZE(uart_parents), 0, PERIP_CLK_CFG, |
176 | UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock); | 175 | UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock); |
177 | clk_register_clkdev(clk, "uart_mux_clk", NULL); | 176 | clk_register_clkdev(clk, "uart_mclk", NULL); |
178 | 177 | ||
179 | clk = clk_register_gate(NULL, "uart0", "uart_mux_clk", 0, | 178 | clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB, |
180 | PERIP1_CLK_ENB, UART0_CLK_ENB, 0, &_lock); | 179 | UART0_CLK_ENB, 0, &_lock); |
181 | clk_register_clkdev(clk, NULL, "d0000000.serial"); | 180 | clk_register_clkdev(clk, NULL, "d0000000.serial"); |
182 | 181 | ||
183 | clk = clk_register_gate(NULL, "uart1", "uart_mux_clk", 0, | 182 | clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB, |
184 | PERIP1_CLK_ENB, UART1_CLK_ENB, 0, &_lock); | 183 | UART1_CLK_ENB, 0, &_lock); |
185 | clk_register_clkdev(clk, NULL, "d0080000.serial"); | 184 | clk_register_clkdev(clk, NULL, "d0080000.serial"); |
186 | 185 | ||
187 | clk = clk_register_aux("firda_synth_clk", "firda_synth_gate_clk", | 186 | clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", |
188 | "pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, | 187 | 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), |
189 | ARRAY_SIZE(aux_rtbl), &_lock, &clk1); | 188 | &_lock, &clk1); |
190 | clk_register_clkdev(clk, "firda_synth_clk", NULL); | 189 | clk_register_clkdev(clk, "firda_syn_clk", NULL); |
191 | clk_register_clkdev(clk1, "firda_synth_gate_clk", NULL); | 190 | clk_register_clkdev(clk1, "firda_syn_gclk", NULL); |
192 | 191 | ||
193 | clk = clk_register_mux(NULL, "firda_mux_clk", firda_parents, | 192 | clk = clk_register_mux(NULL, "firda_mclk", firda_parents, |
194 | ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG, | 193 | ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG, |
195 | FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock); | 194 | FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock); |
196 | clk_register_clkdev(clk, "firda_mux_clk", NULL); | 195 | clk_register_clkdev(clk, "firda_mclk", NULL); |
197 | 196 | ||
198 | clk = clk_register_gate(NULL, "firda_clk", "firda_mux_clk", 0, | 197 | clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0, |
199 | PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock); | 198 | PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock); |
200 | clk_register_clkdev(clk, NULL, "firda"); | 199 | clk_register_clkdev(clk, NULL, "firda"); |
201 | 200 | ||
202 | clk = clk_register_aux("clcd_synth_clk", "clcd_synth_gate_clk", | 201 | clk = clk_register_aux("clcd_syn_clk", "clcd_syn_gclk", "pll1_clk", |
203 | "pll1_clk", 0, CLCD_CLK_SYNT, NULL, aux_rtbl, | 202 | 0, CLCD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), |
204 | ARRAY_SIZE(aux_rtbl), &_lock, &clk1); | 203 | &_lock, &clk1); |
205 | clk_register_clkdev(clk, "clcd_synth_clk", NULL); | 204 | clk_register_clkdev(clk, "clcd_syn_clk", NULL); |
206 | clk_register_clkdev(clk1, "clcd_synth_gate_clk", NULL); | 205 | clk_register_clkdev(clk1, "clcd_syn_gclk", NULL); |
207 | 206 | ||
208 | clk = clk_register_mux(NULL, "clcd_mux_clk", clcd_parents, | 207 | clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents, |
209 | ARRAY_SIZE(clcd_parents), 0, PERIP_CLK_CFG, | 208 | ARRAY_SIZE(clcd_parents), 0, PERIP_CLK_CFG, |
210 | CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0, &_lock); | 209 | CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0, &_lock); |
211 | clk_register_clkdev(clk, "clcd_mux_clk", NULL); | 210 | clk_register_clkdev(clk, "clcd_mclk", NULL); |
212 | 211 | ||
213 | clk = clk_register_gate(NULL, "clcd_clk", "clcd_mux_clk", 0, | 212 | clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0, |
214 | PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock); | 213 | PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock); |
215 | clk_register_clkdev(clk, NULL, "clcd"); | 214 | clk_register_clkdev(clk, NULL, "clcd"); |
216 | 215 | ||
217 | /* gpt clocks */ | 216 | /* gpt clocks */ |
218 | clk = clk_register_gpt("gpt0_1_synth_clk", "pll1_clk", 0, PRSC0_CLK_CFG, | 217 | clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, |
219 | gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); | 218 | gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); |
220 | clk_register_clkdev(clk, "gpt0_1_synth_clk", NULL); | 219 | clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL); |
221 | 220 | ||
222 | clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt0_1_parents, | 221 | clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents, |
223 | ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG, | 222 | ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG, |
224 | GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); | 223 | GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); |
225 | clk_register_clkdev(clk, NULL, "gpt0"); | 224 | clk_register_clkdev(clk, NULL, "gpt0"); |
226 | 225 | ||
227 | clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt0_1_parents, | 226 | clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents, |
228 | ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG, | 227 | ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG, |
229 | GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); | 228 | GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); |
230 | clk_register_clkdev(clk, "gpt1_mux_clk", NULL); | 229 | clk_register_clkdev(clk, "gpt1_mclk", NULL); |
231 | 230 | ||
232 | clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0, | 231 | clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, |
233 | PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock); | 232 | PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock); |
234 | clk_register_clkdev(clk, NULL, "gpt1"); | 233 | clk_register_clkdev(clk, NULL, "gpt1"); |
235 | 234 | ||
236 | clk = clk_register_gpt("gpt2_synth_clk", "pll1_clk", 0, PRSC1_CLK_CFG, | 235 | clk = clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, |
237 | gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); | 236 | gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); |
238 | clk_register_clkdev(clk, "gpt2_synth_clk", NULL); | 237 | clk_register_clkdev(clk, "gpt2_syn_clk", NULL); |
239 | 238 | ||
240 | clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt2_parents, | 239 | clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents, |
241 | ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG, | 240 | ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG, |
242 | GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); | 241 | GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); |
243 | clk_register_clkdev(clk, "gpt2_mux_clk", NULL); | 242 | clk_register_clkdev(clk, "gpt2_mclk", NULL); |
244 | 243 | ||
245 | clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0, | 244 | clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, |
246 | PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock); | 245 | PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock); |
247 | clk_register_clkdev(clk, NULL, "gpt2"); | 246 | clk_register_clkdev(clk, NULL, "gpt2"); |
248 | 247 | ||
249 | clk = clk_register_gpt("gpt3_synth_clk", "pll1_clk", 0, PRSC2_CLK_CFG, | 248 | clk = clk_register_gpt("gpt3_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, |
250 | gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); | 249 | gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); |
251 | clk_register_clkdev(clk, "gpt3_synth_clk", NULL); | 250 | clk_register_clkdev(clk, "gpt3_syn_clk", NULL); |
252 | 251 | ||
253 | clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt3_parents, | 252 | clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents, |
254 | ARRAY_SIZE(gpt3_parents), 0, PERIP_CLK_CFG, | 253 | ARRAY_SIZE(gpt3_parents), 0, PERIP_CLK_CFG, |
255 | GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); | 254 | GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); |
256 | clk_register_clkdev(clk, "gpt3_mux_clk", NULL); | 255 | clk_register_clkdev(clk, "gpt3_mclk", NULL); |
257 | 256 | ||
258 | clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0, | 257 | clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, |
259 | PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock); | 258 | PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock); |
260 | clk_register_clkdev(clk, NULL, "gpt3"); | 259 | clk_register_clkdev(clk, NULL, "gpt3"); |
261 | 260 | ||
262 | /* clock derived from pll3 clk */ | 261 | /* clock derived from pll3 clk */ |
263 | clk = clk_register_gate(NULL, "usbh0_clk", "pll3_48m_clk", 0, | 262 | clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0, |
264 | PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock); | 263 | PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock); |
265 | clk_register_clkdev(clk, NULL, "usbh.0_clk"); | 264 | clk_register_clkdev(clk, NULL, "usbh.0_clk"); |
266 | 265 | ||
267 | clk = clk_register_gate(NULL, "usbh1_clk", "pll3_48m_clk", 0, | 266 | clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0, |
268 | PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock); | 267 | PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock); |
269 | clk_register_clkdev(clk, NULL, "usbh.1_clk"); | 268 | clk_register_clkdev(clk, NULL, "usbh.1_clk"); |
270 | 269 | ||
271 | clk = clk_register_gate(NULL, "usbd_clk", "pll3_48m_clk", 0, | 270 | clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB, |
272 | PERIP1_CLK_ENB, USBD_CLK_ENB, 0, &_lock); | 271 | USBD_CLK_ENB, 0, &_lock); |
273 | clk_register_clkdev(clk, NULL, "designware_udc"); | 272 | clk_register_clkdev(clk, NULL, "designware_udc"); |
274 | 273 | ||
275 | /* clock derived from ahb clk */ | 274 | /* clock derived from ahb clk */ |
@@ -278,9 +277,8 @@ void __init spear6xx_clk_init(void) | |||
278 | clk_register_clkdev(clk, "ahbmult2_clk", NULL); | 277 | clk_register_clkdev(clk, "ahbmult2_clk", NULL); |
279 | 278 | ||
280 | clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, | 279 | clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, |
281 | ARRAY_SIZE(ddr_parents), | 280 | ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT, |
282 | 0, PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, | 281 | MCTR_CLK_MASK, 0, &_lock); |
283 | &_lock); | ||
284 | clk_register_clkdev(clk, "ddr_clk", NULL); | 282 | clk_register_clkdev(clk, "ddr_clk", NULL); |
285 | 283 | ||
286 | clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", | 284 | clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", |