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authorTushar Behera <tushar.behera@linaro.org>2013-05-17 01:55:52 -0400
committerMike Turquette <mturquette@linaro.org>2013-06-10 18:14:07 -0400
commit39b72d89eb2bf74ec94773defece6890febba7a5 (patch)
tree3dfa23ee6c1c7bb325da02e4641c5f4610281e2c /drivers/clk
parent72b5322f11ff0abf6a52b3007486656578d2c982 (diff)
clk: exynos5250: Update cpufreq related clocks for EXYNOS5250
cpufreq driver for EXYNOS5250 is not a platform driver, hence we cannot currently pass the clock names through a device tree node. Instead, we need to make them available through a global alias. cpufreq driver for EXYNOS5250 requires four clocks - 'armclk', 'mout_cpu', 'mout_mpll' and 'mout_apll'. 'armclk' has already been defined with an alias, 'mout_cpu', 'mout_mpll' and 'mout_apll' are now defined with an alias. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/samsung/clk-exynos5250.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 5c97e75924a8..05d099d0d8ba 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -208,10 +208,10 @@ struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
208}; 208};
209 209
210struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { 210struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
211 MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), 211 MUX_A(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, "mout_apll"),
212 MUX(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 212 MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
213 MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1), 213 MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
214 MUX(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1), 214 MUX_A(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
215 MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1), 215 MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
216 MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1), 216 MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
217 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1), 217 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),