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authorDoug Anderson <dianders@chromium.org>2013-06-11 11:24:05 -0400
committerMike Turquette <mturquette@linaro.org>2013-06-11 12:51:26 -0400
commit071ff9a36cb08b5a2b099fcdb45b63a61618f928 (patch)
treeaae3e0d37266606242ea6456ad09c43ffb5a7b2e /drivers/clk
parent589c603b2c591ed470a731ceda589e6d60b77b5f (diff)
clk: samsung: Fix pll36xx_recalc_rate to handle kdiv properly
The KDIV value is often listed as unsigned but it needs to be treated as a 16-bit signed value when using it in calculations. Fix our rate recalculation to do this correctly. Before doing this, I tried setting EPLL on exynos5250 to: rate, m, p, s, k = 80000000, 107, 2, 4, 43691 This rate is exactly from the table in the exynos5250 user manual. I read this back as 80750003 with: cat /sys/kernel/debug/clk/fin_pll/fout_epll/clk_rate After this patch, it reads back as 80000003 Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Reviewed-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/samsung/clk-pll.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 89135f6be116..362f12dcd944 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -111,7 +111,8 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
111 unsigned long parent_rate) 111 unsigned long parent_rate)
112{ 112{
113 struct samsung_clk_pll36xx *pll = to_clk_pll36xx(hw); 113 struct samsung_clk_pll36xx *pll = to_clk_pll36xx(hw);
114 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1; 114 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
115 s16 kdiv;
115 u64 fvco = parent_rate; 116 u64 fvco = parent_rate;
116 117
117 pll_con0 = __raw_readl(pll->con_reg); 118 pll_con0 = __raw_readl(pll->con_reg);
@@ -119,7 +120,7 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
119 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK; 120 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
120 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK; 121 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
121 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK; 122 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
122 kdiv = pll_con1 & PLL36XX_KDIV_MASK; 123 kdiv = (s16)(pll_con1 & PLL36XX_KDIV_MASK);
123 124
124 fvco *= (mdiv << 16) + kdiv; 125 fvco *= (mdiv << 16) + kdiv;
125 do_div(fvco, (pdiv << sdiv)); 126 do_div(fvco, (pdiv << sdiv));