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authorAndrew Lunn <andrew@lunn.ch>2013-02-05 16:52:51 -0500
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2013-02-09 06:56:08 -0500
commit2a4bd9f0db24ba14c8b38777d77add2682233c79 (patch)
treedf5c84538f118e63ff93e13456702086e58708bb /drivers/clk
parent93f0822dff5dae2f0a2645f16300c14af41ca777 (diff)
cpufreq: kirkwood: Add a cpufreq driver for Marvell Kirkwood SoCs
The Marvell Kirkwood SoCs have simple cpufreq support in hardware. The CPU can either use the a high speed cpu clock, or the slower DDR clock. Add a driver to swap between these two clock sources. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Jason Cooper <jason@lakedaemon.net> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/mvebu/clk-gating-ctrl.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
index 8fa5408b6c7d..ebf141d4374b 100644
--- a/drivers/clk/mvebu/clk-gating-ctrl.c
+++ b/drivers/clk/mvebu/clk-gating-ctrl.c
@@ -193,6 +193,7 @@ static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = {
193 { "runit", NULL, 7 }, 193 { "runit", NULL, 7 },
194 { "xor0", NULL, 8 }, 194 { "xor0", NULL, 8 },
195 { "audio", NULL, 9 }, 195 { "audio", NULL, 9 },
196 { "powersave", "cpuclk", 11 },
196 { "sata0", NULL, 14 }, 197 { "sata0", NULL, 14 },
197 { "sata1", NULL, 15 }, 198 { "sata1", NULL, 15 },
198 { "xor1", NULL, 16 }, 199 { "xor1", NULL, 16 },