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authorMichael Turquette <mturquette@linaro.org>2015-02-02 18:01:10 -0500
committerMichael Turquette <mturquette@linaro.org>2015-02-02 18:01:10 -0500
commitf85c6edfae0fea807956fd7890fc680414800cb7 (patch)
tree2d067ea135107f53b0e29747477edaeca238d761 /drivers/clk
parent54eea32f7ed3037c91853924227585b65df909a8 (diff)
parentb270491eb9a033a1ab6c66e778c9dd3e3a4f7639 (diff)
Merge tag 'tegra-clk-3.20' of git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-next
Tegra clock fixes for 3.20
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/tegra/Makefile1
-rw-r--r--drivers/clk/tegra/clk-id.h2
-rw-r--r--drivers/clk/tegra/clk-pll.c18
-rw-r--r--drivers/clk/tegra/clk-tegra-periph.c18
-rw-r--r--drivers/clk/tegra/clk-tegra114.c10
-rw-r--r--drivers/clk/tegra/clk-tegra124.c168
-rw-r--r--drivers/clk/tegra/clk.c7
7 files changed, 172 insertions, 52 deletions
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index f7dfb72884a4..edb8358fa6ce 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
15obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o 15obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
16obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o 16obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o
17obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o 17obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o
18obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index 0011d547a9f7..60738cc954cb 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -64,10 +64,8 @@ enum clk_id {
64 tegra_clk_disp2, 64 tegra_clk_disp2,
65 tegra_clk_dp2, 65 tegra_clk_dp2,
66 tegra_clk_dpaux, 66 tegra_clk_dpaux,
67 tegra_clk_dsia,
68 tegra_clk_dsialp, 67 tegra_clk_dsialp,
69 tegra_clk_dsia_mux, 68 tegra_clk_dsia_mux,
70 tegra_clk_dsib,
71 tegra_clk_dsiblp, 69 tegra_clk_dsiblp,
72 tegra_clk_dsib_mux, 70 tegra_clk_dsib_mux,
73 tegra_clk_dtv, 71 tegra_clk_dtv,
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index c7c6d8fb32fb..bfef9abdf232 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -816,7 +816,9 @@ const struct clk_ops tegra_clk_plle_ops = {
816 .enable = clk_plle_enable, 816 .enable = clk_plle_enable,
817}; 817};
818 818
819#if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC) 819#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
820 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
821 defined(CONFIG_ARCH_TEGRA_132_SOC)
820 822
821static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, 823static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
822 unsigned long parent_rate) 824 unsigned long parent_rate)
@@ -1505,7 +1507,9 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1505 return clk; 1507 return clk;
1506} 1508}
1507 1509
1508#if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC) 1510#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1511 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1512 defined(CONFIG_ARCH_TEGRA_132_SOC)
1509static const struct clk_ops tegra_clk_pllxc_ops = { 1513static const struct clk_ops tegra_clk_pllxc_ops = {
1510 .is_enabled = clk_pll_is_enabled, 1514 .is_enabled = clk_pll_is_enabled,
1511 .enable = clk_pll_iddq_enable, 1515 .enable = clk_pll_iddq_enable,
@@ -1565,7 +1569,7 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1565 parent = __clk_lookup(parent_name); 1569 parent = __clk_lookup(parent_name);
1566 if (!parent) { 1570 if (!parent) {
1567 WARN(1, "parent clk %s of %s must be registered first\n", 1571 WARN(1, "parent clk %s of %s must be registered first\n",
1568 name, parent_name); 1572 parent_name, name);
1569 return ERR_PTR(-EINVAL); 1573 return ERR_PTR(-EINVAL);
1570 } 1574 }
1571 1575
@@ -1665,7 +1669,7 @@ struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
1665 parent = __clk_lookup(parent_name); 1669 parent = __clk_lookup(parent_name);
1666 if (!parent) { 1670 if (!parent) {
1667 WARN(1, "parent clk %s of %s must be registered first\n", 1671 WARN(1, "parent clk %s of %s must be registered first\n",
1668 name, parent_name); 1672 parent_name, name);
1669 return ERR_PTR(-EINVAL); 1673 return ERR_PTR(-EINVAL);
1670 } 1674 }
1671 1675
@@ -1706,7 +1710,7 @@ struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
1706 parent = __clk_lookup(parent_name); 1710 parent = __clk_lookup(parent_name);
1707 if (!parent) { 1711 if (!parent) {
1708 WARN(1, "parent clk %s of %s must be registered first\n", 1712 WARN(1, "parent clk %s of %s must be registered first\n",
1709 name, parent_name); 1713 parent_name, name);
1710 return ERR_PTR(-EINVAL); 1714 return ERR_PTR(-EINVAL);
1711 } 1715 }
1712 1716
@@ -1802,7 +1806,7 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name,
1802} 1806}
1803#endif 1807#endif
1804 1808
1805#ifdef CONFIG_ARCH_TEGRA_124_SOC 1809#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
1806static const struct clk_ops tegra_clk_pllss_ops = { 1810static const struct clk_ops tegra_clk_pllss_ops = {
1807 .is_enabled = clk_pll_is_enabled, 1811 .is_enabled = clk_pll_is_enabled,
1808 .enable = clk_pll_iddq_enable, 1812 .enable = clk_pll_iddq_enable,
@@ -1830,7 +1834,7 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
1830 parent = __clk_lookup(parent_name); 1834 parent = __clk_lookup(parent_name);
1831 if (!parent) { 1835 if (!parent) {
1832 WARN(1, "parent clk %s of %s must be registered first\n", 1836 WARN(1, "parent clk %s of %s must be registered first\n",
1833 name, parent_name); 1837 parent_name, name);
1834 return ERR_PTR(-EINVAL); 1838 return ERR_PTR(-EINVAL);
1835 } 1839 }
1836 1840
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index 37f32c49674e..cef0727b9eec 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -434,10 +434,10 @@ static struct tegra_periph_init_data periph_clks[] = {
434 MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda), 434 MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda),
435 MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x), 435 MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x),
436 MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir), 436 MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir),
437 MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, 0, tegra_clk_sdmmc1), 437 MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1),
438 MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, 0, tegra_clk_sdmmc2), 438 MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2),
439 MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, 0, tegra_clk_sdmmc3), 439 MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3),
440 MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, 0, tegra_clk_sdmmc4), 440 MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4),
441 MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la), 441 MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la),
442 MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace), 442 MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace),
443 MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr), 443 MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr),
@@ -470,10 +470,10 @@ static struct tegra_periph_init_data periph_clks[] = {
470 MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1), 470 MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1),
471 MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1), 471 MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1),
472 MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2), 472 MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2),
473 MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, 0, tegra_clk_sdmmc1_8), 473 MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_8),
474 MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, 0, tegra_clk_sdmmc2_8), 474 MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_8),
475 MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, 0, tegra_clk_sdmmc3_8), 475 MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_8),
476 MUX8("sdmmc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC4, 15, 0, tegra_clk_sdmmc4_8), 476 MUX8("sdmmc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4_8),
477 MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_8), 477 MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_8),
478 MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_8), 478 MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_8),
479 MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_8), 479 MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_8),
@@ -537,8 +537,6 @@ static struct tegra_periph_init_data gate_clks[] = {
537 GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0), 537 GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0),
538 GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0), 538 GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0),
539 GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0), 539 GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),
540 GATE("dsia", "dsia_mux", 48, 0, tegra_clk_dsia, 0),
541 GATE("dsib", "dsib_mux", 82, 0, tegra_clk_dsib, 0),
542 GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED), 540 GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED),
543 GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0), 541 GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),
544 GATE("ispb", "clk_m", 3, 0, tegra_clk_ispb, 0), 542 GATE("ispb", "clk_m", 3, 0, tegra_clk_ispb, 0),
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 0b03d2cf7264..d0766423a5d6 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -715,7 +715,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
715 [tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true }, 715 [tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true },
716 [tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true }, 716 [tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true },
717 [tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true }, 717 [tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true },
718 [tegra_clk_dsia] = { .dt_id = TEGRA114_CLK_DSIA, .present = true },
719 [tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true }, 718 [tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true },
720 [tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true }, 719 [tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true },
721 [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true }, 720 [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },
@@ -739,7 +738,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
739 [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true }, 738 [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true },
740 [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true }, 739 [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true },
741 [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true }, 740 [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true },
742 [tegra_clk_dsib] = { .dt_id = TEGRA114_CLK_DSIB, .present = true },
743 [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true }, 741 [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true },
744 [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true }, 742 [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true },
745 [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true }, 743 [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true },
@@ -1224,6 +1222,14 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1224 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); 1222 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
1225 clks[TEGRA114_CLK_DSIB_MUX] = clk; 1223 clks[TEGRA114_CLK_DSIB_MUX] = clk;
1226 1224
1225 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
1226 0, 48, periph_clk_enb_refcnt);
1227 clks[TEGRA114_CLK_DSIA] = clk;
1228
1229 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
1230 0, 82, periph_clk_enb_refcnt);
1231 clks[TEGRA114_CLK_DSIB] = clk;
1232
1227 /* emc mux */ 1233 /* emc mux */
1228 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 1234 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1229 ARRAY_SIZE(mux_pllmcp_clkm), 1235 ARRAY_SIZE(mux_pllmcp_clkm),
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index f5f9baca7bb6..9a893f2fe8e9 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -28,6 +28,14 @@
28#include "clk.h" 28#include "clk.h"
29#include "clk-id.h" 29#include "clk-id.h"
30 30
31/*
32 * TEGRA124_CAR_BANK_COUNT: the number of peripheral clock register
33 * banks present in the Tegra124/132 CAR IP block. The banks are
34 * identified by single letters, e.g.: L, H, U, V, W, X. See
35 * periph_regs[] in drivers/clk/tegra/clk.c
36 */
37#define TEGRA124_CAR_BANK_COUNT 6
38
31#define CLK_SOURCE_CSITE 0x1d4 39#define CLK_SOURCE_CSITE 0x1d4
32#define CLK_SOURCE_EMC 0x19c 40#define CLK_SOURCE_EMC 0x19c
33 41
@@ -128,7 +136,6 @@ static unsigned long osc_freq;
128static unsigned long pll_ref_freq; 136static unsigned long pll_ref_freq;
129 137
130static DEFINE_SPINLOCK(pll_d_lock); 138static DEFINE_SPINLOCK(pll_d_lock);
131static DEFINE_SPINLOCK(pll_d2_lock);
132static DEFINE_SPINLOCK(pll_e_lock); 139static DEFINE_SPINLOCK(pll_e_lock);
133static DEFINE_SPINLOCK(pll_re_lock); 140static DEFINE_SPINLOCK(pll_re_lock);
134static DEFINE_SPINLOCK(pll_u_lock); 141static DEFINE_SPINLOCK(pll_u_lock);
@@ -145,11 +152,6 @@ static unsigned long tegra124_input_freq[] = {
145 [12] = 260000000, 152 [12] = 260000000,
146}; 153};
147 154
148static const char *mux_plld_out0_plld2_out0[] = {
149 "pll_d_out0", "pll_d2_out0",
150};
151#define mux_plld_out0_plld2_out0_idx NULL
152
153static const char *mux_pllmcp_clkm[] = { 155static const char *mux_pllmcp_clkm[] = {
154 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3", 156 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3",
155}; 157};
@@ -783,7 +785,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
783 [tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true }, 785 [tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true },
784 [tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true }, 786 [tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true },
785 [tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true }, 787 [tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true },
786 [tegra_clk_dsia] = { .dt_id = TEGRA124_CLK_DSIA, .present = true },
787 [tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true }, 788 [tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true },
788 [tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true }, 789 [tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true },
789 [tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true }, 790 [tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true },
@@ -809,7 +810,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
809 [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true }, 810 [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true },
810 [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true }, 811 [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true },
811 [tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true }, 812 [tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true },
812 [tegra_clk_dsib] = { .dt_id = TEGRA124_CLK_DSIB, .present = true },
813 [tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true }, 813 [tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true },
814 [tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true }, 814 [tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true },
815 [tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true }, 815 [tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true },
@@ -949,8 +949,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
949 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true }, 949 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
950 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true }, 950 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
951 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true }, 951 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
952 [tegra_clk_dsia_mux] = { .dt_id = TEGRA124_CLK_DSIA_MUX, .present = true },
953 [tegra_clk_dsib_mux] = { .dt_id = TEGRA124_CLK_DSIB_MUX, .present = true },
954}; 952};
955 953
956static struct tegra_devclk devclks[] __initdata = { 954static struct tegra_devclk devclks[] __initdata = {
@@ -1112,17 +1110,17 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base,
1112 1, 2); 1110 1, 2);
1113 clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk; 1111 clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;
1114 1112
1115 /* dsia mux */ 1113 clk = clk_register_gate(NULL, "plld_dsi", "plld_out0", 0,
1116 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, 1114 clk_base + PLLD_MISC, 30, 0, &pll_d_lock);
1117 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0, 1115 clks[TEGRA124_CLK_PLLD_DSI] = clk;
1118 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); 1116
1119 clks[TEGRA124_CLK_DSIA_MUX] = clk; 1117 clk = tegra_clk_register_periph_gate("dsia", "plld_dsi", 0, clk_base,
1118 0, 48, periph_clk_enb_refcnt);
1119 clks[TEGRA124_CLK_DSIA] = clk;
1120 1120
1121 /* dsib mux */ 1121 clk = tegra_clk_register_periph_gate("dsib", "plld_dsi", 0, clk_base,
1122 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, 1122 0, 82, periph_clk_enb_refcnt);
1123 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0, 1123 clks[TEGRA124_CLK_DSIB] = clk;
1124 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
1125 clks[TEGRA124_CLK_DSIB_MUX] = clk;
1126 1124
1127 /* emc mux */ 1125 /* emc mux */
1128 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 1126 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
@@ -1351,7 +1349,7 @@ static const struct of_device_id pmc_match[] __initconst = {
1351 {}, 1349 {},
1352}; 1350};
1353 1351
1354static struct tegra_clk_init_table init_table[] __initdata = { 1352static struct tegra_clk_init_table common_init_table[] __initdata = {
1355 {TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0}, 1353 {TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0},
1356 {TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0}, 1354 {TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0},
1357 {TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0}, 1355 {TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0},
@@ -1368,6 +1366,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
1368 {TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0}, 1366 {TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
1369 {TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0}, 1367 {TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0},
1370 {TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1}, 1368 {TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1},
1369 {TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0},
1370 {TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0},
1371 {TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1}, 1371 {TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1},
1372 {TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1}, 1372 {TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1},
1373 {TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1}, 1373 {TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1},
@@ -1385,27 +1385,73 @@ static struct tegra_clk_init_table init_table[] __initdata = {
1385 {TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0}, 1385 {TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0},
1386 {TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0}, 1386 {TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0},
1387 {TEGRA124_CLK_EMC, TEGRA124_CLK_CLK_MAX, 0, 1}, 1387 {TEGRA124_CLK_EMC, TEGRA124_CLK_CLK_MAX, 0, 1},
1388 {TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1},
1389 {TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1}, 1388 {TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1},
1390 {TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1}, 1389 {TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1},
1391 {TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0}, 1390 {TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0},
1391 /* This MUST be the last entry. */
1392 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1393};
1394
1395static struct tegra_clk_init_table tegra124_init_table[] __initdata = {
1392 {TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0}, 1396 {TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0},
1397 {TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1},
1398 /* This MUST be the last entry. */
1399 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1400};
1401
1402/* Tegra132 requires the SOC_THERM clock to remain active */
1403static struct tegra_clk_init_table tegra132_init_table[] __initdata = {
1404 {TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 1},
1393 /* This MUST be the last entry. */ 1405 /* This MUST be the last entry. */
1394 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0}, 1406 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1395}; 1407};
1396 1408
1409/**
1410 * tegra124_clock_apply_init_table - initialize clocks on Tegra124 SoCs
1411 *
1412 * Program an initial clock rate and enable or disable clocks needed
1413 * by the rest of the kernel, for Tegra124 SoCs. It is intended to be
1414 * called by assigning a pointer to it to tegra_clk_apply_init_table -
1415 * this will be called as an arch_initcall. No return value.
1416 */
1397static void __init tegra124_clock_apply_init_table(void) 1417static void __init tegra124_clock_apply_init_table(void)
1398{ 1418{
1399 tegra_init_from_table(init_table, clks, TEGRA124_CLK_CLK_MAX); 1419 tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);
1420 tegra_init_from_table(tegra124_init_table, clks, TEGRA124_CLK_CLK_MAX);
1400} 1421}
1401 1422
1402static void __init tegra124_clock_init(struct device_node *np) 1423/**
1424 * tegra132_clock_apply_init_table - initialize clocks on Tegra132 SoCs
1425 *
1426 * Program an initial clock rate and enable or disable clocks needed
1427 * by the rest of the kernel, for Tegra132 SoCs. It is intended to be
1428 * called by assigning a pointer to it to tegra_clk_apply_init_table -
1429 * this will be called as an arch_initcall. No return value.
1430 */
1431static void __init tegra132_clock_apply_init_table(void)
1432{
1433 tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);
1434 tegra_init_from_table(tegra132_init_table, clks, TEGRA124_CLK_CLK_MAX);
1435}
1436
1437/**
1438 * tegra124_132_clock_init_pre - clock initialization preamble for T124/T132
1439 * @np: struct device_node * of the DT node for the SoC CAR IP block
1440 *
1441 * Register most of the clocks controlled by the CAR IP block, along
1442 * with a few clocks controlled by the PMC IP block. Everything in
1443 * this function should be common to Tegra124 and Tegra132. XXX The
1444 * PMC clock initialization should probably be moved to PMC-specific
1445 * driver code. No return value.
1446 */
1447static void __init tegra124_132_clock_init_pre(struct device_node *np)
1403{ 1448{
1404 struct device_node *node; 1449 struct device_node *node;
1450 u32 plld_base;
1405 1451
1406 clk_base = of_iomap(np, 0); 1452 clk_base = of_iomap(np, 0);
1407 if (!clk_base) { 1453 if (!clk_base) {
1408 pr_err("ioremap tegra124 CAR failed\n"); 1454 pr_err("ioremap tegra124/tegra132 CAR failed\n");
1409 return; 1455 return;
1410 } 1456 }
1411 1457
@@ -1423,7 +1469,8 @@ static void __init tegra124_clock_init(struct device_node *np)
1423 return; 1469 return;
1424 } 1470 }
1425 1471
1426 clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX, 6); 1472 clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX,
1473 TEGRA124_CAR_BANK_COUNT);
1427 if (!clks) 1474 if (!clks)
1428 return; 1475 return;
1429 1476
@@ -1437,13 +1484,76 @@ static void __init tegra124_clock_init(struct device_node *np)
1437 tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, &pll_a_params); 1484 tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, &pll_a_params);
1438 tegra_pmc_clk_init(pmc_base, tegra124_clks); 1485 tegra_pmc_clk_init(pmc_base, tegra124_clks);
1439 1486
1487 /* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
1488 plld_base = clk_readl(clk_base + PLLD_BASE);
1489 plld_base &= ~BIT(25);
1490 clk_writel(plld_base, clk_base + PLLD_BASE);
1491}
1492
1493/**
1494 * tegra124_132_clock_init_post - clock initialization postamble for T124/T132
1495 * @np: struct device_node * of the DT node for the SoC CAR IP block
1496 *
1497 * Register most of the along with a few clocks controlled by the PMC
1498 * IP block. Everything in this function should be common to Tegra124
1499 * and Tegra132. This function must be called after
1500 * tegra124_132_clock_init_pre(), otherwise clk_base and pmc_base will
1501 * not be set. No return value.
1502 */
1503static void __init tegra124_132_clock_init_post(struct device_node *np)
1504{
1440 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks, 1505 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks,
1441 &pll_x_params); 1506 &pll_x_params);
1442 tegra_add_of_provider(np); 1507 tegra_add_of_provider(np);
1443 tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 1508 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1444 1509
1510 tegra_cpu_car_ops = &tegra124_cpu_car_ops;
1511}
1512
1513/**
1514 * tegra124_clock_init - Tegra124-specific clock initialization
1515 * @np: struct device_node * of the DT node for the SoC CAR IP block
1516 *
1517 * Register most SoC clocks for the Tegra124 system-on-chip. Most of
1518 * this code is shared between the Tegra124 and Tegra132 SoCs,
1519 * although some of the initial clock settings and CPU clocks differ.
1520 * Intended to be called by the OF init code when a DT node with the
1521 * "nvidia,tegra124-car" string is encountered, and declared with
1522 * CLK_OF_DECLARE. No return value.
1523 */
1524static void __init tegra124_clock_init(struct device_node *np)
1525{
1526 tegra124_132_clock_init_pre(np);
1445 tegra_clk_apply_init_table = tegra124_clock_apply_init_table; 1527 tegra_clk_apply_init_table = tegra124_clock_apply_init_table;
1528 tegra124_132_clock_init_post(np);
1529}
1446 1530
1447 tegra_cpu_car_ops = &tegra124_cpu_car_ops; 1531/**
1532 * tegra132_clock_init - Tegra132-specific clock initialization
1533 * @np: struct device_node * of the DT node for the SoC CAR IP block
1534 *
1535 * Register most SoC clocks for the Tegra132 system-on-chip. Most of
1536 * this code is shared between the Tegra124 and Tegra132 SoCs,
1537 * although some of the initial clock settings and CPU clocks differ.
1538 * Intended to be called by the OF init code when a DT node with the
1539 * "nvidia,tegra132-car" string is encountered, and declared with
1540 * CLK_OF_DECLARE. No return value.
1541 */
1542static void __init tegra132_clock_init(struct device_node *np)
1543{
1544 tegra124_132_clock_init_pre(np);
1545
1546 /*
1547 * On Tegra132, these clocks are controlled by the
1548 * CLUSTER_clocks IP block, located in the CPU complex
1549 */
1550 tegra124_clks[tegra_clk_cclk_g].present = false;
1551 tegra124_clks[tegra_clk_cclk_lp].present = false;
1552 tegra124_clks[tegra_clk_pll_x].present = false;
1553 tegra124_clks[tegra_clk_pll_x_out0].present = false;
1554
1555 tegra_clk_apply_init_table = tegra132_clock_apply_init_table;
1556 tegra124_132_clock_init_post(np);
1448} 1557}
1449CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init); 1558CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init);
1559CLK_OF_DECLARE(tegra132, "nvidia,tegra132-car", tegra132_clock_init);
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index 97dc8595c3cd..9ddb7547cb43 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -302,10 +302,13 @@ struct clk ** __init tegra_lookup_dt_id(int clk_id,
302 302
303tegra_clk_apply_init_table_func tegra_clk_apply_init_table; 303tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
304 304
305void __init tegra_clocks_apply_init_table(void) 305static int __init tegra_clocks_apply_init_table(void)
306{ 306{
307 if (!tegra_clk_apply_init_table) 307 if (!tegra_clk_apply_init_table)
308 return; 308 return 0;
309 309
310 tegra_clk_apply_init_table(); 310 tegra_clk_apply_init_table();
311
312 return 0;
311} 313}
314arch_initcall(tegra_clocks_apply_init_table);