diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2013-06-19 19:51:18 -0400 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2013-06-19 19:51:18 -0400 |
| commit | c3b693d1d63444afe4fbf809d8a311b63741e503 (patch) | |
| tree | 5c0c264203967f1524ac28645f0b5cea57b624bc /drivers/clk | |
| parent | 596fd95ea606548adaa8310a7c05a6dcfec46f16 (diff) | |
| parent | 7fca1f20c0f3e9d7a3b23ee1fc9e832f520f3f1a (diff) | |
Merge tag 'u300-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/soc
From Linus Walleij:
Device Tree and Multiplatform support for U300:
- Add devicetree support to timer, pinctrl (probe), I2C block,
watchdog, DMA controller and clocks.
- Piecewise add a device tree containing all peripherals.
- Delete the ATAG boot path.
- Delete redundant platform data and board files.
- Convert to multiplatform.
* tag 'u300-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: (40 commits)
ARM: u300: switch to using syscon regmap for board
ARM: u300: Update MMC configs for u300 defconfig
spi: pl022: use DMA by default when probing from DT
pinctrl: get rid of all platform data for coh901
ARM: u300: convert MMC/SD clock to device tree
ARM: u300: move the gated system controller clocks to DT
i2c: stu300: do not request a specific clock name
clk: move the U300 fixed and fixed-factor to DT
ARM: u300: remove register definition file
ARM: u300: add syscon node
ARM: u300 use module_spi_driver to register driver
ARM: u300: delete remnant machine headers
ARM: u300: convert to multiplatform
ARM: u300: localize <mach/u300-regs.h>
ARM: u300: delete <mach/irqs.h>
ARM: u300: delete <mach/hardware.h>
ARM: u300: push down syscon registers
ARM: u300: remove deps from debug macro
ARM: u300: move debugmacro to debug includes
ARM: u300: delete all static board data
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/clk-u300.c | 718 |
1 files changed, 583 insertions, 135 deletions
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c index a15f7928fb11..8774e058cb6c 100644 --- a/drivers/clk/clk-u300.c +++ b/drivers/clk/clk-u300.c | |||
| @@ -11,7 +11,349 @@ | |||
| 11 | #include <linux/io.h> | 11 | #include <linux/io.h> |
| 12 | #include <linux/clk-provider.h> | 12 | #include <linux/clk-provider.h> |
| 13 | #include <linux/spinlock.h> | 13 | #include <linux/spinlock.h> |
| 14 | #include <mach/syscon.h> | 14 | #include <linux/of.h> |
| 15 | |||
| 16 | /* APP side SYSCON registers */ | ||
| 17 | /* CLK Control Register 16bit (R/W) */ | ||
| 18 | #define U300_SYSCON_CCR (0x0000) | ||
| 19 | #define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040) | ||
| 20 | #define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020) | ||
| 21 | #define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008) | ||
| 22 | #define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007) | ||
| 23 | #define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04) | ||
| 24 | #define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03) | ||
| 25 | #define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02) | ||
| 26 | #define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01) | ||
| 27 | #define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00) | ||
| 28 | /* CLK Status Register 16bit (R/W) */ | ||
| 29 | #define U300_SYSCON_CSR (0x0004) | ||
| 30 | #define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002) | ||
| 31 | #define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001) | ||
| 32 | /* Reset lines for SLOW devices 16bit (R/W) */ | ||
| 33 | #define U300_SYSCON_RSR (0x0014) | ||
| 34 | #define U300_SYSCON_RSR_PPM_RESET_EN (0x0200) | ||
| 35 | #define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100) | ||
| 36 | #define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080) | ||
| 37 | #define U300_SYSCON_RSR_RTC_RESET_EN (0x0040) | ||
| 38 | #define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020) | ||
| 39 | #define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010) | ||
| 40 | #define U300_SYSCON_RSR_EH_RESET_EN (0x0008) | ||
| 41 | #define U300_SYSCON_RSR_BTR_RESET_EN (0x0004) | ||
| 42 | #define U300_SYSCON_RSR_UART_RESET_EN (0x0002) | ||
| 43 | #define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001) | ||
| 44 | /* Reset lines for FAST devices 16bit (R/W) */ | ||
| 45 | #define U300_SYSCON_RFR (0x0018) | ||
| 46 | #define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080) | ||
| 47 | #define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040) | ||
| 48 | #define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020) | ||
| 49 | #define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010) | ||
| 50 | #define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008) | ||
| 51 | #define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004) | ||
| 52 | #define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002) | ||
| 53 | #define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001) | ||
| 54 | /* Reset lines for the rest of the peripherals 16bit (R/W) */ | ||
| 55 | #define U300_SYSCON_RRR (0x001c) | ||
| 56 | #define U300_SYSCON_RRR_CDS_RESET_EN (0x4000) | ||
| 57 | #define U300_SYSCON_RRR_ISP_RESET_EN (0x2000) | ||
| 58 | #define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000) | ||
| 59 | #define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800) | ||
| 60 | #define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100) | ||
| 61 | #define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080) | ||
| 62 | #define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040) | ||
| 63 | #define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020) | ||
| 64 | #define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010) | ||
| 65 | #define U300_SYSCON_RRR_CPU_RESET_EN (0x0008) | ||
| 66 | #define U300_SYSCON_RRR_APEX_RESET_EN (0x0004) | ||
| 67 | #define U300_SYSCON_RRR_AHB_RESET_EN (0x0002) | ||
| 68 | #define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001) | ||
| 69 | /* Clock enable for SLOW peripherals 16bit (R/W) */ | ||
| 70 | #define U300_SYSCON_CESR (0x0020) | ||
| 71 | #define U300_SYSCON_CESR_PPM_CLK_EN (0x0200) | ||
| 72 | #define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100) | ||
| 73 | #define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080) | ||
| 74 | #define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040) | ||
| 75 | #define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010) | ||
| 76 | #define U300_SYSCON_CESR_EH_CLK_EN (0x0008) | ||
| 77 | #define U300_SYSCON_CESR_BTR_CLK_EN (0x0004) | ||
| 78 | #define U300_SYSCON_CESR_UART_CLK_EN (0x0002) | ||
| 79 | #define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001) | ||
| 80 | /* Clock enable for FAST peripherals 16bit (R/W) */ | ||
| 81 | #define U300_SYSCON_CEFR (0x0024) | ||
| 82 | #define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200) | ||
| 83 | #define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100) | ||
| 84 | #define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080) | ||
| 85 | #define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040) | ||
| 86 | #define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020) | ||
| 87 | #define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010) | ||
| 88 | #define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008) | ||
| 89 | #define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004) | ||
| 90 | #define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002) | ||
| 91 | #define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001) | ||
| 92 | /* Clock enable for the rest of the peripherals 16bit (R/W) */ | ||
| 93 | #define U300_SYSCON_CERR (0x0028) | ||
| 94 | #define U300_SYSCON_CERR_CDS_CLK_EN (0x2000) | ||
| 95 | #define U300_SYSCON_CERR_ISP_CLK_EN (0x1000) | ||
| 96 | #define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800) | ||
| 97 | #define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400) | ||
| 98 | #define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200) | ||
| 99 | #define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100) | ||
| 100 | #define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080) | ||
| 101 | #define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040) | ||
| 102 | #define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020) | ||
| 103 | #define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010) | ||
| 104 | #define U300_SYSCON_CERR_CPU_CLK_EN (0x0008) | ||
| 105 | #define U300_SYSCON_CERR_APEX_CLK_EN (0x0004) | ||
| 106 | #define U300_SYSCON_CERR_AHB_CLK_EN (0x0002) | ||
| 107 | #define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001) | ||
| 108 | /* Single block clock enable 16bit (-/W) */ | ||
| 109 | #define U300_SYSCON_SBCER (0x002c) | ||
| 110 | #define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009) | ||
| 111 | #define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008) | ||
| 112 | #define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007) | ||
| 113 | #define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006) | ||
| 114 | #define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004) | ||
| 115 | #define U300_SYSCON_SBCER_EH_CLK_EN (0x0003) | ||
| 116 | #define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002) | ||
| 117 | #define U300_SYSCON_SBCER_UART_CLK_EN (0x0001) | ||
| 118 | #define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000) | ||
| 119 | #define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019) | ||
| 120 | #define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018) | ||
| 121 | #define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017) | ||
| 122 | #define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016) | ||
| 123 | #define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015) | ||
| 124 | #define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014) | ||
| 125 | #define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013) | ||
| 126 | #define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012) | ||
| 127 | #define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011) | ||
| 128 | #define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010) | ||
| 129 | #define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D) | ||
| 130 | #define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C) | ||
| 131 | #define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B) | ||
| 132 | #define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A) | ||
| 133 | #define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029) | ||
| 134 | #define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028) | ||
| 135 | #define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027) | ||
| 136 | #define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026) | ||
| 137 | #define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025) | ||
| 138 | #define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024) | ||
| 139 | #define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023) | ||
| 140 | #define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022) | ||
| 141 | #define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021) | ||
| 142 | #define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020) | ||
| 143 | /* Single block clock disable 16bit (-/W) */ | ||
| 144 | #define U300_SYSCON_SBCDR (0x0030) | ||
| 145 | /* Same values as above for SBCER */ | ||
| 146 | /* Clock force SLOW peripherals 16bit (R/W) */ | ||
| 147 | #define U300_SYSCON_CFSR (0x003c) | ||
| 148 | #define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200) | ||
| 149 | #define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100) | ||
| 150 | #define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080) | ||
| 151 | #define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020) | ||
| 152 | #define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010) | ||
| 153 | #define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008) | ||
| 154 | #define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004) | ||
| 155 | #define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002) | ||
| 156 | #define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001) | ||
| 157 | /* Clock force FAST peripherals 16bit (R/W) */ | ||
| 158 | #define U300_SYSCON_CFFR (0x40) | ||
| 159 | /* Values not defined. Define if you want to use them. */ | ||
| 160 | /* Clock force the rest of the peripherals 16bit (R/W) */ | ||
| 161 | #define U300_SYSCON_CFRR (0x44) | ||
| 162 | #define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000) | ||
| 163 | #define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000) | ||
| 164 | #define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800) | ||
| 165 | #define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400) | ||
| 166 | #define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200) | ||
| 167 | #define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100) | ||
| 168 | #define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080) | ||
| 169 | #define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040) | ||
| 170 | #define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020) | ||
| 171 | #define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010) | ||
| 172 | #define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008) | ||
| 173 | #define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004) | ||
| 174 | #define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002) | ||
| 175 | #define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001) | ||
| 176 | /* PLL208 Frequency Control 16bit (R/W) */ | ||
| 177 | #define U300_SYSCON_PFCR (0x48) | ||
| 178 | #define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F) | ||
| 179 | /* Power Management Control 16bit (R/W) */ | ||
| 180 | #define U300_SYSCON_PMCR (0x50) | ||
| 181 | #define U300_SYSCON_PMCR_DCON_ENABLE (0x0002) | ||
| 182 | #define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001) | ||
| 183 | /* Reset Out 16bit (R/W) */ | ||
| 184 | #define U300_SYSCON_RCR (0x6c) | ||
| 185 | #define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001) | ||
| 186 | /* EMIF Slew Rate Control 16bit (R/W) */ | ||
| 187 | #define U300_SYSCON_SRCLR (0x70) | ||
| 188 | #define U300_SYSCON_SRCLR_MASK (0x03FF) | ||
| 189 | #define U300_SYSCON_SRCLR_VALUE (0x03FF) | ||
| 190 | #define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200) | ||
| 191 | #define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100) | ||
| 192 | #define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080) | ||
| 193 | #define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040) | ||
| 194 | #define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020) | ||
| 195 | #define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010) | ||
| 196 | #define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008) | ||
| 197 | #define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004) | ||
| 198 | #define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002) | ||
| 199 | #define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001) | ||
| 200 | /* EMIF Clock Control Register 16bit (R/W) */ | ||
| 201 | #define U300_SYSCON_ECCR (0x0078) | ||
| 202 | #define U300_SYSCON_ECCR_MASK (0x000F) | ||
| 203 | #define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008) | ||
| 204 | #define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004) | ||
| 205 | #define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002) | ||
| 206 | #define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001) | ||
| 207 | /* MMC/MSPRO frequency divider register 0 16bit (R/W) */ | ||
| 208 | #define U300_SYSCON_MMF0R (0x90) | ||
| 209 | #define U300_SYSCON_MMF0R_MASK (0x00FF) | ||
| 210 | #define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0) | ||
| 211 | #define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F) | ||
| 212 | /* MMC/MSPRO frequency divider register 1 16bit (R/W) */ | ||
| 213 | #define U300_SYSCON_MMF1R (0x94) | ||
| 214 | #define U300_SYSCON_MMF1R_MASK (0x00FF) | ||
| 215 | #define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0) | ||
| 216 | #define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F) | ||
| 217 | /* Clock control for the MMC and MSPRO blocks 16bit (R/W) */ | ||
| 218 | #define U300_SYSCON_MMCR (0x9C) | ||
| 219 | #define U300_SYSCON_MMCR_MASK (0x0003) | ||
| 220 | #define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002) | ||
| 221 | #define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001) | ||
| 222 | /* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */ | ||
| 223 | #define U300_SYSCON_S0CCR (0x120) | ||
| 224 | #define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF) | ||
| 225 | #define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000) | ||
| 226 | #define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR (0x2000) | ||
| 227 | #define U300_SYSCON_S0CCR_CLOCK_INV (0x0200) | ||
| 228 | #define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0) | ||
| 229 | #define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E) | ||
| 230 | #define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001) | ||
| 231 | #define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1) | ||
| 232 | #define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1) | ||
| 233 | #define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1) | ||
| 234 | #define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1) | ||
| 235 | #define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1) | ||
| 236 | #define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1) | ||
| 237 | #define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1) | ||
| 238 | #define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1) | ||
| 239 | #define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1) | ||
| 240 | /* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */ | ||
| 241 | #define U300_SYSCON_S1CCR (0x124) | ||
| 242 | #define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF) | ||
| 243 | #define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000) | ||
| 244 | #define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR (0x2000) | ||
| 245 | #define U300_SYSCON_S1CCR_CLOCK_INV (0x0200) | ||
| 246 | #define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0) | ||
| 247 | #define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E) | ||
| 248 | #define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001) | ||
| 249 | #define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1) | ||
| 250 | #define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1) | ||
| 251 | #define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1) | ||
| 252 | #define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1) | ||
| 253 | #define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1) | ||
| 254 | #define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1) | ||
| 255 | #define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1) | ||
| 256 | #define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1) | ||
| 257 | #define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1) | ||
| 258 | /* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */ | ||
| 259 | #define U300_SYSCON_S2CCR (0x128) | ||
| 260 | #define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF) | ||
| 261 | #define U300_SYSCON_S2CCR_CLK_STEAL (0x8000) | ||
| 262 | #define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000) | ||
| 263 | #define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR (0x2000) | ||
| 264 | #define U300_SYSCON_S2CCR_CLOCK_INV (0x0200) | ||
| 265 | #define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0) | ||
| 266 | #define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E) | ||
| 267 | #define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001) | ||
| 268 | #define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1) | ||
| 269 | #define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1) | ||
| 270 | #define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1) | ||
| 271 | #define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1) | ||
| 272 | #define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1) | ||
| 273 | #define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1) | ||
| 274 | #define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1) | ||
| 275 | #define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1) | ||
| 276 | #define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1) | ||
| 277 | /* SC_PLL_IRQ_CONTROL 16bit (R/W) */ | ||
| 278 | #define U300_SYSCON_PICR (0x0130) | ||
| 279 | #define U300_SYSCON_PICR_MASK (0x00FF) | ||
| 280 | #define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE (0x0080) | ||
| 281 | #define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE (0x0040) | ||
| 282 | #define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE (0x0020) | ||
| 283 | #define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE (0x0010) | ||
| 284 | #define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE (0x0008) | ||
| 285 | #define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE (0x0004) | ||
| 286 | #define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE (0x0002) | ||
| 287 | #define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE (0x0001) | ||
| 288 | /* SC_PLL_IRQ_STATUS 16 bit (R/-) */ | ||
| 289 | #define U300_SYSCON_PISR (0x0134) | ||
| 290 | #define U300_SYSCON_PISR_MASK (0x000F) | ||
| 291 | #define U300_SYSCON_PISR_PLL13_UNLOCK_IND (0x0008) | ||
| 292 | #define U300_SYSCON_PISR_PLL13_LOCK_IND (0x0004) | ||
| 293 | #define U300_SYSCON_PISR_PLL208_UNLOCK_IND (0x0002) | ||
| 294 | #define U300_SYSCON_PISR_PLL208_LOCK_IND (0x0001) | ||
| 295 | /* SC_PLL_IRQ_CLEAR 16 bit (-/W) */ | ||
| 296 | #define U300_SYSCON_PICLR (0x0138) | ||
| 297 | #define U300_SYSCON_PICLR_MASK (0x000F) | ||
| 298 | #define U300_SYSCON_PICLR_RWMASK (0x0000) | ||
| 299 | #define U300_SYSCON_PICLR_PLL13_UNLOCK_SC (0x0008) | ||
| 300 | #define U300_SYSCON_PICLR_PLL13_LOCK_SC (0x0004) | ||
| 301 | #define U300_SYSCON_PICLR_PLL208_UNLOCK_SC (0x0002) | ||
| 302 | #define U300_SYSCON_PICLR_PLL208_LOCK_SC (0x0001) | ||
| 303 | /* Clock activity observability register 0 */ | ||
| 304 | #define U300_SYSCON_C0OAR (0x140) | ||
| 305 | #define U300_SYSCON_C0OAR_MASK (0xFFFF) | ||
| 306 | #define U300_SYSCON_C0OAR_VALUE (0xFFFF) | ||
| 307 | #define U300_SYSCON_C0OAR_BT_H_CLK (0x8000) | ||
| 308 | #define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000) | ||
| 309 | #define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000) | ||
| 310 | #define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000) | ||
| 311 | #define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800) | ||
| 312 | #define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400) | ||
| 313 | #define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200) | ||
| 314 | #define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100) | ||
| 315 | #define U300_SYSCON_C0OAR_APP_52_CLK (0x0080) | ||
| 316 | #define U300_SYSCON_C0OAR_APP_208_CLK (0x0040) | ||
| 317 | #define U300_SYSCON_C0OAR_APP_104_CLK (0x0020) | ||
| 318 | #define U300_SYSCON_C0OAR_APEX_CLK (0x0010) | ||
| 319 | #define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008) | ||
| 320 | #define U300_SYSCON_C0OAR_AHB_CLK (0x0004) | ||
| 321 | #define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002) | ||
| 322 | #define U300_SYSCON_C0OAR_AAIF_CLK (0x0001) | ||
| 323 | /* Clock activity observability register 1 */ | ||
| 324 | #define U300_SYSCON_C1OAR (0x144) | ||
| 325 | #define U300_SYSCON_C1OAR_MASK (0x3FFE) | ||
| 326 | #define U300_SYSCON_C1OAR_VALUE (0x3FFE) | ||
| 327 | #define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000) | ||
| 328 | #define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000) | ||
| 329 | #define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800) | ||
| 330 | #define U300_SYSCON_C1OAR_MMC_CLK (0x0400) | ||
| 331 | #define U300_SYSCON_C1OAR_KP_P_CLK (0x0200) | ||
| 332 | #define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100) | ||
| 333 | #define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080) | ||
| 334 | #define U300_SYSCON_C1OAR_GPIO_CLK (0x0040) | ||
| 335 | #define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020) | ||
| 336 | #define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010) | ||
| 337 | #define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008) | ||
| 338 | #define U300_SYSCON_C1OAR_PPM_CLK (0x0004) | ||
| 339 | #define U300_SYSCON_C1OAR_DMA_CLK (0x0002) | ||
| 340 | /* Clock activity observability register 2 */ | ||
| 341 | #define U300_SYSCON_C2OAR (0x148) | ||
| 342 | #define U300_SYSCON_C2OAR_MASK (0x0FFF) | ||
| 343 | #define U300_SYSCON_C2OAR_VALUE (0x0FFF) | ||
| 344 | #define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800) | ||
| 345 | #define U300_SYSCON_C2OAR_XGAM_CLK (0x0400) | ||
| 346 | #define U300_SYSCON_C2OAR_VC_H_CLK (0x0200) | ||
| 347 | #define U300_SYSCON_C2OAR_VC_CLK (0x0100) | ||
| 348 | #define U300_SYSCON_C2OAR_UA_P_CLK (0x0080) | ||
| 349 | #define U300_SYSCON_C2OAR_TMR1_CLK (0x0040) | ||
| 350 | #define U300_SYSCON_C2OAR_TMR0_CLK (0x0020) | ||
| 351 | #define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010) | ||
| 352 | #define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008) | ||
| 353 | #define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004) | ||
| 354 | #define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002) | ||
| 355 | #define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001) | ||
| 356 | |||
| 15 | 357 | ||
| 16 | /* | 358 | /* |
| 17 | * The clocking hierarchy currently looks like this. | 359 | * The clocking hierarchy currently looks like this. |
| @@ -386,6 +728,213 @@ syscon_clk_register(struct device *dev, const char *name, | |||
| 386 | return clk; | 728 | return clk; |
| 387 | } | 729 | } |
| 388 | 730 | ||
| 731 | #define U300_CLK_TYPE_SLOW 0 | ||
| 732 | #define U300_CLK_TYPE_FAST 1 | ||
| 733 | #define U300_CLK_TYPE_REST 2 | ||
| 734 | |||
| 735 | /** | ||
| 736 | * struct u300_clock - defines the bits and pieces for a certain clock | ||
| 737 | * @type: the clock type, slow fast or rest | ||
| 738 | * @id: the bit in the slow/fast/rest register for this clock | ||
| 739 | * @hw_ctrld: whether the clock is hardware controlled | ||
| 740 | * @clk_val: a value to poke in the one-write enable/disable registers | ||
| 741 | */ | ||
| 742 | struct u300_clock { | ||
| 743 | u8 type; | ||
| 744 | u8 id; | ||
| 745 | bool hw_ctrld; | ||
| 746 | u16 clk_val; | ||
| 747 | }; | ||
| 748 | |||
| 749 | struct u300_clock const __initconst u300_clk_lookup[] = { | ||
| 750 | { | ||
| 751 | .type = U300_CLK_TYPE_REST, | ||
| 752 | .id = 3, | ||
| 753 | .hw_ctrld = true, | ||
| 754 | .clk_val = U300_SYSCON_SBCER_CPU_CLK_EN, | ||
| 755 | }, | ||
| 756 | { | ||
| 757 | .type = U300_CLK_TYPE_REST, | ||
| 758 | .id = 4, | ||
| 759 | .hw_ctrld = true, | ||
| 760 | .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN, | ||
| 761 | }, | ||
| 762 | { | ||
| 763 | .type = U300_CLK_TYPE_REST, | ||
| 764 | .id = 5, | ||
| 765 | .hw_ctrld = false, | ||
| 766 | .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN, | ||
| 767 | }, | ||
| 768 | { | ||
| 769 | .type = U300_CLK_TYPE_REST, | ||
| 770 | .id = 6, | ||
| 771 | .hw_ctrld = false, | ||
| 772 | .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN, | ||
| 773 | }, | ||
| 774 | { | ||
| 775 | .type = U300_CLK_TYPE_REST, | ||
| 776 | .id = 8, | ||
| 777 | .hw_ctrld = true, | ||
| 778 | .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN, | ||
| 779 | }, | ||
| 780 | { | ||
| 781 | .type = U300_CLK_TYPE_REST, | ||
| 782 | .id = 9, | ||
| 783 | .hw_ctrld = false, | ||
| 784 | .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN, | ||
| 785 | }, | ||
| 786 | { | ||
| 787 | .type = U300_CLK_TYPE_REST, | ||
| 788 | .id = 10, | ||
| 789 | .hw_ctrld = true, | ||
| 790 | .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN, | ||
| 791 | }, | ||
| 792 | { | ||
| 793 | .type = U300_CLK_TYPE_REST, | ||
| 794 | .id = 12, | ||
| 795 | .hw_ctrld = false, | ||
| 796 | /* INTCON: cannot be enabled, just taken out of reset */ | ||
| 797 | .clk_val = 0xFFFFU, | ||
| 798 | }, | ||
| 799 | { | ||
| 800 | .type = U300_CLK_TYPE_FAST, | ||
| 801 | .id = 0, | ||
| 802 | .hw_ctrld = true, | ||
| 803 | .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN, | ||
| 804 | }, | ||
| 805 | { | ||
| 806 | .type = U300_CLK_TYPE_FAST, | ||
| 807 | .id = 1, | ||
| 808 | .hw_ctrld = false, | ||
| 809 | .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN, | ||
| 810 | }, | ||
| 811 | { | ||
| 812 | .type = U300_CLK_TYPE_FAST, | ||
| 813 | .id = 2, | ||
| 814 | .hw_ctrld = false, | ||
| 815 | .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN, | ||
| 816 | }, | ||
| 817 | { | ||
| 818 | .type = U300_CLK_TYPE_FAST, | ||
| 819 | .id = 5, | ||
| 820 | .hw_ctrld = false, | ||
| 821 | .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN, | ||
| 822 | }, | ||
| 823 | { | ||
| 824 | .type = U300_CLK_TYPE_FAST, | ||
| 825 | .id = 6, | ||
| 826 | .hw_ctrld = false, | ||
| 827 | .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN, | ||
| 828 | }, | ||
| 829 | { | ||
| 830 | .type = U300_CLK_TYPE_SLOW, | ||
| 831 | .id = 0, | ||
| 832 | .hw_ctrld = true, | ||
| 833 | .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN, | ||
| 834 | }, | ||
| 835 | { | ||
| 836 | .type = U300_CLK_TYPE_SLOW, | ||
| 837 | .id = 1, | ||
| 838 | .hw_ctrld = false, | ||
| 839 | .clk_val = U300_SYSCON_SBCER_UART_CLK_EN, | ||
| 840 | }, | ||
| 841 | { | ||
| 842 | .type = U300_CLK_TYPE_SLOW, | ||
| 843 | .id = 4, | ||
| 844 | .hw_ctrld = false, | ||
| 845 | .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN, | ||
| 846 | }, | ||
| 847 | { | ||
| 848 | .type = U300_CLK_TYPE_SLOW, | ||
| 849 | .id = 6, | ||
| 850 | .hw_ctrld = true, | ||
| 851 | /* No clock enable register bit */ | ||
| 852 | .clk_val = 0xFFFFU, | ||
| 853 | }, | ||
| 854 | { | ||
| 855 | .type = U300_CLK_TYPE_SLOW, | ||
| 856 | .id = 7, | ||
| 857 | .hw_ctrld = false, | ||
| 858 | .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN, | ||
| 859 | }, | ||
| 860 | { | ||
| 861 | .type = U300_CLK_TYPE_SLOW, | ||
| 862 | .id = 8, | ||
| 863 | .hw_ctrld = false, | ||
| 864 | .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN, | ||
| 865 | }, | ||
| 866 | }; | ||
| 867 | |||
| 868 | static void __init of_u300_syscon_clk_init(struct device_node *np) | ||
| 869 | { | ||
| 870 | struct clk *clk = ERR_PTR(-EINVAL); | ||
| 871 | const char *clk_name = np->name; | ||
| 872 | const char *parent_name; | ||
| 873 | void __iomem *res_reg; | ||
| 874 | void __iomem *en_reg; | ||
| 875 | u32 clk_type; | ||
| 876 | u32 clk_id; | ||
| 877 | int i; | ||
| 878 | |||
| 879 | if (of_property_read_u32(np, "clock-type", &clk_type)) { | ||
| 880 | pr_err("%s: syscon clock \"%s\" missing clock-type property\n", | ||
| 881 | __func__, clk_name); | ||
| 882 | return; | ||
| 883 | } | ||
| 884 | if (of_property_read_u32(np, "clock-id", &clk_id)) { | ||
| 885 | pr_err("%s: syscon clock \"%s\" missing clock-id property\n", | ||
| 886 | __func__, clk_name); | ||
| 887 | return; | ||
| 888 | } | ||
| 889 | parent_name = of_clk_get_parent_name(np, 0); | ||
| 890 | |||
| 891 | switch (clk_type) { | ||
| 892 | case U300_CLK_TYPE_SLOW: | ||
| 893 | res_reg = syscon_vbase + U300_SYSCON_RSR; | ||
| 894 | en_reg = syscon_vbase + U300_SYSCON_CESR; | ||
| 895 | break; | ||
| 896 | case U300_CLK_TYPE_FAST: | ||
| 897 | res_reg = syscon_vbase + U300_SYSCON_RFR; | ||
| 898 | en_reg = syscon_vbase + U300_SYSCON_CEFR; | ||
| 899 | break; | ||
| 900 | case U300_CLK_TYPE_REST: | ||
| 901 | res_reg = syscon_vbase + U300_SYSCON_RRR; | ||
| 902 | en_reg = syscon_vbase + U300_SYSCON_CERR; | ||
| 903 | break; | ||
| 904 | default: | ||
| 905 | pr_err("unknown clock type %x specified\n", clk_type); | ||
| 906 | return; | ||
| 907 | } | ||
| 908 | |||
| 909 | for (i = 0; i < ARRAY_SIZE(u300_clk_lookup); i++) { | ||
| 910 | const struct u300_clock *u3clk = &u300_clk_lookup[i]; | ||
| 911 | |||
| 912 | if (u3clk->type == clk_type && u3clk->id == clk_id) | ||
| 913 | clk = syscon_clk_register(NULL, | ||
| 914 | clk_name, parent_name, | ||
| 915 | 0, u3clk->hw_ctrld, | ||
| 916 | res_reg, u3clk->id, | ||
| 917 | en_reg, u3clk->id, | ||
| 918 | u3clk->clk_val); | ||
| 919 | } | ||
| 920 | |||
| 921 | if (!IS_ERR(clk)) { | ||
| 922 | of_clk_add_provider(np, of_clk_src_simple_get, clk); | ||
| 923 | |||
| 924 | /* | ||
| 925 | * Some few system clocks - device tree does not | ||
| 926 | * represent clocks without a corresponding device node. | ||
| 927 | * for now we add these three clocks here. | ||
| 928 | */ | ||
| 929 | if (clk_type == U300_CLK_TYPE_REST && clk_id == 5) | ||
| 930 | clk_register_clkdev(clk, NULL, "pl172"); | ||
| 931 | if (clk_type == U300_CLK_TYPE_REST && clk_id == 9) | ||
| 932 | clk_register_clkdev(clk, NULL, "semi"); | ||
| 933 | if (clk_type == U300_CLK_TYPE_REST && clk_id == 12) | ||
| 934 | clk_register_clkdev(clk, NULL, "intcon"); | ||
| 935 | } | ||
| 936 | } | ||
| 937 | |||
| 389 | /** | 938 | /** |
| 390 | * struct clk_mclk - U300 MCLK clock (MMC/SD clock) | 939 | * struct clk_mclk - U300 MCLK clock (MMC/SD clock) |
| 391 | * @hw: corresponding clock hardware entry | 940 | * @hw: corresponding clock hardware entry |
| @@ -590,10 +1139,41 @@ mclk_clk_register(struct device *dev, const char *name, | |||
| 590 | return clk; | 1139 | return clk; |
| 591 | } | 1140 | } |
| 592 | 1141 | ||
| 1142 | static void __init of_u300_syscon_mclk_init(struct device_node *np) | ||
| 1143 | { | ||
| 1144 | struct clk *clk = ERR_PTR(-EINVAL); | ||
| 1145 | const char *clk_name = np->name; | ||
| 1146 | const char *parent_name; | ||
| 1147 | |||
| 1148 | parent_name = of_clk_get_parent_name(np, 0); | ||
| 1149 | clk = mclk_clk_register(NULL, clk_name, parent_name, false); | ||
| 1150 | if (!IS_ERR(clk)) | ||
| 1151 | of_clk_add_provider(np, of_clk_src_simple_get, clk); | ||
| 1152 | } | ||
| 1153 | |||
| 1154 | static const __initconst struct of_device_id u300_clk_match[] = { | ||
| 1155 | { | ||
| 1156 | .compatible = "fixed-clock", | ||
| 1157 | .data = of_fixed_clk_setup, | ||
| 1158 | }, | ||
| 1159 | { | ||
| 1160 | .compatible = "fixed-factor-clock", | ||
| 1161 | .data = of_fixed_factor_clk_setup, | ||
| 1162 | }, | ||
| 1163 | { | ||
| 1164 | .compatible = "stericsson,u300-syscon-clk", | ||
| 1165 | .data = of_u300_syscon_clk_init, | ||
| 1166 | }, | ||
| 1167 | { | ||
| 1168 | .compatible = "stericsson,u300-syscon-mclk", | ||
| 1169 | .data = of_u300_syscon_mclk_init, | ||
| 1170 | }, | ||
| 1171 | }; | ||
| 1172 | |||
| 1173 | |||
| 593 | void __init u300_clk_init(void __iomem *base) | 1174 | void __init u300_clk_init(void __iomem *base) |
| 594 | { | 1175 | { |
| 595 | u16 val; | 1176 | u16 val; |
| 596 | struct clk *clk; | ||
| 597 | 1177 | ||
| 598 | syscon_vbase = base; | 1178 | syscon_vbase = base; |
| 599 | 1179 | ||
| @@ -610,137 +1190,5 @@ void __init u300_clk_init(void __iomem *base) | |||
| 610 | val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE; | 1190 | val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE; |
| 611 | writew(val, syscon_vbase + U300_SYSCON_PMCR); | 1191 | writew(val, syscon_vbase + U300_SYSCON_PMCR); |
| 612 | 1192 | ||
| 613 | /* These are always available (RTC and PLL13) */ | 1193 | of_clk_init(u300_clk_match); |
| 614 | clk = clk_register_fixed_rate(NULL, "app_32_clk", NULL, | ||
| 615 | CLK_IS_ROOT, 32768); | ||
| 616 | /* The watchdog sits directly on the 32 kHz clock */ | ||
| 617 | clk_register_clkdev(clk, NULL, "coh901327_wdog"); | ||
| 618 | clk = clk_register_fixed_rate(NULL, "pll13", NULL, | ||
| 619 | CLK_IS_ROOT, 13000000); | ||
| 620 | |||
| 621 | /* These derive from PLL208 */ | ||
| 622 | clk = clk_register_fixed_rate(NULL, "pll208", NULL, | ||
| 623 | CLK_IS_ROOT, 208000000); | ||
| 624 | clk = clk_register_fixed_factor(NULL, "app_208_clk", "pll208", | ||
| 625 | 0, 1, 1); | ||
| 626 | clk = clk_register_fixed_factor(NULL, "app_104_clk", "pll208", | ||
| 627 | 0, 1, 2); | ||
| 628 | clk = clk_register_fixed_factor(NULL, "app_52_clk", "pll208", | ||
| 629 | 0, 1, 4); | ||
| 630 | /* The 52 MHz is divided down to 26 MHz */ | ||
| 631 | clk = clk_register_fixed_factor(NULL, "app_26_clk", "app_52_clk", | ||
| 632 | 0, 1, 2); | ||
| 633 | |||
| 634 | /* Directly on the AMBA interconnect */ | ||
| 635 | clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true, | ||
| 636 | syscon_vbase + U300_SYSCON_RRR, 3, | ||
| 637 | syscon_vbase + U300_SYSCON_CERR, 3, | ||
| 638 | U300_SYSCON_SBCER_CPU_CLK_EN); | ||
| 639 | clk = syscon_clk_register(NULL, "dmac_clk", "app_52_clk", 0, true, | ||
| 640 | syscon_vbase + U300_SYSCON_RRR, 4, | ||
| 641 | syscon_vbase + U300_SYSCON_CERR, 4, | ||
| 642 | U300_SYSCON_SBCER_DMAC_CLK_EN); | ||
| 643 | clk_register_clkdev(clk, NULL, "dma"); | ||
| 644 | clk = syscon_clk_register(NULL, "fsmc_clk", "app_52_clk", 0, false, | ||
| 645 | syscon_vbase + U300_SYSCON_RRR, 6, | ||
| 646 | syscon_vbase + U300_SYSCON_CERR, 6, | ||
| 647 | U300_SYSCON_SBCER_NANDIF_CLK_EN); | ||
| 648 | clk_register_clkdev(clk, NULL, "fsmc-nand"); | ||
| 649 | clk = syscon_clk_register(NULL, "xgam_clk", "app_52_clk", 0, true, | ||
| 650 | syscon_vbase + U300_SYSCON_RRR, 8, | ||
| 651 | syscon_vbase + U300_SYSCON_CERR, 8, | ||
| 652 | U300_SYSCON_SBCER_XGAM_CLK_EN); | ||
| 653 | clk_register_clkdev(clk, NULL, "xgam"); | ||
| 654 | clk = syscon_clk_register(NULL, "semi_clk", "app_104_clk", 0, false, | ||
| 655 | syscon_vbase + U300_SYSCON_RRR, 9, | ||
| 656 | syscon_vbase + U300_SYSCON_CERR, 9, | ||
| 657 | U300_SYSCON_SBCER_SEMI_CLK_EN); | ||
| 658 | clk_register_clkdev(clk, NULL, "semi"); | ||
| 659 | |||
| 660 | /* AHB bridge clocks */ | ||
| 661 | clk = syscon_clk_register(NULL, "ahb_subsys_clk", "app_52_clk", 0, true, | ||
| 662 | syscon_vbase + U300_SYSCON_RRR, 10, | ||
| 663 | syscon_vbase + U300_SYSCON_CERR, 10, | ||
| 664 | U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN); | ||
| 665 | clk = syscon_clk_register(NULL, "intcon_clk", "ahb_subsys_clk", 0, false, | ||
| 666 | syscon_vbase + U300_SYSCON_RRR, 12, | ||
| 667 | syscon_vbase + U300_SYSCON_CERR, 12, | ||
| 668 | /* Cannot be enabled, just taken out of reset */ | ||
| 669 | 0xFFFFU); | ||
| 670 | clk_register_clkdev(clk, NULL, "intcon"); | ||
| 671 | clk = syscon_clk_register(NULL, "emif_clk", "ahb_subsys_clk", 0, false, | ||
| 672 | syscon_vbase + U300_SYSCON_RRR, 5, | ||
| 673 | syscon_vbase + U300_SYSCON_CERR, 5, | ||
| 674 | U300_SYSCON_SBCER_EMIF_CLK_EN); | ||
| 675 | clk_register_clkdev(clk, NULL, "pl172"); | ||
| 676 | |||
| 677 | /* FAST bridge clocks */ | ||
| 678 | clk = syscon_clk_register(NULL, "fast_clk", "app_26_clk", 0, true, | ||
| 679 | syscon_vbase + U300_SYSCON_RFR, 0, | ||
| 680 | syscon_vbase + U300_SYSCON_CEFR, 0, | ||
| 681 | U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN); | ||
| 682 | clk = syscon_clk_register(NULL, "i2c0_p_clk", "fast_clk", 0, false, | ||
| 683 | syscon_vbase + U300_SYSCON_RFR, 1, | ||
| 684 | syscon_vbase + U300_SYSCON_CEFR, 1, | ||
| 685 | U300_SYSCON_SBCER_I2C0_CLK_EN); | ||
| 686 | clk_register_clkdev(clk, NULL, "stu300.0"); | ||
| 687 | clk = syscon_clk_register(NULL, "i2c1_p_clk", "fast_clk", 0, false, | ||
| 688 | syscon_vbase + U300_SYSCON_RFR, 2, | ||
| 689 | syscon_vbase + U300_SYSCON_CEFR, 2, | ||
| 690 | U300_SYSCON_SBCER_I2C1_CLK_EN); | ||
| 691 | clk_register_clkdev(clk, NULL, "stu300.1"); | ||
| 692 | clk = syscon_clk_register(NULL, "mmc_p_clk", "fast_clk", 0, false, | ||
| 693 | syscon_vbase + U300_SYSCON_RFR, 5, | ||
| 694 | syscon_vbase + U300_SYSCON_CEFR, 5, | ||
| 695 | U300_SYSCON_SBCER_MMC_CLK_EN); | ||
| 696 | clk_register_clkdev(clk, "apb_pclk", "mmci"); | ||
| 697 | clk = syscon_clk_register(NULL, "spi_p_clk", "fast_clk", 0, false, | ||
| 698 | syscon_vbase + U300_SYSCON_RFR, 6, | ||
| 699 | syscon_vbase + U300_SYSCON_CEFR, 6, | ||
| 700 | U300_SYSCON_SBCER_SPI_CLK_EN); | ||
| 701 | /* The SPI has no external clock for the outward bus, uses the pclk */ | ||
| 702 | clk_register_clkdev(clk, NULL, "pl022"); | ||
| 703 | clk_register_clkdev(clk, "apb_pclk", "pl022"); | ||
| 704 | |||
| 705 | /* SLOW bridge clocks */ | ||
| 706 | clk = syscon_clk_register(NULL, "slow_clk", "pll13", 0, true, | ||
| 707 | syscon_vbase + U300_SYSCON_RSR, 0, | ||
| 708 | syscon_vbase + U300_SYSCON_CESR, 0, | ||
| 709 | U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN); | ||
| 710 | clk = syscon_clk_register(NULL, "uart0_clk", "slow_clk", 0, false, | ||
| 711 | syscon_vbase + U300_SYSCON_RSR, 1, | ||
| 712 | syscon_vbase + U300_SYSCON_CESR, 1, | ||
| 713 | U300_SYSCON_SBCER_UART_CLK_EN); | ||
| 714 | /* Same clock is used for APB and outward bus */ | ||
| 715 | clk_register_clkdev(clk, NULL, "uart0"); | ||
| 716 | clk_register_clkdev(clk, "apb_pclk", "uart0"); | ||
| 717 | clk = syscon_clk_register(NULL, "gpio_clk", "slow_clk", 0, false, | ||
| 718 | syscon_vbase + U300_SYSCON_RSR, 4, | ||
| 719 | syscon_vbase + U300_SYSCON_CESR, 4, | ||
| 720 | U300_SYSCON_SBCER_GPIO_CLK_EN); | ||
| 721 | clk_register_clkdev(clk, NULL, "u300-gpio"); | ||
| 722 | clk = syscon_clk_register(NULL, "keypad_clk", "slow_clk", 0, false, | ||
| 723 | syscon_vbase + U300_SYSCON_RSR, 5, | ||
| 724 | syscon_vbase + U300_SYSCON_CESR, 6, | ||
| 725 | U300_SYSCON_SBCER_KEYPAD_CLK_EN); | ||
| 726 | clk_register_clkdev(clk, NULL, "coh901461-keypad"); | ||
| 727 | clk = syscon_clk_register(NULL, "rtc_clk", "slow_clk", 0, true, | ||
| 728 | syscon_vbase + U300_SYSCON_RSR, 6, | ||
| 729 | /* No clock enable register bit */ | ||
| 730 | NULL, 0, 0xFFFFU); | ||
| 731 | clk_register_clkdev(clk, NULL, "rtc-coh901331"); | ||
| 732 | clk = syscon_clk_register(NULL, "app_tmr_clk", "slow_clk", 0, false, | ||
| 733 | syscon_vbase + U300_SYSCON_RSR, 7, | ||
| 734 | syscon_vbase + U300_SYSCON_CESR, 7, | ||
| 735 | U300_SYSCON_SBCER_APP_TMR_CLK_EN); | ||
| 736 | clk_register_clkdev(clk, NULL, "apptimer"); | ||
| 737 | clk = syscon_clk_register(NULL, "acc_tmr_clk", "slow_clk", 0, false, | ||
| 738 | syscon_vbase + U300_SYSCON_RSR, 8, | ||
| 739 | syscon_vbase + U300_SYSCON_CESR, 8, | ||
| 740 | U300_SYSCON_SBCER_ACC_TMR_CLK_EN); | ||
| 741 | clk_register_clkdev(clk, NULL, "timer"); | ||
| 742 | |||
| 743 | /* Then this special MMC/SD clock */ | ||
| 744 | clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false); | ||
| 745 | clk_register_clkdev(clk, NULL, "mmci"); | ||
| 746 | } | 1194 | } |