diff options
author | Vipul Kumar Samar <vipulkumar.samar@st.com> | 2012-11-10 01:43:43 -0500 |
---|---|---|
committer | Mike Turquette <mturquette@linaro.org> | 2012-11-21 14:45:45 -0500 |
commit | 1249979242db10d2fe1793f26e7658d94b7bf6dc (patch) | |
tree | 893efc50099b1ad06e137af84c5cd37f7b33c3b2 /drivers/clk | |
parent | 463f9e209ca69d52344479544d1e52c02f2e6918 (diff) |
CLK: SPEAr: Set CLK_SET_RATE_PARENT for few clocks
Flag CLK_SET_RATE_PARENT is required for a clock, where we want to
propagate clk_set_rate to its parent. This patch adds this to multiple clocks.
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Vijay Kumar Mishra <vijay.kumar@st.com>
Signed-off-by: Vijay Kumar Mishra <vijay.kumar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r-- | drivers/clk/spear/clk-aux-synth.c | 3 | ||||
-rw-r--r-- | drivers/clk/spear/spear1310_clock.c | 49 | ||||
-rw-r--r-- | drivers/clk/spear/spear1340_clock.c | 73 | ||||
-rw-r--r-- | drivers/clk/spear/spear3xx_clock.c | 119 | ||||
-rw-r--r-- | drivers/clk/spear/spear6xx_clock.c | 3 |
5 files changed, 133 insertions, 114 deletions
diff --git a/drivers/clk/spear/clk-aux-synth.c b/drivers/clk/spear/clk-aux-synth.c index 6756e7c3bc07..bdfb4421c643 100644 --- a/drivers/clk/spear/clk-aux-synth.c +++ b/drivers/clk/spear/clk-aux-synth.c | |||
@@ -179,7 +179,8 @@ struct clk *clk_register_aux(const char *aux_name, const char *gate_name, | |||
179 | if (gate_name) { | 179 | if (gate_name) { |
180 | struct clk *tgate_clk; | 180 | struct clk *tgate_clk; |
181 | 181 | ||
182 | tgate_clk = clk_register_gate(NULL, gate_name, aux_name, 0, reg, | 182 | tgate_clk = clk_register_gate(NULL, gate_name, aux_name, |
183 | CLK_SET_RATE_PARENT, reg, | ||
183 | aux->masks->enable_bit, 0, lock); | 184 | aux->masks->enable_bit, 0, lock); |
184 | if (IS_ERR_OR_NULL(tgate_clk)) | 185 | if (IS_ERR_OR_NULL(tgate_clk)) |
185 | goto free_aux; | 186 | goto free_aux; |
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c index e84b1fbb5838..2809b670e22c 100644 --- a/drivers/clk/spear/spear1310_clock.c +++ b/drivers/clk/spear/spear1310_clock.c | |||
@@ -483,7 +483,8 @@ void __init spear1310_clk_init(void) | |||
483 | clk_register_clkdev(clk, "ddr_clk", NULL); | 483 | clk_register_clkdev(clk, "ddr_clk", NULL); |
484 | 484 | ||
485 | /* clock derived from pll1 clk */ | 485 | /* clock derived from pll1 clk */ |
486 | clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 2); | 486 | clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", |
487 | CLK_SET_RATE_PARENT, 1, 2); | ||
487 | clk_register_clkdev(clk, "cpu_clk", NULL); | 488 | clk_register_clkdev(clk, "cpu_clk", NULL); |
488 | 489 | ||
489 | clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1, | 490 | clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1, |
@@ -547,14 +548,14 @@ void __init spear1310_clk_init(void) | |||
547 | clk_register_clkdev(clk1, "uart_syn_gclk", NULL); | 548 | clk_register_clkdev(clk1, "uart_syn_gclk", NULL); |
548 | 549 | ||
549 | clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, | 550 | clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, |
550 | ARRAY_SIZE(uart0_parents), 0, SPEAR1310_PERIP_CLK_CFG, | 551 | ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT, |
551 | SPEAR1310_UART_CLK_SHIFT, SPEAR1310_UART_CLK_MASK, 0, | 552 | SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT, |
552 | &_lock); | 553 | SPEAR1310_UART_CLK_MASK, 0, &_lock); |
553 | clk_register_clkdev(clk, "uart0_mclk", NULL); | 554 | clk_register_clkdev(clk, "uart0_mclk", NULL); |
554 | 555 | ||
555 | clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", 0, | 556 | clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", |
556 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UART_CLK_ENB, 0, | 557 | CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, |
557 | &_lock); | 558 | SPEAR1310_UART_CLK_ENB, 0, &_lock); |
558 | clk_register_clkdev(clk, NULL, "e0000000.serial"); | 559 | clk_register_clkdev(clk, NULL, "e0000000.serial"); |
559 | 560 | ||
560 | clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk", | 561 | clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk", |
@@ -563,9 +564,9 @@ void __init spear1310_clk_init(void) | |||
563 | clk_register_clkdev(clk, "sdhci_syn_clk", NULL); | 564 | clk_register_clkdev(clk, "sdhci_syn_clk", NULL); |
564 | clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL); | 565 | clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL); |
565 | 566 | ||
566 | clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", 0, | 567 | clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", |
567 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SDHCI_CLK_ENB, 0, | 568 | CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, |
568 | &_lock); | 569 | SPEAR1310_SDHCI_CLK_ENB, 0, &_lock); |
569 | clk_register_clkdev(clk, NULL, "b3000000.sdhci"); | 570 | clk_register_clkdev(clk, NULL, "b3000000.sdhci"); |
570 | 571 | ||
571 | clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk", | 572 | clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk", |
@@ -574,9 +575,9 @@ void __init spear1310_clk_init(void) | |||
574 | clk_register_clkdev(clk, "cfxd_syn_clk", NULL); | 575 | clk_register_clkdev(clk, "cfxd_syn_clk", NULL); |
575 | clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL); | 576 | clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL); |
576 | 577 | ||
577 | clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", 0, | 578 | clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", |
578 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CFXD_CLK_ENB, 0, | 579 | CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, |
579 | &_lock); | 580 | SPEAR1310_CFXD_CLK_ENB, 0, &_lock); |
580 | clk_register_clkdev(clk, NULL, "b2800000.cf"); | 581 | clk_register_clkdev(clk, NULL, "b2800000.cf"); |
581 | clk_register_clkdev(clk, NULL, "arasan_xd"); | 582 | clk_register_clkdev(clk, NULL, "arasan_xd"); |
582 | 583 | ||
@@ -587,9 +588,9 @@ void __init spear1310_clk_init(void) | |||
587 | clk_register_clkdev(clk1, "c3_syn_gclk", NULL); | 588 | clk_register_clkdev(clk1, "c3_syn_gclk", NULL); |
588 | 589 | ||
589 | clk = clk_register_mux(NULL, "c3_mclk", c3_parents, | 590 | clk = clk_register_mux(NULL, "c3_mclk", c3_parents, |
590 | ARRAY_SIZE(c3_parents), 0, SPEAR1310_PERIP_CLK_CFG, | 591 | ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT, |
591 | SPEAR1310_C3_CLK_SHIFT, SPEAR1310_C3_CLK_MASK, 0, | 592 | SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT, |
592 | &_lock); | 593 | SPEAR1310_C3_CLK_MASK, 0, &_lock); |
593 | clk_register_clkdev(clk, "c3_mclk", NULL); | 594 | clk_register_clkdev(clk, "c3_mclk", NULL); |
594 | 595 | ||
595 | clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0, | 596 | clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0, |
@@ -630,7 +631,7 @@ void __init spear1310_clk_init(void) | |||
630 | clk_register_clkdev(clk, "clcd_syn_clk", NULL); | 631 | clk_register_clkdev(clk, "clcd_syn_clk", NULL); |
631 | 632 | ||
632 | clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, | 633 | clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, |
633 | ARRAY_SIZE(clcd_pixel_parents), 0, | 634 | ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT, |
634 | SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT, | 635 | SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT, |
635 | SPEAR1310_CLCD_CLK_MASK, 0, &_lock); | 636 | SPEAR1310_CLCD_CLK_MASK, 0, &_lock); |
636 | clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); | 637 | clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); |
@@ -653,10 +654,10 @@ void __init spear1310_clk_init(void) | |||
653 | clk_register_clkdev(clk, "i2s_prs1_clk", NULL); | 654 | clk_register_clkdev(clk, "i2s_prs1_clk", NULL); |
654 | 655 | ||
655 | clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, | 656 | clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, |
656 | ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1310_I2S_CLK_CFG, | 657 | ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT, |
657 | SPEAR1310_I2S_REF_SHIFT, SPEAR1310_I2S_REF_SEL_MASK, 0, | 658 | SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT, |
658 | &_lock); | 659 | SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock); |
659 | clk_register_clkdev(clk, "i2s_ref_clk", NULL); | 660 | clk_register_clkdev(clk, "i2s_ref_mclk", NULL); |
660 | 661 | ||
661 | clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0, | 662 | clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0, |
662 | SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB, | 663 | SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB, |
@@ -753,9 +754,9 @@ void __init spear1310_clk_init(void) | |||
753 | clk_register_clkdev(clk, "adc_syn_clk", NULL); | 754 | clk_register_clkdev(clk, "adc_syn_clk", NULL); |
754 | clk_register_clkdev(clk1, "adc_syn_gclk", NULL); | 755 | clk_register_clkdev(clk1, "adc_syn_gclk", NULL); |
755 | 756 | ||
756 | clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", 0, | 757 | clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", |
757 | SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_ADC_CLK_ENB, 0, | 758 | CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, |
758 | &_lock); | 759 | SPEAR1310_ADC_CLK_ENB, 0, &_lock); |
759 | clk_register_clkdev(clk, NULL, "e0080000.adc"); | 760 | clk_register_clkdev(clk, NULL, "e0080000.adc"); |
760 | 761 | ||
761 | /* clock derived from apb clk */ | 762 | /* clock derived from apb clk */ |
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c index 020431ac163d..aa5ed435fbad 100644 --- a/drivers/clk/spear/spear1340_clock.c +++ b/drivers/clk/spear/spear1340_clock.c | |||
@@ -594,14 +594,14 @@ void __init spear1340_clk_init(void) | |||
594 | clk_register_clkdev(clk1, "uart0_syn_gclk", NULL); | 594 | clk_register_clkdev(clk1, "uart0_syn_gclk", NULL); |
595 | 595 | ||
596 | clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, | 596 | clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, |
597 | ARRAY_SIZE(uart0_parents), 0, SPEAR1340_PERIP_CLK_CFG, | 597 | ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT, |
598 | SPEAR1340_UART0_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0, | 598 | SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART0_CLK_SHIFT, |
599 | &_lock); | 599 | SPEAR1340_UART_CLK_MASK, 0, &_lock); |
600 | clk_register_clkdev(clk, "uart0_mclk", NULL); | 600 | clk_register_clkdev(clk, "uart0_mclk", NULL); |
601 | 601 | ||
602 | clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", 0, | 602 | clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", |
603 | SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UART0_CLK_ENB, 0, | 603 | CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, |
604 | &_lock); | 604 | SPEAR1340_UART0_CLK_ENB, 0, &_lock); |
605 | clk_register_clkdev(clk, NULL, "e0000000.serial"); | 605 | clk_register_clkdev(clk, NULL, "e0000000.serial"); |
606 | 606 | ||
607 | clk = clk_register_aux("uart1_syn_clk", "uart1_syn_gclk", | 607 | clk = clk_register_aux("uart1_syn_clk", "uart1_syn_gclk", |
@@ -627,9 +627,9 @@ void __init spear1340_clk_init(void) | |||
627 | clk_register_clkdev(clk, "sdhci_syn_clk", NULL); | 627 | clk_register_clkdev(clk, "sdhci_syn_clk", NULL); |
628 | clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL); | 628 | clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL); |
629 | 629 | ||
630 | clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", 0, | 630 | clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", |
631 | SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SDHCI_CLK_ENB, 0, | 631 | CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, |
632 | &_lock); | 632 | SPEAR1340_SDHCI_CLK_ENB, 0, &_lock); |
633 | clk_register_clkdev(clk, NULL, "b3000000.sdhci"); | 633 | clk_register_clkdev(clk, NULL, "b3000000.sdhci"); |
634 | 634 | ||
635 | clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk", | 635 | clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk", |
@@ -638,9 +638,9 @@ void __init spear1340_clk_init(void) | |||
638 | clk_register_clkdev(clk, "cfxd_syn_clk", NULL); | 638 | clk_register_clkdev(clk, "cfxd_syn_clk", NULL); |
639 | clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL); | 639 | clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL); |
640 | 640 | ||
641 | clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", 0, | 641 | clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", |
642 | SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CFXD_CLK_ENB, 0, | 642 | CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, |
643 | &_lock); | 643 | SPEAR1340_CFXD_CLK_ENB, 0, &_lock); |
644 | clk_register_clkdev(clk, NULL, "b2800000.cf"); | 644 | clk_register_clkdev(clk, NULL, "b2800000.cf"); |
645 | clk_register_clkdev(clk, NULL, "arasan_xd"); | 645 | clk_register_clkdev(clk, NULL, "arasan_xd"); |
646 | 646 | ||
@@ -651,12 +651,12 @@ void __init spear1340_clk_init(void) | |||
651 | clk_register_clkdev(clk1, "c3_syn_gclk", NULL); | 651 | clk_register_clkdev(clk1, "c3_syn_gclk", NULL); |
652 | 652 | ||
653 | clk = clk_register_mux(NULL, "c3_mclk", c3_parents, | 653 | clk = clk_register_mux(NULL, "c3_mclk", c3_parents, |
654 | ARRAY_SIZE(c3_parents), 0, SPEAR1340_PERIP_CLK_CFG, | 654 | ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT, |
655 | SPEAR1340_C3_CLK_SHIFT, SPEAR1340_C3_CLK_MASK, 0, | 655 | SPEAR1340_PERIP_CLK_CFG, SPEAR1340_C3_CLK_SHIFT, |
656 | &_lock); | 656 | SPEAR1340_C3_CLK_MASK, 0, &_lock); |
657 | clk_register_clkdev(clk, "c3_mclk", NULL); | 657 | clk_register_clkdev(clk, "c3_mclk", NULL); |
658 | 658 | ||
659 | clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0, | 659 | clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", CLK_SET_RATE_PARENT, |
660 | SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_C3_CLK_ENB, 0, | 660 | SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_C3_CLK_ENB, 0, |
661 | &_lock); | 661 | &_lock); |
662 | clk_register_clkdev(clk, NULL, "e1800000.c3"); | 662 | clk_register_clkdev(clk, NULL, "e1800000.c3"); |
@@ -694,7 +694,7 @@ void __init spear1340_clk_init(void) | |||
694 | clk_register_clkdev(clk, "clcd_syn_clk", NULL); | 694 | clk_register_clkdev(clk, "clcd_syn_clk", NULL); |
695 | 695 | ||
696 | clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, | 696 | clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, |
697 | ARRAY_SIZE(clcd_pixel_parents), 0, | 697 | ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT, |
698 | SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT, | 698 | SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT, |
699 | SPEAR1340_CLCD_CLK_MASK, 0, &_lock); | 699 | SPEAR1340_CLCD_CLK_MASK, 0, &_lock); |
700 | clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); | 700 | clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); |
@@ -711,15 +711,16 @@ void __init spear1340_clk_init(void) | |||
711 | 0, &_lock); | 711 | 0, &_lock); |
712 | clk_register_clkdev(clk, "i2s_src_mclk", NULL); | 712 | clk_register_clkdev(clk, "i2s_src_mclk", NULL); |
713 | 713 | ||
714 | clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0, | 714 | clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", |
715 | SPEAR1340_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl, | 715 | CLK_SET_RATE_PARENT, SPEAR1340_I2S_CLK_CFG, |
716 | &i2s_prs1_masks, i2s_prs1_rtbl, | ||
716 | ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL); | 717 | ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL); |
717 | clk_register_clkdev(clk, "i2s_prs1_clk", NULL); | 718 | clk_register_clkdev(clk, "i2s_prs1_clk", NULL); |
718 | 719 | ||
719 | clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, | 720 | clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, |
720 | ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1340_I2S_CLK_CFG, | 721 | ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT, |
721 | SPEAR1340_I2S_REF_SHIFT, SPEAR1340_I2S_REF_SEL_MASK, 0, | 722 | SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_REF_SHIFT, |
722 | &_lock); | 723 | SPEAR1340_I2S_REF_SEL_MASK, 0, &_lock); |
723 | clk_register_clkdev(clk, "i2s_ref_mclk", NULL); | 724 | clk_register_clkdev(clk, "i2s_ref_mclk", NULL); |
724 | 725 | ||
725 | clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0, | 726 | clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0, |
@@ -805,9 +806,9 @@ void __init spear1340_clk_init(void) | |||
805 | clk_register_clkdev(clk, "adc_syn_clk", NULL); | 806 | clk_register_clkdev(clk, "adc_syn_clk", NULL); |
806 | clk_register_clkdev(clk1, "adc_syn_gclk", NULL); | 807 | clk_register_clkdev(clk1, "adc_syn_gclk", NULL); |
807 | 808 | ||
808 | clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", 0, | 809 | clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", |
809 | SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_ADC_CLK_ENB, 0, | 810 | CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, |
810 | &_lock); | 811 | SPEAR1340_ADC_CLK_ENB, 0, &_lock); |
811 | clk_register_clkdev(clk, NULL, "e0080000.adc"); | 812 | clk_register_clkdev(clk, NULL, "e0080000.adc"); |
812 | 813 | ||
813 | /* clock derived from apb clk */ | 814 | /* clock derived from apb clk */ |
@@ -874,9 +875,9 @@ void __init spear1340_clk_init(void) | |||
874 | &_lock); | 875 | &_lock); |
875 | clk_register_clkdev(clk, "gen_syn3_clk", NULL); | 876 | clk_register_clkdev(clk, "gen_syn3_clk", NULL); |
876 | 877 | ||
877 | clk = clk_register_gate(NULL, "mali_clk", "gen_syn3_clk", 0, | 878 | clk = clk_register_gate(NULL, "mali_clk", "gen_syn3_clk", |
878 | SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_MALI_CLK_ENB, 0, | 879 | CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB, |
879 | &_lock); | 880 | SPEAR1340_MALI_CLK_ENB, 0, &_lock); |
880 | clk_register_clkdev(clk, NULL, "mali"); | 881 | clk_register_clkdev(clk, NULL, "mali"); |
881 | 882 | ||
882 | clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0, | 883 | clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0, |
@@ -890,25 +891,25 @@ void __init spear1340_clk_init(void) | |||
890 | clk_register_clkdev(clk, NULL, "spear_cec.1"); | 891 | clk_register_clkdev(clk, NULL, "spear_cec.1"); |
891 | 892 | ||
892 | clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents, | 893 | clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents, |
893 | ARRAY_SIZE(spdif_out_parents), 0, | 894 | ARRAY_SIZE(spdif_out_parents), CLK_SET_RATE_PARENT, |
894 | SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT, | 895 | SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT, |
895 | SPEAR1340_SPDIF_CLK_MASK, 0, &_lock); | 896 | SPEAR1340_SPDIF_CLK_MASK, 0, &_lock); |
896 | clk_register_clkdev(clk, "spdif_out_mclk", NULL); | 897 | clk_register_clkdev(clk, "spdif_out_mclk", NULL); |
897 | 898 | ||
898 | clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mclk", 0, | 899 | clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mclk", |
899 | SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_OUT_CLK_ENB, | 900 | CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB, |
900 | 0, &_lock); | 901 | SPEAR1340_SPDIF_OUT_CLK_ENB, 0, &_lock); |
901 | clk_register_clkdev(clk, NULL, "d0000000.spdif-out"); | 902 | clk_register_clkdev(clk, NULL, "d0000000.spdif-out"); |
902 | 903 | ||
903 | clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents, | 904 | clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents, |
904 | ARRAY_SIZE(spdif_in_parents), 0, | 905 | ARRAY_SIZE(spdif_in_parents), CLK_SET_RATE_PARENT, |
905 | SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT, | 906 | SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT, |
906 | SPEAR1340_SPDIF_CLK_MASK, 0, &_lock); | 907 | SPEAR1340_SPDIF_CLK_MASK, 0, &_lock); |
907 | clk_register_clkdev(clk, "spdif_in_mclk", NULL); | 908 | clk_register_clkdev(clk, "spdif_in_mclk", NULL); |
908 | 909 | ||
909 | clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mclk", 0, | 910 | clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mclk", |
910 | SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_IN_CLK_ENB, 0, | 911 | CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB, |
911 | &_lock); | 912 | SPEAR1340_SPDIF_IN_CLK_ENB, 0, &_lock); |
912 | clk_register_clkdev(clk, NULL, "d0100000.spdif-in"); | 913 | clk_register_clkdev(clk, NULL, "d0100000.spdif-in"); |
913 | 914 | ||
914 | clk = clk_register_gate(NULL, "acp_clk", "acp_mclk", 0, | 915 | clk = clk_register_gate(NULL, "acp_clk", "acp_mclk", 0, |
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c index 417f93734612..4c89b143e246 100644 --- a/drivers/clk/spear/spear3xx_clock.c +++ b/drivers/clk/spear/spear3xx_clock.c | |||
@@ -278,23 +278,26 @@ static void __init spear320_clk_init(void) | |||
278 | clk_register_clkdev(clk, NULL, "a9400000.i2s"); | 278 | clk_register_clkdev(clk, NULL, "a9400000.i2s"); |
279 | 279 | ||
280 | clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents, | 280 | clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents, |
281 | ARRAY_SIZE(i2s_ref_parents), 0, SPEAR320_CONTROL_REG, | 281 | ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT, |
282 | I2S_REF_PCLK_SHIFT, I2S_REF_PCLK_MASK, 0, &_lock); | 282 | SPEAR320_CONTROL_REG, I2S_REF_PCLK_SHIFT, |
283 | I2S_REF_PCLK_MASK, 0, &_lock); | ||
283 | clk_register_clkdev(clk, "i2s_ref_clk", NULL); | 284 | clk_register_clkdev(clk, "i2s_ref_clk", NULL); |
284 | 285 | ||
285 | clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk", 0, 1, | 286 | clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk", |
287 | CLK_SET_RATE_PARENT, 1, | ||
286 | 4); | 288 | 4); |
287 | clk_register_clkdev(clk, "i2s_sclk", NULL); | 289 | clk_register_clkdev(clk, "i2s_sclk", NULL); |
288 | 290 | ||
289 | clk = clk_register_mux(NULL, "rs485_clk", uartx_parents, | 291 | clk = clk_register_mux(NULL, "rs485_clk", uartx_parents, |
290 | ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, | 292 | ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT, |
291 | SPEAR320_RS485_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, | 293 | SPEAR320_EXT_CTRL_REG, SPEAR320_RS485_PCLK_SHIFT, |
292 | &_lock); | 294 | SPEAR320_UARTX_PCLK_MASK, 0, &_lock); |
293 | clk_register_clkdev(clk, NULL, "a9300000.serial"); | 295 | clk_register_clkdev(clk, NULL, "a9300000.serial"); |
294 | 296 | ||
295 | clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents, | 297 | clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents, |
296 | ARRAY_SIZE(sdhci_parents), 0, SPEAR320_CONTROL_REG, | 298 | ARRAY_SIZE(sdhci_parents), CLK_SET_RATE_PARENT, |
297 | SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK, 0, &_lock); | 299 | SPEAR320_CONTROL_REG, SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK, |
300 | 0, &_lock); | ||
298 | clk_register_clkdev(clk, NULL, "70000000.sdhci"); | 301 | clk_register_clkdev(clk, NULL, "70000000.sdhci"); |
299 | 302 | ||
300 | clk = clk_register_mux(NULL, "smii_pclk", smii0_parents, | 303 | clk = clk_register_mux(NULL, "smii_pclk", smii0_parents, |
@@ -306,38 +309,39 @@ static void __init spear320_clk_init(void) | |||
306 | clk_register_clkdev(clk, NULL, "smii"); | 309 | clk_register_clkdev(clk, NULL, "smii"); |
307 | 310 | ||
308 | clk = clk_register_mux(NULL, "uart1_clk", uartx_parents, | 311 | clk = clk_register_mux(NULL, "uart1_clk", uartx_parents, |
309 | ARRAY_SIZE(uartx_parents), 0, SPEAR320_CONTROL_REG, | 312 | ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT, |
310 | UART1_PCLK_SHIFT, UART1_PCLK_MASK, 0, &_lock); | 313 | SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK, |
314 | 0, &_lock); | ||
311 | clk_register_clkdev(clk, NULL, "a3000000.serial"); | 315 | clk_register_clkdev(clk, NULL, "a3000000.serial"); |
312 | 316 | ||
313 | clk = clk_register_mux(NULL, "uart2_clk", uartx_parents, | 317 | clk = clk_register_mux(NULL, "uart2_clk", uartx_parents, |
314 | ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, | 318 | ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT, |
315 | SPEAR320_UART2_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, | 319 | SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT, |
316 | &_lock); | 320 | SPEAR320_UARTX_PCLK_MASK, 0, &_lock); |
317 | clk_register_clkdev(clk, NULL, "a4000000.serial"); | 321 | clk_register_clkdev(clk, NULL, "a4000000.serial"); |
318 | 322 | ||
319 | clk = clk_register_mux(NULL, "uart3_clk", uartx_parents, | 323 | clk = clk_register_mux(NULL, "uart3_clk", uartx_parents, |
320 | ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, | 324 | ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT, |
321 | SPEAR320_UART3_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, | 325 | SPEAR320_EXT_CTRL_REG, SPEAR320_UART3_PCLK_SHIFT, |
322 | &_lock); | 326 | SPEAR320_UARTX_PCLK_MASK, 0, &_lock); |
323 | clk_register_clkdev(clk, NULL, "a9100000.serial"); | 327 | clk_register_clkdev(clk, NULL, "a9100000.serial"); |
324 | 328 | ||
325 | clk = clk_register_mux(NULL, "uart4_clk", uartx_parents, | 329 | clk = clk_register_mux(NULL, "uart4_clk", uartx_parents, |
326 | ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, | 330 | ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT, |
327 | SPEAR320_UART4_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, | 331 | SPEAR320_EXT_CTRL_REG, SPEAR320_UART4_PCLK_SHIFT, |
328 | &_lock); | 332 | SPEAR320_UARTX_PCLK_MASK, 0, &_lock); |
329 | clk_register_clkdev(clk, NULL, "a9200000.serial"); | 333 | clk_register_clkdev(clk, NULL, "a9200000.serial"); |
330 | 334 | ||
331 | clk = clk_register_mux(NULL, "uart5_clk", uartx_parents, | 335 | clk = clk_register_mux(NULL, "uart5_clk", uartx_parents, |
332 | ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, | 336 | ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT, |
333 | SPEAR320_UART5_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, | 337 | SPEAR320_EXT_CTRL_REG, SPEAR320_UART5_PCLK_SHIFT, |
334 | &_lock); | 338 | SPEAR320_UARTX_PCLK_MASK, 0, &_lock); |
335 | clk_register_clkdev(clk, NULL, "60000000.serial"); | 339 | clk_register_clkdev(clk, NULL, "60000000.serial"); |
336 | 340 | ||
337 | clk = clk_register_mux(NULL, "uart6_clk", uartx_parents, | 341 | clk = clk_register_mux(NULL, "uart6_clk", uartx_parents, |
338 | ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, | 342 | ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT, |
339 | SPEAR320_UART6_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, | 343 | SPEAR320_EXT_CTRL_REG, SPEAR320_UART6_PCLK_SHIFT, |
340 | &_lock); | 344 | SPEAR320_UARTX_PCLK_MASK, 0, &_lock); |
341 | clk_register_clkdev(clk, NULL, "60100000.serial"); | 345 | clk_register_clkdev(clk, NULL, "60100000.serial"); |
342 | } | 346 | } |
343 | #else | 347 | #else |
@@ -386,7 +390,8 @@ void __init spear3xx_clk_init(void) | |||
386 | clk_register_clkdev(clk1, "pll2_clk", NULL); | 390 | clk_register_clkdev(clk1, "pll2_clk", NULL); |
387 | 391 | ||
388 | /* clock derived from pll1 clk */ | 392 | /* clock derived from pll1 clk */ |
389 | clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 1); | 393 | clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", |
394 | CLK_SET_RATE_PARENT, 1, 1); | ||
390 | clk_register_clkdev(clk, "cpu_clk", NULL); | 395 | clk_register_clkdev(clk, "cpu_clk", NULL); |
391 | 396 | ||
392 | clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", | 397 | clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", |
@@ -401,12 +406,14 @@ void __init spear3xx_clk_init(void) | |||
401 | clk_register_clkdev(clk1, "uart_syn_gclk", NULL); | 406 | clk_register_clkdev(clk1, "uart_syn_gclk", NULL); |
402 | 407 | ||
403 | clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, | 408 | clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, |
404 | ARRAY_SIZE(uart0_parents), 0, PERIP_CLK_CFG, | 409 | ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT, |
405 | UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock); | 410 | PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0, |
411 | &_lock); | ||
406 | clk_register_clkdev(clk, "uart0_mclk", NULL); | 412 | clk_register_clkdev(clk, "uart0_mclk", NULL); |
407 | 413 | ||
408 | clk = clk_register_gate(NULL, "uart0", "uart0_mclk", 0, PERIP1_CLK_ENB, | 414 | clk = clk_register_gate(NULL, "uart0", "uart0_mclk", |
409 | UART_CLK_ENB, 0, &_lock); | 415 | CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, UART_CLK_ENB, 0, |
416 | &_lock); | ||
410 | clk_register_clkdev(clk, NULL, "d0000000.serial"); | 417 | clk_register_clkdev(clk, NULL, "d0000000.serial"); |
411 | 418 | ||
412 | clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 0, | 419 | clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 0, |
@@ -416,40 +423,44 @@ void __init spear3xx_clk_init(void) | |||
416 | clk_register_clkdev(clk1, "firda_syn_gclk", NULL); | 423 | clk_register_clkdev(clk1, "firda_syn_gclk", NULL); |
417 | 424 | ||
418 | clk = clk_register_mux(NULL, "firda_mclk", firda_parents, | 425 | clk = clk_register_mux(NULL, "firda_mclk", firda_parents, |
419 | ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG, | 426 | ARRAY_SIZE(firda_parents), CLK_SET_RATE_PARENT, |
420 | FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock); | 427 | PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, |
428 | &_lock); | ||
421 | clk_register_clkdev(clk, "firda_mclk", NULL); | 429 | clk_register_clkdev(clk, "firda_mclk", NULL); |
422 | 430 | ||
423 | clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0, | 431 | clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", |
424 | PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock); | 432 | CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, |
433 | &_lock); | ||
425 | clk_register_clkdev(clk, NULL, "firda"); | 434 | clk_register_clkdev(clk, NULL, "firda"); |
426 | 435 | ||
427 | /* gpt clocks */ | 436 | /* gpt clocks */ |
428 | clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl, | 437 | clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl, |
429 | ARRAY_SIZE(gpt_rtbl), &_lock); | 438 | ARRAY_SIZE(gpt_rtbl), &_lock); |
430 | clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents, | 439 | clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents, |
431 | ARRAY_SIZE(gpt0_parents), 0, PERIP_CLK_CFG, | 440 | ARRAY_SIZE(gpt0_parents), CLK_SET_RATE_PARENT, |
432 | GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); | 441 | PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); |
433 | clk_register_clkdev(clk, NULL, "gpt0"); | 442 | clk_register_clkdev(clk, NULL, "gpt0"); |
434 | 443 | ||
435 | clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl, | 444 | clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl, |
436 | ARRAY_SIZE(gpt_rtbl), &_lock); | 445 | ARRAY_SIZE(gpt_rtbl), &_lock); |
437 | clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents, | 446 | clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents, |
438 | ARRAY_SIZE(gpt1_parents), 0, PERIP_CLK_CFG, | 447 | ARRAY_SIZE(gpt1_parents), CLK_SET_RATE_PARENT, |
439 | GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); | 448 | PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); |
440 | clk_register_clkdev(clk, "gpt1_mclk", NULL); | 449 | clk_register_clkdev(clk, "gpt1_mclk", NULL); |
441 | clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, | 450 | clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", |
442 | PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock); | 451 | CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, |
452 | &_lock); | ||
443 | clk_register_clkdev(clk, NULL, "gpt1"); | 453 | clk_register_clkdev(clk, NULL, "gpt1"); |
444 | 454 | ||
445 | clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl, | 455 | clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl, |
446 | ARRAY_SIZE(gpt_rtbl), &_lock); | 456 | ARRAY_SIZE(gpt_rtbl), &_lock); |
447 | clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents, | 457 | clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents, |
448 | ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG, | 458 | ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_PARENT, |
449 | GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); | 459 | PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); |
450 | clk_register_clkdev(clk, "gpt2_mclk", NULL); | 460 | clk_register_clkdev(clk, "gpt2_mclk", NULL); |
451 | clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, | 461 | clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", |
452 | PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock); | 462 | CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, |
463 | &_lock); | ||
453 | clk_register_clkdev(clk, NULL, "gpt2"); | 464 | clk_register_clkdev(clk, NULL, "gpt2"); |
454 | 465 | ||
455 | /* general synths clocks */ | 466 | /* general synths clocks */ |
@@ -587,20 +598,24 @@ void __init spear3xx_clk_init(void) | |||
587 | RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock); | 598 | RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock); |
588 | clk_register_clkdev(clk, "ras_pll3_clk", NULL); | 599 | clk_register_clkdev(clk, "ras_pll3_clk", NULL); |
589 | 600 | ||
590 | clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk", 0, | 601 | clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk", |
591 | RAS_CLK_ENB, RAS_SYNT0_CLK_ENB, 0, &_lock); | 602 | CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT0_CLK_ENB, 0, |
603 | &_lock); | ||
592 | clk_register_clkdev(clk, "ras_syn0_gclk", NULL); | 604 | clk_register_clkdev(clk, "ras_syn0_gclk", NULL); |
593 | 605 | ||
594 | clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk", 0, | 606 | clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk", |
595 | RAS_CLK_ENB, RAS_SYNT1_CLK_ENB, 0, &_lock); | 607 | CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT1_CLK_ENB, 0, |
608 | &_lock); | ||
596 | clk_register_clkdev(clk, "ras_syn1_gclk", NULL); | 609 | clk_register_clkdev(clk, "ras_syn1_gclk", NULL); |
597 | 610 | ||
598 | clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk", 0, | 611 | clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk", |
599 | RAS_CLK_ENB, RAS_SYNT2_CLK_ENB, 0, &_lock); | 612 | CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT2_CLK_ENB, 0, |
613 | &_lock); | ||
600 | clk_register_clkdev(clk, "ras_syn2_gclk", NULL); | 614 | clk_register_clkdev(clk, "ras_syn2_gclk", NULL); |
601 | 615 | ||
602 | clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk", 0, | 616 | clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk", |
603 | RAS_CLK_ENB, RAS_SYNT3_CLK_ENB, 0, &_lock); | 617 | CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT3_CLK_ENB, 0, |
618 | &_lock); | ||
604 | clk_register_clkdev(clk, "ras_syn3_gclk", NULL); | 619 | clk_register_clkdev(clk, "ras_syn3_gclk", NULL); |
605 | 620 | ||
606 | if (of_machine_is_compatible("st,spear300")) | 621 | if (of_machine_is_compatible("st,spear300")) |
diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c index c7fa67c7c0ab..e8d2b3109b34 100644 --- a/drivers/clk/spear/spear6xx_clock.c +++ b/drivers/clk/spear/spear6xx_clock.c | |||
@@ -156,7 +156,8 @@ void __init spear6xx_clk_init(void) | |||
156 | clk_register_clkdev(clk, NULL, "wdt"); | 156 | clk_register_clkdev(clk, NULL, "wdt"); |
157 | 157 | ||
158 | /* clock derived from pll1 clk */ | 158 | /* clock derived from pll1 clk */ |
159 | clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 1); | 159 | clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", |
160 | CLK_SET_RATE_PARENT, 1, 1); | ||
160 | clk_register_clkdev(clk, "cpu_clk", NULL); | 161 | clk_register_clkdev(clk, "cpu_clk", NULL); |
161 | 162 | ||
162 | clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", | 163 | clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", |