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authorTomasz Figa <t.figa@samsung.com>2015-03-02 08:17:29 -0500
committerMichael Turquette <mturquette@linaro.org>2015-03-30 18:18:53 -0400
commit045ecad0fdb23f34a2769fa9d49384a3130f7831 (patch)
tree57392da0c6af330e6a28f17a2a46b53af8d458a5 /drivers/clk
parentabec147faa071af48e70f368319ba784284dc016 (diff)
clk: samsung: exynos3250: Add driver for CMU_ISP clock domain
Add clock controller for CMU ISP clock domain on Exynos3250, providing clocks for FIMC-IS subsystem. [b.michalska: use samsung_cmu_register_one to register the provider; updated DT binding documentation] Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Beata Michalska <b.michalska@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> [s.nawrocki: added __init attribute which was missing in function exynos3250_cmu_platform_init() in function, which has been] Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/samsung/clk-exynos3250.c163
1 files changed, 163 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index cc4c348d8a24..538de66a759e 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -894,3 +894,166 @@ static void __init exynos3250_cmu_dmc_init(struct device_node *np)
894} 894}
895CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc", 895CLK_OF_DECLARE(exynos3250_cmu_dmc, "samsung,exynos3250-cmu-dmc",
896 exynos3250_cmu_dmc_init); 896 exynos3250_cmu_dmc_init);
897
898
899/*
900 * CMU ISP
901 */
902
903#define DIV_ISP0 0x300
904#define DIV_ISP1 0x304
905#define GATE_IP_ISP0 0x800
906#define GATE_IP_ISP1 0x804
907#define GATE_SCLK_ISP 0x900
908
909static struct samsung_div_clock isp_div_clks[] __initdata = {
910 /*
911 * NOTE: Following table is sorted by register address in ascending
912 * order and then bitfield shift in descending order, as it is done
913 * in the User's Manual. When adding new entries, please make sure
914 * that the order is preserved, to avoid merge conflicts and make
915 * further work with defined data easier.
916 */
917 /* DIV_ISP0 */
918 DIV(CLK_DIV_ISP1, "div_isp1", "mout_aclk_266_sub", DIV_ISP0, 4, 3),
919 DIV(CLK_DIV_ISP0, "div_isp0", "mout_aclk_266_sub", DIV_ISP0, 0, 3),
920
921 /* DIV_ISP1 */
922 DIV(CLK_DIV_MCUISP1, "div_mcuisp1", "mout_aclk_400_mcuisp_sub",
923 DIV_ISP1, 8, 3),
924 DIV(CLK_DIV_MCUISP0, "div_mcuisp0", "mout_aclk_400_mcuisp_sub",
925 DIV_ISP1, 4, 3),
926 DIV(CLK_DIV_MPWM, "div_mpwm", "div_isp1", DIV_ISP1, 0, 3),
927};
928
929static struct samsung_gate_clock isp_gate_clks[] __initdata = {
930 /*
931 * NOTE: Following table is sorted by register address in ascending
932 * order and then bitfield shift in descending order, as it is done
933 * in the User's Manual. When adding new entries, please make sure
934 * that the order is preserved, to avoid merge conflicts and make
935 * further work with defined data easier.
936 */
937
938 /* GATE_IP_ISP0 */
939 GATE(CLK_UART_ISP, "uart_isp", "uart_isp_top",
940 GATE_IP_ISP0, 31, CLK_IGNORE_UNUSED, 0),
941 GATE(CLK_WDT_ISP, "wdt_isp", "mout_aclk_266_sub",
942 GATE_IP_ISP0, 30, CLK_IGNORE_UNUSED, 0),
943 GATE(CLK_PWM_ISP, "pwm_isp", "mout_aclk_266_sub",
944 GATE_IP_ISP0, 28, CLK_IGNORE_UNUSED, 0),
945 GATE(CLK_I2C1_ISP, "i2c1_isp", "mout_aclk_266_sub",
946 GATE_IP_ISP0, 26, CLK_IGNORE_UNUSED, 0),
947 GATE(CLK_I2C0_ISP, "i2c0_isp", "mout_aclk_266_sub",
948 GATE_IP_ISP0, 25, CLK_IGNORE_UNUSED, 0),
949 GATE(CLK_MPWM_ISP, "mpwm_isp", "mout_aclk_266_sub",
950 GATE_IP_ISP0, 24, CLK_IGNORE_UNUSED, 0),
951 GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "mout_aclk_266_sub",
952 GATE_IP_ISP0, 23, CLK_IGNORE_UNUSED, 0),
953 GATE(CLK_PPMUISPX, "ppmuispx", "mout_aclk_266_sub",
954 GATE_IP_ISP0, 21, CLK_IGNORE_UNUSED, 0),
955 GATE(CLK_PPMUISPMX, "ppmuispmx", "mout_aclk_266_sub",
956 GATE_IP_ISP0, 20, CLK_IGNORE_UNUSED, 0),
957 GATE(CLK_QE_LITE1, "qe_lite1", "mout_aclk_266_sub",
958 GATE_IP_ISP0, 18, CLK_IGNORE_UNUSED, 0),
959 GATE(CLK_QE_LITE0, "qe_lite0", "mout_aclk_266_sub",
960 GATE_IP_ISP0, 17, CLK_IGNORE_UNUSED, 0),
961 GATE(CLK_QE_FD, "qe_fd", "mout_aclk_266_sub",
962 GATE_IP_ISP0, 16, CLK_IGNORE_UNUSED, 0),
963 GATE(CLK_QE_DRC, "qe_drc", "mout_aclk_266_sub",
964 GATE_IP_ISP0, 15, CLK_IGNORE_UNUSED, 0),
965 GATE(CLK_QE_ISP, "qe_isp", "mout_aclk_266_sub",
966 GATE_IP_ISP0, 14, CLK_IGNORE_UNUSED, 0),
967 GATE(CLK_CSIS1, "csis1", "mout_aclk_266_sub",
968 GATE_IP_ISP0, 13, CLK_IGNORE_UNUSED, 0),
969 GATE(CLK_SMMU_LITE1, "smmu_lite1", "mout_aclk_266_sub",
970 GATE_IP_ISP0, 12, CLK_IGNORE_UNUSED, 0),
971 GATE(CLK_SMMU_LITE0, "smmu_lite0", "mout_aclk_266_sub",
972 GATE_IP_ISP0, 11, CLK_IGNORE_UNUSED, 0),
973 GATE(CLK_SMMU_FD, "smmu_fd", "mout_aclk_266_sub",
974 GATE_IP_ISP0, 10, CLK_IGNORE_UNUSED, 0),
975 GATE(CLK_SMMU_DRC, "smmu_drc", "mout_aclk_266_sub",
976 GATE_IP_ISP0, 9, CLK_IGNORE_UNUSED, 0),
977 GATE(CLK_SMMU_ISP, "smmu_isp", "mout_aclk_266_sub",
978 GATE_IP_ISP0, 8, CLK_IGNORE_UNUSED, 0),
979 GATE(CLK_GICISP, "gicisp", "mout_aclk_266_sub",
980 GATE_IP_ISP0, 7, CLK_IGNORE_UNUSED, 0),
981 GATE(CLK_CSIS0, "csis0", "mout_aclk_266_sub",
982 GATE_IP_ISP0, 6, CLK_IGNORE_UNUSED, 0),
983 GATE(CLK_MCUISP, "mcuisp", "mout_aclk_266_sub",
984 GATE_IP_ISP0, 5, CLK_IGNORE_UNUSED, 0),
985 GATE(CLK_LITE1, "lite1", "mout_aclk_266_sub",
986 GATE_IP_ISP0, 4, CLK_IGNORE_UNUSED, 0),
987 GATE(CLK_LITE0, "lite0", "mout_aclk_266_sub",
988 GATE_IP_ISP0, 3, CLK_IGNORE_UNUSED, 0),
989 GATE(CLK_FD, "fd", "mout_aclk_266_sub",
990 GATE_IP_ISP0, 2, CLK_IGNORE_UNUSED, 0),
991 GATE(CLK_DRC, "drc", "mout_aclk_266_sub",
992 GATE_IP_ISP0, 1, CLK_IGNORE_UNUSED, 0),
993 GATE(CLK_ISP, "isp", "mout_aclk_266_sub",
994 GATE_IP_ISP0, 0, CLK_IGNORE_UNUSED, 0),
995
996 /* GATE_IP_ISP1 */
997 GATE(CLK_QE_ISPCX, "qe_ispcx", "uart_isp_top",
998 GATE_IP_ISP0, 21, CLK_IGNORE_UNUSED, 0),
999 GATE(CLK_QE_SCALERP, "qe_scalerp", "uart_isp_top",
1000 GATE_IP_ISP0, 20, CLK_IGNORE_UNUSED, 0),
1001 GATE(CLK_QE_SCALERC, "qe_scalerc", "uart_isp_top",
1002 GATE_IP_ISP0, 19, CLK_IGNORE_UNUSED, 0),
1003 GATE(CLK_SMMU_SCALERP, "smmu_scalerp", "uart_isp_top",
1004 GATE_IP_ISP0, 18, CLK_IGNORE_UNUSED, 0),
1005 GATE(CLK_SMMU_SCALERC, "smmu_scalerc", "uart_isp_top",
1006 GATE_IP_ISP0, 17, CLK_IGNORE_UNUSED, 0),
1007 GATE(CLK_SCALERP, "scalerp", "uart_isp_top",
1008 GATE_IP_ISP0, 16, CLK_IGNORE_UNUSED, 0),
1009 GATE(CLK_SCALERC, "scalerc", "uart_isp_top",
1010 GATE_IP_ISP0, 15, CLK_IGNORE_UNUSED, 0),
1011 GATE(CLK_SPI1_ISP, "spi1_isp", "uart_isp_top",
1012 GATE_IP_ISP0, 13, CLK_IGNORE_UNUSED, 0),
1013 GATE(CLK_SPI0_ISP, "spi0_isp", "uart_isp_top",
1014 GATE_IP_ISP0, 12, CLK_IGNORE_UNUSED, 0),
1015 GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "uart_isp_top",
1016 GATE_IP_ISP0, 4, CLK_IGNORE_UNUSED, 0),
1017 GATE(CLK_ASYNCAXIM, "asyncaxim", "uart_isp_top",
1018 GATE_IP_ISP0, 0, CLK_IGNORE_UNUSED, 0),
1019
1020 /* GATE_SCLK_ISP */
1021 GATE(CLK_SCLK_MPWM_ISP, "sclk_mpwm_isp", "div_mpwm",
1022 GATE_SCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
1023};
1024
1025static struct samsung_cmu_info isp_cmu_info __initdata = {
1026 .div_clks = isp_div_clks,
1027 .nr_div_clks = ARRAY_SIZE(isp_div_clks),
1028 .gate_clks = isp_gate_clks,
1029 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
1030 .nr_clk_ids = NR_CLKS_ISP,
1031};
1032
1033static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev)
1034{
1035 struct device_node *np = pdev->dev.of_node;
1036
1037 samsung_cmu_register_one(np, &isp_cmu_info);
1038 return 0;
1039}
1040
1041static const struct of_device_id exynos3250_cmu_isp_of_match[] = {
1042 { .compatible = "samsung,exynos3250-cmu-isp", },
1043 { /* sentinel */ }
1044};
1045
1046static struct platform_driver exynos3250_cmu_isp_driver = {
1047 .driver = {
1048 .name = "exynos3250-cmu-isp",
1049 .of_match_table = exynos3250_cmu_isp_of_match,
1050 },
1051};
1052
1053static int __init exynos3250_cmu_platform_init(void)
1054{
1055 return platform_driver_probe(&exynos3250_cmu_isp_driver,
1056 exynos3250_cmu_isp_probe);
1057}
1058subsys_initcall(exynos3250_cmu_platform_init);
1059
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-26 01:37:27 -0400