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authorLinus Torvalds <torvalds@linux-foundation.org>2012-12-13 13:57:16 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2012-12-13 13:57:16 -0500
commitb8edf848e9119bab9d999b9ca80d8520641810f2 (patch)
tree76517286b247626ed37dda41a4f946f6c34b8bff /drivers/clk/ux500
parentdb5b0ae00712b5176d7405e7a1dd2bfd6e8f5070 (diff)
parent3f54db784a6af9a6d53396949cbecf62edbad247 (diff)
Merge tag 'multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC multiplatform conversion patches from Olof Johansson: "Here are more patches in the progression towards multiplatform, sparse irq conversions in particular. Tegra has a handful of cleanups and general groundwork, but is not quite there yet on full enablement. Platforms that are enabled through this branch are VT8500 and Zynq. Note that i.MX was converted in one of the earlier cleanup branches as well (before we started a separate topic for multiplatform). And both new platforms for this merge window, sunxi and bcm, were merged with multiplatform support enabled." Fix up conflicts mostly as per Olof. * tag 'multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (29 commits) ARM: zynq: Remove all unused mach headers ARM: zynq: add support for ARCH_MULTIPLATFORM ARM: zynq: make use of debug_ll_io_init() ARM: zynq: remove TTC early mapping ARM: tegra: move debug-macro.S to include/debug ARM: tegra: don't include iomap.h from debug-macro.S ARM: tegra: decouple uncompress.h and debug-macro.S ARM: tegra: simplify DEBUG_LL UART selection options ARM: tegra: select SPARSE_IRQ ARM: tegra: enhance timer.c to get IO address from device tree ARM: tegra: enhance timer.c to get IRQ info from device tree ARM: timer: fix checkpatch warnings ARM: tegra: add TWD to device tree ARM: tegra: define DT bindings for and instantiate RTC ARM: tegra: define DT bindings for and instantiate timer clocksource/mtu-nomadik: use apb_pclk clk: ux500: Register mtu apb_pclocks ARM: plat-nomadik: convert platforms to SPARSE_IRQ mfd/db8500-prcmu: use the irq_domain_add_simple() mfd/ab8500-core: use irq_domain_add_simple() ...
Diffstat (limited to 'drivers/clk/ux500')
-rw-r--r--drivers/clk/ux500/u8500_clk.c11
1 files changed, 4 insertions, 7 deletions
diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
index 7d0e0258f204..6b889a0e90b3 100644
--- a/drivers/clk/ux500/u8500_clk.c
+++ b/drivers/clk/ux500/u8500_clk.c
@@ -12,7 +12,7 @@
12#include <linux/clk-provider.h> 12#include <linux/clk-provider.h>
13#include <linux/mfd/dbx500-prcmu.h> 13#include <linux/mfd/dbx500-prcmu.h>
14#include <linux/platform_data/clk-ux500.h> 14#include <linux/platform_data/clk-ux500.h>
15 15#include <mach/db8500-regs.h>
16#include "clk.h" 16#include "clk.h"
17 17
18void u8500_clk_init(void) 18void u8500_clk_init(void)
@@ -160,12 +160,6 @@ void u8500_clk_init(void)
160 clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT); 160 clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
161 clk_register_clkdev(clk, NULL, "uicc"); 161 clk_register_clkdev(clk, NULL, "uicc");
162 162
163 /*
164 * FIXME: The MTU clocks might need some kind of "parent muxed join"
165 * and these have no K-clocks. For now, we ignore the missing
166 * connection to the corresponding P-clocks, p6_mtu0_clk and
167 * p6_mtu1_clk. Instead timclk is used which is the valid parent.
168 */
169 clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT); 163 clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
170 clk_register_clkdev(clk, NULL, "mtu0"); 164 clk_register_clkdev(clk, NULL, "mtu0");
171 clk_register_clkdev(clk, NULL, "mtu1"); 165 clk_register_clkdev(clk, NULL, "mtu1");
@@ -405,8 +399,11 @@ void u8500_clk_init(void)
405 399
406 clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", U8500_CLKRST6_BASE, 400 clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", U8500_CLKRST6_BASE,
407 BIT(6), 0); 401 BIT(6), 0);
402 clk_register_clkdev(clk, "apb_pclk", "mtu0");
403
408 clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", U8500_CLKRST6_BASE, 404 clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", U8500_CLKRST6_BASE,
409 BIT(7), 0); 405 BIT(7), 0);
406 clk_register_clkdev(clk, "apb_pclk", "mtu1");
410 407
411 /* PRCC K-clocks 408 /* PRCC K-clocks
412 * 409 *