clk: ux500: Support for prcmu_scalable_rate clock

The prcmu_scalable_rate clock can change rate but is not gateable.

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

1 files changed, 17 insertions, 0 deletions

diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c
index 04577ca6a308..74faa7e3cf59 100644
--- a/drivers/clk/ux500/clk-prcmu.c
+++ b/drivers/clk/ux500/clk-prcmu.c
@@ -187,6 +187,13 @@ static struct clk_ops clk_prcmu_gate_ops = {
         .recalc_rate = clk_prcmu_recalc_rate,
 };
 
+static struct clk_ops clk_prcmu_scalable_rate_ops = {
+        .is_enabled = clk_prcmu_is_enabled,
+        .recalc_rate = clk_prcmu_recalc_rate,
+        .round_rate = clk_prcmu_round_rate,
+        .set_rate = clk_prcmu_set_rate,
+};
+
 static struct clk_ops clk_prcmu_rate_ops = {
         .is_enabled = clk_prcmu_is_enabled,
         .recalc_rate = clk_prcmu_recalc_rate,
@@ -278,6 +285,16 @@ struct clk *clk_reg_prcmu_gate(const char *name,
                         &clk_prcmu_gate_ops);
 }
 
+struct clk *clk_reg_prcmu_scalable_rate(const char *name,
+                                        const char *parent_name,
+                                        u8 cg_sel,
+                                        unsigned long rate,
+                                        unsigned long flags)
+{
+        return clk_reg_prcmu(name, parent_name, cg_sel, rate, flags,
+                        &clk_prcmu_scalable_rate_ops);
+}
+
 struct clk *clk_reg_prcmu_rate(const char *name,
                                const char *parent_name,
                                u8 cg_sel,