CLK: TI: DPLL: add support for omap2 core dpll

OMAP2 has slightly different DPLL compared to later OMAP generations. This patch adds support for the ti,omap2-dpll-core-clock and also adds the bindings documentation. Signed-off-by: Tero Kristo <t-kristo@ti.com>
author: Tero Kristo <t-kristo@ti.com> 2014-02-21 10:36:21 -0500
committer: Tero Kristo <t-kristo@ti.com> 2014-05-28 05:28:20 -0400
commit: aa76fcf473f6bfa839f37f77b6fdb71f0fb88d8f (patch)
tree: d8696ea988e4a1e54e6017b31fd8fd268a97a76a /drivers/clk/ti
parent: a6fe3771d389cc660933509b7dfb945c596636f5 (diff)
1 files changed, 67 insertions, 11 deletions
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index dda262db42ea..34e233990212 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -35,21 +35,18 @@ static const struct clk_ops dpll_m4xen_ck_ops = {
        .set_rate       = &omap3_noncore_dpll_set_rate,
        .get_parent     = &omap2_init_dpll_parent,
 };
+#else
+static const struct clk_ops dpll_m4xen_ck_ops = {};
 #endif
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
+        defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \
+        defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 static const struct clk_ops dpll_core_ck_ops = {
        .recalc_rate    = &omap3_dpll_recalc,
        .get_parent     = &omap2_init_dpll_parent,
 };
-#ifdef CONFIG_ARCH_OMAP3
-static const struct clk_ops omap3_dpll_core_ck_ops = {
-        .get_parent     = &omap2_init_dpll_parent,
-        .recalc_rate    = &omap3_dpll_recalc,
-        .round_rate     = &omap2_dpll_round_rate,
-};
-#endif
 static const struct clk_ops dpll_ck_ops = {
        .enable         = &omap3_noncore_dpll_enable,
        .disable        = &omap3_noncore_dpll_disable,
@@ -65,6 +62,33 @@ static const struct clk_ops dpll_no_gate_ck_ops = {
        .round_rate     = &omap2_dpll_round_rate,
        .set_rate       = &omap3_noncore_dpll_set_rate,
 };
+#else
+static const struct clk_ops dpll_core_ck_ops = {};
+static const struct clk_ops dpll_ck_ops = {};
+static const struct clk_ops dpll_no_gate_ck_ops = {};
+const struct clk_hw_omap_ops clkhwops_omap3_dpll = {};
+#endif
+#ifdef CONFIG_ARCH_OMAP2
+static const struct clk_ops omap2_dpll_core_ck_ops = {
+        .get_parent     = &omap2_init_dpll_parent,
+        .recalc_rate    = &omap2_dpllcore_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap2_reprogram_dpllcore,
+};
+#else
+static const struct clk_ops omap2_dpll_core_ck_ops = {};
+#endif
+#ifdef CONFIG_ARCH_OMAP3
+static const struct clk_ops omap3_dpll_core_ck_ops = {
+        .get_parent     = &omap2_init_dpll_parent,
+        .recalc_rate    = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+};
+#else
+static const struct clk_ops omap3_dpll_core_ck_ops = {};
+#endif
 #ifdef CONFIG_ARCH_OMAP3
 static const struct clk_ops omap3_dpll_ck_ops = {
@@ -237,10 +261,27 @@ static void __init of_ti_dpll_setup(struct device_node *node,
        init->parent_names = parent_names;
        dd->control_reg = ti_clk_get_reg_addr(node, 0);
-        dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
-        dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
-        if (!dd->control_reg || !dd->idlest_reg || !dd->mult_div1_reg)
+        /*
+         * Special case for OMAP2 DPLL, register order is different due to
+         * missing idlest_reg, also clkhwops is different. Detected from
+         * missing idlest_mask.
+         */
+        if (!dd->idlest_mask) {
+                dd->mult_div1_reg = ti_clk_get_reg_addr(node, 1);
+#ifdef CONFIG_ARCH_OMAP2
+                clk_hw->ops = &clkhwops_omap2xxx_dpll;
+                omap2xxx_clkt_dpllcore_init(&clk_hw->hw);
+#endif
+        } else {
+                dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
+                if (!dd->idlest_reg)
+                        goto cleanup;
+                dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
+        }
+        if (!dd->control_reg || !dd->mult_div1_reg)
                goto cleanup;
        if (dd->autoidle_mask) {
@@ -547,3 +588,18 @@ static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
 }
 CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
               of_ti_am3_core_dpll_setup);
+static void __init of_ti_omap2_core_dpll_setup(struct device_node *node)
+{
+        const struct dpll_data dd = {
+                .enable_mask = 0x3,
+                .mult_mask = 0x3ff << 12,
+                .div1_mask = 0xf << 8,
+                .max_divider = 16,
+                .min_divider = 1,
+        };
+        of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd);
+}
+CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",
+               of_ti_omap2_core_dpll_setup);
author	Tero Kristo <t-kristo@ti.com>	2014-02-21 10:36:21 -0500
committer	Tero Kristo <t-kristo@ti.com>	2014-05-28 05:28:20 -0400
commit	aa76fcf473f6bfa839f37f77b6fdb71f0fb88d8f (patch)
tree	d8696ea988e4a1e54e6017b31fd8fd268a97a76a /drivers/clk/ti
parent	a6fe3771d389cc660933509b7dfb945c596636f5 (diff)

diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c index dda262db42ea..34e233990212 100644 --- a/drivers/clk/ti/dpll.c +++ b/drivers/clk/ti/dpll.c
@@ -35,21 +35,18 @@ static const struct clk_ops dpll_m4xen_ck_ops = {
35	.set_rate = &omap3_noncore_dpll_set_rate,	35	.set_rate = &omap3_noncore_dpll_set_rate,
36	.get_parent = &omap2_init_dpll_parent,	36	.get_parent = &omap2_init_dpll_parent,
37	};	37	};
		38	#else
		39	static const struct clk_ops dpll_m4xen_ck_ops = {};
38	#endif	40	#endif
39		41
		42	#if defined(CONFIG_ARCH_OMAP3) \|\| defined(CONFIG_ARCH_OMAP4) \|\| \
		43	defined(CONFIG_SOC_OMAP5) \|\| defined(CONFIG_SOC_DRA7XX) \|\| \
		44	defined(CONFIG_SOC_AM33XX) \|\| defined(CONFIG_SOC_AM43XX)
40	static const struct clk_ops dpll_core_ck_ops = {	45	static const struct clk_ops dpll_core_ck_ops = {
41	.recalc_rate = &omap3_dpll_recalc,	46	.recalc_rate = &omap3_dpll_recalc,
42	.get_parent = &omap2_init_dpll_parent,	47	.get_parent = &omap2_init_dpll_parent,
43	};	48	};
44		49
45	#ifdef CONFIG_ARCH_OMAP3
46	static const struct clk_ops omap3_dpll_core_ck_ops = {
47	.get_parent = &omap2_init_dpll_parent,
48	.recalc_rate = &omap3_dpll_recalc,
49	.round_rate = &omap2_dpll_round_rate,
50	};
51	#endif
52
53	static const struct clk_ops dpll_ck_ops = {	50	static const struct clk_ops dpll_ck_ops = {
54	.enable = &omap3_noncore_dpll_enable,	51	.enable = &omap3_noncore_dpll_enable,
55	.disable = &omap3_noncore_dpll_disable,	52	.disable = &omap3_noncore_dpll_disable,
@@ -65,6 +62,33 @@ static const struct clk_ops dpll_no_gate_ck_ops = {
65	.round_rate = &omap2_dpll_round_rate,	62	.round_rate = &omap2_dpll_round_rate,
66	.set_rate = &omap3_noncore_dpll_set_rate,	63	.set_rate = &omap3_noncore_dpll_set_rate,
67	};	64	};
		65	#else
		66	static const struct clk_ops dpll_core_ck_ops = {};
		67	static const struct clk_ops dpll_ck_ops = {};
		68	static const struct clk_ops dpll_no_gate_ck_ops = {};
		69	const struct clk_hw_omap_ops clkhwops_omap3_dpll = {};
		70	#endif
		71
		72	#ifdef CONFIG_ARCH_OMAP2
		73	static const struct clk_ops omap2_dpll_core_ck_ops = {
		74	.get_parent = &omap2_init_dpll_parent,
		75	.recalc_rate = &omap2_dpllcore_recalc,
		76	.round_rate = &omap2_dpll_round_rate,
		77	.set_rate = &omap2_reprogram_dpllcore,
		78	};
		79	#else
		80	static const struct clk_ops omap2_dpll_core_ck_ops = {};
		81	#endif
		82
		83	#ifdef CONFIG_ARCH_OMAP3
		84	static const struct clk_ops omap3_dpll_core_ck_ops = {
		85	.get_parent = &omap2_init_dpll_parent,
		86	.recalc_rate = &omap3_dpll_recalc,
		87	.round_rate = &omap2_dpll_round_rate,
		88	};
		89	#else
		90	static const struct clk_ops omap3_dpll_core_ck_ops = {};
		91	#endif
68		92
69	#ifdef CONFIG_ARCH_OMAP3	93	#ifdef CONFIG_ARCH_OMAP3
70	static const struct clk_ops omap3_dpll_ck_ops = {	94	static const struct clk_ops omap3_dpll_ck_ops = {
@@ -237,10 +261,27 @@ static void __init of_ti_dpll_setup(struct device_node *node,
237	init->parent_names = parent_names;	261	init->parent_names = parent_names;
238		262
239	dd->control_reg = ti_clk_get_reg_addr(node, 0);	263	dd->control_reg = ti_clk_get_reg_addr(node, 0);
240	dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
241	dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
242		264
243	if (!dd->control_reg \|\| !dd->idlest_reg \|\| !dd->mult_div1_reg)	265	/*
		266	* Special case for OMAP2 DPLL, register order is different due to
		267	* missing idlest_reg, also clkhwops is different. Detected from
		268	* missing idlest_mask.
		269	*/
		270	if (!dd->idlest_mask) {
		271	dd->mult_div1_reg = ti_clk_get_reg_addr(node, 1);
		272	#ifdef CONFIG_ARCH_OMAP2
		273	clk_hw->ops = &clkhwops_omap2xxx_dpll;
		274	omap2xxx_clkt_dpllcore_init(&clk_hw->hw);
		275	#endif
		276	} else {
		277	dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
		278	if (!dd->idlest_reg)
		279	goto cleanup;
		280
		281	dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
		282	}
		283
		284	if (!dd->control_reg \|\| !dd->mult_div1_reg)
244	goto cleanup;	285	goto cleanup;
245		286
246	if (dd->autoidle_mask) {	287	if (dd->autoidle_mask) {
@@ -547,3 +588,18 @@ static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
547	}	588	}
548	CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",	589	CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
549	of_ti_am3_core_dpll_setup);	590	of_ti_am3_core_dpll_setup);
		591
		592	static void __init of_ti_omap2_core_dpll_setup(struct device_node *node)
		593	{
		594	const struct dpll_data dd = {
		595	.enable_mask = 0x3,
		596	.mult_mask = 0x3ff << 12,
		597	.div1_mask = 0xf << 8,
		598	.max_divider = 16,
		599	.min_divider = 1,
		600	};
		601
		602	of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd);
		603	}
		604	CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",
		605	of_ti_omap2_core_dpll_setup);