diff options
author | Nishanth Menon <nm@ti.com> | 2014-08-18 12:56:54 -0400 |
---|---|---|
committer | Tero Kristo <t-kristo@ti.com> | 2014-08-21 11:04:16 -0400 |
commit | 2f1032517623b70920d99529e5c87c8c680ab8bf (patch) | |
tree | e69dbbf4e0bf9b0ceb07591eea328945936e1531 /drivers/clk/ti | |
parent | 7d1311b93e58ed55f3a31cc8f94c4b8fe988a2b9 (diff) |
clk: ti: divider: Provide error check for incoming parameters in set_rate
Check for valid parameters in check rate. Else, we end up getting errors
like:
[ 0.000000] Division by zero in kernel.
[ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.17.0-rc1 #1
[ 0.000000] [<c0015160>] (unwind_backtrace) from [<c0011978>] (show_stack+0x10/0x14)
[ 0.000000] [<c0011978>] (show_stack) from [<c055f5f4>] (dump_stack+0x78/0x94)
[ 0.000000] [<c055f5f4>] (dump_stack) from [<c02e17cc>] (Ldiv0+0x8/0x10)
[ 0.000000] [<c02e17cc>] (Ldiv0) from [<c047d228>] (ti_clk_divider_set_rate+0x14/0x14c)
[ 0.000000] [<c047d228>] (ti_clk_divider_set_rate) from [<c047a938>] (clk_change_rate+0x138/0x180)
[ 0.000000] [<c047a938>] (clk_change_rate) from [<c047a908>] (clk_change_rate+0x108/0x180)
This occurs as part of the inital clock tree update of child clock nodes
where new_rate could be 0 for non functional clocks.
Fixes: b4761198bfaf296 ("CLK: ti: add support for ti divider-clock")
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'drivers/clk/ti')
-rw-r--r-- | drivers/clk/ti/divider.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c index e6aa10db7bba..a837f703be65 100644 --- a/drivers/clk/ti/divider.c +++ b/drivers/clk/ti/divider.c | |||
@@ -211,11 +211,16 @@ static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, | |||
211 | static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, | 211 | static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, |
212 | unsigned long parent_rate) | 212 | unsigned long parent_rate) |
213 | { | 213 | { |
214 | struct clk_divider *divider = to_clk_divider(hw); | 214 | struct clk_divider *divider; |
215 | unsigned int div, value; | 215 | unsigned int div, value; |
216 | unsigned long flags = 0; | 216 | unsigned long flags = 0; |
217 | u32 val; | 217 | u32 val; |
218 | 218 | ||
219 | if (!hw || !rate) | ||
220 | return -EINVAL; | ||
221 | |||
222 | divider = to_clk_divider(hw); | ||
223 | |||
219 | div = DIV_ROUND_UP(parent_rate, rate); | 224 | div = DIV_ROUND_UP(parent_rate, rate); |
220 | value = _get_val(divider, div); | 225 | value = _get_val(divider, div); |
221 | 226 | ||