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authorLinus Torvalds <torvalds@linux-foundation.org>2013-05-04 15:31:18 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-05-04 15:31:18 -0400
commit6fa52ed33bea997374a88dbacbba5bf8c7ac4fef (patch)
treea0904b78d66c9b99d6acf944cf58bcaa0cffc511 /drivers/clk/tegra/clk-tegra30.c
parent1db772216f48978d5146b858586f6178433aad38 (diff)
parentbc8fd900c4d460b4e4bf785bb48bfced0ac9941b (diff)
Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver changes from Olof Johansson: "This is a rather large set of patches for device drivers that for one reason or another the subsystem maintainer preferred to get merged through the arm-soc tree. There are both new drivers as well as existing drivers that are getting converted from platform-specific code into standalone drivers using the appropriate subsystem specific interfaces. In particular, we can now have pinctrl, clk, clksource and irqchip drivers in one file per driver, without the need to call into platform specific interface, or to get called from platform specific code, as long as all information about the hardware is provided through a device tree. Most of the drivers we touch this time are for clocksource. Since now most of them are part of drivers/clocksource, I expect that we won't have to touch these again from arm-soc and can let the clocksource maintainers take care of these in the future. Another larger part of this series is specific to the exynos platform, which is seeing some significant effort in upstreaming and modernization of its device drivers this time around, which unfortunately is also the cause for the churn and a lot of the merge conflicts. There is one new subsystem that gets merged as part of this series: the reset controller interface, which is a very simple interface for taking devices on the SoC out of reset or back into reset. Patches to use this interface on i.MX follow later in this merge window, and we are going to have other platforms (at least tegra and sirf) get converted in 3.11. This will let us get rid of platform specific callbacks in a number of platform independent device drivers." * tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (256 commits) irqchip: s3c24xx: add missing __init annotations ARM: dts: Disable the RTC by default on exynos5 clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3} ARM: exynos: restore mach/regs-clock.h for exynos5 clocksource: exynos_mct: fix build error on non-DT pinctrl: vt8500: wmt: Fix checking return value of pinctrl_register() irqchip: vt8500: Convert arch-vt8500 to new irqchip infrastructure reset: NULL deref on allocation failure reset: Add reset controller API dt: describe base reset signal binding ARM: EXYNOS: Add arm-pmu DT binding for exynos421x ARM: EXYNOS: Add arm-pmu DT binding for exynos5250 ARM: EXYNOS: Enable PMUs for exynos4 irqchip: exynos-combiner: Correct combined IRQs for exynos4 irqchip: exynos-combiner: Add set_irq_affinity function for combiner_irq ARM: EXYNOS: fix compilation error introduced due to common clock migration clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3} clk: exynos4: export clocks required for fimc-is clk: samsung: Fix compilation error clk: tegra: fix enum tegra114_clk to match binding ...
Diffstat (limited to 'drivers/clk/tegra/clk-tegra30.c')
-rw-r--r--drivers/clk/tegra/clk-tegra30.c276
1 files changed, 145 insertions, 131 deletions
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index f15f147d473c..c6921f538e28 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -115,8 +115,8 @@
115#define PLLDU_MISC_LOCK_ENABLE 22 115#define PLLDU_MISC_LOCK_ENABLE 22
116#define PLLE_MISC_LOCK_ENABLE 9 116#define PLLE_MISC_LOCK_ENABLE 9
117 117
118#define PLL_BASE_LOCK 27 118#define PLL_BASE_LOCK BIT(27)
119#define PLLE_MISC_LOCK 11 119#define PLLE_MISC_LOCK BIT(11)
120 120
121#define PLLE_AUX 0x48c 121#define PLLE_AUX 0x48c
122#define PLLC_OUT 0x84 122#define PLLC_OUT 0x84
@@ -329,7 +329,7 @@ enum tegra30_clk {
329 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3, 329 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
330 pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow, 330 pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow,
331 dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92, 331 dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92,
332 cdev1, cdev2, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4, 332 cdev2, cdev1, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4,
333 i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x, 333 i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x,
334 atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x, 334 atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x,
335 spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda, 335 spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda,
@@ -373,164 +373,170 @@ static const struct utmi_clk_param utmi_parameters[] = {
373}; 373};
374 374
375static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 375static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
376 { 12000000, 1040000000, 520, 6, 1, 8}, 376 { 12000000, 1040000000, 520, 6, 0, 8},
377 { 13000000, 1040000000, 480, 6, 1, 8}, 377 { 13000000, 1040000000, 480, 6, 0, 8},
378 { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */ 378 { 16800000, 1040000000, 495, 8, 0, 8}, /* actual: 1039.5 MHz */
379 { 19200000, 1040000000, 325, 6, 1, 6}, 379 { 19200000, 1040000000, 325, 6, 0, 6},
380 { 26000000, 1040000000, 520, 13, 1, 8}, 380 { 26000000, 1040000000, 520, 13, 0, 8},
381 381
382 { 12000000, 832000000, 416, 6, 1, 8}, 382 { 12000000, 832000000, 416, 6, 0, 8},
383 { 13000000, 832000000, 832, 13, 1, 8}, 383 { 13000000, 832000000, 832, 13, 0, 8},
384 { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */ 384 { 16800000, 832000000, 396, 8, 0, 8}, /* actual: 831.6 MHz */
385 { 19200000, 832000000, 260, 6, 1, 8}, 385 { 19200000, 832000000, 260, 6, 0, 8},
386 { 26000000, 832000000, 416, 13, 1, 8}, 386 { 26000000, 832000000, 416, 13, 0, 8},
387 387
388 { 12000000, 624000000, 624, 12, 1, 8}, 388 { 12000000, 624000000, 624, 12, 0, 8},
389 { 13000000, 624000000, 624, 13, 1, 8}, 389 { 13000000, 624000000, 624, 13, 0, 8},
390 { 16800000, 600000000, 520, 14, 1, 8}, 390 { 16800000, 600000000, 520, 14, 0, 8},
391 { 19200000, 624000000, 520, 16, 1, 8}, 391 { 19200000, 624000000, 520, 16, 0, 8},
392 { 26000000, 624000000, 624, 26, 1, 8}, 392 { 26000000, 624000000, 624, 26, 0, 8},
393 393
394 { 12000000, 600000000, 600, 12, 1, 8}, 394 { 12000000, 600000000, 600, 12, 0, 8},
395 { 13000000, 600000000, 600, 13, 1, 8}, 395 { 13000000, 600000000, 600, 13, 0, 8},
396 { 16800000, 600000000, 500, 14, 1, 8}, 396 { 16800000, 600000000, 500, 14, 0, 8},
397 { 19200000, 600000000, 375, 12, 1, 6}, 397 { 19200000, 600000000, 375, 12, 0, 6},
398 { 26000000, 600000000, 600, 26, 1, 8}, 398 { 26000000, 600000000, 600, 26, 0, 8},
399 399
400 { 12000000, 520000000, 520, 12, 1, 8}, 400 { 12000000, 520000000, 520, 12, 0, 8},
401 { 13000000, 520000000, 520, 13, 1, 8}, 401 { 13000000, 520000000, 520, 13, 0, 8},
402 { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */ 402 { 16800000, 520000000, 495, 16, 0, 8}, /* actual: 519.75 MHz */
403 { 19200000, 520000000, 325, 12, 1, 6}, 403 { 19200000, 520000000, 325, 12, 0, 6},
404 { 26000000, 520000000, 520, 26, 1, 8}, 404 { 26000000, 520000000, 520, 26, 0, 8},
405 405
406 { 12000000, 416000000, 416, 12, 1, 8}, 406 { 12000000, 416000000, 416, 12, 0, 8},
407 { 13000000, 416000000, 416, 13, 1, 8}, 407 { 13000000, 416000000, 416, 13, 0, 8},
408 { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */ 408 { 16800000, 416000000, 396, 16, 0, 8}, /* actual: 415.8 MHz */
409 { 19200000, 416000000, 260, 12, 1, 6}, 409 { 19200000, 416000000, 260, 12, 0, 6},
410 { 26000000, 416000000, 416, 26, 1, 8}, 410 { 26000000, 416000000, 416, 26, 0, 8},
411 { 0, 0, 0, 0, 0, 0 }, 411 { 0, 0, 0, 0, 0, 0 },
412}; 412};
413 413
414static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 414static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
415 { 12000000, 666000000, 666, 12, 1, 8}, 415 { 12000000, 666000000, 666, 12, 0, 8},
416 { 13000000, 666000000, 666, 13, 1, 8}, 416 { 13000000, 666000000, 666, 13, 0, 8},
417 { 16800000, 666000000, 555, 14, 1, 8}, 417 { 16800000, 666000000, 555, 14, 0, 8},
418 { 19200000, 666000000, 555, 16, 1, 8}, 418 { 19200000, 666000000, 555, 16, 0, 8},
419 { 26000000, 666000000, 666, 26, 1, 8}, 419 { 26000000, 666000000, 666, 26, 0, 8},
420 { 12000000, 600000000, 600, 12, 1, 8}, 420 { 12000000, 600000000, 600, 12, 0, 8},
421 { 13000000, 600000000, 600, 13, 1, 8}, 421 { 13000000, 600000000, 600, 13, 0, 8},
422 { 16800000, 600000000, 500, 14, 1, 8}, 422 { 16800000, 600000000, 500, 14, 0, 8},
423 { 19200000, 600000000, 375, 12, 1, 6}, 423 { 19200000, 600000000, 375, 12, 0, 6},
424 { 26000000, 600000000, 600, 26, 1, 8}, 424 { 26000000, 600000000, 600, 26, 0, 8},
425 { 0, 0, 0, 0, 0, 0 }, 425 { 0, 0, 0, 0, 0, 0 },
426}; 426};
427 427
428static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 428static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
429 { 12000000, 216000000, 432, 12, 2, 8}, 429 { 12000000, 216000000, 432, 12, 1, 8},
430 { 13000000, 216000000, 432, 13, 2, 8}, 430 { 13000000, 216000000, 432, 13, 1, 8},
431 { 16800000, 216000000, 360, 14, 2, 8}, 431 { 16800000, 216000000, 360, 14, 1, 8},
432 { 19200000, 216000000, 360, 16, 2, 8}, 432 { 19200000, 216000000, 360, 16, 1, 8},
433 { 26000000, 216000000, 432, 26, 2, 8}, 433 { 26000000, 216000000, 432, 26, 1, 8},
434 { 0, 0, 0, 0, 0, 0 }, 434 { 0, 0, 0, 0, 0, 0 },
435}; 435};
436 436
437static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 437static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
438 { 9600000, 564480000, 294, 5, 1, 4}, 438 { 9600000, 564480000, 294, 5, 0, 4},
439 { 9600000, 552960000, 288, 5, 1, 4}, 439 { 9600000, 552960000, 288, 5, 0, 4},
440 { 9600000, 24000000, 5, 2, 1, 1}, 440 { 9600000, 24000000, 5, 2, 0, 1},
441 441
442 { 28800000, 56448000, 49, 25, 1, 1}, 442 { 28800000, 56448000, 49, 25, 0, 1},
443 { 28800000, 73728000, 64, 25, 1, 1}, 443 { 28800000, 73728000, 64, 25, 0, 1},
444 { 28800000, 24000000, 5, 6, 1, 1}, 444 { 28800000, 24000000, 5, 6, 0, 1},
445 { 0, 0, 0, 0, 0, 0 }, 445 { 0, 0, 0, 0, 0, 0 },
446}; 446};
447 447
448static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 448static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
449 { 12000000, 216000000, 216, 12, 1, 4}, 449 { 12000000, 216000000, 216, 12, 0, 4},
450 { 13000000, 216000000, 216, 13, 1, 4}, 450 { 13000000, 216000000, 216, 13, 0, 4},
451 { 16800000, 216000000, 180, 14, 1, 4}, 451 { 16800000, 216000000, 180, 14, 0, 4},
452 { 19200000, 216000000, 180, 16, 1, 4}, 452 { 19200000, 216000000, 180, 16, 0, 4},
453 { 26000000, 216000000, 216, 26, 1, 4}, 453 { 26000000, 216000000, 216, 26, 0, 4},
454 454
455 { 12000000, 594000000, 594, 12, 1, 8}, 455 { 12000000, 594000000, 594, 12, 0, 8},
456 { 13000000, 594000000, 594, 13, 1, 8}, 456 { 13000000, 594000000, 594, 13, 0, 8},
457 { 16800000, 594000000, 495, 14, 1, 8}, 457 { 16800000, 594000000, 495, 14, 0, 8},
458 { 19200000, 594000000, 495, 16, 1, 8}, 458 { 19200000, 594000000, 495, 16, 0, 8},
459 { 26000000, 594000000, 594, 26, 1, 8}, 459 { 26000000, 594000000, 594, 26, 0, 8},
460 460
461 { 12000000, 1000000000, 1000, 12, 1, 12}, 461 { 12000000, 1000000000, 1000, 12, 0, 12},
462 { 13000000, 1000000000, 1000, 13, 1, 12}, 462 { 13000000, 1000000000, 1000, 13, 0, 12},
463 { 19200000, 1000000000, 625, 12, 1, 8}, 463 { 19200000, 1000000000, 625, 12, 0, 8},
464 { 26000000, 1000000000, 1000, 26, 1, 12}, 464 { 26000000, 1000000000, 1000, 26, 0, 12},
465 465
466 { 0, 0, 0, 0, 0, 0 }, 466 { 0, 0, 0, 0, 0, 0 },
467}; 467};
468 468
469static struct pdiv_map pllu_p[] = {
470 { .pdiv = 1, .hw_val = 1 },
471 { .pdiv = 2, .hw_val = 0 },
472 { .pdiv = 0, .hw_val = 0 },
473};
474
469static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 475static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
470 { 12000000, 480000000, 960, 12, 2, 12}, 476 { 12000000, 480000000, 960, 12, 0, 12},
471 { 13000000, 480000000, 960, 13, 2, 12}, 477 { 13000000, 480000000, 960, 13, 0, 12},
472 { 16800000, 480000000, 400, 7, 2, 5}, 478 { 16800000, 480000000, 400, 7, 0, 5},
473 { 19200000, 480000000, 200, 4, 2, 3}, 479 { 19200000, 480000000, 200, 4, 0, 3},
474 { 26000000, 480000000, 960, 26, 2, 12}, 480 { 26000000, 480000000, 960, 26, 0, 12},
475 { 0, 0, 0, 0, 0, 0 }, 481 { 0, 0, 0, 0, 0, 0 },
476}; 482};
477 483
478static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 484static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
479 /* 1.7 GHz */ 485 /* 1.7 GHz */
480 { 12000000, 1700000000, 850, 6, 1, 8}, 486 { 12000000, 1700000000, 850, 6, 0, 8},
481 { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */ 487 { 13000000, 1700000000, 915, 7, 0, 8}, /* actual: 1699.2 MHz */
482 { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */ 488 { 16800000, 1700000000, 708, 7, 0, 8}, /* actual: 1699.2 MHz */
483 { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */ 489 { 19200000, 1700000000, 885, 10, 0, 8}, /* actual: 1699.2 MHz */
484 { 26000000, 1700000000, 850, 13, 1, 8}, 490 { 26000000, 1700000000, 850, 13, 0, 8},
485 491
486 /* 1.6 GHz */ 492 /* 1.6 GHz */
487 { 12000000, 1600000000, 800, 6, 1, 8}, 493 { 12000000, 1600000000, 800, 6, 0, 8},
488 { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */ 494 { 13000000, 1600000000, 738, 6, 0, 8}, /* actual: 1599.0 MHz */
489 { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */ 495 { 16800000, 1600000000, 857, 9, 0, 8}, /* actual: 1599.7 MHz */
490 { 19200000, 1600000000, 500, 6, 1, 8}, 496 { 19200000, 1600000000, 500, 6, 0, 8},
491 { 26000000, 1600000000, 800, 13, 1, 8}, 497 { 26000000, 1600000000, 800, 13, 0, 8},
492 498
493 /* 1.5 GHz */ 499 /* 1.5 GHz */
494 { 12000000, 1500000000, 750, 6, 1, 8}, 500 { 12000000, 1500000000, 750, 6, 0, 8},
495 { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */ 501 { 13000000, 1500000000, 923, 8, 0, 8}, /* actual: 1499.8 MHz */
496 { 16800000, 1500000000, 625, 7, 1, 8}, 502 { 16800000, 1500000000, 625, 7, 0, 8},
497 { 19200000, 1500000000, 625, 8, 1, 8}, 503 { 19200000, 1500000000, 625, 8, 0, 8},
498 { 26000000, 1500000000, 750, 13, 1, 8}, 504 { 26000000, 1500000000, 750, 13, 0, 8},
499 505
500 /* 1.4 GHz */ 506 /* 1.4 GHz */
501 { 12000000, 1400000000, 700, 6, 1, 8}, 507 { 12000000, 1400000000, 700, 6, 0, 8},
502 { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */ 508 { 13000000, 1400000000, 969, 9, 0, 8}, /* actual: 1399.7 MHz */
503 { 16800000, 1400000000, 1000, 12, 1, 8}, 509 { 16800000, 1400000000, 1000, 12, 0, 8},
504 { 19200000, 1400000000, 875, 12, 1, 8}, 510 { 19200000, 1400000000, 875, 12, 0, 8},
505 { 26000000, 1400000000, 700, 13, 1, 8}, 511 { 26000000, 1400000000, 700, 13, 0, 8},
506 512
507 /* 1.3 GHz */ 513 /* 1.3 GHz */
508 { 12000000, 1300000000, 975, 9, 1, 8}, 514 { 12000000, 1300000000, 975, 9, 0, 8},
509 { 13000000, 1300000000, 1000, 10, 1, 8}, 515 { 13000000, 1300000000, 1000, 10, 0, 8},
510 { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */ 516 { 16800000, 1300000000, 928, 12, 0, 8}, /* actual: 1299.2 MHz */
511 { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */ 517 { 19200000, 1300000000, 812, 12, 0, 8}, /* actual: 1299.2 MHz */
512 { 26000000, 1300000000, 650, 13, 1, 8}, 518 { 26000000, 1300000000, 650, 13, 0, 8},
513 519
514 /* 1.2 GHz */ 520 /* 1.2 GHz */
515 { 12000000, 1200000000, 1000, 10, 1, 8}, 521 { 12000000, 1200000000, 1000, 10, 0, 8},
516 { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */ 522 { 13000000, 1200000000, 923, 10, 0, 8}, /* actual: 1199.9 MHz */
517 { 16800000, 1200000000, 1000, 14, 1, 8}, 523 { 16800000, 1200000000, 1000, 14, 0, 8},
518 { 19200000, 1200000000, 1000, 16, 1, 8}, 524 { 19200000, 1200000000, 1000, 16, 0, 8},
519 { 26000000, 1200000000, 600, 13, 1, 8}, 525 { 26000000, 1200000000, 600, 13, 0, 8},
520 526
521 /* 1.1 GHz */ 527 /* 1.1 GHz */
522 { 12000000, 1100000000, 825, 9, 1, 8}, 528 { 12000000, 1100000000, 825, 9, 0, 8},
523 { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */ 529 { 13000000, 1100000000, 846, 10, 0, 8}, /* actual: 1099.8 MHz */
524 { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */ 530 { 16800000, 1100000000, 982, 15, 0, 8}, /* actual: 1099.8 MHz */
525 { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */ 531 { 19200000, 1100000000, 859, 15, 0, 8}, /* actual: 1099.5 MHz */
526 { 26000000, 1100000000, 550, 13, 1, 8}, 532 { 26000000, 1100000000, 550, 13, 0, 8},
527 533
528 /* 1 GHz */ 534 /* 1 GHz */
529 { 12000000, 1000000000, 1000, 12, 1, 8}, 535 { 12000000, 1000000000, 1000, 12, 0, 8},
530 { 13000000, 1000000000, 1000, 13, 1, 8}, 536 { 13000000, 1000000000, 1000, 13, 0, 8},
531 { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */ 537 { 16800000, 1000000000, 833, 14, 0, 8}, /* actual: 999.6 MHz */
532 { 19200000, 1000000000, 625, 12, 1, 8}, 538 { 19200000, 1000000000, 625, 12, 0, 8},
533 { 26000000, 1000000000, 1000, 26, 1, 8}, 539 { 26000000, 1000000000, 1000, 26, 0, 8},
534 540
535 { 0, 0, 0, 0, 0, 0 }, 541 { 0, 0, 0, 0, 0, 0 },
536}; 542};
@@ -552,7 +558,7 @@ static struct tegra_clk_pll_params pll_c_params = {
552 .vco_max = 1400000000, 558 .vco_max = 1400000000,
553 .base_reg = PLLC_BASE, 559 .base_reg = PLLC_BASE,
554 .misc_reg = PLLC_MISC, 560 .misc_reg = PLLC_MISC,
555 .lock_bit_idx = PLL_BASE_LOCK, 561 .lock_mask = PLL_BASE_LOCK,
556 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 562 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
557 .lock_delay = 300, 563 .lock_delay = 300,
558}; 564};
@@ -566,7 +572,7 @@ static struct tegra_clk_pll_params pll_m_params = {
566 .vco_max = 1200000000, 572 .vco_max = 1200000000,
567 .base_reg = PLLM_BASE, 573 .base_reg = PLLM_BASE,
568 .misc_reg = PLLM_MISC, 574 .misc_reg = PLLM_MISC,
569 .lock_bit_idx = PLL_BASE_LOCK, 575 .lock_mask = PLL_BASE_LOCK,
570 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 576 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
571 .lock_delay = 300, 577 .lock_delay = 300,
572}; 578};
@@ -580,7 +586,7 @@ static struct tegra_clk_pll_params pll_p_params = {
580 .vco_max = 1400000000, 586 .vco_max = 1400000000,
581 .base_reg = PLLP_BASE, 587 .base_reg = PLLP_BASE,
582 .misc_reg = PLLP_MISC, 588 .misc_reg = PLLP_MISC,
583 .lock_bit_idx = PLL_BASE_LOCK, 589 .lock_mask = PLL_BASE_LOCK,
584 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 590 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
585 .lock_delay = 300, 591 .lock_delay = 300,
586}; 592};
@@ -594,7 +600,7 @@ static struct tegra_clk_pll_params pll_a_params = {
594 .vco_max = 1400000000, 600 .vco_max = 1400000000,
595 .base_reg = PLLA_BASE, 601 .base_reg = PLLA_BASE,
596 .misc_reg = PLLA_MISC, 602 .misc_reg = PLLA_MISC,
597 .lock_bit_idx = PLL_BASE_LOCK, 603 .lock_mask = PLL_BASE_LOCK,
598 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 604 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
599 .lock_delay = 300, 605 .lock_delay = 300,
600}; 606};
@@ -608,7 +614,7 @@ static struct tegra_clk_pll_params pll_d_params = {
608 .vco_max = 1000000000, 614 .vco_max = 1000000000,
609 .base_reg = PLLD_BASE, 615 .base_reg = PLLD_BASE,
610 .misc_reg = PLLD_MISC, 616 .misc_reg = PLLD_MISC,
611 .lock_bit_idx = PLL_BASE_LOCK, 617 .lock_mask = PLL_BASE_LOCK,
612 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 618 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
613 .lock_delay = 1000, 619 .lock_delay = 1000,
614}; 620};
@@ -622,7 +628,7 @@ static struct tegra_clk_pll_params pll_d2_params = {
622 .vco_max = 1000000000, 628 .vco_max = 1000000000,
623 .base_reg = PLLD2_BASE, 629 .base_reg = PLLD2_BASE,
624 .misc_reg = PLLD2_MISC, 630 .misc_reg = PLLD2_MISC,
625 .lock_bit_idx = PLL_BASE_LOCK, 631 .lock_mask = PLL_BASE_LOCK,
626 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 632 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
627 .lock_delay = 1000, 633 .lock_delay = 1000,
628}; 634};
@@ -636,9 +642,10 @@ static struct tegra_clk_pll_params pll_u_params = {
636 .vco_max = 960000000, 642 .vco_max = 960000000,
637 .base_reg = PLLU_BASE, 643 .base_reg = PLLU_BASE,
638 .misc_reg = PLLU_MISC, 644 .misc_reg = PLLU_MISC,
639 .lock_bit_idx = PLL_BASE_LOCK, 645 .lock_mask = PLL_BASE_LOCK,
640 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 646 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
641 .lock_delay = 1000, 647 .lock_delay = 1000,
648 .pdiv_tohw = pllu_p,
642}; 649};
643 650
644static struct tegra_clk_pll_params pll_x_params = { 651static struct tegra_clk_pll_params pll_x_params = {
@@ -650,7 +657,7 @@ static struct tegra_clk_pll_params pll_x_params = {
650 .vco_max = 1700000000, 657 .vco_max = 1700000000,
651 .base_reg = PLLX_BASE, 658 .base_reg = PLLX_BASE,
652 .misc_reg = PLLX_MISC, 659 .misc_reg = PLLX_MISC,
653 .lock_bit_idx = PLL_BASE_LOCK, 660 .lock_mask = PLL_BASE_LOCK,
654 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 661 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
655 .lock_delay = 300, 662 .lock_delay = 300,
656}; 663};
@@ -664,7 +671,7 @@ static struct tegra_clk_pll_params pll_e_params = {
664 .vco_max = 2400000000U, 671 .vco_max = 2400000000U,
665 .base_reg = PLLE_BASE, 672 .base_reg = PLLE_BASE,
666 .misc_reg = PLLE_MISC, 673 .misc_reg = PLLE_MISC,
667 .lock_bit_idx = PLLE_MISC_LOCK, 674 .lock_mask = PLLE_MISC_LOCK,
668 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 675 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
669 .lock_delay = 300, 676 .lock_delay = 300,
670}; 677};
@@ -1660,7 +1667,7 @@ static void __init tegra30_periph_clk_init(void)
1660 data = &tegra_periph_clk_list[i]; 1667 data = &tegra_periph_clk_list[i];
1661 clk = tegra_clk_register_periph(data->name, data->parent_names, 1668 clk = tegra_clk_register_periph(data->name, data->parent_names,
1662 data->num_parents, &data->periph, 1669 data->num_parents, &data->periph,
1663 clk_base, data->offset); 1670 clk_base, data->offset, data->flags);
1664 clk_register_clkdev(clk, data->con_id, data->dev_id); 1671 clk_register_clkdev(clk, data->con_id, data->dev_id);
1665 clks[data->clk_id] = clk; 1672 clks[data->clk_id] = clk;
1666 } 1673 }
@@ -1910,9 +1917,16 @@ static __initdata struct tegra_clk_init_table init_table[] = {
1910 {disp1, pll_p, 600000000, 0}, 1917 {disp1, pll_p, 600000000, 0},
1911 {disp2, pll_p, 600000000, 0}, 1918 {disp2, pll_p, 600000000, 0},
1912 {twd, clk_max, 0, 1}, 1919 {twd, clk_max, 0, 1},
1920 {gr2d, pll_c, 300000000, 0},
1921 {gr3d, pll_c, 300000000, 0},
1913 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */ 1922 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */
1914}; 1923};
1915 1924
1925static void __init tegra30_clock_apply_init_table(void)
1926{
1927 tegra_init_from_table(init_table, clks, clk_max);
1928}
1929
1916/* 1930/*
1917 * Some clocks may be used by different drivers depending on the board 1931 * Some clocks may be used by different drivers depending on the board
1918 * configuration. List those here to register them twice in the clock lookup 1932 * configuration. List those here to register them twice in the clock lookup
@@ -1986,7 +2000,7 @@ void __init tegra30_clock_init(struct device_node *np)
1986 clk_data.clk_num = ARRAY_SIZE(clks); 2000 clk_data.clk_num = ARRAY_SIZE(clks);
1987 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 2001 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
1988 2002
1989 tegra_init_from_table(init_table, clks, clk_max); 2003 tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
1990 2004
1991 tegra_cpu_car_ops = &tegra30_cpu_car_ops; 2005 tegra_cpu_car_ops = &tegra30_cpu_car_ops;
1992} 2006}