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authorPeter De Schrijver <pdeschrijver@nvidia.com>2013-04-03 10:40:36 -0400
committerStephen Warren <swarren@nvidia.com>2013-04-04 18:10:33 -0400
commitdba4072a4a20b2986562cced98ce04a887614528 (patch)
tree68bfcbd1b984799bed2b75d262abe5789f4d4d40 /drivers/clk/tegra/clk-tegra20.c
parent6a676fa0af4e2bd11ab3950e277e81a959a9a198 (diff)
clk: tegra: Refactor PLL programming code
Refactor the PLL programming code to make it useable by the new PLL types introduced by Tegra114. The following changes were done: * Split programming the PLL into updating m,n,p and updating cpcon * Move locking from _update_pll_cpcon() to clk_pll_set_rate() * Introduce _get_pll_mnp() helper * Move check for identical m,n,p values to clk_pll_set_rate() * struct tegra_clk_pll_freq_table will always contain the values as defined by the hardware. * Simplify the arguments to clk_pll_wait_for_lock() * Split _tegra_clk_register_pll() Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra20.c')
-rw-r--r--drivers/clk/tegra/clk-tegra20.c144
1 files changed, 72 insertions, 72 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index a15fb28197b5..c2a1c4cae47c 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -248,125 +248,125 @@ static struct clk *clks[clk_max];
248static struct clk_onecell_data clk_data; 248static struct clk_onecell_data clk_data;
249 249
250static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 250static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
251 { 12000000, 600000000, 600, 12, 1, 8 }, 251 { 12000000, 600000000, 600, 12, 0, 8 },
252 { 13000000, 600000000, 600, 13, 1, 8 }, 252 { 13000000, 600000000, 600, 13, 0, 8 },
253 { 19200000, 600000000, 500, 16, 1, 6 }, 253 { 19200000, 600000000, 500, 16, 0, 6 },
254 { 26000000, 600000000, 600, 26, 1, 8 }, 254 { 26000000, 600000000, 600, 26, 0, 8 },
255 { 0, 0, 0, 0, 0, 0 }, 255 { 0, 0, 0, 0, 0, 0 },
256}; 256};
257 257
258static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 258static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
259 { 12000000, 666000000, 666, 12, 1, 8}, 259 { 12000000, 666000000, 666, 12, 0, 8},
260 { 13000000, 666000000, 666, 13, 1, 8}, 260 { 13000000, 666000000, 666, 13, 0, 8},
261 { 19200000, 666000000, 555, 16, 1, 8}, 261 { 19200000, 666000000, 555, 16, 0, 8},
262 { 26000000, 666000000, 666, 26, 1, 8}, 262 { 26000000, 666000000, 666, 26, 0, 8},
263 { 12000000, 600000000, 600, 12, 1, 8}, 263 { 12000000, 600000000, 600, 12, 0, 8},
264 { 13000000, 600000000, 600, 13, 1, 8}, 264 { 13000000, 600000000, 600, 13, 0, 8},
265 { 19200000, 600000000, 375, 12, 1, 6}, 265 { 19200000, 600000000, 375, 12, 0, 6},
266 { 26000000, 600000000, 600, 26, 1, 8}, 266 { 26000000, 600000000, 600, 26, 0, 8},
267 { 0, 0, 0, 0, 0, 0 }, 267 { 0, 0, 0, 0, 0, 0 },
268}; 268};
269 269
270static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 270static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
271 { 12000000, 216000000, 432, 12, 2, 8}, 271 { 12000000, 216000000, 432, 12, 1, 8},
272 { 13000000, 216000000, 432, 13, 2, 8}, 272 { 13000000, 216000000, 432, 13, 1, 8},
273 { 19200000, 216000000, 90, 4, 2, 1}, 273 { 19200000, 216000000, 90, 4, 1, 1},
274 { 26000000, 216000000, 432, 26, 2, 8}, 274 { 26000000, 216000000, 432, 26, 1, 8},
275 { 12000000, 432000000, 432, 12, 1, 8}, 275 { 12000000, 432000000, 432, 12, 0, 8},
276 { 13000000, 432000000, 432, 13, 1, 8}, 276 { 13000000, 432000000, 432, 13, 0, 8},
277 { 19200000, 432000000, 90, 4, 1, 1}, 277 { 19200000, 432000000, 90, 4, 0, 1},
278 { 26000000, 432000000, 432, 26, 1, 8}, 278 { 26000000, 432000000, 432, 26, 0, 8},
279 { 0, 0, 0, 0, 0, 0 }, 279 { 0, 0, 0, 0, 0, 0 },
280}; 280};
281 281
282static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 282static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
283 { 28800000, 56448000, 49, 25, 1, 1}, 283 { 28800000, 56448000, 49, 25, 0, 1},
284 { 28800000, 73728000, 64, 25, 1, 1}, 284 { 28800000, 73728000, 64, 25, 0, 1},
285 { 28800000, 24000000, 5, 6, 1, 1}, 285 { 28800000, 24000000, 5, 6, 0, 1},
286 { 0, 0, 0, 0, 0, 0 }, 286 { 0, 0, 0, 0, 0, 0 },
287}; 287};
288 288
289static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 289static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
290 { 12000000, 216000000, 216, 12, 1, 4}, 290 { 12000000, 216000000, 216, 12, 0, 4},
291 { 13000000, 216000000, 216, 13, 1, 4}, 291 { 13000000, 216000000, 216, 13, 0, 4},
292 { 19200000, 216000000, 135, 12, 1, 3}, 292 { 19200000, 216000000, 135, 12, 0, 3},
293 { 26000000, 216000000, 216, 26, 1, 4}, 293 { 26000000, 216000000, 216, 26, 0, 4},
294 294
295 { 12000000, 594000000, 594, 12, 1, 8}, 295 { 12000000, 594000000, 594, 12, 0, 8},
296 { 13000000, 594000000, 594, 13, 1, 8}, 296 { 13000000, 594000000, 594, 13, 0, 8},
297 { 19200000, 594000000, 495, 16, 1, 8}, 297 { 19200000, 594000000, 495, 16, 0, 8},
298 { 26000000, 594000000, 594, 26, 1, 8}, 298 { 26000000, 594000000, 594, 26, 0, 8},
299 299
300 { 12000000, 1000000000, 1000, 12, 1, 12}, 300 { 12000000, 1000000000, 1000, 12, 0, 12},
301 { 13000000, 1000000000, 1000, 13, 1, 12}, 301 { 13000000, 1000000000, 1000, 13, 0, 12},
302 { 19200000, 1000000000, 625, 12, 1, 8}, 302 { 19200000, 1000000000, 625, 12, 0, 8},
303 { 26000000, 1000000000, 1000, 26, 1, 12}, 303 { 26000000, 1000000000, 1000, 26, 0, 12},
304 304
305 { 0, 0, 0, 0, 0, 0 }, 305 { 0, 0, 0, 0, 0, 0 },
306}; 306};
307 307
308static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 308static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
309 { 12000000, 480000000, 960, 12, 2, 0}, 309 { 12000000, 480000000, 960, 12, 0, 0},
310 { 13000000, 480000000, 960, 13, 2, 0}, 310 { 13000000, 480000000, 960, 13, 0, 0},
311 { 19200000, 480000000, 200, 4, 2, 0}, 311 { 19200000, 480000000, 200, 4, 0, 0},
312 { 26000000, 480000000, 960, 26, 2, 0}, 312 { 26000000, 480000000, 960, 26, 0, 0},
313 { 0, 0, 0, 0, 0, 0 }, 313 { 0, 0, 0, 0, 0, 0 },
314}; 314};
315 315
316static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 316static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
317 /* 1 GHz */ 317 /* 1 GHz */
318 { 12000000, 1000000000, 1000, 12, 1, 12}, 318 { 12000000, 1000000000, 1000, 12, 0, 12},
319 { 13000000, 1000000000, 1000, 13, 1, 12}, 319 { 13000000, 1000000000, 1000, 13, 0, 12},
320 { 19200000, 1000000000, 625, 12, 1, 8}, 320 { 19200000, 1000000000, 625, 12, 0, 8},
321 { 26000000, 1000000000, 1000, 26, 1, 12}, 321 { 26000000, 1000000000, 1000, 26, 0, 12},
322 322
323 /* 912 MHz */ 323 /* 912 MHz */
324 { 12000000, 912000000, 912, 12, 1, 12}, 324 { 12000000, 912000000, 912, 12, 0, 12},
325 { 13000000, 912000000, 912, 13, 1, 12}, 325 { 13000000, 912000000, 912, 13, 0, 12},
326 { 19200000, 912000000, 760, 16, 1, 8}, 326 { 19200000, 912000000, 760, 16, 0, 8},
327 { 26000000, 912000000, 912, 26, 1, 12}, 327 { 26000000, 912000000, 912, 26, 0, 12},
328 328
329 /* 816 MHz */ 329 /* 816 MHz */
330 { 12000000, 816000000, 816, 12, 1, 12}, 330 { 12000000, 816000000, 816, 12, 0, 12},
331 { 13000000, 816000000, 816, 13, 1, 12}, 331 { 13000000, 816000000, 816, 13, 0, 12},
332 { 19200000, 816000000, 680, 16, 1, 8}, 332 { 19200000, 816000000, 680, 16, 0, 8},
333 { 26000000, 816000000, 816, 26, 1, 12}, 333 { 26000000, 816000000, 816, 26, 0, 12},
334 334
335 /* 760 MHz */ 335 /* 760 MHz */
336 { 12000000, 760000000, 760, 12, 1, 12}, 336 { 12000000, 760000000, 760, 12, 0, 12},
337 { 13000000, 760000000, 760, 13, 1, 12}, 337 { 13000000, 760000000, 760, 13, 0, 12},
338 { 19200000, 760000000, 950, 24, 1, 8}, 338 { 19200000, 760000000, 950, 24, 0, 8},
339 { 26000000, 760000000, 760, 26, 1, 12}, 339 { 26000000, 760000000, 760, 26, 0, 12},
340 340
341 /* 750 MHz */ 341 /* 750 MHz */
342 { 12000000, 750000000, 750, 12, 1, 12}, 342 { 12000000, 750000000, 750, 12, 0, 12},
343 { 13000000, 750000000, 750, 13, 1, 12}, 343 { 13000000, 750000000, 750, 13, 0, 12},
344 { 19200000, 750000000, 625, 16, 1, 8}, 344 { 19200000, 750000000, 625, 16, 0, 8},
345 { 26000000, 750000000, 750, 26, 1, 12}, 345 { 26000000, 750000000, 750, 26, 0, 12},
346 346
347 /* 608 MHz */ 347 /* 608 MHz */
348 { 12000000, 608000000, 608, 12, 1, 12}, 348 { 12000000, 608000000, 608, 12, 0, 12},
349 { 13000000, 608000000, 608, 13, 1, 12}, 349 { 13000000, 608000000, 608, 13, 0, 12},
350 { 19200000, 608000000, 380, 12, 1, 8}, 350 { 19200000, 608000000, 380, 12, 0, 8},
351 { 26000000, 608000000, 608, 26, 1, 12}, 351 { 26000000, 608000000, 608, 26, 0, 12},
352 352
353 /* 456 MHz */ 353 /* 456 MHz */
354 { 12000000, 456000000, 456, 12, 1, 12}, 354 { 12000000, 456000000, 456, 12, 0, 12},
355 { 13000000, 456000000, 456, 13, 1, 12}, 355 { 13000000, 456000000, 456, 13, 0, 12},
356 { 19200000, 456000000, 380, 16, 1, 8}, 356 { 19200000, 456000000, 380, 16, 0, 8},
357 { 26000000, 456000000, 456, 26, 1, 12}, 357 { 26000000, 456000000, 456, 26, 0, 12},
358 358
359 /* 312 MHz */ 359 /* 312 MHz */
360 { 12000000, 312000000, 312, 12, 1, 12}, 360 { 12000000, 312000000, 312, 12, 0, 12},
361 { 13000000, 312000000, 312, 13, 1, 12}, 361 { 13000000, 312000000, 312, 13, 0, 12},
362 { 19200000, 312000000, 260, 16, 1, 8}, 362 { 19200000, 312000000, 260, 16, 0, 8},
363 { 26000000, 312000000, 312, 26, 1, 12}, 363 { 26000000, 312000000, 312, 26, 0, 12},
364 364
365 { 0, 0, 0, 0, 0, 0 }, 365 { 0, 0, 0, 0, 0, 0 },
366}; 366};
367 367
368static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 368static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
369 { 12000000, 100000000, 200, 24, 1, 0 }, 369 { 12000000, 100000000, 200, 24, 0, 0 },
370 { 0, 0, 0, 0, 0, 0 }, 370 { 0, 0, 0, 0, 0, 0 },
371}; 371};
372 372
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