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authorEmilio López <emilio@elopez.com.ar>2013-04-10 18:02:57 -0400
committerMike Turquette <mturquette@linaro.org>2013-04-12 14:23:41 -0400
commit38e4aa00975cf37afd63d7cd1cefd754dcf66e07 (patch)
tree32cdda9d4b6eeb68e3a5192263802e016c569208 /drivers/clk/sunxi
parentf363e215931ecc8077b6f6ee6d39d9ffaf1c3bd0 (diff)
clk: sunxi: Unify oscillator clock
This commit uses the new fixed-rate support on the composite clock to unify osc24M_fixed and osc24M clocks, so it matches the actual hardware. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: replace clk_register_gatable_osc with a call to clk_register_composite]
Diffstat (limited to 'drivers/clk/sunxi')
-rw-r--r--drivers/clk/sunxi/clk-sunxi.c33
1 files changed, 26 insertions, 7 deletions
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 0bb0eb4ed217..8492ad1d5360 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -33,16 +33,36 @@ static DEFINE_SPINLOCK(clk_lock);
33static void __init sunxi_osc_clk_setup(struct device_node *node) 33static void __init sunxi_osc_clk_setup(struct device_node *node)
34{ 34{
35 struct clk *clk; 35 struct clk *clk;
36 struct clk_fixed_rate *fixed;
37 struct clk_gate *gate;
36 const char *clk_name = node->name; 38 const char *clk_name = node->name;
37 const char *parent; 39 u32 rate;
38 void *reg;
39 40
40 reg = of_iomap(node, 0); 41 /* allocate fixed-rate and gate clock structs */
42 fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
43 if (!fixed)
44 return;
45 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
46 if (!gate) {
47 kfree(fixed);
48 return;
49 }
41 50
42 parent = of_clk_get_parent_name(node, 0); 51 if (of_property_read_u32(node, "clock-frequency", &rate))
52 return;
53
54 /* set up gate and fixed rate properties */
55 gate->reg = of_iomap(node, 0);
56 gate->bit_idx = SUNXI_OSC24M_GATE;
57 gate->lock = &clk_lock;
58 fixed->fixed_rate = rate;
43 59
44 clk = clk_register_gate(NULL, clk_name, parent, 0, reg, 60 clk = clk_register_composite(NULL, clk_name,
45 SUNXI_OSC24M_GATE, 0, &clk_lock); 61 NULL, 0,
62 NULL, NULL,
63 &fixed->hw, &clk_fixed_rate_ops,
64 &gate->hw, &clk_gate_ops,
65 CLK_IS_ROOT);
46 66
47 if (clk) { 67 if (clk) {
48 of_clk_add_provider(node, of_clk_src_simple_get, clk); 68 of_clk_add_provider(node, of_clk_src_simple_get, clk);
@@ -380,7 +400,6 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
380 400
381/* Matches for of_clk_init */ 401/* Matches for of_clk_init */
382static const __initconst struct of_device_id clk_match[] = { 402static const __initconst struct of_device_id clk_match[] = {
383 {.compatible = "fixed-clock", .data = of_fixed_clk_setup,},
384 {.compatible = "allwinner,sun4i-osc-clk", .data = sunxi_osc_clk_setup,}, 403 {.compatible = "allwinner,sun4i-osc-clk", .data = sunxi_osc_clk_setup,},
385 {} 404 {}
386}; 405};