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authorChanwoo Choi <cw00.choi@samsung.com>2015-02-02 09:24:05 -0500
committerSylwester Nawrocki <s.nawrocki@samsung.com>2015-02-04 12:58:14 -0500
commit4b8013554b0454984e71bc20bc31966886079e15 (patch)
treeaec461bd118b077e7326389b1b625035454ffdce /drivers/clk/samsung
parent5785d6e61f27f7af4d239c1647d5a22e0dbff19b (diff)
clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain
This patch adds the mux/divider/gate clocks for CMU_FSYS domain which contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers/clk/samsung')
-rw-r--r--drivers/clk/samsung/clk-exynos5433.c302
1 files changed, 302 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 7c4e91a440e5..1cdc47e05ac1 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -462,6 +462,16 @@ static struct samsung_div_clock top_div_clks[] __initdata = {
462 DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b", 462 DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
463 DIV_TOP_FSYS1, 0, 4), 463 DIV_TOP_FSYS1, 0, 4),
464 464
465 /* DIV_TOP_FSYS2 */
466 DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
467 DIV_TOP_FSYS2, 12, 3),
468 DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
469 "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
470 DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
471 "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
472 DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
473 DIV_TOP_FSYS2, 0, 4),
474
465 /* DIV_TOP_PERIC0 */ 475 /* DIV_TOP_PERIC0 */
466 DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a", 476 DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
467 DIV_TOP_PERIC0, 16, 8), 477 DIV_TOP_PERIC0, 16, 8),
@@ -543,12 +553,23 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
543 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 553 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
544 554
545 /* ENABLE_SCLK_TOP_FSYS */ 555 /* ENABLE_SCLK_TOP_FSYS */
556 GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
557 ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
546 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b", 558 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
547 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0), 559 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
548 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b", 560 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
549 ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0), 561 ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
550 GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b", 562 GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
551 ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0), 563 ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
564 GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
565 "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
566 3, CLK_SET_RATE_PARENT, 0),
567 GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
568 "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
569 1, CLK_SET_RATE_PARENT, 0),
570 GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
571 "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS,
572 0, CLK_SET_RATE_PARENT, 0),
552 573
553 /* ENABLE_SCLK_TOP_PERIC */ 574 /* ENABLE_SCLK_TOP_PERIC */
554 GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b", 575 GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
@@ -1832,10 +1853,45 @@ CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
1832#define ENABLE_IP_FSYS1 0x0b04 1853#define ENABLE_IP_FSYS1 0x0b04
1833 1854
1834/* list of all parent clock list */ 1855/* list of all parent clock list */
1856PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", };
1835PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "div_aclk_fsys_200", }; 1857PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "div_aclk_fsys_200", };
1858PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",};
1859PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",};
1836PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", }; 1860PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", };
1837PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", }; 1861PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", };
1838PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", }; 1862PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", };
1863PNAME(mout_sclk_usbhost30_user_p) = { "oscclk", "sclk_usbhost30_fsys",};
1864PNAME(mout_sclk_usbdrd30_user_p) = { "oscclk", "sclk_usbdrd30_fsys", };
1865
1866PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
1867 = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
1868PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
1869 = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", };
1870PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
1871 = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", };
1872PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
1873 = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", };
1874PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
1875 = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", };
1876PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
1877 = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", };
1878PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
1879 = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", };
1880PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
1881 = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", };
1882PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
1883 = { "oscclk", "phyclk_ufs_rx1_symbol_phy", };
1884PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
1885 = { "oscclk", "phyclk_ufs_rx0_symbol_phy", };
1886PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
1887 = { "oscclk", "phyclk_ufs_tx1_symbol_phy", };
1888PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
1889 = { "oscclk", "phyclk_ufs_tx0_symbol_phy", };
1890PNAME(mout_phyclk_lli_mphy_to_ufs_user_p)
1891 = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", };
1892PNAME(mout_sclk_mphy_p)
1893 = { "mout_sclk_ufs_mphy_user",
1894 "mout_phyclk_lli_mphy_to_ufs_user", };
1839 1895
1840static unsigned long fsys_clk_regs[] __initdata = { 1896static unsigned long fsys_clk_regs[] __initdata = {
1841 MUX_SEL_FSYS0, 1897 MUX_SEL_FSYS0,
@@ -1863,18 +1919,130 @@ static unsigned long fsys_clk_regs[] __initdata = {
1863 ENABLE_IP_FSYS1, 1919 ENABLE_IP_FSYS1,
1864}; 1920};
1865 1921
1922static struct samsung_fixed_rate_clock fsys_fixed_clks[] __initdata = {
1923 /* PHY clocks from USBDRD30_PHY */
1924 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
1925 "phyclk_usbdrd30_udrd30_phyclock_phy", NULL,
1926 CLK_IS_ROOT, 60000000),
1927 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY,
1928 "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL,
1929 CLK_IS_ROOT, 125000000),
1930 /* PHY clocks from USBHOST30_PHY */
1931 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY,
1932 "phyclk_usbhost30_uhost30_phyclock_phy", NULL,
1933 CLK_IS_ROOT, 60000000),
1934 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY,
1935 "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL,
1936 CLK_IS_ROOT, 125000000),
1937 /* PHY clocks from USBHOST20_PHY */
1938 FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY,
1939 "phyclk_usbhost20_phy_freeclk_phy", NULL, CLK_IS_ROOT,
1940 60000000),
1941 FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY,
1942 "phyclk_usbhost20_phy_phyclock_phy", NULL, CLK_IS_ROOT,
1943 60000000),
1944 FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY,
1945 "phyclk_usbhost20_phy_clk48mohci_phy", NULL,
1946 CLK_IS_ROOT, 48000000),
1947 FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY,
1948 "phyclk_usbhost20_phy_hsic1_phy", NULL, CLK_IS_ROOT,
1949 60000000),
1950 /* PHY clocks from UFS_PHY */
1951 FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy",
1952 NULL, CLK_IS_ROOT, 300000000),
1953 FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy",
1954 NULL, CLK_IS_ROOT, 300000000),
1955 FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy",
1956 NULL, CLK_IS_ROOT, 300000000),
1957 FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy",
1958 NULL, CLK_IS_ROOT, 300000000),
1959 /* PHY clocks from LLI_PHY */
1960 FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy",
1961 NULL, CLK_IS_ROOT, 26000000),
1962};
1963
1866static struct samsung_mux_clock fsys_mux_clks[] __initdata = { 1964static struct samsung_mux_clock fsys_mux_clks[] __initdata = {
1867 /* MUX_SEL_FSYS0 */ 1965 /* MUX_SEL_FSYS0 */
1966 MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
1967 mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
1868 MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user", 1968 MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
1869 mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1), 1969 mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
1870 1970
1871 /* MUX_SEL_FSYS1 */ 1971 /* MUX_SEL_FSYS1 */
1972 MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user",
1973 mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1),
1974 MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user",
1975 mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1),
1872 MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user", 1976 MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
1873 mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1), 1977 mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
1874 MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user", 1978 MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
1875 mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1), 1979 mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
1876 MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user", 1980 MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
1877 mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1), 1981 mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
1982 MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user",
1983 mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1),
1984 MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user",
1985 mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
1986
1987 /* MUX_SEL_FSYS2 */
1988 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER,
1989 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
1990 mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p,
1991 MUX_SEL_FSYS2, 28, 1),
1992 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER,
1993 "mout_phyclk_usbhost30_uhost30_phyclock_user",
1994 mout_phyclk_usbhost30_uhost30_phyclock_user_p,
1995 MUX_SEL_FSYS2, 24, 1),
1996 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER,
1997 "mout_phyclk_usbhost20_phy_hsic1",
1998 mout_phyclk_usbhost20_phy_hsic1_p,
1999 MUX_SEL_FSYS2, 20, 1),
2000 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER,
2001 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2002 mout_phyclk_usbhost20_phy_clk48mohci_user_p,
2003 MUX_SEL_FSYS2, 16, 1),
2004 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER,
2005 "mout_phyclk_usbhost20_phy_phyclock_user",
2006 mout_phyclk_usbhost20_phy_phyclock_user_p,
2007 MUX_SEL_FSYS2, 12, 1),
2008 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER,
2009 "mout_phyclk_usbhost20_phy_freeclk_user",
2010 mout_phyclk_usbhost20_phy_freeclk_user_p,
2011 MUX_SEL_FSYS2, 8, 1),
2012 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
2013 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2014 mout_phyclk_usbdrd30_udrd30_pipe_pclk_p,
2015 MUX_SEL_FSYS2, 4, 1),
2016 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
2017 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2018 mout_phyclk_usbdrd30_udrd30_phyclock_user_p,
2019 MUX_SEL_FSYS2, 0, 1),
2020
2021 /* MUX_SEL_FSYS3 */
2022 MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
2023 "mout_phyclk_ufs_rx1_symbol_user",
2024 mout_phyclk_ufs_rx1_symbol_user_p,
2025 MUX_SEL_FSYS3, 16, 1),
2026 MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
2027 "mout_phyclk_ufs_rx0_symbol_user",
2028 mout_phyclk_ufs_rx0_symbol_user_p,
2029 MUX_SEL_FSYS3, 12, 1),
2030 MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
2031 "mout_phyclk_ufs_tx1_symbol_user",
2032 mout_phyclk_ufs_tx1_symbol_user_p,
2033 MUX_SEL_FSYS3, 8, 1),
2034 MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
2035 "mout_phyclk_ufs_tx0_symbol_user",
2036 mout_phyclk_ufs_tx0_symbol_user_p,
2037 MUX_SEL_FSYS3, 4, 1),
2038 MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
2039 "mout_phyclk_lli_mphy_to_ufs_user",
2040 mout_phyclk_lli_mphy_to_ufs_user_p,
2041 MUX_SEL_FSYS3, 0, 1),
2042
2043 /* MUX_SEL_FSYS4 */
2044 MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p,
2045 MUX_SEL_FSYS4, 0, 1),
1878}; 2046};
1879 2047
1880static struct samsung_gate_clock fsys_gate_clks[] __initdata = { 2048static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
@@ -1902,13 +2070,145 @@ static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
1902 GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user", 2070 GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
1903 ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0), 2071 ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
1904 2072
2073 /* ENABLE_ACLK_FSYS1 */
2074 GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user",
2075 ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
2076 GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1",
2077 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2078 26, CLK_IGNORE_UNUSED, 0),
2079 GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2080 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
2081 GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
2082 ENABLE_ACLK_FSYS1, 24, 0, 0),
2083 GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
2084 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2085 22, CLK_IGNORE_UNUSED, 0),
2086 GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2087 ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
2088 GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user",
2089 ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
2090 GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30",
2091 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2092 13, 0, 0),
2093 GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30",
2094 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2095 12, 0, 0),
2096 GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0",
2097 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2098 11, CLK_IGNORE_UNUSED, 0),
2099 GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs",
2100 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2101 10, CLK_IGNORE_UNUSED, 0),
2102 GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx",
2103 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2104 9, CLK_IGNORE_UNUSED, 0),
2105 GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp",
2106 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2107 8, CLK_IGNORE_UNUSED, 0),
2108 GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs",
2109 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2110 7, CLK_IGNORE_UNUSED, 0),
2111 GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0",
2112 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2113 6, CLK_IGNORE_UNUSED, 0),
2114 GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user",
2115 ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
2116 GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user",
2117 ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
2118 GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user",
2119 ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
2120 GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user",
2121 ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
2122 GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user",
2123 ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
2124 GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user",
2125 ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
2126
2127 /* ENABLE_PCLK_FSYS */
2128 GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
2129 ENABLE_PCLK_FSYS, 17, 0, 0),
2130 GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2131 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
2132 GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
2133 ENABLE_PCLK_FSYS, 14, 0, 0),
2134 GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
2135 ENABLE_PCLK_FSYS, 13, 0, 0),
2136 GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2137 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
2138 GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
2139 ENABLE_PCLK_FSYS, 5, 0, 0),
2140 GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30",
2141 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
2142 GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30",
2143 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
2144 GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user",
2145 ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
2146 GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user",
2147 ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
2148 GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys",
2149 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS,
2150 0, CLK_IGNORE_UNUSED, 0),
2151
1905 /* ENABLE_SCLK_FSYS */ 2152 /* ENABLE_SCLK_FSYS */
2153 GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user",
2154 ENABLE_SCLK_FSYS, 21, 0, 0),
2155 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
2156 "phyclk_usbhost30_uhost30_pipe_pclk",
2157 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2158 ENABLE_SCLK_FSYS, 18, 0, 0),
2159 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
2160 "phyclk_usbhost30_uhost30_phyclock",
2161 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2162 ENABLE_SCLK_FSYS, 17, 0, 0),
2163 GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol",
2164 "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS,
2165 16, 0, 0),
2166 GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol",
2167 "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS,
2168 15, 0, 0),
2169 GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol",
2170 "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS,
2171 14, 0, 0),
2172 GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol",
2173 "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS,
2174 13, 0, 0),
2175 GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1",
2176 "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS,
2177 12, 0, 0),
2178 GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
2179 "phyclk_usbhost20_phy_clk48mohci",
2180 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2181 ENABLE_SCLK_FSYS, 11, 0, 0),
2182 GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
2183 "phyclk_usbhost20_phy_phyclock",
2184 "mout_phyclk_usbhost20_phy_phyclock_user",
2185 ENABLE_SCLK_FSYS, 10, 0, 0),
2186 GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
2187 "phyclk_usbhost20_phy_freeclk",
2188 "mout_phyclk_usbhost20_phy_freeclk_user",
2189 ENABLE_SCLK_FSYS, 9, 0, 0),
2190 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
2191 "phyclk_usbdrd30_udrd30_pipe_pclk",
2192 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2193 ENABLE_SCLK_FSYS, 8, 0, 0),
2194 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
2195 "phyclk_usbdrd30_udrd30_phyclock",
2196 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2197 ENABLE_SCLK_FSYS, 7, 0, 0),
2198 GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy",
2199 ENABLE_SCLK_FSYS, 6, 0, 0),
2200 GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user",
2201 ENABLE_SCLK_FSYS, 5, 0, 0),
1906 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user", 2202 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
1907 ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0), 2203 ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
1908 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user", 2204 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
1909 ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0), 2205 ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
1910 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user", 2206 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
1911 ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 2207 ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
2208 GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user",
2209 ENABLE_SCLK_FSYS, 1, 0, 0),
2210 GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user",
2211 ENABLE_SCLK_FSYS, 0, 0, 0),
1912 2212
1913 /* ENABLE_IP_FSYS0 */ 2213 /* ENABLE_IP_FSYS0 */
1914 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0), 2214 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
@@ -1920,6 +2220,8 @@ static struct samsung_cmu_info fsys_cmu_info __initdata = {
1920 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), 2220 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
1921 .gate_clks = fsys_gate_clks, 2221 .gate_clks = fsys_gate_clks,
1922 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks), 2222 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
2223 .fixed_clks = fsys_fixed_clks,
2224 .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks),
1923 .nr_clk_ids = FSYS_NR_CLK, 2225 .nr_clk_ids = FSYS_NR_CLK,
1924 .clk_regs = fsys_clk_regs, 2226 .clk_regs = fsys_clk_regs,
1925 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs), 2227 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-02 15:21:11 -0500