clk: samsung: exynos7: add gate clock for ADC block

Add clock support for the ADC interface in Exynos7.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index 17e5cf4d2248..ea4483b8d62e 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -486,6 +486,8 @@ static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
                 ENABLE_PCLK_PERIC0, 14, 0, 0),
         GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
                 ENABLE_PCLK_PERIC0, 16, 0, 0),
+        GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user",
+                ENABLE_PCLK_PERIC0, 20, 0, 0),
         GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
                 ENABLE_PCLK_PERIC0, 21, 0, 0),