clk: samsung: exynos5420: fix parent clocks for mscl sysmmu

This patch fixes the parent clocks for mscl sysmmu.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>

1 files changed, 6 insertions, 3 deletions

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index cb7a63913e18..48a5772dca89 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -583,6 +583,9 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
                         DIV2_RATIO0, 4, 2),
         DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
 
+        /* MSCL Block */
+        DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
+
         /* ISP Block */
         DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
         DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
@@ -816,11 +819,11 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
         GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
         GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
         GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
-        GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "aclk400_mscl",
+        GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
                         GATE_IP_MSCL, 8, 0, 0),
-        GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "aclk400_mscl",
+        GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
                         GATE_IP_MSCL, 9, 0, 0),
-        GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "aclk400_mscl",
+        GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
                         GATE_IP_MSCL, 10, 0, 0),
 
         GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),