diff options
author | Sachin Kamat <sachin.kamat@linaro.org> | 2013-08-07 00:48:38 -0400 |
---|---|---|
committer | Mike Turquette <mturquette@linaro.org> | 2013-08-08 18:57:35 -0400 |
commit | b6993ecb87ac65cf7e718f4f45579e4f78fc1c27 (patch) | |
tree | 895c9f8ac930a27eb3ca2cc38746f2fa457b98ca /drivers/clk/samsung/clk-exynos5250.c | |
parent | 3c701c51ef918ce7bbe6ba983ea2e0e0cead5810 (diff) |
clk: exynos5250: Fix incorrect placement of __initdata
__initdata should be placed between the variable name and equal
sign for the variable to be placed in the intended section.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos5250.c')
-rw-r--r-- | drivers/clk/samsung/clk-exynos5250.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 5865cefa69f4..a9916a46e7a7 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c | |||
@@ -132,7 +132,7 @@ enum exynos5250_clks { | |||
132 | * list of controller registers to be saved and restored during a | 132 | * list of controller registers to be saved and restored during a |
133 | * suspend/resume cycle. | 133 | * suspend/resume cycle. |
134 | */ | 134 | */ |
135 | static __initdata unsigned long exynos5250_clk_regs[] = { | 135 | static unsigned long exynos5250_clk_regs[] __initdata = { |
136 | SRC_CPU, | 136 | SRC_CPU, |
137 | DIV_CPU0, | 137 | DIV_CPU0, |
138 | SRC_CORE1, | 138 | SRC_CORE1, |
@@ -494,7 +494,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { | |||
494 | GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0), | 494 | GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0), |
495 | }; | 495 | }; |
496 | 496 | ||
497 | static __initdata struct samsung_pll_rate_table vpll_24mhz_tbl[] = { | 497 | static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { |
498 | /* sorted in descending order */ | 498 | /* sorted in descending order */ |
499 | /* PLL_36XX_RATE(rate, m, p, s, k) */ | 499 | /* PLL_36XX_RATE(rate, m, p, s, k) */ |
500 | PLL_36XX_RATE(266000000, 266, 3, 3, 0), | 500 | PLL_36XX_RATE(266000000, 266, 3, 3, 0), |
@@ -503,7 +503,7 @@ static __initdata struct samsung_pll_rate_table vpll_24mhz_tbl[] = { | |||
503 | { }, | 503 | { }, |
504 | }; | 504 | }; |
505 | 505 | ||
506 | static __initdata struct samsung_pll_rate_table epll_24mhz_tbl[] = { | 506 | static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = { |
507 | /* sorted in descending order */ | 507 | /* sorted in descending order */ |
508 | /* PLL_36XX_RATE(rate, m, p, s, k) */ | 508 | /* PLL_36XX_RATE(rate, m, p, s, k) */ |
509 | PLL_36XX_RATE(192000000, 64, 2, 2, 0), | 509 | PLL_36XX_RATE(192000000, 64, 2, 2, 0), |
@@ -517,7 +517,7 @@ static __initdata struct samsung_pll_rate_table epll_24mhz_tbl[] = { | |||
517 | { }, | 517 | { }, |
518 | }; | 518 | }; |
519 | 519 | ||
520 | static struct __initdata samsung_pll_clock exynos5250_plls[nr_plls] = { | 520 | static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = { |
521 | [apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, | 521 | [apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, |
522 | APLL_CON0, "fout_apll", NULL), | 522 | APLL_CON0, "fout_apll", NULL), |
523 | [mpll] = PLL_A(pll_35xx, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK, | 523 | [mpll] = PLL_A(pll_35xx, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK, |
@@ -534,7 +534,7 @@ static struct __initdata samsung_pll_clock exynos5250_plls[nr_plls] = { | |||
534 | VPLL_LOCK, VPLL_CON0, NULL), | 534 | VPLL_LOCK, VPLL_CON0, NULL), |
535 | }; | 535 | }; |
536 | 536 | ||
537 | static __initdata struct of_device_id ext_clk_match[] = { | 537 | static struct of_device_id ext_clk_match[] __initdata = { |
538 | { .compatible = "samsung,clock-xxti", .data = (void *)0, }, | 538 | { .compatible = "samsung,clock-xxti", .data = (void *)0, }, |
539 | { }, | 539 | { }, |
540 | }; | 540 | }; |