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authorMilosz Tanski <milosz@adfin.com>2013-09-06 12:41:20 -0400
committerMilosz Tanski <milosz@adfin.com>2013-09-06 12:41:20 -0400
commitcd0a2df681ec2af45f50c555c2a39dc92a4dff71 (patch)
tree35d2278a9494582025f3dac08feb2266adef6a4d /drivers/clk/samsung/clk-exynos4.c
parentc35455791c1131e7ccbf56ea6fbdd562401c2ce2 (diff)
parent5a6f282a2052bb13171b53f03b34501cf72c33f1 (diff)
Merge tag 'fscache-fixes-for-ceph' into wip-fscache
Patches for Ceph FS-Cache support
Diffstat (limited to 'drivers/clk/samsung/clk-exynos4.c')
-rw-r--r--drivers/clk/samsung/clk-exynos4.c64
1 files changed, 34 insertions, 30 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 1bdb882c845b..4e5739773c33 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -581,11 +581,15 @@ struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
581 DIV(none, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4), 581 DIV(none, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
582 DIV(none, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8), 582 DIV(none, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
583 DIV(none, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4), 583 DIV(none, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
584 DIV(div_isp0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3), 584 DIV_F(div_isp0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3,
585 DIV(div_isp1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3), 585 CLK_GET_RATE_NOCACHE, 0),
586 DIV_F(div_isp1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3,
587 CLK_GET_RATE_NOCACHE, 0),
586 DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), 588 DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
587 DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3), 589 DIV_F(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1,
588 DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3), 590 4, 3, CLK_GET_RATE_NOCACHE, 0),
591 DIV_F(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
592 8, 3, CLK_GET_RATE_NOCACHE, 0),
589 DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), 593 DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
590}; 594};
591 595
@@ -863,57 +867,57 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
863 GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100", 867 GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100",
864 E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"), 868 E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"),
865 GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0, 869 GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0,
866 CLK_IGNORE_UNUSED, 0), 870 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
867 GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1, 871 GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1,
868 CLK_IGNORE_UNUSED, 0), 872 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
869 GATE(fimc_fd, "fd", "aclk200", E4X12_GATE_ISP0, 2, 873 GATE(fimc_fd, "fd", "aclk200", E4X12_GATE_ISP0, 2,
870 CLK_IGNORE_UNUSED, 0), 874 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
871 GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 875 GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3,
872 CLK_IGNORE_UNUSED, 0), 876 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
873 GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 877 GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4,
874 CLK_IGNORE_UNUSED, 0), 878 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
875 GATE(mcuisp, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 879 GATE(mcuisp, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5,
876 CLK_IGNORE_UNUSED, 0), 880 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
877 GATE(gicisp, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, 881 GATE(gicisp, "gicisp", "aclk200", E4X12_GATE_ISP0, 7,
878 CLK_IGNORE_UNUSED, 0), 882 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
879 GATE(smmu_isp, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, 883 GATE(smmu_isp, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8,
880 CLK_IGNORE_UNUSED, 0), 884 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
881 GATE(smmu_drc, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, 885 GATE(smmu_drc, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9,
882 CLK_IGNORE_UNUSED, 0), 886 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
883 GATE(smmu_fd, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, 887 GATE(smmu_fd, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10,
884 CLK_IGNORE_UNUSED, 0), 888 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
885 GATE(smmu_lite0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11, 889 GATE(smmu_lite0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
886 CLK_IGNORE_UNUSED, 0), 890 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
887 GATE(smmu_lite1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12, 891 GATE(smmu_lite1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
888 CLK_IGNORE_UNUSED, 0), 892 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
889 GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20, 893 GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
890 CLK_IGNORE_UNUSED, 0), 894 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
891 GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21, 895 GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
892 CLK_IGNORE_UNUSED, 0), 896 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
893 GATE(mcuctl_isp, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23, 897 GATE(mcuctl_isp, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
894 CLK_IGNORE_UNUSED, 0), 898 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
895 GATE(mpwm_isp, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24, 899 GATE(mpwm_isp, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
896 CLK_IGNORE_UNUSED, 0), 900 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
897 GATE(i2c0_isp, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25, 901 GATE(i2c0_isp, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
898 CLK_IGNORE_UNUSED, 0), 902 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
899 GATE(i2c1_isp, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26, 903 GATE(i2c1_isp, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
900 CLK_IGNORE_UNUSED, 0), 904 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
901 GATE(mtcadc_isp, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27, 905 GATE(mtcadc_isp, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
902 CLK_IGNORE_UNUSED, 0), 906 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
903 GATE(pwm_isp, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, 907 GATE(pwm_isp, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28,
904 CLK_IGNORE_UNUSED, 0), 908 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
905 GATE(wdt_isp, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, 909 GATE(wdt_isp, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30,
906 CLK_IGNORE_UNUSED, 0), 910 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
907 GATE(uart_isp, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31, 911 GATE(uart_isp, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
908 CLK_IGNORE_UNUSED, 0), 912 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
909 GATE(asyncaxim, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0, 913 GATE(asyncaxim, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
910 CLK_IGNORE_UNUSED, 0), 914 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
911 GATE(smmu_ispcx, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4, 915 GATE(smmu_ispcx, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
912 CLK_IGNORE_UNUSED, 0), 916 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
913 GATE(spi0_isp, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12, 917 GATE(spi0_isp, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
914 CLK_IGNORE_UNUSED, 0), 918 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
915 GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, 919 GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
916 CLK_IGNORE_UNUSED, 0), 920 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
917 GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), 921 GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
918}; 922};
919 923