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authorRahul Sharma <rahul.sharma@samsung.com>2014-03-12 10:56:44 -0400
committerTomasz Figa <t.figa@samsung.com>2014-05-14 13:15:38 -0400
commit976face4b46ab36b04312b4e404d160296716d46 (patch)
tree69952ba0f302faf76209e1e6da0aa8ceb32b97b3 /drivers/clk/samsung/clk-exynos4.c
parent2916f9a2c6d9200b4c840a613cd1fa1dad04240f (diff)
clk/samsung: add support for multiple clock providers
Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos4.c')
-rw-r--r--drivers/clk/samsung/clk-exynos4.c47
1 files changed, 25 insertions, 22 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index b4f967210175..57ed5a8fb052 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1043,7 +1043,7 @@ static unsigned long exynos4_get_xom(void)
1043 return xom; 1043 return xom;
1044} 1044}
1045 1045
1046static void __init exynos4_clk_register_finpll(void) 1046static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)
1047{ 1047{
1048 struct samsung_fixed_rate_clock fclk; 1048 struct samsung_fixed_rate_clock fclk;
1049 struct clk *clk; 1049 struct clk *clk;
@@ -1066,7 +1066,7 @@ static void __init exynos4_clk_register_finpll(void)
1066 fclk.parent_name = NULL; 1066 fclk.parent_name = NULL;
1067 fclk.flags = CLK_IS_ROOT; 1067 fclk.flags = CLK_IS_ROOT;
1068 fclk.fixed_rate = finpll_f; 1068 fclk.fixed_rate = finpll_f;
1069 samsung_clk_register_fixed_rate(&fclk, 1); 1069 samsung_clk_register_fixed_rate(ctx, &fclk, 1);
1070 1070
1071} 1071}
1072 1072
@@ -1176,22 +1176,25 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
1176static void __init exynos4_clk_init(struct device_node *np, 1176static void __init exynos4_clk_init(struct device_node *np,
1177 enum exynos4_soc soc) 1177 enum exynos4_soc soc)
1178{ 1178{
1179 struct samsung_clk_provider *ctx;
1179 exynos4_soc = soc; 1180 exynos4_soc = soc;
1180 1181
1181 reg_base = of_iomap(np, 0); 1182 reg_base = of_iomap(np, 0);
1182 if (!reg_base) 1183 if (!reg_base)
1183 panic("%s: failed to map registers\n", __func__); 1184 panic("%s: failed to map registers\n", __func__);
1184 1185
1185 samsung_clk_init(np, reg_base, CLK_NR_CLKS); 1186 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
1187 if (!ctx)
1188 panic("%s: unable to allocate context.\n", __func__);
1186 1189
1187 samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks, 1190 samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
1188 ARRAY_SIZE(exynos4_fixed_rate_ext_clks), 1191 ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
1189 ext_clk_match); 1192 ext_clk_match);
1190 1193
1191 exynos4_clk_register_finpll(); 1194 exynos4_clk_register_finpll(ctx);
1192 1195
1193 if (exynos4_soc == EXYNOS4210) { 1196 if (exynos4_soc == EXYNOS4210) {
1194 samsung_clk_register_mux(exynos4210_mux_early, 1197 samsung_clk_register_mux(ctx, exynos4210_mux_early,
1195 ARRAY_SIZE(exynos4210_mux_early)); 1198 ARRAY_SIZE(exynos4210_mux_early));
1196 1199
1197 if (_get_rate("fin_pll") == 24000000) { 1200 if (_get_rate("fin_pll") == 24000000) {
@@ -1205,7 +1208,7 @@ static void __init exynos4_clk_init(struct device_node *np,
1205 exynos4210_plls[vpll].rate_table = 1208 exynos4210_plls[vpll].rate_table =
1206 exynos4210_vpll_rates; 1209 exynos4210_vpll_rates;
1207 1210
1208 samsung_clk_register_pll(exynos4210_plls, 1211 samsung_clk_register_pll(ctx, exynos4210_plls,
1209 ARRAY_SIZE(exynos4210_plls), reg_base); 1212 ARRAY_SIZE(exynos4210_plls), reg_base);
1210 } else { 1213 } else {
1211 if (_get_rate("fin_pll") == 24000000) { 1214 if (_get_rate("fin_pll") == 24000000) {
@@ -1217,42 +1220,42 @@ static void __init exynos4_clk_init(struct device_node *np,
1217 exynos4x12_vpll_rates; 1220 exynos4x12_vpll_rates;
1218 } 1221 }
1219 1222
1220 samsung_clk_register_pll(exynos4x12_plls, 1223 samsung_clk_register_pll(ctx, exynos4x12_plls,
1221 ARRAY_SIZE(exynos4x12_plls), reg_base); 1224 ARRAY_SIZE(exynos4x12_plls), reg_base);
1222 } 1225 }
1223 1226
1224 samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks, 1227 samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,
1225 ARRAY_SIZE(exynos4_fixed_rate_clks)); 1228 ARRAY_SIZE(exynos4_fixed_rate_clks));
1226 samsung_clk_register_mux(exynos4_mux_clks, 1229 samsung_clk_register_mux(ctx, exynos4_mux_clks,
1227 ARRAY_SIZE(exynos4_mux_clks)); 1230 ARRAY_SIZE(exynos4_mux_clks));
1228 samsung_clk_register_div(exynos4_div_clks, 1231 samsung_clk_register_div(ctx, exynos4_div_clks,
1229 ARRAY_SIZE(exynos4_div_clks)); 1232 ARRAY_SIZE(exynos4_div_clks));
1230 samsung_clk_register_gate(exynos4_gate_clks, 1233 samsung_clk_register_gate(ctx, exynos4_gate_clks,
1231 ARRAY_SIZE(exynos4_gate_clks)); 1234 ARRAY_SIZE(exynos4_gate_clks));
1232 1235
1233 if (exynos4_soc == EXYNOS4210) { 1236 if (exynos4_soc == EXYNOS4210) {
1234 samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks, 1237 samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
1235 ARRAY_SIZE(exynos4210_fixed_rate_clks)); 1238 ARRAY_SIZE(exynos4210_fixed_rate_clks));
1236 samsung_clk_register_mux(exynos4210_mux_clks, 1239 samsung_clk_register_mux(ctx, exynos4210_mux_clks,
1237 ARRAY_SIZE(exynos4210_mux_clks)); 1240 ARRAY_SIZE(exynos4210_mux_clks));
1238 samsung_clk_register_div(exynos4210_div_clks, 1241 samsung_clk_register_div(ctx, exynos4210_div_clks,
1239 ARRAY_SIZE(exynos4210_div_clks)); 1242 ARRAY_SIZE(exynos4210_div_clks));
1240 samsung_clk_register_gate(exynos4210_gate_clks, 1243 samsung_clk_register_gate(ctx, exynos4210_gate_clks,
1241 ARRAY_SIZE(exynos4210_gate_clks)); 1244 ARRAY_SIZE(exynos4210_gate_clks));
1242 samsung_clk_register_alias(exynos4210_aliases, 1245 samsung_clk_register_alias(ctx, exynos4210_aliases,
1243 ARRAY_SIZE(exynos4210_aliases)); 1246 ARRAY_SIZE(exynos4210_aliases));
1244 } else { 1247 } else {
1245 samsung_clk_register_mux(exynos4x12_mux_clks, 1248 samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
1246 ARRAY_SIZE(exynos4x12_mux_clks)); 1249 ARRAY_SIZE(exynos4x12_mux_clks));
1247 samsung_clk_register_div(exynos4x12_div_clks, 1250 samsung_clk_register_div(ctx, exynos4x12_div_clks,
1248 ARRAY_SIZE(exynos4x12_div_clks)); 1251 ARRAY_SIZE(exynos4x12_div_clks));
1249 samsung_clk_register_gate(exynos4x12_gate_clks, 1252 samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
1250 ARRAY_SIZE(exynos4x12_gate_clks)); 1253 ARRAY_SIZE(exynos4x12_gate_clks));
1251 samsung_clk_register_alias(exynos4x12_aliases, 1254 samsung_clk_register_alias(ctx, exynos4x12_aliases,
1252 ARRAY_SIZE(exynos4x12_aliases)); 1255 ARRAY_SIZE(exynos4x12_aliases));
1253 } 1256 }
1254 1257
1255 samsung_clk_register_alias(exynos4_aliases, 1258 samsung_clk_register_alias(ctx, exynos4_aliases,
1256 ARRAY_SIZE(exynos4_aliases)); 1259 ARRAY_SIZE(exynos4_aliases));
1257 1260
1258 exynos4_clk_sleep_init(); 1261 exynos4_clk_sleep_init();