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authorLinus Torvalds <torvalds@linux-foundation.org>2013-05-04 15:31:18 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-05-04 15:31:18 -0400
commit6fa52ed33bea997374a88dbacbba5bf8c7ac4fef (patch)
treea0904b78d66c9b99d6acf944cf58bcaa0cffc511 /drivers/clk/samsung/clk-exynos4.c
parent1db772216f48978d5146b858586f6178433aad38 (diff)
parentbc8fd900c4d460b4e4bf785bb48bfced0ac9941b (diff)
Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver changes from Olof Johansson: "This is a rather large set of patches for device drivers that for one reason or another the subsystem maintainer preferred to get merged through the arm-soc tree. There are both new drivers as well as existing drivers that are getting converted from platform-specific code into standalone drivers using the appropriate subsystem specific interfaces. In particular, we can now have pinctrl, clk, clksource and irqchip drivers in one file per driver, without the need to call into platform specific interface, or to get called from platform specific code, as long as all information about the hardware is provided through a device tree. Most of the drivers we touch this time are for clocksource. Since now most of them are part of drivers/clocksource, I expect that we won't have to touch these again from arm-soc and can let the clocksource maintainers take care of these in the future. Another larger part of this series is specific to the exynos platform, which is seeing some significant effort in upstreaming and modernization of its device drivers this time around, which unfortunately is also the cause for the churn and a lot of the merge conflicts. There is one new subsystem that gets merged as part of this series: the reset controller interface, which is a very simple interface for taking devices on the SoC out of reset or back into reset. Patches to use this interface on i.MX follow later in this merge window, and we are going to have other platforms (at least tegra and sirf) get converted in 3.11. This will let us get rid of platform specific callbacks in a number of platform independent device drivers." * tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (256 commits) irqchip: s3c24xx: add missing __init annotations ARM: dts: Disable the RTC by default on exynos5 clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3} ARM: exynos: restore mach/regs-clock.h for exynos5 clocksource: exynos_mct: fix build error on non-DT pinctrl: vt8500: wmt: Fix checking return value of pinctrl_register() irqchip: vt8500: Convert arch-vt8500 to new irqchip infrastructure reset: NULL deref on allocation failure reset: Add reset controller API dt: describe base reset signal binding ARM: EXYNOS: Add arm-pmu DT binding for exynos421x ARM: EXYNOS: Add arm-pmu DT binding for exynos5250 ARM: EXYNOS: Enable PMUs for exynos4 irqchip: exynos-combiner: Correct combined IRQs for exynos4 irqchip: exynos-combiner: Add set_irq_affinity function for combiner_irq ARM: EXYNOS: fix compilation error introduced due to common clock migration clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3} clk: exynos4: export clocks required for fimc-is clk: samsung: Fix compilation error clk: tegra: fix enum tegra114_clk to match binding ...
Diffstat (limited to 'drivers/clk/samsung/clk-exynos4.c')
-rw-r--r--drivers/clk/samsung/clk-exynos4.c1091
1 files changed, 1091 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
new file mode 100644
index 000000000000..71046694d9dd
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -0,0 +1,1091 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 * Author: Thomas Abraham <thomas.ab@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Common Clock Framework support for all Exynos4 SoCs.
11*/
12
13#include <linux/clk.h>
14#include <linux/clkdev.h>
15#include <linux/clk-provider.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18
19#include <plat/cpu.h>
20#include "clk.h"
21#include "clk-pll.h"
22
23/* Exynos4 clock controller register offsets */
24#define SRC_LEFTBUS 0x4200
25#define DIV_LEFTBUS 0x4500
26#define GATE_IP_LEFTBUS 0x4800
27#define E4X12_GATE_IP_IMAGE 0x4930
28#define SRC_RIGHTBUS 0x8200
29#define DIV_RIGHTBUS 0x8500
30#define GATE_IP_RIGHTBUS 0x8800
31#define E4X12_GATE_IP_PERIR 0x8960
32#define EPLL_LOCK 0xc010
33#define VPLL_LOCK 0xc020
34#define EPLL_CON0 0xc110
35#define EPLL_CON1 0xc114
36#define EPLL_CON2 0xc118
37#define VPLL_CON0 0xc120
38#define VPLL_CON1 0xc124
39#define VPLL_CON2 0xc128
40#define SRC_TOP0 0xc210
41#define SRC_TOP1 0xc214
42#define SRC_CAM 0xc220
43#define SRC_TV 0xc224
44#define SRC_MFC 0xcc28
45#define SRC_G3D 0xc22c
46#define E4210_SRC_IMAGE 0xc230
47#define SRC_LCD0 0xc234
48#define E4210_SRC_LCD1 0xc238
49#define E4X12_SRC_ISP 0xc238
50#define SRC_MAUDIO 0xc23c
51#define SRC_FSYS 0xc240
52#define SRC_PERIL0 0xc250
53#define SRC_PERIL1 0xc254
54#define E4X12_SRC_CAM1 0xc258
55#define SRC_MASK_TOP 0xc310
56#define SRC_MASK_CAM 0xc320
57#define SRC_MASK_TV 0xc324
58#define SRC_MASK_LCD0 0xc334
59#define E4210_SRC_MASK_LCD1 0xc338
60#define E4X12_SRC_MASK_ISP 0xc338
61#define SRC_MASK_MAUDIO 0xc33c
62#define SRC_MASK_FSYS 0xc340
63#define SRC_MASK_PERIL0 0xc350
64#define SRC_MASK_PERIL1 0xc354
65#define DIV_TOP 0xc510
66#define DIV_CAM 0xc520
67#define DIV_TV 0xc524
68#define DIV_MFC 0xc528
69#define DIV_G3D 0xc52c
70#define DIV_IMAGE 0xc530
71#define DIV_LCD0 0xc534
72#define E4210_DIV_LCD1 0xc538
73#define E4X12_DIV_ISP 0xc538
74#define DIV_MAUDIO 0xc53c
75#define DIV_FSYS0 0xc540
76#define DIV_FSYS1 0xc544
77#define DIV_FSYS2 0xc548
78#define DIV_FSYS3 0xc54c
79#define DIV_PERIL0 0xc550
80#define DIV_PERIL1 0xc554
81#define DIV_PERIL2 0xc558
82#define DIV_PERIL3 0xc55c
83#define DIV_PERIL4 0xc560
84#define DIV_PERIL5 0xc564
85#define E4X12_DIV_CAM1 0xc568
86#define GATE_SCLK_CAM 0xc820
87#define GATE_IP_CAM 0xc920
88#define GATE_IP_TV 0xc924
89#define GATE_IP_MFC 0xc928
90#define GATE_IP_G3D 0xc92c
91#define E4210_GATE_IP_IMAGE 0xc930
92#define GATE_IP_LCD0 0xc934
93#define E4210_GATE_IP_LCD1 0xc938
94#define E4X12_GATE_IP_ISP 0xc938
95#define E4X12_GATE_IP_MAUDIO 0xc93c
96#define GATE_IP_FSYS 0xc940
97#define GATE_IP_GPS 0xc94c
98#define GATE_IP_PERIL 0xc950
99#define E4210_GATE_IP_PERIR 0xc960
100#define GATE_BLOCK 0xc970
101#define E4X12_MPLL_CON0 0x10108
102#define SRC_DMC 0x10200
103#define SRC_MASK_DMC 0x10300
104#define DIV_DMC0 0x10500
105#define DIV_DMC1 0x10504
106#define GATE_IP_DMC 0x10900
107#define APLL_CON0 0x14100
108#define E4210_MPLL_CON0 0x14108
109#define SRC_CPU 0x14200
110#define DIV_CPU0 0x14500
111#define DIV_CPU1 0x14504
112#define GATE_SCLK_CPU 0x14800
113#define GATE_IP_CPU 0x14900
114#define E4X12_DIV_ISP0 0x18300
115#define E4X12_DIV_ISP1 0x18304
116#define E4X12_GATE_ISP0 0x18800
117#define E4X12_GATE_ISP1 0x18804
118
119/* the exynos4 soc type */
120enum exynos4_soc {
121 EXYNOS4210,
122 EXYNOS4X12,
123};
124
125/*
126 * Let each supported clock get a unique id. This id is used to lookup the clock
127 * for device tree based platforms. The clocks are categorized into three
128 * sections: core, sclk gate and bus interface gate clocks.
129 *
130 * When adding a new clock to this list, it is advised to choose a clock
131 * category and add it to the end of that category. That is because the the
132 * device tree source file is referring to these ids and any change in the
133 * sequence number of existing clocks will require corresponding change in the
134 * device tree files. This limitation would go away when pre-processor support
135 * for dtc would be available.
136 */
137enum exynos4_clks {
138 none,
139
140 /* core clocks */
141 xxti, xusbxti, fin_pll, fout_apll, fout_mpll, fout_epll, fout_vpll,
142 sclk_apll, sclk_mpll, sclk_epll, sclk_vpll, arm_clk, aclk200, aclk100,
143 aclk160, aclk133, mout_mpll_user_t, mout_mpll_user_c, mout_core,
144 mout_apll, /* 20 */
145
146 /* gate for special clocks (sclk) */
147 sclk_fimc0 = 128, sclk_fimc1, sclk_fimc2, sclk_fimc3, sclk_cam0,
148 sclk_cam1, sclk_csis0, sclk_csis1, sclk_hdmi, sclk_mixer, sclk_dac,
149 sclk_pixel, sclk_fimd0, sclk_mdnie0, sclk_mdnie_pwm0, sclk_mipi0,
150 sclk_audio0, sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_mmc4,
151 sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4,
152 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
153 sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
154 sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp,
155 sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp,
156
157 /* gate clocks */
158 fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
159 smmu_fimc1, smmu_fimc2, smmu_fimc3, smmu_jpeg, vp, mixer, tvenc, hdmi,
160 smmu_tv, mfc, smmu_mfcl, smmu_mfcr, g3d, g2d, rotator, mdma, smmu_g2d,
161 smmu_rotator, smmu_mdma, fimd0, mie0, mdnie0, dsim0, smmu_fimd0, fimd1,
162 mie1, dsim1, smmu_fimd1, pdma0, pdma1, pcie_phy, sata_phy, tsi, sdmmc0,
163 sdmmc1, sdmmc2, sdmmc3, sdmmc4, sata, sromc, usb_host, usb_device, pcie,
164 onenand, nfcon, smmu_pcie, gps, smmu_gps, uart0, uart1, uart2, uart3,
165 uart4, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc,
166 spi0, spi1, spi2, i2s1, i2s2, pcm0, i2s0, pcm1, pcm2, pwm, slimbus,
167 spdif, ac97, modemif, chipid, sysreg, hdmi_cec, mct, wdt, rtc, keyif,
168 audss, mipi_hsi, mdma2, pixelasyncm0, pixelasyncm1, fimc_lite0,
169 fimc_lite1, ppmuispx, ppmuispmx, fimc_isp, fimc_drc, fimc_fd, mcuisp,
170 gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp,
171 mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp,
172 asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk,
173 spi1_isp_sclk, uart_isp_sclk,
174
175 /* mux clocks */
176 mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0,
177 mout_cam1, mout_csis0, mout_csis1, mout_g3d0, mout_g3d1, mout_g3d,
178 aclk400_mcuisp,
179
180 /* div clocks */
181 div_isp0 = 450, div_isp1, div_mcuisp0, div_mcuisp1, div_aclk200,
182 div_aclk400_mcuisp,
183
184 nr_clks,
185};
186
187/*
188 * list of controller registers to be saved and restored during a
189 * suspend/resume cycle.
190 */
191static __initdata unsigned long exynos4210_clk_save[] = {
192 E4210_SRC_IMAGE,
193 E4210_SRC_LCD1,
194 E4210_SRC_MASK_LCD1,
195 E4210_DIV_LCD1,
196 E4210_GATE_IP_IMAGE,
197 E4210_GATE_IP_LCD1,
198 E4210_GATE_IP_PERIR,
199 E4210_MPLL_CON0,
200};
201
202static __initdata unsigned long exynos4x12_clk_save[] = {
203 E4X12_GATE_IP_IMAGE,
204 E4X12_GATE_IP_PERIR,
205 E4X12_SRC_CAM1,
206 E4X12_DIV_ISP,
207 E4X12_DIV_CAM1,
208 E4X12_MPLL_CON0,
209};
210
211static __initdata unsigned long exynos4_clk_regs[] = {
212 SRC_LEFTBUS,
213 DIV_LEFTBUS,
214 GATE_IP_LEFTBUS,
215 SRC_RIGHTBUS,
216 DIV_RIGHTBUS,
217 GATE_IP_RIGHTBUS,
218 EPLL_CON0,
219 EPLL_CON1,
220 EPLL_CON2,
221 VPLL_CON0,
222 VPLL_CON1,
223 VPLL_CON2,
224 SRC_TOP0,
225 SRC_TOP1,
226 SRC_CAM,
227 SRC_TV,
228 SRC_MFC,
229 SRC_G3D,
230 SRC_LCD0,
231 SRC_MAUDIO,
232 SRC_FSYS,
233 SRC_PERIL0,
234 SRC_PERIL1,
235 SRC_MASK_TOP,
236 SRC_MASK_CAM,
237 SRC_MASK_TV,
238 SRC_MASK_LCD0,
239 SRC_MASK_MAUDIO,
240 SRC_MASK_FSYS,
241 SRC_MASK_PERIL0,
242 SRC_MASK_PERIL1,
243 DIV_TOP,
244 DIV_CAM,
245 DIV_TV,
246 DIV_MFC,
247 DIV_G3D,
248 DIV_IMAGE,
249 DIV_LCD0,
250 DIV_MAUDIO,
251 DIV_FSYS0,
252 DIV_FSYS1,
253 DIV_FSYS2,
254 DIV_FSYS3,
255 DIV_PERIL0,
256 DIV_PERIL1,
257 DIV_PERIL2,
258 DIV_PERIL3,
259 DIV_PERIL4,
260 DIV_PERIL5,
261 GATE_SCLK_CAM,
262 GATE_IP_CAM,
263 GATE_IP_TV,
264 GATE_IP_MFC,
265 GATE_IP_G3D,
266 GATE_IP_LCD0,
267 GATE_IP_FSYS,
268 GATE_IP_GPS,
269 GATE_IP_PERIL,
270 GATE_BLOCK,
271 SRC_MASK_DMC,
272 SRC_DMC,
273 DIV_DMC0,
274 DIV_DMC1,
275 GATE_IP_DMC,
276 APLL_CON0,
277 SRC_CPU,
278 DIV_CPU0,
279 DIV_CPU1,
280 GATE_SCLK_CPU,
281 GATE_IP_CPU,
282};
283
284/* list of all parent clock list */
285PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
286PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
287PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
288PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", };
289PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
290PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", };
291PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", };
292PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", };
293PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", };
294PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", };
295PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", };
296PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
297 "spdif_extclk", };
298PNAME(mout_onenand_p) = {"aclk133", "aclk160", };
299PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", };
300
301/* Exynos 4210-specific parent groups */
302PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", };
303PNAME(mout_core_p4210) = { "mout_apll", "sclk_mpll", };
304PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", };
305PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m",
306 "sclk_usbphy0", "none", "sclk_hdmiphy",
307 "sclk_mpll", "sclk_epll", "sclk_vpll", };
308PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m",
309 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
310 "sclk_epll", "sclk_vpll" };
311PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m",
312 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
313 "sclk_epll", "sclk_vpll", };
314PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m",
315 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
316 "sclk_epll", "sclk_vpll", };
317PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", };
318PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", };
319
320/* Exynos 4x12-specific parent groups */
321PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
322PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", };
323PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", };
324PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
325 "none", "sclk_hdmiphy", "mout_mpll_user_t",
326 "sclk_epll", "sclk_vpll", };
327PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m",
328 "sclk_usbphy0", "xxti", "xusbxti",
329 "mout_mpll_user_t", "sclk_epll", "sclk_vpll" };
330PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m",
331 "sclk_usbphy0", "xxti", "xusbxti",
332 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
333PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m",
334 "sclk_usbphy0", "xxti", "xusbxti",
335 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
336PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", };
337PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
338PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
339PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
340
341/* fixed rate clocks generated outside the soc */
342struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
343 FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0),
344 FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0),
345};
346
347/* fixed rate clocks generated inside the soc */
348struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
349 FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
350 FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
351 FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
352};
353
354struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
355 FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
356};
357
358/* list of mux clocks supported in all exynos4 soc's */
359struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
360 MUX_F(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
361 CLK_SET_RATE_PARENT, 0),
362 MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
363 MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
364 MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
365 MUX_F(mout_g3d1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
366 CLK_SET_RATE_PARENT, 0),
367 MUX_F(mout_g3d, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
368 CLK_SET_RATE_PARENT, 0),
369 MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
370 MUX(none, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
371 MUX_A(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, "sclk_epll"),
372 MUX(none, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
373};
374
375/* list of mux clocks supported in exynos4210 soc */
376struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
377 MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
378 MUX(none, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
379 MUX(none, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
380 MUX(none, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
381 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
382 MUX(none, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
383 MUX(none, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
384 MUX(none, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
385 MUX(none, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
386 MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
387 MUX(none, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
388 MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
389 MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "sclk_mpll"),
390 MUX_A(mout_core, "mout_core", mout_core_p4210,
391 SRC_CPU, 16, 1, "mout_core"),
392 MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210,
393 SRC_TOP0, 8, 1, "sclk_vpll"),
394 MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
395 MUX(mout_fimc1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
396 MUX(mout_fimc2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
397 MUX(mout_fimc3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4),
398 MUX(mout_cam0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4),
399 MUX(mout_cam1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4),
400 MUX(mout_csis0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
401 MUX(mout_csis1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
402 MUX(none, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
403 MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
404 CLK_SET_RATE_PARENT, 0),
405 MUX(none, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
406 MUX(none, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
407 MUX(none, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
408 MUX(none, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4),
409 MUX(none, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4),
410 MUX(none, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
411 MUX(none, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
412 MUX(none, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
413 MUX(none, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1),
414 MUX(none, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
415 MUX(none, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
416 MUX(none, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),
417 MUX(none, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4),
418 MUX(none, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4),
419 MUX(none, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4),
420 MUX(none, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4),
421 MUX(none, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
422 MUX(none, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
423 MUX(none, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
424};
425
426/* list of mux clocks supported in exynos4x12 soc */
427struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
428 MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12,
429 SRC_CPU, 24, 1),
430 MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
431 MUX(none, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
432 MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12,
433 SRC_TOP1, 12, 1),
434 MUX(none, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12,
435 SRC_TOP1, 16, 1),
436 MUX(aclk200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1),
437 MUX(aclk400_mcuisp, "aclk400_mcuisp", mout_user_aclk400_mcuisp_p4x12,
438 SRC_TOP1, 24, 1),
439 MUX(none, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
440 MUX(none, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
441 MUX(none, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
442 MUX(none, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1),
443 MUX(none, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4),
444 MUX(none, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4),
445 MUX(none, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1),
446 MUX(none, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
447 MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
448 MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
449 MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p,
450 SRC_DMC, 12, 1, "sclk_mpll"),
451 MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p,
452 SRC_TOP0, 8, 1, "sclk_vpll"),
453 MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
454 MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
455 MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
456 MUX(mout_fimc2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
457 MUX(mout_fimc3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4),
458 MUX(mout_cam0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4),
459 MUX(mout_cam1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4),
460 MUX(mout_csis0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
461 MUX(mout_csis1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
462 MUX(none, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
463 MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
464 CLK_SET_RATE_PARENT, 0),
465 MUX(none, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
466 MUX(none, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
467 MUX(none, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
468 MUX(none, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4),
469 MUX(none, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4),
470 MUX(none, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
471 MUX(none, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
472 MUX(none, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
473 MUX(none, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),
474 MUX(none, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
475 MUX(none, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
476 MUX(none, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),
477 MUX(none, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4),
478 MUX(none, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4),
479 MUX(none, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4),
480 MUX(none, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4),
481 MUX(none, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4),
482 MUX(none, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4),
483 MUX(none, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4),
484 MUX(none, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4),
485 MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
486 MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
487 MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
488};
489
490/* list of divider clocks supported in all exynos4 soc's */
491struct samsung_div_clock exynos4_div_clks[] __initdata = {
492 DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3),
493 DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3),
494 DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
495 DIV(none, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
496 DIV(none, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
497 DIV(none, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
498 DIV(none, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
499 DIV(none, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
500 DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
501 DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
502 DIV(sclk_mfc, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
503 DIV_F(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4,
504 CLK_SET_RATE_PARENT, 0),
505 DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
506 DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
507 DIV(none, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
508 DIV(sclk_pcm0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
509 DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
510 DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
511 DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
512 DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
513 DIV(sclk_pixel, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
514 DIV(aclk100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
515 DIV(aclk160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
516 DIV(aclk133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
517 DIV(none, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
518 DIV(sclk_slimbus, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
519 DIV(sclk_pcm1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
520 DIV(sclk_pcm2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
521 DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
522 DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
523 DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
524 DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8),
525 DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
526 DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
527 DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
528 DIV(none, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
529 DIV(none, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
530 DIV(none, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
531 DIV(none, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
532 DIV(none, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
533 DIV(none, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
534 DIV(none, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
535 DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
536 DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
537 DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
538 DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "arm_clk"),
539 DIV_A(sclk_apll, "sclk_apll", "mout_apll",
540 DIV_CPU0, 24, 3, "sclk_apll"),
541 DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
542 CLK_SET_RATE_PARENT, 0),
543 DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
544 CLK_SET_RATE_PARENT, 0),
545 DIV_F(none, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
546 CLK_SET_RATE_PARENT, 0),
547 DIV_F(none, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
548 CLK_SET_RATE_PARENT, 0),
549 DIV_F(none, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
550 CLK_SET_RATE_PARENT, 0),
551};
552
553/* list of divider clocks supported in exynos4210 soc */
554struct samsung_div_clock exynos4210_div_clks[] __initdata = {
555 DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
556 DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4),
557 DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
558 DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
559 DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
560 DIV_F(none, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4,
561 CLK_SET_RATE_PARENT, 0),
562};
563
564/* list of divider clocks supported in exynos4x12 soc */
565struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
566 DIV(none, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
567 DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
568 DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
569 DIV(none, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
570 DIV(none, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
571 DIV(div_aclk200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3),
572 DIV(none, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3),
573 DIV(div_aclk400_mcuisp, "div_aclk400_mcuisp", "mout_aclk400_mcuisp",
574 DIV_TOP, 24, 3),
575 DIV(none, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4),
576 DIV(none, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4),
577 DIV(none, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8),
578 DIV(none, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
579 DIV(none, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
580 DIV(none, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
581 DIV(div_isp0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3),
582 DIV(div_isp1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3),
583 DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
584 DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3),
585 DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3),
586};
587
588/* list of gate clocks supported in all exynos4 soc's */
589struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
590 /*
591 * After all Exynos4 based platforms are migrated to use device tree,
592 * the device name and clock alias names specified below for some
593 * of the clocks can be removed.
594 */
595 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
596 GATE(sclk_spdif, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, 0),
597 GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
598 GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
599 GATE(dsim0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
600 GATE(fimd1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0),
601 GATE(mie1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0),
602 GATE(dsim1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0),
603 GATE(smmu_fimd1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0, 0),
604 GATE(tsi, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
605 GATE(sromc, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
606 GATE(sclk_g3d, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0,
607 CLK_SET_RATE_PARENT, 0),
608 GATE(usb_device, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
609 GATE(onenand, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
610 GATE(nfcon, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
611 GATE(gps, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
612 GATE(smmu_gps, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
613 GATE(slimbus, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
614 GATE(sclk_cam0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
615 CLK_SET_RATE_PARENT, 0),
616 GATE(sclk_cam1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5,
617 CLK_SET_RATE_PARENT, 0),
618 GATE(sclk_mipi0, "sclk_mipi0", "div_mipi_pre0",
619 SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
620 GATE(sclk_audio0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
621 CLK_SET_RATE_PARENT, 0),
622 GATE(sclk_audio1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,
623 CLK_SET_RATE_PARENT, 0),
624 GATE_D(vp, "s5p-mixer", "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
625 GATE_D(mixer, "s5p-mixer", "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
626 GATE_D(hdmi, "exynos4-hdmi", "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
627 GATE_A(pwm, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0, "timers"),
628 GATE_A(sdmmc4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0, "biu"),
629 GATE_A(usb_host, "usb_host", "aclk133",
630 GATE_IP_FSYS, 12, 0, 0, "usbhost"),
631 GATE_DA(sclk_fimc0, "exynos4-fimc.0", "sclk_fimc0", "div_fimc0",
632 SRC_MASK_CAM, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
633 GATE_DA(sclk_fimc1, "exynos4-fimc.1", "sclk_fimc1", "div_fimc1",
634 SRC_MASK_CAM, 4, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
635 GATE_DA(sclk_fimc2, "exynos4-fimc.2", "sclk_fimc2", "div_fimc2",
636 SRC_MASK_CAM, 8, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
637 GATE_DA(sclk_fimc3, "exynos4-fimc.3", "sclk_fimc3", "div_fimc3",
638 SRC_MASK_CAM, 12, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
639 GATE_DA(sclk_csis0, "s5p-mipi-csis.0", "sclk_csis0", "div_csis0",
640 SRC_MASK_CAM, 24, CLK_SET_RATE_PARENT, 0, "sclk_csis"),
641 GATE_DA(sclk_csis1, "s5p-mipi-csis.1", "sclk_csis1", "div_csis1",
642 SRC_MASK_CAM, 28, CLK_SET_RATE_PARENT, 0, "sclk_csis"),
643 GATE_DA(sclk_fimd0, "exynos4-fb.0", "sclk_fimd0", "div_fimd0",
644 SRC_MASK_LCD0, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),
645 GATE_DA(sclk_mmc0, "exynos4-sdhci.0", "sclk_mmc0", "div_mmc_pre0",
646 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0,
647 "mmc_busclk.2"),
648 GATE_DA(sclk_mmc1, "exynos4-sdhci.1", "sclk_mmc1", "div_mmc_pre1",
649 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0,
650 "mmc_busclk.2"),
651 GATE_DA(sclk_mmc2, "exynos4-sdhci.2", "sclk_mmc2", "div_mmc_pre2",
652 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0,
653 "mmc_busclk.2"),
654 GATE_DA(sclk_mmc3, "exynos4-sdhci.3", "sclk_mmc3", "div_mmc_pre3",
655 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0,
656 "mmc_busclk.2"),
657 GATE_DA(sclk_mmc4, NULL, "sclk_mmc4", "div_mmc_pre4",
658 SRC_MASK_FSYS, 16, CLK_SET_RATE_PARENT, 0, "ciu"),
659 GATE_DA(sclk_uart0, "exynos4210-uart.0", "uclk0", "div_uart0",
660 SRC_MASK_PERIL0, 0, CLK_SET_RATE_PARENT,
661 0, "clk_uart_baud0"),
662 GATE_DA(sclk_uart1, "exynos4210-uart.1", "uclk1", "div_uart1",
663 SRC_MASK_PERIL0, 4, CLK_SET_RATE_PARENT,
664 0, "clk_uart_baud0"),
665 GATE_DA(sclk_uart2, "exynos4210-uart.2", "uclk2", "div_uart2",
666 SRC_MASK_PERIL0, 8, CLK_SET_RATE_PARENT,
667 0, "clk_uart_baud0"),
668 GATE_DA(sclk_uart3, "exynos4210-uart.3", "uclk3", "div_uart3",
669 SRC_MASK_PERIL0, 12, CLK_SET_RATE_PARENT,
670 0, "clk_uart_baud0"),
671 GATE_DA(sclk_uart4, "exynos4210-uart.4", "uclk4", "div_uart4",
672 SRC_MASK_PERIL0, 16, CLK_SET_RATE_PARENT,
673 0, "clk_uart_baud0"),
674 GATE(sclk_audio2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4,
675 CLK_SET_RATE_PARENT, 0),
676 GATE_DA(sclk_spi0, "exynos4210-spi.0", "sclk_spi0", "div_spi_pre0",
677 SRC_MASK_PERIL1, 16, CLK_SET_RATE_PARENT,
678 0, "spi_busclk0"),
679 GATE_DA(sclk_spi1, "exynos4210-spi.1", "sclk_spi1", "div_spi_pre1",
680 SRC_MASK_PERIL1, 20, CLK_SET_RATE_PARENT,
681 0, "spi_busclk0"),
682 GATE_DA(sclk_spi2, "exynos4210-spi.2", "sclk_spi2", "div_spi_pre2",
683 SRC_MASK_PERIL1, 24, CLK_SET_RATE_PARENT,
684 0, "spi_busclk0"),
685 GATE_DA(fimc0, "exynos4-fimc.0", "fimc0", "aclk160",
686 GATE_IP_CAM, 0, 0, 0, "fimc"),
687 GATE_DA(fimc1, "exynos4-fimc.1", "fimc1", "aclk160",
688 GATE_IP_CAM, 1, 0, 0, "fimc"),
689 GATE_DA(fimc2, "exynos4-fimc.2", "fimc2", "aclk160",
690 GATE_IP_CAM, 2, 0, 0, "fimc"),
691 GATE_DA(fimc3, "exynos4-fimc.3", "fimc3", "aclk160",
692 GATE_IP_CAM, 3, 0, 0, "fimc"),
693 GATE_DA(csis0, "s5p-mipi-csis.0", "csis0", "aclk160",
694 GATE_IP_CAM, 4, 0, 0, "fimc"),
695 GATE_DA(csis1, "s5p-mipi-csis.1", "csis1", "aclk160",
696 GATE_IP_CAM, 5, 0, 0, "fimc"),
697 GATE_DA(smmu_fimc0, "exynos-sysmmu.5", "smmu_fimc0", "aclk160",
698 GATE_IP_CAM, 7, 0, 0, "sysmmu"),
699 GATE_DA(smmu_fimc1, "exynos-sysmmu.6", "smmu_fimc1", "aclk160",
700 GATE_IP_CAM, 8, 0, 0, "sysmmu"),
701 GATE_DA(smmu_fimc2, "exynos-sysmmu.7", "smmu_fimc2", "aclk160",
702 GATE_IP_CAM, 9, 0, 0, "sysmmu"),
703 GATE_DA(smmu_fimc3, "exynos-sysmmu.8", "smmu_fimc3", "aclk160",
704 GATE_IP_CAM, 10, 0, 0, "sysmmu"),
705 GATE_DA(smmu_jpeg, "exynos-sysmmu.3", "smmu_jpeg", "aclk160",
706 GATE_IP_CAM, 11, 0, 0, "sysmmu"),
707 GATE(pixelasyncm0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
708 GATE(pixelasyncm1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
709 GATE_DA(smmu_tv, "exynos-sysmmu.2", "smmu_tv", "aclk160",
710 GATE_IP_TV, 4, 0, 0, "sysmmu"),
711 GATE_DA(mfc, "s5p-mfc", "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0, "mfc"),
712 GATE_DA(smmu_mfcl, "exynos-sysmmu.0", "smmu_mfcl", "aclk100",
713 GATE_IP_MFC, 1, 0, 0, "sysmmu"),
714 GATE_DA(smmu_mfcr, "exynos-sysmmu.1", "smmu_mfcr", "aclk100",
715 GATE_IP_MFC, 2, 0, 0, "sysmmu"),
716 GATE_DA(fimd0, "exynos4-fb.0", "fimd0", "aclk160",
717 GATE_IP_LCD0, 0, 0, 0, "fimd"),
718 GATE_DA(smmu_fimd0, "exynos-sysmmu.10", "smmu_fimd0", "aclk160",
719 GATE_IP_LCD0, 4, 0, 0, "sysmmu"),
720 GATE_DA(pdma0, "dma-pl330.0", "pdma0", "aclk133",
721 GATE_IP_FSYS, 0, 0, 0, "dma"),
722 GATE_DA(pdma1, "dma-pl330.1", "pdma1", "aclk133",
723 GATE_IP_FSYS, 1, 0, 0, "dma"),
724 GATE_DA(sdmmc0, "exynos4-sdhci.0", "sdmmc0", "aclk133",
725 GATE_IP_FSYS, 5, 0, 0, "hsmmc"),
726 GATE_DA(sdmmc1, "exynos4-sdhci.1", "sdmmc1", "aclk133",
727 GATE_IP_FSYS, 6, 0, 0, "hsmmc"),
728 GATE_DA(sdmmc2, "exynos4-sdhci.2", "sdmmc2", "aclk133",
729 GATE_IP_FSYS, 7, 0, 0, "hsmmc"),
730 GATE_DA(sdmmc3, "exynos4-sdhci.3", "sdmmc3", "aclk133",
731 GATE_IP_FSYS, 8, 0, 0, "hsmmc"),
732 GATE_DA(uart0, "exynos4210-uart.0", "uart0", "aclk100",
733 GATE_IP_PERIL, 0, 0, 0, "uart"),
734 GATE_DA(uart1, "exynos4210-uart.1", "uart1", "aclk100",
735 GATE_IP_PERIL, 1, 0, 0, "uart"),
736 GATE_DA(uart2, "exynos4210-uart.2", "uart2", "aclk100",
737 GATE_IP_PERIL, 2, 0, 0, "uart"),
738 GATE_DA(uart3, "exynos4210-uart.3", "uart3", "aclk100",
739 GATE_IP_PERIL, 3, 0, 0, "uart"),
740 GATE_DA(uart4, "exynos4210-uart.4", "uart4", "aclk100",
741 GATE_IP_PERIL, 4, 0, 0, "uart"),
742 GATE_DA(i2c0, "s3c2440-i2c.0", "i2c0", "aclk100",
743 GATE_IP_PERIL, 6, 0, 0, "i2c"),
744 GATE_DA(i2c1, "s3c2440-i2c.1", "i2c1", "aclk100",
745 GATE_IP_PERIL, 7, 0, 0, "i2c"),
746 GATE_DA(i2c2, "s3c2440-i2c.2", "i2c2", "aclk100",
747 GATE_IP_PERIL, 8, 0, 0, "i2c"),
748 GATE_DA(i2c3, "s3c2440-i2c.3", "i2c3", "aclk100",
749 GATE_IP_PERIL, 9, 0, 0, "i2c"),
750 GATE_DA(i2c4, "s3c2440-i2c.4", "i2c4", "aclk100",
751 GATE_IP_PERIL, 10, 0, 0, "i2c"),
752 GATE_DA(i2c5, "s3c2440-i2c.5", "i2c5", "aclk100",
753 GATE_IP_PERIL, 11, 0, 0, "i2c"),
754 GATE_DA(i2c6, "s3c2440-i2c.6", "i2c6", "aclk100",
755 GATE_IP_PERIL, 12, 0, 0, "i2c"),
756 GATE_DA(i2c7, "s3c2440-i2c.7", "i2c7", "aclk100",
757 GATE_IP_PERIL, 13, 0, 0, "i2c"),
758 GATE_DA(i2c_hdmi, "s3c2440-hdmiphy-i2c", "i2c-hdmi", "aclk100",
759 GATE_IP_PERIL, 14, 0, 0, "i2c"),
760 GATE_DA(spi0, "exynos4210-spi.0", "spi0", "aclk100",
761 GATE_IP_PERIL, 16, 0, 0, "spi"),
762 GATE_DA(spi1, "exynos4210-spi.1", "spi1", "aclk100",
763 GATE_IP_PERIL, 17, 0, 0, "spi"),
764 GATE_DA(spi2, "exynos4210-spi.2", "spi2", "aclk100",
765 GATE_IP_PERIL, 18, 0, 0, "spi"),
766 GATE_DA(i2s1, "samsung-i2s.1", "i2s1", "aclk100",
767 GATE_IP_PERIL, 20, 0, 0, "iis"),
768 GATE_DA(i2s2, "samsung-i2s.2", "i2s2", "aclk100",
769 GATE_IP_PERIL, 21, 0, 0, "iis"),
770 GATE_DA(pcm1, "samsung-pcm.1", "pcm1", "aclk100",
771 GATE_IP_PERIL, 22, 0, 0, "pcm"),
772 GATE_DA(pcm2, "samsung-pcm.2", "pcm2", "aclk100",
773 GATE_IP_PERIL, 23, 0, 0, "pcm"),
774 GATE_DA(spdif, "samsung-spdif", "spdif", "aclk100",
775 GATE_IP_PERIL, 26, 0, 0, "spdif"),
776 GATE_DA(ac97, "samsung-ac97", "ac97", "aclk100",
777 GATE_IP_PERIL, 27, 0, 0, "ac97"),
778};
779
780/* list of gate clocks supported in exynos4210 soc */
781struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
782 GATE(tvenc, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
783 GATE(g2d, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
784 GATE(rotator, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
785 GATE(mdma, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0),
786 GATE(smmu_g2d, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
787 GATE(smmu_mdma, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, 0),
788 GATE(pcie_phy, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
789 GATE(sata_phy, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
790 GATE(sata, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
791 GATE(pcie, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
792 GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
793 GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
794 GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
795 GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
796 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0),
797 GATE(smmu_rotator, "smmu_rotator", "aclk200",
798 E4210_GATE_IP_IMAGE, 4, 0, 0),
799 GATE(sclk_mipi1, "sclk_mipi1", "div_mipi_pre1",
800 E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
801 GATE(sclk_sata, "sclk_sata", "div_sata",
802 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
803 GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
804 GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
805 GATE_A(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 0, 0, "adc"),
806 GATE_A(mct, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, 0, 0, "mct"),
807 GATE_A(wdt, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, 0, 0, "watchdog"),
808 GATE_A(rtc, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, 0, 0, "rtc"),
809 GATE_A(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 0, 0, "keypad"),
810 GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1",
811 E4210_SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),
812};
813
814/* list of gate clocks supported in exynos4x12 soc */
815struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
816 GATE(audss, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
817 GATE(mdnie0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
818 GATE(rotator, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
819 GATE(mdma2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
820 GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0),
821 GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
822 GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
823 GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 0, 0),
824 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0),
825 GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0",
826 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
827 GATE(sclk_mdnie_pwm0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0",
828 SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0),
829 GATE(sclk_mipihsi, "sclk_mipihsi", "div_mipihsi",
830 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
831 GATE(smmu_rotator, "smmu_rotator", "aclk200",
832 E4X12_GATE_IP_IMAGE, 4, 0, 0),
833 GATE_A(mct, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, 0, 0, "mct"),
834 GATE_A(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 0, 0, "rtc"),
835 GATE_A(keyif, "keyif", "aclk100",
836 E4X12_GATE_IP_PERIR, 16, 0, 0, "keypad"),
837 GATE(sclk_pwm_isp, "sclk_pwm_isp", "div_pwm_isp",
838 E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0),
839 GATE(sclk_spi0_isp, "sclk_spi0_isp", "div_spi0_isp_pre",
840 E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0),
841 GATE(sclk_spi1_isp, "sclk_spi1_isp", "div_spi1_isp_pre",
842 E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0),
843 GATE(sclk_uart_isp, "sclk_uart_isp", "div_uart_isp",
844 E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0),
845 GATE(pwm_isp_sclk, "pwm_isp_sclk", "sclk_pwm_isp",
846 E4X12_GATE_IP_ISP, 0, 0, 0),
847 GATE(spi0_isp_sclk, "spi0_isp_sclk", "sclk_spi0_isp",
848 E4X12_GATE_IP_ISP, 1, 0, 0),
849 GATE(spi1_isp_sclk, "spi1_isp_sclk", "sclk_spi1_isp",
850 E4X12_GATE_IP_ISP, 2, 0, 0),
851 GATE(uart_isp_sclk, "uart_isp_sclk", "sclk_uart_isp",
852 E4X12_GATE_IP_ISP, 3, 0, 0),
853 GATE_A(wdt, "watchdog", "aclk100",
854 E4X12_GATE_IP_PERIR, 14, 0, 0, "watchdog"),
855 GATE_DA(pcm0, "samsung-pcm.0", "pcm0", "aclk100",
856 E4X12_GATE_IP_MAUDIO, 2, 0, 0, "pcm"),
857 GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100",
858 E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"),
859 GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0,
860 CLK_IGNORE_UNUSED, 0),
861 GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1,
862 CLK_IGNORE_UNUSED, 0),
863 GATE(fimc_fd, "fd", "aclk200", E4X12_GATE_ISP0, 2,
864 CLK_IGNORE_UNUSED, 0),
865 GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3,
866 CLK_IGNORE_UNUSED, 0),
867 GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4,
868 CLK_IGNORE_UNUSED, 0),
869 GATE(mcuisp, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5,
870 CLK_IGNORE_UNUSED, 0),
871 GATE(gicisp, "gicisp", "aclk200", E4X12_GATE_ISP0, 7,
872 CLK_IGNORE_UNUSED, 0),
873 GATE(smmu_isp, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8,
874 CLK_IGNORE_UNUSED, 0),
875 GATE(smmu_drc, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9,
876 CLK_IGNORE_UNUSED, 0),
877 GATE(smmu_fd, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10,
878 CLK_IGNORE_UNUSED, 0),
879 GATE(smmu_lite0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
880 CLK_IGNORE_UNUSED, 0),
881 GATE(smmu_lite1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
882 CLK_IGNORE_UNUSED, 0),
883 GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
884 CLK_IGNORE_UNUSED, 0),
885 GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
886 CLK_IGNORE_UNUSED, 0),
887 GATE(mcuctl_isp, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
888 CLK_IGNORE_UNUSED, 0),
889 GATE(mpwm_isp, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
890 CLK_IGNORE_UNUSED, 0),
891 GATE(i2c0_isp, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
892 CLK_IGNORE_UNUSED, 0),
893 GATE(i2c1_isp, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
894 CLK_IGNORE_UNUSED, 0),
895 GATE(mtcadc_isp, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
896 CLK_IGNORE_UNUSED, 0),
897 GATE(pwm_isp, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28,
898 CLK_IGNORE_UNUSED, 0),
899 GATE(wdt_isp, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30,
900 CLK_IGNORE_UNUSED, 0),
901 GATE(uart_isp, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
902 CLK_IGNORE_UNUSED, 0),
903 GATE(asyncaxim, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
904 CLK_IGNORE_UNUSED, 0),
905 GATE(smmu_ispcx, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
906 CLK_IGNORE_UNUSED, 0),
907 GATE(spi0_isp, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
908 CLK_IGNORE_UNUSED, 0),
909 GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
910 CLK_IGNORE_UNUSED, 0),
911};
912
913#ifdef CONFIG_OF
914static struct of_device_id exynos4_clk_ids[] __initdata = {
915 { .compatible = "samsung,exynos4210-clock",
916 .data = (void *)EXYNOS4210, },
917 { .compatible = "samsung,exynos4412-clock",
918 .data = (void *)EXYNOS4X12, },
919 { },
920};
921#endif
922
923/*
924 * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
925 * resides in chipid register space, outside of the clock controller memory
926 * mapped space. So to determine the parent of fin_pll clock, the chipid
927 * controller is first remapped and the value of XOM[0] bit is read to
928 * determine the parent clock.
929 */
930static void __init exynos4_clk_register_finpll(void)
931{
932 struct samsung_fixed_rate_clock fclk;
933 struct device_node *np;
934 struct clk *clk;
935 void __iomem *chipid_base = S5P_VA_CHIPID;
936 unsigned long xom, finpll_f = 24000000;
937 char *parent_name;
938
939 np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
940 if (np)
941 chipid_base = of_iomap(np, 0);
942
943 if (chipid_base) {
944 xom = readl(chipid_base + 8);
945 parent_name = xom & 1 ? "xusbxti" : "xxti";
946 clk = clk_get(NULL, parent_name);
947 if (IS_ERR(clk)) {
948 pr_err("%s: failed to lookup parent clock %s, assuming "
949 "fin_pll clock frequency is 24MHz\n", __func__,
950 parent_name);
951 } else {
952 finpll_f = clk_get_rate(clk);
953 }
954 } else {
955 pr_err("%s: failed to map chipid registers, assuming "
956 "fin_pll clock frequency is 24MHz\n", __func__);
957 }
958
959 fclk.id = fin_pll;
960 fclk.name = "fin_pll";
961 fclk.parent_name = NULL;
962 fclk.flags = CLK_IS_ROOT;
963 fclk.fixed_rate = finpll_f;
964 samsung_clk_register_fixed_rate(&fclk, 1);
965
966 if (np)
967 iounmap(chipid_base);
968}
969
970/*
971 * This function allows non-dt platforms to specify the clock speed of the
972 * xxti and xusbxti clocks. These clocks are then registered with the specified
973 * clock speed.
974 */
975void __init exynos4_clk_register_fixed_ext(unsigned long xxti_f,
976 unsigned long xusbxti_f)
977{
978 exynos4_fixed_rate_ext_clks[0].fixed_rate = xxti_f;
979 exynos4_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f;
980 samsung_clk_register_fixed_rate(exynos4_fixed_rate_ext_clks,
981 ARRAY_SIZE(exynos4_fixed_rate_ext_clks));
982}
983
984static __initdata struct of_device_id ext_clk_match[] = {
985 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
986 { .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
987 {},
988};
989
990/* register exynos4 clocks */
991void __init exynos4_clk_init(struct device_node *np)
992{
993 void __iomem *reg_base;
994 struct clk *apll, *mpll, *epll, *vpll;
995 u32 exynos4_soc;
996
997 if (np) {
998 const struct of_device_id *match;
999 match = of_match_node(exynos4_clk_ids, np);
1000 exynos4_soc = (u32)match->data;
1001
1002 reg_base = of_iomap(np, 0);
1003 if (!reg_base)
1004 panic("%s: failed to map registers\n", __func__);
1005 } else {
1006 reg_base = S5P_VA_CMU;
1007 if (soc_is_exynos4210())
1008 exynos4_soc = EXYNOS4210;
1009 else if (soc_is_exynos4212() || soc_is_exynos4412())
1010 exynos4_soc = EXYNOS4X12;
1011 else
1012 panic("%s: unable to determine soc\n", __func__);
1013 }
1014
1015 if (exynos4_soc == EXYNOS4210)
1016 samsung_clk_init(np, reg_base, nr_clks,
1017 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
1018 exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save));
1019 else
1020 samsung_clk_init(np, reg_base, nr_clks,
1021 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
1022 exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save));
1023
1024 if (np)
1025 samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
1026 ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
1027 ext_clk_match);
1028
1029 exynos4_clk_register_finpll();
1030
1031 if (exynos4_soc == EXYNOS4210) {
1032 apll = samsung_clk_register_pll45xx("fout_apll", "fin_pll",
1033 reg_base + APLL_CON0, pll_4508);
1034 mpll = samsung_clk_register_pll45xx("fout_mpll", "fin_pll",
1035 reg_base + E4210_MPLL_CON0, pll_4508);
1036 epll = samsung_clk_register_pll46xx("fout_epll", "fin_pll",
1037 reg_base + EPLL_CON0, pll_4600);
1038 vpll = samsung_clk_register_pll46xx("fout_vpll", "mout_vpllsrc",
1039 reg_base + VPLL_CON0, pll_4650c);
1040 } else {
1041 apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
1042 reg_base + APLL_CON0);
1043 mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
1044 reg_base + E4X12_MPLL_CON0);
1045 epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
1046 reg_base + EPLL_CON0);
1047 vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll",
1048 reg_base + VPLL_CON0);
1049 }
1050
1051 samsung_clk_add_lookup(apll, fout_apll);
1052 samsung_clk_add_lookup(mpll, fout_mpll);
1053 samsung_clk_add_lookup(epll, fout_epll);
1054 samsung_clk_add_lookup(vpll, fout_vpll);
1055
1056 samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks,
1057 ARRAY_SIZE(exynos4_fixed_rate_clks));
1058 samsung_clk_register_mux(exynos4_mux_clks,
1059 ARRAY_SIZE(exynos4_mux_clks));
1060 samsung_clk_register_div(exynos4_div_clks,
1061 ARRAY_SIZE(exynos4_div_clks));
1062 samsung_clk_register_gate(exynos4_gate_clks,
1063 ARRAY_SIZE(exynos4_gate_clks));
1064
1065 if (exynos4_soc == EXYNOS4210) {
1066 samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks,
1067 ARRAY_SIZE(exynos4210_fixed_rate_clks));
1068 samsung_clk_register_mux(exynos4210_mux_clks,
1069 ARRAY_SIZE(exynos4210_mux_clks));
1070 samsung_clk_register_div(exynos4210_div_clks,
1071 ARRAY_SIZE(exynos4210_div_clks));
1072 samsung_clk_register_gate(exynos4210_gate_clks,
1073 ARRAY_SIZE(exynos4210_gate_clks));
1074 } else {
1075 samsung_clk_register_mux(exynos4x12_mux_clks,
1076 ARRAY_SIZE(exynos4x12_mux_clks));
1077 samsung_clk_register_div(exynos4x12_div_clks,
1078 ARRAY_SIZE(exynos4x12_div_clks));
1079 samsung_clk_register_gate(exynos4x12_gate_clks,
1080 ARRAY_SIZE(exynos4x12_gate_clks));
1081 }
1082
1083 pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
1084 "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
1085 exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
1086 _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
1087 _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
1088 _get_rate("arm_clk"));
1089}
1090CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4_clk_init);
1091CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4_clk_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 23:36:26 -0500