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authorTomasz Figa <t.figa@samsung.com>2014-05-13 09:05:06 -0400
committerTomasz Figa <t.figa@samsung.com>2014-05-14 13:41:32 -0400
commit2ce16c53422a17c0afea8203dd96ac1e7a142cf9 (patch)
tree3533cb9f1e2c7369cf4216f8d7bfb1541a94375f /drivers/clk/samsung/clk-exynos3250.c
parent3bc0c5a16d65ef2a2edb7326f5b77d6a5bcf08a5 (diff)
clk: samsung: exynos3250: Add clocks using common clock framework
This patch add new the clock drvier of Exynos3250 SoC based on Cortex-A7 using common clock framework. The CMU (Clock Management Unit) of Exynos3250 control PLLs(Phase Locked Loops) and generate system clocks for CPU, buses, and function clocks for individual IPs. The CMU of Exynos3250 includes following clock doamins: - CPU block for Cortex-A7 MPCore processor - LEFTBUS/RIGHTBUS block - TOP block for G3D/MFC/LCD0/ISP/CAM/FSYS/MFC/PERIL/PERIR Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Hyunhee Kim <hyunhee.kim@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Karol Wrona <k.wrona@samsung.com> Signed-off-by: YoungJun Cho <yj44.cho@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos3250.c')
-rw-r--r--drivers/clk/samsung/clk-exynos3250.c780
1 files changed, 780 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
new file mode 100644
index 000000000000..7a17bd40d1dd
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -0,0 +1,780 @@
1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Common Clock Framework support for Exynos3250 SoC.
9 */
10
11#include <linux/clk.h>
12#include <linux/clkdev.h>
13#include <linux/clk-provider.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/platform_device.h>
17#include <linux/syscore_ops.h>
18
19#include <dt-bindings/clock/exynos3250.h>
20
21#include "clk.h"
22#include "clk-pll.h"
23
24#define SRC_LEFTBUS 0x4200
25#define DIV_LEFTBUS 0x4500
26#define GATE_IP_LEFTBUS 0x4800
27#define SRC_RIGHTBUS 0x8200
28#define DIV_RIGHTBUS 0x8500
29#define GATE_IP_RIGHTBUS 0x8800
30#define GATE_IP_PERIR 0x8960
31#define MPLL_LOCK 0xc010
32#define MPLL_CON0 0xc110
33#define VPLL_LOCK 0xc020
34#define VPLL_CON0 0xc120
35#define UPLL_LOCK 0xc030
36#define UPLL_CON0 0xc130
37#define SRC_TOP0 0xc210
38#define SRC_TOP1 0xc214
39#define SRC_CAM 0xc220
40#define SRC_MFC 0xc228
41#define SRC_G3D 0xc22c
42#define SRC_LCD 0xc234
43#define SRC_ISP 0xc238
44#define SRC_FSYS 0xc240
45#define SRC_PERIL0 0xc250
46#define SRC_PERIL1 0xc254
47#define SRC_MASK_TOP 0xc310
48#define SRC_MASK_CAM 0xc320
49#define SRC_MASK_LCD 0xc334
50#define SRC_MASK_ISP 0xc338
51#define SRC_MASK_FSYS 0xc340
52#define SRC_MASK_PERIL0 0xc350
53#define SRC_MASK_PERIL1 0xc354
54#define DIV_TOP 0xc510
55#define DIV_CAM 0xc520
56#define DIV_MFC 0xc528
57#define DIV_G3D 0xc52c
58#define DIV_LCD 0xc534
59#define DIV_ISP 0xc538
60#define DIV_FSYS0 0xc540
61#define DIV_FSYS1 0xc544
62#define DIV_FSYS2 0xc548
63#define DIV_PERIL0 0xc550
64#define DIV_PERIL1 0xc554
65#define DIV_PERIL3 0xc55c
66#define DIV_PERIL4 0xc560
67#define DIV_PERIL5 0xc564
68#define DIV_CAM1 0xc568
69#define CLKDIV2_RATIO 0xc580
70#define GATE_SCLK_CAM 0xc820
71#define GATE_SCLK_MFC 0xc828
72#define GATE_SCLK_G3D 0xc82c
73#define GATE_SCLK_LCD 0xc834
74#define GATE_SCLK_ISP_TOP 0xc838
75#define GATE_SCLK_FSYS 0xc840
76#define GATE_SCLK_PERIL 0xc850
77#define GATE_IP_CAM 0xc920
78#define GATE_IP_MFC 0xc928
79#define GATE_IP_G3D 0xc92c
80#define GATE_IP_LCD 0xc934
81#define GATE_IP_ISP 0xc938
82#define GATE_IP_FSYS 0xc940
83#define GATE_IP_PERIL 0xc950
84#define GATE_BLOCK 0xc970
85#define APLL_LOCK 0x14000
86#define APLL_CON0 0x14100
87#define SRC_CPU 0x14200
88#define DIV_CPU0 0x14500
89#define DIV_CPU1 0x14504
90
91/* list of PLLs to be registered */
92enum exynos3250_plls {
93 apll, mpll, vpll, upll,
94 nr_plls
95};
96
97static void __iomem *reg_base;
98
99/*
100 * Support for CMU save/restore across system suspends
101 */
102#ifdef CONFIG_PM_SLEEP
103static struct samsung_clk_reg_dump *exynos3250_clk_regs;
104
105static unsigned long exynos3250_cmu_clk_regs[] __initdata = {
106 SRC_LEFTBUS,
107 DIV_LEFTBUS,
108 GATE_IP_LEFTBUS,
109 SRC_RIGHTBUS,
110 DIV_RIGHTBUS,
111 GATE_IP_RIGHTBUS,
112 GATE_IP_PERIR,
113 MPLL_LOCK,
114 MPLL_CON0,
115 VPLL_LOCK,
116 VPLL_CON0,
117 UPLL_LOCK,
118 UPLL_CON0,
119 SRC_TOP0,
120 SRC_TOP1,
121 SRC_CAM,
122 SRC_MFC,
123 SRC_G3D,
124 SRC_LCD,
125 SRC_ISP,
126 SRC_FSYS,
127 SRC_PERIL0,
128 SRC_PERIL1,
129 SRC_MASK_TOP,
130 SRC_MASK_CAM,
131 SRC_MASK_LCD,
132 SRC_MASK_ISP,
133 SRC_MASK_FSYS,
134 SRC_MASK_PERIL0,
135 SRC_MASK_PERIL1,
136 DIV_TOP,
137 DIV_CAM,
138 DIV_MFC,
139 DIV_G3D,
140 DIV_LCD,
141 DIV_ISP,
142 DIV_FSYS0,
143 DIV_FSYS1,
144 DIV_FSYS2,
145 DIV_PERIL0,
146 DIV_PERIL1,
147 DIV_PERIL3,
148 DIV_PERIL4,
149 DIV_PERIL5,
150 DIV_CAM1,
151 CLKDIV2_RATIO,
152 GATE_SCLK_CAM,
153 GATE_SCLK_MFC,
154 GATE_SCLK_G3D,
155 GATE_SCLK_LCD,
156 GATE_SCLK_ISP_TOP,
157 GATE_SCLK_FSYS,
158 GATE_SCLK_PERIL,
159 GATE_IP_CAM,
160 GATE_IP_MFC,
161 GATE_IP_G3D,
162 GATE_IP_LCD,
163 GATE_IP_ISP,
164 GATE_IP_FSYS,
165 GATE_IP_PERIL,
166 GATE_BLOCK,
167 APLL_LOCK,
168 SRC_CPU,
169 DIV_CPU0,
170 DIV_CPU1,
171};
172
173static int exynos3250_clk_suspend(void)
174{
175 samsung_clk_save(reg_base, exynos3250_clk_regs,
176 ARRAY_SIZE(exynos3250_cmu_clk_regs));
177 return 0;
178}
179
180static void exynos3250_clk_resume(void)
181{
182 samsung_clk_restore(reg_base, exynos3250_clk_regs,
183 ARRAY_SIZE(exynos3250_cmu_clk_regs));
184}
185
186static struct syscore_ops exynos3250_clk_syscore_ops = {
187 .suspend = exynos3250_clk_suspend,
188 .resume = exynos3250_clk_resume,
189};
190
191static void exynos3250_clk_sleep_init(void)
192{
193 exynos3250_clk_regs =
194 samsung_clk_alloc_reg_dump(exynos3250_cmu_clk_regs,
195 ARRAY_SIZE(exynos3250_cmu_clk_regs));
196 if (!exynos3250_clk_regs) {
197 pr_warn("%s: Failed to allocate sleep save data\n", __func__);
198 goto err;
199 }
200
201 register_syscore_ops(&exynos3250_clk_syscore_ops);
202 return;
203err:
204 kfree(exynos3250_clk_regs);
205}
206#else
207static inline void exynos3250_clk_sleep_init(void) { }
208#endif
209
210/* list of all parent clock list */
211PNAME(mout_vpllsrc_p) = { "fin_pll", };
212
213PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
214PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
215PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
216PNAME(mout_upll_p) = { "fin_pll", "fout_upll", };
217
218PNAME(mout_mpll_user_p) = { "fin_pll", "div_mpll_pre", };
219PNAME(mout_epll_user_p) = { "fin_pll", "mout_epll", };
220PNAME(mout_core_p) = { "mout_apll", "mout_mpll_user_c", };
221PNAME(mout_hpm_p) = { "mout_apll", "mout_mpll_user_c", };
222
223PNAME(mout_ebi_p) = { "div_aclk_200", "div_aclk_160", };
224PNAME(mout_ebi_1_p) = { "mout_ebi", "mout_vpll", };
225
226PNAME(mout_gdl_p) = { "mout_mpll_user_l", };
227PNAME(mout_gdr_p) = { "mout_mpll_user_r", };
228
229PNAME(mout_aclk_400_mcuisp_sub_p)
230 = { "fin_pll", "div_aclk_400_mcuisp", };
231PNAME(mout_aclk_266_0_p) = { "div_mpll_pre", "mout_vpll", };
232PNAME(mout_aclk_266_1_p) = { "mout_epll_user", };
233PNAME(mout_aclk_266_p) = { "mout_aclk_266_0", "mout_aclk_266_1", };
234PNAME(mout_aclk_266_sub_p) = { "fin_pll", "div_aclk_266", };
235
236PNAME(group_div_mpll_pre_p) = { "div_mpll_pre", };
237PNAME(group_epll_vpll_p) = { "mout_epll_user", "mout_vpll" };
238PNAME(group_sclk_p) = { "xxti", "xusbxti",
239 "none", "none",
240 "none", "none", "div_mpll_pre",
241 "mout_epll_user", "mout_vpll", };
242PNAME(group_sclk_audio_p) = { "audiocdclk", "none",
243 "none", "none",
244 "xxti", "xusbxti",
245 "div_mpll_pre", "mout_epll_user",
246 "mout_vpll", };
247PNAME(group_sclk_cam_blk_p) = { "xxti", "xusbxti",
248 "none", "none", "none",
249 "none", "div_mpll_pre",
250 "mout_epll_user", "mout_vpll",
251 "div_cam_blk_320", };
252PNAME(group_sclk_fimd0_p) = { "xxti", "xusbxti",
253 "m_bitclkhsdiv4_2l", "none",
254 "none", "none", "div_mpll_pre",
255 "mout_epll_user", "mout_vpll",
256 "none", "none", "none",
257 "div_lcd_blk_145", };
258
259PNAME(mout_mfc_p) = { "mout_mfc_0", "mout_mfc_1" };
260PNAME(mout_g3d_p) = { "mout_g3d_0", "mout_g3d_1" };
261
262static struct samsung_fixed_factor_clock fixed_factor_clks[] __initdata = {
263 FFACTOR(0, "sclk_mpll_1600", "mout_mpll", 1, 1, 0),
264 FFACTOR(0, "sclk_mpll_mif", "mout_mpll", 1, 2, 0),
265 FFACTOR(0, "sclk_bpll", "fout_bpll", 1, 2, 0),
266 FFACTOR(0, "div_cam_blk_320", "sclk_mpll_1600", 1, 5, 0),
267 FFACTOR(0, "div_lcd_blk_145", "sclk_mpll_1600", 1, 11, 0),
268
269 /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */
270 FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
271};
272
273static struct samsung_mux_clock mux_clks[] __initdata = {
274 /*
275 * NOTE: Following table is sorted by register address in ascending
276 * order and then bitfield shift in descending order, as it is done
277 * in the User's Manual. When adding new entries, please make sure
278 * that the order is preserved, to avoid merge conflicts and make
279 * further work with defined data easier.
280 */
281
282 /* SRC_LEFTBUS */
283 MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
284 SRC_LEFTBUS, 4, 1),
285 MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
286
287 /* SRC_RIGHTBUS */
288 MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
289 SRC_RIGHTBUS, 4, 1),
290 MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
291
292 /* SRC_TOP0 */
293 MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
294 MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1),
295 MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1),
296 MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1),
297 MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1),
298 MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, SRC_TOP0, 13, 1),
299 MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p, SRC_TOP0, 12, 1),
300 MUX(CLK_MOUT_VPLL, "mout_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
301 MUX(CLK_MOUT_EPLL_USER, "mout_epll_user", mout_epll_user_p, SRC_TOP0, 4, 1),
302 MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
303
304 /* SRC_TOP1 */
305 MUX(CLK_MOUT_UPLL, "mout_upll", mout_upll_p, SRC_TOP1, 28, 1),
306 MUX(CLK_MOUT_ACLK_400_MCUISP_SUB, "mout_aclk_400_mcuisp_sub", mout_aclk_400_mcuisp_sub_p,
307 SRC_TOP1, 24, 1),
308 MUX(CLK_MOUT_ACLK_266_SUB, "mout_aclk_266_sub", mout_aclk_266_sub_p, SRC_TOP1, 20, 1),
309 MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_TOP1, 12, 1),
310 MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp", group_div_mpll_pre_p, SRC_TOP1, 8, 1),
311 MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
312
313 /* SRC_CAM */
314 MUX(CLK_MOUT_CAM1, "mout_cam1", group_sclk_p, SRC_CAM, 20, 4),
315 MUX(CLK_MOUT_CAM_BLK, "mout_cam_blk", group_sclk_cam_blk_p, SRC_CAM, 0, 4),
316
317 /* SRC_MFC */
318 MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
319 MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_vpll_p, SRC_MFC, 4, 1),
320 MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_div_mpll_pre_p, SRC_MFC, 0, 1),
321
322 /* SRC_G3D */
323 MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
324 MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_vpll_p, SRC_G3D, 4, 1),
325 MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_div_mpll_pre_p, SRC_G3D, 0, 1),
326
327 /* SRC_LCD */
328 MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_sclk_p, SRC_LCD, 12, 4),
329 MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
330
331 /* SRC_ISP */
332 MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_sclk_p, SRC_ISP, 12, 4),
333 MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_sclk_p, SRC_ISP, 8, 4),
334 MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_sclk_p, SRC_ISP, 4, 4),
335
336 /* SRC_FSYS */
337 MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
338 MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 3),
339 MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 3),
340
341 /* SRC_PERIL0 */
342 MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
343 MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
344
345 /* SRC_PERIL1 */
346 MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),
347 MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),
348 MUX(CLK_MOUT_AUDIO, "mout_audio", group_sclk_audio_p, SRC_PERIL1, 4, 4),
349
350 /* SRC_CPU */
351 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
352 SRC_CPU, 24, 1),
353 MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
354 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1),
355 MUX(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
356};
357
358static struct samsung_div_clock div_clks[] __initdata = {
359 /*
360 * NOTE: Following table is sorted by register address in ascending
361 * order and then bitfield shift in descending order, as it is done
362 * in the User's Manual. When adding new entries, please make sure
363 * that the order is preserved, to avoid merge conflicts and make
364 * further work with defined data easier.
365 */
366
367 /* DIV_LEFTBUS */
368 DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
369 DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
370
371 /* DIV_RIGHTBUS */
372 DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
373 DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
374
375 /* DIV_TOP */
376 DIV(CLK_DIV_MPLL_PRE, "div_mpll_pre", "sclk_mpll_mif", DIV_TOP, 28, 2),
377 DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",
378 "mout_aclk_400_mcuisp", DIV_TOP, 24, 3),
379 DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),
380 DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),
381 DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
382 DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),
383 DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),
384
385 /* DIV_CAM */
386 DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
387 DIV(CLK_DIV_CAM_BLK, "div_cam_blk", "mout_cam_blk", DIV_CAM, 0, 4),
388
389 /* DIV_MFC */
390 DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
391
392 /* DIV_G3D */
393 DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
394
395 /* DIV_LCD */
396 DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
397 CLK_SET_RATE_PARENT, 0),
398 DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),
399 DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),
400
401 /* DIV_ISP */
402 DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),
403 DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
404 DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
405 DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
406 DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
407 DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
408 DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 0, 4),
409
410 /* DIV_FSYS0 */
411 DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
412 CLK_SET_RATE_PARENT, 0),
413 DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),
414
415 /* DIV_FSYS1 */
416 DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
417 CLK_SET_RATE_PARENT, 0),
418 DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
419 DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
420 CLK_SET_RATE_PARENT, 0),
421 DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
422
423 /* DIV_PERIL0 */
424 DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
425 DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
426
427 /* DIV_PERIL1 */
428 DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
429 CLK_SET_RATE_PARENT, 0),
430 DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
431 DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
432 CLK_SET_RATE_PARENT, 0),
433 DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
434
435 /* DIV_PERIL4 */
436 DIV(CLK_DIV_PCM, "div_pcm", "div_audio", DIV_PERIL4, 20, 8),
437 DIV(CLK_DIV_AUDIO, "div_audio", "mout_audio", DIV_PERIL4, 16, 4),
438
439 /* DIV_PERIL5 */
440 DIV(CLK_DIV_I2S, "div_i2s", "div_audio", DIV_PERIL5, 8, 6),
441
442 /* DIV_CPU0 */
443 DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
444 DIV(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
445 DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
446 DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
447 DIV(CLK_DIV_COREM, "div_corem", "div_core2", DIV_CPU0, 4, 3),
448 DIV(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3),
449
450 /* DIV_CPU1 */
451 DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
452 DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
453};
454
455static struct samsung_gate_clock gate_clks[] __initdata = {
456 /*
457 * NOTE: Following table is sorted by register address in ascending
458 * order and then bitfield shift in descending order, as it is done
459 * in the User's Manual. When adding new entries, please make sure
460 * that the order is preserved, to avoid merge conflicts and make
461 * further work with defined data easier.
462 */
463
464 /* GATE_IP_LEFTBUS */
465 GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
466 CLK_IGNORE_UNUSED, 0),
467 GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
468 CLK_IGNORE_UNUSED, 0),
469 GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
470 CLK_IGNORE_UNUSED, 0),
471 GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
472 CLK_IGNORE_UNUSED, 0),
473
474 /* GATE_IP_RIGHTBUS */
475 GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
476 GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),
477 GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
478 GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
479 GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
480 GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),
481 GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,
482 CLK_IGNORE_UNUSED, 0),
483 GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1,
484 CLK_IGNORE_UNUSED, 0),
485 GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100", GATE_IP_RIGHTBUS, 0,
486 CLK_IGNORE_UNUSED, 0),
487
488 /* GATE_IP_PERIR */
489 GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
490 CLK_IGNORE_UNUSED, 0),
491 GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
492 CLK_IGNORE_UNUSED, 0),
493 GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
494 GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),
495 GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
496 GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),
497 GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
498 CLK_IGNORE_UNUSED, 0),
499 GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
500 GATE_IP_PERIR, 17, 0, 0),
501 GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
502 GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
503 GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
504 GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
505 GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
506 CLK_IGNORE_UNUSED, 0),
507 GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
508 CLK_IGNORE_UNUSED, 0),
509 GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
510 CLK_IGNORE_UNUSED, 0),
511 GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
512 CLK_IGNORE_UNUSED, 0),
513 GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
514 CLK_IGNORE_UNUSED, 0),
515 GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
516 CLK_IGNORE_UNUSED, 0),
517 GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
518 CLK_IGNORE_UNUSED, 0),
519 GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
520 CLK_IGNORE_UNUSED, 0),
521 GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
522 CLK_IGNORE_UNUSED, 0),
523 GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
524 CLK_IGNORE_UNUSED, 0),
525 GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
526 CLK_IGNORE_UNUSED, 0),
527 GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
528 CLK_IGNORE_UNUSED, 0),
529
530 /* GATE_SCLK_CAM */
531 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_cam_blk",
532 GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
533 GATE(CLK_SCLK_M2MSCALER, "sclk_m2mscaler", "div_cam_blk",
534 GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
535 GATE(CLK_SCLK_GSCALER1, "sclk_gscaler1", "div_cam_blk",
536 GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
537 GATE(CLK_SCLK_GSCALER0, "sclk_gscaler0", "div_cam_blk",
538 GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
539
540 /* GATE_SCLK_MFC */
541 GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
542 GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
543
544 /* GATE_SCLK_G3D */
545 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
546 GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
547
548 /* GATE_SCLK_LCD */
549 GATE(CLK_SCLK_MIPIDPHY2L, "sclk_mipidphy2l", "div_mipi0",
550 GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
551 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
552 GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
553 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
554 GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
555
556 /* GATE_SCLK_ISP_TOP */
557 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
558 GATE_SCLK_ISP_TOP, 4, CLK_SET_RATE_PARENT, 0),
559 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",
560 GATE_SCLK_ISP_TOP, 3, CLK_SET_RATE_PARENT, 0),
561 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp",
562 GATE_SCLK_ISP_TOP, 2, CLK_SET_RATE_PARENT, 0),
563 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp",
564 GATE_SCLK_ISP_TOP, 1, CLK_SET_RATE_PARENT, 0),
565
566 /* GATE_SCLK_FSYS */
567 GATE(CLK_SCLK_UPLL, "sclk_upll", "mout_upll", GATE_SCLK_FSYS, 10, 0, 0),
568 GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
569 GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
570 GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
571 GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
572 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
573 GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
574 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
575 GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
576
577 /* GATE_SCLK_PERIL */
578 GATE(CLK_SCLK_I2S, "sclk_i2s", "div_i2s",
579 GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
580 GATE(CLK_SCLK_PCM, "sclk_pcm", "div_pcm",
581 GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
582 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
583 GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
584 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
585 GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
586 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
587 GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
588 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
589 GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),
590
591 /* GATE_IP_CAM */
592 GATE(CLK_QEJPEG, "qejpeg", "div_cam_blk_320", GATE_IP_CAM, 19,
593 CLK_IGNORE_UNUSED, 0),
594 GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_cam_blk_320",
595 GATE_IP_CAM, 18, CLK_IGNORE_UNUSED, 0),
596 GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_cam_blk_320",
597 GATE_IP_CAM, 17, CLK_IGNORE_UNUSED, 0),
598 GATE(CLK_PPMUCAMIF, "ppmucamif", "div_cam_blk_320",
599 GATE_IP_CAM, 16, CLK_IGNORE_UNUSED, 0),
600 GATE(CLK_QEM2MSCALER, "qem2mscaler", "div_cam_blk_320",
601 GATE_IP_CAM, 14, CLK_IGNORE_UNUSED, 0),
602 GATE(CLK_QEGSCALER1, "qegscaler1", "div_cam_blk_320",
603 GATE_IP_CAM, 13, CLK_IGNORE_UNUSED, 0),
604 GATE(CLK_QEGSCALER0, "qegscaler0", "div_cam_blk_320",
605 GATE_IP_CAM, 12, CLK_IGNORE_UNUSED, 0),
606 GATE(CLK_SMMUJPEG, "smmujpeg", "div_cam_blk_320",
607 GATE_IP_CAM, 11, 0, 0),
608 GATE(CLK_SMMUM2M2SCALER, "smmum2m2scaler", "div_cam_blk_320",
609 GATE_IP_CAM, 9, 0, 0),
610 GATE(CLK_SMMUGSCALER1, "smmugscaler1", "div_cam_blk_320",
611 GATE_IP_CAM, 8, 0, 0),
612 GATE(CLK_SMMUGSCALER0, "smmugscaler0", "div_cam_blk_320",
613 GATE_IP_CAM, 7, 0, 0),
614 GATE(CLK_JPEG, "jpeg", "div_cam_blk_320", GATE_IP_CAM, 6, 0, 0),
615 GATE(CLK_M2MSCALER, "m2mscaler", "div_cam_blk_320",
616 GATE_IP_CAM, 2, 0, 0),
617 GATE(CLK_GSCALER1, "gscaler1", "div_cam_blk_320", GATE_IP_CAM, 1, 0, 0),
618 GATE(CLK_GSCALER0, "gscaler0", "div_cam_blk_320", GATE_IP_CAM, 0, 0, 0),
619
620 /* GATE_IP_MFC */
621 GATE(CLK_QEMFC, "qemfc", "div_aclk_200", GATE_IP_MFC, 5,
622 CLK_IGNORE_UNUSED, 0),
623 GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
624 CLK_IGNORE_UNUSED, 0),
625 GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
626 GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
627
628 /* GATE_IP_G3D */
629 GATE(CLK_SMMUG3D, "smmug3d", "div_aclk_200", GATE_IP_G3D, 3, 0, 0),
630 GATE(CLK_QEG3D, "qeg3d", "div_aclk_200", GATE_IP_G3D, 2,
631 CLK_IGNORE_UNUSED, 0),
632 GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
633 CLK_IGNORE_UNUSED, 0),
634 GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
635
636 /* GATE_IP_LCD */
637 GATE(CLK_QE_CH1_LCD, "qe_ch1_lcd", "div_aclk_160", GATE_IP_LCD, 7,
638 CLK_IGNORE_UNUSED, 0),
639 GATE(CLK_QE_CH0_LCD, "qe_ch0_lcd", "div_aclk_160", GATE_IP_LCD, 6,
640 CLK_IGNORE_UNUSED, 0),
641 GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
642 CLK_IGNORE_UNUSED, 0),
643 GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
644 GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
645 GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
646 GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
647
648 /* GATE_IP_ISP */
649 GATE(CLK_CAM1, "cam1", "mout_aclk_266_sub", GATE_IP_ISP, 5, 0, 0),
650 GATE(CLK_UART_ISP_TOP, "uart_isp_top", "mout_aclk_266_sub",
651 GATE_IP_ISP, 3, 0, 0),
652 GATE(CLK_SPI1_ISP_TOP, "spi1_isp_top", "mout_aclk_266_sub",
653 GATE_IP_ISP, 2, 0, 0),
654 GATE(CLK_SPI0_ISP_TOP, "spi0_isp_top", "mout_aclk_266_sub",
655 GATE_IP_ISP, 1, 0, 0),
656
657 /* GATE_IP_FSYS */
658 GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
659 GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
660 CLK_IGNORE_UNUSED, 0),
661 GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
662 GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
663 GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
664 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
665 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
666 GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
667 GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
668
669 /* GATE_IP_PERIL */
670 GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
671 GATE(CLK_PCM, "pcm", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
672 GATE(CLK_I2S, "i2s", "div_aclk_100", GATE_IP_PERIL, 21, 0, 0),
673 GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
674 GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
675 GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
676 GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
677 GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
678 GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
679 GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
680 GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
681 GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
682 GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
683 GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
684 GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
685};
686
687/* APLL & MPLL & BPLL & UPLL */
688static struct samsung_pll_rate_table exynos3250_pll_rates[] = {
689 PLL_35XX_RATE(1200000000, 400, 4, 1),
690 PLL_35XX_RATE(1100000000, 275, 3, 1),
691 PLL_35XX_RATE(1066000000, 533, 6, 1),
692 PLL_35XX_RATE(1000000000, 250, 3, 1),
693 PLL_35XX_RATE( 960000000, 320, 4, 1),
694 PLL_35XX_RATE( 900000000, 300, 4, 1),
695 PLL_35XX_RATE( 850000000, 425, 6, 1),
696 PLL_35XX_RATE( 800000000, 200, 3, 1),
697 PLL_35XX_RATE( 700000000, 175, 3, 1),
698 PLL_35XX_RATE( 667000000, 667, 12, 1),
699 PLL_35XX_RATE( 600000000, 400, 4, 2),
700 PLL_35XX_RATE( 533000000, 533, 6, 2),
701 PLL_35XX_RATE( 520000000, 260, 3, 2),
702 PLL_35XX_RATE( 500000000, 250, 3, 2),
703 PLL_35XX_RATE( 400000000, 200, 3, 2),
704 PLL_35XX_RATE( 200000000, 200, 3, 3),
705 PLL_35XX_RATE( 100000000, 200, 3, 4),
706 { /* sentinel */ }
707};
708
709/* VPLL */
710static struct samsung_pll_rate_table exynos3250_vpll_rates[] = {
711 PLL_36XX_RATE(600000000, 100, 2, 1, 0),
712 PLL_36XX_RATE(533000000, 266, 3, 2, 32768),
713 PLL_36XX_RATE(519230987, 173, 2, 2, 5046),
714 PLL_36XX_RATE(500000000, 250, 3, 2, 0),
715 PLL_36XX_RATE(445500000, 148, 2, 2, 32768),
716 PLL_36XX_RATE(445055007, 148, 2, 2, 23047),
717 PLL_36XX_RATE(400000000, 200, 3, 2, 0),
718 PLL_36XX_RATE(371250000, 123, 2, 2, 49152),
719 PLL_36XX_RATE(370878997, 185, 3, 2, 28803),
720 PLL_36XX_RATE(340000000, 170, 3, 2, 0),
721 PLL_36XX_RATE(335000015, 111, 2, 2, 43691),
722 PLL_36XX_RATE(333000000, 111, 2, 2, 0),
723 PLL_36XX_RATE(330000000, 110, 2, 2, 0),
724 PLL_36XX_RATE(320000015, 106, 2, 2, 43691),
725 PLL_36XX_RATE(300000000, 100, 2, 2, 0),
726 PLL_36XX_RATE(275000000, 275, 3, 3, 0),
727 PLL_36XX_RATE(222750000, 148, 2, 3, 32768),
728 PLL_36XX_RATE(222528007, 148, 2, 3, 23069),
729 PLL_36XX_RATE(160000000, 160, 3, 3, 0),
730 PLL_36XX_RATE(148500000, 99, 2, 3, 0),
731 PLL_36XX_RATE(148352005, 98, 2, 3, 59070),
732 PLL_36XX_RATE(108000000, 144, 2, 4, 0),
733 PLL_36XX_RATE( 74250000, 99, 2, 4, 0),
734 PLL_36XX_RATE( 74176002, 98, 3, 4, 59070),
735 PLL_36XX_RATE( 54054000, 216, 3, 5, 14156),
736 PLL_36XX_RATE( 54000000, 144, 2, 5, 0),
737 { /* sentinel */ }
738};
739
740static struct samsung_pll_clock exynos3250_plls[nr_plls] __initdata = {
741 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
742 APLL_LOCK, APLL_CON0, NULL),
743 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
744 MPLL_LOCK, MPLL_CON0, NULL),
745 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
746 VPLL_LOCK, VPLL_CON0, NULL),
747 [upll] = PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll",
748 UPLL_LOCK, UPLL_CON0, NULL),
749};
750
751static void __init exynos3250_cmu_init(struct device_node *np)
752{
753 struct samsung_clk_provider *ctx;
754
755 reg_base = of_iomap(np, 0);
756 if (!reg_base)
757 panic("%s: failed to map registers\n", __func__);
758
759 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
760 if (!ctx)
761 panic("%s: unable to allocate context.\n", __func__);
762
763 samsung_clk_register_fixed_factor(ctx, fixed_factor_clks,
764 ARRAY_SIZE(fixed_factor_clks));
765
766 exynos3250_plls[apll].rate_table = exynos3250_pll_rates;
767 exynos3250_plls[mpll].rate_table = exynos3250_pll_rates;
768 exynos3250_plls[vpll].rate_table = exynos3250_vpll_rates;
769 exynos3250_plls[upll].rate_table = exynos3250_pll_rates;
770
771 samsung_clk_register_pll(ctx, exynos3250_plls,
772 ARRAY_SIZE(exynos3250_plls), reg_base);
773
774 samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks));
775 samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks));
776 samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks));
777
778 exynos3250_clk_sleep_init();
779}
780CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-21 00:41:52 -0500