diff options
| author | Linus Walleij <linus.walleij@linaro.org> | 2013-05-02 10:56:15 -0400 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2013-06-17 07:54:31 -0400 |
| commit | 0004b017fe65eff60a9b403c52acc03521108c21 (patch) | |
| tree | 23831006e3fc8c6621344065d8d9e5ad5ec22ab3 /drivers/clk/clk-u300.c | |
| parent | 22f718efe61edffe30f9dc97292e5bbe66123843 (diff) | |
ARM: u300: push down syscon registers
Get rid of the <mach/syscon.h> header as a prerequisite for
multiplatform support. Do this by pushing the registers down
to their respective drivers and deleting the unused remainder.
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/clk/clk-u300.c')
| -rw-r--r-- | drivers/clk/clk-u300.c | 343 |
1 files changed, 342 insertions, 1 deletions
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c index a15f7928fb11..a41e42ec0916 100644 --- a/drivers/clk/clk-u300.c +++ b/drivers/clk/clk-u300.c | |||
| @@ -11,7 +11,348 @@ | |||
| 11 | #include <linux/io.h> | 11 | #include <linux/io.h> |
| 12 | #include <linux/clk-provider.h> | 12 | #include <linux/clk-provider.h> |
| 13 | #include <linux/spinlock.h> | 13 | #include <linux/spinlock.h> |
| 14 | #include <mach/syscon.h> | 14 | |
| 15 | /* APP side SYSCON registers */ | ||
| 16 | /* CLK Control Register 16bit (R/W) */ | ||
| 17 | #define U300_SYSCON_CCR (0x0000) | ||
| 18 | #define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040) | ||
| 19 | #define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020) | ||
| 20 | #define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008) | ||
| 21 | #define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007) | ||
| 22 | #define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04) | ||
| 23 | #define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03) | ||
| 24 | #define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02) | ||
| 25 | #define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01) | ||
| 26 | #define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00) | ||
| 27 | /* CLK Status Register 16bit (R/W) */ | ||
| 28 | #define U300_SYSCON_CSR (0x0004) | ||
| 29 | #define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002) | ||
| 30 | #define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001) | ||
| 31 | /* Reset lines for SLOW devices 16bit (R/W) */ | ||
| 32 | #define U300_SYSCON_RSR (0x0014) | ||
| 33 | #define U300_SYSCON_RSR_PPM_RESET_EN (0x0200) | ||
| 34 | #define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100) | ||
| 35 | #define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080) | ||
| 36 | #define U300_SYSCON_RSR_RTC_RESET_EN (0x0040) | ||
| 37 | #define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020) | ||
| 38 | #define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010) | ||
| 39 | #define U300_SYSCON_RSR_EH_RESET_EN (0x0008) | ||
| 40 | #define U300_SYSCON_RSR_BTR_RESET_EN (0x0004) | ||
| 41 | #define U300_SYSCON_RSR_UART_RESET_EN (0x0002) | ||
| 42 | #define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001) | ||
| 43 | /* Reset lines for FAST devices 16bit (R/W) */ | ||
| 44 | #define U300_SYSCON_RFR (0x0018) | ||
| 45 | #define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080) | ||
| 46 | #define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040) | ||
| 47 | #define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020) | ||
| 48 | #define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010) | ||
| 49 | #define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008) | ||
| 50 | #define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004) | ||
| 51 | #define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002) | ||
| 52 | #define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001) | ||
| 53 | /* Reset lines for the rest of the peripherals 16bit (R/W) */ | ||
| 54 | #define U300_SYSCON_RRR (0x001c) | ||
| 55 | #define U300_SYSCON_RRR_CDS_RESET_EN (0x4000) | ||
| 56 | #define U300_SYSCON_RRR_ISP_RESET_EN (0x2000) | ||
| 57 | #define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000) | ||
| 58 | #define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800) | ||
| 59 | #define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100) | ||
| 60 | #define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080) | ||
| 61 | #define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040) | ||
| 62 | #define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020) | ||
| 63 | #define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010) | ||
| 64 | #define U300_SYSCON_RRR_CPU_RESET_EN (0x0008) | ||
| 65 | #define U300_SYSCON_RRR_APEX_RESET_EN (0x0004) | ||
| 66 | #define U300_SYSCON_RRR_AHB_RESET_EN (0x0002) | ||
| 67 | #define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001) | ||
| 68 | /* Clock enable for SLOW peripherals 16bit (R/W) */ | ||
| 69 | #define U300_SYSCON_CESR (0x0020) | ||
| 70 | #define U300_SYSCON_CESR_PPM_CLK_EN (0x0200) | ||
| 71 | #define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100) | ||
| 72 | #define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080) | ||
| 73 | #define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040) | ||
| 74 | #define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010) | ||
| 75 | #define U300_SYSCON_CESR_EH_CLK_EN (0x0008) | ||
| 76 | #define U300_SYSCON_CESR_BTR_CLK_EN (0x0004) | ||
| 77 | #define U300_SYSCON_CESR_UART_CLK_EN (0x0002) | ||
| 78 | #define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001) | ||
| 79 | /* Clock enable for FAST peripherals 16bit (R/W) */ | ||
| 80 | #define U300_SYSCON_CEFR (0x0024) | ||
| 81 | #define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200) | ||
| 82 | #define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100) | ||
| 83 | #define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080) | ||
| 84 | #define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040) | ||
| 85 | #define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020) | ||
| 86 | #define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010) | ||
| 87 | #define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008) | ||
| 88 | #define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004) | ||
| 89 | #define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002) | ||
| 90 | #define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001) | ||
| 91 | /* Clock enable for the rest of the peripherals 16bit (R/W) */ | ||
| 92 | #define U300_SYSCON_CERR (0x0028) | ||
| 93 | #define U300_SYSCON_CERR_CDS_CLK_EN (0x2000) | ||
| 94 | #define U300_SYSCON_CERR_ISP_CLK_EN (0x1000) | ||
| 95 | #define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800) | ||
| 96 | #define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400) | ||
| 97 | #define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200) | ||
| 98 | #define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100) | ||
| 99 | #define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080) | ||
| 100 | #define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040) | ||
| 101 | #define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020) | ||
| 102 | #define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010) | ||
| 103 | #define U300_SYSCON_CERR_CPU_CLK_EN (0x0008) | ||
| 104 | #define U300_SYSCON_CERR_APEX_CLK_EN (0x0004) | ||
| 105 | #define U300_SYSCON_CERR_AHB_CLK_EN (0x0002) | ||
| 106 | #define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001) | ||
| 107 | /* Single block clock enable 16bit (-/W) */ | ||
| 108 | #define U300_SYSCON_SBCER (0x002c) | ||
| 109 | #define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009) | ||
| 110 | #define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008) | ||
| 111 | #define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007) | ||
| 112 | #define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006) | ||
| 113 | #define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004) | ||
| 114 | #define U300_SYSCON_SBCER_EH_CLK_EN (0x0003) | ||
| 115 | #define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002) | ||
| 116 | #define U300_SYSCON_SBCER_UART_CLK_EN (0x0001) | ||
| 117 | #define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000) | ||
| 118 | #define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019) | ||
| 119 | #define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018) | ||
| 120 | #define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017) | ||
| 121 | #define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016) | ||
| 122 | #define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015) | ||
| 123 | #define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014) | ||
| 124 | #define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013) | ||
| 125 | #define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012) | ||
| 126 | #define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011) | ||
| 127 | #define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010) | ||
| 128 | #define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D) | ||
| 129 | #define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C) | ||
| 130 | #define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B) | ||
| 131 | #define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A) | ||
| 132 | #define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029) | ||
| 133 | #define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028) | ||
| 134 | #define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027) | ||
| 135 | #define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026) | ||
| 136 | #define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025) | ||
| 137 | #define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024) | ||
| 138 | #define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023) | ||
| 139 | #define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022) | ||
| 140 | #define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021) | ||
| 141 | #define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020) | ||
| 142 | /* Single block clock disable 16bit (-/W) */ | ||
| 143 | #define U300_SYSCON_SBCDR (0x0030) | ||
| 144 | /* Same values as above for SBCER */ | ||
| 145 | /* Clock force SLOW peripherals 16bit (R/W) */ | ||
| 146 | #define U300_SYSCON_CFSR (0x003c) | ||
| 147 | #define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200) | ||
| 148 | #define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100) | ||
| 149 | #define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080) | ||
| 150 | #define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020) | ||
| 151 | #define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010) | ||
| 152 | #define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008) | ||
| 153 | #define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004) | ||
| 154 | #define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002) | ||
| 155 | #define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001) | ||
| 156 | /* Clock force FAST peripherals 16bit (R/W) */ | ||
| 157 | #define U300_SYSCON_CFFR (0x40) | ||
| 158 | /* Values not defined. Define if you want to use them. */ | ||
| 159 | /* Clock force the rest of the peripherals 16bit (R/W) */ | ||
| 160 | #define U300_SYSCON_CFRR (0x44) | ||
| 161 | #define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000) | ||
| 162 | #define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000) | ||
| 163 | #define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800) | ||
| 164 | #define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400) | ||
| 165 | #define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200) | ||
| 166 | #define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100) | ||
| 167 | #define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080) | ||
| 168 | #define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040) | ||
| 169 | #define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020) | ||
| 170 | #define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010) | ||
| 171 | #define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008) | ||
| 172 | #define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004) | ||
| 173 | #define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002) | ||
| 174 | #define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001) | ||
| 175 | /* PLL208 Frequency Control 16bit (R/W) */ | ||
| 176 | #define U300_SYSCON_PFCR (0x48) | ||
| 177 | #define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F) | ||
| 178 | /* Power Management Control 16bit (R/W) */ | ||
| 179 | #define U300_SYSCON_PMCR (0x50) | ||
| 180 | #define U300_SYSCON_PMCR_DCON_ENABLE (0x0002) | ||
| 181 | #define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001) | ||
| 182 | /* Reset Out 16bit (R/W) */ | ||
| 183 | #define U300_SYSCON_RCR (0x6c) | ||
| 184 | #define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001) | ||
| 185 | /* EMIF Slew Rate Control 16bit (R/W) */ | ||
| 186 | #define U300_SYSCON_SRCLR (0x70) | ||
| 187 | #define U300_SYSCON_SRCLR_MASK (0x03FF) | ||
| 188 | #define U300_SYSCON_SRCLR_VALUE (0x03FF) | ||
| 189 | #define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200) | ||
| 190 | #define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100) | ||
| 191 | #define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080) | ||
| 192 | #define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040) | ||
| 193 | #define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020) | ||
| 194 | #define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010) | ||
| 195 | #define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008) | ||
| 196 | #define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004) | ||
| 197 | #define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002) | ||
| 198 | #define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001) | ||
| 199 | /* EMIF Clock Control Register 16bit (R/W) */ | ||
| 200 | #define U300_SYSCON_ECCR (0x0078) | ||
| 201 | #define U300_SYSCON_ECCR_MASK (0x000F) | ||
| 202 | #define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008) | ||
| 203 | #define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004) | ||
| 204 | #define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002) | ||
| 205 | #define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001) | ||
| 206 | /* MMC/MSPRO frequency divider register 0 16bit (R/W) */ | ||
| 207 | #define U300_SYSCON_MMF0R (0x90) | ||
| 208 | #define U300_SYSCON_MMF0R_MASK (0x00FF) | ||
| 209 | #define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0) | ||
| 210 | #define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F) | ||
| 211 | /* MMC/MSPRO frequency divider register 1 16bit (R/W) */ | ||
| 212 | #define U300_SYSCON_MMF1R (0x94) | ||
| 213 | #define U300_SYSCON_MMF1R_MASK (0x00FF) | ||
| 214 | #define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0) | ||
| 215 | #define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F) | ||
| 216 | /* Clock control for the MMC and MSPRO blocks 16bit (R/W) */ | ||
| 217 | #define U300_SYSCON_MMCR (0x9C) | ||
| 218 | #define U300_SYSCON_MMCR_MASK (0x0003) | ||
| 219 | #define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002) | ||
| 220 | #define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001) | ||
| 221 | /* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */ | ||
| 222 | #define U300_SYSCON_S0CCR (0x120) | ||
| 223 | #define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF) | ||
| 224 | #define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000) | ||
| 225 | #define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR (0x2000) | ||
| 226 | #define U300_SYSCON_S0CCR_CLOCK_INV (0x0200) | ||
| 227 | #define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0) | ||
| 228 | #define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E) | ||
| 229 | #define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001) | ||
| 230 | #define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1) | ||
| 231 | #define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1) | ||
| 232 | #define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1) | ||
| 233 | #define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1) | ||
| 234 | #define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1) | ||
| 235 | #define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1) | ||
| 236 | #define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1) | ||
| 237 | #define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1) | ||
| 238 | #define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1) | ||
| 239 | /* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */ | ||
| 240 | #define U300_SYSCON_S1CCR (0x124) | ||
| 241 | #define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF) | ||
| 242 | #define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000) | ||
| 243 | #define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR (0x2000) | ||
| 244 | #define U300_SYSCON_S1CCR_CLOCK_INV (0x0200) | ||
| 245 | #define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0) | ||
| 246 | #define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E) | ||
| 247 | #define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001) | ||
| 248 | #define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1) | ||
| 249 | #define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1) | ||
| 250 | #define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1) | ||
| 251 | #define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1) | ||
| 252 | #define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1) | ||
| 253 | #define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1) | ||
| 254 | #define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1) | ||
| 255 | #define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1) | ||
| 256 | #define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1) | ||
| 257 | /* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */ | ||
| 258 | #define U300_SYSCON_S2CCR (0x128) | ||
| 259 | #define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF) | ||
| 260 | #define U300_SYSCON_S2CCR_CLK_STEAL (0x8000) | ||
| 261 | #define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000) | ||
| 262 | #define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR (0x2000) | ||
| 263 | #define U300_SYSCON_S2CCR_CLOCK_INV (0x0200) | ||
| 264 | #define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0) | ||
| 265 | #define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E) | ||
| 266 | #define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001) | ||
| 267 | #define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1) | ||
| 268 | #define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1) | ||
| 269 | #define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1) | ||
| 270 | #define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1) | ||
| 271 | #define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1) | ||
| 272 | #define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1) | ||
| 273 | #define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1) | ||
| 274 | #define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1) | ||
| 275 | #define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1) | ||
| 276 | /* SC_PLL_IRQ_CONTROL 16bit (R/W) */ | ||
| 277 | #define U300_SYSCON_PICR (0x0130) | ||
| 278 | #define U300_SYSCON_PICR_MASK (0x00FF) | ||
| 279 | #define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE (0x0080) | ||
| 280 | #define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE (0x0040) | ||
| 281 | #define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE (0x0020) | ||
| 282 | #define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE (0x0010) | ||
| 283 | #define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE (0x0008) | ||
| 284 | #define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE (0x0004) | ||
| 285 | #define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE (0x0002) | ||
| 286 | #define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE (0x0001) | ||
| 287 | /* SC_PLL_IRQ_STATUS 16 bit (R/-) */ | ||
| 288 | #define U300_SYSCON_PISR (0x0134) | ||
| 289 | #define U300_SYSCON_PISR_MASK (0x000F) | ||
| 290 | #define U300_SYSCON_PISR_PLL13_UNLOCK_IND (0x0008) | ||
| 291 | #define U300_SYSCON_PISR_PLL13_LOCK_IND (0x0004) | ||
| 292 | #define U300_SYSCON_PISR_PLL208_UNLOCK_IND (0x0002) | ||
| 293 | #define U300_SYSCON_PISR_PLL208_LOCK_IND (0x0001) | ||
| 294 | /* SC_PLL_IRQ_CLEAR 16 bit (-/W) */ | ||
| 295 | #define U300_SYSCON_PICLR (0x0138) | ||
| 296 | #define U300_SYSCON_PICLR_MASK (0x000F) | ||
| 297 | #define U300_SYSCON_PICLR_RWMASK (0x0000) | ||
| 298 | #define U300_SYSCON_PICLR_PLL13_UNLOCK_SC (0x0008) | ||
| 299 | #define U300_SYSCON_PICLR_PLL13_LOCK_SC (0x0004) | ||
| 300 | #define U300_SYSCON_PICLR_PLL208_UNLOCK_SC (0x0002) | ||
| 301 | #define U300_SYSCON_PICLR_PLL208_LOCK_SC (0x0001) | ||
| 302 | /* Clock activity observability register 0 */ | ||
| 303 | #define U300_SYSCON_C0OAR (0x140) | ||
| 304 | #define U300_SYSCON_C0OAR_MASK (0xFFFF) | ||
| 305 | #define U300_SYSCON_C0OAR_VALUE (0xFFFF) | ||
| 306 | #define U300_SYSCON_C0OAR_BT_H_CLK (0x8000) | ||
| 307 | #define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000) | ||
| 308 | #define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000) | ||
| 309 | #define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000) | ||
| 310 | #define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800) | ||
| 311 | #define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400) | ||
| 312 | #define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200) | ||
| 313 | #define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100) | ||
| 314 | #define U300_SYSCON_C0OAR_APP_52_CLK (0x0080) | ||
| 315 | #define U300_SYSCON_C0OAR_APP_208_CLK (0x0040) | ||
| 316 | #define U300_SYSCON_C0OAR_APP_104_CLK (0x0020) | ||
| 317 | #define U300_SYSCON_C0OAR_APEX_CLK (0x0010) | ||
| 318 | #define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008) | ||
| 319 | #define U300_SYSCON_C0OAR_AHB_CLK (0x0004) | ||
| 320 | #define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002) | ||
| 321 | #define U300_SYSCON_C0OAR_AAIF_CLK (0x0001) | ||
| 322 | /* Clock activity observability register 1 */ | ||
| 323 | #define U300_SYSCON_C1OAR (0x144) | ||
| 324 | #define U300_SYSCON_C1OAR_MASK (0x3FFE) | ||
| 325 | #define U300_SYSCON_C1OAR_VALUE (0x3FFE) | ||
| 326 | #define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000) | ||
| 327 | #define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000) | ||
| 328 | #define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800) | ||
| 329 | #define U300_SYSCON_C1OAR_MMC_CLK (0x0400) | ||
| 330 | #define U300_SYSCON_C1OAR_KP_P_CLK (0x0200) | ||
| 331 | #define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100) | ||
| 332 | #define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080) | ||
| 333 | #define U300_SYSCON_C1OAR_GPIO_CLK (0x0040) | ||
| 334 | #define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020) | ||
| 335 | #define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010) | ||
| 336 | #define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008) | ||
| 337 | #define U300_SYSCON_C1OAR_PPM_CLK (0x0004) | ||
| 338 | #define U300_SYSCON_C1OAR_DMA_CLK (0x0002) | ||
| 339 | /* Clock activity observability register 2 */ | ||
| 340 | #define U300_SYSCON_C2OAR (0x148) | ||
| 341 | #define U300_SYSCON_C2OAR_MASK (0x0FFF) | ||
| 342 | #define U300_SYSCON_C2OAR_VALUE (0x0FFF) | ||
| 343 | #define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800) | ||
| 344 | #define U300_SYSCON_C2OAR_XGAM_CLK (0x0400) | ||
| 345 | #define U300_SYSCON_C2OAR_VC_H_CLK (0x0200) | ||
| 346 | #define U300_SYSCON_C2OAR_VC_CLK (0x0100) | ||
| 347 | #define U300_SYSCON_C2OAR_UA_P_CLK (0x0080) | ||
| 348 | #define U300_SYSCON_C2OAR_TMR1_CLK (0x0040) | ||
| 349 | #define U300_SYSCON_C2OAR_TMR0_CLK (0x0020) | ||
| 350 | #define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010) | ||
| 351 | #define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008) | ||
| 352 | #define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004) | ||
| 353 | #define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002) | ||
| 354 | #define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001) | ||
| 355 | |||
| 15 | 356 | ||
| 16 | /* | 357 | /* |
| 17 | * The clocking hierarchy currently looks like this. | 358 | * The clocking hierarchy currently looks like this. |