clk: wrap I/O access for improved portability

the common clock drivers were motivated/initiated by ARM development
and apparently assume little endian peripherals

wrap register/peripherals access in the common code (div, gate, mux)
in preparation of adding COMMON_CLK support for other platforms

Signed-off-by: Gerhard Sittig <gsi@denx.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

1 files changed, 3 insertions, 3 deletions

diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 0811633fcc4d..4f96ff3ba728 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -42,7 +42,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
          * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
          * val = 0x4 really means "bit 2, index starts at bit 0"
          */
-        val = readl(mux->reg) >> mux->shift;
+        val = clk_readl(mux->reg) >> mux->shift;
         val &= mux->mask;
 
         if (mux->table) {
@@ -89,11 +89,11 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
         if (mux->flags & CLK_MUX_HIWORD_MASK) {
                 val = mux->mask << (mux->shift + 16);
         } else {
-                val = readl(mux->reg);
+                val = clk_readl(mux->reg);
                 val &= ~(mux->mask << mux->shift);
         }
         val |= index << mux->shift;
-        writel(val, mux->reg);
+        clk_writel(val, mux->reg);
 
         if (mux->lock)
                 spin_unlock_irqrestore(mux->lock, flags);