clk: divider: add CLK_DIVIDER_HIWORD_MASK flag

In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the
paradigm of reading-changing-writing the register contents.
Instead they use a hiword mask to indicate the changed bits.

When b01 should be set as setting divider, it also needs to indicate
the change by setting hiword mask (b11 << 16).

The patch adds divider flag for this usage.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

1 files changed, 13 insertions, 2 deletions

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 6024e60e49aa..6d55eb2cb959 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -227,8 +227,12 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
         if (divider->lock)
                 spin_lock_irqsave(divider->lock, flags);
 
-        val = readl(divider->reg);
-        val &= ~(div_mask(divider) << divider->shift);
+        if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
+                val = div_mask(divider) << (divider->shift + 16);
+        } else {
+                val = readl(divider->reg);
+                val &= ~(div_mask(divider) << divider->shift);
+        }
         val |= value << divider->shift;
         writel(val, divider->reg);
 
@@ -255,6 +259,13 @@ static struct clk *_register_divider(struct device *dev, const char *name,
         struct clk *clk;
         struct clk_init_data init;
 
+        if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
+                if (width + shift > 16) {
+                        pr_warn("divider value exceeds LOWORD field\n");
+                        return ERR_PTR(-EINVAL);
+                }
+        }
+
         /* allocate the divider */
         div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
         if (!div) {