clk: divider: Introduce CLK_DIVIDER_ALLOW_ZERO flag

Dividers which have CLK_DIVIDER_ONE_BASED set have a redundant state,
being a divider value of zero. Some hardware implementations allow a
zero divider which simply doesn't alter the frequency. I.e. it acts like
a divide by one or bypassing the divider.
This flag is used to handle such HW in the clk-divider model.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

1 files changed, 3 insertions, 2 deletions

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 68b402101170..6d9674160430 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -109,8 +109,9 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
 
         div = _get_div(divider, val);
         if (!div) {
-                WARN(1, "%s: Invalid divisor for clock %s\n", __func__,
-                                                __clk_get_name(hw->clk));
+                WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
+                        "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
+                        __clk_get_name(hw->clk));
                 return parent_rate;
         }