diff options
author | Heiko Stübner <heiko@sntech.de> | 2014-07-02 19:57:30 -0400 |
---|---|---|
committer | Mike Turquette <mturquette@linaro.org> | 2014-07-13 15:17:04 -0400 |
commit | 0c02cf2f1c2ffd75221b43bacb4f02a0e52e014b (patch) | |
tree | f077dfd8233e422d494a70b3ea9f41671faaa747 /drivers/clk/clk-composite.c | |
parent | 3eb635f1ca2d25bd11a697f5bdb52ac3d08c240e (diff) |
clk: composite: allow read-only clocks
This allows readl-only composite clocks by making mux_ops->set_parent and
divider_ops->round_rate/set_rate optional.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/clk-composite.c')
-rw-r--r-- | drivers/clk/clk-composite.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index 9548bfcbd56b..faf7c32fe351 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c | |||
@@ -207,7 +207,7 @@ struct clk *clk_register_composite(struct device *dev, const char *name, | |||
207 | clk_composite_ops = &composite->ops; | 207 | clk_composite_ops = &composite->ops; |
208 | 208 | ||
209 | if (mux_hw && mux_ops) { | 209 | if (mux_hw && mux_ops) { |
210 | if (!mux_ops->get_parent || !mux_ops->set_parent) { | 210 | if (!mux_ops->get_parent) { |
211 | clk = ERR_PTR(-EINVAL); | 211 | clk = ERR_PTR(-EINVAL); |
212 | goto err; | 212 | goto err; |
213 | } | 213 | } |
@@ -215,7 +215,8 @@ struct clk *clk_register_composite(struct device *dev, const char *name, | |||
215 | composite->mux_hw = mux_hw; | 215 | composite->mux_hw = mux_hw; |
216 | composite->mux_ops = mux_ops; | 216 | composite->mux_ops = mux_ops; |
217 | clk_composite_ops->get_parent = clk_composite_get_parent; | 217 | clk_composite_ops->get_parent = clk_composite_get_parent; |
218 | clk_composite_ops->set_parent = clk_composite_set_parent; | 218 | if (mux_ops->set_parent) |
219 | clk_composite_ops->set_parent = clk_composite_set_parent; | ||
219 | if (mux_ops->determine_rate) | 220 | if (mux_ops->determine_rate) |
220 | clk_composite_ops->determine_rate = clk_composite_determine_rate; | 221 | clk_composite_ops->determine_rate = clk_composite_determine_rate; |
221 | } | 222 | } |
@@ -232,10 +233,6 @@ struct clk *clk_register_composite(struct device *dev, const char *name, | |||
232 | if (rate_ops->set_rate) { | 233 | if (rate_ops->set_rate) { |
233 | clk_composite_ops->set_rate = clk_composite_set_rate; | 234 | clk_composite_ops->set_rate = clk_composite_set_rate; |
234 | } | 235 | } |
235 | } else { | ||
236 | WARN(rate_ops->set_rate, | ||
237 | "%s: missing round_rate op is required\n", | ||
238 | __func__); | ||
239 | } | 236 | } |
240 | 237 | ||
241 | composite->rate_hw = rate_hw; | 238 | composite->rate_hw = rate_hw; |