diff options
author | Michel Dänzer <michel@tungstengraphics.com> | 2006-08-07 06:41:53 -0400 |
---|---|---|
committer | Dave Airlie <airlied@linux.ie> | 2006-09-21 15:32:31 -0400 |
commit | b9b603dd1c99a68e65ad51cda25379441df2e17b (patch) | |
tree | 7f8c00912a48714072840a2d4345282ae5d25049 /drivers/char | |
parent | ae1b1a4816ac11075d338af79a239f4c326d675c (diff) |
drm: radeon: Use RADEON_RB3D_DSTCACHE_CTLSTAT instead of RADEON_RB2D_DSTCACHE_CTLSTAT.
The latter seems to be a read-only mirror of the former.
Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/char')
-rw-r--r-- | drivers/char/drm/radeon_cp.c | 10 | ||||
-rw-r--r-- | drivers/char/drm/radeon_drv.h | 9 |
2 files changed, 12 insertions, 7 deletions
diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c index 3956628b2576..45f8044e9a30 100644 --- a/drivers/char/drm/radeon_cp.c +++ b/drivers/char/drm/radeon_cp.c | |||
@@ -864,13 +864,13 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) | |||
864 | 864 | ||
865 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | 865 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; |
866 | 866 | ||
867 | tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT); | 867 | tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); |
868 | tmp |= RADEON_RB2D_DC_FLUSH_ALL; | 868 | tmp |= RADEON_RB3D_DC_FLUSH_ALL; |
869 | RADEON_WRITE(RADEON_RB2D_DSTCACHE_CTLSTAT, tmp); | 869 | RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); |
870 | 870 | ||
871 | for (i = 0; i < dev_priv->usec_timeout; i++) { | 871 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
872 | if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT) | 872 | if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) |
873 | & RADEON_RB2D_DC_BUSY)) { | 873 | & RADEON_RB3D_DC_BUSY)) { |
874 | return 0; | 874 | return 0; |
875 | } | 875 | } |
876 | DRM_UDELAY(1); | 876 | DRM_UDELAY(1); |
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h index b54b8967dcd2..2f51d5147730 100644 --- a/drivers/char/drm/radeon_drv.h +++ b/drivers/char/drm/radeon_drv.h | |||
@@ -545,6 +545,11 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp, | |||
545 | # define RADEON_RB3D_ZC_FREE (1 << 2) | 545 | # define RADEON_RB3D_ZC_FREE (1 << 2) |
546 | # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 | 546 | # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 |
547 | # define RADEON_RB3D_ZC_BUSY (1 << 31) | 547 | # define RADEON_RB3D_ZC_BUSY (1 << 31) |
548 | #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c | ||
549 | # define RADEON_RB3D_DC_FLUSH (3 << 0) | ||
550 | # define RADEON_RB3D_DC_FREE (3 << 2) | ||
551 | # define RADEON_RB3D_DC_FLUSH_ALL 0xf | ||
552 | # define RADEON_RB3D_DC_BUSY (1 << 31) | ||
548 | #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c | 553 | #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c |
549 | # define RADEON_Z_TEST_MASK (7 << 4) | 554 | # define RADEON_Z_TEST_MASK (7 << 4) |
550 | # define RADEON_Z_TEST_ALWAYS (7 << 4) | 555 | # define RADEON_Z_TEST_ALWAYS (7 << 4) |
@@ -987,12 +992,12 @@ do { \ | |||
987 | } while (0) | 992 | } while (0) |
988 | 993 | ||
989 | #define RADEON_FLUSH_CACHE() do { \ | 994 | #define RADEON_FLUSH_CACHE() do { \ |
990 | OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \ | 995 | OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ |
991 | OUT_RING( RADEON_RB2D_DC_FLUSH ); \ | 996 | OUT_RING( RADEON_RB2D_DC_FLUSH ); \ |
992 | } while (0) | 997 | } while (0) |
993 | 998 | ||
994 | #define RADEON_PURGE_CACHE() do { \ | 999 | #define RADEON_PURGE_CACHE() do { \ |
995 | OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \ | 1000 | OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ |
996 | OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \ | 1001 | OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \ |
997 | } while (0) | 1002 | } while (0) |
998 | 1003 | ||