agp/intel: Support the extended physical addressing bits on Sandybridge.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
[anholt: Split this patch out of a larger patch for Sandybridge fixes]
Signed-off-by: Eric Anholt <eric@anholt.net>

2 files changed, 45 insertions, 2 deletions

diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index d836a71bf06d..5bbc7be203a6 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -816,9 +816,9 @@ static const struct intel_driver_description {
         { PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
             "HD Graphics", NULL, &intel_i965_driver },
         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG,
-            "Sandybridge", NULL, &intel_i965_driver },
+            "Sandybridge", NULL, &intel_gen6_driver },
         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG,
-            "Sandybridge", NULL, &intel_i965_driver },
+            "Sandybridge", NULL, &intel_gen6_driver },
         { 0, 0, NULL, NULL, NULL }
 };
 
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index f97122a53ca3..2b1a0e96c71f 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1315,6 +1315,16 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
         return addr | bridge->driver->masks[type].mask;
 }
 
+static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge,
+                                            dma_addr_t addr, int type)
+{
+        /* Shift high bits down */
+        addr |= (addr >> 28) & 0xff;
+
+        /* Type checking must be done elsewhere */
+        return addr | bridge->driver->masks[type].mask;
+}
+
 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
 {
         u16 snb_gmch_ctl;
@@ -1528,6 +1538,39 @@ static const struct agp_bridge_driver intel_i965_driver = {
 #endif
 };
 
+static const struct agp_bridge_driver intel_gen6_driver = {
+        .owner                  = THIS_MODULE,
+        .aperture_sizes         = intel_i830_sizes,
+        .size_type              = FIXED_APER_SIZE,
+        .num_aperture_sizes     = 4,
+        .needs_scratch_page     = true,
+        .configure              = intel_i9xx_configure,
+        .fetch_size             = intel_i9xx_fetch_size,
+        .cleanup                = intel_i915_cleanup,
+        .mask_memory            = intel_gen6_mask_memory,
+        .masks                  = intel_i810_masks,
+        .agp_enable             = intel_i810_agp_enable,
+        .cache_flush            = global_cache_flush,
+        .create_gatt_table      = intel_i965_create_gatt_table,
+        .free_gatt_table        = intel_i830_free_gatt_table,
+        .insert_memory          = intel_i915_insert_entries,
+        .remove_memory          = intel_i915_remove_entries,
+        .alloc_by_type          = intel_i830_alloc_by_type,
+        .free_by_type           = intel_i810_free_by_type,
+        .agp_alloc_page         = agp_generic_alloc_page,
+        .agp_alloc_pages        = agp_generic_alloc_pages,
+        .agp_destroy_page       = agp_generic_destroy_page,
+        .agp_destroy_pages      = agp_generic_destroy_pages,
+        .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
+        .chipset_flush          = intel_i915_chipset_flush,
+#ifdef USE_PCI_DMA_API
+        .agp_map_page           = intel_agp_map_page,
+        .agp_unmap_page         = intel_agp_unmap_page,
+        .agp_map_memory         = intel_agp_map_memory,
+        .agp_unmap_memory       = intel_agp_unmap_memory,
+#endif
+};
+
 static const struct agp_bridge_driver intel_g33_driver = {
         .owner                  = THIS_MODULE,
         .aperture_sizes         = intel_i830_sizes,