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authorKeith Packard <keithp@keithp.com>2008-05-06 22:27:53 -0400
committerDave Airlie <airlied@linux.ie>2008-05-06 22:27:53 -0400
commite948e99400b28af152414f15f8c8023ff2430b79 (patch)
tree2a6d1ff037cc39ba8a3c6294e73b82ff70328570 /drivers/char
parenta59e122a67b88925944d3bbf33d15229cf0fc3de (diff)
drm/i915: save and restore dsparb and d_state registers.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/char')
-rw-r--r--drivers/char/drm/i915_drv.c7
-rw-r--r--drivers/char/drm/i915_drv.h10
2 files changed, 17 insertions, 0 deletions
diff --git a/drivers/char/drm/i915_drv.c b/drivers/char/drm/i915_drv.c
index 96db72542e7d..e8f3d682e3b1 100644
--- a/drivers/char/drm/i915_drv.c
+++ b/drivers/char/drm/i915_drv.c
@@ -256,6 +256,9 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
256 pci_save_state(dev->pdev); 256 pci_save_state(dev->pdev);
257 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB); 257 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
258 258
259 /* Display arbitration control */
260 dev_priv->saveDSPARB = I915_READ(DSPARB);
261
259 /* Pipe & plane A info */ 262 /* Pipe & plane A info */
260 dev_priv->savePIPEACONF = I915_READ(PIPEACONF); 263 dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
261 dev_priv->savePIPEASRC = I915_READ(PIPEASRC); 264 dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
@@ -349,6 +352,7 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
349 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL); 352 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
350 353
351 /* Clock gating state */ 354 /* Clock gating state */
355 dev_priv->saveD_STATE = I915_READ(D_STATE);
352 dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D); 356 dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
353 357
354 /* Cache mode state */ 358 /* Cache mode state */
@@ -388,6 +392,8 @@ static int i915_resume(struct drm_device *dev)
388 392
389 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); 393 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
390 394
395 I915_WRITE(DSPARB, dev_priv->saveDSPARB);
396
391 /* Pipe & plane A info */ 397 /* Pipe & plane A info */
392 /* Prime the clock */ 398 /* Prime the clock */
393 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) { 399 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
@@ -507,6 +513,7 @@ static int i915_resume(struct drm_device *dev)
507 udelay(150); 513 udelay(150);
508 514
509 /* Clock gating state */ 515 /* Clock gating state */
516 I915_WRITE (D_STATE, dev_priv->saveD_STATE);
510 I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D); 517 I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
511 518
512 /* Cache mode state */ 519 /* Cache mode state */
diff --git a/drivers/char/drm/i915_drv.h b/drivers/char/drm/i915_drv.h
index 7619c49e5885..1b20f7c0639c 100644
--- a/drivers/char/drm/i915_drv.h
+++ b/drivers/char/drm/i915_drv.h
@@ -119,6 +119,7 @@ typedef struct drm_i915_private {
119 u8 saveLBB; 119 u8 saveLBB;
120 u32 saveDSPACNTR; 120 u32 saveDSPACNTR;
121 u32 saveDSPBCNTR; 121 u32 saveDSPBCNTR;
122 u32 saveDSPARB;
122 u32 savePIPEACONF; 123 u32 savePIPEACONF;
123 u32 savePIPEBCONF; 124 u32 savePIPEBCONF;
124 u32 savePIPEASRC; 125 u32 savePIPEASRC;
@@ -188,6 +189,7 @@ typedef struct drm_i915_private {
188 u32 saveIIR; 189 u32 saveIIR;
189 u32 saveIMR; 190 u32 saveIMR;
190 u32 saveCACHE_MODE_0; 191 u32 saveCACHE_MODE_0;
192 u32 saveD_STATE;
191 u32 saveDSPCLK_GATE_D; 193 u32 saveDSPCLK_GATE_D;
192 u32 saveMI_ARB_STATE; 194 u32 saveMI_ARB_STATE;
193 u32 saveSWF0[16]; 195 u32 saveSWF0[16];
@@ -670,6 +672,8 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
670/** P1 value is 2 greater than this field */ 672/** P1 value is 2 greater than this field */
671# define VGA0_PD_P1_MASK (0x1f << 0) 673# define VGA0_PD_P1_MASK (0x1f << 0)
672 674
675/* PCI D state control register */
676#define D_STATE 0x6104
673#define DSPCLK_GATE_D 0x6200 677#define DSPCLK_GATE_D 0x6200
674 678
675/* I830 CRTC registers */ 679/* I830 CRTC registers */
@@ -980,6 +984,12 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
980#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 984#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
981#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 985#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
982 986
987#define DSPARB 0x70030
988#define DSPARB_CSTART_MASK (0x7f << 7)
989#define DSPARB_CSTART_SHIFT 7
990#define DSPARB_BSTART_MASK (0x7f)
991#define DSPARB_BSTART_SHIFT 0
992
983#define PIPEBCONF 0x71008 993#define PIPEBCONF 0x71008
984#define PIPEBCONF_ENABLE (1<<31) 994#define PIPEBCONF_ENABLE (1<<31)
985#define PIPEBCONF_DISABLE 0 995#define PIPEBCONF_DISABLE 0