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authorLinus Torvalds <torvalds@linux-foundation.org>2009-09-24 13:30:41 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-09-24 13:30:41 -0400
commit94e0fb086fc5663c38bbc0fe86d698be8314f82f (patch)
tree1c3be6c71ec3511aa2a4eb6dfa25f35677464ebb /drivers/char
parentb7f21bb2e23b4fec16b448a34889f467465be659 (diff)
parentc715089f49844260f1eeae8e3b55af9468ba1325 (diff)
Merge branch 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: (57 commits) drm/i915: Handle ERESTARTSYS during page fault drm/i915: Warn before mmaping a purgeable buffer. drm/i915: Track purged state. drm/i915: Remove eviction debug spam drm/i915: Immediately discard any backing storage for uneeded objects drm/i915: Do not mis-classify clean objects as purgeable drm/i915: Whitespace correction for madv drm/i915: BUG_ON page refleak during unbind drm/i915: Search harder for a reusable object drm/i915: Clean up evict from list. drm/i915: Add tracepoints drm/i915: framebuffer compression for GM45+ drm/i915: split display functions by chip type drm/i915: Skip the sanity checks if the current relocation is valid drm/i915: Check that the relocation points to within the target drm/i915: correct FBC update when pipe base update occurs drm/i915: blacklist Acer AspireOne lid status ACPI: make ACPI button funcs no-ops if not built in drm/i915: prevent FIFO calculation overflows on 32 bits with high dotclocks drm/i915: intel_display.c handle latency variable efficiently ... Fix up trivial conflicts in drivers/gpu/drm/i915/{i915_dma.c|i915_drv.h}
Diffstat (limited to 'drivers/char')
-rw-r--r--drivers/char/agp/intel-agp.c37
1 files changed, 30 insertions, 7 deletions
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index 1540e693d91e..4068467ce7b9 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -46,6 +46,8 @@
46#define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2 46#define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
47#define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0 47#define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
48#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 48#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
49#define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40
50#define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42
49#define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40 51#define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40
50#define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42 52#define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42
51#define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00 53#define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00
@@ -91,6 +93,7 @@
91 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \ 93 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
92 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \ 94 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
93 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \ 95 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
96 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \
94 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \ 97 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \
95 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB || \ 98 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB || \
96 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MA_HB) 99 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MA_HB)
@@ -804,23 +807,39 @@ static void intel_i830_setup_flush(void)
804 if (!intel_private.i8xx_page) 807 if (!intel_private.i8xx_page)
805 return; 808 return;
806 809
807 /* make page uncached */
808 map_page_into_agp(intel_private.i8xx_page);
809
810 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); 810 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
811 if (!intel_private.i8xx_flush_page) 811 if (!intel_private.i8xx_flush_page)
812 intel_i830_fini_flush(); 812 intel_i830_fini_flush();
813} 813}
814 814
815static void
816do_wbinvd(void *null)
817{
818 wbinvd();
819}
820
821/* The chipset_flush interface needs to get data that has already been
822 * flushed out of the CPU all the way out to main memory, because the GPU
823 * doesn't snoop those buffers.
824 *
825 * The 8xx series doesn't have the same lovely interface for flushing the
826 * chipset write buffers that the later chips do. According to the 865
827 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
828 * that buffer out, we just fill 1KB and clflush it out, on the assumption
829 * that it'll push whatever was in there out. It appears to work.
830 */
815static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) 831static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
816{ 832{
817 unsigned int *pg = intel_private.i8xx_flush_page; 833 unsigned int *pg = intel_private.i8xx_flush_page;
818 int i;
819 834
820 for (i = 0; i < 256; i += 2) 835 memset(pg, 0, 1024);
821 *(pg + i) = i;
822 836
823 wmb(); 837 if (cpu_has_clflush) {
838 clflush_cache_range(pg, 1024);
839 } else {
840 if (on_each_cpu(do_wbinvd, NULL, 1) != 0)
841 printk(KERN_ERR "Timed out waiting for cache flush.\n");
842 }
824} 843}
825 844
826/* The intel i830 automatically initializes the agp aperture during POST. 845/* The intel i830 automatically initializes the agp aperture during POST.
@@ -1341,6 +1360,7 @@ static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1341 case PCI_DEVICE_ID_INTEL_Q45_HB: 1360 case PCI_DEVICE_ID_INTEL_Q45_HB:
1342 case PCI_DEVICE_ID_INTEL_G45_HB: 1361 case PCI_DEVICE_ID_INTEL_G45_HB:
1343 case PCI_DEVICE_ID_INTEL_G41_HB: 1362 case PCI_DEVICE_ID_INTEL_G41_HB:
1363 case PCI_DEVICE_ID_INTEL_B43_HB:
1344 case PCI_DEVICE_ID_INTEL_IGDNG_D_HB: 1364 case PCI_DEVICE_ID_INTEL_IGDNG_D_HB:
1345 case PCI_DEVICE_ID_INTEL_IGDNG_M_HB: 1365 case PCI_DEVICE_ID_INTEL_IGDNG_M_HB:
1346 case PCI_DEVICE_ID_INTEL_IGDNG_MA_HB: 1366 case PCI_DEVICE_ID_INTEL_IGDNG_MA_HB:
@@ -2335,6 +2355,8 @@ static const struct intel_driver_description {
2335 "Q45/Q43", NULL, &intel_i965_driver }, 2355 "Q45/Q43", NULL, &intel_i965_driver },
2336 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0, 2356 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2337 "G45/G43", NULL, &intel_i965_driver }, 2357 "G45/G43", NULL, &intel_i965_driver },
2358 { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG, 0,
2359 "B43", NULL, &intel_i965_driver },
2338 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0, 2360 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
2339 "G41", NULL, &intel_i965_driver }, 2361 "G41", NULL, &intel_i965_driver },
2340 { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0, 2362 { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0,
@@ -2535,6 +2557,7 @@ static struct pci_device_id agp_intel_pci_table[] = {
2535 ID(PCI_DEVICE_ID_INTEL_Q45_HB), 2557 ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2536 ID(PCI_DEVICE_ID_INTEL_G45_HB), 2558 ID(PCI_DEVICE_ID_INTEL_G45_HB),
2537 ID(PCI_DEVICE_ID_INTEL_G41_HB), 2559 ID(PCI_DEVICE_ID_INTEL_G41_HB),
2560 ID(PCI_DEVICE_ID_INTEL_B43_HB),
2538 ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB), 2561 ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB),
2539 ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB), 2562 ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB),
2540 ID(PCI_DEVICE_ID_INTEL_IGDNG_MA_HB), 2563 ID(PCI_DEVICE_ID_INTEL_IGDNG_MA_HB),