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authorBjorn Helgaas <bhelgaas@google.com>2014-01-06 16:39:40 -0500
committerBjorn Helgaas <bhelgaas@google.com>2014-01-07 13:36:50 -0500
commit5acc4ce44cd0a9cf5dbcfe50085708e9156e0177 (patch)
tree826f131df8fede89868655e71c6fd3b531d95390 /drivers/char
parent21c346075c0694581303ff04ff2be021587e4b40 (diff)
agp/intel: Rename gtt_bus_addr to gtt_phys_addr
The only use of gtt_bus_addr is as an argument to ioremap(), so it is a CPU physical address, not a bus address. Rename it to gtt_phys_addr to reflect this. No functional change. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/char')
-rw-r--r--drivers/char/agp/intel-gtt.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index b8e2014cb9cb..54202ffcf467 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -64,7 +64,7 @@ static struct _intel_private {
64 struct pci_dev *pcidev; /* device one */ 64 struct pci_dev *pcidev; /* device one */
65 struct pci_dev *bridge_dev; 65 struct pci_dev *bridge_dev;
66 u8 __iomem *registers; 66 u8 __iomem *registers;
67 phys_addr_t gtt_bus_addr; 67 phys_addr_t gtt_phys_addr;
68 u32 PGETBL_save; 68 u32 PGETBL_save;
69 u32 __iomem *gtt; /* I915G */ 69 u32 __iomem *gtt; /* I915G */
70 bool clear_fake_agp; /* on first access via agp, fill with scratch */ 70 bool clear_fake_agp; /* on first access via agp, fill with scratch */
@@ -191,7 +191,7 @@ static int i810_setup(void)
191 writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED, 191 writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
192 intel_private.registers+I810_PGETBL_CTL); 192 intel_private.registers+I810_PGETBL_CTL);
193 193
194 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; 194 intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
195 195
196 if ((readl(intel_private.registers+I810_DRAM_CTL) 196 if ((readl(intel_private.registers+I810_DRAM_CTL)
197 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 197 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
@@ -636,10 +636,10 @@ static int intel_gtt_init(void)
636 636
637 intel_private.gtt = NULL; 637 intel_private.gtt = NULL;
638 if (intel_gtt_can_wc()) 638 if (intel_gtt_can_wc())
639 intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr, 639 intel_private.gtt = ioremap_wc(intel_private.gtt_phys_addr,
640 gtt_map_size); 640 gtt_map_size);
641 if (intel_private.gtt == NULL) 641 if (intel_private.gtt == NULL)
642 intel_private.gtt = ioremap(intel_private.gtt_bus_addr, 642 intel_private.gtt = ioremap(intel_private.gtt_phys_addr,
643 gtt_map_size); 643 gtt_map_size);
644 if (intel_private.gtt == NULL) { 644 if (intel_private.gtt == NULL) {
645 intel_private.driver->cleanup(); 645 intel_private.driver->cleanup();
@@ -796,7 +796,7 @@ static int i830_setup(void)
796 if (!intel_private.registers) 796 if (!intel_private.registers)
797 return -ENOMEM; 797 return -ENOMEM;
798 798
799 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; 799 intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
800 800
801 return 0; 801 return 0;
802} 802}
@@ -1123,13 +1123,13 @@ static int i9xx_setup(void)
1123 case 3: 1123 case 3:
1124 pci_read_config_dword(intel_private.pcidev, 1124 pci_read_config_dword(intel_private.pcidev,
1125 I915_PTEADDR, &gtt_addr); 1125 I915_PTEADDR, &gtt_addr);
1126 intel_private.gtt_bus_addr = gtt_addr; 1126 intel_private.gtt_phys_addr = gtt_addr;
1127 break; 1127 break;
1128 case 5: 1128 case 5:
1129 intel_private.gtt_bus_addr = reg_addr + MB(2); 1129 intel_private.gtt_phys_addr = reg_addr + MB(2);
1130 break; 1130 break;
1131 default: 1131 default:
1132 intel_private.gtt_bus_addr = reg_addr + KB(512); 1132 intel_private.gtt_phys_addr = reg_addr + KB(512);
1133 break; 1133 break;
1134 } 1134 }
1135 1135