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authorThomas Hellstrom <thomas@tungstengraphics.com>2006-12-27 07:16:49 -0500
committerDave Jones <davej@redhat.com>2006-12-28 22:24:45 -0500
commit7f02d687b44aba0cfc393102ea1ccc78eadf8a04 (patch)
tree8370a17d4132ebda939701d816b3ee738a72ef52 /drivers/char
parentc41e0deb50c44f9d119c2268f1be05e6a6bb5772 (diff)
[AGPGART] Fix PCI-posting flush typo.
Unfortunately there was a typo in one of the patches I sent, (The one now committed to the agpgart tree). It may cause a bus error on i810 type hardware. Signed-off-by: Thomas Hellstrom <thomas@tungstengraphics.com> Signed-off-by: Dave Jones <davej@redhat.com>
Diffstat (limited to 'drivers/char')
-rw-r--r--drivers/char/agp/intel-agp.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index ccb8018b831f..ab0a9c0ad7c0 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -253,7 +253,7 @@ insert:
253 mem->memory[i], mem->type), 253 mem->memory[i], mem->type),
254 intel_i810_private.registers+I810_PTE_BASE+(j*4)); 254 intel_i810_private.registers+I810_PTE_BASE+(j*4));
255 } 255 }
256 readl(intel_i810_private.registers+I810_PTE_BASE+(j-1*4)); /* PCI Posting. */ 256 readl(intel_i810_private.registers+I810_PTE_BASE+((j-1)*4)); /* PCI Posting. */
257 257
258 agp_bridge->driver->tlb_flush(mem); 258 agp_bridge->driver->tlb_flush(mem);
259 return 0; 259 return 0;