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authorAlex Deucher <alexdeucher@gmail.com>2008-05-27 21:57:40 -0400
committerDave Airlie <airlied@redhat.com>2008-06-18 21:27:40 -0400
commit5b92c4045eaa42441b7ec249a406e4110ea400d4 (patch)
tree5ee8b6907868b0fb7cd62272f6df0b612ed8bb2c /drivers/char
parentd396db321bcaec54345e7e9e87cea8482d6ae3a8 (diff)
drm/radeon: init pipe setup in kernel code.
This inits the card pipes in the kernel and lets userspace getparam the correct setup. Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/char')
-rw-r--r--drivers/char/drm/radeon_cp.c48
-rw-r--r--drivers/char/drm/radeon_drm.h1
-rw-r--r--drivers/char/drm/radeon_drv.h23
-rw-r--r--drivers/char/drm/radeon_state.c3
4 files changed, 75 insertions, 0 deletions
diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c
index 77bd90f6d414..599187558abb 100644
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@ -247,6 +247,50 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
247 return -EBUSY; 247 return -EBUSY;
248} 248}
249 249
250static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
251{
252 uint32_t gb_tile_config, gb_pipe_sel = 0;
253
254 /* RS4xx/RS6xx/R4xx/R5xx */
255 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
256 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
257 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
258 } else {
259 /* R3xx */
260 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
261 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
262 dev_priv->num_gb_pipes = 2;
263 } else {
264 /* R3Vxx */
265 dev_priv->num_gb_pipes = 1;
266 }
267 }
268 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
269
270 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
271
272 switch (dev_priv->num_gb_pipes) {
273 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
274 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
275 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
276 default:
277 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
278 }
279
280 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
281 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
282 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
283 }
284 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
285 radeon_do_wait_for_idle(dev_priv);
286 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
287 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
288 R300_DC_AUTOFLUSH_ENABLE |
289 R300_DC_DC_DISABLE_IGNORE_PE));
290
291
292}
293
250/* ================================================================ 294/* ================================================================
251 * CP control, initialization 295 * CP control, initialization
252 */ 296 */
@@ -464,6 +508,10 @@ static int radeon_do_engine_reset(struct drm_device * dev)
464 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); 508 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
465 } 509 }
466 510
511 /* setup the raster pipes */
512 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
513 radeon_init_pipes(dev_priv);
514
467 /* Reset the CP ring */ 515 /* Reset the CP ring */
468 radeon_do_cp_reset(dev_priv); 516 radeon_do_cp_reset(dev_priv);
469 517
diff --git a/drivers/char/drm/radeon_drm.h b/drivers/char/drm/radeon_drm.h
index aab82e121e07..68b0608e01c9 100644
--- a/drivers/char/drm/radeon_drm.h
+++ b/drivers/char/drm/radeon_drm.h
@@ -669,6 +669,7 @@ typedef struct drm_radeon_indirect {
669#define RADEON_PARAM_CARD_TYPE 12 669#define RADEON_PARAM_CARD_TYPE 12
670#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ 670#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
671#define RADEON_PARAM_FB_LOCATION 14 /* FB location */ 671#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
672#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
672 673
673typedef struct drm_radeon_getparam { 674typedef struct drm_radeon_getparam {
674 int param; 675 int param;
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index 5e6f4612adba..c3615cf20b85 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -307,6 +307,8 @@ typedef struct drm_radeon_private {
307 /* starting from here on, data is preserved accross an open */ 307 /* starting from here on, data is preserved accross an open */
308 uint32_t flags; /* see radeon_chip_flags */ 308 uint32_t flags; /* see radeon_chip_flags */
309 unsigned long fb_aper_offset; 309 unsigned long fb_aper_offset;
310
311 int num_gb_pipes;
310} drm_radeon_private_t; 312} drm_radeon_private_t;
311 313
312typedef struct drm_radeon_buf_priv { 314typedef struct drm_radeon_buf_priv {
@@ -529,6 +531,27 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
529#define RS480_AGP_BASE_2 0x0164 531#define RS480_AGP_BASE_2 0x0164
530#define RADEON_AGP_BASE 0x0170 532#define RADEON_AGP_BASE 0x0170
531 533
534/* pipe config regs */
535#define R400_GB_PIPE_SELECT 0x402c
536#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
537#define R500_SU_REG_DEST 0x42c8
538#define R300_GB_TILE_CONFIG 0x4018
539# define R300_ENABLE_TILING (1 << 0)
540# define R300_PIPE_COUNT_RV350 (0 << 1)
541# define R300_PIPE_COUNT_R300 (3 << 1)
542# define R300_PIPE_COUNT_R420_3P (6 << 1)
543# define R300_PIPE_COUNT_R420 (7 << 1)
544# define R300_TILE_SIZE_8 (0 << 4)
545# define R300_TILE_SIZE_16 (1 << 4)
546# define R300_TILE_SIZE_32 (2 << 4)
547# define R300_SUBPIXEL_1_12 (0 << 16)
548# define R300_SUBPIXEL_1_16 (1 << 16)
549#define R300_DST_PIPE_CONFIG 0x170c
550# define R300_PIPE_AUTO_CONFIG (1 << 31)
551#define R300_RB2D_DSTCACHE_MODE 0x3428
552# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
553# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
554
532#define RADEON_RB3D_COLOROFFSET 0x1c40 555#define RADEON_RB3D_COLOROFFSET 0x1c40
533#define RADEON_RB3D_COLORPITCH 0x1c48 556#define RADEON_RB3D_COLORPITCH 0x1c48
534 557
diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c
index 6f75512f591e..eee135712403 100644
--- a/drivers/char/drm/radeon_state.c
+++ b/drivers/char/drm/radeon_state.c
@@ -3037,6 +3037,9 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
3037 case RADEON_PARAM_FB_LOCATION: 3037 case RADEON_PARAM_FB_LOCATION:
3038 value = radeon_read_fb_location(dev_priv); 3038 value = radeon_read_fb_location(dev_priv);
3039 break; 3039 break;
3040 case RADEON_PARAM_NUM_GB_PIPES:
3041 value = dev_priv->num_gb_pipes;
3042 break;
3040 default: 3043 default:
3041 DRM_DEBUG("Invalid parameter %d\n", param->param); 3044 DRM_DEBUG("Invalid parameter %d\n", param->param);
3042 return -EINVAL; 3045 return -EINVAL;