diff options
author | Eric Anholt <eric@anholt.net> | 2010-03-18 15:19:37 -0400 |
---|---|---|
committer | Eric Anholt <eric@anholt.net> | 2010-03-18 19:48:00 -0400 |
commit | 66f6ff09ff67c45919b336395c4d7d0ed3a97edc (patch) | |
tree | a559ad7e46eeaca0cb16d3b576e351740d4909df /drivers/char | |
parent | 285aca8e2a7f8af2a18cf89d1dfa95df2f9c9132 (diff) |
agp/intel: Don't do the chipset flush on Sandybridge.
This CPU should be coherent with graphics in this direction, though
flushing graphics caches are still required. Fixes a system reset on
module load on Sandybridge with 4G+ memory.
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/char')
-rw-r--r-- | drivers/char/agp/intel-agp.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c index f499c5e0ca54..b78d5c381efe 100644 --- a/drivers/char/agp/intel-agp.c +++ b/drivers/char/agp/intel-agp.c | |||
@@ -97,6 +97,9 @@ EXPORT_SYMBOL(intel_agp_enabled); | |||
97 | #define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \ | 97 | #define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \ |
98 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB) | 98 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB) |
99 | 99 | ||
100 | #define IS_SNB (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \ | ||
101 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) | ||
102 | |||
100 | #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \ | 103 | #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \ |
101 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \ | 104 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \ |
102 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \ | 105 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \ |
@@ -107,8 +110,7 @@ EXPORT_SYMBOL(intel_agp_enabled); | |||
107 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \ | 110 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \ |
108 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \ | 111 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \ |
109 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \ | 112 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \ |
110 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \ | 113 | IS_SNB) |
111 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) | ||
112 | 114 | ||
113 | extern int agp_memory_reserved; | 115 | extern int agp_memory_reserved; |
114 | 116 | ||
@@ -1204,6 +1206,9 @@ static void intel_i9xx_setup_flush(void) | |||
1204 | if (intel_private.ifp_resource.start) | 1206 | if (intel_private.ifp_resource.start) |
1205 | return; | 1207 | return; |
1206 | 1208 | ||
1209 | if (IS_SNB) | ||
1210 | return; | ||
1211 | |||
1207 | /* setup a resource for this object */ | 1212 | /* setup a resource for this object */ |
1208 | intel_private.ifp_resource.name = "Intel Flush Page"; | 1213 | intel_private.ifp_resource.name = "Intel Flush Page"; |
1209 | intel_private.ifp_resource.flags = IORESOURCE_MEM; | 1214 | intel_private.ifp_resource.flags = IORESOURCE_MEM; |