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authorJiri Slaby <jirislaby@gmail.com>2008-02-07 03:16:46 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2008-02-07 11:42:34 -0500
commit1c45607ad3eb7397bc2433f3c36a4ed8b315889e (patch)
treeb6794a82b1b18b7249d39883877e197d5961cced /drivers/char
parentf122bfb5a43c6b57733eb7a76ad4ed392be6a910 (diff)
Char: mxser, remove it
(Old) mxser is obsoleted by mxser_new and scheduled for removal on Dec 2007. Remove it by renaming mxser_new to mxser. Signed-off-by: Jiri Slaby <jirislaby@gmail.com> Reviewed-by: Alan Cox <alan@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/char')
-rw-r--r--drivers/char/Kconfig13
-rw-r--r--drivers/char/Makefile1
-rw-r--r--drivers/char/mxser.c3868
-rw-r--r--drivers/char/mxser.h478
-rw-r--r--drivers/char/mxser_new.c2729
-rw-r--r--drivers/char/mxser_new.h287
6 files changed, 1891 insertions, 5485 deletions
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index 85bf9b2aa74a..7927fd0faca3 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -194,17 +194,6 @@ config MOXA_INTELLIO
194 module will be called moxa. 194 module will be called moxa.
195 195
196config MOXA_SMARTIO 196config MOXA_SMARTIO
197 tristate "Moxa SmartIO support (OBSOLETE)"
198 depends on SERIAL_NONSTANDARD
199 help
200 Say Y here if you have a Moxa SmartIO multiport serial card.
201
202 This driver can also be built as a module ( = code which can be
203 inserted in and removed from the running kernel whenever you want).
204 The module will be called mxser. If you want to do that, say M
205 here.
206
207config MOXA_SMARTIO_NEW
208 tristate "Moxa SmartIO support v. 2.0" 197 tristate "Moxa SmartIO support v. 2.0"
209 depends on SERIAL_NONSTANDARD && (PCI || EISA || ISA) 198 depends on SERIAL_NONSTANDARD && (PCI || EISA || ISA)
210 help 199 help
@@ -215,7 +204,7 @@ config MOXA_SMARTIO_NEW
215 changes finally resulting in PCI probing. 204 changes finally resulting in PCI probing.
216 205
217 This driver can also be built as a module. The module will be called 206 This driver can also be built as a module. The module will be called
218 mxser_new. If you want to do that, say M here. 207 mxser. If you want to do that, say M here.
219 208
220config ISI 209config ISI
221 tristate "Multi-Tech multiport card support (EXPERIMENTAL)" 210 tristate "Multi-Tech multiport card support (EXPERIMENTAL)"
diff --git a/drivers/char/Makefile b/drivers/char/Makefile
index 96fc01eddefe..4396e37b3d0f 100644
--- a/drivers/char/Makefile
+++ b/drivers/char/Makefile
@@ -33,7 +33,6 @@ obj-$(CONFIG_MOXA_INTELLIO) += moxa.o
33obj-$(CONFIG_A2232) += ser_a2232.o generic_serial.o 33obj-$(CONFIG_A2232) += ser_a2232.o generic_serial.o
34obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o 34obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o
35obj-$(CONFIG_MOXA_SMARTIO) += mxser.o 35obj-$(CONFIG_MOXA_SMARTIO) += mxser.o
36obj-$(CONFIG_MOXA_SMARTIO_NEW) += mxser_new.o
37obj-$(CONFIG_COMPUTONE) += ip2/ 36obj-$(CONFIG_COMPUTONE) += ip2/
38obj-$(CONFIG_RISCOM8) += riscom8.o 37obj-$(CONFIG_RISCOM8) += riscom8.o
39obj-$(CONFIG_ISI) += isicom.o 38obj-$(CONFIG_ISI) += isicom.o
diff --git a/drivers/char/mxser.c b/drivers/char/mxser.c
index 35ff7a245540..dd1b0ab4b310 100644
--- a/drivers/char/mxser.c
+++ b/drivers/char/mxser.c
@@ -1,41 +1,24 @@
1/* 1/*
2 * mxser.c -- MOXA Smartio/Industio family multiport serial driver. 2 * mxser.c -- MOXA Smartio/Industio family multiport serial driver.
3 * 3 *
4 * Copyright (C) 1999-2001 Moxa Technologies (support@moxa.com.tw). 4 * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com.tw).
5 * Copyright (C) 2006-2007 Jiri Slaby <jirislaby@gmail.com>
5 * 6 *
6 * This code is loosely based on the Linux serial driver, written by 7 * This code is loosely based on the 1.8 moxa driver which is based on
7 * Linus Torvalds, Theodore T'so and others. 8 * Linux serial driver, written by Linus Torvalds, Theodore T'so and
9 * others.
8 * 10 *
9 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by 12 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or 13 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version. 14 * (at your option) any later version.
13 * 15 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 * Original release 10/26/00
24 *
25 * 02/06/01 Support MOXA Industio family boards.
26 * 02/06/01 Support TIOCGICOUNT.
27 * 02/06/01 Fix the problem for connecting to serial mouse.
28 * 02/06/01 Fix the problem for H/W flow control.
29 * 02/06/01 Fix the compling warning when CONFIG_PCI
30 * don't be defined.
31 *
32 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox 16 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
33 * <alan@redhat.com>. The original 1.8 code is available on www.moxa.com. 17 * <alan@redhat.com>. The original 1.8 code is available on www.moxa.com.
34 * - Fixed x86_64 cleanness 18 * - Fixed x86_64 cleanness
35 * - Fixed sleep with spinlock held in mxser_send_break 19 * - Fixed sleep with spinlock held in mxser_send_break
36 */ 20 */
37 21
38
39#include <linux/module.h> 22#include <linux/module.h>
40#include <linux/errno.h> 23#include <linux/errno.h>
41#include <linux/signal.h> 24#include <linux/signal.h>
@@ -64,30 +47,36 @@
64 47
65#include "mxser.h" 48#include "mxser.h"
66 49
67#define MXSER_VERSION "1.8" 50#define MXSER_VERSION "2.0.2" /* 1.10 */
68#define MXSERMAJOR 174 51#define MXSERMAJOR 174
69#define MXSERCUMAJOR 175 52#define MXSERCUMAJOR 175
70 53
71#define MXSER_EVENT_TXLOW 1
72#define MXSER_EVENT_HANGUP 2
73
74#define MXSER_BOARDS 4 /* Max. boards */ 54#define MXSER_BOARDS 4 /* Max. boards */
75#define MXSER_PORTS 32 /* Max. ports */
76#define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */ 55#define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */
77#define MXSER_ISR_PASS_LIMIT 256 56#define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
57#define MXSER_ISR_PASS_LIMIT 100
78 58
79#define MXSER_ERR_IOADDR -1 59#define MXSER_ERR_IOADDR -1
80#define MXSER_ERR_IRQ -2 60#define MXSER_ERR_IRQ -2
81#define MXSER_ERR_IRQ_CONFLIT -3 61#define MXSER_ERR_IRQ_CONFLIT -3
82#define MXSER_ERR_VECTOR -4 62#define MXSER_ERR_VECTOR -4
83 63
64/*CheckIsMoxaMust return value*/
65#define MOXA_OTHER_UART 0x00
66#define MOXA_MUST_MU150_HWID 0x01
67#define MOXA_MUST_MU860_HWID 0x02
68
84#define WAKEUP_CHARS 256 69#define WAKEUP_CHARS 256
85 70
86#define UART_MCR_AFE 0x20 71#define UART_MCR_AFE 0x20
87#define UART_LSR_SPECIAL 0x1E 72#define UART_LSR_SPECIAL 0x1E
88 73
74#define PCI_DEVICE_ID_CB108 0x1080
75#define PCI_DEVICE_ID_CB114 0x1142
76#define PCI_DEVICE_ID_CB134I 0x1341
77#define PCI_DEVICE_ID_CP138U 0x1380
78#define PCI_DEVICE_ID_POS104UL 0x1044
89 79
90#define IRQ_T(info) ((info->flags & ASYNC_SHARE_IRQ) ? IRQF_SHARED : IRQF_DISABLED)
91 80
92#define C168_ASIC_ID 1 81#define C168_ASIC_ID 1
93#define C104_ASIC_ID 2 82#define C104_ASIC_ID 2
@@ -96,88 +85,11 @@
96#define CI134_ASIC_ID 3 85#define CI134_ASIC_ID 3
97#define CI104J_ASIC_ID 5 86#define CI104J_ASIC_ID 5
98 87
99enum { 88#define MXSER_HIGHBAUD 1
100 MXSER_BOARD_C168_ISA = 1, 89#define MXSER_HAS2 2
101 MXSER_BOARD_C104_ISA,
102 MXSER_BOARD_CI104J,
103 MXSER_BOARD_C168_PCI,
104 MXSER_BOARD_C104_PCI,
105 MXSER_BOARD_C102_ISA,
106 MXSER_BOARD_CI132,
107 MXSER_BOARD_CI134,
108 MXSER_BOARD_CP132,
109 MXSER_BOARD_CP114,
110 MXSER_BOARD_CT114,
111 MXSER_BOARD_CP102,
112 MXSER_BOARD_CP104U,
113 MXSER_BOARD_CP168U,
114 MXSER_BOARD_CP132U,
115 MXSER_BOARD_CP134U,
116 MXSER_BOARD_CP104JU,
117 MXSER_BOARD_RC7000,
118 MXSER_BOARD_CP118U,
119 MXSER_BOARD_CP102UL,
120 MXSER_BOARD_CP102U,
121};
122
123static char *mxser_brdname[] = {
124 "C168 series",
125 "C104 series",
126 "CI-104J series",
127 "C168H/PCI series",
128 "C104H/PCI series",
129 "C102 series",
130 "CI-132 series",
131 "CI-134 series",
132 "CP-132 series",
133 "CP-114 series",
134 "CT-114 series",
135 "CP-102 series",
136 "CP-104U series",
137 "CP-168U series",
138 "CP-132U series",
139 "CP-134U series",
140 "CP-104JU series",
141 "Moxa UC7000 Serial",
142 "CP-118U series",
143 "CP-102UL series",
144 "CP-102U series",
145};
146
147static int mxser_numports[] = {
148 8, /* C168-ISA */
149 4, /* C104-ISA */
150 4, /* CI104J */
151 8, /* C168-PCI */
152 4, /* C104-PCI */
153 2, /* C102-ISA */
154 2, /* CI132 */
155 4, /* CI134 */
156 2, /* CP132 */
157 4, /* CP114 */
158 4, /* CT114 */
159 2, /* CP102 */
160 4, /* CP104U */
161 8, /* CP168U */
162 2, /* CP132U */
163 4, /* CP134U */
164 4, /* CP104JU */
165 8, /* RC7000 */
166 8, /* CP118U */
167 2, /* CP102UL */
168 2, /* CP102U */
169};
170
171#define UART_TYPE_NUM 2
172
173static const unsigned int Gmoxa_uart_id[UART_TYPE_NUM] = {
174 MOXA_MUST_MU150_HWID,
175 MOXA_MUST_MU860_HWID
176};
177 90
178/* This is only for PCI */ 91/* This is only for PCI */
179#define UART_INFO_NUM 3 92static const struct {
180struct mxpciuart_info {
181 int type; 93 int type;
182 int tx_fifo; 94 int tx_fifo;
183 int rx_fifo; 95 int rx_fifo;
@@ -186,51 +98,83 @@ struct mxpciuart_info {
186 int rx_trigger; 98 int rx_trigger;
187 int rx_low_water; 99 int rx_low_water;
188 long max_baud; 100 long max_baud;
189}; 101} Gpci_uart_info[] = {
190
191static const struct mxpciuart_info Gpci_uart_info[UART_INFO_NUM] = {
192 {MOXA_OTHER_UART, 16, 16, 16, 14, 14, 1, 921600L}, 102 {MOXA_OTHER_UART, 16, 16, 16, 14, 14, 1, 921600L},
193 {MOXA_MUST_MU150_HWID, 64, 64, 64, 48, 48, 16, 230400L}, 103 {MOXA_MUST_MU150_HWID, 64, 64, 64, 48, 48, 16, 230400L},
194 {MOXA_MUST_MU860_HWID, 128, 128, 128, 96, 96, 32, 921600L} 104 {MOXA_MUST_MU860_HWID, 128, 128, 128, 96, 96, 32, 921600L}
195}; 105};
106#define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info)
196 107
108struct mxser_cardinfo {
109 char *name;
110 unsigned int nports;
111 unsigned int flags;
112};
197 113
198#ifdef CONFIG_PCI 114static const struct mxser_cardinfo mxser_cards[] = {
115/* 0*/ { "C168 series", 8, },
116 { "C104 series", 4, },
117 { "CI-104J series", 4, },
118 { "C168H/PCI series", 8, },
119 { "C104H/PCI series", 4, },
120/* 5*/ { "C102 series", 4, MXSER_HAS2 }, /* C102-ISA */
121 { "CI-132 series", 4, MXSER_HAS2 },
122 { "CI-134 series", 4, },
123 { "CP-132 series", 2, },
124 { "CP-114 series", 4, },
125/*10*/ { "CT-114 series", 4, },
126 { "CP-102 series", 2, MXSER_HIGHBAUD },
127 { "CP-104U series", 4, },
128 { "CP-168U series", 8, },
129 { "CP-132U series", 2, },
130/*15*/ { "CP-134U series", 4, },
131 { "CP-104JU series", 4, },
132 { "Moxa UC7000 Serial", 8, }, /* RC7000 */
133 { "CP-118U series", 8, },
134 { "CP-102UL series", 2, },
135/*20*/ { "CP-102U series", 2, },
136 { "CP-118EL series", 8, },
137 { "CP-168EL series", 8, },
138 { "CP-104EL series", 4, },
139 { "CB-108 series", 8, },
140/*25*/ { "CB-114 series", 4, },
141 { "CB-134I series", 4, },
142 { "CP-138U series", 8, },
143 { "POS-104UL series", 4, }
144};
199 145
146/* driver_data correspond to the lines in the structure above
147 see also ISA probe function before you change something */
200static struct pci_device_id mxser_pcibrds[] = { 148static struct pci_device_id mxser_pcibrds[] = {
201 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_C168, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_C168_PCI}, 149 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C168), .driver_data = 3 },
202 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_C104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_C104_PCI}, 150 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C104), .driver_data = 4 },
203 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP132}, 151 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132), .driver_data = 8 },
204 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP114}, 152 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114), .driver_data = 9 },
205 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CT114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CT114}, 153 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CT114), .driver_data = 10 },
206 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP102}, 154 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102), .driver_data = 11 },
207 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104U, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP104U}, 155 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104U), .driver_data = 12 },
208 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168U, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP168U}, 156 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168U), .driver_data = 13 },
209 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132U, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP132U}, 157 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132U), .driver_data = 14 },
210 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134U, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP134U}, 158 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134U), .driver_data = 15 },
211 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104JU, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP104JU}, 159 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104JU),.driver_data = 16 },
212 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_RC7000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_RC7000}, 160 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_RC7000), .driver_data = 17 },
213 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118U, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP118U}, 161 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118U), .driver_data = 18 },
214 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102UL, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP102UL}, 162 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102UL),.driver_data = 19 },
215 {PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102U, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MXSER_BOARD_CP102U}, 163 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102U), .driver_data = 20 },
216 {0} 164 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL),.driver_data = 21 },
165 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL),.driver_data = 22 },
166 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL),.driver_data = 23 },
167 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB108), .driver_data = 24 },
168 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB114), .driver_data = 25 },
169 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB134I), .driver_data = 26 },
170 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP138U), .driver_data = 27 },
171 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_POS104UL), .driver_data = 28 },
172 { }
217}; 173};
218
219MODULE_DEVICE_TABLE(pci, mxser_pcibrds); 174MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
220 175
221
222#endif
223
224typedef struct _moxa_pci_info {
225 unsigned short busNum;
226 unsigned short devNum;
227 struct pci_dev *pdev; /* add by Victor Yu. 06-23-2003 */
228} moxa_pci_info;
229
230static int ioaddr[MXSER_BOARDS] = { 0, 0, 0, 0 }; 176static int ioaddr[MXSER_BOARDS] = { 0, 0, 0, 0 };
231static int ttymajor = MXSERMAJOR; 177static int ttymajor = MXSERMAJOR;
232static int calloutmajor = MXSERCUMAJOR;
233static int verbose = 0;
234 178
235/* Variables for insmod */ 179/* Variables for insmod */
236 180
@@ -238,8 +182,6 @@ MODULE_AUTHOR("Casper Yang");
238MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver"); 182MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
239module_param_array(ioaddr, int, NULL, 0); 183module_param_array(ioaddr, int, NULL, 0);
240module_param(ttymajor, int, 0); 184module_param(ttymajor, int, 0);
241module_param(calloutmajor, int, 0);
242module_param(verbose, bool, 0);
243MODULE_LICENSE("GPL"); 185MODULE_LICENSE("GPL");
244 186
245struct mxser_log { 187struct mxser_log {
@@ -274,67 +216,69 @@ struct mxser_mon_ext {
274 int iftype[32]; 216 int iftype[32];
275}; 217};
276 218
277struct mxser_hwconf { 219struct mxser_board;
278 int board_type; 220
279 int ports; 221struct mxser_port {
280 int irq; 222 struct mxser_board *board;
281 int vector; 223 struct tty_struct *tty;
282 int vector_mask; 224
283 int uart_type; 225 unsigned long ioaddr;
284 int ioaddr[MXSER_PORTS_PER_BOARD]; 226 unsigned long opmode_ioaddr;
285 int baud_base[MXSER_PORTS_PER_BOARD]; 227 int max_baud;
286 moxa_pci_info pciInfo;
287 int IsMoxaMustChipFlag; /* add by Victor Yu. 08-30-2002 */
288 int MaxCanSetBaudRate[MXSER_PORTS_PER_BOARD]; /* add by Victor Yu. 09-04-2002 */
289 int opmode_ioaddr[MXSER_PORTS_PER_BOARD]; /* add by Victor Yu. 01-05-2004 */
290};
291 228
292struct mxser_struct {
293 int port;
294 int base; /* port base address */
295 int irq; /* port using irq no. */
296 int vector; /* port irq vector */
297 int vectormask; /* port vector mask */
298 int rx_high_water; 229 int rx_high_water;
299 int rx_trigger; /* Rx fifo trigger level */ 230 int rx_trigger; /* Rx fifo trigger level */
300 int rx_low_water; 231 int rx_low_water;
301 int baud_base; /* max. speed */ 232 int baud_base; /* max. speed */
302 int flags; /* defined in tty.h */
303 int type; /* UART type */ 233 int type; /* UART type */
304 struct tty_struct *tty; 234 int flags; /* defined in tty.h */
305 int read_status_mask; 235
306 int ignore_status_mask;
307 int xmit_fifo_size;
308 int custom_divisor;
309 int x_char; /* xon/xoff character */ 236 int x_char; /* xon/xoff character */
310 int close_delay;
311 unsigned short closing_wait;
312 int IER; /* Interrupt Enable Register */ 237 int IER; /* Interrupt Enable Register */
313 int MCR; /* Modem control register */ 238 int MCR; /* Modem control register */
239
240 unsigned char stop_rx;
241 unsigned char ldisc_stop_rx;
242
243 int custom_divisor;
244 int close_delay;
245 unsigned short closing_wait;
246 unsigned char err_shadow;
314 unsigned long event; 247 unsigned long event;
248
315 int count; /* # of fd on device */ 249 int count; /* # of fd on device */
316 int blocked_open; /* # of blocked opens */ 250 int blocked_open; /* # of blocked opens */
251 struct async_icount icount; /* kernel counters for 4 input interrupts */
252 int timeout;
253
254 int read_status_mask;
255 int ignore_status_mask;
256 int xmit_fifo_size;
317 unsigned char *xmit_buf; 257 unsigned char *xmit_buf;
318 int xmit_head; 258 int xmit_head;
319 int xmit_tail; 259 int xmit_tail;
320 int xmit_cnt; 260 int xmit_cnt;
321 struct work_struct tqueue; 261
322 struct ktermios normal_termios; 262 struct ktermios normal_termios;
323 struct ktermios callout_termios; 263
324 wait_queue_head_t open_wait;
325 wait_queue_head_t close_wait;
326 wait_queue_head_t delta_msr_wait;
327 struct async_icount icount; /* kernel counters for the 4 input interrupts */
328 int timeout;
329 int IsMoxaMustChipFlag; /* add by Victor Yu. 08-30-2002 */
330 int MaxCanSetBaudRate; /* add by Victor Yu. 09-04-2002 */
331 int opmode_ioaddr; /* add by Victor Yu. 01-05-2004 */
332 unsigned char stop_rx;
333 unsigned char ldisc_stop_rx;
334 long realbaud;
335 struct mxser_mon mon_data; 264 struct mxser_mon mon_data;
336 unsigned char err_shadow; 265
337 spinlock_t slock; 266 spinlock_t slock;
267 wait_queue_head_t open_wait;
268 wait_queue_head_t delta_msr_wait;
269};
270
271struct mxser_board {
272 unsigned int idx;
273 int irq;
274 const struct mxser_cardinfo *info;
275 unsigned long vector;
276 unsigned long vector_mask;
277
278 int chip_flag;
279 int uart_type;
280
281 struct mxser_port ports[MXSER_PORTS_PER_BOARD];
338}; 282};
339 283
340struct mxser_mstatus { 284struct mxser_mstatus {
@@ -352,73 +296,16 @@ static int mxserBoardCAP[MXSER_BOARDS] = {
352 /* 0x180, 0x280, 0x200, 0x320 */ 296 /* 0x180, 0x280, 0x200, 0x320 */
353}; 297};
354 298
299static struct mxser_board mxser_boards[MXSER_BOARDS];
355static struct tty_driver *mxvar_sdriver; 300static struct tty_driver *mxvar_sdriver;
356static struct mxser_struct mxvar_table[MXSER_PORTS];
357static struct tty_struct *mxvar_tty[MXSER_PORTS + 1];
358static struct ktermios *mxvar_termios[MXSER_PORTS + 1];
359static struct ktermios *mxvar_termios_locked[MXSER_PORTS + 1];
360static struct mxser_log mxvar_log; 301static struct mxser_log mxvar_log;
361static int mxvar_diagflag; 302static int mxvar_diagflag;
362static unsigned char mxser_msr[MXSER_PORTS + 1]; 303static unsigned char mxser_msr[MXSER_PORTS + 1];
363static struct mxser_mon_ext mon_data_ext; 304static struct mxser_mon_ext mon_data_ext;
364static int mxser_set_baud_method[MXSER_PORTS + 1]; 305static int mxser_set_baud_method[MXSER_PORTS + 1];
365static spinlock_t gm_lock;
366
367/*
368 * This is used to figure out the divisor speeds and the timeouts
369 */
370
371static struct mxser_hwconf mxsercfg[MXSER_BOARDS];
372
373/*
374 * static functions:
375 */
376
377static void mxser_getcfg(int board, struct mxser_hwconf *hwconf);
378static int mxser_init(void);
379
380/* static void mxser_poll(unsigned long); */
381static int mxser_get_ISA_conf(int, struct mxser_hwconf *);
382static void mxser_do_softint(struct work_struct *);
383static int mxser_open(struct tty_struct *, struct file *);
384static void mxser_close(struct tty_struct *, struct file *);
385static int mxser_write(struct tty_struct *, const unsigned char *, int);
386static int mxser_write_room(struct tty_struct *);
387static void mxser_flush_buffer(struct tty_struct *);
388static int mxser_chars_in_buffer(struct tty_struct *);
389static void mxser_flush_chars(struct tty_struct *);
390static void mxser_put_char(struct tty_struct *, unsigned char);
391static int mxser_ioctl(struct tty_struct *, struct file *, uint, ulong);
392static int mxser_ioctl_special(unsigned int, void __user *);
393static void mxser_throttle(struct tty_struct *);
394static void mxser_unthrottle(struct tty_struct *);
395static void mxser_set_termios(struct tty_struct *, struct ktermios *);
396static void mxser_stop(struct tty_struct *);
397static void mxser_start(struct tty_struct *);
398static void mxser_hangup(struct tty_struct *);
399static void mxser_rs_break(struct tty_struct *, int);
400static irqreturn_t mxser_interrupt(int, void *);
401static void mxser_receive_chars(struct mxser_struct *, int *);
402static void mxser_transmit_chars(struct mxser_struct *);
403static void mxser_check_modem_status(struct mxser_struct *, int);
404static int mxser_block_til_ready(struct tty_struct *, struct file *, struct mxser_struct *);
405static int mxser_startup(struct mxser_struct *);
406static void mxser_shutdown(struct mxser_struct *);
407static int mxser_change_speed(struct mxser_struct *, struct ktermios *old_termios);
408static int mxser_get_serial_info(struct mxser_struct *, struct serial_struct __user *);
409static int mxser_set_serial_info(struct mxser_struct *, struct serial_struct __user *);
410static int mxser_get_lsr_info(struct mxser_struct *, unsigned int __user *);
411static void mxser_send_break(struct mxser_struct *, int);
412static int mxser_tiocmget(struct tty_struct *, struct file *);
413static int mxser_tiocmset(struct tty_struct *, struct file *, unsigned int, unsigned int);
414static int mxser_set_baud(struct mxser_struct *info, long newspd);
415static void mxser_wait_until_sent(struct tty_struct *tty, int timeout);
416
417static void mxser_startrx(struct tty_struct *tty);
418static void mxser_stoprx(struct tty_struct *tty);
419 306
420#ifdef CONFIG_PCI 307#ifdef CONFIG_PCI
421static int CheckIsMoxaMust(int io) 308static int __devinit CheckIsMoxaMust(unsigned long io)
422{ 309{
423 u8 oldmcr, hwid; 310 u8 oldmcr, hwid;
424 int i; 311 int i;
@@ -434,90 +321,15 @@ static int CheckIsMoxaMust(int io)
434 } 321 }
435 322
436 GET_MOXA_MUST_HARDWARE_ID(io, &hwid); 323 GET_MOXA_MUST_HARDWARE_ID(io, &hwid);
437 for (i = 0; i < UART_TYPE_NUM; i++) { 324 for (i = 1; i < UART_INFO_NUM; i++) { /* 0 = OTHER_UART */
438 if (hwid == Gmoxa_uart_id[i]) 325 if (hwid == Gpci_uart_info[i].type)
439 return (int)hwid; 326 return (int)hwid;
440 } 327 }
441 return MOXA_OTHER_UART; 328 return MOXA_OTHER_UART;
442} 329}
443#endif 330#endif
444 331
445/* above is modified by Victor Yu. 08-15-2002 */ 332static void process_txrx_fifo(struct mxser_port *info)
446
447static const struct tty_operations mxser_ops = {
448 .open = mxser_open,
449 .close = mxser_close,
450 .write = mxser_write,
451 .put_char = mxser_put_char,
452 .flush_chars = mxser_flush_chars,
453 .write_room = mxser_write_room,
454 .chars_in_buffer = mxser_chars_in_buffer,
455 .flush_buffer = mxser_flush_buffer,
456 .ioctl = mxser_ioctl,
457 .throttle = mxser_throttle,
458 .unthrottle = mxser_unthrottle,
459 .set_termios = mxser_set_termios,
460 .stop = mxser_stop,
461 .start = mxser_start,
462 .hangup = mxser_hangup,
463 .break_ctl = mxser_rs_break,
464 .wait_until_sent = mxser_wait_until_sent,
465 .tiocmget = mxser_tiocmget,
466 .tiocmset = mxser_tiocmset,
467};
468
469/*
470 * The MOXA Smartio/Industio serial driver boot-time initialization code!
471 */
472
473static int __init mxser_module_init(void)
474{
475 int ret;
476
477 if (verbose)
478 printk(KERN_DEBUG "Loading module mxser ...\n");
479 ret = mxser_init();
480 if (verbose)
481 printk(KERN_DEBUG "Done.\n");
482 return ret;
483}
484
485static void __exit mxser_module_exit(void)
486{
487 int i, err;
488
489 if (verbose)
490 printk(KERN_DEBUG "Unloading module mxser ...\n");
491
492 err = tty_unregister_driver(mxvar_sdriver);
493 if (!err)
494 put_tty_driver(mxvar_sdriver);
495 else
496 printk(KERN_ERR "Couldn't unregister MOXA Smartio/Industio family serial driver\n");
497
498 for (i = 0; i < MXSER_BOARDS; i++) {
499 struct pci_dev *pdev;
500
501 if (mxsercfg[i].board_type == -1)
502 continue;
503 else {
504 pdev = mxsercfg[i].pciInfo.pdev;
505 free_irq(mxsercfg[i].irq, &mxvar_table[i * MXSER_PORTS_PER_BOARD]);
506 if (pdev != NULL) { /* PCI */
507 release_region(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2));
508 release_region(pci_resource_start(pdev, 3), pci_resource_len(pdev, 3));
509 pci_dev_put(pdev);
510 } else {
511 release_region(mxsercfg[i].ioaddr[0], 8 * mxsercfg[i].ports);
512 release_region(mxsercfg[i].vector, 1);
513 }
514 }
515 }
516 if (verbose)
517 printk(KERN_DEBUG "Done.\n");
518}
519
520static void process_txrx_fifo(struct mxser_struct *info)
521{ 333{
522 int i; 334 int i;
523 335
@@ -526,424 +338,548 @@ static void process_txrx_fifo(struct mxser_struct *info)
526 info->rx_high_water = 1; 338 info->rx_high_water = 1;
527 info->rx_low_water = 1; 339 info->rx_low_water = 1;
528 info->xmit_fifo_size = 1; 340 info->xmit_fifo_size = 1;
529 } else { 341 } else
530 for (i = 0; i < UART_INFO_NUM; i++) { 342 for (i = 0; i < UART_INFO_NUM; i++)
531 if (info->IsMoxaMustChipFlag == Gpci_uart_info[i].type) { 343 if (info->board->chip_flag == Gpci_uart_info[i].type) {
532 info->rx_trigger = Gpci_uart_info[i].rx_trigger; 344 info->rx_trigger = Gpci_uart_info[i].rx_trigger;
533 info->rx_low_water = Gpci_uart_info[i].rx_low_water; 345 info->rx_low_water = Gpci_uart_info[i].rx_low_water;
534 info->rx_high_water = Gpci_uart_info[i].rx_high_water; 346 info->rx_high_water = Gpci_uart_info[i].rx_high_water;
535 info->xmit_fifo_size = Gpci_uart_info[i].xmit_fifo_size; 347 info->xmit_fifo_size = Gpci_uart_info[i].xmit_fifo_size;
536 break; 348 break;
537 } 349 }
538 }
539 }
540} 350}
541 351
542static int mxser_initbrd(int board, struct mxser_hwconf *hwconf) 352static unsigned char mxser_get_msr(int baseaddr, int mode, int port)
543{ 353{
544 struct mxser_struct *info; 354 unsigned char status = 0;
545 int retval;
546 int i, n;
547 355
548 n = board * MXSER_PORTS_PER_BOARD; 356 status = inb(baseaddr + UART_MSR);
549 info = &mxvar_table[n];
550 /*if (verbose) */ {
551 printk(KERN_DEBUG " ttyMI%d - ttyMI%d ",
552 n, n + hwconf->ports - 1);
553 printk(" max. baud rate = %d bps.\n",
554 hwconf->MaxCanSetBaudRate[0]);
555 }
556
557 for (i = 0; i < hwconf->ports; i++, n++, info++) {
558 info->port = n;
559 info->base = hwconf->ioaddr[i];
560 info->irq = hwconf->irq;
561 info->vector = hwconf->vector;
562 info->vectormask = hwconf->vector_mask;
563 info->opmode_ioaddr = hwconf->opmode_ioaddr[i]; /* add by Victor Yu. 01-05-2004 */
564 info->stop_rx = 0;
565 info->ldisc_stop_rx = 0;
566 357
567 info->IsMoxaMustChipFlag = hwconf->IsMoxaMustChipFlag; 358 mxser_msr[port] &= 0x0F;
568 /* Enhance mode enabled here */ 359 mxser_msr[port] |= status;
569 if (info->IsMoxaMustChipFlag != MOXA_OTHER_UART) { 360 status = mxser_msr[port];
570 ENABLE_MOXA_MUST_ENCHANCE_MODE(info->base); 361 if (mode)
571 } 362 mxser_msr[port] = 0;
572 363
573 info->flags = ASYNC_SHARE_IRQ; 364 return status;
574 info->type = hwconf->uart_type; 365}
575 info->baud_base = hwconf->baud_base[i];
576 366
577 info->MaxCanSetBaudRate = hwconf->MaxCanSetBaudRate[i]; 367static int mxser_block_til_ready(struct tty_struct *tty, struct file *filp,
368 struct mxser_port *port)
369{
370 DECLARE_WAITQUEUE(wait, current);
371 int retval;
372 int do_clocal = 0;
373 unsigned long flags;
578 374
579 process_txrx_fifo(info); 375 /*
376 * If non-blocking mode is set, or the port is not enabled,
377 * then make the check up front and then exit.
378 */
379 if ((filp->f_flags & O_NONBLOCK) ||
380 test_bit(TTY_IO_ERROR, &tty->flags)) {
381 port->flags |= ASYNC_NORMAL_ACTIVE;
382 return 0;
383 }
580 384
385 if (tty->termios->c_cflag & CLOCAL)
386 do_clocal = 1;
581 387
582 info->custom_divisor = hwconf->baud_base[i] * 16;
583 info->close_delay = 5 * HZ / 10;
584 info->closing_wait = 30 * HZ;
585 INIT_WORK(&info->tqueue, mxser_do_softint);
586 info->normal_termios = mxvar_sdriver->init_termios;
587 init_waitqueue_head(&info->open_wait);
588 init_waitqueue_head(&info->close_wait);
589 init_waitqueue_head(&info->delta_msr_wait);
590 memset(&info->mon_data, 0, sizeof(struct mxser_mon));
591 info->err_shadow = 0;
592 spin_lock_init(&info->slock);
593 }
594 /* 388 /*
595 * Allocate the IRQ if necessary 389 * Block waiting for the carrier detect and the line to become
390 * free (i.e., not in use by the callout). While we are in
391 * this loop, port->count is dropped by one, so that
392 * mxser_close() knows when to free things. We restore it upon
393 * exit, either normal or abnormal.
596 */ 394 */
395 retval = 0;
396 add_wait_queue(&port->open_wait, &wait);
597 397
598 398 spin_lock_irqsave(&port->slock, flags);
599 /* before set INT ISR, disable all int */ 399 if (!tty_hung_up_p(filp))
600 for (i = 0; i < hwconf->ports; i++) { 400 port->count--;
601 outb(inb(hwconf->ioaddr[i] + UART_IER) & 0xf0, 401 spin_unlock_irqrestore(&port->slock, flags);
602 hwconf->ioaddr[i] + UART_IER); 402 port->blocked_open++;
403 while (1) {
404 spin_lock_irqsave(&port->slock, flags);
405 outb(inb(port->ioaddr + UART_MCR) |
406 UART_MCR_DTR | UART_MCR_RTS, port->ioaddr + UART_MCR);
407 spin_unlock_irqrestore(&port->slock, flags);
408 set_current_state(TASK_INTERRUPTIBLE);
409 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)) {
410 if (port->flags & ASYNC_HUP_NOTIFY)
411 retval = -EAGAIN;
412 else
413 retval = -ERESTARTSYS;
414 break;
415 }
416 if (!(port->flags & ASYNC_CLOSING) &&
417 (do_clocal ||
418 (inb(port->ioaddr + UART_MSR) & UART_MSR_DCD)))
419 break;
420 if (signal_pending(current)) {
421 retval = -ERESTARTSYS;
422 break;
423 }
424 schedule();
603 } 425 }
604 426 set_current_state(TASK_RUNNING);
605 n = board * MXSER_PORTS_PER_BOARD; 427 remove_wait_queue(&port->open_wait, &wait);
606 info = &mxvar_table[n]; 428 if (!tty_hung_up_p(filp))
607 429 port->count++;
608 retval = request_irq(hwconf->irq, mxser_interrupt, IRQ_T(info), 430 port->blocked_open--;
609 "mxser", info); 431 if (retval)
610 if (retval) {
611 printk(KERN_ERR "Board %d: %s",
612 board, mxser_brdname[hwconf->board_type - 1]);
613 printk(" Request irq failed, IRQ (%d) may conflict with"
614 " another device.\n", info->irq);
615 return retval; 432 return retval;
616 } 433 port->flags |= ASYNC_NORMAL_ACTIVE;
617 return 0; 434 return 0;
618} 435}
619 436
620static void mxser_getcfg(int board, struct mxser_hwconf *hwconf) 437static int mxser_set_baud(struct mxser_port *info, long newspd)
621{ 438{
622 mxsercfg[board] = *hwconf; 439 int quot = 0, baud;
623} 440 unsigned char cval;
624 441
625#ifdef CONFIG_PCI 442 if (!info->tty || !info->tty->termios)
626static int mxser_get_PCI_conf(int busnum, int devnum, int board_type, struct mxser_hwconf *hwconf) 443 return -1;
627{
628 int i, j;
629 /* unsigned int val; */
630 unsigned int ioaddress;
631 struct pci_dev *pdev = hwconf->pciInfo.pdev;
632 444
633 /* io address */ 445 if (!(info->ioaddr))
634 hwconf->board_type = board_type; 446 return -1;
635 hwconf->ports = mxser_numports[board_type - 1];
636 ioaddress = pci_resource_start(pdev, 2);
637 request_region(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2),
638 "mxser(IO)");
639 447
640 for (i = 0; i < hwconf->ports; i++) 448 if (newspd > info->max_baud)
641 hwconf->ioaddr[i] = ioaddress + 8 * i; 449 return -1;
642 450
643 /* vector */ 451 if (newspd == 134) {
644 ioaddress = pci_resource_start(pdev, 3); 452 quot = 2 * info->baud_base / 269;
645 request_region(pci_resource_start(pdev, 3), pci_resource_len(pdev, 3), 453 tty_encode_baud_rate(info->tty, 134, 134);
646 "mxser(vector)"); 454 } else if (newspd) {
647 hwconf->vector = ioaddress; 455 quot = info->baud_base / newspd;
456 if (quot == 0)
457 quot = 1;
458 baud = info->baud_base/quot;
459 tty_encode_baud_rate(info->tty, baud, baud);
460 } else {
461 quot = 0;
462 }
648 463
649 /* irq */ 464 info->timeout = ((info->xmit_fifo_size * HZ * 10 * quot) / info->baud_base);
650 hwconf->irq = hwconf->pciInfo.pdev->irq; 465 info->timeout += HZ / 50; /* Add .02 seconds of slop */
651 466
652 hwconf->IsMoxaMustChipFlag = CheckIsMoxaMust(hwconf->ioaddr[0]); 467 if (quot) {
653 hwconf->uart_type = PORT_16550A; 468 info->MCR |= UART_MCR_DTR;
654 hwconf->vector_mask = 0; 469 outb(info->MCR, info->ioaddr + UART_MCR);
470 } else {
471 info->MCR &= ~UART_MCR_DTR;
472 outb(info->MCR, info->ioaddr + UART_MCR);
473 return 0;
474 }
655 475
476 cval = inb(info->ioaddr + UART_LCR);
656 477
657 for (i = 0; i < hwconf->ports; i++) { 478 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */
658 for (j = 0; j < UART_INFO_NUM; j++) {
659 if (Gpci_uart_info[j].type == hwconf->IsMoxaMustChipFlag) {
660 hwconf->MaxCanSetBaudRate[i] = Gpci_uart_info[j].max_baud;
661 479
662 /* exception....CP-102 */ 480 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */
663 if (board_type == MXSER_BOARD_CP102) 481 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */
664 hwconf->MaxCanSetBaudRate[i] = 921600; 482 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */
665 break;
666 }
667 }
668 }
669 483
670 if (hwconf->IsMoxaMustChipFlag == MOXA_MUST_MU860_HWID) { 484#ifdef BOTHER
671 for (i = 0; i < hwconf->ports; i++) { 485 if (C_BAUD(info->tty) == BOTHER) {
672 if (i < 4) 486 quot = info->baud_base % newspd;
673 hwconf->opmode_ioaddr[i] = ioaddress + 4; 487 quot *= 8;
674 else 488 if (quot % newspd > newspd / 2) {
675 hwconf->opmode_ioaddr[i] = ioaddress + 0x0c; 489 quot /= newspd;
676 } 490 quot++;
677 outb(0, ioaddress + 4); /* default set to RS232 mode */ 491 } else
678 outb(0, ioaddress + 0x0c); /* default set to RS232 mode */ 492 quot /= newspd;
679 } 493
494 SET_MOXA_MUST_ENUM_VALUE(info->ioaddr, quot);
495 } else
496#endif
497 SET_MOXA_MUST_ENUM_VALUE(info->ioaddr, 0);
680 498
681 for (i = 0; i < hwconf->ports; i++) {
682 hwconf->vector_mask |= (1 << i);
683 hwconf->baud_base[i] = 921600;
684 }
685 return 0; 499 return 0;
686} 500}
687#endif
688 501
689static int mxser_init(void) 502/*
503 * This routine is called to set the UART divisor registers to match
504 * the specified baud rate for a serial port.
505 */
506static int mxser_change_speed(struct mxser_port *info,
507 struct ktermios *old_termios)
690{ 508{
691 int i, m, retval, b, n; 509 unsigned cflag, cval, fcr;
692 struct pci_dev *pdev = NULL; 510 int ret = 0;
693 int index; 511 unsigned char status;
694 unsigned char busnum, devnum;
695 struct mxser_hwconf hwconf;
696
697 mxvar_sdriver = alloc_tty_driver(MXSER_PORTS + 1);
698 if (!mxvar_sdriver)
699 return -ENOMEM;
700 spin_lock_init(&gm_lock);
701
702 for (i = 0; i < MXSER_BOARDS; i++) {
703 mxsercfg[i].board_type = -1;
704 }
705 512
706 printk(KERN_INFO "MOXA Smartio/Industio family driver version %s\n", 513 if (!info->tty || !info->tty->termios)
707 MXSER_VERSION); 514 return ret;
515 cflag = info->tty->termios->c_cflag;
516 if (!(info->ioaddr))
517 return ret;
708 518
709 /* Initialize the tty_driver structure */ 519 if (mxser_set_baud_method[info->tty->index] == 0)
710 memset(mxvar_sdriver, 0, sizeof(struct tty_driver)); 520 mxser_set_baud(info, tty_get_baud_rate(info->tty));
711 mxvar_sdriver->owner = THIS_MODULE;
712 mxvar_sdriver->magic = TTY_DRIVER_MAGIC;
713 mxvar_sdriver->name = "ttyMI";
714 mxvar_sdriver->major = ttymajor;
715 mxvar_sdriver->minor_start = 0;
716 mxvar_sdriver->num = MXSER_PORTS + 1;
717 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
718 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
719 mxvar_sdriver->init_termios = tty_std_termios;
720 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
721 mxvar_sdriver->init_termios.c_ispeed = 9600;
722 mxvar_sdriver->init_termios.c_ospeed = 9600;
723 mxvar_sdriver->flags = TTY_DRIVER_REAL_RAW;
724 tty_set_operations(mxvar_sdriver, &mxser_ops);
725 mxvar_sdriver->ttys = mxvar_tty;
726 mxvar_sdriver->termios = mxvar_termios;
727 mxvar_sdriver->termios_locked = mxvar_termios_locked;
728 521
729 mxvar_diagflag = 0; 522 /* byte size and parity */
730 memset(mxvar_table, 0, MXSER_PORTS * sizeof(struct mxser_struct)); 523 switch (cflag & CSIZE) {
731 memset(&mxvar_log, 0, sizeof(struct mxser_log)); 524 case CS5:
525 cval = 0x00;
526 break;
527 case CS6:
528 cval = 0x01;
529 break;
530 case CS7:
531 cval = 0x02;
532 break;
533 case CS8:
534 cval = 0x03;
535 break;
536 default:
537 cval = 0x00;
538 break; /* too keep GCC shut... */
539 }
540 if (cflag & CSTOPB)
541 cval |= 0x04;
542 if (cflag & PARENB)
543 cval |= UART_LCR_PARITY;
544 if (!(cflag & PARODD))
545 cval |= UART_LCR_EPAR;
546 if (cflag & CMSPAR)
547 cval |= UART_LCR_SPAR;
732 548
733 memset(&mxser_msr, 0, sizeof(unsigned char) * (MXSER_PORTS + 1)); 549 if ((info->type == PORT_8250) || (info->type == PORT_16450)) {
734 memset(&mon_data_ext, 0, sizeof(struct mxser_mon_ext)); 550 if (info->board->chip_flag) {
735 memset(&mxser_set_baud_method, 0, sizeof(int) * (MXSER_PORTS + 1)); 551 fcr = UART_FCR_ENABLE_FIFO;
736 memset(&hwconf, 0, sizeof(struct mxser_hwconf)); 552 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
553 SET_MOXA_MUST_FIFO_VALUE(info);
554 } else
555 fcr = 0;
556 } else {
557 fcr = UART_FCR_ENABLE_FIFO;
558 if (info->board->chip_flag) {
559 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
560 SET_MOXA_MUST_FIFO_VALUE(info);
561 } else {
562 switch (info->rx_trigger) {
563 case 1:
564 fcr |= UART_FCR_TRIGGER_1;
565 break;
566 case 4:
567 fcr |= UART_FCR_TRIGGER_4;
568 break;
569 case 8:
570 fcr |= UART_FCR_TRIGGER_8;
571 break;
572 default:
573 fcr |= UART_FCR_TRIGGER_14;
574 break;
575 }
576 }
577 }
737 578
738 m = 0; 579 /* CTS flow control flag and modem status interrupts */
739 /* Start finding ISA boards here */ 580 info->IER &= ~UART_IER_MSI;
740 for (b = 0; b < MXSER_BOARDS && m < MXSER_BOARDS; b++) { 581 info->MCR &= ~UART_MCR_AFE;
741 int cap; 582 if (cflag & CRTSCTS) {
742 583 info->flags |= ASYNC_CTS_FLOW;
743 if (!(cap = mxserBoardCAP[b])) 584 info->IER |= UART_IER_MSI;
744 continue; 585 if ((info->type == PORT_16550A) || (info->board->chip_flag)) {
745 586 info->MCR |= UART_MCR_AFE;
746 retval = mxser_get_ISA_conf(cap, &hwconf); 587 } else {
747 588 status = inb(info->ioaddr + UART_MSR);
748 if (retval != 0) 589 if (info->tty->hw_stopped) {
749 printk(KERN_INFO "Found MOXA %s board (CAP=0x%x)\n", 590 if (status & UART_MSR_CTS) {
750 mxser_brdname[hwconf.board_type - 1], ioaddr[b]); 591 info->tty->hw_stopped = 0;
751 592 if (info->type != PORT_16550A &&
752 if (retval <= 0) { 593 !info->board->chip_flag) {
753 if (retval == MXSER_ERR_IRQ) 594 outb(info->IER & ~UART_IER_THRI,
754 printk(KERN_ERR "Invalid interrupt number, " 595 info->ioaddr +
755 "board not configured\n"); 596 UART_IER);
756 else if (retval == MXSER_ERR_IRQ_CONFLIT) 597 info->IER |= UART_IER_THRI;
757 printk(KERN_ERR "Invalid interrupt number, " 598 outb(info->IER, info->ioaddr +
758 "board not configured\n"); 599 UART_IER);
759 else if (retval == MXSER_ERR_VECTOR) 600 }
760 printk(KERN_ERR "Invalid interrupt vector, " 601 tty_wakeup(info->tty);
761 "board not configured\n"); 602 }
762 else if (retval == MXSER_ERR_IOADDR) 603 } else {
763 printk(KERN_ERR "Invalid I/O address, " 604 if (!(status & UART_MSR_CTS)) {
764 "board not configured\n"); 605 info->tty->hw_stopped = 1;
765 606 if ((info->type != PORT_16550A) &&
766 continue; 607 (!info->board->chip_flag)) {
608 info->IER &= ~UART_IER_THRI;
609 outb(info->IER, info->ioaddr +
610 UART_IER);
611 }
612 }
613 }
767 } 614 }
615 } else {
616 info->flags &= ~ASYNC_CTS_FLOW;
617 }
618 outb(info->MCR, info->ioaddr + UART_MCR);
619 if (cflag & CLOCAL) {
620 info->flags &= ~ASYNC_CHECK_CD;
621 } else {
622 info->flags |= ASYNC_CHECK_CD;
623 info->IER |= UART_IER_MSI;
624 }
625 outb(info->IER, info->ioaddr + UART_IER);
626
627 /*
628 * Set up parity check flag
629 */
630 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
631 if (I_INPCK(info->tty))
632 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
633 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
634 info->read_status_mask |= UART_LSR_BI;
768 635
769 hwconf.pciInfo.busNum = 0; 636 info->ignore_status_mask = 0;
770 hwconf.pciInfo.devNum = 0;
771 hwconf.pciInfo.pdev = NULL;
772 637
773 mxser_getcfg(m, &hwconf); 638 if (I_IGNBRK(info->tty)) {
639 info->ignore_status_mask |= UART_LSR_BI;
640 info->read_status_mask |= UART_LSR_BI;
774 /* 641 /*
775 * init mxsercfg first, 642 * If we're ignore parity and break indicators, ignore
776 * or mxsercfg data is not correct on ISR. 643 * overruns too. (For real raw support).
777 */ 644 */
778 /* mxser_initbrd will hook ISR. */ 645 if (I_IGNPAR(info->tty)) {
779 if (mxser_initbrd(m, &hwconf) < 0) 646 info->ignore_status_mask |=
780 continue; 647 UART_LSR_OE |
781 648 UART_LSR_PE |
782 m++; 649 UART_LSR_FE;
650 info->read_status_mask |=
651 UART_LSR_OE |
652 UART_LSR_PE |
653 UART_LSR_FE;
654 }
655 }
656 if (info->board->chip_flag) {
657 SET_MOXA_MUST_XON1_VALUE(info->ioaddr, START_CHAR(info->tty));
658 SET_MOXA_MUST_XOFF1_VALUE(info->ioaddr, STOP_CHAR(info->tty));
659 if (I_IXON(info->tty)) {
660 ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr);
661 } else {
662 DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr);
663 }
664 if (I_IXOFF(info->tty)) {
665 ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(info->ioaddr);
666 } else {
667 DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(info->ioaddr);
668 }
783 } 669 }
784 670
785 /* Start finding ISA boards from module arg */
786 for (b = 0; b < MXSER_BOARDS && m < MXSER_BOARDS; b++) {
787 int cap;
788 671
789 if (!(cap = ioaddr[b])) 672 outb(fcr, info->ioaddr + UART_FCR); /* set fcr */
790 continue; 673 outb(cval, info->ioaddr + UART_LCR);
791 674
792 retval = mxser_get_ISA_conf(cap, &hwconf); 675 return ret;
676}
793 677
794 if (retval != 0) 678static void mxser_check_modem_status(struct mxser_port *port, int status)
795 printk(KERN_INFO "Found MOXA %s board (CAP=0x%x)\n", 679{
796 mxser_brdname[hwconf.board_type - 1], ioaddr[b]); 680 /* update input line counters */
681 if (status & UART_MSR_TERI)
682 port->icount.rng++;
683 if (status & UART_MSR_DDSR)
684 port->icount.dsr++;
685 if (status & UART_MSR_DDCD)
686 port->icount.dcd++;
687 if (status & UART_MSR_DCTS)
688 port->icount.cts++;
689 port->mon_data.modem_status = status;
690 wake_up_interruptible(&port->delta_msr_wait);
797 691
798 if (retval <= 0) { 692 if ((port->flags & ASYNC_CHECK_CD) && (status & UART_MSR_DDCD)) {
799 if (retval == MXSER_ERR_IRQ) 693 if (status & UART_MSR_DCD)
800 printk(KERN_ERR "Invalid interrupt number, " 694 wake_up_interruptible(&port->open_wait);
801 "board not configured\n"); 695 }
802 else if (retval == MXSER_ERR_IRQ_CONFLIT)
803 printk(KERN_ERR "Invalid interrupt number, "
804 "board not configured\n");
805 else if (retval == MXSER_ERR_VECTOR)
806 printk(KERN_ERR "Invalid interrupt vector, "
807 "board not configured\n");
808 else if (retval == MXSER_ERR_IOADDR)
809 printk(KERN_ERR "Invalid I/O address, "
810 "board not configured\n");
811 696
812 continue; 697 if (port->flags & ASYNC_CTS_FLOW) {
698 if (port->tty->hw_stopped) {
699 if (status & UART_MSR_CTS) {
700 port->tty->hw_stopped = 0;
701
702 if ((port->type != PORT_16550A) &&
703 (!port->board->chip_flag)) {
704 outb(port->IER & ~UART_IER_THRI,
705 port->ioaddr + UART_IER);
706 port->IER |= UART_IER_THRI;
707 outb(port->IER, port->ioaddr +
708 UART_IER);
709 }
710 tty_wakeup(port->tty);
711 }
712 } else {
713 if (!(status & UART_MSR_CTS)) {
714 port->tty->hw_stopped = 1;
715 if (port->type != PORT_16550A &&
716 !port->board->chip_flag) {
717 port->IER &= ~UART_IER_THRI;
718 outb(port->IER, port->ioaddr +
719 UART_IER);
720 }
721 }
813 } 722 }
723 }
724}
814 725
815 hwconf.pciInfo.busNum = 0; 726static int mxser_startup(struct mxser_port *info)
816 hwconf.pciInfo.devNum = 0; 727{
817 hwconf.pciInfo.pdev = NULL; 728 unsigned long page;
729 unsigned long flags;
818 730
819 mxser_getcfg(m, &hwconf); 731 page = __get_free_page(GFP_KERNEL);
820 /* 732 if (!page)
821 * init mxsercfg first, 733 return -ENOMEM;
822 * or mxsercfg data is not correct on ISR. 734
823 */ 735 spin_lock_irqsave(&info->slock, flags);
824 /* mxser_initbrd will hook ISR. */
825 if (mxser_initbrd(m, &hwconf) < 0)
826 continue;
827 736
828 m++; 737 if (info->flags & ASYNC_INITIALIZED) {
738 free_page(page);
739 spin_unlock_irqrestore(&info->slock, flags);
740 return 0;
829 } 741 }
830 742
831 /* start finding PCI board here */ 743 if (!info->ioaddr || !info->type) {
832#ifdef CONFIG_PCI 744 if (info->tty)
833 n = ARRAY_SIZE(mxser_pcibrds) - 1; 745 set_bit(TTY_IO_ERROR, &info->tty->flags);
834 index = 0; 746 free_page(page);
835 b = 0; 747 spin_unlock_irqrestore(&info->slock, flags);
836 while (b < n) { 748 return 0;
837 pdev = pci_get_device(mxser_pcibrds[b].vendor,
838 mxser_pcibrds[b].device, pdev);
839 if (pdev == NULL) {
840 b++;
841 continue;
842 }
843 hwconf.pciInfo.busNum = busnum = pdev->bus->number;
844 hwconf.pciInfo.devNum = devnum = PCI_SLOT(pdev->devfn) << 3;
845 hwconf.pciInfo.pdev = pdev;
846 printk(KERN_INFO "Found MOXA %s board(BusNo=%d,DevNo=%d)\n",
847 mxser_brdname[(int) (mxser_pcibrds[b].driver_data) - 1],
848 busnum, devnum >> 3);
849 index++;
850 if (m >= MXSER_BOARDS)
851 printk(KERN_ERR
852 "Too many Smartio/Industio family boards find "
853 "(maximum %d), board not configured\n",
854 MXSER_BOARDS);
855 else {
856 if (pci_enable_device(pdev)) {
857 printk(KERN_ERR "Moxa SmartI/O PCI enable "
858 "fail !\n");
859 continue;
860 }
861 retval = mxser_get_PCI_conf(busnum, devnum,
862 (int)mxser_pcibrds[b].driver_data,
863 &hwconf);
864 if (retval < 0) {
865 if (retval == MXSER_ERR_IRQ)
866 printk(KERN_ERR
867 "Invalid interrupt number, "
868 "board not configured\n");
869 else if (retval == MXSER_ERR_IRQ_CONFLIT)
870 printk(KERN_ERR
871 "Invalid interrupt number, "
872 "board not configured\n");
873 else if (retval == MXSER_ERR_VECTOR)
874 printk(KERN_ERR
875 "Invalid interrupt vector, "
876 "board not configured\n");
877 else if (retval == MXSER_ERR_IOADDR)
878 printk(KERN_ERR
879 "Invalid I/O address, "
880 "board not configured\n");
881 continue;
882 }
883 mxser_getcfg(m, &hwconf);
884 /* init mxsercfg first,
885 * or mxsercfg data is not correct on ISR.
886 */
887 /* mxser_initbrd will hook ISR. */
888 if (mxser_initbrd(m, &hwconf) < 0)
889 continue;
890 m++;
891 /* Keep an extra reference if we succeeded. It will
892 be returned at unload time */
893 pci_dev_get(pdev);
894 }
895 } 749 }
896#endif 750 if (info->xmit_buf)
751 free_page(page);
752 else
753 info->xmit_buf = (unsigned char *) page;
897 754
898 retval = tty_register_driver(mxvar_sdriver); 755 /*
899 if (retval) { 756 * Clear the FIFO buffers and disable them
900 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family" 757 * (they will be reenabled in mxser_change_speed())
901 " driver !\n"); 758 */
902 put_tty_driver(mxvar_sdriver); 759 if (info->board->chip_flag)
760 outb((UART_FCR_CLEAR_RCVR |
761 UART_FCR_CLEAR_XMIT |
762 MOXA_MUST_FCR_GDA_MODE_ENABLE), info->ioaddr + UART_FCR);
763 else
764 outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
765 info->ioaddr + UART_FCR);
903 766
904 for (i = 0; i < MXSER_BOARDS; i++) { 767 /*
905 if (mxsercfg[i].board_type == -1) 768 * At this point there's no way the LSR could still be 0xFF;
906 continue; 769 * if it is, then bail out, because there's likely no UART
907 else { 770 * here.
908 free_irq(mxsercfg[i].irq, &mxvar_table[i * MXSER_PORTS_PER_BOARD]); 771 */
909 /* todo: release io, vector */ 772 if (inb(info->ioaddr + UART_LSR) == 0xff) {
910 } 773 spin_unlock_irqrestore(&info->slock, flags);
911 } 774 if (capable(CAP_SYS_ADMIN)) {
912 return retval; 775 if (info->tty)
776 set_bit(TTY_IO_ERROR, &info->tty->flags);
777 return 0;
778 } else
779 return -ENODEV;
913 } 780 }
914 781
782 /*
783 * Clear the interrupt registers.
784 */
785 (void) inb(info->ioaddr + UART_LSR);
786 (void) inb(info->ioaddr + UART_RX);
787 (void) inb(info->ioaddr + UART_IIR);
788 (void) inb(info->ioaddr + UART_MSR);
789
790 /*
791 * Now, initialize the UART
792 */
793 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */
794 info->MCR = UART_MCR_DTR | UART_MCR_RTS;
795 outb(info->MCR, info->ioaddr + UART_MCR);
796
797 /*
798 * Finally, enable interrupts
799 */
800 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
801
802 if (info->board->chip_flag)
803 info->IER |= MOXA_MUST_IER_EGDAI;
804 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */
805
806 /*
807 * And clear the interrupt registers again for luck.
808 */
809 (void) inb(info->ioaddr + UART_LSR);
810 (void) inb(info->ioaddr + UART_RX);
811 (void) inb(info->ioaddr + UART_IIR);
812 (void) inb(info->ioaddr + UART_MSR);
813
814 if (info->tty)
815 clear_bit(TTY_IO_ERROR, &info->tty->flags);
816 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
817
818 /*
819 * and set the speed of the serial port
820 */
821 mxser_change_speed(info, NULL);
822 info->flags |= ASYNC_INITIALIZED;
823 spin_unlock_irqrestore(&info->slock, flags);
824
915 return 0; 825 return 0;
916} 826}
917 827
918static void mxser_do_softint(struct work_struct *work) 828/*
829 * This routine will shutdown a serial port; interrupts maybe disabled, and
830 * DTR is dropped if the hangup on close termio flag is on.
831 */
832static void mxser_shutdown(struct mxser_port *info)
919{ 833{
920 struct mxser_struct *info = 834 unsigned long flags;
921 container_of(work, struct mxser_struct, tqueue); 835
922 struct tty_struct *tty; 836 if (!(info->flags & ASYNC_INITIALIZED))
837 return;
923 838
924 tty = info->tty; 839 spin_lock_irqsave(&info->slock, flags);
840
841 /*
842 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
843 * here so the queue might never be waken up
844 */
845 wake_up_interruptible(&info->delta_msr_wait);
925 846
926 if (tty) { 847 /*
927 if (test_and_clear_bit(MXSER_EVENT_TXLOW, &info->event)) 848 * Free the IRQ, if necessary
928 tty_wakeup(tty); 849 */
929 if (test_and_clear_bit(MXSER_EVENT_HANGUP, &info->event)) 850 if (info->xmit_buf) {
930 tty_hangup(tty); 851 free_page((unsigned long) info->xmit_buf);
852 info->xmit_buf = NULL;
931 } 853 }
932}
933 854
934static unsigned char mxser_get_msr(int baseaddr, int mode, int port, struct mxser_struct *info) 855 info->IER = 0;
935{ 856 outb(0x00, info->ioaddr + UART_IER);
936 unsigned char status = 0;
937 857
938 status = inb(baseaddr + UART_MSR); 858 if (!info->tty || (info->tty->termios->c_cflag & HUPCL))
859 info->MCR &= ~(UART_MCR_DTR | UART_MCR_RTS);
860 outb(info->MCR, info->ioaddr + UART_MCR);
939 861
940 mxser_msr[port] &= 0x0F; 862 /* clear Rx/Tx FIFO's */
941 mxser_msr[port] |= status; 863 if (info->board->chip_flag)
942 status = mxser_msr[port]; 864 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT |
943 if (mode) 865 MOXA_MUST_FCR_GDA_MODE_ENABLE,
944 mxser_msr[port] = 0; 866 info->ioaddr + UART_FCR);
867 else
868 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
869 info->ioaddr + UART_FCR);
945 870
946 return status; 871 /* read data port to reset things */
872 (void) inb(info->ioaddr + UART_RX);
873
874 if (info->tty)
875 set_bit(TTY_IO_ERROR, &info->tty->flags);
876
877 info->flags &= ~ASYNC_INITIALIZED;
878
879 if (info->board->chip_flag)
880 SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(info->ioaddr);
881
882 spin_unlock_irqrestore(&info->slock, flags);
947} 883}
948 884
949/* 885/*
@@ -954,19 +890,17 @@ static unsigned char mxser_get_msr(int baseaddr, int mode, int port, struct mxse
954 */ 890 */
955static int mxser_open(struct tty_struct *tty, struct file *filp) 891static int mxser_open(struct tty_struct *tty, struct file *filp)
956{ 892{
957 struct mxser_struct *info; 893 struct mxser_port *info;
894 unsigned long flags;
958 int retval, line; 895 int retval, line;
959 896
960 /* initialize driver_data in case something fails */
961 tty->driver_data = NULL;
962
963 line = tty->index; 897 line = tty->index;
964 if (line == MXSER_PORTS) 898 if (line == MXSER_PORTS)
965 return 0; 899 return 0;
966 if (line < 0 || line > MXSER_PORTS) 900 if (line < 0 || line > MXSER_PORTS)
967 return -ENODEV; 901 return -ENODEV;
968 info = mxvar_table + line; 902 info = &mxser_boards[line / MXSER_PORTS_PER_BOARD].ports[line % MXSER_PORTS_PER_BOARD];
969 if (!info->base) 903 if (!info->ioaddr)
970 return -ENODEV; 904 return -ENODEV;
971 905
972 tty->driver_data = info; 906 tty->driver_data = info;
@@ -974,6 +908,9 @@ static int mxser_open(struct tty_struct *tty, struct file *filp)
974 /* 908 /*
975 * Start up serial port 909 * Start up serial port
976 */ 910 */
911 spin_lock_irqsave(&info->slock, flags);
912 info->count++;
913 spin_unlock_irqrestore(&info->slock, flags);
977 retval = mxser_startup(info); 914 retval = mxser_startup(info);
978 if (retval) 915 if (retval)
979 return retval; 916 return retval;
@@ -982,21 +919,6 @@ static int mxser_open(struct tty_struct *tty, struct file *filp)
982 if (retval) 919 if (retval)
983 return retval; 920 return retval;
984 921
985 info->count++;
986
987 if ((info->count == 1) && (info->flags & ASYNC_SPLIT_TERMIOS)) {
988 if (tty->driver->subtype == SERIAL_TYPE_NORMAL)
989 *tty->termios = info->normal_termios;
990 else
991 *tty->termios = info->callout_termios;
992 mxser_change_speed(info, NULL);
993 }
994
995 /*
996 status = mxser_get_msr(info->base, 0, info->port);
997 mxser_check_modem_status(info, status);
998 */
999
1000 /* unmark here for very high baud rate (ex. 921600 bps) used */ 922 /* unmark here for very high baud rate (ex. 921600 bps) used */
1001 tty->low_latency = 1; 923 tty->low_latency = 1;
1002 return 0; 924 return 0;
@@ -1010,11 +932,10 @@ static int mxser_open(struct tty_struct *tty, struct file *filp)
1010 */ 932 */
1011static void mxser_close(struct tty_struct *tty, struct file *filp) 933static void mxser_close(struct tty_struct *tty, struct file *filp)
1012{ 934{
1013 struct mxser_struct *info = tty->driver_data; 935 struct mxser_port *info = tty->driver_data;
1014 936
1015 unsigned long timeout; 937 unsigned long timeout;
1016 unsigned long flags; 938 unsigned long flags;
1017 struct tty_ldisc *ld;
1018 939
1019 if (tty->index == MXSER_PORTS) 940 if (tty->index == MXSER_PORTS)
1020 return; 941 return;
@@ -1041,7 +962,7 @@ static void mxser_close(struct tty_struct *tty, struct file *filp)
1041 } 962 }
1042 if (--info->count < 0) { 963 if (--info->count < 0) {
1043 printk(KERN_ERR "mxser_close: bad serial port count for " 964 printk(KERN_ERR "mxser_close: bad serial port count for "
1044 "ttys%d: %d\n", info->port, info->count); 965 "ttys%d: %d\n", tty->index, info->count);
1045 info->count = 0; 966 info->count = 0;
1046 } 967 }
1047 if (info->count) { 968 if (info->count) {
@@ -1070,20 +991,18 @@ static void mxser_close(struct tty_struct *tty, struct file *filp)
1070 * line status register. 991 * line status register.
1071 */ 992 */
1072 info->IER &= ~UART_IER_RLSI; 993 info->IER &= ~UART_IER_RLSI;
1073 if (info->IsMoxaMustChipFlag) 994 if (info->board->chip_flag)
1074 info->IER &= ~MOXA_MUST_RECV_ISR; 995 info->IER &= ~MOXA_MUST_RECV_ISR;
1075/* by William 996
1076 info->read_status_mask &= ~UART_LSR_DR;
1077*/
1078 if (info->flags & ASYNC_INITIALIZED) { 997 if (info->flags & ASYNC_INITIALIZED) {
1079 outb(info->IER, info->base + UART_IER); 998 outb(info->IER, info->ioaddr + UART_IER);
1080 /* 999 /*
1081 * Before we drop DTR, make sure the UART transmitter 1000 * Before we drop DTR, make sure the UART transmitter
1082 * has completely drained; this is especially 1001 * has completely drained; this is especially
1083 * important if there is a transmit FIFO! 1002 * important if there is a transmit FIFO!
1084 */ 1003 */
1085 timeout = jiffies + HZ; 1004 timeout = jiffies + HZ;
1086 while (!(inb(info->base + UART_LSR) & UART_LSR_TEMT)) { 1005 while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) {
1087 schedule_timeout_interruptible(5); 1006 schedule_timeout_interruptible(5);
1088 if (time_after(jiffies, timeout)) 1007 if (time_after(jiffies, timeout))
1089 break; 1008 break;
@@ -1093,14 +1012,9 @@ static void mxser_close(struct tty_struct *tty, struct file *filp)
1093 1012
1094 if (tty->driver->flush_buffer) 1013 if (tty->driver->flush_buffer)
1095 tty->driver->flush_buffer(tty); 1014 tty->driver->flush_buffer(tty);
1096 1015
1097 ld = tty_ldisc_ref(tty); 1016 tty_ldisc_flush(tty);
1098 if (ld) { 1017
1099 if (ld->flush_buffer)
1100 ld->flush_buffer(tty);
1101 tty_ldisc_deref(ld);
1102 }
1103
1104 tty->closing = 0; 1018 tty->closing = 0;
1105 info->event = 0; 1019 info->event = 0;
1106 info->tty = NULL; 1020 info->tty = NULL;
@@ -1111,14 +1025,12 @@ static void mxser_close(struct tty_struct *tty, struct file *filp)
1111 } 1025 }
1112 1026
1113 info->flags &= ~(ASYNC_NORMAL_ACTIVE | ASYNC_CLOSING); 1027 info->flags &= ~(ASYNC_NORMAL_ACTIVE | ASYNC_CLOSING);
1114 wake_up_interruptible(&info->close_wait);
1115
1116} 1028}
1117 1029
1118static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count) 1030static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count)
1119{ 1031{
1120 int c, total = 0; 1032 int c, total = 0;
1121 struct mxser_struct *info = tty->driver_data; 1033 struct mxser_port *info = tty->driver_data;
1122 unsigned long flags; 1034 unsigned long flags;
1123 1035
1124 if (!info->xmit_buf) 1036 if (!info->xmit_buf)
@@ -1142,13 +1054,15 @@ static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int cou
1142 total += c; 1054 total += c;
1143 } 1055 }
1144 1056
1145 if (info->xmit_cnt && !tty->stopped && !(info->IER & UART_IER_THRI)) { 1057 if (info->xmit_cnt && !tty->stopped) {
1146 if (!tty->hw_stopped || 1058 if (!tty->hw_stopped ||
1147 (info->type == PORT_16550A) || 1059 (info->type == PORT_16550A) ||
1148 (info->IsMoxaMustChipFlag)) { 1060 (info->board->chip_flag)) {
1149 spin_lock_irqsave(&info->slock, flags); 1061 spin_lock_irqsave(&info->slock, flags);
1062 outb(info->IER & ~UART_IER_THRI, info->ioaddr +
1063 UART_IER);
1150 info->IER |= UART_IER_THRI; 1064 info->IER |= UART_IER_THRI;
1151 outb(info->IER, info->base + UART_IER); 1065 outb(info->IER, info->ioaddr + UART_IER);
1152 spin_unlock_irqrestore(&info->slock, flags); 1066 spin_unlock_irqrestore(&info->slock, flags);
1153 } 1067 }
1154 } 1068 }
@@ -1157,7 +1071,7 @@ static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int cou
1157 1071
1158static void mxser_put_char(struct tty_struct *tty, unsigned char ch) 1072static void mxser_put_char(struct tty_struct *tty, unsigned char ch)
1159{ 1073{
1160 struct mxser_struct *info = tty->driver_data; 1074 struct mxser_port *info = tty->driver_data;
1161 unsigned long flags; 1075 unsigned long flags;
1162 1076
1163 if (!info->xmit_buf) 1077 if (!info->xmit_buf)
@@ -1171,13 +1085,14 @@ static void mxser_put_char(struct tty_struct *tty, unsigned char ch)
1171 info->xmit_head &= SERIAL_XMIT_SIZE - 1; 1085 info->xmit_head &= SERIAL_XMIT_SIZE - 1;
1172 info->xmit_cnt++; 1086 info->xmit_cnt++;
1173 spin_unlock_irqrestore(&info->slock, flags); 1087 spin_unlock_irqrestore(&info->slock, flags);
1174 if (!tty->stopped && !(info->IER & UART_IER_THRI)) { 1088 if (!tty->stopped) {
1175 if (!tty->hw_stopped || 1089 if (!tty->hw_stopped ||
1176 (info->type == PORT_16550A) || 1090 (info->type == PORT_16550A) ||
1177 info->IsMoxaMustChipFlag) { 1091 info->board->chip_flag) {
1178 spin_lock_irqsave(&info->slock, flags); 1092 spin_lock_irqsave(&info->slock, flags);
1093 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1179 info->IER |= UART_IER_THRI; 1094 info->IER |= UART_IER_THRI;
1180 outb(info->IER, info->base + UART_IER); 1095 outb(info->IER, info->ioaddr + UART_IER);
1181 spin_unlock_irqrestore(&info->slock, flags); 1096 spin_unlock_irqrestore(&info->slock, flags);
1182 } 1097 }
1183 } 1098 }
@@ -1186,7 +1101,7 @@ static void mxser_put_char(struct tty_struct *tty, unsigned char ch)
1186 1101
1187static void mxser_flush_chars(struct tty_struct *tty) 1102static void mxser_flush_chars(struct tty_struct *tty)
1188{ 1103{
1189 struct mxser_struct *info = tty->driver_data; 1104 struct mxser_port *info = tty->driver_data;
1190 unsigned long flags; 1105 unsigned long flags;
1191 1106
1192 if (info->xmit_cnt <= 0 || 1107 if (info->xmit_cnt <= 0 ||
@@ -1194,21 +1109,22 @@ static void mxser_flush_chars(struct tty_struct *tty)
1194 !info->xmit_buf || 1109 !info->xmit_buf ||
1195 (tty->hw_stopped && 1110 (tty->hw_stopped &&
1196 (info->type != PORT_16550A) && 1111 (info->type != PORT_16550A) &&
1197 (!info->IsMoxaMustChipFlag) 1112 (!info->board->chip_flag)
1198 )) 1113 ))
1199 return; 1114 return;
1200 1115
1201 spin_lock_irqsave(&info->slock, flags); 1116 spin_lock_irqsave(&info->slock, flags);
1202 1117
1118 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1203 info->IER |= UART_IER_THRI; 1119 info->IER |= UART_IER_THRI;
1204 outb(info->IER, info->base + UART_IER); 1120 outb(info->IER, info->ioaddr + UART_IER);
1205 1121
1206 spin_unlock_irqrestore(&info->slock, flags); 1122 spin_unlock_irqrestore(&info->slock, flags);
1207} 1123}
1208 1124
1209static int mxser_write_room(struct tty_struct *tty) 1125static int mxser_write_room(struct tty_struct *tty)
1210{ 1126{
1211 struct mxser_struct *info = tty->driver_data; 1127 struct mxser_port *info = tty->driver_data;
1212 int ret; 1128 int ret;
1213 1129
1214 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1; 1130 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
@@ -1219,13 +1135,13 @@ static int mxser_write_room(struct tty_struct *tty)
1219 1135
1220static int mxser_chars_in_buffer(struct tty_struct *tty) 1136static int mxser_chars_in_buffer(struct tty_struct *tty)
1221{ 1137{
1222 struct mxser_struct *info = tty->driver_data; 1138 struct mxser_port *info = tty->driver_data;
1223 return info->xmit_cnt; 1139 return info->xmit_cnt;
1224} 1140}
1225 1141
1226static void mxser_flush_buffer(struct tty_struct *tty) 1142static void mxser_flush_buffer(struct tty_struct *tty)
1227{ 1143{
1228 struct mxser_struct *info = tty->driver_data; 1144 struct mxser_port *info = tty->driver_data;
1229 char fcr; 1145 char fcr;
1230 unsigned long flags; 1146 unsigned long flags;
1231 1147
@@ -1233,39 +1149,491 @@ static void mxser_flush_buffer(struct tty_struct *tty)
1233 spin_lock_irqsave(&info->slock, flags); 1149 spin_lock_irqsave(&info->slock, flags);
1234 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; 1150 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1235 1151
1236 /* below added by shinhay */ 1152 fcr = inb(info->ioaddr + UART_FCR);
1237 fcr = inb(info->base + UART_FCR);
1238 outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT), 1153 outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
1239 info->base + UART_FCR); 1154 info->ioaddr + UART_FCR);
1240 outb(fcr, info->base + UART_FCR); 1155 outb(fcr, info->ioaddr + UART_FCR);
1241 1156
1242 spin_unlock_irqrestore(&info->slock, flags); 1157 spin_unlock_irqrestore(&info->slock, flags);
1243 /* above added by shinhay */
1244 1158
1245 tty_wakeup(tty); 1159 tty_wakeup(tty);
1246} 1160}
1247 1161
1248static int mxser_ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg) 1162/*
1163 * ------------------------------------------------------------
1164 * friends of mxser_ioctl()
1165 * ------------------------------------------------------------
1166 */
1167static int mxser_get_serial_info(struct mxser_port *info,
1168 struct serial_struct __user *retinfo)
1169{
1170 struct serial_struct tmp = {
1171 .type = info->type,
1172 .line = info->tty->index,
1173 .port = info->ioaddr,
1174 .irq = info->board->irq,
1175 .flags = info->flags,
1176 .baud_base = info->baud_base,
1177 .close_delay = info->close_delay,
1178 .closing_wait = info->closing_wait,
1179 .custom_divisor = info->custom_divisor,
1180 .hub6 = 0
1181 };
1182 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
1183 return -EFAULT;
1184 return 0;
1185}
1186
1187static int mxser_set_serial_info(struct mxser_port *info,
1188 struct serial_struct __user *new_info)
1249{ 1189{
1250 struct mxser_struct *info = tty->driver_data; 1190 struct serial_struct new_serial;
1251 int retval; 1191 unsigned long sl_flags;
1252 struct async_icount cprev, cnow; /* kernel counter temps */ 1192 unsigned int flags;
1193 int retval = 0;
1194
1195 if (!new_info || !info->ioaddr)
1196 return -EFAULT;
1197 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
1198 return -EFAULT;
1199
1200 if ((new_serial.irq != info->board->irq) ||
1201 (new_serial.port != info->ioaddr) ||
1202 (new_serial.custom_divisor != info->custom_divisor) ||
1203 (new_serial.baud_base != info->baud_base))
1204 return -EPERM;
1205
1206 flags = info->flags & ASYNC_SPD_MASK;
1207
1208 if (!capable(CAP_SYS_ADMIN)) {
1209 if ((new_serial.baud_base != info->baud_base) ||
1210 (new_serial.close_delay != info->close_delay) ||
1211 ((new_serial.flags & ~ASYNC_USR_MASK) != (info->flags & ~ASYNC_USR_MASK)))
1212 return -EPERM;
1213 info->flags = ((info->flags & ~ASYNC_USR_MASK) |
1214 (new_serial.flags & ASYNC_USR_MASK));
1215 } else {
1216 /*
1217 * OK, past this point, all the error checking has been done.
1218 * At this point, we start making changes.....
1219 */
1220 info->flags = ((info->flags & ~ASYNC_FLAGS) |
1221 (new_serial.flags & ASYNC_FLAGS));
1222 info->close_delay = new_serial.close_delay * HZ / 100;
1223 info->closing_wait = new_serial.closing_wait * HZ / 100;
1224 info->tty->low_latency =
1225 (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1226 info->tty->low_latency = 0;
1227 }
1228
1229 info->type = new_serial.type;
1230
1231 process_txrx_fifo(info);
1232
1233 if (info->flags & ASYNC_INITIALIZED) {
1234 if (flags != (info->flags & ASYNC_SPD_MASK)) {
1235 spin_lock_irqsave(&info->slock, sl_flags);
1236 mxser_change_speed(info, NULL);
1237 spin_unlock_irqrestore(&info->slock, sl_flags);
1238 }
1239 } else
1240 retval = mxser_startup(info);
1241
1242 return retval;
1243}
1244
1245/*
1246 * mxser_get_lsr_info - get line status register info
1247 *
1248 * Purpose: Let user call ioctl() to get info when the UART physically
1249 * is emptied. On bus types like RS485, the transmitter must
1250 * release the bus after transmitting. This must be done when
1251 * the transmit shift register is empty, not be done when the
1252 * transmit holding register is empty. This functionality
1253 * allows an RS485 driver to be written in user space.
1254 */
1255static int mxser_get_lsr_info(struct mxser_port *info,
1256 unsigned int __user *value)
1257{
1258 unsigned char status;
1259 unsigned int result;
1260 unsigned long flags;
1261
1262 spin_lock_irqsave(&info->slock, flags);
1263 status = inb(info->ioaddr + UART_LSR);
1264 spin_unlock_irqrestore(&info->slock, flags);
1265 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
1266 return put_user(result, value);
1267}
1268
1269/*
1270 * This routine sends a break character out the serial port.
1271 */
1272static void mxser_send_break(struct mxser_port *info, int duration)
1273{
1274 unsigned long flags;
1275
1276 if (!info->ioaddr)
1277 return;
1278 set_current_state(TASK_INTERRUPTIBLE);
1279 spin_lock_irqsave(&info->slock, flags);
1280 outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC,
1281 info->ioaddr + UART_LCR);
1282 spin_unlock_irqrestore(&info->slock, flags);
1283 schedule_timeout(duration);
1284 spin_lock_irqsave(&info->slock, flags);
1285 outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC,
1286 info->ioaddr + UART_LCR);
1287 spin_unlock_irqrestore(&info->slock, flags);
1288}
1289
1290static int mxser_tiocmget(struct tty_struct *tty, struct file *file)
1291{
1292 struct mxser_port *info = tty->driver_data;
1293 unsigned char control, status;
1294 unsigned long flags;
1295
1296
1297 if (tty->index == MXSER_PORTS)
1298 return -ENOIOCTLCMD;
1299 if (test_bit(TTY_IO_ERROR, &tty->flags))
1300 return -EIO;
1301
1302 control = info->MCR;
1303
1304 spin_lock_irqsave(&info->slock, flags);
1305 status = inb(info->ioaddr + UART_MSR);
1306 if (status & UART_MSR_ANY_DELTA)
1307 mxser_check_modem_status(info, status);
1308 spin_unlock_irqrestore(&info->slock, flags);
1309 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
1310 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
1311 ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) |
1312 ((status & UART_MSR_RI) ? TIOCM_RNG : 0) |
1313 ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) |
1314 ((status & UART_MSR_CTS) ? TIOCM_CTS : 0);
1315}
1316
1317static int mxser_tiocmset(struct tty_struct *tty, struct file *file,
1318 unsigned int set, unsigned int clear)
1319{
1320 struct mxser_port *info = tty->driver_data;
1321 unsigned long flags;
1322
1323
1324 if (tty->index == MXSER_PORTS)
1325 return -ENOIOCTLCMD;
1326 if (test_bit(TTY_IO_ERROR, &tty->flags))
1327 return -EIO;
1328
1329 spin_lock_irqsave(&info->slock, flags);
1330
1331 if (set & TIOCM_RTS)
1332 info->MCR |= UART_MCR_RTS;
1333 if (set & TIOCM_DTR)
1334 info->MCR |= UART_MCR_DTR;
1335
1336 if (clear & TIOCM_RTS)
1337 info->MCR &= ~UART_MCR_RTS;
1338 if (clear & TIOCM_DTR)
1339 info->MCR &= ~UART_MCR_DTR;
1340
1341 outb(info->MCR, info->ioaddr + UART_MCR);
1342 spin_unlock_irqrestore(&info->slock, flags);
1343 return 0;
1344}
1345
1346static int __init mxser_program_mode(int port)
1347{
1348 int id, i, j, n;
1349
1350 outb(0, port);
1351 outb(0, port);
1352 outb(0, port);
1353 (void)inb(port);
1354 (void)inb(port);
1355 outb(0, port);
1356 (void)inb(port);
1357
1358 id = inb(port + 1) & 0x1F;
1359 if ((id != C168_ASIC_ID) &&
1360 (id != C104_ASIC_ID) &&
1361 (id != C102_ASIC_ID) &&
1362 (id != CI132_ASIC_ID) &&
1363 (id != CI134_ASIC_ID) &&
1364 (id != CI104J_ASIC_ID))
1365 return -1;
1366 for (i = 0, j = 0; i < 4; i++) {
1367 n = inb(port + 2);
1368 if (n == 'M') {
1369 j = 1;
1370 } else if ((j == 1) && (n == 1)) {
1371 j = 2;
1372 break;
1373 } else
1374 j = 0;
1375 }
1376 if (j != 2)
1377 id = -2;
1378 return id;
1379}
1380
1381static void __init mxser_normal_mode(int port)
1382{
1383 int i, n;
1384
1385 outb(0xA5, port + 1);
1386 outb(0x80, port + 3);
1387 outb(12, port + 0); /* 9600 bps */
1388 outb(0, port + 1);
1389 outb(0x03, port + 3); /* 8 data bits */
1390 outb(0x13, port + 4); /* loop back mode */
1391 for (i = 0; i < 16; i++) {
1392 n = inb(port + 5);
1393 if ((n & 0x61) == 0x60)
1394 break;
1395 if ((n & 1) == 1)
1396 (void)inb(port);
1397 }
1398 outb(0x00, port + 4);
1399}
1400
1401#define CHIP_SK 0x01 /* Serial Data Clock in Eprom */
1402#define CHIP_DO 0x02 /* Serial Data Output in Eprom */
1403#define CHIP_CS 0x04 /* Serial Chip Select in Eprom */
1404#define CHIP_DI 0x08 /* Serial Data Input in Eprom */
1405#define EN_CCMD 0x000 /* Chip's command register */
1406#define EN0_RSARLO 0x008 /* Remote start address reg 0 */
1407#define EN0_RSARHI 0x009 /* Remote start address reg 1 */
1408#define EN0_RCNTLO 0x00A /* Remote byte count reg WR */
1409#define EN0_RCNTHI 0x00B /* Remote byte count reg WR */
1410#define EN0_DCFG 0x00E /* Data configuration reg WR */
1411#define EN0_PORT 0x010 /* Rcv missed frame error counter RD */
1412#define ENC_PAGE0 0x000 /* Select page 0 of chip registers */
1413#define ENC_PAGE3 0x0C0 /* Select page 3 of chip registers */
1414static int __init mxser_read_register(int port, unsigned short *regs)
1415{
1416 int i, k, value, id;
1417 unsigned int j;
1418
1419 id = mxser_program_mode(port);
1420 if (id < 0)
1421 return id;
1422 for (i = 0; i < 14; i++) {
1423 k = (i & 0x3F) | 0x180;
1424 for (j = 0x100; j > 0; j >>= 1) {
1425 outb(CHIP_CS, port);
1426 if (k & j) {
1427 outb(CHIP_CS | CHIP_DO, port);
1428 outb(CHIP_CS | CHIP_DO | CHIP_SK, port); /* A? bit of read */
1429 } else {
1430 outb(CHIP_CS, port);
1431 outb(CHIP_CS | CHIP_SK, port); /* A? bit of read */
1432 }
1433 }
1434 (void)inb(port);
1435 value = 0;
1436 for (k = 0, j = 0x8000; k < 16; k++, j >>= 1) {
1437 outb(CHIP_CS, port);
1438 outb(CHIP_CS | CHIP_SK, port);
1439 if (inb(port) & CHIP_DI)
1440 value |= j;
1441 }
1442 regs[i] = value;
1443 outb(0, port);
1444 }
1445 mxser_normal_mode(port);
1446 return id;
1447}
1448
1449static int mxser_ioctl_special(unsigned int cmd, void __user *argp)
1450{
1451 struct mxser_port *port;
1452 int result, status;
1453 unsigned int i, j;
1454
1455 switch (cmd) {
1456 case MOXA_GET_MAJOR:
1457 return put_user(ttymajor, (int __user *)argp);
1458
1459 case MOXA_CHKPORTENABLE:
1460 result = 0;
1461
1462 for (i = 0; i < MXSER_BOARDS; i++)
1463 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++)
1464 if (mxser_boards[i].ports[j].ioaddr)
1465 result |= (1 << i);
1466
1467 return put_user(result, (unsigned long __user *)argp);
1468 case MOXA_GETDATACOUNT:
1469 if (copy_to_user(argp, &mxvar_log, sizeof(mxvar_log)))
1470 return -EFAULT;
1471 return 0;
1472 case MOXA_GETMSTATUS:
1473 for (i = 0; i < MXSER_BOARDS; i++)
1474 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) {
1475 port = &mxser_boards[i].ports[j];
1476
1477 GMStatus[i].ri = 0;
1478 if (!port->ioaddr) {
1479 GMStatus[i].dcd = 0;
1480 GMStatus[i].dsr = 0;
1481 GMStatus[i].cts = 0;
1482 continue;
1483 }
1484
1485 if (!port->tty || !port->tty->termios)
1486 GMStatus[i].cflag =
1487 port->normal_termios.c_cflag;
1488 else
1489 GMStatus[i].cflag =
1490 port->tty->termios->c_cflag;
1491
1492 status = inb(port->ioaddr + UART_MSR);
1493 if (status & 0x80 /*UART_MSR_DCD */ )
1494 GMStatus[i].dcd = 1;
1495 else
1496 GMStatus[i].dcd = 0;
1497
1498 if (status & 0x20 /*UART_MSR_DSR */ )
1499 GMStatus[i].dsr = 1;
1500 else
1501 GMStatus[i].dsr = 0;
1502
1503
1504 if (status & 0x10 /*UART_MSR_CTS */ )
1505 GMStatus[i].cts = 1;
1506 else
1507 GMStatus[i].cts = 0;
1508 }
1509 if (copy_to_user(argp, GMStatus,
1510 sizeof(struct mxser_mstatus) * MXSER_PORTS))
1511 return -EFAULT;
1512 return 0;
1513 case MOXA_ASPP_MON_EXT: {
1514 int p, shiftbit;
1515 unsigned long opmode;
1516 unsigned cflag, iflag;
1517
1518 for (i = 0; i < MXSER_BOARDS; i++)
1519 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) {
1520 port = &mxser_boards[i].ports[j];
1521 if (!port->ioaddr)
1522 continue;
1523
1524 status = mxser_get_msr(port->ioaddr, 0, i);
1525
1526 if (status & UART_MSR_TERI)
1527 port->icount.rng++;
1528 if (status & UART_MSR_DDSR)
1529 port->icount.dsr++;
1530 if (status & UART_MSR_DDCD)
1531 port->icount.dcd++;
1532 if (status & UART_MSR_DCTS)
1533 port->icount.cts++;
1534
1535 port->mon_data.modem_status = status;
1536 mon_data_ext.rx_cnt[i] = port->mon_data.rxcnt;
1537 mon_data_ext.tx_cnt[i] = port->mon_data.txcnt;
1538 mon_data_ext.up_rxcnt[i] =
1539 port->mon_data.up_rxcnt;
1540 mon_data_ext.up_txcnt[i] =
1541 port->mon_data.up_txcnt;
1542 mon_data_ext.modem_status[i] =
1543 port->mon_data.modem_status;
1544 mon_data_ext.baudrate[i] =
1545 tty_get_baud_rate(port->tty);
1546
1547 if (!port->tty || !port->tty->termios) {
1548 cflag = port->normal_termios.c_cflag;
1549 iflag = port->normal_termios.c_iflag;
1550 } else {
1551 cflag = port->tty->termios->c_cflag;
1552 iflag = port->tty->termios->c_iflag;
1553 }
1554
1555 mon_data_ext.databits[i] = cflag & CSIZE;
1556
1557 mon_data_ext.stopbits[i] = cflag & CSTOPB;
1558
1559 mon_data_ext.parity[i] =
1560 cflag & (PARENB | PARODD | CMSPAR);
1561
1562 mon_data_ext.flowctrl[i] = 0x00;
1563
1564 if (cflag & CRTSCTS)
1565 mon_data_ext.flowctrl[i] |= 0x03;
1566
1567 if (iflag & (IXON | IXOFF))
1568 mon_data_ext.flowctrl[i] |= 0x0C;
1569
1570 if (port->type == PORT_16550A)
1571 mon_data_ext.fifo[i] = 1;
1572 else
1573 mon_data_ext.fifo[i] = 0;
1574
1575 p = i % 4;
1576 shiftbit = p * 2;
1577 opmode = inb(port->opmode_ioaddr) >> shiftbit;
1578 opmode &= OP_MODE_MASK;
1579
1580 mon_data_ext.iftype[i] = opmode;
1581
1582 }
1583 if (copy_to_user(argp, &mon_data_ext,
1584 sizeof(mon_data_ext)))
1585 return -EFAULT;
1586
1587 return 0;
1588
1589 } default:
1590 return -ENOIOCTLCMD;
1591 }
1592 return 0;
1593}
1594
1595static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg,
1596 struct async_icount *cprev)
1597{
1598 struct async_icount cnow;
1599 unsigned long flags;
1600 int ret;
1601
1602 spin_lock_irqsave(&info->slock, flags);
1603 cnow = info->icount; /* atomic copy */
1604 spin_unlock_irqrestore(&info->slock, flags);
1605
1606 ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) ||
1607 ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) ||
1608 ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) ||
1609 ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts));
1610
1611 *cprev = cnow;
1612
1613 return ret;
1614}
1615
1616static int mxser_ioctl(struct tty_struct *tty, struct file *file,
1617 unsigned int cmd, unsigned long arg)
1618{
1619 struct mxser_port *info = tty->driver_data;
1620 struct async_icount cnow;
1253 struct serial_icounter_struct __user *p_cuser; 1621 struct serial_icounter_struct __user *p_cuser;
1254 unsigned long templ;
1255 unsigned long flags; 1622 unsigned long flags;
1256 void __user *argp = (void __user *)arg; 1623 void __user *argp = (void __user *)arg;
1624 int retval;
1257 1625
1258 if (tty->index == MXSER_PORTS) 1626 if (tty->index == MXSER_PORTS)
1259 return mxser_ioctl_special(cmd, argp); 1627 return mxser_ioctl_special(cmd, argp);
1260 1628
1261 /* following add by Victor Yu. 01-05-2004 */
1262 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) { 1629 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) {
1263 int opmode, p; 1630 int p;
1631 unsigned long opmode;
1264 static unsigned char ModeMask[] = { 0xfc, 0xf3, 0xcf, 0x3f }; 1632 static unsigned char ModeMask[] = { 0xfc, 0xf3, 0xcf, 0x3f };
1265 int shiftbit; 1633 int shiftbit;
1266 unsigned char val, mask; 1634 unsigned char val, mask;
1267 1635
1268 p = info->port % 4; 1636 p = tty->index % 4;
1269 if (cmd == MOXA_SET_OP_MODE) { 1637 if (cmd == MOXA_SET_OP_MODE) {
1270 if (get_user(opmode, (int __user *) argp)) 1638 if (get_user(opmode, (int __user *) argp))
1271 return -EFAULT; 1639 return -EFAULT;
@@ -1284,17 +1652,16 @@ static int mxser_ioctl(struct tty_struct *tty, struct file *file, unsigned int c
1284 shiftbit = p * 2; 1652 shiftbit = p * 2;
1285 opmode = inb(info->opmode_ioaddr) >> shiftbit; 1653 opmode = inb(info->opmode_ioaddr) >> shiftbit;
1286 opmode &= OP_MODE_MASK; 1654 opmode &= OP_MODE_MASK;
1287 if (copy_to_user(argp, &opmode, sizeof(int))) 1655 if (put_user(opmode, (int __user *)argp))
1288 return -EFAULT; 1656 return -EFAULT;
1289 } 1657 }
1290 return 0; 1658 return 0;
1291 } 1659 }
1292 /* above add by Victor Yu. 01-05-2004 */
1293 1660
1294 if ((cmd != TIOCGSERIAL) && (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) { 1661 if (cmd != TIOCGSERIAL && cmd != TIOCMIWAIT && cmd != TIOCGICOUNT &&
1295 if (tty->flags & (1 << TTY_IO_ERROR)) 1662 test_bit(TTY_IO_ERROR, &tty->flags))
1296 return -EIO; 1663 return -EIO;
1297 } 1664
1298 switch (cmd) { 1665 switch (cmd) {
1299 case TCSBRK: /* SVID version: non-zero arg --> no break */ 1666 case TCSBRK: /* SVID version: non-zero arg --> no break */
1300 retval = tty_check_change(tty); 1667 retval = tty_check_change(tty);
@@ -1312,11 +1679,10 @@ static int mxser_ioctl(struct tty_struct *tty, struct file *file, unsigned int c
1312 mxser_send_break(info, arg ? arg * (HZ / 10) : HZ / 4); 1679 mxser_send_break(info, arg ? arg * (HZ / 10) : HZ / 4);
1313 return 0; 1680 return 0;
1314 case TIOCGSOFTCAR: 1681 case TIOCGSOFTCAR:
1315 return put_user(C_CLOCAL(tty) ? 1 : 0, (unsigned long __user *)argp); 1682 return put_user(!!C_CLOCAL(tty), (unsigned long __user *)argp);
1316 case TIOCSSOFTCAR: 1683 case TIOCSSOFTCAR:
1317 if (get_user(templ, (unsigned long __user *) argp)) 1684 if (get_user(arg, (unsigned long __user *)argp))
1318 return -EFAULT; 1685 return -EFAULT;
1319 arg = templ;
1320 tty->termios->c_cflag = ((tty->termios->c_cflag & ~CLOCAL) | (arg ? CLOCAL : 0)); 1686 tty->termios->c_cflag = ((tty->termios->c_cflag & ~CLOCAL) | (arg ? CLOCAL : 0));
1321 return 0; 1687 return 0;
1322 case TIOCGSERIAL: 1688 case TIOCGSERIAL:
@@ -1336,30 +1702,19 @@ static int mxser_ioctl(struct tty_struct *tty, struct file *file, unsigned int c
1336 cnow = info->icount; /* note the counters on entry */ 1702 cnow = info->icount; /* note the counters on entry */
1337 spin_unlock_irqrestore(&info->slock, flags); 1703 spin_unlock_irqrestore(&info->slock, flags);
1338 1704
1339 wait_event_interruptible(info->delta_msr_wait, ({ 1705 return wait_event_interruptible(info->delta_msr_wait,
1340 cprev = cnow; 1706 mxser_cflags_changed(info, arg, &cnow));
1341 spin_lock_irqsave(&info->slock, flags); 1707 /*
1342 cnow = info->icount; /* atomic copy */ 1708 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1343 spin_unlock_irqrestore(&info->slock, flags); 1709 * Return: write counters to the user passed counter struct
1344 1710 * NB: both 1->0 and 0->1 transitions are counted except for
1345 ((arg & TIOCM_RNG) && (cnow.rng != cprev.rng)) || 1711 * RI where only 0->1 is counted.
1346 ((arg & TIOCM_DSR) && (cnow.dsr != cprev.dsr)) || 1712 */
1347 ((arg & TIOCM_CD) && (cnow.dcd != cprev.dcd)) ||
1348 ((arg & TIOCM_CTS) && (cnow.cts != cprev.cts));
1349 }));
1350 break;
1351 /*
1352 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1353 * Return: write counters to the user passed counter struct
1354 * NB: both 1->0 and 0->1 transitions are counted except for
1355 * RI where only 0->1 is counted.
1356 */
1357 case TIOCGICOUNT: 1713 case TIOCGICOUNT:
1358 spin_lock_irqsave(&info->slock, flags); 1714 spin_lock_irqsave(&info->slock, flags);
1359 cnow = info->icount; 1715 cnow = info->icount;
1360 spin_unlock_irqrestore(&info->slock, flags); 1716 spin_unlock_irqrestore(&info->slock, flags);
1361 p_cuser = argp; 1717 p_cuser = argp;
1362 /* modified by casper 1/11/2000 */
1363 if (put_user(cnow.frame, &p_cuser->frame)) 1718 if (put_user(cnow.frame, &p_cuser->frame))
1364 return -EFAULT; 1719 return -EFAULT;
1365 if (put_user(cnow.brk, &p_cuser->brk)) 1720 if (put_user(cnow.brk, &p_cuser->brk))
@@ -1381,241 +1736,65 @@ static int mxser_ioctl(struct tty_struct *tty, struct file *file, unsigned int c
1381 return 0; 1736 return 0;
1382 case MOXA_HighSpeedOn: 1737 case MOXA_HighSpeedOn:
1383 return put_user(info->baud_base != 115200 ? 1 : 0, (int __user *)argp); 1738 return put_user(info->baud_base != 115200 ? 1 : 0, (int __user *)argp);
1384 case MOXA_SDS_RSTICOUNTER: { 1739 case MOXA_SDS_RSTICOUNTER:
1385 info->mon_data.rxcnt = 0; 1740 info->mon_data.rxcnt = 0;
1386 info->mon_data.txcnt = 0; 1741 info->mon_data.txcnt = 0;
1387 return 0;
1388 }
1389/* (above) added by James. */
1390 case MOXA_ASPP_SETBAUD:{
1391 long baud;
1392 if (get_user(baud, (long __user *)argp))
1393 return -EFAULT;
1394 if (mxser_set_baud(info, baud) == -1)
1395 return -1;
1396 return 0;
1397 }
1398 case MOXA_ASPP_GETBAUD:
1399 if (copy_to_user(argp, &info->realbaud, sizeof(long)))
1400 return -EFAULT;
1401
1402 return 0; 1742 return 0;
1403 1743
1404 case MOXA_ASPP_OQUEUE:{ 1744 case MOXA_ASPP_OQUEUE:{
1405 int len, lsr; 1745 int len, lsr;
1406 1746
1407 len = mxser_chars_in_buffer(tty); 1747 len = mxser_chars_in_buffer(tty);
1408 1748
1409 lsr = inb(info->base + UART_LSR) & UART_LSR_TEMT; 1749 lsr = inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT;
1410 1750
1411 len += (lsr ? 0 : 1); 1751 len += (lsr ? 0 : 1);
1412 1752
1413 if (copy_to_user(argp, &len, sizeof(int))) 1753 return put_user(len, (int __user *)argp);
1414 return -EFAULT; 1754 }
1415
1416 return 0;
1417 }
1418 case MOXA_ASPP_MON: { 1755 case MOXA_ASPP_MON: {
1419 int mcr, status; 1756 int mcr, status;
1420
1421 /* info->mon_data.ser_param = tty->termios->c_cflag; */
1422 1757
1423 status = mxser_get_msr(info->base, 1, info->port, info); 1758 status = mxser_get_msr(info->ioaddr, 1, tty->index);
1424 mxser_check_modem_status(info, status); 1759 mxser_check_modem_status(info, status);
1425
1426 mcr = inb(info->base + UART_MCR);
1427 if (mcr & MOXA_MUST_MCR_XON_FLAG)
1428 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFHOLD;
1429 else
1430 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFHOLD;
1431
1432 if (mcr & MOXA_MUST_MCR_TX_XON)
1433 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFXENT;
1434 else
1435 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFXENT;
1436
1437 if (info->tty->hw_stopped)
1438 info->mon_data.hold_reason |= NPPI_NOTIFY_CTSHOLD;
1439 else
1440 info->mon_data.hold_reason &= ~NPPI_NOTIFY_CTSHOLD;
1441
1442 if (copy_to_user(argp, &info->mon_data,
1443 sizeof(struct mxser_mon)))
1444 return -EFAULT;
1445
1446 return 0;
1447 }
1448
1449 case MOXA_ASPP_LSTATUS: {
1450 if (copy_to_user(argp, &info->err_shadow,
1451 sizeof(unsigned char)))
1452 return -EFAULT;
1453
1454 info->err_shadow = 0;
1455 return 0;
1456 }
1457 case MOXA_SET_BAUD_METHOD: {
1458 int method;
1459
1460 if (get_user(method, (int __user *)argp))
1461 return -EFAULT;
1462 mxser_set_baud_method[info->port] = method;
1463 if (copy_to_user(argp, &method, sizeof(int)))
1464 return -EFAULT;
1465 1760
1466 return 0; 1761 mcr = inb(info->ioaddr + UART_MCR);
1467 } 1762 if (mcr & MOXA_MUST_MCR_XON_FLAG)
1468 default: 1763 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFHOLD;
1469 return -ENOIOCTLCMD; 1764 else
1470 } 1765 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFHOLD;
1471 return 0;
1472}
1473 1766
1474#ifndef CMSPAR 1767 if (mcr & MOXA_MUST_MCR_TX_XON)
1475#define CMSPAR 010000000000 1768 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFXENT;
1476#endif 1769 else
1770 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFXENT;
1477 1771
1478static int mxser_ioctl_special(unsigned int cmd, void __user *argp) 1772 if (info->tty->hw_stopped)
1479{ 1773 info->mon_data.hold_reason |= NPPI_NOTIFY_CTSHOLD;
1480 int i, result, status; 1774 else
1775 info->mon_data.hold_reason &= ~NPPI_NOTIFY_CTSHOLD;
1481 1776
1482 switch (cmd) { 1777 if (copy_to_user(argp, &info->mon_data,
1483 case MOXA_GET_CONF: 1778 sizeof(struct mxser_mon)))
1484 if (copy_to_user(argp, mxsercfg,
1485 sizeof(struct mxser_hwconf) * 4))
1486 return -EFAULT; 1779 return -EFAULT;
1487 return 0;
1488 case MOXA_GET_MAJOR:
1489 if (copy_to_user(argp, &ttymajor, sizeof(int)))
1490 return -EFAULT;
1491 return 0;
1492 1780
1493 case MOXA_GET_CUMAJOR:
1494 if (copy_to_user(argp, &calloutmajor, sizeof(int)))
1495 return -EFAULT;
1496 return 0; 1781 return 0;
1497 1782 }
1498 case MOXA_CHKPORTENABLE: 1783 case MOXA_ASPP_LSTATUS: {
1499 result = 0; 1784 if (put_user(info->err_shadow, (unsigned char __user *)argp))
1500 for (i = 0; i < MXSER_PORTS; i++) {
1501 if (mxvar_table[i].base)
1502 result |= (1 << i);
1503 }
1504 return put_user(result, (unsigned long __user *)argp);
1505 case MOXA_GETDATACOUNT:
1506 if (copy_to_user(argp, &mxvar_log, sizeof(mxvar_log)))
1507 return -EFAULT; 1785 return -EFAULT;
1508 return 0;
1509 case MOXA_GETMSTATUS:
1510 for (i = 0; i < MXSER_PORTS; i++) {
1511 GMStatus[i].ri = 0;
1512 if (!mxvar_table[i].base) {
1513 GMStatus[i].dcd = 0;
1514 GMStatus[i].dsr = 0;
1515 GMStatus[i].cts = 0;
1516 continue;
1517 }
1518
1519 if (!mxvar_table[i].tty || !mxvar_table[i].tty->termios)
1520 GMStatus[i].cflag = mxvar_table[i].normal_termios.c_cflag;
1521 else
1522 GMStatus[i].cflag = mxvar_table[i].tty->termios->c_cflag;
1523
1524 status = inb(mxvar_table[i].base + UART_MSR);
1525 if (status & 0x80 /*UART_MSR_DCD */ )
1526 GMStatus[i].dcd = 1;
1527 else
1528 GMStatus[i].dcd = 0;
1529
1530 if (status & 0x20 /*UART_MSR_DSR */ )
1531 GMStatus[i].dsr = 1;
1532 else
1533 GMStatus[i].dsr = 0;
1534
1535 1786
1536 if (status & 0x10 /*UART_MSR_CTS */ ) 1787 info->err_shadow = 0;
1537 GMStatus[i].cts = 1;
1538 else
1539 GMStatus[i].cts = 0;
1540 }
1541 if (copy_to_user(argp, GMStatus,
1542 sizeof(struct mxser_mstatus) * MXSER_PORTS))
1543 return -EFAULT;
1544 return 0; 1788 return 0;
1545 case MOXA_ASPP_MON_EXT: { 1789 }
1546 int status; 1790 case MOXA_SET_BAUD_METHOD: {
1547 int opmode, p; 1791 int method;
1548 int shiftbit;
1549 unsigned cflag, iflag;
1550
1551 for (i = 0; i < MXSER_PORTS; i++) {
1552 if (!mxvar_table[i].base)
1553 continue;
1554
1555 status = mxser_get_msr(mxvar_table[i].base, 0,
1556 i, &(mxvar_table[i]));
1557 /*
1558 mxser_check_modem_status(&mxvar_table[i],
1559 status);
1560 */
1561 if (status & UART_MSR_TERI)
1562 mxvar_table[i].icount.rng++;
1563 if (status & UART_MSR_DDSR)
1564 mxvar_table[i].icount.dsr++;
1565 if (status & UART_MSR_DDCD)
1566 mxvar_table[i].icount.dcd++;
1567 if (status & UART_MSR_DCTS)
1568 mxvar_table[i].icount.cts++;
1569
1570 mxvar_table[i].mon_data.modem_status = status;
1571 mon_data_ext.rx_cnt[i] = mxvar_table[i].mon_data.rxcnt;
1572 mon_data_ext.tx_cnt[i] = mxvar_table[i].mon_data.txcnt;
1573 mon_data_ext.up_rxcnt[i] = mxvar_table[i].mon_data.up_rxcnt;
1574 mon_data_ext.up_txcnt[i] = mxvar_table[i].mon_data.up_txcnt;
1575 mon_data_ext.modem_status[i] = mxvar_table[i].mon_data.modem_status;
1576 mon_data_ext.baudrate[i] = mxvar_table[i].realbaud;
1577
1578 if (!mxvar_table[i].tty || !mxvar_table[i].tty->termios) {
1579 cflag = mxvar_table[i].normal_termios.c_cflag;
1580 iflag = mxvar_table[i].normal_termios.c_iflag;
1581 } else {
1582 cflag = mxvar_table[i].tty->termios->c_cflag;
1583 iflag = mxvar_table[i].tty->termios->c_iflag;
1584 }
1585
1586 mon_data_ext.databits[i] = cflag & CSIZE;
1587
1588 mon_data_ext.stopbits[i] = cflag & CSTOPB;
1589
1590 mon_data_ext.parity[i] = cflag & (PARENB | PARODD | CMSPAR);
1591
1592 mon_data_ext.flowctrl[i] = 0x00;
1593
1594 if (cflag & CRTSCTS)
1595 mon_data_ext.flowctrl[i] |= 0x03;
1596
1597 if (iflag & (IXON | IXOFF))
1598 mon_data_ext.flowctrl[i] |= 0x0C;
1599
1600 if (mxvar_table[i].type == PORT_16550A)
1601 mon_data_ext.fifo[i] = 1;
1602 else
1603 mon_data_ext.fifo[i] = 0;
1604
1605 p = i % 4;
1606 shiftbit = p * 2;
1607 opmode = inb(mxvar_table[i].opmode_ioaddr) >> shiftbit;
1608 opmode &= OP_MODE_MASK;
1609
1610 mon_data_ext.iftype[i] = opmode;
1611
1612 }
1613 if (copy_to_user(argp, &mon_data_ext, sizeof(struct mxser_mon_ext)))
1614 return -EFAULT;
1615
1616 return 0;
1617 1792
1618 } 1793 if (get_user(method, (int __user *)argp))
1794 return -EFAULT;
1795 mxser_set_baud_method[tty->index] = method;
1796 return put_user(method, (int __user *)argp);
1797 }
1619 default: 1798 default:
1620 return -ENOIOCTLCMD; 1799 return -ENOIOCTLCMD;
1621 } 1800 }
@@ -1624,107 +1803,105 @@ static int mxser_ioctl_special(unsigned int cmd, void __user *argp)
1624 1803
1625static void mxser_stoprx(struct tty_struct *tty) 1804static void mxser_stoprx(struct tty_struct *tty)
1626{ 1805{
1627 struct mxser_struct *info = tty->driver_data; 1806 struct mxser_port *info = tty->driver_data;
1628 /* unsigned long flags; */
1629 1807
1630 info->ldisc_stop_rx = 1; 1808 info->ldisc_stop_rx = 1;
1631 if (I_IXOFF(tty)) { 1809 if (I_IXOFF(tty)) {
1632 /* MX_LOCK(&info->slock); */ 1810 if (info->board->chip_flag) {
1633 /* following add by Victor Yu. 09-02-2002 */
1634 if (info->IsMoxaMustChipFlag) {
1635 info->IER &= ~MOXA_MUST_RECV_ISR; 1811 info->IER &= ~MOXA_MUST_RECV_ISR;
1636 outb(info->IER, info->base + UART_IER); 1812 outb(info->IER, info->ioaddr + UART_IER);
1637 } else { 1813 } else {
1638 /* above add by Victor Yu. 09-02-2002 */
1639 info->x_char = STOP_CHAR(tty); 1814 info->x_char = STOP_CHAR(tty);
1640 /* mask by Victor Yu. 09-02-2002 */ 1815 outb(0, info->ioaddr + UART_IER);
1641 /* outb(info->IER, 0); */
1642 outb(0, info->base + UART_IER);
1643 info->IER |= UART_IER_THRI; 1816 info->IER |= UART_IER_THRI;
1644 /* force Tx interrupt */ 1817 outb(info->IER, info->ioaddr + UART_IER);
1645 outb(info->IER, info->base + UART_IER); 1818 }
1646 } /* add by Victor Yu. 09-02-2002 */
1647 /* MX_UNLOCK(&info->slock); */
1648 } 1819 }
1649 1820
1650 if (info->tty->termios->c_cflag & CRTSCTS) { 1821 if (info->tty->termios->c_cflag & CRTSCTS) {
1651 /* MX_LOCK(&info->slock); */
1652 info->MCR &= ~UART_MCR_RTS; 1822 info->MCR &= ~UART_MCR_RTS;
1653 outb(info->MCR, info->base + UART_MCR); 1823 outb(info->MCR, info->ioaddr + UART_MCR);
1654 /* MX_UNLOCK(&info->slock); */
1655 } 1824 }
1656} 1825}
1657 1826
1658static void mxser_startrx(struct tty_struct *tty) 1827/*
1828 * This routine is called by the upper-layer tty layer to signal that
1829 * incoming characters should be throttled.
1830 */
1831static void mxser_throttle(struct tty_struct *tty)
1832{
1833 mxser_stoprx(tty);
1834}
1835
1836static void mxser_unthrottle(struct tty_struct *tty)
1659{ 1837{
1660 struct mxser_struct *info = tty->driver_data; 1838 struct mxser_port *info = tty->driver_data;
1661 /* unsigned long flags; */
1662 1839
1840 /* startrx */
1663 info->ldisc_stop_rx = 0; 1841 info->ldisc_stop_rx = 0;
1664 if (I_IXOFF(tty)) { 1842 if (I_IXOFF(tty)) {
1665 if (info->x_char) 1843 if (info->x_char)
1666 info->x_char = 0; 1844 info->x_char = 0;
1667 else { 1845 else {
1668 /* MX_LOCK(&info->slock); */ 1846 if (info->board->chip_flag) {
1669
1670 /* following add by Victor Yu. 09-02-2002 */
1671 if (info->IsMoxaMustChipFlag) {
1672 info->IER |= MOXA_MUST_RECV_ISR; 1847 info->IER |= MOXA_MUST_RECV_ISR;
1673 outb(info->IER, info->base + UART_IER); 1848 outb(info->IER, info->ioaddr + UART_IER);
1674 } else { 1849 } else {
1675 /* above add by Victor Yu. 09-02-2002 */
1676
1677 info->x_char = START_CHAR(tty); 1850 info->x_char = START_CHAR(tty);
1678 /* mask by Victor Yu. 09-02-2002 */ 1851 outb(0, info->ioaddr + UART_IER);
1679 /* outb(info->IER, 0); */
1680 /* add by Victor Yu. 09-02-2002 */
1681 outb(0, info->base + UART_IER);
1682 /* force Tx interrupt */
1683 info->IER |= UART_IER_THRI; 1852 info->IER |= UART_IER_THRI;
1684 outb(info->IER, info->base + UART_IER); 1853 outb(info->IER, info->ioaddr + UART_IER);
1685 } /* add by Victor Yu. 09-02-2002 */ 1854 }
1686 /* MX_UNLOCK(&info->slock); */
1687 } 1855 }
1688 } 1856 }
1689 1857
1690 if (info->tty->termios->c_cflag & CRTSCTS) { 1858 if (info->tty->termios->c_cflag & CRTSCTS) {
1691 /* MX_LOCK(&info->slock); */
1692 info->MCR |= UART_MCR_RTS; 1859 info->MCR |= UART_MCR_RTS;
1693 outb(info->MCR, info->base + UART_MCR); 1860 outb(info->MCR, info->ioaddr + UART_MCR);
1694 /* MX_UNLOCK(&info->slock); */
1695 } 1861 }
1696} 1862}
1697 1863
1698/* 1864/*
1699 * This routine is called by the upper-layer tty layer to signal that 1865 * mxser_stop() and mxser_start()
1700 * incoming characters should be throttled. 1866 *
1867 * This routines are called before setting or resetting tty->stopped.
1868 * They enable or disable transmitter interrupts, as necessary.
1701 */ 1869 */
1702static void mxser_throttle(struct tty_struct *tty) 1870static void mxser_stop(struct tty_struct *tty)
1703{ 1871{
1704 /* struct mxser_struct *info = tty->driver_data; */ 1872 struct mxser_port *info = tty->driver_data;
1705 /* unsigned long flags; */ 1873 unsigned long flags;
1706 1874
1707 /* MX_LOCK(&info->slock); */ 1875 spin_lock_irqsave(&info->slock, flags);
1708 mxser_stoprx(tty); 1876 if (info->IER & UART_IER_THRI) {
1709 /* MX_UNLOCK(&info->slock); */ 1877 info->IER &= ~UART_IER_THRI;
1878 outb(info->IER, info->ioaddr + UART_IER);
1879 }
1880 spin_unlock_irqrestore(&info->slock, flags);
1710} 1881}
1711 1882
1712static void mxser_unthrottle(struct tty_struct *tty) 1883static void mxser_start(struct tty_struct *tty)
1713{ 1884{
1714 /* struct mxser_struct *info = tty->driver_data; */ 1885 struct mxser_port *info = tty->driver_data;
1715 /* unsigned long flags; */ 1886 unsigned long flags;
1716 1887
1717 /* MX_LOCK(&info->slock); */ 1888 spin_lock_irqsave(&info->slock, flags);
1718 mxser_startrx(tty); 1889 if (info->xmit_cnt && info->xmit_buf) {
1719 /* MX_UNLOCK(&info->slock); */ 1890 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1891 info->IER |= UART_IER_THRI;
1892 outb(info->IER, info->ioaddr + UART_IER);
1893 }
1894 spin_unlock_irqrestore(&info->slock, flags);
1720} 1895}
1721 1896
1722static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios) 1897static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1723{ 1898{
1724 struct mxser_struct *info = tty->driver_data; 1899 struct mxser_port *info = tty->driver_data;
1725 unsigned long flags; 1900 unsigned long flags;
1726 1901
1902 spin_lock_irqsave(&info->slock, flags);
1727 mxser_change_speed(info, old_termios); 1903 mxser_change_speed(info, old_termios);
1904 spin_unlock_irqrestore(&info->slock, flags);
1728 1905
1729 if ((old_termios->c_cflag & CRTSCTS) && 1906 if ((old_termios->c_cflag & CRTSCTS) &&
1730 !(tty->termios->c_cflag & CRTSCTS)) { 1907 !(tty->termios->c_cflag & CRTSCTS)) {
@@ -1732,61 +1909,27 @@ static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termi
1732 mxser_start(tty); 1909 mxser_start(tty);
1733 } 1910 }
1734 1911
1735/* Handle sw stopped */ 1912 /* Handle sw stopped */
1736 if ((old_termios->c_iflag & IXON) && 1913 if ((old_termios->c_iflag & IXON) &&
1737 !(tty->termios->c_iflag & IXON)) { 1914 !(tty->termios->c_iflag & IXON)) {
1738 tty->stopped = 0; 1915 tty->stopped = 0;
1739 1916
1740 /* following add by Victor Yu. 09-02-2002 */ 1917 if (info->board->chip_flag) {
1741 if (info->IsMoxaMustChipFlag) {
1742 spin_lock_irqsave(&info->slock, flags); 1918 spin_lock_irqsave(&info->slock, flags);
1743 DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->base); 1919 DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr);
1744 spin_unlock_irqrestore(&info->slock, flags); 1920 spin_unlock_irqrestore(&info->slock, flags);
1745 } 1921 }
1746 /* above add by Victor Yu. 09-02-2002 */
1747 1922
1748 mxser_start(tty); 1923 mxser_start(tty);
1749 } 1924 }
1750} 1925}
1751 1926
1752/* 1927/*
1753 * mxser_stop() and mxser_start()
1754 *
1755 * This routines are called before setting or resetting tty->stopped.
1756 * They enable or disable transmitter interrupts, as necessary.
1757 */
1758static void mxser_stop(struct tty_struct *tty)
1759{
1760 struct mxser_struct *info = tty->driver_data;
1761 unsigned long flags;
1762
1763 spin_lock_irqsave(&info->slock, flags);
1764 if (info->IER & UART_IER_THRI) {
1765 info->IER &= ~UART_IER_THRI;
1766 outb(info->IER, info->base + UART_IER);
1767 }
1768 spin_unlock_irqrestore(&info->slock, flags);
1769}
1770
1771static void mxser_start(struct tty_struct *tty)
1772{
1773 struct mxser_struct *info = tty->driver_data;
1774 unsigned long flags;
1775
1776 spin_lock_irqsave(&info->slock, flags);
1777 if (info->xmit_cnt && info->xmit_buf && !(info->IER & UART_IER_THRI)) {
1778 info->IER |= UART_IER_THRI;
1779 outb(info->IER, info->base + UART_IER);
1780 }
1781 spin_unlock_irqrestore(&info->slock, flags);
1782}
1783
1784/*
1785 * mxser_wait_until_sent() --- wait until the transmitter is empty 1928 * mxser_wait_until_sent() --- wait until the transmitter is empty
1786 */ 1929 */
1787static void mxser_wait_until_sent(struct tty_struct *tty, int timeout) 1930static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
1788{ 1931{
1789 struct mxser_struct *info = tty->driver_data; 1932 struct mxser_port *info = tty->driver_data;
1790 unsigned long orig_jiffies, char_time; 1933 unsigned long orig_jiffies, char_time;
1791 int lsr; 1934 int lsr;
1792 1935
@@ -1827,7 +1970,7 @@ static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
1827 timeout, char_time); 1970 timeout, char_time);
1828 printk("jiff=%lu...", jiffies); 1971 printk("jiff=%lu...", jiffies);
1829#endif 1972#endif
1830 while (!((lsr = inb(info->base + UART_LSR)) & UART_LSR_TEMT)) { 1973 while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) {
1831#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT 1974#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
1832 printk("lsr = %d (jiff=%lu)...", lsr, jiffies); 1975 printk("lsr = %d (jiff=%lu)...", lsr, jiffies);
1833#endif 1976#endif
@@ -1844,13 +1987,12 @@ static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
1844#endif 1987#endif
1845} 1988}
1846 1989
1847
1848/* 1990/*
1849 * This routine is called by tty_hangup() when a hangup is signaled. 1991 * This routine is called by tty_hangup() when a hangup is signaled.
1850 */ 1992 */
1851void mxser_hangup(struct tty_struct *tty) 1993static void mxser_hangup(struct tty_struct *tty)
1852{ 1994{
1853 struct mxser_struct *info = tty->driver_data; 1995 struct mxser_port *info = tty->driver_data;
1854 1996
1855 mxser_flush_buffer(tty); 1997 mxser_flush_buffer(tty);
1856 mxser_shutdown(info); 1998 mxser_shutdown(info);
@@ -1861,231 +2003,73 @@ void mxser_hangup(struct tty_struct *tty)
1861 wake_up_interruptible(&info->open_wait); 2003 wake_up_interruptible(&info->open_wait);
1862} 2004}
1863 2005
1864
1865/* added by James 03-12-2004. */
1866/* 2006/*
1867 * mxser_rs_break() --- routine which turns the break handling on or off 2007 * mxser_rs_break() --- routine which turns the break handling on or off
1868 */ 2008 */
1869static void mxser_rs_break(struct tty_struct *tty, int break_state) 2009static void mxser_rs_break(struct tty_struct *tty, int break_state)
1870{ 2010{
1871 struct mxser_struct *info = tty->driver_data; 2011 struct mxser_port *info = tty->driver_data;
1872 unsigned long flags; 2012 unsigned long flags;
1873 2013
1874 spin_lock_irqsave(&info->slock, flags); 2014 spin_lock_irqsave(&info->slock, flags);
1875 if (break_state == -1) 2015 if (break_state == -1)
1876 outb(inb(info->base + UART_LCR) | UART_LCR_SBC, 2016 outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC,
1877 info->base + UART_LCR); 2017 info->ioaddr + UART_LCR);
1878 else 2018 else
1879 outb(inb(info->base + UART_LCR) & ~UART_LCR_SBC, 2019 outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC,
1880 info->base + UART_LCR); 2020 info->ioaddr + UART_LCR);
1881 spin_unlock_irqrestore(&info->slock, flags); 2021 spin_unlock_irqrestore(&info->slock, flags);
1882} 2022}
1883 2023
1884/* (above) added by James. */ 2024static void mxser_receive_chars(struct mxser_port *port, int *status)
1885
1886
1887/*
1888 * This is the serial driver's generic interrupt routine
1889 */
1890static irqreturn_t mxser_interrupt(int irq, void *dev_id)
1891{
1892 int status, iir, i;
1893 struct mxser_struct *info;
1894 struct mxser_struct *port;
1895 int max, irqbits, bits, msr;
1896 int pass_counter = 0;
1897 int handled = IRQ_NONE;
1898
1899 port = NULL;
1900 /* spin_lock(&gm_lock); */
1901
1902 for (i = 0; i < MXSER_BOARDS; i++) {
1903 if (dev_id == &(mxvar_table[i * MXSER_PORTS_PER_BOARD])) {
1904 port = dev_id;
1905 break;
1906 }
1907 }
1908
1909 if (i == MXSER_BOARDS)
1910 goto irq_stop;
1911 if (port == 0)
1912 goto irq_stop;
1913 max = mxser_numports[mxsercfg[i].board_type - 1];
1914 while (1) {
1915 irqbits = inb(port->vector) & port->vectormask;
1916 if (irqbits == port->vectormask)
1917 break;
1918
1919 handled = IRQ_HANDLED;
1920 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
1921 if (irqbits == port->vectormask)
1922 break;
1923 if (bits & irqbits)
1924 continue;
1925 info = port + i;
1926
1927 /* following add by Victor Yu. 09-13-2002 */
1928 iir = inb(info->base + UART_IIR);
1929 if (iir & UART_IIR_NO_INT)
1930 continue;
1931 iir &= MOXA_MUST_IIR_MASK;
1932 if (!info->tty) {
1933 status = inb(info->base + UART_LSR);
1934 outb(0x27, info->base + UART_FCR);
1935 inb(info->base + UART_MSR);
1936 continue;
1937 }
1938
1939 /* mask by Victor Yu. 09-13-2002
1940 if ( !info->tty ||
1941 (inb(info->base + UART_IIR) & UART_IIR_NO_INT) )
1942 continue;
1943 */
1944 /* mask by Victor Yu. 09-02-2002
1945 status = inb(info->base + UART_LSR) & info->read_status_mask;
1946 */
1947
1948 /* following add by Victor Yu. 09-02-2002 */
1949 status = inb(info->base + UART_LSR);
1950
1951 if (status & UART_LSR_PE)
1952 info->err_shadow |= NPPI_NOTIFY_PARITY;
1953 if (status & UART_LSR_FE)
1954 info->err_shadow |= NPPI_NOTIFY_FRAMING;
1955 if (status & UART_LSR_OE)
1956 info->err_shadow |= NPPI_NOTIFY_HW_OVERRUN;
1957 if (status & UART_LSR_BI)
1958 info->err_shadow |= NPPI_NOTIFY_BREAK;
1959
1960 if (info->IsMoxaMustChipFlag) {
1961 /*
1962 if ( (status & 0x02) && !(status & 0x01) ) {
1963 outb(info->base+UART_FCR, 0x23);
1964 continue;
1965 }
1966 */
1967 if (iir == MOXA_MUST_IIR_GDA ||
1968 iir == MOXA_MUST_IIR_RDA ||
1969 iir == MOXA_MUST_IIR_RTO ||
1970 iir == MOXA_MUST_IIR_LSR)
1971 mxser_receive_chars(info, &status);
1972
1973 } else {
1974 /* above add by Victor Yu. 09-02-2002 */
1975
1976 status &= info->read_status_mask;
1977 if (status & UART_LSR_DR)
1978 mxser_receive_chars(info, &status);
1979 }
1980 msr = inb(info->base + UART_MSR);
1981 if (msr & UART_MSR_ANY_DELTA) {
1982 mxser_check_modem_status(info, msr);
1983 }
1984 /* following add by Victor Yu. 09-13-2002 */
1985 if (info->IsMoxaMustChipFlag) {
1986 if ((iir == 0x02) && (status & UART_LSR_THRE)) {
1987 mxser_transmit_chars(info);
1988 }
1989 } else {
1990 /* above add by Victor Yu. 09-13-2002 */
1991
1992 if (status & UART_LSR_THRE) {
1993/* 8-2-99 by William
1994 if ( info->x_char || (info->xmit_cnt > 0) )
1995*/
1996 mxser_transmit_chars(info);
1997 }
1998 }
1999 }
2000 if (pass_counter++ > MXSER_ISR_PASS_LIMIT) {
2001 break; /* Prevent infinite loops */
2002 }
2003 }
2004
2005 irq_stop:
2006 /* spin_unlock(&gm_lock); */
2007 return handled;
2008}
2009
2010static void mxser_receive_chars(struct mxser_struct *info, int *status)
2011{ 2025{
2012 struct tty_struct *tty = info->tty; 2026 struct tty_struct *tty = port->tty;
2013 unsigned char ch, gdl; 2027 unsigned char ch, gdl;
2014 int ignored = 0; 2028 int ignored = 0;
2015 int cnt = 0; 2029 int cnt = 0;
2016 int recv_room; 2030 int recv_room;
2017 int max = 256; 2031 int max = 256;
2018 unsigned long flags;
2019
2020 spin_lock_irqsave(&info->slock, flags);
2021 2032
2022 recv_room = tty->receive_room; 2033 recv_room = tty->receive_room;
2023 if ((recv_room == 0) && (!info->ldisc_stop_rx)) { 2034 if ((recv_room == 0) && (!port->ldisc_stop_rx))
2024 /* mxser_throttle(tty); */
2025 mxser_stoprx(tty); 2035 mxser_stoprx(tty);
2026 /* return; */
2027 }
2028 2036
2029 /* following add by Victor Yu. 09-02-2002 */ 2037 if (port->board->chip_flag != MOXA_OTHER_UART) {
2030 if (info->IsMoxaMustChipFlag != MOXA_OTHER_UART) {
2031 2038
2032 if (*status & UART_LSR_SPECIAL) { 2039 if (*status & UART_LSR_SPECIAL)
2033 goto intr_old; 2040 goto intr_old;
2034 } 2041 if (port->board->chip_flag == MOXA_MUST_MU860_HWID &&
2035 /* following add by Victor Yu. 02-11-2004 */
2036 if (info->IsMoxaMustChipFlag == MOXA_MUST_MU860_HWID &&
2037 (*status & MOXA_MUST_LSR_RERR)) 2042 (*status & MOXA_MUST_LSR_RERR))
2038 goto intr_old; 2043 goto intr_old;
2039 /* above add by Victor Yu. 02-14-2004 */
2040 if (*status & MOXA_MUST_LSR_RERR) 2044 if (*status & MOXA_MUST_LSR_RERR)
2041 goto intr_old; 2045 goto intr_old;
2042 2046
2043 gdl = inb(info->base + MOXA_MUST_GDL_REGISTER); 2047 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER);
2044 2048
2045 /* add by Victor Yu. 02-11-2004 */ 2049 if (port->board->chip_flag == MOXA_MUST_MU150_HWID)
2046 if (info->IsMoxaMustChipFlag == MOXA_MUST_MU150_HWID)
2047 gdl &= MOXA_MUST_GDL_MASK; 2050 gdl &= MOXA_MUST_GDL_MASK;
2048 if (gdl >= recv_room) { 2051 if (gdl >= recv_room) {
2049 if (!info->ldisc_stop_rx) { 2052 if (!port->ldisc_stop_rx)
2050 /* mxser_throttle(tty); */
2051 mxser_stoprx(tty); 2053 mxser_stoprx(tty);
2052 }
2053 /* return; */
2054 } 2054 }
2055 while (gdl--) { 2055 while (gdl--) {
2056 ch = inb(info->base + UART_RX); 2056 ch = inb(port->ioaddr + UART_RX);
2057 tty_insert_flip_char(tty, ch, 0); 2057 tty_insert_flip_char(tty, ch, 0);
2058 cnt++; 2058 cnt++;
2059 /*
2060 if ((cnt >= HI_WATER) && (info->stop_rx == 0)) {
2061 mxser_stoprx(tty);
2062 info->stop_rx = 1;
2063 break;
2064 } */
2065 } 2059 }
2066 goto end_intr; 2060 goto end_intr;
2067 } 2061 }
2068 intr_old: 2062intr_old:
2069 /* above add by Victor Yu. 09-02-2002 */
2070 2063
2071 do { 2064 do {
2072 if (max-- < 0) 2065 if (max-- < 0)
2073 break; 2066 break;
2074 /*
2075 if ((cnt >= HI_WATER) && (info->stop_rx == 0)) {
2076 mxser_stoprx(tty);
2077 info->stop_rx=1;
2078 break;
2079 }
2080 */
2081 2067
2082 ch = inb(info->base + UART_RX); 2068 ch = inb(port->ioaddr + UART_RX);
2083 /* following add by Victor Yu. 09-02-2002 */ 2069 if (port->board->chip_flag && (*status & UART_LSR_OE))
2084 if (info->IsMoxaMustChipFlag && (*status & UART_LSR_OE) /*&& !(*status&UART_LSR_DR) */ ) 2070 outb(0x23, port->ioaddr + UART_FCR);
2085 outb(0x23, info->base + UART_FCR); 2071 *status &= port->read_status_mask;
2086 *status &= info->read_status_mask; 2072 if (*status & port->ignore_status_mask) {
2087 /* above add by Victor Yu. 09-02-2002 */
2088 if (*status & info->ignore_status_mask) {
2089 if (++ignored > 100) 2073 if (++ignored > 100)
2090 break; 2074 break;
2091 } else { 2075 } else {
@@ -2093,1048 +2077,652 @@ static void mxser_receive_chars(struct mxser_struct *info, int *status)
2093 if (*status & UART_LSR_SPECIAL) { 2077 if (*status & UART_LSR_SPECIAL) {
2094 if (*status & UART_LSR_BI) { 2078 if (*status & UART_LSR_BI) {
2095 flag = TTY_BREAK; 2079 flag = TTY_BREAK;
2096/* added by casper 1/11/2000 */ 2080 port->icount.brk++;
2097 info->icount.brk++; 2081
2098/* */ 2082 if (port->flags & ASYNC_SAK)
2099 if (info->flags & ASYNC_SAK)
2100 do_SAK(tty); 2083 do_SAK(tty);
2101 } else if (*status & UART_LSR_PE) { 2084 } else if (*status & UART_LSR_PE) {
2102 flag = TTY_PARITY; 2085 flag = TTY_PARITY;
2103/* added by casper 1/11/2000 */ 2086 port->icount.parity++;
2104 info->icount.parity++;
2105/* */
2106 } else if (*status & UART_LSR_FE) { 2087 } else if (*status & UART_LSR_FE) {
2107 flag = TTY_FRAME; 2088 flag = TTY_FRAME;
2108/* added by casper 1/11/2000 */ 2089 port->icount.frame++;
2109 info->icount.frame++;
2110/* */
2111 } else if (*status & UART_LSR_OE) { 2090 } else if (*status & UART_LSR_OE) {
2112 flag = TTY_OVERRUN; 2091 flag = TTY_OVERRUN;
2113/* added by casper 1/11/2000 */ 2092 port->icount.overrun++;
2114 info->icount.overrun++; 2093 } else
2115/* */ 2094 flag = TTY_BREAK;
2116 }
2117 } 2095 }
2118 tty_insert_flip_char(tty, ch, flag); 2096 tty_insert_flip_char(tty, ch, flag);
2119 cnt++; 2097 cnt++;
2120 if (cnt >= recv_room) { 2098 if (cnt >= recv_room) {
2121 if (!info->ldisc_stop_rx) { 2099 if (!port->ldisc_stop_rx)
2122 /* mxser_throttle(tty); */
2123 mxser_stoprx(tty); 2100 mxser_stoprx(tty);
2124 }
2125 break; 2101 break;
2126 } 2102 }
2127 2103
2128 } 2104 }
2129 2105
2130 /* following add by Victor Yu. 09-02-2002 */ 2106 if (port->board->chip_flag)
2131 if (info->IsMoxaMustChipFlag)
2132 break; 2107 break;
2133 /* above add by Victor Yu. 09-02-2002 */
2134 2108
2135 /* mask by Victor Yu. 09-02-2002 2109 *status = inb(port->ioaddr + UART_LSR);
2136 *status = inb(info->base + UART_LSR) & info->read_status_mask;
2137 */
2138 /* following add by Victor Yu. 09-02-2002 */
2139 *status = inb(info->base + UART_LSR);
2140 /* above add by Victor Yu. 09-02-2002 */
2141 } while (*status & UART_LSR_DR); 2110 } while (*status & UART_LSR_DR);
2142 2111
2143end_intr: /* add by Victor Yu. 09-02-2002 */ 2112end_intr:
2144 mxvar_log.rxcnt[info->port] += cnt; 2113 mxvar_log.rxcnt[port->tty->index] += cnt;
2145 info->mon_data.rxcnt += cnt; 2114 port->mon_data.rxcnt += cnt;
2146 info->mon_data.up_rxcnt += cnt; 2115 port->mon_data.up_rxcnt += cnt;
2147 spin_unlock_irqrestore(&info->slock, flags);
2148 2116
2117 /*
2118 * We are called from an interrupt context with &port->slock
2119 * being held. Drop it temporarily in order to prevent
2120 * recursive locking.
2121 */
2122 spin_unlock(&port->slock);
2149 tty_flip_buffer_push(tty); 2123 tty_flip_buffer_push(tty);
2124 spin_lock(&port->slock);
2150} 2125}
2151 2126
2152static void mxser_transmit_chars(struct mxser_struct *info) 2127static void mxser_transmit_chars(struct mxser_port *port)
2153{ 2128{
2154 int count, cnt; 2129 int count, cnt;
2155 unsigned long flags;
2156
2157 spin_lock_irqsave(&info->slock, flags);
2158 2130
2159 if (info->x_char) { 2131 if (port->x_char) {
2160 outb(info->x_char, info->base + UART_TX); 2132 outb(port->x_char, port->ioaddr + UART_TX);
2161 info->x_char = 0; 2133 port->x_char = 0;
2162 mxvar_log.txcnt[info->port]++; 2134 mxvar_log.txcnt[port->tty->index]++;
2163 info->mon_data.txcnt++; 2135 port->mon_data.txcnt++;
2164 info->mon_data.up_txcnt++; 2136 port->mon_data.up_txcnt++;
2165 2137 port->icount.tx++;
2166/* added by casper 1/11/2000 */
2167 info->icount.tx++;
2168/* */
2169 spin_unlock_irqrestore(&info->slock, flags);
2170 return; 2138 return;
2171 } 2139 }
2172 2140
2173 if (info->xmit_buf == 0) { 2141 if (port->xmit_buf == NULL)
2174 spin_unlock_irqrestore(&info->slock, flags);
2175 return; 2142 return;
2176 }
2177 2143
2178 if ((info->xmit_cnt <= 0) || info->tty->stopped || 2144 if ((port->xmit_cnt <= 0) || port->tty->stopped ||
2179 (info->tty->hw_stopped && 2145 (port->tty->hw_stopped &&
2180 (info->type != PORT_16550A) && 2146 (port->type != PORT_16550A) &&
2181 (!info->IsMoxaMustChipFlag))) { 2147 (!port->board->chip_flag))) {
2182 info->IER &= ~UART_IER_THRI; 2148 port->IER &= ~UART_IER_THRI;
2183 outb(info->IER, info->base + UART_IER); 2149 outb(port->IER, port->ioaddr + UART_IER);
2184 spin_unlock_irqrestore(&info->slock, flags);
2185 return; 2150 return;
2186 } 2151 }
2187 2152
2188 cnt = info->xmit_cnt; 2153 cnt = port->xmit_cnt;
2189 count = info->xmit_fifo_size; 2154 count = port->xmit_fifo_size;
2190 do { 2155 do {
2191 outb(info->xmit_buf[info->xmit_tail++], 2156 outb(port->xmit_buf[port->xmit_tail++],
2192 info->base + UART_TX); 2157 port->ioaddr + UART_TX);
2193 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE - 1); 2158 port->xmit_tail = port->xmit_tail & (SERIAL_XMIT_SIZE - 1);
2194 if (--info->xmit_cnt <= 0) 2159 if (--port->xmit_cnt <= 0)
2195 break; 2160 break;
2196 } while (--count > 0); 2161 } while (--count > 0);
2197 mxvar_log.txcnt[info->port] += (cnt - info->xmit_cnt); 2162 mxvar_log.txcnt[port->tty->index] += (cnt - port->xmit_cnt);
2198 2163
2199/* added by James 03-12-2004. */ 2164 port->mon_data.txcnt += (cnt - port->xmit_cnt);
2200 info->mon_data.txcnt += (cnt - info->xmit_cnt); 2165 port->mon_data.up_txcnt += (cnt - port->xmit_cnt);
2201 info->mon_data.up_txcnt += (cnt - info->xmit_cnt); 2166 port->icount.tx += (cnt - port->xmit_cnt);
2202/* (above) added by James. */
2203 2167
2204/* added by casper 1/11/2000 */ 2168 if (port->xmit_cnt < WAKEUP_CHARS)
2205 info->icount.tx += (cnt - info->xmit_cnt); 2169 tty_wakeup(port->tty);
2206/* */
2207 2170
2208 if (info->xmit_cnt < WAKEUP_CHARS) { 2171 if (port->xmit_cnt <= 0) {
2209 set_bit(MXSER_EVENT_TXLOW, &info->event); 2172 port->IER &= ~UART_IER_THRI;
2210 schedule_work(&info->tqueue); 2173 outb(port->IER, port->ioaddr + UART_IER);
2211 }
2212 if (info->xmit_cnt <= 0) {
2213 info->IER &= ~UART_IER_THRI;
2214 outb(info->IER, info->base + UART_IER);
2215 } 2174 }
2216 spin_unlock_irqrestore(&info->slock, flags);
2217} 2175}
2218 2176
2219static void mxser_check_modem_status(struct mxser_struct *info, int status) 2177/*
2178 * This is the serial driver's generic interrupt routine
2179 */
2180static irqreturn_t mxser_interrupt(int irq, void *dev_id)
2220{ 2181{
2221 /* update input line counters */ 2182 int status, iir, i;
2222 if (status & UART_MSR_TERI) 2183 struct mxser_board *brd = NULL;
2223 info->icount.rng++; 2184 struct mxser_port *port;
2224 if (status & UART_MSR_DDSR) 2185 int max, irqbits, bits, msr;
2225 info->icount.dsr++; 2186 unsigned int int_cnt, pass_counter = 0;
2226 if (status & UART_MSR_DDCD) 2187 int handled = IRQ_NONE;
2227 info->icount.dcd++;
2228 if (status & UART_MSR_DCTS)
2229 info->icount.cts++;
2230 info->mon_data.modem_status = status;
2231 wake_up_interruptible(&info->delta_msr_wait);
2232
2233 if ((info->flags & ASYNC_CHECK_CD) && (status & UART_MSR_DDCD)) {
2234 if (status & UART_MSR_DCD)
2235 wake_up_interruptible(&info->open_wait);
2236 schedule_work(&info->tqueue);
2237 }
2238
2239 if (info->flags & ASYNC_CTS_FLOW) {
2240 if (info->tty->hw_stopped) {
2241 if (status & UART_MSR_CTS) {
2242 info->tty->hw_stopped = 0;
2243 2188
2244 if ((info->type != PORT_16550A) && 2189 for (i = 0; i < MXSER_BOARDS; i++)
2245 (!info->IsMoxaMustChipFlag)) { 2190 if (dev_id == &mxser_boards[i]) {
2246 info->IER |= UART_IER_THRI; 2191 brd = dev_id;
2247 outb(info->IER, info->base + UART_IER); 2192 break;
2248 }
2249 set_bit(MXSER_EVENT_TXLOW, &info->event);
2250 schedule_work(&info->tqueue); }
2251 } else {
2252 if (!(status & UART_MSR_CTS)) {
2253 info->tty->hw_stopped = 1;
2254 if ((info->type != PORT_16550A) &&
2255 (!info->IsMoxaMustChipFlag)) {
2256 info->IER &= ~UART_IER_THRI;
2257 outb(info->IER, info->base + UART_IER);
2258 }
2259 }
2260 } 2193 }
2261 }
2262}
2263
2264static int mxser_block_til_ready(struct tty_struct *tty, struct file *filp, struct mxser_struct *info)
2265{
2266 DECLARE_WAITQUEUE(wait, current);
2267 int retval;
2268 int do_clocal = 0;
2269 unsigned long flags;
2270 2194
2271 /* 2195 if (i == MXSER_BOARDS)
2272 * If non-blocking mode is set, or the port is not enabled, 2196 goto irq_stop;
2273 * then make the check up front and then exit. 2197 if (brd == NULL)
2274 */ 2198 goto irq_stop;
2275 if ((filp->f_flags & O_NONBLOCK) || (tty->flags & (1 << TTY_IO_ERROR))) { 2199 max = brd->info->nports;
2276 info->flags |= ASYNC_NORMAL_ACTIVE; 2200 while (pass_counter++ < MXSER_ISR_PASS_LIMIT) {
2277 return 0; 2201 irqbits = inb(brd->vector) & brd->vector_mask;
2278 } 2202 if (irqbits == brd->vector_mask)
2203 break;
2279 2204
2280 if (tty->termios->c_cflag & CLOCAL) 2205 handled = IRQ_HANDLED;
2281 do_clocal = 1; 2206 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
2207 if (irqbits == brd->vector_mask)
2208 break;
2209 if (bits & irqbits)
2210 continue;
2211 port = &brd->ports[i];
2212
2213 int_cnt = 0;
2214 spin_lock(&port->slock);
2215 do {
2216 iir = inb(port->ioaddr + UART_IIR);
2217 if (iir & UART_IIR_NO_INT)
2218 break;
2219 iir &= MOXA_MUST_IIR_MASK;
2220 if (!port->tty ||
2221 (port->flags & ASYNC_CLOSING) ||
2222 !(port->flags &
2223 ASYNC_INITIALIZED)) {
2224 status = inb(port->ioaddr + UART_LSR);
2225 outb(0x27, port->ioaddr + UART_FCR);
2226 inb(port->ioaddr + UART_MSR);
2227 break;
2228 }
2282 2229
2283 /* 2230 status = inb(port->ioaddr + UART_LSR);
2284 * Block waiting for the carrier detect and the line to become 2231
2285 * free (i.e., not in use by the callout). While we are in 2232 if (status & UART_LSR_PE)
2286 * this loop, info->count is dropped by one, so that 2233 port->err_shadow |= NPPI_NOTIFY_PARITY;
2287 * mxser_close() knows when to free things. We restore it upon 2234 if (status & UART_LSR_FE)
2288 * exit, either normal or abnormal. 2235 port->err_shadow |= NPPI_NOTIFY_FRAMING;
2289 */ 2236 if (status & UART_LSR_OE)
2290 retval = 0; 2237 port->err_shadow |=
2291 add_wait_queue(&info->open_wait, &wait); 2238 NPPI_NOTIFY_HW_OVERRUN;
2239 if (status & UART_LSR_BI)
2240 port->err_shadow |= NPPI_NOTIFY_BREAK;
2241
2242 if (port->board->chip_flag) {
2243 if (iir == MOXA_MUST_IIR_GDA ||
2244 iir == MOXA_MUST_IIR_RDA ||
2245 iir == MOXA_MUST_IIR_RTO ||
2246 iir == MOXA_MUST_IIR_LSR)
2247 mxser_receive_chars(port,
2248 &status);
2292 2249
2293 spin_lock_irqsave(&info->slock, flags); 2250 } else {
2294 if (!tty_hung_up_p(filp)) 2251 status &= port->read_status_mask;
2295 info->count--; 2252 if (status & UART_LSR_DR)
2296 spin_unlock_irqrestore(&info->slock, flags); 2253 mxser_receive_chars(port,
2297 info->blocked_open++; 2254 &status);
2298 while (1) { 2255 }
2299 spin_lock_irqsave(&info->slock, flags); 2256 msr = inb(port->ioaddr + UART_MSR);
2300 outb(inb(info->base + UART_MCR) | 2257 if (msr & UART_MSR_ANY_DELTA)
2301 UART_MCR_DTR | UART_MCR_RTS, info->base + UART_MCR); 2258 mxser_check_modem_status(port, msr);
2302 spin_unlock_irqrestore(&info->slock, flags); 2259
2303 set_current_state(TASK_INTERRUPTIBLE); 2260 if (port->board->chip_flag) {
2304 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)) { 2261 if (iir == 0x02 && (status &
2305 if (info->flags & ASYNC_HUP_NOTIFY) 2262 UART_LSR_THRE))
2306 retval = -EAGAIN; 2263 mxser_transmit_chars(port);
2307 else 2264 } else {
2308 retval = -ERESTARTSYS; 2265 if (status & UART_LSR_THRE)
2309 break; 2266 mxser_transmit_chars(port);
2310 } 2267 }
2311 if (!(info->flags & ASYNC_CLOSING) && 2268 } while (int_cnt++ < MXSER_ISR_PASS_LIMIT);
2312 (do_clocal || 2269 spin_unlock(&port->slock);
2313 (inb(info->base + UART_MSR) & UART_MSR_DCD)))
2314 break;
2315 if (signal_pending(current)) {
2316 retval = -ERESTARTSYS;
2317 break;
2318 } 2270 }
2319 schedule();
2320 } 2271 }
2321 set_current_state(TASK_RUNNING);
2322 remove_wait_queue(&info->open_wait, &wait);
2323 if (!tty_hung_up_p(filp))
2324 info->count++;
2325 info->blocked_open--;
2326 if (retval)
2327 return retval;
2328 info->flags |= ASYNC_NORMAL_ACTIVE;
2329 return 0;
2330}
2331 2272
2332static int mxser_startup(struct mxser_struct *info) 2273irq_stop:
2333{ 2274 return handled;
2334 unsigned long page; 2275}
2335 unsigned long flags;
2336
2337 page = __get_free_page(GFP_KERNEL);
2338 if (!page)
2339 return -ENOMEM;
2340
2341 spin_lock_irqsave(&info->slock, flags);
2342
2343 if (info->flags & ASYNC_INITIALIZED) {
2344 free_page(page);
2345 spin_unlock_irqrestore(&info->slock, flags);
2346 return 0;
2347 }
2348 2276
2349 if (!info->base || !info->type) { 2277static const struct tty_operations mxser_ops = {
2350 if (info->tty) 2278 .open = mxser_open,
2351 set_bit(TTY_IO_ERROR, &info->tty->flags); 2279 .close = mxser_close,
2352 free_page(page); 2280 .write = mxser_write,
2353 spin_unlock_irqrestore(&info->slock, flags); 2281 .put_char = mxser_put_char,
2354 return 0; 2282 .flush_chars = mxser_flush_chars,
2355 } 2283 .write_room = mxser_write_room,
2356 if (info->xmit_buf) 2284 .chars_in_buffer = mxser_chars_in_buffer,
2357 free_page(page); 2285 .flush_buffer = mxser_flush_buffer,
2358 else 2286 .ioctl = mxser_ioctl,
2359 info->xmit_buf = (unsigned char *) page; 2287 .throttle = mxser_throttle,
2288 .unthrottle = mxser_unthrottle,
2289 .set_termios = mxser_set_termios,
2290 .stop = mxser_stop,
2291 .start = mxser_start,
2292 .hangup = mxser_hangup,
2293 .break_ctl = mxser_rs_break,
2294 .wait_until_sent = mxser_wait_until_sent,
2295 .tiocmget = mxser_tiocmget,
2296 .tiocmset = mxser_tiocmset,
2297};
2360 2298
2361 /* 2299/*
2362 * Clear the FIFO buffers and disable them 2300 * The MOXA Smartio/Industio serial driver boot-time initialization code!
2363 * (they will be reenabled in mxser_change_speed()) 2301 */
2364 */
2365 if (info->IsMoxaMustChipFlag)
2366 outb((UART_FCR_CLEAR_RCVR |
2367 UART_FCR_CLEAR_XMIT |
2368 MOXA_MUST_FCR_GDA_MODE_ENABLE), info->base + UART_FCR);
2369 else
2370 outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
2371 info->base + UART_FCR);
2372 2302
2373 /* 2303static void mxser_release_res(struct mxser_board *brd, struct pci_dev *pdev,
2374 * At this point there's no way the LSR could still be 0xFF; 2304 unsigned int irq)
2375 * if it is, then bail out, because there's likely no UART 2305{
2376 * here. 2306 if (irq)
2377 */ 2307 free_irq(brd->irq, brd);
2378 if (inb(info->base + UART_LSR) == 0xff) { 2308 if (pdev != NULL) { /* PCI */
2379 spin_unlock_irqrestore(&info->slock, flags); 2309#ifdef CONFIG_PCI
2380 if (capable(CAP_SYS_ADMIN)) { 2310 pci_release_region(pdev, 2);
2381 if (info->tty) 2311 pci_release_region(pdev, 3);
2382 set_bit(TTY_IO_ERROR, &info->tty->flags); 2312#endif
2383 return 0; 2313 } else {
2384 } else 2314 release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
2385 return -ENODEV; 2315 release_region(brd->vector, 1);
2386 } 2316 }
2387
2388 /*
2389 * Clear the interrupt registers.
2390 */
2391 (void) inb(info->base + UART_LSR);
2392 (void) inb(info->base + UART_RX);
2393 (void) inb(info->base + UART_IIR);
2394 (void) inb(info->base + UART_MSR);
2395
2396 /*
2397 * Now, initialize the UART
2398 */
2399 outb(UART_LCR_WLEN8, info->base + UART_LCR); /* reset DLAB */
2400 info->MCR = UART_MCR_DTR | UART_MCR_RTS;
2401 outb(info->MCR, info->base + UART_MCR);
2402
2403 /*
2404 * Finally, enable interrupts
2405 */
2406 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
2407 /* info->IER = UART_IER_RLSI | UART_IER_RDI; */
2408
2409 /* following add by Victor Yu. 08-30-2002 */
2410 if (info->IsMoxaMustChipFlag)
2411 info->IER |= MOXA_MUST_IER_EGDAI;
2412 /* above add by Victor Yu. 08-30-2002 */
2413 outb(info->IER, info->base + UART_IER); /* enable interrupts */
2414
2415 /*
2416 * And clear the interrupt registers again for luck.
2417 */
2418 (void) inb(info->base + UART_LSR);
2419 (void) inb(info->base + UART_RX);
2420 (void) inb(info->base + UART_IIR);
2421 (void) inb(info->base + UART_MSR);
2422
2423 if (info->tty)
2424 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2425 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2426
2427 /*
2428 * and set the speed of the serial port
2429 */
2430 spin_unlock_irqrestore(&info->slock, flags);
2431 mxser_change_speed(info, NULL);
2432
2433 info->flags |= ASYNC_INITIALIZED;
2434 return 0;
2435} 2317}
2436 2318
2437/* 2319static int __devinit mxser_initbrd(struct mxser_board *brd,
2438 * This routine will shutdown a serial port; interrupts maybe disabled, and 2320 struct pci_dev *pdev)
2439 * DTR is dropped if the hangup on close termio flag is on.
2440 */
2441static void mxser_shutdown(struct mxser_struct *info)
2442{ 2321{
2443 unsigned long flags; 2322 struct mxser_port *info;
2444 2323 unsigned int i;
2445 if (!(info->flags & ASYNC_INITIALIZED)) 2324 int retval;
2446 return;
2447
2448 spin_lock_irqsave(&info->slock, flags);
2449
2450 /*
2451 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
2452 * here so the queue might never be waken up
2453 */
2454 wake_up_interruptible(&info->delta_msr_wait);
2455
2456 /*
2457 * Free the IRQ, if necessary
2458 */
2459 if (info->xmit_buf) {
2460 free_page((unsigned long) info->xmit_buf);
2461 info->xmit_buf = NULL;
2462 }
2463 2325
2464 info->IER = 0; 2326 printk(KERN_INFO "max. baud rate = %d bps.\n", brd->ports[0].max_baud);
2465 outb(0x00, info->base + UART_IER);
2466 2327
2467 if (!info->tty || (info->tty->termios->c_cflag & HUPCL)) 2328 for (i = 0; i < brd->info->nports; i++) {
2468 info->MCR &= ~(UART_MCR_DTR | UART_MCR_RTS); 2329 info = &brd->ports[i];
2469 outb(info->MCR, info->base + UART_MCR); 2330 info->board = brd;
2331 info->stop_rx = 0;
2332 info->ldisc_stop_rx = 0;
2470 2333
2471 /* clear Rx/Tx FIFO's */ 2334 /* Enhance mode enabled here */
2472 /* following add by Victor Yu. 08-30-2002 */ 2335 if (brd->chip_flag != MOXA_OTHER_UART)
2473 if (info->IsMoxaMustChipFlag) 2336 ENABLE_MOXA_MUST_ENCHANCE_MODE(info->ioaddr);
2474 outb((UART_FCR_CLEAR_RCVR |
2475 UART_FCR_CLEAR_XMIT |
2476 MOXA_MUST_FCR_GDA_MODE_ENABLE), info->base + UART_FCR);
2477 else
2478 /* above add by Victor Yu. 08-30-2002 */
2479 outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
2480 info->base + UART_FCR);
2481 2337
2482 /* read data port to reset things */ 2338 info->flags = ASYNC_SHARE_IRQ;
2483 (void) inb(info->base + UART_RX); 2339 info->type = brd->uart_type;
2484 2340
2485 if (info->tty) 2341 process_txrx_fifo(info);
2486 set_bit(TTY_IO_ERROR, &info->tty->flags);
2487 2342
2488 info->flags &= ~ASYNC_INITIALIZED; 2343 info->custom_divisor = info->baud_base * 16;
2344 info->close_delay = 5 * HZ / 10;
2345 info->closing_wait = 30 * HZ;
2346 info->normal_termios = mxvar_sdriver->init_termios;
2347 init_waitqueue_head(&info->open_wait);
2348 init_waitqueue_head(&info->delta_msr_wait);
2349 memset(&info->mon_data, 0, sizeof(struct mxser_mon));
2350 info->err_shadow = 0;
2351 spin_lock_init(&info->slock);
2489 2352
2490 /* following add by Victor Yu. 09-23-2002 */ 2353 /* before set INT ISR, disable all int */
2491 if (info->IsMoxaMustChipFlag) 2354 outb(inb(info->ioaddr + UART_IER) & 0xf0,
2492 SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(info->base); 2355 info->ioaddr + UART_IER);
2493 /* above add by Victor Yu. 09-23-2002 */ 2356 }
2494 2357
2495 spin_unlock_irqrestore(&info->slock, flags); 2358 retval = request_irq(brd->irq, mxser_interrupt, IRQF_SHARED, "mxser",
2359 brd);
2360 if (retval) {
2361 printk(KERN_ERR "Board %s: Request irq failed, IRQ (%d) may "
2362 "conflict with another device.\n",
2363 brd->info->name, brd->irq);
2364 /* We hold resources, we need to release them. */
2365 mxser_release_res(brd, pdev, 0);
2366 }
2367 return retval;
2496} 2368}
2497 2369
2498/* 2370static int __init mxser_get_ISA_conf(int cap, struct mxser_board *brd)
2499 * This routine is called to set the UART divisor registers to match
2500 * the specified baud rate for a serial port.
2501 */
2502static int mxser_change_speed(struct mxser_struct *info, struct ktermios *old_termios)
2503{ 2371{
2504 unsigned cflag, cval, fcr; 2372 int id, i, bits;
2505 int ret = 0; 2373 unsigned short regs[16], irq;
2506 unsigned char status; 2374 unsigned char scratch, scratch2;
2507 long baud;
2508 unsigned long flags;
2509 2375
2510 if (!info->tty || !info->tty->termios) 2376 brd->chip_flag = MOXA_OTHER_UART;
2511 return ret;
2512 cflag = info->tty->termios->c_cflag;
2513 if (!(info->base))
2514 return ret;
2515 2377
2516#ifndef B921600 2378 id = mxser_read_register(cap, regs);
2517#define B921600 (B460800 +1) 2379 switch (id) {
2518#endif 2380 case C168_ASIC_ID:
2519 if (mxser_set_baud_method[info->port] == 0) { 2381 brd->info = &mxser_cards[0];
2520 baud = tty_get_baud_rate(info->tty);
2521 if (mxser_set_baud(info, baud) == -1) {
2522 /* Use previous rate on a failure */
2523 if (old_termios) {
2524 baud = tty_termios_baud_rate(old_termios);
2525 tty_encode_baud_rate(info->tty, baud, baud);
2526 }
2527 }
2528 }
2529
2530 /* byte size and parity */
2531 switch (cflag & CSIZE) {
2532 case CS5:
2533 cval = 0x00;
2534 break; 2382 break;
2535 case CS6: 2383 case C104_ASIC_ID:
2536 cval = 0x01; 2384 brd->info = &mxser_cards[1];
2537 break; 2385 break;
2538 case CS7: 2386 case CI104J_ASIC_ID:
2539 cval = 0x02; 2387 brd->info = &mxser_cards[2];
2540 break; 2388 break;
2541 case CS8: 2389 case C102_ASIC_ID:
2542 cval = 0x03; 2390 brd->info = &mxser_cards[5];
2391 break;
2392 case CI132_ASIC_ID:
2393 brd->info = &mxser_cards[6];
2394 break;
2395 case CI134_ASIC_ID:
2396 brd->info = &mxser_cards[7];
2543 break; 2397 break;
2544 default: 2398 default:
2545 cval = 0x00; 2399 return 0;
2546 break; /* too keep GCC shut... */
2547 } 2400 }
2548 if (cflag & CSTOPB)
2549 cval |= 0x04;
2550 if (cflag & PARENB)
2551 cval |= UART_LCR_PARITY;
2552 if (!(cflag & PARODD))
2553 cval |= UART_LCR_EPAR;
2554 if (cflag & CMSPAR)
2555 cval |= UART_LCR_SPAR;
2556 2401
2557 if ((info->type == PORT_8250) || (info->type == PORT_16450)) { 2402 irq = 0;
2558 if (info->IsMoxaMustChipFlag) { 2403 /* some ISA cards have 2 ports, but we want to see them as 4-port (why?)
2559 fcr = UART_FCR_ENABLE_FIFO; 2404 Flag-hack checks if configuration should be read as 2-port here. */
2560 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; 2405 if (brd->info->nports == 2 || (brd->info->flags & MXSER_HAS2)) {
2561 SET_MOXA_MUST_FIFO_VALUE(info); 2406 irq = regs[9] & 0xF000;
2562 } else 2407 irq = irq | (irq >> 4);
2563 fcr = 0; 2408 if (irq != (regs[9] & 0xFF00))
2564 } else { 2409 return MXSER_ERR_IRQ_CONFLIT;
2565 fcr = UART_FCR_ENABLE_FIFO; 2410 } else if (brd->info->nports == 4) {
2566 /* following add by Victor Yu. 08-30-2002 */ 2411 irq = regs[9] & 0xF000;
2567 if (info->IsMoxaMustChipFlag) { 2412 irq = irq | (irq >> 4);
2568 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; 2413 irq = irq | (irq >> 8);
2569 SET_MOXA_MUST_FIFO_VALUE(info); 2414 if (irq != regs[9])
2570 } else { 2415 return MXSER_ERR_IRQ_CONFLIT;
2571 /* above add by Victor Yu. 08-30-2002 */ 2416 } else if (brd->info->nports == 8) {
2572 switch (info->rx_trigger) { 2417 irq = regs[9] & 0xF000;
2573 case 1: 2418 irq = irq | (irq >> 4);
2574 fcr |= UART_FCR_TRIGGER_1; 2419 irq = irq | (irq >> 8);
2575 break; 2420 if ((irq != regs[9]) || (irq != regs[10]))
2576 case 4: 2421 return MXSER_ERR_IRQ_CONFLIT;
2577 fcr |= UART_FCR_TRIGGER_4;
2578 break;
2579 case 8:
2580 fcr |= UART_FCR_TRIGGER_8;
2581 break;
2582 default:
2583 fcr |= UART_FCR_TRIGGER_14;
2584 break;
2585 }
2586 }
2587 } 2422 }
2588 2423
2589 /* CTS flow control flag and modem status interrupts */ 2424 if (!irq)
2590 info->IER &= ~UART_IER_MSI; 2425 return MXSER_ERR_IRQ;
2591 info->MCR &= ~UART_MCR_AFE; 2426 brd->irq = ((int)(irq & 0xF000) >> 12);
2592 if (cflag & CRTSCTS) { 2427 for (i = 0; i < 8; i++)
2593 info->flags |= ASYNC_CTS_FLOW; 2428 brd->ports[i].ioaddr = (int) regs[i + 1] & 0xFFF8;
2594 info->IER |= UART_IER_MSI; 2429 if ((regs[12] & 0x80) == 0)
2595 if ((info->type == PORT_16550A) || (info->IsMoxaMustChipFlag)) { 2430 return MXSER_ERR_VECTOR;
2596 info->MCR |= UART_MCR_AFE; 2431 brd->vector = (int)regs[11]; /* interrupt vector */
2432 if (id == 1)
2433 brd->vector_mask = 0x00FF;
2434 else
2435 brd->vector_mask = 0x000F;
2436 for (i = 7, bits = 0x0100; i >= 0; i--, bits <<= 1) {
2437 if (regs[12] & bits) {
2438 brd->ports[i].baud_base = 921600;
2439 brd->ports[i].max_baud = 921600;
2597 } else { 2440 } else {
2598 status = inb(info->base + UART_MSR); 2441 brd->ports[i].baud_base = 115200;
2599 if (info->tty->hw_stopped) { 2442 brd->ports[i].max_baud = 115200;
2600 if (status & UART_MSR_CTS) {
2601 info->tty->hw_stopped = 0;
2602 if ((info->type != PORT_16550A) &&
2603 (!info->IsMoxaMustChipFlag)) {
2604 info->IER |= UART_IER_THRI;
2605 outb(info->IER, info->base + UART_IER);
2606 }
2607 set_bit(MXSER_EVENT_TXLOW, &info->event);
2608 schedule_work(&info->tqueue); }
2609 } else {
2610 if (!(status & UART_MSR_CTS)) {
2611 info->tty->hw_stopped = 1;
2612 if ((info->type != PORT_16550A) &&
2613 (!info->IsMoxaMustChipFlag)) {
2614 info->IER &= ~UART_IER_THRI;
2615 outb(info->IER, info->base + UART_IER);
2616 }
2617 }
2618 }
2619 } 2443 }
2620 } else {
2621 info->flags &= ~ASYNC_CTS_FLOW;
2622 }
2623 outb(info->MCR, info->base + UART_MCR);
2624 if (cflag & CLOCAL) {
2625 info->flags &= ~ASYNC_CHECK_CD;
2626 } else {
2627 info->flags |= ASYNC_CHECK_CD;
2628 info->IER |= UART_IER_MSI;
2629 } 2444 }
2630 outb(info->IER, info->base + UART_IER); 2445 scratch2 = inb(cap + UART_LCR) & (~UART_LCR_DLAB);
2631 2446 outb(scratch2 | UART_LCR_DLAB, cap + UART_LCR);
2632 /* 2447 outb(0, cap + UART_EFR); /* EFR is the same as FCR */
2633 * Set up parity check flag 2448 outb(scratch2, cap + UART_LCR);
2634 */ 2449 outb(UART_FCR_ENABLE_FIFO, cap + UART_FCR);
2635 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 2450 scratch = inb(cap + UART_IIR);
2636 if (I_INPCK(info->tty))
2637 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2638 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2639 info->read_status_mask |= UART_LSR_BI;
2640
2641 info->ignore_status_mask = 0;
2642 2451
2643 if (I_IGNBRK(info->tty)) { 2452 if (scratch & 0xC0)
2644 info->ignore_status_mask |= UART_LSR_BI; 2453 brd->uart_type = PORT_16550A;
2645 info->read_status_mask |= UART_LSR_BI; 2454 else
2646 /* 2455 brd->uart_type = PORT_16450;
2647 * If we're ignore parity and break indicators, ignore 2456 if (!request_region(brd->ports[0].ioaddr, 8 * brd->info->nports,
2648 * overruns too. (For real raw support). 2457 "mxser(IO)"))
2649 */ 2458 return MXSER_ERR_IOADDR;
2650 if (I_IGNPAR(info->tty)) { 2459 if (!request_region(brd->vector, 1, "mxser(vector)")) {
2651 info->ignore_status_mask |= 2460 release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
2652 UART_LSR_OE | 2461 return MXSER_ERR_VECTOR;
2653 UART_LSR_PE |
2654 UART_LSR_FE;
2655 info->read_status_mask |=
2656 UART_LSR_OE |
2657 UART_LSR_PE |
2658 UART_LSR_FE;
2659 }
2660 }
2661 /* following add by Victor Yu. 09-02-2002 */
2662 if (info->IsMoxaMustChipFlag) {
2663 spin_lock_irqsave(&info->slock, flags);
2664 SET_MOXA_MUST_XON1_VALUE(info->base, START_CHAR(info->tty));
2665 SET_MOXA_MUST_XOFF1_VALUE(info->base, STOP_CHAR(info->tty));
2666 if (I_IXON(info->tty)) {
2667 ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->base);
2668 } else {
2669 DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->base);
2670 }
2671 if (I_IXOFF(info->tty)) {
2672 ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(info->base);
2673 } else {
2674 DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(info->base);
2675 }
2676 /*
2677 if ( I_IXANY(info->tty) ) {
2678 info->MCR |= MOXA_MUST_MCR_XON_ANY;
2679 ENABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(info->base);
2680 } else {
2681 info->MCR &= ~MOXA_MUST_MCR_XON_ANY;
2682 DISABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(info->base);
2683 }
2684 */
2685 spin_unlock_irqrestore(&info->slock, flags);
2686 } 2462 }
2687 /* above add by Victor Yu. 09-02-2002 */ 2463 return brd->info->nports;
2688
2689
2690 outb(fcr, info->base + UART_FCR); /* set fcr */
2691 outb(cval, info->base + UART_LCR);
2692
2693 return ret;
2694} 2464}
2695 2465
2696 2466static int __devinit mxser_probe(struct pci_dev *pdev,
2697static int mxser_set_baud(struct mxser_struct *info, long newspd) 2467 const struct pci_device_id *ent)
2698{ 2468{
2699 int quot = 0; 2469#ifdef CONFIG_PCI
2700 unsigned char cval; 2470 struct mxser_board *brd;
2701 unsigned long flags; 2471 unsigned int i, j;
2702 unsigned int baud; 2472 unsigned long ioaddress;
2703 2473 int retval = -EINVAL;
2704 if (!info->tty || !info->tty->termios)
2705 return -1;
2706
2707 if (!(info->base))
2708 return -1;
2709 2474
2710 if (newspd > info->MaxCanSetBaudRate) 2475 for (i = 0; i < MXSER_BOARDS; i++)
2711 return -1; 2476 if (mxser_boards[i].info == NULL)
2477 break;
2712 2478
2713 info->realbaud = newspd; 2479 if (i >= MXSER_BOARDS) {
2714 if (newspd == 134) { 2480 printk(KERN_ERR "Too many Smartio/Industio family boards found "
2715 quot = (2 * info->baud_base / 269); 2481 "(maximum %d), board not configured\n", MXSER_BOARDS);
2716 tty_encode_baud_rate(info->tty, 134, 134); 2482 goto err;
2717 } else if (newspd) {
2718 quot = info->baud_base / newspd;
2719 if (quot == 0)
2720 quot = 1;
2721 baud = info->baud_base / quot;
2722 tty_encode_baud_rate(info->tty, baud, baud);
2723 } else {
2724 quot = 0;
2725 tty_encode_baud_rate(info->tty, 0, 0);
2726 } 2483 }
2727 2484
2728 info->timeout = ((info->xmit_fifo_size * HZ * 10 * quot) / info->baud_base); 2485 brd = &mxser_boards[i];
2729 info->timeout += HZ / 50; /* Add .02 seconds of slop */ 2486 brd->idx = i * MXSER_PORTS_PER_BOARD;
2487 printk(KERN_INFO "Found MOXA %s board (BusNo=%d, DevNo=%d)\n",
2488 mxser_cards[ent->driver_data].name,
2489 pdev->bus->number, PCI_SLOT(pdev->devfn));
2730 2490
2731 if (quot) { 2491 retval = pci_enable_device(pdev);
2732 spin_lock_irqsave(&info->slock, flags); 2492 if (retval) {
2733 info->MCR |= UART_MCR_DTR; 2493 printk(KERN_ERR "Moxa SmartI/O PCI enable fail !\n");
2734 outb(info->MCR, info->base + UART_MCR); 2494 goto err;
2735 spin_unlock_irqrestore(&info->slock, flags);
2736 } else {
2737 spin_lock_irqsave(&info->slock, flags);
2738 info->MCR &= ~UART_MCR_DTR;
2739 outb(info->MCR, info->base + UART_MCR);
2740 spin_unlock_irqrestore(&info->slock, flags);
2741 return 0;
2742 } 2495 }
2743 2496
2744 cval = inb(info->base + UART_LCR); 2497 /* io address */
2745 2498 ioaddress = pci_resource_start(pdev, 2);
2746 outb(cval | UART_LCR_DLAB, info->base + UART_LCR); /* set DLAB */ 2499 retval = pci_request_region(pdev, 2, "mxser(IO)");
2747 2500 if (retval)
2748 outb(quot & 0xff, info->base + UART_DLL); /* LS of divisor */ 2501 goto err;
2749 outb(quot >> 8, info->base + UART_DLM); /* MS of divisor */
2750 outb(cval, info->base + UART_LCR); /* reset DLAB */
2751
2752 2502
2753 return 0; 2503 brd->info = &mxser_cards[ent->driver_data];
2754} 2504 for (i = 0; i < brd->info->nports; i++)
2505 brd->ports[i].ioaddr = ioaddress + 8 * i;
2755 2506
2756/* 2507 /* vector */
2757 * ------------------------------------------------------------ 2508 ioaddress = pci_resource_start(pdev, 3);
2758 * friends of mxser_ioctl() 2509 retval = pci_request_region(pdev, 3, "mxser(vector)");
2759 * ------------------------------------------------------------ 2510 if (retval)
2760 */ 2511 goto err_relio;
2761static int mxser_get_serial_info(struct mxser_struct *info, struct serial_struct __user *retinfo) 2512 brd->vector = ioaddress;
2762{
2763 struct serial_struct tmp;
2764 2513
2765 if (!retinfo) 2514 /* irq */
2766 return -EFAULT; 2515 brd->irq = pdev->irq;
2767 memset(&tmp, 0, sizeof(tmp));
2768 tmp.type = info->type;
2769 tmp.line = info->port;
2770 tmp.port = info->base;
2771 tmp.irq = info->irq;
2772 tmp.flags = info->flags;
2773 tmp.baud_base = info->baud_base;
2774 tmp.close_delay = info->close_delay;
2775 tmp.closing_wait = info->closing_wait;
2776 tmp.custom_divisor = info->custom_divisor;
2777 tmp.hub6 = 0;
2778 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
2779 return -EFAULT;
2780 return 0;
2781}
2782 2516
2783static int mxser_set_serial_info(struct mxser_struct *info, struct serial_struct __user *new_info) 2517 brd->chip_flag = CheckIsMoxaMust(brd->ports[0].ioaddr);
2784{ 2518 brd->uart_type = PORT_16550A;
2785 struct serial_struct new_serial; 2519 brd->vector_mask = 0;
2786 unsigned int flags;
2787 int retval = 0;
2788 2520
2789 if (!new_info || !info->base) 2521 for (i = 0; i < brd->info->nports; i++) {
2790 return -EFAULT; 2522 for (j = 0; j < UART_INFO_NUM; j++) {
2791 if (copy_from_user(&new_serial, new_info, sizeof(new_serial))) 2523 if (Gpci_uart_info[j].type == brd->chip_flag) {
2792 return -EFAULT; 2524 brd->ports[i].max_baud =
2525 Gpci_uart_info[j].max_baud;
2793 2526
2794 if ((new_serial.irq != info->irq) || 2527 /* exception....CP-102 */
2795 (new_serial.port != info->base) || 2528 if (brd->info->flags & MXSER_HIGHBAUD)
2796 (new_serial.custom_divisor != info->custom_divisor) || 2529 brd->ports[i].max_baud = 921600;
2797 (new_serial.baud_base != info->baud_base)) 2530 break;
2798 return -EPERM; 2531 }
2532 }
2533 }
2799 2534
2800 flags = info->flags & ASYNC_SPD_MASK; 2535 if (brd->chip_flag == MOXA_MUST_MU860_HWID) {
2536 for (i = 0; i < brd->info->nports; i++) {
2537 if (i < 4)
2538 brd->ports[i].opmode_ioaddr = ioaddress + 4;
2539 else
2540 brd->ports[i].opmode_ioaddr = ioaddress + 0x0c;
2541 }
2542 outb(0, ioaddress + 4); /* default set to RS232 mode */
2543 outb(0, ioaddress + 0x0c); /* default set to RS232 mode */
2544 }
2801 2545
2802 if (!capable(CAP_SYS_ADMIN)) { 2546 for (i = 0; i < brd->info->nports; i++) {
2803 if ((new_serial.baud_base != info->baud_base) || 2547 brd->vector_mask |= (1 << i);
2804 (new_serial.close_delay != info->close_delay) || 2548 brd->ports[i].baud_base = 921600;
2805 ((new_serial.flags & ~ASYNC_USR_MASK) != (info->flags & ~ASYNC_USR_MASK)))
2806 return -EPERM;
2807 info->flags = ((info->flags & ~ASYNC_USR_MASK) |
2808 (new_serial.flags & ASYNC_USR_MASK));
2809 } else {
2810 /*
2811 * OK, past this point, all the error checking has been done.
2812 * At this point, we start making changes.....
2813 */
2814 info->flags = ((info->flags & ~ASYNC_FLAGS) |
2815 (new_serial.flags & ASYNC_FLAGS));
2816 info->close_delay = new_serial.close_delay * HZ / 100;
2817 info->closing_wait = new_serial.closing_wait * HZ / 100;
2818 info->tty->low_latency =
2819 (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
2820 info->tty->low_latency = 0; /* (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0; */
2821 } 2549 }
2822 2550
2823 /* added by casper, 3/17/2000, for mouse */ 2551 /* mxser_initbrd will hook ISR. */
2824 info->type = new_serial.type; 2552 retval = mxser_initbrd(brd, pdev);
2553 if (retval)
2554 goto err_null;
2825 2555
2826 process_txrx_fifo(info); 2556 for (i = 0; i < brd->info->nports; i++)
2557 tty_register_device(mxvar_sdriver, brd->idx + i, &pdev->dev);
2827 2558
2828 if (info->flags & ASYNC_INITIALIZED) { 2559 pci_set_drvdata(pdev, brd);
2829 if (flags != (info->flags & ASYNC_SPD_MASK)) { 2560
2830 mxser_change_speed(info, NULL); 2561 return 0;
2831 } 2562err_relio:
2832 } else { 2563 pci_release_region(pdev, 2);
2833 retval = mxser_startup(info); 2564err_null:
2834 } 2565 brd->info = NULL;
2566err:
2835 return retval; 2567 return retval;
2568#else
2569 return -ENODEV;
2570#endif
2836} 2571}
2837 2572
2838/* 2573static void __devexit mxser_remove(struct pci_dev *pdev)
2839 * mxser_get_lsr_info - get line status register info
2840 *
2841 * Purpose: Let user call ioctl() to get info when the UART physically
2842 * is emptied. On bus types like RS485, the transmitter must
2843 * release the bus after transmitting. This must be done when
2844 * the transmit shift register is empty, not be done when the
2845 * transmit holding register is empty. This functionality
2846 * allows an RS485 driver to be written in user space.
2847 */
2848static int mxser_get_lsr_info(struct mxser_struct *info, unsigned int __user *value)
2849{ 2574{
2850 unsigned char status; 2575 struct mxser_board *brd = pci_get_drvdata(pdev);
2851 unsigned int result; 2576 unsigned int i;
2852 unsigned long flags;
2853 2577
2854 spin_lock_irqsave(&info->slock, flags); 2578 for (i = 0; i < brd->info->nports; i++)
2855 status = inb(info->base + UART_LSR); 2579 tty_unregister_device(mxvar_sdriver, brd->idx + i);
2856 spin_unlock_irqrestore(&info->slock, flags);
2857 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
2858 return put_user(result, value);
2859}
2860
2861/*
2862 * This routine sends a break character out the serial port.
2863 */
2864static void mxser_send_break(struct mxser_struct *info, int duration)
2865{
2866 unsigned long flags;
2867 2580
2868 if (!info->base) 2581 mxser_release_res(brd, pdev, 1);
2869 return; 2582 brd->info = NULL;
2870 set_current_state(TASK_INTERRUPTIBLE);
2871 spin_lock_irqsave(&info->slock, flags);
2872 outb(inb(info->base + UART_LCR) | UART_LCR_SBC,
2873 info->base + UART_LCR);
2874 spin_unlock_irqrestore(&info->slock, flags);
2875 schedule_timeout(duration);
2876 spin_lock_irqsave(&info->slock, flags);
2877 outb(inb(info->base + UART_LCR) & ~UART_LCR_SBC,
2878 info->base + UART_LCR);
2879 spin_unlock_irqrestore(&info->slock, flags);
2880} 2583}
2881 2584
2882static int mxser_tiocmget(struct tty_struct *tty, struct file *file) 2585static struct pci_driver mxser_driver = {
2883{ 2586 .name = "mxser",
2884 struct mxser_struct *info = tty->driver_data; 2587 .id_table = mxser_pcibrds,
2885 unsigned char control, status; 2588 .probe = mxser_probe,
2886 unsigned long flags; 2589 .remove = __devexit_p(mxser_remove)
2590};
2887 2591
2592static int __init mxser_module_init(void)
2593{
2594 struct mxser_board *brd;
2595 unsigned long cap;
2596 unsigned int i, m, isaloop;
2597 int retval, b;
2888 2598
2889 if (tty->index == MXSER_PORTS) 2599 pr_debug("Loading module mxser ...\n");
2890 return -ENOIOCTLCMD;
2891 if (tty->flags & (1 << TTY_IO_ERROR))
2892 return -EIO;
2893 2600
2894 control = info->MCR; 2601 mxvar_sdriver = alloc_tty_driver(MXSER_PORTS + 1);
2602 if (!mxvar_sdriver)
2603 return -ENOMEM;
2895 2604
2896 spin_lock_irqsave(&info->slock, flags); 2605 printk(KERN_INFO "MOXA Smartio/Industio family driver version %s\n",
2897 status = inb(info->base + UART_MSR); 2606 MXSER_VERSION);
2898 if (status & UART_MSR_ANY_DELTA)
2899 mxser_check_modem_status(info, status);
2900 spin_unlock_irqrestore(&info->slock, flags);
2901 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
2902 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
2903 ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) |
2904 ((status & UART_MSR_RI) ? TIOCM_RNG : 0) |
2905 ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) |
2906 ((status & UART_MSR_CTS) ? TIOCM_CTS : 0);
2907}
2908 2607
2909static int mxser_tiocmset(struct tty_struct *tty, struct file *file, unsigned int set, unsigned int clear) 2608 /* Initialize the tty_driver structure */
2910{ 2609 mxvar_sdriver->owner = THIS_MODULE;
2911 struct mxser_struct *info = tty->driver_data; 2610 mxvar_sdriver->magic = TTY_DRIVER_MAGIC;
2912 unsigned long flags; 2611 mxvar_sdriver->name = "ttyMI";
2612 mxvar_sdriver->major = ttymajor;
2613 mxvar_sdriver->minor_start = 0;
2614 mxvar_sdriver->num = MXSER_PORTS + 1;
2615 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
2616 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
2617 mxvar_sdriver->init_termios = tty_std_termios;
2618 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
2619 mxvar_sdriver->flags = TTY_DRIVER_REAL_RAW|TTY_DRIVER_DYNAMIC_DEV;
2620 tty_set_operations(mxvar_sdriver, &mxser_ops);
2913 2621
2622 retval = tty_register_driver(mxvar_sdriver);
2623 if (retval) {
2624 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family "
2625 "tty driver !\n");
2626 goto err_put;
2627 }
2914 2628
2915 if (tty->index == MXSER_PORTS) 2629 mxvar_diagflag = 0;
2916 return -ENOIOCTLCMD;
2917 if (tty->flags & (1 << TTY_IO_ERROR))
2918 return -EIO;
2919 2630
2920 spin_lock_irqsave(&info->slock, flags); 2631 m = 0;
2632 /* Start finding ISA boards here */
2633 for (isaloop = 0; isaloop < 2; isaloop++)
2634 for (b = 0; b < MXSER_BOARDS && m < MXSER_BOARDS; b++) {
2635 if (!isaloop)
2636 cap = mxserBoardCAP[b]; /* predefined */
2637 else
2638 cap = ioaddr[b]; /* module param */
2921 2639
2922 if (set & TIOCM_RTS) 2640 if (!cap)
2923 info->MCR |= UART_MCR_RTS; 2641 continue;
2924 if (set & TIOCM_DTR)
2925 info->MCR |= UART_MCR_DTR;
2926 2642
2927 if (clear & TIOCM_RTS) 2643 brd = &mxser_boards[m];
2928 info->MCR &= ~UART_MCR_RTS; 2644 retval = mxser_get_ISA_conf(cap, brd);
2929 if (clear & TIOCM_DTR)
2930 info->MCR &= ~UART_MCR_DTR;
2931 2645
2932 outb(info->MCR, info->base + UART_MCR); 2646 if (retval != 0)
2933 spin_unlock_irqrestore(&info->slock, flags); 2647 printk(KERN_INFO "Found MOXA %s board "
2934 return 0; 2648 "(CAP=0x%x)\n",
2935} 2649 brd->info->name, ioaddr[b]);
2936 2650
2651 if (retval <= 0) {
2652 if (retval == MXSER_ERR_IRQ)
2653 printk(KERN_ERR "Invalid interrupt "
2654 "number, board not "
2655 "configured\n");
2656 else if (retval == MXSER_ERR_IRQ_CONFLIT)
2657 printk(KERN_ERR "Invalid interrupt "
2658 "number, board not "
2659 "configured\n");
2660 else if (retval == MXSER_ERR_VECTOR)
2661 printk(KERN_ERR "Invalid interrupt "
2662 "vector, board not "
2663 "configured\n");
2664 else if (retval == MXSER_ERR_IOADDR)
2665 printk(KERN_ERR "Invalid I/O address, "
2666 "board not configured\n");
2937 2667
2938static int mxser_read_register(int, unsigned short *); 2668 brd->info = NULL;
2939static int mxser_program_mode(int); 2669 continue;
2940static void mxser_normal_mode(int); 2670 }
2941 2671
2942static int mxser_get_ISA_conf(int cap, struct mxser_hwconf *hwconf) 2672 /* mxser_initbrd will hook ISR. */
2943{ 2673 if (mxser_initbrd(brd, NULL) < 0) {
2944 int id, i, bits; 2674 brd->info = NULL;
2945 unsigned short regs[16], irq; 2675 continue;
2946 unsigned char scratch, scratch2; 2676 }
2947 2677
2948 hwconf->IsMoxaMustChipFlag = MOXA_OTHER_UART; 2678 brd->idx = m * MXSER_PORTS_PER_BOARD;
2679 for (i = 0; i < brd->info->nports; i++)
2680 tty_register_device(mxvar_sdriver, brd->idx + i,
2681 NULL);
2949 2682
2950 id = mxser_read_register(cap, regs); 2683 m++;
2951 if (id == C168_ASIC_ID) { 2684 }
2952 hwconf->board_type = MXSER_BOARD_C168_ISA;
2953 hwconf->ports = 8;
2954 } else if (id == C104_ASIC_ID) {
2955 hwconf->board_type = MXSER_BOARD_C104_ISA;
2956 hwconf->ports = 4;
2957 } else if (id == C102_ASIC_ID) {
2958 hwconf->board_type = MXSER_BOARD_C102_ISA;
2959 hwconf->ports = 2;
2960 } else if (id == CI132_ASIC_ID) {
2961 hwconf->board_type = MXSER_BOARD_CI132;
2962 hwconf->ports = 2;
2963 } else if (id == CI134_ASIC_ID) {
2964 hwconf->board_type = MXSER_BOARD_CI134;
2965 hwconf->ports = 4;
2966 } else if (id == CI104J_ASIC_ID) {
2967 hwconf->board_type = MXSER_BOARD_CI104J;
2968 hwconf->ports = 4;
2969 } else
2970 return 0;
2971 2685
2972 irq = 0; 2686 retval = pci_register_driver(&mxser_driver);
2973 if (hwconf->ports == 2) { 2687 if (retval) {
2974 irq = regs[9] & 0xF000; 2688 printk(KERN_ERR "Can't register pci driver\n");
2975 irq = irq | (irq >> 4); 2689 if (!m) {
2976 if (irq != (regs[9] & 0xFF00)) 2690 retval = -ENODEV;
2977 return MXSER_ERR_IRQ_CONFLIT; 2691 goto err_unr;
2978 } else if (hwconf->ports == 4) { 2692 } /* else: we have some ISA cards under control */
2979 irq = regs[9] & 0xF000;
2980 irq = irq | (irq >> 4);
2981 irq = irq | (irq >> 8);
2982 if (irq != regs[9])
2983 return MXSER_ERR_IRQ_CONFLIT;
2984 } else if (hwconf->ports == 8) {
2985 irq = regs[9] & 0xF000;
2986 irq = irq | (irq >> 4);
2987 irq = irq | (irq >> 8);
2988 if ((irq != regs[9]) || (irq != regs[10]))
2989 return MXSER_ERR_IRQ_CONFLIT;
2990 } 2693 }
2991 2694
2992 if (!irq) 2695 pr_debug("Done.\n");
2993 return MXSER_ERR_IRQ;
2994 hwconf->irq = ((int)(irq & 0xF000) >> 12);
2995 for (i = 0; i < 8; i++)
2996 hwconf->ioaddr[i] = (int) regs[i + 1] & 0xFFF8;
2997 if ((regs[12] & 0x80) == 0)
2998 return MXSER_ERR_VECTOR;
2999 hwconf->vector = (int)regs[11]; /* interrupt vector */
3000 if (id == 1)
3001 hwconf->vector_mask = 0x00FF;
3002 else
3003 hwconf->vector_mask = 0x000F;
3004 for (i = 7, bits = 0x0100; i >= 0; i--, bits <<= 1) {
3005 if (regs[12] & bits) {
3006 hwconf->baud_base[i] = 921600;
3007 hwconf->MaxCanSetBaudRate[i] = 921600; /* add by Victor Yu. 09-04-2002 */
3008 } else {
3009 hwconf->baud_base[i] = 115200;
3010 hwconf->MaxCanSetBaudRate[i] = 115200; /* add by Victor Yu. 09-04-2002 */
3011 }
3012 }
3013 scratch2 = inb(cap + UART_LCR) & (~UART_LCR_DLAB);
3014 outb(scratch2 | UART_LCR_DLAB, cap + UART_LCR);
3015 outb(0, cap + UART_EFR); /* EFR is the same as FCR */
3016 outb(scratch2, cap + UART_LCR);
3017 outb(UART_FCR_ENABLE_FIFO, cap + UART_FCR);
3018 scratch = inb(cap + UART_IIR);
3019 2696
3020 if (scratch & 0xC0) 2697 return 0;
3021 hwconf->uart_type = PORT_16550A; 2698err_unr:
3022 else 2699 tty_unregister_driver(mxvar_sdriver);
3023 hwconf->uart_type = PORT_16450; 2700err_put:
3024 if (id == 1) 2701 put_tty_driver(mxvar_sdriver);
3025 hwconf->ports = 8; 2702 return retval;
3026 else
3027 hwconf->ports = 4;
3028 request_region(hwconf->ioaddr[0], 8 * hwconf->ports, "mxser(IO)");
3029 request_region(hwconf->vector, 1, "mxser(vector)");
3030 return hwconf->ports;
3031} 2703}
3032 2704
3033#define CHIP_SK 0x01 /* Serial Data Clock in Eprom */ 2705static void __exit mxser_module_exit(void)
3034#define CHIP_DO 0x02 /* Serial Data Output in Eprom */
3035#define CHIP_CS 0x04 /* Serial Chip Select in Eprom */
3036#define CHIP_DI 0x08 /* Serial Data Input in Eprom */
3037#define EN_CCMD 0x000 /* Chip's command register */
3038#define EN0_RSARLO 0x008 /* Remote start address reg 0 */
3039#define EN0_RSARHI 0x009 /* Remote start address reg 1 */
3040#define EN0_RCNTLO 0x00A /* Remote byte count reg WR */
3041#define EN0_RCNTHI 0x00B /* Remote byte count reg WR */
3042#define EN0_DCFG 0x00E /* Data configuration reg WR */
3043#define EN0_PORT 0x010 /* Rcv missed frame error counter RD */
3044#define ENC_PAGE0 0x000 /* Select page 0 of chip registers */
3045#define ENC_PAGE3 0x0C0 /* Select page 3 of chip registers */
3046static int mxser_read_register(int port, unsigned short *regs)
3047{ 2706{
3048 int i, k, value, id; 2707 unsigned int i, j;
3049 unsigned int j;
3050 2708
3051 id = mxser_program_mode(port); 2709 pr_debug("Unloading module mxser ...\n");
3052 if (id < 0)
3053 return id;
3054 for (i = 0; i < 14; i++) {
3055 k = (i & 0x3F) | 0x180;
3056 for (j = 0x100; j > 0; j >>= 1) {
3057 outb(CHIP_CS, port);
3058 if (k & j) {
3059 outb(CHIP_CS | CHIP_DO, port);
3060 outb(CHIP_CS | CHIP_DO | CHIP_SK, port); /* A? bit of read */
3061 } else {
3062 outb(CHIP_CS, port);
3063 outb(CHIP_CS | CHIP_SK, port); /* A? bit of read */
3064 }
3065 }
3066 (void)inb(port);
3067 value = 0;
3068 for (k = 0, j = 0x8000; k < 16; k++, j >>= 1) {
3069 outb(CHIP_CS, port);
3070 outb(CHIP_CS | CHIP_SK, port);
3071 if (inb(port) & CHIP_DI)
3072 value |= j;
3073 }
3074 regs[i] = value;
3075 outb(0, port);
3076 }
3077 mxser_normal_mode(port);
3078 return id;
3079}
3080 2710
3081static int mxser_program_mode(int port) 2711 pci_unregister_driver(&mxser_driver);
3082{
3083 int id, i, j, n;
3084 /* unsigned long flags; */
3085 2712
3086 spin_lock(&gm_lock); 2713 for (i = 0; i < MXSER_BOARDS; i++) /* ISA remains */
3087 outb(0, port); 2714 if (mxser_boards[i].info != NULL)
3088 outb(0, port); 2715 for (j = 0; j < mxser_boards[i].info->nports; j++)
3089 outb(0, port); 2716 tty_unregister_device(mxvar_sdriver,
3090 (void)inb(port); 2717 mxser_boards[i].idx + j);
3091 (void)inb(port); 2718 tty_unregister_driver(mxvar_sdriver);
3092 outb(0, port); 2719 put_tty_driver(mxvar_sdriver);
3093 (void)inb(port);
3094 /* restore_flags(flags); */
3095 spin_unlock(&gm_lock);
3096 2720
3097 id = inb(port + 1) & 0x1F; 2721 for (i = 0; i < MXSER_BOARDS; i++)
3098 if ((id != C168_ASIC_ID) && 2722 if (mxser_boards[i].info != NULL)
3099 (id != C104_ASIC_ID) && 2723 mxser_release_res(&mxser_boards[i], NULL, 1);
3100 (id != C102_ASIC_ID) &&
3101 (id != CI132_ASIC_ID) &&
3102 (id != CI134_ASIC_ID) &&
3103 (id != CI104J_ASIC_ID))
3104 return -1;
3105 for (i = 0, j = 0; i < 4; i++) {
3106 n = inb(port + 2);
3107 if (n == 'M') {
3108 j = 1;
3109 } else if ((j == 1) && (n == 1)) {
3110 j = 2;
3111 break;
3112 } else
3113 j = 0;
3114 }
3115 if (j != 2)
3116 id = -2;
3117 return id;
3118}
3119
3120static void mxser_normal_mode(int port)
3121{
3122 int i, n;
3123 2724
3124 outb(0xA5, port + 1); 2725 pr_debug("Done.\n");
3125 outb(0x80, port + 3);
3126 outb(12, port + 0); /* 9600 bps */
3127 outb(0, port + 1);
3128 outb(0x03, port + 3); /* 8 data bits */
3129 outb(0x13, port + 4); /* loop back mode */
3130 for (i = 0; i < 16; i++) {
3131 n = inb(port + 5);
3132 if ((n & 0x61) == 0x60)
3133 break;
3134 if ((n & 1) == 1)
3135 (void)inb(port);
3136 }
3137 outb(0x00, port + 4);
3138} 2726}
3139 2727
3140module_init(mxser_module_init); 2728module_init(mxser_module_init);
diff --git a/drivers/char/mxser.h b/drivers/char/mxser.h
index 1f4aa45ec004..844171115954 100644
--- a/drivers/char/mxser.h
+++ b/drivers/char/mxser.h
@@ -4,19 +4,17 @@
4/* 4/*
5 * Semi-public control interfaces 5 * Semi-public control interfaces
6 */ 6 */
7 7
8/* 8/*
9 * MOXA ioctls 9 * MOXA ioctls
10 */ 10 */
11 11
12#define MOXA 0x400 12#define MOXA 0x400
13#define MOXA_GETDATACOUNT (MOXA + 23) 13#define MOXA_GETDATACOUNT (MOXA + 23)
14#define MOXA_GET_CONF (MOXA + 35)
15#define MOXA_DIAGNOSE (MOXA + 50) 14#define MOXA_DIAGNOSE (MOXA + 50)
16#define MOXA_CHKPORTENABLE (MOXA + 60) 15#define MOXA_CHKPORTENABLE (MOXA + 60)
17#define MOXA_HighSpeedOn (MOXA + 61) 16#define MOXA_HighSpeedOn (MOXA + 61)
18#define MOXA_GET_MAJOR (MOXA + 63) 17#define MOXA_GET_MAJOR (MOXA + 63)
19#define MOXA_GET_CUMAJOR (MOXA + 64)
20#define MOXA_GETMSTATUS (MOXA + 65) 18#define MOXA_GETMSTATUS (MOXA + 65)
21#define MOXA_SET_OP_MODE (MOXA + 66) 19#define MOXA_SET_OP_MODE (MOXA + 66)
22#define MOXA_GET_OP_MODE (MOXA + 67) 20#define MOXA_GET_OP_MODE (MOXA + 67)
@@ -26,26 +24,14 @@
26#define RS422_MODE 2 24#define RS422_MODE 2
27#define RS485_4WIRE_MODE 3 25#define RS485_4WIRE_MODE 3
28#define OP_MODE_MASK 3 26#define OP_MODE_MASK 3
29// above add by Victor Yu. 01-05-2004
30
31#define TTY_THRESHOLD_THROTTLE 128
32
33#define HI_WATER 768
34
35// added by James. 03-11-2004.
36#define MOXA_SDS_GETICOUNTER (MOXA + 68)
37#define MOXA_SDS_RSTICOUNTER (MOXA + 69)
38// (above) added by James.
39 27
28#define MOXA_SDS_RSTICOUNTER (MOXA + 69)
40#define MOXA_ASPP_OQUEUE (MOXA + 70) 29#define MOXA_ASPP_OQUEUE (MOXA + 70)
41#define MOXA_ASPP_SETBAUD (MOXA + 71)
42#define MOXA_ASPP_GETBAUD (MOXA + 72)
43#define MOXA_ASPP_MON (MOXA + 73) 30#define MOXA_ASPP_MON (MOXA + 73)
44#define MOXA_ASPP_LSTATUS (MOXA + 74) 31#define MOXA_ASPP_LSTATUS (MOXA + 74)
45#define MOXA_ASPP_MON_EXT (MOXA + 75) 32#define MOXA_ASPP_MON_EXT (MOXA + 75)
46#define MOXA_SET_BAUD_METHOD (MOXA + 76) 33#define MOXA_SET_BAUD_METHOD (MOXA + 76)
47 34
48
49/* --------------------------------------------------- */ 35/* --------------------------------------------------- */
50 36
51#define NPPI_NOTIFY_PARITY 0x01 37#define NPPI_NOTIFY_PARITY 0x01
@@ -54,51 +40,46 @@
54#define NPPI_NOTIFY_SW_OVERRUN 0x08 40#define NPPI_NOTIFY_SW_OVERRUN 0x08
55#define NPPI_NOTIFY_BREAK 0x10 41#define NPPI_NOTIFY_BREAK 0x10
56 42
57#define NPPI_NOTIFY_CTSHOLD 0x01 // Tx hold by CTS low 43#define NPPI_NOTIFY_CTSHOLD 0x01 /* Tx hold by CTS low */
58#define NPPI_NOTIFY_DSRHOLD 0x02 // Tx hold by DSR low 44#define NPPI_NOTIFY_DSRHOLD 0x02 /* Tx hold by DSR low */
59#define NPPI_NOTIFY_XOFFHOLD 0x08 // Tx hold by Xoff received 45#define NPPI_NOTIFY_XOFFHOLD 0x08 /* Tx hold by Xoff received */
60#define NPPI_NOTIFY_XOFFXENT 0x10 // Xoff Sent 46#define NPPI_NOTIFY_XOFFXENT 0x10 /* Xoff Sent */
61 47
62//CheckIsMoxaMust return value 48/* follow just for Moxa Must chip define. */
63#define MOXA_OTHER_UART 0x00 49/* */
64#define MOXA_MUST_MU150_HWID 0x01 50/* when LCR register (offset 0x03) write following value, */
65#define MOXA_MUST_MU860_HWID 0x02 51/* the Must chip will enter enchance mode. And write value */
66 52/* on EFR (offset 0x02) bit 6,7 to change bank. */
67// follow just for Moxa Must chip define.
68//
69// when LCR register (offset 0x03) write following value,
70// the Must chip will enter enchance mode. And write value
71// on EFR (offset 0x02) bit 6,7 to change bank.
72#define MOXA_MUST_ENTER_ENCHANCE 0xBF 53#define MOXA_MUST_ENTER_ENCHANCE 0xBF
73 54
74// when enhance mode enable, access on general bank register 55/* when enhance mode enable, access on general bank register */
75#define MOXA_MUST_GDL_REGISTER 0x07 56#define MOXA_MUST_GDL_REGISTER 0x07
76#define MOXA_MUST_GDL_MASK 0x7F 57#define MOXA_MUST_GDL_MASK 0x7F
77#define MOXA_MUST_GDL_HAS_BAD_DATA 0x80 58#define MOXA_MUST_GDL_HAS_BAD_DATA 0x80
78 59
79#define MOXA_MUST_LSR_RERR 0x80 // error in receive FIFO 60#define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */
80// enchance register bank select and enchance mode setting register 61/* enchance register bank select and enchance mode setting register */
81// when LCR register equal to 0xBF 62/* when LCR register equal to 0xBF */
82#define MOXA_MUST_EFR_REGISTER 0x02 63#define MOXA_MUST_EFR_REGISTER 0x02
83// enchance mode enable 64/* enchance mode enable */
84#define MOXA_MUST_EFR_EFRB_ENABLE 0x10 65#define MOXA_MUST_EFR_EFRB_ENABLE 0x10
85// enchance reister bank set 0, 1, 2 66/* enchance reister bank set 0, 1, 2 */
86#define MOXA_MUST_EFR_BANK0 0x00 67#define MOXA_MUST_EFR_BANK0 0x00
87#define MOXA_MUST_EFR_BANK1 0x40 68#define MOXA_MUST_EFR_BANK1 0x40
88#define MOXA_MUST_EFR_BANK2 0x80 69#define MOXA_MUST_EFR_BANK2 0x80
89#define MOXA_MUST_EFR_BANK3 0xC0 70#define MOXA_MUST_EFR_BANK3 0xC0
90#define MOXA_MUST_EFR_BANK_MASK 0xC0 71#define MOXA_MUST_EFR_BANK_MASK 0xC0
91 72
92// set XON1 value register, when LCR=0xBF and change to bank0 73/* set XON1 value register, when LCR=0xBF and change to bank0 */
93#define MOXA_MUST_XON1_REGISTER 0x04 74#define MOXA_MUST_XON1_REGISTER 0x04
94 75
95// set XON2 value register, when LCR=0xBF and change to bank0 76/* set XON2 value register, when LCR=0xBF and change to bank0 */
96#define MOXA_MUST_XON2_REGISTER 0x05 77#define MOXA_MUST_XON2_REGISTER 0x05
97 78
98// set XOFF1 value register, when LCR=0xBF and change to bank0 79/* set XOFF1 value register, when LCR=0xBF and change to bank0 */
99#define MOXA_MUST_XOFF1_REGISTER 0x06 80#define MOXA_MUST_XOFF1_REGISTER 0x06
100 81
101// set XOFF2 value register, when LCR=0xBF and change to bank0 82/* set XOFF2 value register, when LCR=0xBF and change to bank0 */
102#define MOXA_MUST_XOFF2_REGISTER 0x07 83#define MOXA_MUST_XOFF2_REGISTER 0x07
103 84
104#define MOXA_MUST_RBRTL_REGISTER 0x04 85#define MOXA_MUST_RBRTL_REGISTER 0x04
@@ -110,32 +91,32 @@
110#define MOXA_MUST_ECR_REGISTER 0x06 91#define MOXA_MUST_ECR_REGISTER 0x06
111#define MOXA_MUST_CSR_REGISTER 0x07 92#define MOXA_MUST_CSR_REGISTER 0x07
112 93
113// good data mode enable 94/* good data mode enable */
114#define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 95#define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20
115// only good data put into RxFIFO 96/* only good data put into RxFIFO */
116#define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 97#define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10
117 98
118// enable CTS interrupt 99/* enable CTS interrupt */
119#define MOXA_MUST_IER_ECTSI 0x80 100#define MOXA_MUST_IER_ECTSI 0x80
120// enable RTS interrupt 101/* enable RTS interrupt */
121#define MOXA_MUST_IER_ERTSI 0x40 102#define MOXA_MUST_IER_ERTSI 0x40
122// enable Xon/Xoff interrupt 103/* enable Xon/Xoff interrupt */
123#define MOXA_MUST_IER_XINT 0x20 104#define MOXA_MUST_IER_XINT 0x20
124// enable GDA interrupt 105/* enable GDA interrupt */
125#define MOXA_MUST_IER_EGDAI 0x10 106#define MOXA_MUST_IER_EGDAI 0x10
126 107
127#define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI) 108#define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI)
128 109
129// GDA interrupt pending 110/* GDA interrupt pending */
130#define MOXA_MUST_IIR_GDA 0x1C 111#define MOXA_MUST_IIR_GDA 0x1C
131#define MOXA_MUST_IIR_RDA 0x04 112#define MOXA_MUST_IIR_RDA 0x04
132#define MOXA_MUST_IIR_RTO 0x0C 113#define MOXA_MUST_IIR_RTO 0x0C
133#define MOXA_MUST_IIR_LSR 0x06 114#define MOXA_MUST_IIR_LSR 0x06
134 115
135// recieved Xon/Xoff or specical interrupt pending 116/* recieved Xon/Xoff or specical interrupt pending */
136#define MOXA_MUST_IIR_XSC 0x10 117#define MOXA_MUST_IIR_XSC 0x10
137 118
138// RTS/CTS change state interrupt pending 119/* RTS/CTS change state interrupt pending */
139#define MOXA_MUST_IIR_RTSCTS 0x20 120#define MOXA_MUST_IIR_RTSCTS 0x20
140#define MOXA_MUST_IIR_MASK 0x3E 121#define MOXA_MUST_IIR_MASK 0x3E
141 122
@@ -143,299 +124,164 @@
143#define MOXA_MUST_MCR_XON_ANY 0x80 124#define MOXA_MUST_MCR_XON_ANY 0x80
144#define MOXA_MUST_MCR_TX_XON 0x08 125#define MOXA_MUST_MCR_TX_XON 0x08
145 126
146 127/* software flow control on chip mask value */
147// software flow control on chip mask value
148#define MOXA_MUST_EFR_SF_MASK 0x0F 128#define MOXA_MUST_EFR_SF_MASK 0x0F
149// send Xon1/Xoff1 129/* send Xon1/Xoff1 */
150#define MOXA_MUST_EFR_SF_TX1 0x08 130#define MOXA_MUST_EFR_SF_TX1 0x08
151// send Xon2/Xoff2 131/* send Xon2/Xoff2 */
152#define MOXA_MUST_EFR_SF_TX2 0x04 132#define MOXA_MUST_EFR_SF_TX2 0x04
153// send Xon1,Xon2/Xoff1,Xoff2 133/* send Xon1,Xon2/Xoff1,Xoff2 */
154#define MOXA_MUST_EFR_SF_TX12 0x0C 134#define MOXA_MUST_EFR_SF_TX12 0x0C
155// don't send Xon/Xoff 135/* don't send Xon/Xoff */
156#define MOXA_MUST_EFR_SF_TX_NO 0x00 136#define MOXA_MUST_EFR_SF_TX_NO 0x00
157// Tx software flow control mask 137/* Tx software flow control mask */
158#define MOXA_MUST_EFR_SF_TX_MASK 0x0C 138#define MOXA_MUST_EFR_SF_TX_MASK 0x0C
159// don't receive Xon/Xoff 139/* don't receive Xon/Xoff */
160#define MOXA_MUST_EFR_SF_RX_NO 0x00 140#define MOXA_MUST_EFR_SF_RX_NO 0x00
161// receive Xon1/Xoff1 141/* receive Xon1/Xoff1 */
162#define MOXA_MUST_EFR_SF_RX1 0x02 142#define MOXA_MUST_EFR_SF_RX1 0x02
163// receive Xon2/Xoff2 143/* receive Xon2/Xoff2 */
164#define MOXA_MUST_EFR_SF_RX2 0x01 144#define MOXA_MUST_EFR_SF_RX2 0x01
165// receive Xon1,Xon2/Xoff1,Xoff2 145/* receive Xon1,Xon2/Xoff1,Xoff2 */
166#define MOXA_MUST_EFR_SF_RX12 0x03 146#define MOXA_MUST_EFR_SF_RX12 0x03
167// Rx software flow control mask 147/* Rx software flow control mask */
168#define MOXA_MUST_EFR_SF_RX_MASK 0x03 148#define MOXA_MUST_EFR_SF_RX_MASK 0x03
169 149
170//#define MOXA_MUST_MIN_XOFFLIMIT 66 150#define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \
171//#define MOXA_MUST_MIN_XONLIMIT 20 151 u8 __oldlcr, __efr; \
172//#define ID1_RX_TRIG 120 152 __oldlcr = inb((baseio)+UART_LCR); \
173
174
175#define CHECK_MOXA_MUST_XOFFLIMIT(info) { \
176 if ( (info)->IsMoxaMustChipFlag && \
177 (info)->HandFlow.XoffLimit < MOXA_MUST_MIN_XOFFLIMIT ) { \
178 (info)->HandFlow.XoffLimit = MOXA_MUST_MIN_XOFFLIMIT; \
179 (info)->HandFlow.XonLimit = MOXA_MUST_MIN_XONLIMIT; \
180 } \
181}
182
183#define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) { \
184 u8 __oldlcr, __efr; \
185 __oldlcr = inb((baseio)+UART_LCR); \
186 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 153 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
187 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 154 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
188 __efr |= MOXA_MUST_EFR_EFRB_ENABLE; \ 155 __efr |= MOXA_MUST_EFR_EFRB_ENABLE; \
189 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 156 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
190 outb(__oldlcr, (baseio)+UART_LCR); \ 157 outb(__oldlcr, (baseio)+UART_LCR); \
191} 158} while (0)
192 159
193#define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) { \ 160#define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \
194 u8 __oldlcr, __efr; \ 161 u8 __oldlcr, __efr; \
195 __oldlcr = inb((baseio)+UART_LCR); \ 162 __oldlcr = inb((baseio)+UART_LCR); \
196 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 163 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
197 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 164 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
198 __efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; \ 165 __efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; \
199 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 166 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
200 outb(__oldlcr, (baseio)+UART_LCR); \ 167 outb(__oldlcr, (baseio)+UART_LCR); \
201} 168} while (0)
202 169
203#define SET_MOXA_MUST_XON1_VALUE(baseio, Value) { \ 170#define SET_MOXA_MUST_XON1_VALUE(baseio, Value) do { \
204 u8 __oldlcr, __efr; \ 171 u8 __oldlcr, __efr; \
205 __oldlcr = inb((baseio)+UART_LCR); \ 172 __oldlcr = inb((baseio)+UART_LCR); \
206 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 173 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
207 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 174 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
208 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ 175 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
209 __efr |= MOXA_MUST_EFR_BANK0; \ 176 __efr |= MOXA_MUST_EFR_BANK0; \
210 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 177 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
211 outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER); \ 178 outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER); \
212 outb(__oldlcr, (baseio)+UART_LCR); \ 179 outb(__oldlcr, (baseio)+UART_LCR); \
213} 180} while (0)
214 181
215#define SET_MOXA_MUST_XON2_VALUE(baseio, Value) { \ 182#define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) do { \
216 u8 __oldlcr, __efr; \ 183 u8 __oldlcr, __efr; \
217 __oldlcr = inb((baseio)+UART_LCR); \ 184 __oldlcr = inb((baseio)+UART_LCR); \
218 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 185 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
219 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 186 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
220 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ 187 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
221 __efr |= MOXA_MUST_EFR_BANK0; \ 188 __efr |= MOXA_MUST_EFR_BANK0; \
222 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 189 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
223 outb((u8)(Value), (baseio)+MOXA_MUST_XON2_REGISTER); \
224 outb(__oldlcr, (baseio)+UART_LCR); \
225}
226
227#define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) { \
228 u8 __oldlcr, __efr; \
229 __oldlcr = inb((baseio)+UART_LCR); \
230 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
231 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
232 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
233 __efr |= MOXA_MUST_EFR_BANK0; \
234 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
235 outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER); \ 190 outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER); \
236 outb(__oldlcr, (baseio)+UART_LCR); \ 191 outb(__oldlcr, (baseio)+UART_LCR); \
237} 192} while (0)
238 193
239#define SET_MOXA_MUST_XOFF2_VALUE(baseio, Value) { \ 194#define SET_MOXA_MUST_FIFO_VALUE(info) do { \
240 u8 __oldlcr, __efr; \ 195 u8 __oldlcr, __efr; \
241 __oldlcr = inb((baseio)+UART_LCR); \ 196 __oldlcr = inb((info)->ioaddr+UART_LCR); \
242 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 197 outb(MOXA_MUST_ENTER_ENCHANCE, (info)->ioaddr+UART_LCR);\
243 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 198 __efr = inb((info)->ioaddr+MOXA_MUST_EFR_REGISTER); \
244 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ 199 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
245 __efr |= MOXA_MUST_EFR_BANK0; \ 200 __efr |= MOXA_MUST_EFR_BANK1; \
246 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 201 outb(__efr, (info)->ioaddr+MOXA_MUST_EFR_REGISTER); \
247 outb((u8)(Value), (baseio)+MOXA_MUST_XOFF2_REGISTER); \ 202 outb((u8)((info)->rx_high_water), (info)->ioaddr+ \
248 outb(__oldlcr, (baseio)+UART_LCR); \ 203 MOXA_MUST_RBRTH_REGISTER); \
249} 204 outb((u8)((info)->rx_trigger), (info)->ioaddr+ \
250 205 MOXA_MUST_RBRTI_REGISTER); \
251#define SET_MOXA_MUST_RBRTL_VALUE(baseio, Value) { \ 206 outb((u8)((info)->rx_low_water), (info)->ioaddr+ \
252 u8 __oldlcr, __efr; \ 207 MOXA_MUST_RBRTL_REGISTER); \
253 __oldlcr = inb((baseio)+UART_LCR); \ 208 outb(__oldlcr, (info)->ioaddr+UART_LCR); \
254 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 209} while (0)
255 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 210
256 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ 211#define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) do { \
257 __efr |= MOXA_MUST_EFR_BANK1; \ 212 u8 __oldlcr, __efr; \
258 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 213 __oldlcr = inb((baseio)+UART_LCR); \
259 outb((u8)(Value), (baseio)+MOXA_MUST_RBRTL_REGISTER); \
260 outb(__oldlcr, (baseio)+UART_LCR); \
261}
262
263#define SET_MOXA_MUST_RBRTH_VALUE(baseio, Value) { \
264 u8 __oldlcr, __efr; \
265 __oldlcr = inb((baseio)+UART_LCR); \
266 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
267 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
268 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
269 __efr |= MOXA_MUST_EFR_BANK1; \
270 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
271 outb((u8)(Value), (baseio)+MOXA_MUST_RBRTH_REGISTER); \
272 outb(__oldlcr, (baseio)+UART_LCR); \
273}
274
275#define SET_MOXA_MUST_RBRTI_VALUE(baseio, Value) { \
276 u8 __oldlcr, __efr; \
277 __oldlcr = inb((baseio)+UART_LCR); \
278 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 214 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
279 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 215 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
280 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ 216 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
281 __efr |= MOXA_MUST_EFR_BANK1; \ 217 __efr |= MOXA_MUST_EFR_BANK2; \
282 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 218 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
283 outb((u8)(Value), (baseio)+MOXA_MUST_RBRTI_REGISTER); \
284 outb(__oldlcr, (baseio)+UART_LCR); \
285}
286
287#define SET_MOXA_MUST_THRTL_VALUE(baseio, Value) { \
288 u8 __oldlcr, __efr; \
289 __oldlcr = inb((baseio)+UART_LCR); \
290 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
291 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
292 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
293 __efr |= MOXA_MUST_EFR_BANK1; \
294 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
295 outb((u8)(Value), (baseio)+MOXA_MUST_THRTL_REGISTER); \
296 outb(__oldlcr, (baseio)+UART_LCR); \
297}
298
299//#define MOXA_MUST_RBRL_VALUE 4
300#define SET_MOXA_MUST_FIFO_VALUE(info) { \
301 u8 __oldlcr, __efr; \
302 __oldlcr = inb((info)->base+UART_LCR); \
303 outb(MOXA_MUST_ENTER_ENCHANCE, (info)->base+UART_LCR); \
304 __efr = inb((info)->base+MOXA_MUST_EFR_REGISTER); \
305 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
306 __efr |= MOXA_MUST_EFR_BANK1; \
307 outb(__efr, (info)->base+MOXA_MUST_EFR_REGISTER); \
308 outb((u8)((info)->rx_high_water), (info)->base+MOXA_MUST_RBRTH_REGISTER); \
309 outb((u8)((info)->rx_trigger), (info)->base+MOXA_MUST_RBRTI_REGISTER); \
310 outb((u8)((info)->rx_low_water), (info)->base+MOXA_MUST_RBRTL_REGISTER); \
311 outb(__oldlcr, (info)->base+UART_LCR); \
312}
313
314
315
316#define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) { \
317 u8 __oldlcr, __efr; \
318 __oldlcr = inb((baseio)+UART_LCR); \
319 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
320 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
321 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
322 __efr |= MOXA_MUST_EFR_BANK2; \
323 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
324 outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER); \ 219 outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER); \
325 outb(__oldlcr, (baseio)+UART_LCR); \ 220 outb(__oldlcr, (baseio)+UART_LCR); \
326} 221} while (0)
327 222
328#define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) { \ 223#define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) do { \
329 u8 __oldlcr, __efr; \ 224 u8 __oldlcr, __efr; \
330 __oldlcr = inb((baseio)+UART_LCR); \ 225 __oldlcr = inb((baseio)+UART_LCR); \
331 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
332 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
333 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
334 __efr |= MOXA_MUST_EFR_BANK2; \
335 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
336 *pId = inb((baseio)+MOXA_MUST_HWID_REGISTER); \
337 outb(__oldlcr, (baseio)+UART_LCR); \
338}
339
340#define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) { \
341 u8 __oldlcr, __efr; \
342 __oldlcr = inb((baseio)+UART_LCR); \
343 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
344 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
345 __efr &= ~MOXA_MUST_EFR_SF_MASK; \
346 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
347 outb(__oldlcr, (baseio)+UART_LCR); \
348}
349
350#define SET_MOXA_MUST_JUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \
351 u8 __oldlcr, __efr; \
352 __oldlcr = inb((baseio)+UART_LCR); \
353 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
354 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
355 __efr &= ~MOXA_MUST_EFR_SF_MASK; \
356 __efr |= MOXA_MUST_EFR_SF_TX1; \
357 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
358 outb(__oldlcr, (baseio)+UART_LCR); \
359}
360
361#define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \
362 u8 __oldlcr, __efr; \
363 __oldlcr = inb((baseio)+UART_LCR); \
364 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 226 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
365 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 227 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
366 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \ 228 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
367 __efr |= MOXA_MUST_EFR_SF_TX1; \ 229 __efr |= MOXA_MUST_EFR_BANK2; \
368 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 230 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
369 outb(__oldlcr, (baseio)+UART_LCR); \ 231 *pId = inb((baseio)+MOXA_MUST_HWID_REGISTER); \
370} 232 outb(__oldlcr, (baseio)+UART_LCR); \
371 233} while (0)
372#define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \ 234
373 u8 __oldlcr, __efr; \ 235#define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) do { \
374 __oldlcr = inb((baseio)+UART_LCR); \ 236 u8 __oldlcr, __efr; \
237 __oldlcr = inb((baseio)+UART_LCR); \
375 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 238 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
376 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 239 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
377 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \ 240 __efr &= ~MOXA_MUST_EFR_SF_MASK; \
378 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 241 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
379 outb(__oldlcr, (baseio)+UART_LCR); \ 242 outb(__oldlcr, (baseio)+UART_LCR); \
380} 243} while (0)
381 244
382#define SET_MOXA_MUST_JUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \ 245#define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \
383 u8 __oldlcr, __efr; \ 246 u8 __oldlcr, __efr; \
384 __oldlcr = inb((baseio)+UART_LCR); \ 247 __oldlcr = inb((baseio)+UART_LCR); \
385 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 248 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
386 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 249 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
387 __efr &= ~MOXA_MUST_EFR_SF_MASK; \ 250 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
388 __efr |= MOXA_MUST_EFR_SF_RX1; \ 251 __efr |= MOXA_MUST_EFR_SF_TX1; \
389 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 252 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
390 outb(__oldlcr, (baseio)+UART_LCR); \ 253 outb(__oldlcr, (baseio)+UART_LCR); \
391} 254} while (0)
392 255
393#define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \ 256#define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \
394 u8 __oldlcr, __efr; \ 257 u8 __oldlcr, __efr; \
395 __oldlcr = inb((baseio)+UART_LCR); \ 258 __oldlcr = inb((baseio)+UART_LCR); \
396 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 259 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
397 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 260 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
398 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \ 261 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
399 __efr |= MOXA_MUST_EFR_SF_RX1; \ 262 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
400 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 263 outb(__oldlcr, (baseio)+UART_LCR); \
401 outb(__oldlcr, (baseio)+UART_LCR); \ 264} while (0)
402} 265
403 266#define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \
404#define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \ 267 u8 __oldlcr, __efr; \
405 u8 __oldlcr, __efr; \ 268 __oldlcr = inb((baseio)+UART_LCR); \
406 __oldlcr = inb((baseio)+UART_LCR); \
407 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 269 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
408 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 270 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
409 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \ 271 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
410 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 272 __efr |= MOXA_MUST_EFR_SF_RX1; \
411 outb(__oldlcr, (baseio)+UART_LCR); \ 273 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
412} 274 outb(__oldlcr, (baseio)+UART_LCR); \
413 275} while (0)
414#define ENABLE_MOXA_MUST_TX_RX_SOFTWARE_FLOW_CONTROL(baseio) { \ 276
415 u8 __oldlcr, __efr; \ 277#define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \
416 __oldlcr = inb((baseio)+UART_LCR); \ 278 u8 __oldlcr, __efr; \
279 __oldlcr = inb((baseio)+UART_LCR); \
417 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 280 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
418 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 281 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
419 __efr &= ~MOXA_MUST_EFR_SF_MASK; \ 282 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
420 __efr |= (MOXA_MUST_EFR_SF_RX1|MOXA_MUST_EFR_SF_TX1); \ 283 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
421 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 284 outb(__oldlcr, (baseio)+UART_LCR); \
422 outb(__oldlcr, (baseio)+UART_LCR); \ 285} while (0)
423}
424
425#define ENABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(baseio) { \
426 u8 __oldmcr; \
427 __oldmcr = inb((baseio)+UART_MCR); \
428 __oldmcr |= MOXA_MUST_MCR_XON_ANY; \
429 outb(__oldmcr, (baseio)+UART_MCR); \
430}
431
432#define DISABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(baseio) { \
433 u8 __oldmcr; \
434 __oldmcr = inb((baseio)+UART_MCR); \
435 __oldmcr &= ~MOXA_MUST_MCR_XON_ANY; \
436 outb(__oldmcr, (baseio)+UART_MCR); \
437}
438
439#define READ_MOXA_MUST_GDL(baseio) inb((baseio)+MOXA_MUST_GDL_REGISTER)
440 286
441#endif 287#endif
diff --git a/drivers/char/mxser_new.c b/drivers/char/mxser_new.c
deleted file mode 100644
index 5c5d246a4261..000000000000
--- a/drivers/char/mxser_new.c
+++ /dev/null
@@ -1,2729 +0,0 @@
1/*
2 * mxser.c -- MOXA Smartio/Industio family multiport serial driver.
3 *
4 * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com.tw).
5 * Copyright (C) 2006-2007 Jiri Slaby <jirislaby@gmail.com>
6 *
7 * This code is loosely based on the 1.8 moxa driver which is based on
8 * Linux serial driver, written by Linus Torvalds, Theodore T'so and
9 * others.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
17 * <alan@redhat.com>. The original 1.8 code is available on www.moxa.com.
18 * - Fixed x86_64 cleanness
19 * - Fixed sleep with spinlock held in mxser_send_break
20 */
21
22#include <linux/module.h>
23#include <linux/errno.h>
24#include <linux/signal.h>
25#include <linux/sched.h>
26#include <linux/timer.h>
27#include <linux/interrupt.h>
28#include <linux/tty.h>
29#include <linux/tty_flip.h>
30#include <linux/serial.h>
31#include <linux/serial_reg.h>
32#include <linux/major.h>
33#include <linux/string.h>
34#include <linux/fcntl.h>
35#include <linux/ptrace.h>
36#include <linux/gfp.h>
37#include <linux/ioport.h>
38#include <linux/mm.h>
39#include <linux/delay.h>
40#include <linux/pci.h>
41#include <linux/bitops.h>
42
43#include <asm/system.h>
44#include <asm/io.h>
45#include <asm/irq.h>
46#include <asm/uaccess.h>
47
48#include "mxser_new.h"
49
50#define MXSER_VERSION "2.0.2" /* 1.10 */
51#define MXSERMAJOR 174
52#define MXSERCUMAJOR 175
53
54#define MXSER_BOARDS 4 /* Max. boards */
55#define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */
56#define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
57#define MXSER_ISR_PASS_LIMIT 100
58
59#define MXSER_ERR_IOADDR -1
60#define MXSER_ERR_IRQ -2
61#define MXSER_ERR_IRQ_CONFLIT -3
62#define MXSER_ERR_VECTOR -4
63
64/*CheckIsMoxaMust return value*/
65#define MOXA_OTHER_UART 0x00
66#define MOXA_MUST_MU150_HWID 0x01
67#define MOXA_MUST_MU860_HWID 0x02
68
69#define WAKEUP_CHARS 256
70
71#define UART_MCR_AFE 0x20
72#define UART_LSR_SPECIAL 0x1E
73
74#define PCI_DEVICE_ID_CB108 0x1080
75#define PCI_DEVICE_ID_CB114 0x1142
76#define PCI_DEVICE_ID_CB134I 0x1341
77#define PCI_DEVICE_ID_CP138U 0x1380
78#define PCI_DEVICE_ID_POS104UL 0x1044
79
80
81#define C168_ASIC_ID 1
82#define C104_ASIC_ID 2
83#define C102_ASIC_ID 0xB
84#define CI132_ASIC_ID 4
85#define CI134_ASIC_ID 3
86#define CI104J_ASIC_ID 5
87
88#define MXSER_HIGHBAUD 1
89#define MXSER_HAS2 2
90
91/* This is only for PCI */
92static const struct {
93 int type;
94 int tx_fifo;
95 int rx_fifo;
96 int xmit_fifo_size;
97 int rx_high_water;
98 int rx_trigger;
99 int rx_low_water;
100 long max_baud;
101} Gpci_uart_info[] = {
102 {MOXA_OTHER_UART, 16, 16, 16, 14, 14, 1, 921600L},
103 {MOXA_MUST_MU150_HWID, 64, 64, 64, 48, 48, 16, 230400L},
104 {MOXA_MUST_MU860_HWID, 128, 128, 128, 96, 96, 32, 921600L}
105};
106#define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info)
107
108struct mxser_cardinfo {
109 char *name;
110 unsigned int nports;
111 unsigned int flags;
112};
113
114static const struct mxser_cardinfo mxser_cards[] = {
115/* 0*/ { "C168 series", 8, },
116 { "C104 series", 4, },
117 { "CI-104J series", 4, },
118 { "C168H/PCI series", 8, },
119 { "C104H/PCI series", 4, },
120/* 5*/ { "C102 series", 4, MXSER_HAS2 }, /* C102-ISA */
121 { "CI-132 series", 4, MXSER_HAS2 },
122 { "CI-134 series", 4, },
123 { "CP-132 series", 2, },
124 { "CP-114 series", 4, },
125/*10*/ { "CT-114 series", 4, },
126 { "CP-102 series", 2, MXSER_HIGHBAUD },
127 { "CP-104U series", 4, },
128 { "CP-168U series", 8, },
129 { "CP-132U series", 2, },
130/*15*/ { "CP-134U series", 4, },
131 { "CP-104JU series", 4, },
132 { "Moxa UC7000 Serial", 8, }, /* RC7000 */
133 { "CP-118U series", 8, },
134 { "CP-102UL series", 2, },
135/*20*/ { "CP-102U series", 2, },
136 { "CP-118EL series", 8, },
137 { "CP-168EL series", 8, },
138 { "CP-104EL series", 4, },
139 { "CB-108 series", 8, },
140/*25*/ { "CB-114 series", 4, },
141 { "CB-134I series", 4, },
142 { "CP-138U series", 8, },
143 { "POS-104UL series", 4, }
144};
145
146/* driver_data correspond to the lines in the structure above
147 see also ISA probe function before you change something */
148static struct pci_device_id mxser_pcibrds[] = {
149 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C168), .driver_data = 3 },
150 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C104), .driver_data = 4 },
151 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132), .driver_data = 8 },
152 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114), .driver_data = 9 },
153 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CT114), .driver_data = 10 },
154 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102), .driver_data = 11 },
155 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104U), .driver_data = 12 },
156 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168U), .driver_data = 13 },
157 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132U), .driver_data = 14 },
158 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134U), .driver_data = 15 },
159 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104JU),.driver_data = 16 },
160 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_RC7000), .driver_data = 17 },
161 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118U), .driver_data = 18 },
162 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102UL),.driver_data = 19 },
163 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102U), .driver_data = 20 },
164 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL),.driver_data = 21 },
165 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL),.driver_data = 22 },
166 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL),.driver_data = 23 },
167 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB108), .driver_data = 24 },
168 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB114), .driver_data = 25 },
169 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB134I), .driver_data = 26 },
170 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP138U), .driver_data = 27 },
171 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_POS104UL), .driver_data = 28 },
172 { }
173};
174MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
175
176static int ioaddr[MXSER_BOARDS] = { 0, 0, 0, 0 };
177static int ttymajor = MXSERMAJOR;
178
179/* Variables for insmod */
180
181MODULE_AUTHOR("Casper Yang");
182MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
183module_param_array(ioaddr, int, NULL, 0);
184module_param(ttymajor, int, 0);
185MODULE_LICENSE("GPL");
186
187struct mxser_log {
188 int tick;
189 unsigned long rxcnt[MXSER_PORTS];
190 unsigned long txcnt[MXSER_PORTS];
191};
192
193
194struct mxser_mon {
195 unsigned long rxcnt;
196 unsigned long txcnt;
197 unsigned long up_rxcnt;
198 unsigned long up_txcnt;
199 int modem_status;
200 unsigned char hold_reason;
201};
202
203struct mxser_mon_ext {
204 unsigned long rx_cnt[32];
205 unsigned long tx_cnt[32];
206 unsigned long up_rxcnt[32];
207 unsigned long up_txcnt[32];
208 int modem_status[32];
209
210 long baudrate[32];
211 int databits[32];
212 int stopbits[32];
213 int parity[32];
214 int flowctrl[32];
215 int fifo[32];
216 int iftype[32];
217};
218
219struct mxser_board;
220
221struct mxser_port {
222 struct mxser_board *board;
223 struct tty_struct *tty;
224
225 unsigned long ioaddr;
226 unsigned long opmode_ioaddr;
227 int max_baud;
228
229 int rx_high_water;
230 int rx_trigger; /* Rx fifo trigger level */
231 int rx_low_water;
232 int baud_base; /* max. speed */
233 int type; /* UART type */
234 int flags; /* defined in tty.h */
235
236 int x_char; /* xon/xoff character */
237 int IER; /* Interrupt Enable Register */
238 int MCR; /* Modem control register */
239
240 unsigned char stop_rx;
241 unsigned char ldisc_stop_rx;
242
243 int custom_divisor;
244 int close_delay;
245 unsigned short closing_wait;
246 unsigned char err_shadow;
247 unsigned long event;
248
249 int count; /* # of fd on device */
250 int blocked_open; /* # of blocked opens */
251 struct async_icount icount; /* kernel counters for 4 input interrupts */
252 int timeout;
253
254 int read_status_mask;
255 int ignore_status_mask;
256 int xmit_fifo_size;
257 unsigned char *xmit_buf;
258 int xmit_head;
259 int xmit_tail;
260 int xmit_cnt;
261
262 struct ktermios normal_termios;
263
264 struct mxser_mon mon_data;
265
266 spinlock_t slock;
267 wait_queue_head_t open_wait;
268 wait_queue_head_t delta_msr_wait;
269};
270
271struct mxser_board {
272 unsigned int idx;
273 int irq;
274 const struct mxser_cardinfo *info;
275 unsigned long vector;
276 unsigned long vector_mask;
277
278 int chip_flag;
279 int uart_type;
280
281 struct mxser_port ports[MXSER_PORTS_PER_BOARD];
282};
283
284struct mxser_mstatus {
285 tcflag_t cflag;
286 int cts;
287 int dsr;
288 int ri;
289 int dcd;
290};
291
292static struct mxser_mstatus GMStatus[MXSER_PORTS];
293
294static int mxserBoardCAP[MXSER_BOARDS] = {
295 0, 0, 0, 0
296 /* 0x180, 0x280, 0x200, 0x320 */
297};
298
299static struct mxser_board mxser_boards[MXSER_BOARDS];
300static struct tty_driver *mxvar_sdriver;
301static struct mxser_log mxvar_log;
302static int mxvar_diagflag;
303static unsigned char mxser_msr[MXSER_PORTS + 1];
304static struct mxser_mon_ext mon_data_ext;
305static int mxser_set_baud_method[MXSER_PORTS + 1];
306
307#ifdef CONFIG_PCI
308static int __devinit CheckIsMoxaMust(unsigned long io)
309{
310 u8 oldmcr, hwid;
311 int i;
312
313 outb(0, io + UART_LCR);
314 DISABLE_MOXA_MUST_ENCHANCE_MODE(io);
315 oldmcr = inb(io + UART_MCR);
316 outb(0, io + UART_MCR);
317 SET_MOXA_MUST_XON1_VALUE(io, 0x11);
318 if ((hwid = inb(io + UART_MCR)) != 0) {
319 outb(oldmcr, io + UART_MCR);
320 return MOXA_OTHER_UART;
321 }
322
323 GET_MOXA_MUST_HARDWARE_ID(io, &hwid);
324 for (i = 1; i < UART_INFO_NUM; i++) { /* 0 = OTHER_UART */
325 if (hwid == Gpci_uart_info[i].type)
326 return (int)hwid;
327 }
328 return MOXA_OTHER_UART;
329}
330#endif
331
332static void process_txrx_fifo(struct mxser_port *info)
333{
334 int i;
335
336 if ((info->type == PORT_16450) || (info->type == PORT_8250)) {
337 info->rx_trigger = 1;
338 info->rx_high_water = 1;
339 info->rx_low_water = 1;
340 info->xmit_fifo_size = 1;
341 } else
342 for (i = 0; i < UART_INFO_NUM; i++)
343 if (info->board->chip_flag == Gpci_uart_info[i].type) {
344 info->rx_trigger = Gpci_uart_info[i].rx_trigger;
345 info->rx_low_water = Gpci_uart_info[i].rx_low_water;
346 info->rx_high_water = Gpci_uart_info[i].rx_high_water;
347 info->xmit_fifo_size = Gpci_uart_info[i].xmit_fifo_size;
348 break;
349 }
350}
351
352static unsigned char mxser_get_msr(int baseaddr, int mode, int port)
353{
354 unsigned char status = 0;
355
356 status = inb(baseaddr + UART_MSR);
357
358 mxser_msr[port] &= 0x0F;
359 mxser_msr[port] |= status;
360 status = mxser_msr[port];
361 if (mode)
362 mxser_msr[port] = 0;
363
364 return status;
365}
366
367static int mxser_block_til_ready(struct tty_struct *tty, struct file *filp,
368 struct mxser_port *port)
369{
370 DECLARE_WAITQUEUE(wait, current);
371 int retval;
372 int do_clocal = 0;
373 unsigned long flags;
374
375 /*
376 * If non-blocking mode is set, or the port is not enabled,
377 * then make the check up front and then exit.
378 */
379 if ((filp->f_flags & O_NONBLOCK) ||
380 test_bit(TTY_IO_ERROR, &tty->flags)) {
381 port->flags |= ASYNC_NORMAL_ACTIVE;
382 return 0;
383 }
384
385 if (tty->termios->c_cflag & CLOCAL)
386 do_clocal = 1;
387
388 /*
389 * Block waiting for the carrier detect and the line to become
390 * free (i.e., not in use by the callout). While we are in
391 * this loop, port->count is dropped by one, so that
392 * mxser_close() knows when to free things. We restore it upon
393 * exit, either normal or abnormal.
394 */
395 retval = 0;
396 add_wait_queue(&port->open_wait, &wait);
397
398 spin_lock_irqsave(&port->slock, flags);
399 if (!tty_hung_up_p(filp))
400 port->count--;
401 spin_unlock_irqrestore(&port->slock, flags);
402 port->blocked_open++;
403 while (1) {
404 spin_lock_irqsave(&port->slock, flags);
405 outb(inb(port->ioaddr + UART_MCR) |
406 UART_MCR_DTR | UART_MCR_RTS, port->ioaddr + UART_MCR);
407 spin_unlock_irqrestore(&port->slock, flags);
408 set_current_state(TASK_INTERRUPTIBLE);
409 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)) {
410 if (port->flags & ASYNC_HUP_NOTIFY)
411 retval = -EAGAIN;
412 else
413 retval = -ERESTARTSYS;
414 break;
415 }
416 if (!(port->flags & ASYNC_CLOSING) &&
417 (do_clocal ||
418 (inb(port->ioaddr + UART_MSR) & UART_MSR_DCD)))
419 break;
420 if (signal_pending(current)) {
421 retval = -ERESTARTSYS;
422 break;
423 }
424 schedule();
425 }
426 set_current_state(TASK_RUNNING);
427 remove_wait_queue(&port->open_wait, &wait);
428 if (!tty_hung_up_p(filp))
429 port->count++;
430 port->blocked_open--;
431 if (retval)
432 return retval;
433 port->flags |= ASYNC_NORMAL_ACTIVE;
434 return 0;
435}
436
437static int mxser_set_baud(struct mxser_port *info, long newspd)
438{
439 int quot = 0, baud;
440 unsigned char cval;
441
442 if (!info->tty || !info->tty->termios)
443 return -1;
444
445 if (!(info->ioaddr))
446 return -1;
447
448 if (newspd > info->max_baud)
449 return -1;
450
451 if (newspd == 134) {
452 quot = 2 * info->baud_base / 269;
453 tty_encode_baud_rate(info->tty, 134, 134);
454 } else if (newspd) {
455 quot = info->baud_base / newspd;
456 if (quot == 0)
457 quot = 1;
458 baud = info->baud_base/quot;
459 tty_encode_baud_rate(info->tty, baud, baud);
460 } else {
461 quot = 0;
462 }
463
464 info->timeout = ((info->xmit_fifo_size * HZ * 10 * quot) / info->baud_base);
465 info->timeout += HZ / 50; /* Add .02 seconds of slop */
466
467 if (quot) {
468 info->MCR |= UART_MCR_DTR;
469 outb(info->MCR, info->ioaddr + UART_MCR);
470 } else {
471 info->MCR &= ~UART_MCR_DTR;
472 outb(info->MCR, info->ioaddr + UART_MCR);
473 return 0;
474 }
475
476 cval = inb(info->ioaddr + UART_LCR);
477
478 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */
479
480 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */
481 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */
482 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */
483
484#ifdef BOTHER
485 if (C_BAUD(info->tty) == BOTHER) {
486 quot = info->baud_base % newspd;
487 quot *= 8;
488 if (quot % newspd > newspd / 2) {
489 quot /= newspd;
490 quot++;
491 } else
492 quot /= newspd;
493
494 SET_MOXA_MUST_ENUM_VALUE(info->ioaddr, quot);
495 } else
496#endif
497 SET_MOXA_MUST_ENUM_VALUE(info->ioaddr, 0);
498
499 return 0;
500}
501
502/*
503 * This routine is called to set the UART divisor registers to match
504 * the specified baud rate for a serial port.
505 */
506static int mxser_change_speed(struct mxser_port *info,
507 struct ktermios *old_termios)
508{
509 unsigned cflag, cval, fcr;
510 int ret = 0;
511 unsigned char status;
512
513 if (!info->tty || !info->tty->termios)
514 return ret;
515 cflag = info->tty->termios->c_cflag;
516 if (!(info->ioaddr))
517 return ret;
518
519 if (mxser_set_baud_method[info->tty->index] == 0)
520 mxser_set_baud(info, tty_get_baud_rate(info->tty));
521
522 /* byte size and parity */
523 switch (cflag & CSIZE) {
524 case CS5:
525 cval = 0x00;
526 break;
527 case CS6:
528 cval = 0x01;
529 break;
530 case CS7:
531 cval = 0x02;
532 break;
533 case CS8:
534 cval = 0x03;
535 break;
536 default:
537 cval = 0x00;
538 break; /* too keep GCC shut... */
539 }
540 if (cflag & CSTOPB)
541 cval |= 0x04;
542 if (cflag & PARENB)
543 cval |= UART_LCR_PARITY;
544 if (!(cflag & PARODD))
545 cval |= UART_LCR_EPAR;
546 if (cflag & CMSPAR)
547 cval |= UART_LCR_SPAR;
548
549 if ((info->type == PORT_8250) || (info->type == PORT_16450)) {
550 if (info->board->chip_flag) {
551 fcr = UART_FCR_ENABLE_FIFO;
552 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
553 SET_MOXA_MUST_FIFO_VALUE(info);
554 } else
555 fcr = 0;
556 } else {
557 fcr = UART_FCR_ENABLE_FIFO;
558 if (info->board->chip_flag) {
559 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
560 SET_MOXA_MUST_FIFO_VALUE(info);
561 } else {
562 switch (info->rx_trigger) {
563 case 1:
564 fcr |= UART_FCR_TRIGGER_1;
565 break;
566 case 4:
567 fcr |= UART_FCR_TRIGGER_4;
568 break;
569 case 8:
570 fcr |= UART_FCR_TRIGGER_8;
571 break;
572 default:
573 fcr |= UART_FCR_TRIGGER_14;
574 break;
575 }
576 }
577 }
578
579 /* CTS flow control flag and modem status interrupts */
580 info->IER &= ~UART_IER_MSI;
581 info->MCR &= ~UART_MCR_AFE;
582 if (cflag & CRTSCTS) {
583 info->flags |= ASYNC_CTS_FLOW;
584 info->IER |= UART_IER_MSI;
585 if ((info->type == PORT_16550A) || (info->board->chip_flag)) {
586 info->MCR |= UART_MCR_AFE;
587 } else {
588 status = inb(info->ioaddr + UART_MSR);
589 if (info->tty->hw_stopped) {
590 if (status & UART_MSR_CTS) {
591 info->tty->hw_stopped = 0;
592 if (info->type != PORT_16550A &&
593 !info->board->chip_flag) {
594 outb(info->IER & ~UART_IER_THRI,
595 info->ioaddr +
596 UART_IER);
597 info->IER |= UART_IER_THRI;
598 outb(info->IER, info->ioaddr +
599 UART_IER);
600 }
601 tty_wakeup(info->tty);
602 }
603 } else {
604 if (!(status & UART_MSR_CTS)) {
605 info->tty->hw_stopped = 1;
606 if ((info->type != PORT_16550A) &&
607 (!info->board->chip_flag)) {
608 info->IER &= ~UART_IER_THRI;
609 outb(info->IER, info->ioaddr +
610 UART_IER);
611 }
612 }
613 }
614 }
615 } else {
616 info->flags &= ~ASYNC_CTS_FLOW;
617 }
618 outb(info->MCR, info->ioaddr + UART_MCR);
619 if (cflag & CLOCAL) {
620 info->flags &= ~ASYNC_CHECK_CD;
621 } else {
622 info->flags |= ASYNC_CHECK_CD;
623 info->IER |= UART_IER_MSI;
624 }
625 outb(info->IER, info->ioaddr + UART_IER);
626
627 /*
628 * Set up parity check flag
629 */
630 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
631 if (I_INPCK(info->tty))
632 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
633 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
634 info->read_status_mask |= UART_LSR_BI;
635
636 info->ignore_status_mask = 0;
637
638 if (I_IGNBRK(info->tty)) {
639 info->ignore_status_mask |= UART_LSR_BI;
640 info->read_status_mask |= UART_LSR_BI;
641 /*
642 * If we're ignore parity and break indicators, ignore
643 * overruns too. (For real raw support).
644 */
645 if (I_IGNPAR(info->tty)) {
646 info->ignore_status_mask |=
647 UART_LSR_OE |
648 UART_LSR_PE |
649 UART_LSR_FE;
650 info->read_status_mask |=
651 UART_LSR_OE |
652 UART_LSR_PE |
653 UART_LSR_FE;
654 }
655 }
656 if (info->board->chip_flag) {
657 SET_MOXA_MUST_XON1_VALUE(info->ioaddr, START_CHAR(info->tty));
658 SET_MOXA_MUST_XOFF1_VALUE(info->ioaddr, STOP_CHAR(info->tty));
659 if (I_IXON(info->tty)) {
660 ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr);
661 } else {
662 DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr);
663 }
664 if (I_IXOFF(info->tty)) {
665 ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(info->ioaddr);
666 } else {
667 DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(info->ioaddr);
668 }
669 }
670
671
672 outb(fcr, info->ioaddr + UART_FCR); /* set fcr */
673 outb(cval, info->ioaddr + UART_LCR);
674
675 return ret;
676}
677
678static void mxser_check_modem_status(struct mxser_port *port, int status)
679{
680 /* update input line counters */
681 if (status & UART_MSR_TERI)
682 port->icount.rng++;
683 if (status & UART_MSR_DDSR)
684 port->icount.dsr++;
685 if (status & UART_MSR_DDCD)
686 port->icount.dcd++;
687 if (status & UART_MSR_DCTS)
688 port->icount.cts++;
689 port->mon_data.modem_status = status;
690 wake_up_interruptible(&port->delta_msr_wait);
691
692 if ((port->flags & ASYNC_CHECK_CD) && (status & UART_MSR_DDCD)) {
693 if (status & UART_MSR_DCD)
694 wake_up_interruptible(&port->open_wait);
695 }
696
697 if (port->flags & ASYNC_CTS_FLOW) {
698 if (port->tty->hw_stopped) {
699 if (status & UART_MSR_CTS) {
700 port->tty->hw_stopped = 0;
701
702 if ((port->type != PORT_16550A) &&
703 (!port->board->chip_flag)) {
704 outb(port->IER & ~UART_IER_THRI,
705 port->ioaddr + UART_IER);
706 port->IER |= UART_IER_THRI;
707 outb(port->IER, port->ioaddr +
708 UART_IER);
709 }
710 tty_wakeup(port->tty);
711 }
712 } else {
713 if (!(status & UART_MSR_CTS)) {
714 port->tty->hw_stopped = 1;
715 if (port->type != PORT_16550A &&
716 !port->board->chip_flag) {
717 port->IER &= ~UART_IER_THRI;
718 outb(port->IER, port->ioaddr +
719 UART_IER);
720 }
721 }
722 }
723 }
724}
725
726static int mxser_startup(struct mxser_port *info)
727{
728 unsigned long page;
729 unsigned long flags;
730
731 page = __get_free_page(GFP_KERNEL);
732 if (!page)
733 return -ENOMEM;
734
735 spin_lock_irqsave(&info->slock, flags);
736
737 if (info->flags & ASYNC_INITIALIZED) {
738 free_page(page);
739 spin_unlock_irqrestore(&info->slock, flags);
740 return 0;
741 }
742
743 if (!info->ioaddr || !info->type) {
744 if (info->tty)
745 set_bit(TTY_IO_ERROR, &info->tty->flags);
746 free_page(page);
747 spin_unlock_irqrestore(&info->slock, flags);
748 return 0;
749 }
750 if (info->xmit_buf)
751 free_page(page);
752 else
753 info->xmit_buf = (unsigned char *) page;
754
755 /*
756 * Clear the FIFO buffers and disable them
757 * (they will be reenabled in mxser_change_speed())
758 */
759 if (info->board->chip_flag)
760 outb((UART_FCR_CLEAR_RCVR |
761 UART_FCR_CLEAR_XMIT |
762 MOXA_MUST_FCR_GDA_MODE_ENABLE), info->ioaddr + UART_FCR);
763 else
764 outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
765 info->ioaddr + UART_FCR);
766
767 /*
768 * At this point there's no way the LSR could still be 0xFF;
769 * if it is, then bail out, because there's likely no UART
770 * here.
771 */
772 if (inb(info->ioaddr + UART_LSR) == 0xff) {
773 spin_unlock_irqrestore(&info->slock, flags);
774 if (capable(CAP_SYS_ADMIN)) {
775 if (info->tty)
776 set_bit(TTY_IO_ERROR, &info->tty->flags);
777 return 0;
778 } else
779 return -ENODEV;
780 }
781
782 /*
783 * Clear the interrupt registers.
784 */
785 (void) inb(info->ioaddr + UART_LSR);
786 (void) inb(info->ioaddr + UART_RX);
787 (void) inb(info->ioaddr + UART_IIR);
788 (void) inb(info->ioaddr + UART_MSR);
789
790 /*
791 * Now, initialize the UART
792 */
793 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */
794 info->MCR = UART_MCR_DTR | UART_MCR_RTS;
795 outb(info->MCR, info->ioaddr + UART_MCR);
796
797 /*
798 * Finally, enable interrupts
799 */
800 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
801
802 if (info->board->chip_flag)
803 info->IER |= MOXA_MUST_IER_EGDAI;
804 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */
805
806 /*
807 * And clear the interrupt registers again for luck.
808 */
809 (void) inb(info->ioaddr + UART_LSR);
810 (void) inb(info->ioaddr + UART_RX);
811 (void) inb(info->ioaddr + UART_IIR);
812 (void) inb(info->ioaddr + UART_MSR);
813
814 if (info->tty)
815 clear_bit(TTY_IO_ERROR, &info->tty->flags);
816 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
817
818 /*
819 * and set the speed of the serial port
820 */
821 mxser_change_speed(info, NULL);
822 info->flags |= ASYNC_INITIALIZED;
823 spin_unlock_irqrestore(&info->slock, flags);
824
825 return 0;
826}
827
828/*
829 * This routine will shutdown a serial port; interrupts maybe disabled, and
830 * DTR is dropped if the hangup on close termio flag is on.
831 */
832static void mxser_shutdown(struct mxser_port *info)
833{
834 unsigned long flags;
835
836 if (!(info->flags & ASYNC_INITIALIZED))
837 return;
838
839 spin_lock_irqsave(&info->slock, flags);
840
841 /*
842 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
843 * here so the queue might never be waken up
844 */
845 wake_up_interruptible(&info->delta_msr_wait);
846
847 /*
848 * Free the IRQ, if necessary
849 */
850 if (info->xmit_buf) {
851 free_page((unsigned long) info->xmit_buf);
852 info->xmit_buf = NULL;
853 }
854
855 info->IER = 0;
856 outb(0x00, info->ioaddr + UART_IER);
857
858 if (!info->tty || (info->tty->termios->c_cflag & HUPCL))
859 info->MCR &= ~(UART_MCR_DTR | UART_MCR_RTS);
860 outb(info->MCR, info->ioaddr + UART_MCR);
861
862 /* clear Rx/Tx FIFO's */
863 if (info->board->chip_flag)
864 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT |
865 MOXA_MUST_FCR_GDA_MODE_ENABLE,
866 info->ioaddr + UART_FCR);
867 else
868 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
869 info->ioaddr + UART_FCR);
870
871 /* read data port to reset things */
872 (void) inb(info->ioaddr + UART_RX);
873
874 if (info->tty)
875 set_bit(TTY_IO_ERROR, &info->tty->flags);
876
877 info->flags &= ~ASYNC_INITIALIZED;
878
879 if (info->board->chip_flag)
880 SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(info->ioaddr);
881
882 spin_unlock_irqrestore(&info->slock, flags);
883}
884
885/*
886 * This routine is called whenever a serial port is opened. It
887 * enables interrupts for a serial port, linking in its async structure into
888 * the IRQ chain. It also performs the serial-specific
889 * initialization for the tty structure.
890 */
891static int mxser_open(struct tty_struct *tty, struct file *filp)
892{
893 struct mxser_port *info;
894 unsigned long flags;
895 int retval, line;
896
897 line = tty->index;
898 if (line == MXSER_PORTS)
899 return 0;
900 if (line < 0 || line > MXSER_PORTS)
901 return -ENODEV;
902 info = &mxser_boards[line / MXSER_PORTS_PER_BOARD].ports[line % MXSER_PORTS_PER_BOARD];
903 if (!info->ioaddr)
904 return -ENODEV;
905
906 tty->driver_data = info;
907 info->tty = tty;
908 /*
909 * Start up serial port
910 */
911 spin_lock_irqsave(&info->slock, flags);
912 info->count++;
913 spin_unlock_irqrestore(&info->slock, flags);
914 retval = mxser_startup(info);
915 if (retval)
916 return retval;
917
918 retval = mxser_block_til_ready(tty, filp, info);
919 if (retval)
920 return retval;
921
922 /* unmark here for very high baud rate (ex. 921600 bps) used */
923 tty->low_latency = 1;
924 return 0;
925}
926
927/*
928 * This routine is called when the serial port gets closed. First, we
929 * wait for the last remaining data to be sent. Then, we unlink its
930 * async structure from the interrupt chain if necessary, and we free
931 * that IRQ if nothing is left in the chain.
932 */
933static void mxser_close(struct tty_struct *tty, struct file *filp)
934{
935 struct mxser_port *info = tty->driver_data;
936
937 unsigned long timeout;
938 unsigned long flags;
939
940 if (tty->index == MXSER_PORTS)
941 return;
942 if (!info)
943 return;
944
945 spin_lock_irqsave(&info->slock, flags);
946
947 if (tty_hung_up_p(filp)) {
948 spin_unlock_irqrestore(&info->slock, flags);
949 return;
950 }
951 if ((tty->count == 1) && (info->count != 1)) {
952 /*
953 * Uh, oh. tty->count is 1, which means that the tty
954 * structure will be freed. Info->count should always
955 * be one in these conditions. If it's greater than
956 * one, we've got real problems, since it means the
957 * serial port won't be shutdown.
958 */
959 printk(KERN_ERR "mxser_close: bad serial port count; "
960 "tty->count is 1, info->count is %d\n", info->count);
961 info->count = 1;
962 }
963 if (--info->count < 0) {
964 printk(KERN_ERR "mxser_close: bad serial port count for "
965 "ttys%d: %d\n", tty->index, info->count);
966 info->count = 0;
967 }
968 if (info->count) {
969 spin_unlock_irqrestore(&info->slock, flags);
970 return;
971 }
972 info->flags |= ASYNC_CLOSING;
973 spin_unlock_irqrestore(&info->slock, flags);
974 /*
975 * Save the termios structure, since this port may have
976 * separate termios for callout and dialin.
977 */
978 if (info->flags & ASYNC_NORMAL_ACTIVE)
979 info->normal_termios = *tty->termios;
980 /*
981 * Now we wait for the transmit buffer to clear; and we notify
982 * the line discipline to only process XON/XOFF characters.
983 */
984 tty->closing = 1;
985 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE)
986 tty_wait_until_sent(tty, info->closing_wait);
987 /*
988 * At this point we stop accepting input. To do this, we
989 * disable the receive line status interrupts, and tell the
990 * interrupt driver to stop checking the data ready bit in the
991 * line status register.
992 */
993 info->IER &= ~UART_IER_RLSI;
994 if (info->board->chip_flag)
995 info->IER &= ~MOXA_MUST_RECV_ISR;
996
997 if (info->flags & ASYNC_INITIALIZED) {
998 outb(info->IER, info->ioaddr + UART_IER);
999 /*
1000 * Before we drop DTR, make sure the UART transmitter
1001 * has completely drained; this is especially
1002 * important if there is a transmit FIFO!
1003 */
1004 timeout = jiffies + HZ;
1005 while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) {
1006 schedule_timeout_interruptible(5);
1007 if (time_after(jiffies, timeout))
1008 break;
1009 }
1010 }
1011 mxser_shutdown(info);
1012
1013 if (tty->driver->flush_buffer)
1014 tty->driver->flush_buffer(tty);
1015
1016 tty_ldisc_flush(tty);
1017
1018 tty->closing = 0;
1019 info->event = 0;
1020 info->tty = NULL;
1021 if (info->blocked_open) {
1022 if (info->close_delay)
1023 schedule_timeout_interruptible(info->close_delay);
1024 wake_up_interruptible(&info->open_wait);
1025 }
1026
1027 info->flags &= ~(ASYNC_NORMAL_ACTIVE | ASYNC_CLOSING);
1028}
1029
1030static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count)
1031{
1032 int c, total = 0;
1033 struct mxser_port *info = tty->driver_data;
1034 unsigned long flags;
1035
1036 if (!info->xmit_buf)
1037 return 0;
1038
1039 while (1) {
1040 c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
1041 SERIAL_XMIT_SIZE - info->xmit_head));
1042 if (c <= 0)
1043 break;
1044
1045 memcpy(info->xmit_buf + info->xmit_head, buf, c);
1046 spin_lock_irqsave(&info->slock, flags);
1047 info->xmit_head = (info->xmit_head + c) &
1048 (SERIAL_XMIT_SIZE - 1);
1049 info->xmit_cnt += c;
1050 spin_unlock_irqrestore(&info->slock, flags);
1051
1052 buf += c;
1053 count -= c;
1054 total += c;
1055 }
1056
1057 if (info->xmit_cnt && !tty->stopped) {
1058 if (!tty->hw_stopped ||
1059 (info->type == PORT_16550A) ||
1060 (info->board->chip_flag)) {
1061 spin_lock_irqsave(&info->slock, flags);
1062 outb(info->IER & ~UART_IER_THRI, info->ioaddr +
1063 UART_IER);
1064 info->IER |= UART_IER_THRI;
1065 outb(info->IER, info->ioaddr + UART_IER);
1066 spin_unlock_irqrestore(&info->slock, flags);
1067 }
1068 }
1069 return total;
1070}
1071
1072static void mxser_put_char(struct tty_struct *tty, unsigned char ch)
1073{
1074 struct mxser_port *info = tty->driver_data;
1075 unsigned long flags;
1076
1077 if (!info->xmit_buf)
1078 return;
1079
1080 if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1)
1081 return;
1082
1083 spin_lock_irqsave(&info->slock, flags);
1084 info->xmit_buf[info->xmit_head++] = ch;
1085 info->xmit_head &= SERIAL_XMIT_SIZE - 1;
1086 info->xmit_cnt++;
1087 spin_unlock_irqrestore(&info->slock, flags);
1088 if (!tty->stopped) {
1089 if (!tty->hw_stopped ||
1090 (info->type == PORT_16550A) ||
1091 info->board->chip_flag) {
1092 spin_lock_irqsave(&info->slock, flags);
1093 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1094 info->IER |= UART_IER_THRI;
1095 outb(info->IER, info->ioaddr + UART_IER);
1096 spin_unlock_irqrestore(&info->slock, flags);
1097 }
1098 }
1099}
1100
1101
1102static void mxser_flush_chars(struct tty_struct *tty)
1103{
1104 struct mxser_port *info = tty->driver_data;
1105 unsigned long flags;
1106
1107 if (info->xmit_cnt <= 0 ||
1108 tty->stopped ||
1109 !info->xmit_buf ||
1110 (tty->hw_stopped &&
1111 (info->type != PORT_16550A) &&
1112 (!info->board->chip_flag)
1113 ))
1114 return;
1115
1116 spin_lock_irqsave(&info->slock, flags);
1117
1118 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1119 info->IER |= UART_IER_THRI;
1120 outb(info->IER, info->ioaddr + UART_IER);
1121
1122 spin_unlock_irqrestore(&info->slock, flags);
1123}
1124
1125static int mxser_write_room(struct tty_struct *tty)
1126{
1127 struct mxser_port *info = tty->driver_data;
1128 int ret;
1129
1130 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
1131 if (ret < 0)
1132 ret = 0;
1133 return ret;
1134}
1135
1136static int mxser_chars_in_buffer(struct tty_struct *tty)
1137{
1138 struct mxser_port *info = tty->driver_data;
1139 return info->xmit_cnt;
1140}
1141
1142static void mxser_flush_buffer(struct tty_struct *tty)
1143{
1144 struct mxser_port *info = tty->driver_data;
1145 char fcr;
1146 unsigned long flags;
1147
1148
1149 spin_lock_irqsave(&info->slock, flags);
1150 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1151
1152 fcr = inb(info->ioaddr + UART_FCR);
1153 outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
1154 info->ioaddr + UART_FCR);
1155 outb(fcr, info->ioaddr + UART_FCR);
1156
1157 spin_unlock_irqrestore(&info->slock, flags);
1158
1159 tty_wakeup(tty);
1160}
1161
1162/*
1163 * ------------------------------------------------------------
1164 * friends of mxser_ioctl()
1165 * ------------------------------------------------------------
1166 */
1167static int mxser_get_serial_info(struct mxser_port *info,
1168 struct serial_struct __user *retinfo)
1169{
1170 struct serial_struct tmp = {
1171 .type = info->type,
1172 .line = info->tty->index,
1173 .port = info->ioaddr,
1174 .irq = info->board->irq,
1175 .flags = info->flags,
1176 .baud_base = info->baud_base,
1177 .close_delay = info->close_delay,
1178 .closing_wait = info->closing_wait,
1179 .custom_divisor = info->custom_divisor,
1180 .hub6 = 0
1181 };
1182 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
1183 return -EFAULT;
1184 return 0;
1185}
1186
1187static int mxser_set_serial_info(struct mxser_port *info,
1188 struct serial_struct __user *new_info)
1189{
1190 struct serial_struct new_serial;
1191 unsigned long sl_flags;
1192 unsigned int flags;
1193 int retval = 0;
1194
1195 if (!new_info || !info->ioaddr)
1196 return -EFAULT;
1197 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
1198 return -EFAULT;
1199
1200 if ((new_serial.irq != info->board->irq) ||
1201 (new_serial.port != info->ioaddr) ||
1202 (new_serial.custom_divisor != info->custom_divisor) ||
1203 (new_serial.baud_base != info->baud_base))
1204 return -EPERM;
1205
1206 flags = info->flags & ASYNC_SPD_MASK;
1207
1208 if (!capable(CAP_SYS_ADMIN)) {
1209 if ((new_serial.baud_base != info->baud_base) ||
1210 (new_serial.close_delay != info->close_delay) ||
1211 ((new_serial.flags & ~ASYNC_USR_MASK) != (info->flags & ~ASYNC_USR_MASK)))
1212 return -EPERM;
1213 info->flags = ((info->flags & ~ASYNC_USR_MASK) |
1214 (new_serial.flags & ASYNC_USR_MASK));
1215 } else {
1216 /*
1217 * OK, past this point, all the error checking has been done.
1218 * At this point, we start making changes.....
1219 */
1220 info->flags = ((info->flags & ~ASYNC_FLAGS) |
1221 (new_serial.flags & ASYNC_FLAGS));
1222 info->close_delay = new_serial.close_delay * HZ / 100;
1223 info->closing_wait = new_serial.closing_wait * HZ / 100;
1224 info->tty->low_latency =
1225 (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1226 info->tty->low_latency = 0;
1227 }
1228
1229 info->type = new_serial.type;
1230
1231 process_txrx_fifo(info);
1232
1233 if (info->flags & ASYNC_INITIALIZED) {
1234 if (flags != (info->flags & ASYNC_SPD_MASK)) {
1235 spin_lock_irqsave(&info->slock, sl_flags);
1236 mxser_change_speed(info, NULL);
1237 spin_unlock_irqrestore(&info->slock, sl_flags);
1238 }
1239 } else
1240 retval = mxser_startup(info);
1241
1242 return retval;
1243}
1244
1245/*
1246 * mxser_get_lsr_info - get line status register info
1247 *
1248 * Purpose: Let user call ioctl() to get info when the UART physically
1249 * is emptied. On bus types like RS485, the transmitter must
1250 * release the bus after transmitting. This must be done when
1251 * the transmit shift register is empty, not be done when the
1252 * transmit holding register is empty. This functionality
1253 * allows an RS485 driver to be written in user space.
1254 */
1255static int mxser_get_lsr_info(struct mxser_port *info,
1256 unsigned int __user *value)
1257{
1258 unsigned char status;
1259 unsigned int result;
1260 unsigned long flags;
1261
1262 spin_lock_irqsave(&info->slock, flags);
1263 status = inb(info->ioaddr + UART_LSR);
1264 spin_unlock_irqrestore(&info->slock, flags);
1265 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
1266 return put_user(result, value);
1267}
1268
1269/*
1270 * This routine sends a break character out the serial port.
1271 */
1272static void mxser_send_break(struct mxser_port *info, int duration)
1273{
1274 unsigned long flags;
1275
1276 if (!info->ioaddr)
1277 return;
1278 set_current_state(TASK_INTERRUPTIBLE);
1279 spin_lock_irqsave(&info->slock, flags);
1280 outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC,
1281 info->ioaddr + UART_LCR);
1282 spin_unlock_irqrestore(&info->slock, flags);
1283 schedule_timeout(duration);
1284 spin_lock_irqsave(&info->slock, flags);
1285 outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC,
1286 info->ioaddr + UART_LCR);
1287 spin_unlock_irqrestore(&info->slock, flags);
1288}
1289
1290static int mxser_tiocmget(struct tty_struct *tty, struct file *file)
1291{
1292 struct mxser_port *info = tty->driver_data;
1293 unsigned char control, status;
1294 unsigned long flags;
1295
1296
1297 if (tty->index == MXSER_PORTS)
1298 return -ENOIOCTLCMD;
1299 if (test_bit(TTY_IO_ERROR, &tty->flags))
1300 return -EIO;
1301
1302 control = info->MCR;
1303
1304 spin_lock_irqsave(&info->slock, flags);
1305 status = inb(info->ioaddr + UART_MSR);
1306 if (status & UART_MSR_ANY_DELTA)
1307 mxser_check_modem_status(info, status);
1308 spin_unlock_irqrestore(&info->slock, flags);
1309 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
1310 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
1311 ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) |
1312 ((status & UART_MSR_RI) ? TIOCM_RNG : 0) |
1313 ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) |
1314 ((status & UART_MSR_CTS) ? TIOCM_CTS : 0);
1315}
1316
1317static int mxser_tiocmset(struct tty_struct *tty, struct file *file,
1318 unsigned int set, unsigned int clear)
1319{
1320 struct mxser_port *info = tty->driver_data;
1321 unsigned long flags;
1322
1323
1324 if (tty->index == MXSER_PORTS)
1325 return -ENOIOCTLCMD;
1326 if (test_bit(TTY_IO_ERROR, &tty->flags))
1327 return -EIO;
1328
1329 spin_lock_irqsave(&info->slock, flags);
1330
1331 if (set & TIOCM_RTS)
1332 info->MCR |= UART_MCR_RTS;
1333 if (set & TIOCM_DTR)
1334 info->MCR |= UART_MCR_DTR;
1335
1336 if (clear & TIOCM_RTS)
1337 info->MCR &= ~UART_MCR_RTS;
1338 if (clear & TIOCM_DTR)
1339 info->MCR &= ~UART_MCR_DTR;
1340
1341 outb(info->MCR, info->ioaddr + UART_MCR);
1342 spin_unlock_irqrestore(&info->slock, flags);
1343 return 0;
1344}
1345
1346static int __init mxser_program_mode(int port)
1347{
1348 int id, i, j, n;
1349
1350 outb(0, port);
1351 outb(0, port);
1352 outb(0, port);
1353 (void)inb(port);
1354 (void)inb(port);
1355 outb(0, port);
1356 (void)inb(port);
1357
1358 id = inb(port + 1) & 0x1F;
1359 if ((id != C168_ASIC_ID) &&
1360 (id != C104_ASIC_ID) &&
1361 (id != C102_ASIC_ID) &&
1362 (id != CI132_ASIC_ID) &&
1363 (id != CI134_ASIC_ID) &&
1364 (id != CI104J_ASIC_ID))
1365 return -1;
1366 for (i = 0, j = 0; i < 4; i++) {
1367 n = inb(port + 2);
1368 if (n == 'M') {
1369 j = 1;
1370 } else if ((j == 1) && (n == 1)) {
1371 j = 2;
1372 break;
1373 } else
1374 j = 0;
1375 }
1376 if (j != 2)
1377 id = -2;
1378 return id;
1379}
1380
1381static void __init mxser_normal_mode(int port)
1382{
1383 int i, n;
1384
1385 outb(0xA5, port + 1);
1386 outb(0x80, port + 3);
1387 outb(12, port + 0); /* 9600 bps */
1388 outb(0, port + 1);
1389 outb(0x03, port + 3); /* 8 data bits */
1390 outb(0x13, port + 4); /* loop back mode */
1391 for (i = 0; i < 16; i++) {
1392 n = inb(port + 5);
1393 if ((n & 0x61) == 0x60)
1394 break;
1395 if ((n & 1) == 1)
1396 (void)inb(port);
1397 }
1398 outb(0x00, port + 4);
1399}
1400
1401#define CHIP_SK 0x01 /* Serial Data Clock in Eprom */
1402#define CHIP_DO 0x02 /* Serial Data Output in Eprom */
1403#define CHIP_CS 0x04 /* Serial Chip Select in Eprom */
1404#define CHIP_DI 0x08 /* Serial Data Input in Eprom */
1405#define EN_CCMD 0x000 /* Chip's command register */
1406#define EN0_RSARLO 0x008 /* Remote start address reg 0 */
1407#define EN0_RSARHI 0x009 /* Remote start address reg 1 */
1408#define EN0_RCNTLO 0x00A /* Remote byte count reg WR */
1409#define EN0_RCNTHI 0x00B /* Remote byte count reg WR */
1410#define EN0_DCFG 0x00E /* Data configuration reg WR */
1411#define EN0_PORT 0x010 /* Rcv missed frame error counter RD */
1412#define ENC_PAGE0 0x000 /* Select page 0 of chip registers */
1413#define ENC_PAGE3 0x0C0 /* Select page 3 of chip registers */
1414static int __init mxser_read_register(int port, unsigned short *regs)
1415{
1416 int i, k, value, id;
1417 unsigned int j;
1418
1419 id = mxser_program_mode(port);
1420 if (id < 0)
1421 return id;
1422 for (i = 0; i < 14; i++) {
1423 k = (i & 0x3F) | 0x180;
1424 for (j = 0x100; j > 0; j >>= 1) {
1425 outb(CHIP_CS, port);
1426 if (k & j) {
1427 outb(CHIP_CS | CHIP_DO, port);
1428 outb(CHIP_CS | CHIP_DO | CHIP_SK, port); /* A? bit of read */
1429 } else {
1430 outb(CHIP_CS, port);
1431 outb(CHIP_CS | CHIP_SK, port); /* A? bit of read */
1432 }
1433 }
1434 (void)inb(port);
1435 value = 0;
1436 for (k = 0, j = 0x8000; k < 16; k++, j >>= 1) {
1437 outb(CHIP_CS, port);
1438 outb(CHIP_CS | CHIP_SK, port);
1439 if (inb(port) & CHIP_DI)
1440 value |= j;
1441 }
1442 regs[i] = value;
1443 outb(0, port);
1444 }
1445 mxser_normal_mode(port);
1446 return id;
1447}
1448
1449static int mxser_ioctl_special(unsigned int cmd, void __user *argp)
1450{
1451 struct mxser_port *port;
1452 int result, status;
1453 unsigned int i, j;
1454
1455 switch (cmd) {
1456 case MOXA_GET_MAJOR:
1457 return put_user(ttymajor, (int __user *)argp);
1458
1459 case MOXA_CHKPORTENABLE:
1460 result = 0;
1461
1462 for (i = 0; i < MXSER_BOARDS; i++)
1463 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++)
1464 if (mxser_boards[i].ports[j].ioaddr)
1465 result |= (1 << i);
1466
1467 return put_user(result, (unsigned long __user *)argp);
1468 case MOXA_GETDATACOUNT:
1469 if (copy_to_user(argp, &mxvar_log, sizeof(mxvar_log)))
1470 return -EFAULT;
1471 return 0;
1472 case MOXA_GETMSTATUS:
1473 for (i = 0; i < MXSER_BOARDS; i++)
1474 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) {
1475 port = &mxser_boards[i].ports[j];
1476
1477 GMStatus[i].ri = 0;
1478 if (!port->ioaddr) {
1479 GMStatus[i].dcd = 0;
1480 GMStatus[i].dsr = 0;
1481 GMStatus[i].cts = 0;
1482 continue;
1483 }
1484
1485 if (!port->tty || !port->tty->termios)
1486 GMStatus[i].cflag =
1487 port->normal_termios.c_cflag;
1488 else
1489 GMStatus[i].cflag =
1490 port->tty->termios->c_cflag;
1491
1492 status = inb(port->ioaddr + UART_MSR);
1493 if (status & 0x80 /*UART_MSR_DCD */ )
1494 GMStatus[i].dcd = 1;
1495 else
1496 GMStatus[i].dcd = 0;
1497
1498 if (status & 0x20 /*UART_MSR_DSR */ )
1499 GMStatus[i].dsr = 1;
1500 else
1501 GMStatus[i].dsr = 0;
1502
1503
1504 if (status & 0x10 /*UART_MSR_CTS */ )
1505 GMStatus[i].cts = 1;
1506 else
1507 GMStatus[i].cts = 0;
1508 }
1509 if (copy_to_user(argp, GMStatus,
1510 sizeof(struct mxser_mstatus) * MXSER_PORTS))
1511 return -EFAULT;
1512 return 0;
1513 case MOXA_ASPP_MON_EXT: {
1514 int p, shiftbit;
1515 unsigned long opmode;
1516 unsigned cflag, iflag;
1517
1518 for (i = 0; i < MXSER_BOARDS; i++)
1519 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) {
1520 port = &mxser_boards[i].ports[j];
1521 if (!port->ioaddr)
1522 continue;
1523
1524 status = mxser_get_msr(port->ioaddr, 0, i);
1525
1526 if (status & UART_MSR_TERI)
1527 port->icount.rng++;
1528 if (status & UART_MSR_DDSR)
1529 port->icount.dsr++;
1530 if (status & UART_MSR_DDCD)
1531 port->icount.dcd++;
1532 if (status & UART_MSR_DCTS)
1533 port->icount.cts++;
1534
1535 port->mon_data.modem_status = status;
1536 mon_data_ext.rx_cnt[i] = port->mon_data.rxcnt;
1537 mon_data_ext.tx_cnt[i] = port->mon_data.txcnt;
1538 mon_data_ext.up_rxcnt[i] =
1539 port->mon_data.up_rxcnt;
1540 mon_data_ext.up_txcnt[i] =
1541 port->mon_data.up_txcnt;
1542 mon_data_ext.modem_status[i] =
1543 port->mon_data.modem_status;
1544 mon_data_ext.baudrate[i] =
1545 tty_get_baud_rate(port->tty);
1546
1547 if (!port->tty || !port->tty->termios) {
1548 cflag = port->normal_termios.c_cflag;
1549 iflag = port->normal_termios.c_iflag;
1550 } else {
1551 cflag = port->tty->termios->c_cflag;
1552 iflag = port->tty->termios->c_iflag;
1553 }
1554
1555 mon_data_ext.databits[i] = cflag & CSIZE;
1556
1557 mon_data_ext.stopbits[i] = cflag & CSTOPB;
1558
1559 mon_data_ext.parity[i] =
1560 cflag & (PARENB | PARODD | CMSPAR);
1561
1562 mon_data_ext.flowctrl[i] = 0x00;
1563
1564 if (cflag & CRTSCTS)
1565 mon_data_ext.flowctrl[i] |= 0x03;
1566
1567 if (iflag & (IXON | IXOFF))
1568 mon_data_ext.flowctrl[i] |= 0x0C;
1569
1570 if (port->type == PORT_16550A)
1571 mon_data_ext.fifo[i] = 1;
1572 else
1573 mon_data_ext.fifo[i] = 0;
1574
1575 p = i % 4;
1576 shiftbit = p * 2;
1577 opmode = inb(port->opmode_ioaddr) >> shiftbit;
1578 opmode &= OP_MODE_MASK;
1579
1580 mon_data_ext.iftype[i] = opmode;
1581
1582 }
1583 if (copy_to_user(argp, &mon_data_ext,
1584 sizeof(mon_data_ext)))
1585 return -EFAULT;
1586
1587 return 0;
1588
1589 } default:
1590 return -ENOIOCTLCMD;
1591 }
1592 return 0;
1593}
1594
1595static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg,
1596 struct async_icount *cprev)
1597{
1598 struct async_icount cnow;
1599 unsigned long flags;
1600 int ret;
1601
1602 spin_lock_irqsave(&info->slock, flags);
1603 cnow = info->icount; /* atomic copy */
1604 spin_unlock_irqrestore(&info->slock, flags);
1605
1606 ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) ||
1607 ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) ||
1608 ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) ||
1609 ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts));
1610
1611 *cprev = cnow;
1612
1613 return ret;
1614}
1615
1616static int mxser_ioctl(struct tty_struct *tty, struct file *file,
1617 unsigned int cmd, unsigned long arg)
1618{
1619 struct mxser_port *info = tty->driver_data;
1620 struct async_icount cnow;
1621 struct serial_icounter_struct __user *p_cuser;
1622 unsigned long flags;
1623 void __user *argp = (void __user *)arg;
1624 int retval;
1625
1626 if (tty->index == MXSER_PORTS)
1627 return mxser_ioctl_special(cmd, argp);
1628
1629 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) {
1630 int p;
1631 unsigned long opmode;
1632 static unsigned char ModeMask[] = { 0xfc, 0xf3, 0xcf, 0x3f };
1633 int shiftbit;
1634 unsigned char val, mask;
1635
1636 p = tty->index % 4;
1637 if (cmd == MOXA_SET_OP_MODE) {
1638 if (get_user(opmode, (int __user *) argp))
1639 return -EFAULT;
1640 if (opmode != RS232_MODE &&
1641 opmode != RS485_2WIRE_MODE &&
1642 opmode != RS422_MODE &&
1643 opmode != RS485_4WIRE_MODE)
1644 return -EFAULT;
1645 mask = ModeMask[p];
1646 shiftbit = p * 2;
1647 val = inb(info->opmode_ioaddr);
1648 val &= mask;
1649 val |= (opmode << shiftbit);
1650 outb(val, info->opmode_ioaddr);
1651 } else {
1652 shiftbit = p * 2;
1653 opmode = inb(info->opmode_ioaddr) >> shiftbit;
1654 opmode &= OP_MODE_MASK;
1655 if (put_user(opmode, (int __user *)argp))
1656 return -EFAULT;
1657 }
1658 return 0;
1659 }
1660
1661 if (cmd != TIOCGSERIAL && cmd != TIOCMIWAIT && cmd != TIOCGICOUNT &&
1662 test_bit(TTY_IO_ERROR, &tty->flags))
1663 return -EIO;
1664
1665 switch (cmd) {
1666 case TCSBRK: /* SVID version: non-zero arg --> no break */
1667 retval = tty_check_change(tty);
1668 if (retval)
1669 return retval;
1670 tty_wait_until_sent(tty, 0);
1671 if (!arg)
1672 mxser_send_break(info, HZ / 4); /* 1/4 second */
1673 return 0;
1674 case TCSBRKP: /* support for POSIX tcsendbreak() */
1675 retval = tty_check_change(tty);
1676 if (retval)
1677 return retval;
1678 tty_wait_until_sent(tty, 0);
1679 mxser_send_break(info, arg ? arg * (HZ / 10) : HZ / 4);
1680 return 0;
1681 case TIOCGSOFTCAR:
1682 return put_user(!!C_CLOCAL(tty), (unsigned long __user *)argp);
1683 case TIOCSSOFTCAR:
1684 if (get_user(arg, (unsigned long __user *)argp))
1685 return -EFAULT;
1686 tty->termios->c_cflag = ((tty->termios->c_cflag & ~CLOCAL) | (arg ? CLOCAL : 0));
1687 return 0;
1688 case TIOCGSERIAL:
1689 return mxser_get_serial_info(info, argp);
1690 case TIOCSSERIAL:
1691 return mxser_set_serial_info(info, argp);
1692 case TIOCSERGETLSR: /* Get line status register */
1693 return mxser_get_lsr_info(info, argp);
1694 /*
1695 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
1696 * - mask passed in arg for lines of interest
1697 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
1698 * Caller should use TIOCGICOUNT to see which one it was
1699 */
1700 case TIOCMIWAIT:
1701 spin_lock_irqsave(&info->slock, flags);
1702 cnow = info->icount; /* note the counters on entry */
1703 spin_unlock_irqrestore(&info->slock, flags);
1704
1705 return wait_event_interruptible(info->delta_msr_wait,
1706 mxser_cflags_changed(info, arg, &cnow));
1707 /*
1708 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1709 * Return: write counters to the user passed counter struct
1710 * NB: both 1->0 and 0->1 transitions are counted except for
1711 * RI where only 0->1 is counted.
1712 */
1713 case TIOCGICOUNT:
1714 spin_lock_irqsave(&info->slock, flags);
1715 cnow = info->icount;
1716 spin_unlock_irqrestore(&info->slock, flags);
1717 p_cuser = argp;
1718 if (put_user(cnow.frame, &p_cuser->frame))
1719 return -EFAULT;
1720 if (put_user(cnow.brk, &p_cuser->brk))
1721 return -EFAULT;
1722 if (put_user(cnow.overrun, &p_cuser->overrun))
1723 return -EFAULT;
1724 if (put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1725 return -EFAULT;
1726 if (put_user(cnow.parity, &p_cuser->parity))
1727 return -EFAULT;
1728 if (put_user(cnow.rx, &p_cuser->rx))
1729 return -EFAULT;
1730 if (put_user(cnow.tx, &p_cuser->tx))
1731 return -EFAULT;
1732 put_user(cnow.cts, &p_cuser->cts);
1733 put_user(cnow.dsr, &p_cuser->dsr);
1734 put_user(cnow.rng, &p_cuser->rng);
1735 put_user(cnow.dcd, &p_cuser->dcd);
1736 return 0;
1737 case MOXA_HighSpeedOn:
1738 return put_user(info->baud_base != 115200 ? 1 : 0, (int __user *)argp);
1739 case MOXA_SDS_RSTICOUNTER:
1740 info->mon_data.rxcnt = 0;
1741 info->mon_data.txcnt = 0;
1742 return 0;
1743
1744 case MOXA_ASPP_OQUEUE:{
1745 int len, lsr;
1746
1747 len = mxser_chars_in_buffer(tty);
1748
1749 lsr = inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT;
1750
1751 len += (lsr ? 0 : 1);
1752
1753 return put_user(len, (int __user *)argp);
1754 }
1755 case MOXA_ASPP_MON: {
1756 int mcr, status;
1757
1758 status = mxser_get_msr(info->ioaddr, 1, tty->index);
1759 mxser_check_modem_status(info, status);
1760
1761 mcr = inb(info->ioaddr + UART_MCR);
1762 if (mcr & MOXA_MUST_MCR_XON_FLAG)
1763 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFHOLD;
1764 else
1765 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFHOLD;
1766
1767 if (mcr & MOXA_MUST_MCR_TX_XON)
1768 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFXENT;
1769 else
1770 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFXENT;
1771
1772 if (info->tty->hw_stopped)
1773 info->mon_data.hold_reason |= NPPI_NOTIFY_CTSHOLD;
1774 else
1775 info->mon_data.hold_reason &= ~NPPI_NOTIFY_CTSHOLD;
1776
1777 if (copy_to_user(argp, &info->mon_data,
1778 sizeof(struct mxser_mon)))
1779 return -EFAULT;
1780
1781 return 0;
1782 }
1783 case MOXA_ASPP_LSTATUS: {
1784 if (put_user(info->err_shadow, (unsigned char __user *)argp))
1785 return -EFAULT;
1786
1787 info->err_shadow = 0;
1788 return 0;
1789 }
1790 case MOXA_SET_BAUD_METHOD: {
1791 int method;
1792
1793 if (get_user(method, (int __user *)argp))
1794 return -EFAULT;
1795 mxser_set_baud_method[tty->index] = method;
1796 return put_user(method, (int __user *)argp);
1797 }
1798 default:
1799 return -ENOIOCTLCMD;
1800 }
1801 return 0;
1802}
1803
1804static void mxser_stoprx(struct tty_struct *tty)
1805{
1806 struct mxser_port *info = tty->driver_data;
1807
1808 info->ldisc_stop_rx = 1;
1809 if (I_IXOFF(tty)) {
1810 if (info->board->chip_flag) {
1811 info->IER &= ~MOXA_MUST_RECV_ISR;
1812 outb(info->IER, info->ioaddr + UART_IER);
1813 } else {
1814 info->x_char = STOP_CHAR(tty);
1815 outb(0, info->ioaddr + UART_IER);
1816 info->IER |= UART_IER_THRI;
1817 outb(info->IER, info->ioaddr + UART_IER);
1818 }
1819 }
1820
1821 if (info->tty->termios->c_cflag & CRTSCTS) {
1822 info->MCR &= ~UART_MCR_RTS;
1823 outb(info->MCR, info->ioaddr + UART_MCR);
1824 }
1825}
1826
1827/*
1828 * This routine is called by the upper-layer tty layer to signal that
1829 * incoming characters should be throttled.
1830 */
1831static void mxser_throttle(struct tty_struct *tty)
1832{
1833 mxser_stoprx(tty);
1834}
1835
1836static void mxser_unthrottle(struct tty_struct *tty)
1837{
1838 struct mxser_port *info = tty->driver_data;
1839
1840 /* startrx */
1841 info->ldisc_stop_rx = 0;
1842 if (I_IXOFF(tty)) {
1843 if (info->x_char)
1844 info->x_char = 0;
1845 else {
1846 if (info->board->chip_flag) {
1847 info->IER |= MOXA_MUST_RECV_ISR;
1848 outb(info->IER, info->ioaddr + UART_IER);
1849 } else {
1850 info->x_char = START_CHAR(tty);
1851 outb(0, info->ioaddr + UART_IER);
1852 info->IER |= UART_IER_THRI;
1853 outb(info->IER, info->ioaddr + UART_IER);
1854 }
1855 }
1856 }
1857
1858 if (info->tty->termios->c_cflag & CRTSCTS) {
1859 info->MCR |= UART_MCR_RTS;
1860 outb(info->MCR, info->ioaddr + UART_MCR);
1861 }
1862}
1863
1864/*
1865 * mxser_stop() and mxser_start()
1866 *
1867 * This routines are called before setting or resetting tty->stopped.
1868 * They enable or disable transmitter interrupts, as necessary.
1869 */
1870static void mxser_stop(struct tty_struct *tty)
1871{
1872 struct mxser_port *info = tty->driver_data;
1873 unsigned long flags;
1874
1875 spin_lock_irqsave(&info->slock, flags);
1876 if (info->IER & UART_IER_THRI) {
1877 info->IER &= ~UART_IER_THRI;
1878 outb(info->IER, info->ioaddr + UART_IER);
1879 }
1880 spin_unlock_irqrestore(&info->slock, flags);
1881}
1882
1883static void mxser_start(struct tty_struct *tty)
1884{
1885 struct mxser_port *info = tty->driver_data;
1886 unsigned long flags;
1887
1888 spin_lock_irqsave(&info->slock, flags);
1889 if (info->xmit_cnt && info->xmit_buf) {
1890 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1891 info->IER |= UART_IER_THRI;
1892 outb(info->IER, info->ioaddr + UART_IER);
1893 }
1894 spin_unlock_irqrestore(&info->slock, flags);
1895}
1896
1897static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1898{
1899 struct mxser_port *info = tty->driver_data;
1900 unsigned long flags;
1901
1902 spin_lock_irqsave(&info->slock, flags);
1903 mxser_change_speed(info, old_termios);
1904 spin_unlock_irqrestore(&info->slock, flags);
1905
1906 if ((old_termios->c_cflag & CRTSCTS) &&
1907 !(tty->termios->c_cflag & CRTSCTS)) {
1908 tty->hw_stopped = 0;
1909 mxser_start(tty);
1910 }
1911
1912 /* Handle sw stopped */
1913 if ((old_termios->c_iflag & IXON) &&
1914 !(tty->termios->c_iflag & IXON)) {
1915 tty->stopped = 0;
1916
1917 if (info->board->chip_flag) {
1918 spin_lock_irqsave(&info->slock, flags);
1919 DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(info->ioaddr);
1920 spin_unlock_irqrestore(&info->slock, flags);
1921 }
1922
1923 mxser_start(tty);
1924 }
1925}
1926
1927/*
1928 * mxser_wait_until_sent() --- wait until the transmitter is empty
1929 */
1930static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
1931{
1932 struct mxser_port *info = tty->driver_data;
1933 unsigned long orig_jiffies, char_time;
1934 int lsr;
1935
1936 if (info->type == PORT_UNKNOWN)
1937 return;
1938
1939 if (info->xmit_fifo_size == 0)
1940 return; /* Just in case.... */
1941
1942 orig_jiffies = jiffies;
1943 /*
1944 * Set the check interval to be 1/5 of the estimated time to
1945 * send a single character, and make it at least 1. The check
1946 * interval should also be less than the timeout.
1947 *
1948 * Note: we have to use pretty tight timings here to satisfy
1949 * the NIST-PCTS.
1950 */
1951 char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size;
1952 char_time = char_time / 5;
1953 if (char_time == 0)
1954 char_time = 1;
1955 if (timeout && timeout < char_time)
1956 char_time = timeout;
1957 /*
1958 * If the transmitter hasn't cleared in twice the approximate
1959 * amount of time to send the entire FIFO, it probably won't
1960 * ever clear. This assumes the UART isn't doing flow
1961 * control, which is currently the case. Hence, if it ever
1962 * takes longer than info->timeout, this is probably due to a
1963 * UART bug of some kind. So, we clamp the timeout parameter at
1964 * 2*info->timeout.
1965 */
1966 if (!timeout || timeout > 2 * info->timeout)
1967 timeout = 2 * info->timeout;
1968#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
1969 printk(KERN_DEBUG "In rs_wait_until_sent(%d) check=%lu...",
1970 timeout, char_time);
1971 printk("jiff=%lu...", jiffies);
1972#endif
1973 while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) {
1974#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
1975 printk("lsr = %d (jiff=%lu)...", lsr, jiffies);
1976#endif
1977 schedule_timeout_interruptible(char_time);
1978 if (signal_pending(current))
1979 break;
1980 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1981 break;
1982 }
1983 set_current_state(TASK_RUNNING);
1984
1985#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
1986 printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies);
1987#endif
1988}
1989
1990/*
1991 * This routine is called by tty_hangup() when a hangup is signaled.
1992 */
1993static void mxser_hangup(struct tty_struct *tty)
1994{
1995 struct mxser_port *info = tty->driver_data;
1996
1997 mxser_flush_buffer(tty);
1998 mxser_shutdown(info);
1999 info->event = 0;
2000 info->count = 0;
2001 info->flags &= ~ASYNC_NORMAL_ACTIVE;
2002 info->tty = NULL;
2003 wake_up_interruptible(&info->open_wait);
2004}
2005
2006/*
2007 * mxser_rs_break() --- routine which turns the break handling on or off
2008 */
2009static void mxser_rs_break(struct tty_struct *tty, int break_state)
2010{
2011 struct mxser_port *info = tty->driver_data;
2012 unsigned long flags;
2013
2014 spin_lock_irqsave(&info->slock, flags);
2015 if (break_state == -1)
2016 outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC,
2017 info->ioaddr + UART_LCR);
2018 else
2019 outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC,
2020 info->ioaddr + UART_LCR);
2021 spin_unlock_irqrestore(&info->slock, flags);
2022}
2023
2024static void mxser_receive_chars(struct mxser_port *port, int *status)
2025{
2026 struct tty_struct *tty = port->tty;
2027 unsigned char ch, gdl;
2028 int ignored = 0;
2029 int cnt = 0;
2030 int recv_room;
2031 int max = 256;
2032
2033 recv_room = tty->receive_room;
2034 if ((recv_room == 0) && (!port->ldisc_stop_rx))
2035 mxser_stoprx(tty);
2036
2037 if (port->board->chip_flag != MOXA_OTHER_UART) {
2038
2039 if (*status & UART_LSR_SPECIAL)
2040 goto intr_old;
2041 if (port->board->chip_flag == MOXA_MUST_MU860_HWID &&
2042 (*status & MOXA_MUST_LSR_RERR))
2043 goto intr_old;
2044 if (*status & MOXA_MUST_LSR_RERR)
2045 goto intr_old;
2046
2047 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER);
2048
2049 if (port->board->chip_flag == MOXA_MUST_MU150_HWID)
2050 gdl &= MOXA_MUST_GDL_MASK;
2051 if (gdl >= recv_room) {
2052 if (!port->ldisc_stop_rx)
2053 mxser_stoprx(tty);
2054 }
2055 while (gdl--) {
2056 ch = inb(port->ioaddr + UART_RX);
2057 tty_insert_flip_char(tty, ch, 0);
2058 cnt++;
2059 }
2060 goto end_intr;
2061 }
2062intr_old:
2063
2064 do {
2065 if (max-- < 0)
2066 break;
2067
2068 ch = inb(port->ioaddr + UART_RX);
2069 if (port->board->chip_flag && (*status & UART_LSR_OE))
2070 outb(0x23, port->ioaddr + UART_FCR);
2071 *status &= port->read_status_mask;
2072 if (*status & port->ignore_status_mask) {
2073 if (++ignored > 100)
2074 break;
2075 } else {
2076 char flag = 0;
2077 if (*status & UART_LSR_SPECIAL) {
2078 if (*status & UART_LSR_BI) {
2079 flag = TTY_BREAK;
2080 port->icount.brk++;
2081
2082 if (port->flags & ASYNC_SAK)
2083 do_SAK(tty);
2084 } else if (*status & UART_LSR_PE) {
2085 flag = TTY_PARITY;
2086 port->icount.parity++;
2087 } else if (*status & UART_LSR_FE) {
2088 flag = TTY_FRAME;
2089 port->icount.frame++;
2090 } else if (*status & UART_LSR_OE) {
2091 flag = TTY_OVERRUN;
2092 port->icount.overrun++;
2093 } else
2094 flag = TTY_BREAK;
2095 }
2096 tty_insert_flip_char(tty, ch, flag);
2097 cnt++;
2098 if (cnt >= recv_room) {
2099 if (!port->ldisc_stop_rx)
2100 mxser_stoprx(tty);
2101 break;
2102 }
2103
2104 }
2105
2106 if (port->board->chip_flag)
2107 break;
2108
2109 *status = inb(port->ioaddr + UART_LSR);
2110 } while (*status & UART_LSR_DR);
2111
2112end_intr:
2113 mxvar_log.rxcnt[port->tty->index] += cnt;
2114 port->mon_data.rxcnt += cnt;
2115 port->mon_data.up_rxcnt += cnt;
2116
2117 /*
2118 * We are called from an interrupt context with &port->slock
2119 * being held. Drop it temporarily in order to prevent
2120 * recursive locking.
2121 */
2122 spin_unlock(&port->slock);
2123 tty_flip_buffer_push(tty);
2124 spin_lock(&port->slock);
2125}
2126
2127static void mxser_transmit_chars(struct mxser_port *port)
2128{
2129 int count, cnt;
2130
2131 if (port->x_char) {
2132 outb(port->x_char, port->ioaddr + UART_TX);
2133 port->x_char = 0;
2134 mxvar_log.txcnt[port->tty->index]++;
2135 port->mon_data.txcnt++;
2136 port->mon_data.up_txcnt++;
2137 port->icount.tx++;
2138 return;
2139 }
2140
2141 if (port->xmit_buf == NULL)
2142 return;
2143
2144 if ((port->xmit_cnt <= 0) || port->tty->stopped ||
2145 (port->tty->hw_stopped &&
2146 (port->type != PORT_16550A) &&
2147 (!port->board->chip_flag))) {
2148 port->IER &= ~UART_IER_THRI;
2149 outb(port->IER, port->ioaddr + UART_IER);
2150 return;
2151 }
2152
2153 cnt = port->xmit_cnt;
2154 count = port->xmit_fifo_size;
2155 do {
2156 outb(port->xmit_buf[port->xmit_tail++],
2157 port->ioaddr + UART_TX);
2158 port->xmit_tail = port->xmit_tail & (SERIAL_XMIT_SIZE - 1);
2159 if (--port->xmit_cnt <= 0)
2160 break;
2161 } while (--count > 0);
2162 mxvar_log.txcnt[port->tty->index] += (cnt - port->xmit_cnt);
2163
2164 port->mon_data.txcnt += (cnt - port->xmit_cnt);
2165 port->mon_data.up_txcnt += (cnt - port->xmit_cnt);
2166 port->icount.tx += (cnt - port->xmit_cnt);
2167
2168 if (port->xmit_cnt < WAKEUP_CHARS)
2169 tty_wakeup(port->tty);
2170
2171 if (port->xmit_cnt <= 0) {
2172 port->IER &= ~UART_IER_THRI;
2173 outb(port->IER, port->ioaddr + UART_IER);
2174 }
2175}
2176
2177/*
2178 * This is the serial driver's generic interrupt routine
2179 */
2180static irqreturn_t mxser_interrupt(int irq, void *dev_id)
2181{
2182 int status, iir, i;
2183 struct mxser_board *brd = NULL;
2184 struct mxser_port *port;
2185 int max, irqbits, bits, msr;
2186 unsigned int int_cnt, pass_counter = 0;
2187 int handled = IRQ_NONE;
2188
2189 for (i = 0; i < MXSER_BOARDS; i++)
2190 if (dev_id == &mxser_boards[i]) {
2191 brd = dev_id;
2192 break;
2193 }
2194
2195 if (i == MXSER_BOARDS)
2196 goto irq_stop;
2197 if (brd == NULL)
2198 goto irq_stop;
2199 max = brd->info->nports;
2200 while (pass_counter++ < MXSER_ISR_PASS_LIMIT) {
2201 irqbits = inb(brd->vector) & brd->vector_mask;
2202 if (irqbits == brd->vector_mask)
2203 break;
2204
2205 handled = IRQ_HANDLED;
2206 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
2207 if (irqbits == brd->vector_mask)
2208 break;
2209 if (bits & irqbits)
2210 continue;
2211 port = &brd->ports[i];
2212
2213 int_cnt = 0;
2214 spin_lock(&port->slock);
2215 do {
2216 iir = inb(port->ioaddr + UART_IIR);
2217 if (iir & UART_IIR_NO_INT)
2218 break;
2219 iir &= MOXA_MUST_IIR_MASK;
2220 if (!port->tty ||
2221 (port->flags & ASYNC_CLOSING) ||
2222 !(port->flags &
2223 ASYNC_INITIALIZED)) {
2224 status = inb(port->ioaddr + UART_LSR);
2225 outb(0x27, port->ioaddr + UART_FCR);
2226 inb(port->ioaddr + UART_MSR);
2227 break;
2228 }
2229
2230 status = inb(port->ioaddr + UART_LSR);
2231
2232 if (status & UART_LSR_PE)
2233 port->err_shadow |= NPPI_NOTIFY_PARITY;
2234 if (status & UART_LSR_FE)
2235 port->err_shadow |= NPPI_NOTIFY_FRAMING;
2236 if (status & UART_LSR_OE)
2237 port->err_shadow |=
2238 NPPI_NOTIFY_HW_OVERRUN;
2239 if (status & UART_LSR_BI)
2240 port->err_shadow |= NPPI_NOTIFY_BREAK;
2241
2242 if (port->board->chip_flag) {
2243 if (iir == MOXA_MUST_IIR_GDA ||
2244 iir == MOXA_MUST_IIR_RDA ||
2245 iir == MOXA_MUST_IIR_RTO ||
2246 iir == MOXA_MUST_IIR_LSR)
2247 mxser_receive_chars(port,
2248 &status);
2249
2250 } else {
2251 status &= port->read_status_mask;
2252 if (status & UART_LSR_DR)
2253 mxser_receive_chars(port,
2254 &status);
2255 }
2256 msr = inb(port->ioaddr + UART_MSR);
2257 if (msr & UART_MSR_ANY_DELTA)
2258 mxser_check_modem_status(port, msr);
2259
2260 if (port->board->chip_flag) {
2261 if (iir == 0x02 && (status &
2262 UART_LSR_THRE))
2263 mxser_transmit_chars(port);
2264 } else {
2265 if (status & UART_LSR_THRE)
2266 mxser_transmit_chars(port);
2267 }
2268 } while (int_cnt++ < MXSER_ISR_PASS_LIMIT);
2269 spin_unlock(&port->slock);
2270 }
2271 }
2272
2273irq_stop:
2274 return handled;
2275}
2276
2277static const struct tty_operations mxser_ops = {
2278 .open = mxser_open,
2279 .close = mxser_close,
2280 .write = mxser_write,
2281 .put_char = mxser_put_char,
2282 .flush_chars = mxser_flush_chars,
2283 .write_room = mxser_write_room,
2284 .chars_in_buffer = mxser_chars_in_buffer,
2285 .flush_buffer = mxser_flush_buffer,
2286 .ioctl = mxser_ioctl,
2287 .throttle = mxser_throttle,
2288 .unthrottle = mxser_unthrottle,
2289 .set_termios = mxser_set_termios,
2290 .stop = mxser_stop,
2291 .start = mxser_start,
2292 .hangup = mxser_hangup,
2293 .break_ctl = mxser_rs_break,
2294 .wait_until_sent = mxser_wait_until_sent,
2295 .tiocmget = mxser_tiocmget,
2296 .tiocmset = mxser_tiocmset,
2297};
2298
2299/*
2300 * The MOXA Smartio/Industio serial driver boot-time initialization code!
2301 */
2302
2303static void mxser_release_res(struct mxser_board *brd, struct pci_dev *pdev,
2304 unsigned int irq)
2305{
2306 if (irq)
2307 free_irq(brd->irq, brd);
2308 if (pdev != NULL) { /* PCI */
2309#ifdef CONFIG_PCI
2310 pci_release_region(pdev, 2);
2311 pci_release_region(pdev, 3);
2312#endif
2313 } else {
2314 release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
2315 release_region(brd->vector, 1);
2316 }
2317}
2318
2319static int __devinit mxser_initbrd(struct mxser_board *brd,
2320 struct pci_dev *pdev)
2321{
2322 struct mxser_port *info;
2323 unsigned int i;
2324 int retval;
2325
2326 printk(KERN_INFO "max. baud rate = %d bps.\n", brd->ports[0].max_baud);
2327
2328 for (i = 0; i < brd->info->nports; i++) {
2329 info = &brd->ports[i];
2330 info->board = brd;
2331 info->stop_rx = 0;
2332 info->ldisc_stop_rx = 0;
2333
2334 /* Enhance mode enabled here */
2335 if (brd->chip_flag != MOXA_OTHER_UART)
2336 ENABLE_MOXA_MUST_ENCHANCE_MODE(info->ioaddr);
2337
2338 info->flags = ASYNC_SHARE_IRQ;
2339 info->type = brd->uart_type;
2340
2341 process_txrx_fifo(info);
2342
2343 info->custom_divisor = info->baud_base * 16;
2344 info->close_delay = 5 * HZ / 10;
2345 info->closing_wait = 30 * HZ;
2346 info->normal_termios = mxvar_sdriver->init_termios;
2347 init_waitqueue_head(&info->open_wait);
2348 init_waitqueue_head(&info->delta_msr_wait);
2349 memset(&info->mon_data, 0, sizeof(struct mxser_mon));
2350 info->err_shadow = 0;
2351 spin_lock_init(&info->slock);
2352
2353 /* before set INT ISR, disable all int */
2354 outb(inb(info->ioaddr + UART_IER) & 0xf0,
2355 info->ioaddr + UART_IER);
2356 }
2357
2358 retval = request_irq(brd->irq, mxser_interrupt, IRQF_SHARED, "mxser",
2359 brd);
2360 if (retval) {
2361 printk(KERN_ERR "Board %s: Request irq failed, IRQ (%d) may "
2362 "conflict with another device.\n",
2363 brd->info->name, brd->irq);
2364 /* We hold resources, we need to release them. */
2365 mxser_release_res(brd, pdev, 0);
2366 }
2367 return retval;
2368}
2369
2370static int __init mxser_get_ISA_conf(int cap, struct mxser_board *brd)
2371{
2372 int id, i, bits;
2373 unsigned short regs[16], irq;
2374 unsigned char scratch, scratch2;
2375
2376 brd->chip_flag = MOXA_OTHER_UART;
2377
2378 id = mxser_read_register(cap, regs);
2379 switch (id) {
2380 case C168_ASIC_ID:
2381 brd->info = &mxser_cards[0];
2382 break;
2383 case C104_ASIC_ID:
2384 brd->info = &mxser_cards[1];
2385 break;
2386 case CI104J_ASIC_ID:
2387 brd->info = &mxser_cards[2];
2388 break;
2389 case C102_ASIC_ID:
2390 brd->info = &mxser_cards[5];
2391 break;
2392 case CI132_ASIC_ID:
2393 brd->info = &mxser_cards[6];
2394 break;
2395 case CI134_ASIC_ID:
2396 brd->info = &mxser_cards[7];
2397 break;
2398 default:
2399 return 0;
2400 }
2401
2402 irq = 0;
2403 /* some ISA cards have 2 ports, but we want to see them as 4-port (why?)
2404 Flag-hack checks if configuration should be read as 2-port here. */
2405 if (brd->info->nports == 2 || (brd->info->flags & MXSER_HAS2)) {
2406 irq = regs[9] & 0xF000;
2407 irq = irq | (irq >> 4);
2408 if (irq != (regs[9] & 0xFF00))
2409 return MXSER_ERR_IRQ_CONFLIT;
2410 } else if (brd->info->nports == 4) {
2411 irq = regs[9] & 0xF000;
2412 irq = irq | (irq >> 4);
2413 irq = irq | (irq >> 8);
2414 if (irq != regs[9])
2415 return MXSER_ERR_IRQ_CONFLIT;
2416 } else if (brd->info->nports == 8) {
2417 irq = regs[9] & 0xF000;
2418 irq = irq | (irq >> 4);
2419 irq = irq | (irq >> 8);
2420 if ((irq != regs[9]) || (irq != regs[10]))
2421 return MXSER_ERR_IRQ_CONFLIT;
2422 }
2423
2424 if (!irq)
2425 return MXSER_ERR_IRQ;
2426 brd->irq = ((int)(irq & 0xF000) >> 12);
2427 for (i = 0; i < 8; i++)
2428 brd->ports[i].ioaddr = (int) regs[i + 1] & 0xFFF8;
2429 if ((regs[12] & 0x80) == 0)
2430 return MXSER_ERR_VECTOR;
2431 brd->vector = (int)regs[11]; /* interrupt vector */
2432 if (id == 1)
2433 brd->vector_mask = 0x00FF;
2434 else
2435 brd->vector_mask = 0x000F;
2436 for (i = 7, bits = 0x0100; i >= 0; i--, bits <<= 1) {
2437 if (regs[12] & bits) {
2438 brd->ports[i].baud_base = 921600;
2439 brd->ports[i].max_baud = 921600;
2440 } else {
2441 brd->ports[i].baud_base = 115200;
2442 brd->ports[i].max_baud = 115200;
2443 }
2444 }
2445 scratch2 = inb(cap + UART_LCR) & (~UART_LCR_DLAB);
2446 outb(scratch2 | UART_LCR_DLAB, cap + UART_LCR);
2447 outb(0, cap + UART_EFR); /* EFR is the same as FCR */
2448 outb(scratch2, cap + UART_LCR);
2449 outb(UART_FCR_ENABLE_FIFO, cap + UART_FCR);
2450 scratch = inb(cap + UART_IIR);
2451
2452 if (scratch & 0xC0)
2453 brd->uart_type = PORT_16550A;
2454 else
2455 brd->uart_type = PORT_16450;
2456 if (!request_region(brd->ports[0].ioaddr, 8 * brd->info->nports,
2457 "mxser(IO)"))
2458 return MXSER_ERR_IOADDR;
2459 if (!request_region(brd->vector, 1, "mxser(vector)")) {
2460 release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
2461 return MXSER_ERR_VECTOR;
2462 }
2463 return brd->info->nports;
2464}
2465
2466static int __devinit mxser_probe(struct pci_dev *pdev,
2467 const struct pci_device_id *ent)
2468{
2469#ifdef CONFIG_PCI
2470 struct mxser_board *brd;
2471 unsigned int i, j;
2472 unsigned long ioaddress;
2473 int retval = -EINVAL;
2474
2475 for (i = 0; i < MXSER_BOARDS; i++)
2476 if (mxser_boards[i].info == NULL)
2477 break;
2478
2479 if (i >= MXSER_BOARDS) {
2480 printk(KERN_ERR "Too many Smartio/Industio family boards found "
2481 "(maximum %d), board not configured\n", MXSER_BOARDS);
2482 goto err;
2483 }
2484
2485 brd = &mxser_boards[i];
2486 brd->idx = i * MXSER_PORTS_PER_BOARD;
2487 printk(KERN_INFO "Found MOXA %s board (BusNo=%d, DevNo=%d)\n",
2488 mxser_cards[ent->driver_data].name,
2489 pdev->bus->number, PCI_SLOT(pdev->devfn));
2490
2491 retval = pci_enable_device(pdev);
2492 if (retval) {
2493 printk(KERN_ERR "Moxa SmartI/O PCI enable fail !\n");
2494 goto err;
2495 }
2496
2497 /* io address */
2498 ioaddress = pci_resource_start(pdev, 2);
2499 retval = pci_request_region(pdev, 2, "mxser(IO)");
2500 if (retval)
2501 goto err;
2502
2503 brd->info = &mxser_cards[ent->driver_data];
2504 for (i = 0; i < brd->info->nports; i++)
2505 brd->ports[i].ioaddr = ioaddress + 8 * i;
2506
2507 /* vector */
2508 ioaddress = pci_resource_start(pdev, 3);
2509 retval = pci_request_region(pdev, 3, "mxser(vector)");
2510 if (retval)
2511 goto err_relio;
2512 brd->vector = ioaddress;
2513
2514 /* irq */
2515 brd->irq = pdev->irq;
2516
2517 brd->chip_flag = CheckIsMoxaMust(brd->ports[0].ioaddr);
2518 brd->uart_type = PORT_16550A;
2519 brd->vector_mask = 0;
2520
2521 for (i = 0; i < brd->info->nports; i++) {
2522 for (j = 0; j < UART_INFO_NUM; j++) {
2523 if (Gpci_uart_info[j].type == brd->chip_flag) {
2524 brd->ports[i].max_baud =
2525 Gpci_uart_info[j].max_baud;
2526
2527 /* exception....CP-102 */
2528 if (brd->info->flags & MXSER_HIGHBAUD)
2529 brd->ports[i].max_baud = 921600;
2530 break;
2531 }
2532 }
2533 }
2534
2535 if (brd->chip_flag == MOXA_MUST_MU860_HWID) {
2536 for (i = 0; i < brd->info->nports; i++) {
2537 if (i < 4)
2538 brd->ports[i].opmode_ioaddr = ioaddress + 4;
2539 else
2540 brd->ports[i].opmode_ioaddr = ioaddress + 0x0c;
2541 }
2542 outb(0, ioaddress + 4); /* default set to RS232 mode */
2543 outb(0, ioaddress + 0x0c); /* default set to RS232 mode */
2544 }
2545
2546 for (i = 0; i < brd->info->nports; i++) {
2547 brd->vector_mask |= (1 << i);
2548 brd->ports[i].baud_base = 921600;
2549 }
2550
2551 /* mxser_initbrd will hook ISR. */
2552 retval = mxser_initbrd(brd, pdev);
2553 if (retval)
2554 goto err_null;
2555
2556 for (i = 0; i < brd->info->nports; i++)
2557 tty_register_device(mxvar_sdriver, brd->idx + i, &pdev->dev);
2558
2559 pci_set_drvdata(pdev, brd);
2560
2561 return 0;
2562err_relio:
2563 pci_release_region(pdev, 2);
2564err_null:
2565 brd->info = NULL;
2566err:
2567 return retval;
2568#else
2569 return -ENODEV;
2570#endif
2571}
2572
2573static void __devexit mxser_remove(struct pci_dev *pdev)
2574{
2575 struct mxser_board *brd = pci_get_drvdata(pdev);
2576 unsigned int i;
2577
2578 for (i = 0; i < brd->info->nports; i++)
2579 tty_unregister_device(mxvar_sdriver, brd->idx + i);
2580
2581 mxser_release_res(brd, pdev, 1);
2582 brd->info = NULL;
2583}
2584
2585static struct pci_driver mxser_driver = {
2586 .name = "mxser",
2587 .id_table = mxser_pcibrds,
2588 .probe = mxser_probe,
2589 .remove = __devexit_p(mxser_remove)
2590};
2591
2592static int __init mxser_module_init(void)
2593{
2594 struct mxser_board *brd;
2595 unsigned long cap;
2596 unsigned int i, m, isaloop;
2597 int retval, b;
2598
2599 pr_debug("Loading module mxser ...\n");
2600
2601 mxvar_sdriver = alloc_tty_driver(MXSER_PORTS + 1);
2602 if (!mxvar_sdriver)
2603 return -ENOMEM;
2604
2605 printk(KERN_INFO "MOXA Smartio/Industio family driver version %s\n",
2606 MXSER_VERSION);
2607
2608 /* Initialize the tty_driver structure */
2609 mxvar_sdriver->owner = THIS_MODULE;
2610 mxvar_sdriver->magic = TTY_DRIVER_MAGIC;
2611 mxvar_sdriver->name = "ttyMI";
2612 mxvar_sdriver->major = ttymajor;
2613 mxvar_sdriver->minor_start = 0;
2614 mxvar_sdriver->num = MXSER_PORTS + 1;
2615 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
2616 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
2617 mxvar_sdriver->init_termios = tty_std_termios;
2618 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
2619 mxvar_sdriver->flags = TTY_DRIVER_REAL_RAW|TTY_DRIVER_DYNAMIC_DEV;
2620 tty_set_operations(mxvar_sdriver, &mxser_ops);
2621
2622 retval = tty_register_driver(mxvar_sdriver);
2623 if (retval) {
2624 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family "
2625 "tty driver !\n");
2626 goto err_put;
2627 }
2628
2629 mxvar_diagflag = 0;
2630
2631 m = 0;
2632 /* Start finding ISA boards here */
2633 for (isaloop = 0; isaloop < 2; isaloop++)
2634 for (b = 0; b < MXSER_BOARDS && m < MXSER_BOARDS; b++) {
2635 if (!isaloop)
2636 cap = mxserBoardCAP[b]; /* predefined */
2637 else
2638 cap = ioaddr[b]; /* module param */
2639
2640 if (!cap)
2641 continue;
2642
2643 brd = &mxser_boards[m];
2644 retval = mxser_get_ISA_conf(cap, brd);
2645
2646 if (retval != 0)
2647 printk(KERN_INFO "Found MOXA %s board "
2648 "(CAP=0x%x)\n",
2649 brd->info->name, ioaddr[b]);
2650
2651 if (retval <= 0) {
2652 if (retval == MXSER_ERR_IRQ)
2653 printk(KERN_ERR "Invalid interrupt "
2654 "number, board not "
2655 "configured\n");
2656 else if (retval == MXSER_ERR_IRQ_CONFLIT)
2657 printk(KERN_ERR "Invalid interrupt "
2658 "number, board not "
2659 "configured\n");
2660 else if (retval == MXSER_ERR_VECTOR)
2661 printk(KERN_ERR "Invalid interrupt "
2662 "vector, board not "
2663 "configured\n");
2664 else if (retval == MXSER_ERR_IOADDR)
2665 printk(KERN_ERR "Invalid I/O address, "
2666 "board not configured\n");
2667
2668 brd->info = NULL;
2669 continue;
2670 }
2671
2672 /* mxser_initbrd will hook ISR. */
2673 if (mxser_initbrd(brd, NULL) < 0) {
2674 brd->info = NULL;
2675 continue;
2676 }
2677
2678 brd->idx = m * MXSER_PORTS_PER_BOARD;
2679 for (i = 0; i < brd->info->nports; i++)
2680 tty_register_device(mxvar_sdriver, brd->idx + i,
2681 NULL);
2682
2683 m++;
2684 }
2685
2686 retval = pci_register_driver(&mxser_driver);
2687 if (retval) {
2688 printk(KERN_ERR "Can't register pci driver\n");
2689 if (!m) {
2690 retval = -ENODEV;
2691 goto err_unr;
2692 } /* else: we have some ISA cards under control */
2693 }
2694
2695 pr_debug("Done.\n");
2696
2697 return 0;
2698err_unr:
2699 tty_unregister_driver(mxvar_sdriver);
2700err_put:
2701 put_tty_driver(mxvar_sdriver);
2702 return retval;
2703}
2704
2705static void __exit mxser_module_exit(void)
2706{
2707 unsigned int i, j;
2708
2709 pr_debug("Unloading module mxser ...\n");
2710
2711 pci_unregister_driver(&mxser_driver);
2712
2713 for (i = 0; i < MXSER_BOARDS; i++) /* ISA remains */
2714 if (mxser_boards[i].info != NULL)
2715 for (j = 0; j < mxser_boards[i].info->nports; j++)
2716 tty_unregister_device(mxvar_sdriver,
2717 mxser_boards[i].idx + j);
2718 tty_unregister_driver(mxvar_sdriver);
2719 put_tty_driver(mxvar_sdriver);
2720
2721 for (i = 0; i < MXSER_BOARDS; i++)
2722 if (mxser_boards[i].info != NULL)
2723 mxser_release_res(&mxser_boards[i], NULL, 1);
2724
2725 pr_debug("Done.\n");
2726}
2727
2728module_init(mxser_module_init);
2729module_exit(mxser_module_exit);
diff --git a/drivers/char/mxser_new.h b/drivers/char/mxser_new.h
deleted file mode 100644
index 844171115954..000000000000
--- a/drivers/char/mxser_new.h
+++ /dev/null
@@ -1,287 +0,0 @@
1#ifndef _MXSER_H
2#define _MXSER_H
3
4/*
5 * Semi-public control interfaces
6 */
7
8/*
9 * MOXA ioctls
10 */
11
12#define MOXA 0x400
13#define MOXA_GETDATACOUNT (MOXA + 23)
14#define MOXA_DIAGNOSE (MOXA + 50)
15#define MOXA_CHKPORTENABLE (MOXA + 60)
16#define MOXA_HighSpeedOn (MOXA + 61)
17#define MOXA_GET_MAJOR (MOXA + 63)
18#define MOXA_GETMSTATUS (MOXA + 65)
19#define MOXA_SET_OP_MODE (MOXA + 66)
20#define MOXA_GET_OP_MODE (MOXA + 67)
21
22#define RS232_MODE 0
23#define RS485_2WIRE_MODE 1
24#define RS422_MODE 2
25#define RS485_4WIRE_MODE 3
26#define OP_MODE_MASK 3
27
28#define MOXA_SDS_RSTICOUNTER (MOXA + 69)
29#define MOXA_ASPP_OQUEUE (MOXA + 70)
30#define MOXA_ASPP_MON (MOXA + 73)
31#define MOXA_ASPP_LSTATUS (MOXA + 74)
32#define MOXA_ASPP_MON_EXT (MOXA + 75)
33#define MOXA_SET_BAUD_METHOD (MOXA + 76)
34
35/* --------------------------------------------------- */
36
37#define NPPI_NOTIFY_PARITY 0x01
38#define NPPI_NOTIFY_FRAMING 0x02
39#define NPPI_NOTIFY_HW_OVERRUN 0x04
40#define NPPI_NOTIFY_SW_OVERRUN 0x08
41#define NPPI_NOTIFY_BREAK 0x10
42
43#define NPPI_NOTIFY_CTSHOLD 0x01 /* Tx hold by CTS low */
44#define NPPI_NOTIFY_DSRHOLD 0x02 /* Tx hold by DSR low */
45#define NPPI_NOTIFY_XOFFHOLD 0x08 /* Tx hold by Xoff received */
46#define NPPI_NOTIFY_XOFFXENT 0x10 /* Xoff Sent */
47
48/* follow just for Moxa Must chip define. */
49/* */
50/* when LCR register (offset 0x03) write following value, */
51/* the Must chip will enter enchance mode. And write value */
52/* on EFR (offset 0x02) bit 6,7 to change bank. */
53#define MOXA_MUST_ENTER_ENCHANCE 0xBF
54
55/* when enhance mode enable, access on general bank register */
56#define MOXA_MUST_GDL_REGISTER 0x07
57#define MOXA_MUST_GDL_MASK 0x7F
58#define MOXA_MUST_GDL_HAS_BAD_DATA 0x80
59
60#define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */
61/* enchance register bank select and enchance mode setting register */
62/* when LCR register equal to 0xBF */
63#define MOXA_MUST_EFR_REGISTER 0x02
64/* enchance mode enable */
65#define MOXA_MUST_EFR_EFRB_ENABLE 0x10
66/* enchance reister bank set 0, 1, 2 */
67#define MOXA_MUST_EFR_BANK0 0x00
68#define MOXA_MUST_EFR_BANK1 0x40
69#define MOXA_MUST_EFR_BANK2 0x80
70#define MOXA_MUST_EFR_BANK3 0xC0
71#define MOXA_MUST_EFR_BANK_MASK 0xC0
72
73/* set XON1 value register, when LCR=0xBF and change to bank0 */
74#define MOXA_MUST_XON1_REGISTER 0x04
75
76/* set XON2 value register, when LCR=0xBF and change to bank0 */
77#define MOXA_MUST_XON2_REGISTER 0x05
78
79/* set XOFF1 value register, when LCR=0xBF and change to bank0 */
80#define MOXA_MUST_XOFF1_REGISTER 0x06
81
82/* set XOFF2 value register, when LCR=0xBF and change to bank0 */
83#define MOXA_MUST_XOFF2_REGISTER 0x07
84
85#define MOXA_MUST_RBRTL_REGISTER 0x04
86#define MOXA_MUST_RBRTH_REGISTER 0x05
87#define MOXA_MUST_RBRTI_REGISTER 0x06
88#define MOXA_MUST_THRTL_REGISTER 0x07
89#define MOXA_MUST_ENUM_REGISTER 0x04
90#define MOXA_MUST_HWID_REGISTER 0x05
91#define MOXA_MUST_ECR_REGISTER 0x06
92#define MOXA_MUST_CSR_REGISTER 0x07
93
94/* good data mode enable */
95#define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20
96/* only good data put into RxFIFO */
97#define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10
98
99/* enable CTS interrupt */
100#define MOXA_MUST_IER_ECTSI 0x80
101/* enable RTS interrupt */
102#define MOXA_MUST_IER_ERTSI 0x40
103/* enable Xon/Xoff interrupt */
104#define MOXA_MUST_IER_XINT 0x20
105/* enable GDA interrupt */
106#define MOXA_MUST_IER_EGDAI 0x10
107
108#define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI)
109
110/* GDA interrupt pending */
111#define MOXA_MUST_IIR_GDA 0x1C
112#define MOXA_MUST_IIR_RDA 0x04
113#define MOXA_MUST_IIR_RTO 0x0C
114#define MOXA_MUST_IIR_LSR 0x06
115
116/* recieved Xon/Xoff or specical interrupt pending */
117#define MOXA_MUST_IIR_XSC 0x10
118
119/* RTS/CTS change state interrupt pending */
120#define MOXA_MUST_IIR_RTSCTS 0x20
121#define MOXA_MUST_IIR_MASK 0x3E
122
123#define MOXA_MUST_MCR_XON_FLAG 0x40
124#define MOXA_MUST_MCR_XON_ANY 0x80
125#define MOXA_MUST_MCR_TX_XON 0x08
126
127/* software flow control on chip mask value */
128#define MOXA_MUST_EFR_SF_MASK 0x0F
129/* send Xon1/Xoff1 */
130#define MOXA_MUST_EFR_SF_TX1 0x08
131/* send Xon2/Xoff2 */
132#define MOXA_MUST_EFR_SF_TX2 0x04
133/* send Xon1,Xon2/Xoff1,Xoff2 */
134#define MOXA_MUST_EFR_SF_TX12 0x0C
135/* don't send Xon/Xoff */
136#define MOXA_MUST_EFR_SF_TX_NO 0x00
137/* Tx software flow control mask */
138#define MOXA_MUST_EFR_SF_TX_MASK 0x0C
139/* don't receive Xon/Xoff */
140#define MOXA_MUST_EFR_SF_RX_NO 0x00
141/* receive Xon1/Xoff1 */
142#define MOXA_MUST_EFR_SF_RX1 0x02
143/* receive Xon2/Xoff2 */
144#define MOXA_MUST_EFR_SF_RX2 0x01
145/* receive Xon1,Xon2/Xoff1,Xoff2 */
146#define MOXA_MUST_EFR_SF_RX12 0x03
147/* Rx software flow control mask */
148#define MOXA_MUST_EFR_SF_RX_MASK 0x03
149
150#define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \
151 u8 __oldlcr, __efr; \
152 __oldlcr = inb((baseio)+UART_LCR); \
153 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
154 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
155 __efr |= MOXA_MUST_EFR_EFRB_ENABLE; \
156 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
157 outb(__oldlcr, (baseio)+UART_LCR); \
158} while (0)
159
160#define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \
161 u8 __oldlcr, __efr; \
162 __oldlcr = inb((baseio)+UART_LCR); \
163 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
164 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
165 __efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; \
166 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
167 outb(__oldlcr, (baseio)+UART_LCR); \
168} while (0)
169
170#define SET_MOXA_MUST_XON1_VALUE(baseio, Value) do { \
171 u8 __oldlcr, __efr; \
172 __oldlcr = inb((baseio)+UART_LCR); \
173 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
174 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
175 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
176 __efr |= MOXA_MUST_EFR_BANK0; \
177 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
178 outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER); \
179 outb(__oldlcr, (baseio)+UART_LCR); \
180} while (0)
181
182#define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) do { \
183 u8 __oldlcr, __efr; \
184 __oldlcr = inb((baseio)+UART_LCR); \
185 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
186 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
187 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
188 __efr |= MOXA_MUST_EFR_BANK0; \
189 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
190 outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER); \
191 outb(__oldlcr, (baseio)+UART_LCR); \
192} while (0)
193
194#define SET_MOXA_MUST_FIFO_VALUE(info) do { \
195 u8 __oldlcr, __efr; \
196 __oldlcr = inb((info)->ioaddr+UART_LCR); \
197 outb(MOXA_MUST_ENTER_ENCHANCE, (info)->ioaddr+UART_LCR);\
198 __efr = inb((info)->ioaddr+MOXA_MUST_EFR_REGISTER); \
199 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
200 __efr |= MOXA_MUST_EFR_BANK1; \
201 outb(__efr, (info)->ioaddr+MOXA_MUST_EFR_REGISTER); \
202 outb((u8)((info)->rx_high_water), (info)->ioaddr+ \
203 MOXA_MUST_RBRTH_REGISTER); \
204 outb((u8)((info)->rx_trigger), (info)->ioaddr+ \
205 MOXA_MUST_RBRTI_REGISTER); \
206 outb((u8)((info)->rx_low_water), (info)->ioaddr+ \
207 MOXA_MUST_RBRTL_REGISTER); \
208 outb(__oldlcr, (info)->ioaddr+UART_LCR); \
209} while (0)
210
211#define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) do { \
212 u8 __oldlcr, __efr; \
213 __oldlcr = inb((baseio)+UART_LCR); \
214 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
215 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
216 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
217 __efr |= MOXA_MUST_EFR_BANK2; \
218 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
219 outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER); \
220 outb(__oldlcr, (baseio)+UART_LCR); \
221} while (0)
222
223#define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) do { \
224 u8 __oldlcr, __efr; \
225 __oldlcr = inb((baseio)+UART_LCR); \
226 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
227 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
228 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
229 __efr |= MOXA_MUST_EFR_BANK2; \
230 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
231 *pId = inb((baseio)+MOXA_MUST_HWID_REGISTER); \
232 outb(__oldlcr, (baseio)+UART_LCR); \
233} while (0)
234
235#define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) do { \
236 u8 __oldlcr, __efr; \
237 __oldlcr = inb((baseio)+UART_LCR); \
238 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
239 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
240 __efr &= ~MOXA_MUST_EFR_SF_MASK; \
241 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
242 outb(__oldlcr, (baseio)+UART_LCR); \
243} while (0)
244
245#define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \
246 u8 __oldlcr, __efr; \
247 __oldlcr = inb((baseio)+UART_LCR); \
248 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
249 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
250 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
251 __efr |= MOXA_MUST_EFR_SF_TX1; \
252 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
253 outb(__oldlcr, (baseio)+UART_LCR); \
254} while (0)
255
256#define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \
257 u8 __oldlcr, __efr; \
258 __oldlcr = inb((baseio)+UART_LCR); \
259 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
260 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
261 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
262 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
263 outb(__oldlcr, (baseio)+UART_LCR); \
264} while (0)
265
266#define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \
267 u8 __oldlcr, __efr; \
268 __oldlcr = inb((baseio)+UART_LCR); \
269 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
270 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
271 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
272 __efr |= MOXA_MUST_EFR_SF_RX1; \
273 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
274 outb(__oldlcr, (baseio)+UART_LCR); \
275} while (0)
276
277#define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \
278 u8 __oldlcr, __efr; \
279 __oldlcr = inb((baseio)+UART_LCR); \
280 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
281 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
282 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
283 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
284 outb(__oldlcr, (baseio)+UART_LCR); \
285} while (0)
286
287#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 14:40:42 -0500