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authorLinus Torvalds <torvalds@linux-foundation.org>2012-12-17 11:26:17 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2012-12-17 11:26:17 -0500
commit3c2e81ef344a90bb0a39d84af6878b4aeff568a2 (patch)
treebd8c8b23466174899d2fe4d35af6e1e838edb068 /drivers/char
parent221392c3ad0432e39fd74a349364f66cb0ed78f6 (diff)
parent55bde6b1442fed8af67b92d21acce67db454c9f9 (diff)
Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
Pull DRM updates from Dave Airlie: "This is the one and only next pull for 3.8, we had a regression we found last week, so I was waiting for that to resolve itself, and I ended up with some Intel fixes on top as well. Highlights: - new driver: nvidia tegra 20/30/hdmi support - radeon: add support for previously unused DMA engines, more HDMI regs, eviction speeds ups and fixes - i915: HSW support enable, agp removal on GEN6, seqno wrapping - exynos: IPP subsystem support (image post proc), HDMI - nouveau: display class reworking, nv20->40 z compression - ttm: start of locking fixes, rcu usage for lookups, - core: documentation updates, docbook integration, monotonic clock usage, move from connector to object properties" * 'drm-next' of git://people.freedesktop.org/~airlied/linux: (590 commits) drm/exynos: add gsc ipp driver drm/exynos: add rotator ipp driver drm/exynos: add fimc ipp driver drm/exynos: add iommu support for ipp drm/exynos: add ipp subsystem drm/exynos: support device tree for fimd radeon: fix regression with eviction since evict caching changes drm/radeon: add more pedantic checks in the CP DMA checker drm/radeon: bump version for CS ioctl support for async DMA drm/radeon: enable the async DMA rings in the CS ioctl drm/radeon: add VM CS parser support for async DMA on cayman/TN/SI drm/radeon/kms: add evergreen/cayman CS parser for async DMA (v2) drm/radeon/kms: add 6xx/7xx CS parser for async DMA (v2) drm/radeon: fix htile buffer size computation for command stream checker drm/radeon: fix fence locking in the pageflip callback drm/radeon: make indirect register access concurrency-safe drm/radeon: add W|RREG32_IDX for MM_INDEX|DATA based mmio accesss drm/exynos: support extended screen coordinate of fimd drm/exynos: fix x, y coordinates for right bottom pixel drm/exynos: fix fb offset calculation for plane ...
Diffstat (limited to 'drivers/char')
-rw-r--r--drivers/char/agp/intel-agp.h91
-rw-r--r--drivers/char/agp/intel-gtt.c320
2 files changed, 12 insertions, 399 deletions
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 6ec0fff79bc2..1042c1b90376 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -62,12 +62,6 @@
62#define I810_PTE_LOCAL 0x00000002 62#define I810_PTE_LOCAL 0x00000002
63#define I810_PTE_VALID 0x00000001 63#define I810_PTE_VALID 0x00000001
64#define I830_PTE_SYSTEM_CACHED 0x00000006 64#define I830_PTE_SYSTEM_CACHED 0x00000006
65/* GT PTE cache control fields */
66#define GEN6_PTE_UNCACHED 0x00000002
67#define HSW_PTE_UNCACHED 0x00000000
68#define GEN6_PTE_LLC 0x00000004
69#define GEN6_PTE_LLC_MLC 0x00000006
70#define GEN6_PTE_GFDT 0x00000008
71 65
72#define I810_SMRAM_MISCC 0x70 66#define I810_SMRAM_MISCC 0x70
73#define I810_GFX_MEM_WIN_SIZE 0x00010000 67#define I810_GFX_MEM_WIN_SIZE 0x00010000
@@ -97,7 +91,6 @@
97#define G4x_GMCH_SIZE_VT_2M (G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN) 91#define G4x_GMCH_SIZE_VT_2M (G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN)
98 92
99#define GFX_FLSH_CNTL 0x2170 /* 915+ */ 93#define GFX_FLSH_CNTL 0x2170 /* 915+ */
100#define GFX_FLSH_CNTL_VLV 0x101008
101 94
102#define I810_DRAM_CTL 0x3000 95#define I810_DRAM_CTL 0x3000
103#define I810_DRAM_ROW_0 0x00000001 96#define I810_DRAM_ROW_0 0x00000001
@@ -148,29 +141,6 @@
148#define INTEL_I7505_AGPCTRL 0x70 141#define INTEL_I7505_AGPCTRL 0x70
149#define INTEL_I7505_MCHCFG 0x50 142#define INTEL_I7505_MCHCFG 0x50
150 143
151#define SNB_GMCH_CTRL 0x50
152#define SNB_GMCH_GMS_STOLEN_MASK 0xF8
153#define SNB_GMCH_GMS_STOLEN_32M (1 << 3)
154#define SNB_GMCH_GMS_STOLEN_64M (2 << 3)
155#define SNB_GMCH_GMS_STOLEN_96M (3 << 3)
156#define SNB_GMCH_GMS_STOLEN_128M (4 << 3)
157#define SNB_GMCH_GMS_STOLEN_160M (5 << 3)
158#define SNB_GMCH_GMS_STOLEN_192M (6 << 3)
159#define SNB_GMCH_GMS_STOLEN_224M (7 << 3)
160#define SNB_GMCH_GMS_STOLEN_256M (8 << 3)
161#define SNB_GMCH_GMS_STOLEN_288M (9 << 3)
162#define SNB_GMCH_GMS_STOLEN_320M (0xa << 3)
163#define SNB_GMCH_GMS_STOLEN_352M (0xb << 3)
164#define SNB_GMCH_GMS_STOLEN_384M (0xc << 3)
165#define SNB_GMCH_GMS_STOLEN_416M (0xd << 3)
166#define SNB_GMCH_GMS_STOLEN_448M (0xe << 3)
167#define SNB_GMCH_GMS_STOLEN_480M (0xf << 3)
168#define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3)
169#define SNB_GTT_SIZE_0M (0 << 8)
170#define SNB_GTT_SIZE_1M (1 << 8)
171#define SNB_GTT_SIZE_2M (2 << 8)
172#define SNB_GTT_SIZE_MASK (3 << 8)
173
174/* pci devices ids */ 144/* pci devices ids */
175#define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588 145#define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
176#define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a 146#define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
@@ -219,66 +189,5 @@
219#define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062 189#define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062
220#define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a 190#define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a
221#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046 191#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046
222#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB 0x0100 /* Desktop */
223#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG 0x0102
224#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG 0x0112
225#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG 0x0122
226#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB 0x0104 /* Mobile */
227#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG 0x0106
228#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG 0x0116
229#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG 0x0126
230#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB 0x0108 /* Server */
231#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG 0x010A
232#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB 0x0150 /* Desktop */
233#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG 0x0152
234#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG 0x0162
235#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB 0x0154 /* Mobile */
236#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG 0x0156
237#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG 0x0166
238#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB 0x0158 /* Server */
239#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG 0x015A
240#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG 0x016A
241#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB 0x0F00 /* VLV1 */
242#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG 0x0F30
243#define PCI_DEVICE_ID_INTEL_HASWELL_HB 0x0400 /* Desktop */
244#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG 0x0402
245#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG 0x0412
246#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG 0x0422
247#define PCI_DEVICE_ID_INTEL_HASWELL_M_HB 0x0404 /* Mobile */
248#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG 0x0406
249#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG 0x0416
250#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG 0x0426
251#define PCI_DEVICE_ID_INTEL_HASWELL_S_HB 0x0408 /* Server */
252#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG 0x040a
253#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG 0x041a
254#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG 0x042a
255#define PCI_DEVICE_ID_INTEL_HASWELL_E_HB 0x0c04
256#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG 0x0C02
257#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG 0x0C12
258#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG 0x0C22
259#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG 0x0C06
260#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG 0x0C16
261#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG 0x0C26
262#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG 0x0C0A
263#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG 0x0C1A
264#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG 0x0C2A
265#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG 0x0A02
266#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG 0x0A12
267#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG 0x0A22
268#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG 0x0A06
269#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG 0x0A16
270#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG 0x0A26
271#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG 0x0A0A
272#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG 0x0A1A
273#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG 0x0A2A
274#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG 0x0D12
275#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG 0x0D22
276#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG 0x0D32
277#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG 0x0D16
278#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG 0x0D26
279#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG 0x0D36
280#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG 0x0D1A
281#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG 0x0D2A
282#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG 0x0D3A
283 192
284#endif 193#endif
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 38390f7c6ab6..dbd901e94ea6 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -367,62 +367,6 @@ static unsigned int intel_gtt_stolen_size(void)
367 stolen_size = 0; 367 stolen_size = 0;
368 break; 368 break;
369 } 369 }
370 } else if (INTEL_GTT_GEN == 6) {
371 /*
372 * SandyBridge has new memory control reg at 0x50.w
373 */
374 u16 snb_gmch_ctl;
375 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
376 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
377 case SNB_GMCH_GMS_STOLEN_32M:
378 stolen_size = MB(32);
379 break;
380 case SNB_GMCH_GMS_STOLEN_64M:
381 stolen_size = MB(64);
382 break;
383 case SNB_GMCH_GMS_STOLEN_96M:
384 stolen_size = MB(96);
385 break;
386 case SNB_GMCH_GMS_STOLEN_128M:
387 stolen_size = MB(128);
388 break;
389 case SNB_GMCH_GMS_STOLEN_160M:
390 stolen_size = MB(160);
391 break;
392 case SNB_GMCH_GMS_STOLEN_192M:
393 stolen_size = MB(192);
394 break;
395 case SNB_GMCH_GMS_STOLEN_224M:
396 stolen_size = MB(224);
397 break;
398 case SNB_GMCH_GMS_STOLEN_256M:
399 stolen_size = MB(256);
400 break;
401 case SNB_GMCH_GMS_STOLEN_288M:
402 stolen_size = MB(288);
403 break;
404 case SNB_GMCH_GMS_STOLEN_320M:
405 stolen_size = MB(320);
406 break;
407 case SNB_GMCH_GMS_STOLEN_352M:
408 stolen_size = MB(352);
409 break;
410 case SNB_GMCH_GMS_STOLEN_384M:
411 stolen_size = MB(384);
412 break;
413 case SNB_GMCH_GMS_STOLEN_416M:
414 stolen_size = MB(416);
415 break;
416 case SNB_GMCH_GMS_STOLEN_448M:
417 stolen_size = MB(448);
418 break;
419 case SNB_GMCH_GMS_STOLEN_480M:
420 stolen_size = MB(480);
421 break;
422 case SNB_GMCH_GMS_STOLEN_512M:
423 stolen_size = MB(512);
424 break;
425 }
426 } else { 370 } else {
427 switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 371 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
428 case I855_GMCH_GMS_STOLEN_1M: 372 case I855_GMCH_GMS_STOLEN_1M:
@@ -556,29 +500,9 @@ static unsigned int i965_gtt_total_entries(void)
556 500
557static unsigned int intel_gtt_total_entries(void) 501static unsigned int intel_gtt_total_entries(void)
558{ 502{
559 int size;
560
561 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) 503 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
562 return i965_gtt_total_entries(); 504 return i965_gtt_total_entries();
563 else if (INTEL_GTT_GEN == 6) { 505 else {
564 u16 snb_gmch_ctl;
565
566 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
567 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
568 default:
569 case SNB_GTT_SIZE_0M:
570 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
571 size = MB(0);
572 break;
573 case SNB_GTT_SIZE_1M:
574 size = MB(1);
575 break;
576 case SNB_GTT_SIZE_2M:
577 size = MB(2);
578 break;
579 }
580 return size/4;
581 } else {
582 /* On previous hardware, the GTT size was just what was 506 /* On previous hardware, the GTT size was just what was
583 * required to map the aperture. 507 * required to map the aperture.
584 */ 508 */
@@ -778,9 +702,6 @@ bool intel_enable_gtt(void)
778{ 702{
779 u8 __iomem *reg; 703 u8 __iomem *reg;
780 704
781 if (INTEL_GTT_GEN >= 6)
782 return true;
783
784 if (INTEL_GTT_GEN == 2) { 705 if (INTEL_GTT_GEN == 2) {
785 u16 gmch_ctrl; 706 u16 gmch_ctrl;
786 707
@@ -1149,85 +1070,6 @@ static void i965_write_entry(dma_addr_t addr,
1149 writel(addr | pte_flags, intel_private.gtt + entry); 1070 writel(addr | pte_flags, intel_private.gtt + entry);
1150} 1071}
1151 1072
1152static bool gen6_check_flags(unsigned int flags)
1153{
1154 return true;
1155}
1156
1157static void haswell_write_entry(dma_addr_t addr, unsigned int entry,
1158 unsigned int flags)
1159{
1160 unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
1161 unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
1162 u32 pte_flags;
1163
1164 if (type_mask == AGP_USER_MEMORY)
1165 pte_flags = HSW_PTE_UNCACHED | I810_PTE_VALID;
1166 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
1167 pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
1168 if (gfdt)
1169 pte_flags |= GEN6_PTE_GFDT;
1170 } else { /* set 'normal'/'cached' to LLC by default */
1171 pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
1172 if (gfdt)
1173 pte_flags |= GEN6_PTE_GFDT;
1174 }
1175
1176 /* gen6 has bit11-4 for physical addr bit39-32 */
1177 addr |= (addr >> 28) & 0xff0;
1178 writel(addr | pte_flags, intel_private.gtt + entry);
1179}
1180
1181static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
1182 unsigned int flags)
1183{
1184 unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
1185 unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
1186 u32 pte_flags;
1187
1188 if (type_mask == AGP_USER_MEMORY)
1189 pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
1190 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
1191 pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
1192 if (gfdt)
1193 pte_flags |= GEN6_PTE_GFDT;
1194 } else { /* set 'normal'/'cached' to LLC by default */
1195 pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
1196 if (gfdt)
1197 pte_flags |= GEN6_PTE_GFDT;
1198 }
1199
1200 /* gen6 has bit11-4 for physical addr bit39-32 */
1201 addr |= (addr >> 28) & 0xff0;
1202 writel(addr | pte_flags, intel_private.gtt + entry);
1203}
1204
1205static void valleyview_write_entry(dma_addr_t addr, unsigned int entry,
1206 unsigned int flags)
1207{
1208 unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
1209 unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
1210 u32 pte_flags;
1211
1212 if (type_mask == AGP_USER_MEMORY)
1213 pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
1214 else {
1215 pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
1216 if (gfdt)
1217 pte_flags |= GEN6_PTE_GFDT;
1218 }
1219
1220 /* gen6 has bit11-4 for physical addr bit39-32 */
1221 addr |= (addr >> 28) & 0xff0;
1222 writel(addr | pte_flags, intel_private.gtt + entry);
1223
1224 writel(1, intel_private.registers + GFX_FLSH_CNTL_VLV);
1225}
1226
1227static void gen6_cleanup(void)
1228{
1229}
1230
1231/* Certain Gen5 chipsets require require idling the GPU before 1073/* Certain Gen5 chipsets require require idling the GPU before
1232 * unmapping anything from the GTT when VT-d is enabled. 1074 * unmapping anything from the GTT when VT-d is enabled.
1233 */ 1075 */
@@ -1249,41 +1091,29 @@ static inline int needs_idle_maps(void)
1249 1091
1250static int i9xx_setup(void) 1092static int i9xx_setup(void)
1251{ 1093{
1252 u32 reg_addr; 1094 u32 reg_addr, gtt_addr;
1253 int size = KB(512); 1095 int size = KB(512);
1254 1096
1255 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr); 1097 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
1256 1098
1257 reg_addr &= 0xfff80000; 1099 reg_addr &= 0xfff80000;
1258 1100
1259 if (INTEL_GTT_GEN >= 7)
1260 size = MB(2);
1261
1262 intel_private.registers = ioremap(reg_addr, size); 1101 intel_private.registers = ioremap(reg_addr, size);
1263 if (!intel_private.registers) 1102 if (!intel_private.registers)
1264 return -ENOMEM; 1103 return -ENOMEM;
1265 1104
1266 if (INTEL_GTT_GEN == 3) { 1105 switch (INTEL_GTT_GEN) {
1267 u32 gtt_addr; 1106 case 3:
1268
1269 pci_read_config_dword(intel_private.pcidev, 1107 pci_read_config_dword(intel_private.pcidev,
1270 I915_PTEADDR, &gtt_addr); 1108 I915_PTEADDR, &gtt_addr);
1271 intel_private.gtt_bus_addr = gtt_addr; 1109 intel_private.gtt_bus_addr = gtt_addr;
1272 } else { 1110 break;
1273 u32 gtt_offset; 1111 case 5:
1274 1112 intel_private.gtt_bus_addr = reg_addr + MB(2);
1275 switch (INTEL_GTT_GEN) { 1113 break;
1276 case 5: 1114 default:
1277 case 6: 1115 intel_private.gtt_bus_addr = reg_addr + KB(512);
1278 case 7: 1116 break;
1279 gtt_offset = MB(2);
1280 break;
1281 case 4:
1282 default:
1283 gtt_offset = KB(512);
1284 break;
1285 }
1286 intel_private.gtt_bus_addr = reg_addr + gtt_offset;
1287 } 1117 }
1288 1118
1289 if (needs_idle_maps()) 1119 if (needs_idle_maps())
@@ -1395,32 +1225,6 @@ static const struct intel_gtt_driver ironlake_gtt_driver = {
1395 .check_flags = i830_check_flags, 1225 .check_flags = i830_check_flags,
1396 .chipset_flush = i9xx_chipset_flush, 1226 .chipset_flush = i9xx_chipset_flush,
1397}; 1227};
1398static const struct intel_gtt_driver sandybridge_gtt_driver = {
1399 .gen = 6,
1400 .setup = i9xx_setup,
1401 .cleanup = gen6_cleanup,
1402 .write_entry = gen6_write_entry,
1403 .dma_mask_size = 40,
1404 .check_flags = gen6_check_flags,
1405 .chipset_flush = i9xx_chipset_flush,
1406};
1407static const struct intel_gtt_driver haswell_gtt_driver = {
1408 .gen = 6,
1409 .setup = i9xx_setup,
1410 .cleanup = gen6_cleanup,
1411 .write_entry = haswell_write_entry,
1412 .dma_mask_size = 40,
1413 .check_flags = gen6_check_flags,
1414 .chipset_flush = i9xx_chipset_flush,
1415};
1416static const struct intel_gtt_driver valleyview_gtt_driver = {
1417 .gen = 7,
1418 .setup = i9xx_setup,
1419 .cleanup = gen6_cleanup,
1420 .write_entry = valleyview_write_entry,
1421 .dma_mask_size = 40,
1422 .check_flags = gen6_check_flags,
1423};
1424 1228
1425/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 1229/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1426 * driver and gmch_driver must be non-null, and find_gmch will determine 1230 * driver and gmch_driver must be non-null, and find_gmch will determine
@@ -1501,106 +1305,6 @@ static const struct intel_gtt_driver_description {
1501 "HD Graphics", &ironlake_gtt_driver }, 1305 "HD Graphics", &ironlake_gtt_driver },
1502 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 1306 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1503 "HD Graphics", &ironlake_gtt_driver }, 1307 "HD Graphics", &ironlake_gtt_driver },
1504 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1505 "Sandybridge", &sandybridge_gtt_driver },
1506 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1507 "Sandybridge", &sandybridge_gtt_driver },
1508 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1509 "Sandybridge", &sandybridge_gtt_driver },
1510 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1511 "Sandybridge", &sandybridge_gtt_driver },
1512 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1513 "Sandybridge", &sandybridge_gtt_driver },
1514 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1515 "Sandybridge", &sandybridge_gtt_driver },
1516 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1517 "Sandybridge", &sandybridge_gtt_driver },
1518 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG,
1519 "Ivybridge", &sandybridge_gtt_driver },
1520 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG,
1521 "Ivybridge", &sandybridge_gtt_driver },
1522 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG,
1523 "Ivybridge", &sandybridge_gtt_driver },
1524 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG,
1525 "Ivybridge", &sandybridge_gtt_driver },
1526 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,
1527 "Ivybridge", &sandybridge_gtt_driver },
1528 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG,
1529 "Ivybridge", &sandybridge_gtt_driver },
1530 { PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG,
1531 "ValleyView", &valleyview_gtt_driver },
1532 { PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG,
1533 "Haswell", &haswell_gtt_driver },
1534 { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,
1535 "Haswell", &haswell_gtt_driver },
1536 { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG,
1537 "Haswell", &haswell_gtt_driver },
1538 { PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,
1539 "Haswell", &haswell_gtt_driver },
1540 { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,
1541 "Haswell", &haswell_gtt_driver },
1542 { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG,
1543 "Haswell", &haswell_gtt_driver },
1544 { PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,
1545 "Haswell", &haswell_gtt_driver },
1546 { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,
1547 "Haswell", &haswell_gtt_driver },
1548 { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG,
1549 "Haswell", &haswell_gtt_driver },
1550 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG,
1551 "Haswell", &haswell_gtt_driver },
1552 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG,
1553 "Haswell", &haswell_gtt_driver },
1554 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG,
1555 "Haswell", &haswell_gtt_driver },
1556 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG,
1557 "Haswell", &haswell_gtt_driver },
1558 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG,
1559 "Haswell", &haswell_gtt_driver },
1560 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG,
1561 "Haswell", &haswell_gtt_driver },
1562 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG,
1563 "Haswell", &haswell_gtt_driver },
1564 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG,
1565 "Haswell", &haswell_gtt_driver },
1566 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG,
1567 "Haswell", &haswell_gtt_driver },
1568 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG,
1569 "Haswell", &haswell_gtt_driver },
1570 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG,
1571 "Haswell", &haswell_gtt_driver },
1572 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG,
1573 "Haswell", &haswell_gtt_driver },
1574 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG,
1575 "Haswell", &haswell_gtt_driver },
1576 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG,
1577 "Haswell", &haswell_gtt_driver },
1578 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG,
1579 "Haswell", &haswell_gtt_driver },
1580 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG,
1581 "Haswell", &haswell_gtt_driver },
1582 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG,
1583 "Haswell", &haswell_gtt_driver },
1584 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG,
1585 "Haswell", &haswell_gtt_driver },
1586 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG,
1587 "Haswell", &haswell_gtt_driver },
1588 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG,
1589 "Haswell", &haswell_gtt_driver },
1590 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG,
1591 "Haswell", &haswell_gtt_driver },
1592 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG,
1593 "Haswell", &haswell_gtt_driver },
1594 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG,
1595 "Haswell", &haswell_gtt_driver },
1596 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG,
1597 "Haswell", &haswell_gtt_driver },
1598 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG,
1599 "Haswell", &haswell_gtt_driver },
1600 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG,
1601 "Haswell", &haswell_gtt_driver },
1602 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG,
1603 "Haswell", &haswell_gtt_driver },
1604 { 0, NULL, NULL } 1308 { 0, NULL, NULL }
1605}; 1309};
1606 1310
@@ -1686,7 +1390,7 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
1686} 1390}
1687EXPORT_SYMBOL(intel_gmch_probe); 1391EXPORT_SYMBOL(intel_gmch_probe);
1688 1392
1689const struct intel_gtt *intel_gtt_get(void) 1393struct intel_gtt *intel_gtt_get(void)
1690{ 1394{
1691 return &intel_private.base; 1395 return &intel_private.base;
1692} 1396}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 22:46:08 -0500