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authorAl Viro <viro@ftp.linux.org.uk>2008-03-19 12:27:48 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-03-19 22:42:36 -0400
commit457fb605834504af294916411be128a9b21fc3f6 (patch)
tree6813daab294e40068269c0564bd8c4f479f73dbc /drivers/char/rocket_int.h
parent635440c0235537a3f0a90ed5b6f8cd8a5da862de (diff)
drivers/char/rocket portability fixes
unsigned long != __le32, TYVM, and unsigned char[4] is not guaranteed to be aligned for u32. While we are at it, sanitize sOutDW() a bit - have it take Byte_t * and handle dereferencing internally. NB: sWriteTxPrioByte() is almost certainly buggered on big-endian and is missing cpu_to_le16() on assignments to *WordPtr; I've left it alone for now. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Acked-by: "Theodore Ts'o" <tytso@mit.edu> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/char/rocket_int.h')
-rw-r--r--drivers/char/rocket_int.h83
1 files changed, 37 insertions, 46 deletions
diff --git a/drivers/char/rocket_int.h b/drivers/char/rocket_int.h
index f3a75791b811..b01d38125a8f 100644
--- a/drivers/char/rocket_int.h
+++ b/drivers/char/rocket_int.h
@@ -26,7 +26,6 @@ typedef unsigned int ByteIO_t;
26typedef unsigned int Word_t; 26typedef unsigned int Word_t;
27typedef unsigned int WordIO_t; 27typedef unsigned int WordIO_t;
28 28
29typedef unsigned long DWord_t;
30typedef unsigned int DWordIO_t; 29typedef unsigned int DWordIO_t;
31 30
32/* 31/*
@@ -38,7 +37,6 @@ typedef unsigned int DWordIO_t;
38 * instruction. 37 * instruction.
39 */ 38 */
40 39
41#ifdef ROCKET_DEBUG_IO
42static inline void sOutB(unsigned short port, unsigned char value) 40static inline void sOutB(unsigned short port, unsigned char value)
43{ 41{
44#ifdef ROCKET_DEBUG_IO 42#ifdef ROCKET_DEBUG_IO
@@ -55,12 +53,13 @@ static inline void sOutW(unsigned short port, unsigned short value)
55 outw_p(value, port); 53 outw_p(value, port);
56} 54}
57 55
58static inline void sOutDW(unsigned short port, unsigned long value) 56static inline void out32(unsigned short port, Byte_t *p)
59{ 57{
58 u32 value = le32_to_cpu(get_unaligned((__le32 *)p));
60#ifdef ROCKET_DEBUG_IO 59#ifdef ROCKET_DEBUG_IO
61 printk(KERN_DEBUG "sOutDW(%x, %lx)...\n", port, value); 60 printk(KERN_DEBUG "out32(%x, %lx)...\n", port, value);
62#endif 61#endif
63 outl_p(cpu_to_le32(value), port); 62 outl_p(value, port);
64} 63}
65 64
66static inline unsigned char sInB(unsigned short port) 65static inline unsigned char sInB(unsigned short port)
@@ -73,14 +72,6 @@ static inline unsigned short sInW(unsigned short port)
73 return inw_p(port); 72 return inw_p(port);
74} 73}
75 74
76#else /* !ROCKET_DEBUG_IO */
77#define sOutB(a, b) outb_p(b, a)
78#define sOutW(a, b) outw_p(b, a)
79#define sOutDW(port, value) outl_p(cpu_to_le32(value), port)
80#define sInB(a) (inb_p(a))
81#define sInW(a) (inw_p(a))
82#endif /* ROCKET_DEBUG_IO */
83
84/* This is used to move arrays of bytes so byte swapping isn't appropriate. */ 75/* This is used to move arrays of bytes so byte swapping isn't appropriate. */
85#define sOutStrW(port, addr, count) if (count) outsw(port, addr, count) 76#define sOutStrW(port, addr, count) if (count) outsw(port, addr, count)
86#define sInStrW(port, addr, count) if (count) insw(port, addr, count) 77#define sInStrW(port, addr, count) if (count) insw(port, addr, count)
@@ -390,7 +381,7 @@ Call: sClrBreak(ChP)
390#define sClrBreak(ChP) \ 381#define sClrBreak(ChP) \
391do { \ 382do { \
392 (ChP)->TxControl[3] &= ~SETBREAK; \ 383 (ChP)->TxControl[3] &= ~SETBREAK; \
393 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 384 out32((ChP)->IndexAddr,(ChP)->TxControl); \
394} while (0) 385} while (0)
395 386
396/*************************************************************************** 387/***************************************************************************
@@ -402,7 +393,7 @@ Call: sClrDTR(ChP)
402#define sClrDTR(ChP) \ 393#define sClrDTR(ChP) \
403do { \ 394do { \
404 (ChP)->TxControl[3] &= ~SET_DTR; \ 395 (ChP)->TxControl[3] &= ~SET_DTR; \
405 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 396 out32((ChP)->IndexAddr,(ChP)->TxControl); \
406} while (0) 397} while (0)
407 398
408/*************************************************************************** 399/***************************************************************************
@@ -415,7 +406,7 @@ Call: sClrRTS(ChP)
415do { \ 406do { \
416 if ((ChP)->rtsToggle) break; \ 407 if ((ChP)->rtsToggle) break; \
417 (ChP)->TxControl[3] &= ~SET_RTS; \ 408 (ChP)->TxControl[3] &= ~SET_RTS; \
418 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 409 out32((ChP)->IndexAddr,(ChP)->TxControl); \
419} while (0) 410} while (0)
420 411
421/*************************************************************************** 412/***************************************************************************
@@ -489,7 +480,7 @@ Call: sDisCTSFlowCtl(ChP)
489#define sDisCTSFlowCtl(ChP) \ 480#define sDisCTSFlowCtl(ChP) \
490do { \ 481do { \
491 (ChP)->TxControl[2] &= ~CTSFC_EN; \ 482 (ChP)->TxControl[2] &= ~CTSFC_EN; \
492 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 483 out32((ChP)->IndexAddr,(ChP)->TxControl); \
493} while (0) 484} while (0)
494 485
495/*************************************************************************** 486/***************************************************************************
@@ -501,7 +492,7 @@ Call: sDisIXANY(ChP)
501#define sDisIXANY(ChP) \ 492#define sDisIXANY(ChP) \
502do { \ 493do { \
503 (ChP)->R[0x0e] = 0x86; \ 494 (ChP)->R[0x0e] = 0x86; \
504 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \ 495 out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \
505} while (0) 496} while (0)
506 497
507/*************************************************************************** 498/***************************************************************************
@@ -515,7 +506,7 @@ Comments: Function sSetParity() can be used in place of functions sEnParity(),
515#define sDisParity(ChP) \ 506#define sDisParity(ChP) \
516do { \ 507do { \
517 (ChP)->TxControl[2] &= ~PARITY_EN; \ 508 (ChP)->TxControl[2] &= ~PARITY_EN; \
518 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 509 out32((ChP)->IndexAddr,(ChP)->TxControl); \
519} while (0) 510} while (0)
520 511
521/*************************************************************************** 512/***************************************************************************
@@ -527,7 +518,7 @@ Call: sDisRTSToggle(ChP)
527#define sDisRTSToggle(ChP) \ 518#define sDisRTSToggle(ChP) \
528do { \ 519do { \
529 (ChP)->TxControl[2] &= ~RTSTOG_EN; \ 520 (ChP)->TxControl[2] &= ~RTSTOG_EN; \
530 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 521 out32((ChP)->IndexAddr,(ChP)->TxControl); \
531 (ChP)->rtsToggle = 0; \ 522 (ChP)->rtsToggle = 0; \
532} while (0) 523} while (0)
533 524
@@ -540,7 +531,7 @@ Call: sDisRxFIFO(ChP)
540#define sDisRxFIFO(ChP) \ 531#define sDisRxFIFO(ChP) \
541do { \ 532do { \
542 (ChP)->R[0x32] = 0x0a; \ 533 (ChP)->R[0x32] = 0x0a; \
543 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \ 534 out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \
544} while (0) 535} while (0)
545 536
546/*************************************************************************** 537/***************************************************************************
@@ -567,7 +558,7 @@ Call: sDisTransmit(ChP)
567#define sDisTransmit(ChP) \ 558#define sDisTransmit(ChP) \
568do { \ 559do { \
569 (ChP)->TxControl[3] &= ~TX_ENABLE; \ 560 (ChP)->TxControl[3] &= ~TX_ENABLE; \
570 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 561 out32((ChP)->IndexAddr,(ChP)->TxControl); \
571} while (0) 562} while (0)
572 563
573/*************************************************************************** 564/***************************************************************************
@@ -579,7 +570,7 @@ Call: sDisTxSoftFlowCtl(ChP)
579#define sDisTxSoftFlowCtl(ChP) \ 570#define sDisTxSoftFlowCtl(ChP) \
580do { \ 571do { \
581 (ChP)->R[0x06] = 0x8a; \ 572 (ChP)->R[0x06] = 0x8a; \
582 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \ 573 out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
583} while (0) 574} while (0)
584 575
585/*************************************************************************** 576/***************************************************************************
@@ -604,7 +595,7 @@ Call: sEnCTSFlowCtl(ChP)
604#define sEnCTSFlowCtl(ChP) \ 595#define sEnCTSFlowCtl(ChP) \
605do { \ 596do { \
606 (ChP)->TxControl[2] |= CTSFC_EN; \ 597 (ChP)->TxControl[2] |= CTSFC_EN; \
607 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 598 out32((ChP)->IndexAddr,(ChP)->TxControl); \
608} while (0) 599} while (0)
609 600
610/*************************************************************************** 601/***************************************************************************
@@ -616,7 +607,7 @@ Call: sEnIXANY(ChP)
616#define sEnIXANY(ChP) \ 607#define sEnIXANY(ChP) \
617do { \ 608do { \
618 (ChP)->R[0x0e] = 0x21; \ 609 (ChP)->R[0x0e] = 0x21; \
619 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \ 610 out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \
620} while (0) 611} while (0)
621 612
622/*************************************************************************** 613/***************************************************************************
@@ -633,7 +624,7 @@ Warnings: Before enabling parity odd or even parity should be chosen using
633#define sEnParity(ChP) \ 624#define sEnParity(ChP) \
634do { \ 625do { \
635 (ChP)->TxControl[2] |= PARITY_EN; \ 626 (ChP)->TxControl[2] |= PARITY_EN; \
636 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 627 out32((ChP)->IndexAddr,(ChP)->TxControl); \
637} while (0) 628} while (0)
638 629
639/*************************************************************************** 630/***************************************************************************
@@ -647,10 +638,10 @@ Comments: This function will disable RTS flow control and clear the RTS
647#define sEnRTSToggle(ChP) \ 638#define sEnRTSToggle(ChP) \
648do { \ 639do { \
649 (ChP)->RxControl[2] &= ~RTSFC_EN; \ 640 (ChP)->RxControl[2] &= ~RTSFC_EN; \
650 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ 641 out32((ChP)->IndexAddr,(ChP)->RxControl); \
651 (ChP)->TxControl[2] |= RTSTOG_EN; \ 642 (ChP)->TxControl[2] |= RTSTOG_EN; \
652 (ChP)->TxControl[3] &= ~SET_RTS; \ 643 (ChP)->TxControl[3] &= ~SET_RTS; \
653 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 644 out32((ChP)->IndexAddr,(ChP)->TxControl); \
654 (ChP)->rtsToggle = 1; \ 645 (ChP)->rtsToggle = 1; \
655} while (0) 646} while (0)
656 647
@@ -663,7 +654,7 @@ Call: sEnRxFIFO(ChP)
663#define sEnRxFIFO(ChP) \ 654#define sEnRxFIFO(ChP) \
664do { \ 655do { \
665 (ChP)->R[0x32] = 0x08; \ 656 (ChP)->R[0x32] = 0x08; \
666 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \ 657 out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \
667} while (0) 658} while (0)
668 659
669/*************************************************************************** 660/***************************************************************************
@@ -684,7 +675,7 @@ Warnings: This function must be called after valid microcode has been
684#define sEnRxProcessor(ChP) \ 675#define sEnRxProcessor(ChP) \
685do { \ 676do { \
686 (ChP)->RxControl[2] |= RXPROC_EN; \ 677 (ChP)->RxControl[2] |= RXPROC_EN; \
687 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ 678 out32((ChP)->IndexAddr,(ChP)->RxControl); \
688} while (0) 679} while (0)
689 680
690/*************************************************************************** 681/***************************************************************************
@@ -708,7 +699,7 @@ Call: sEnTransmit(ChP)
708#define sEnTransmit(ChP) \ 699#define sEnTransmit(ChP) \
709do { \ 700do { \
710 (ChP)->TxControl[3] |= TX_ENABLE; \ 701 (ChP)->TxControl[3] |= TX_ENABLE; \
711 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 702 out32((ChP)->IndexAddr,(ChP)->TxControl); \
712} while (0) 703} while (0)
713 704
714/*************************************************************************** 705/***************************************************************************
@@ -720,7 +711,7 @@ Call: sEnTxSoftFlowCtl(ChP)
720#define sEnTxSoftFlowCtl(ChP) \ 711#define sEnTxSoftFlowCtl(ChP) \
721do { \ 712do { \
722 (ChP)->R[0x06] = 0xc5; \ 713 (ChP)->R[0x06] = 0xc5; \
723 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \ 714 out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
724} while (0) 715} while (0)
725 716
726/*************************************************************************** 717/***************************************************************************
@@ -927,7 +918,7 @@ Call: sSendBreak(ChP)
927#define sSendBreak(ChP) \ 918#define sSendBreak(ChP) \
928do { \ 919do { \
929 (ChP)->TxControl[3] |= SETBREAK; \ 920 (ChP)->TxControl[3] |= SETBREAK; \
930 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 921 out32((ChP)->IndexAddr,(ChP)->TxControl); \
931} while (0) 922} while (0)
932 923
933/*************************************************************************** 924/***************************************************************************
@@ -941,7 +932,7 @@ Call: sSetBaud(ChP,Divisor)
941do { \ 932do { \
942 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \ 933 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
943 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \ 934 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
944 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->BaudDiv[0]); \ 935 out32((ChP)->IndexAddr,(ChP)->BaudDiv); \
945} while (0) 936} while (0)
946 937
947/*************************************************************************** 938/***************************************************************************
@@ -953,7 +944,7 @@ Call: sSetData7(ChP)
953#define sSetData7(ChP) \ 944#define sSetData7(ChP) \
954do { \ 945do { \
955 (ChP)->TxControl[2] &= ~DATA8BIT; \ 946 (ChP)->TxControl[2] &= ~DATA8BIT; \
956 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 947 out32((ChP)->IndexAddr,(ChP)->TxControl); \
957} while (0) 948} while (0)
958 949
959/*************************************************************************** 950/***************************************************************************
@@ -965,7 +956,7 @@ Call: sSetData8(ChP)
965#define sSetData8(ChP) \ 956#define sSetData8(ChP) \
966do { \ 957do { \
967 (ChP)->TxControl[2] |= DATA8BIT; \ 958 (ChP)->TxControl[2] |= DATA8BIT; \
968 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 959 out32((ChP)->IndexAddr,(ChP)->TxControl); \
969} while (0) 960} while (0)
970 961
971/*************************************************************************** 962/***************************************************************************
@@ -977,7 +968,7 @@ Call: sSetDTR(ChP)
977#define sSetDTR(ChP) \ 968#define sSetDTR(ChP) \
978do { \ 969do { \
979 (ChP)->TxControl[3] |= SET_DTR; \ 970 (ChP)->TxControl[3] |= SET_DTR; \
980 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 971 out32((ChP)->IndexAddr,(ChP)->TxControl); \
981} while (0) 972} while (0)
982 973
983/*************************************************************************** 974/***************************************************************************
@@ -994,7 +985,7 @@ Warnings: This function has no effect unless parity is enabled with function
994#define sSetEvenParity(ChP) \ 985#define sSetEvenParity(ChP) \
995do { \ 986do { \
996 (ChP)->TxControl[2] |= EVEN_PAR; \ 987 (ChP)->TxControl[2] |= EVEN_PAR; \
997 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 988 out32((ChP)->IndexAddr,(ChP)->TxControl); \
998} while (0) 989} while (0)
999 990
1000/*************************************************************************** 991/***************************************************************************
@@ -1011,7 +1002,7 @@ Warnings: This function has no effect unless parity is enabled with function
1011#define sSetOddParity(ChP) \ 1002#define sSetOddParity(ChP) \
1012do { \ 1003do { \
1013 (ChP)->TxControl[2] &= ~EVEN_PAR; \ 1004 (ChP)->TxControl[2] &= ~EVEN_PAR; \
1014 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 1005 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1015} while (0) 1006} while (0)
1016 1007
1017/*************************************************************************** 1008/***************************************************************************
@@ -1024,7 +1015,7 @@ Call: sSetRTS(ChP)
1024do { \ 1015do { \
1025 if ((ChP)->rtsToggle) break; \ 1016 if ((ChP)->rtsToggle) break; \
1026 (ChP)->TxControl[3] |= SET_RTS; \ 1017 (ChP)->TxControl[3] |= SET_RTS; \
1027 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 1018 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1028} while (0) 1019} while (0)
1029 1020
1030/*************************************************************************** 1021/***************************************************************************
@@ -1050,7 +1041,7 @@ Comments: An interrupt will be generated when the trigger level is reached
1050do { \ 1041do { \
1051 (ChP)->RxControl[2] &= ~TRIG_MASK; \ 1042 (ChP)->RxControl[2] &= ~TRIG_MASK; \
1052 (ChP)->RxControl[2] |= LEVEL; \ 1043 (ChP)->RxControl[2] |= LEVEL; \
1053 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ 1044 out32((ChP)->IndexAddr,(ChP)->RxControl); \
1054} while (0) 1045} while (0)
1055 1046
1056/*************************************************************************** 1047/***************************************************************************
@@ -1062,7 +1053,7 @@ Call: sSetStop1(ChP)
1062#define sSetStop1(ChP) \ 1053#define sSetStop1(ChP) \
1063do { \ 1054do { \
1064 (ChP)->TxControl[2] &= ~STOP2; \ 1055 (ChP)->TxControl[2] &= ~STOP2; \
1065 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 1056 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1066} while (0) 1057} while (0)
1067 1058
1068/*************************************************************************** 1059/***************************************************************************
@@ -1074,7 +1065,7 @@ Call: sSetStop2(ChP)
1074#define sSetStop2(ChP) \ 1065#define sSetStop2(ChP) \
1075do { \ 1066do { \
1076 (ChP)->TxControl[2] |= STOP2; \ 1067 (ChP)->TxControl[2] |= STOP2; \
1077 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 1068 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1078} while (0) 1069} while (0)
1079 1070
1080/*************************************************************************** 1071/***************************************************************************
@@ -1087,7 +1078,7 @@ Call: sSetTxXOFFChar(ChP,Ch)
1087#define sSetTxXOFFChar(ChP,CH) \ 1078#define sSetTxXOFFChar(ChP,CH) \
1088do { \ 1079do { \
1089 (ChP)->R[0x07] = (CH); \ 1080 (ChP)->R[0x07] = (CH); \
1090 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \ 1081 out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
1091} while (0) 1082} while (0)
1092 1083
1093/*************************************************************************** 1084/***************************************************************************
@@ -1100,7 +1091,7 @@ Call: sSetTxXONChar(ChP,Ch)
1100#define sSetTxXONChar(ChP,CH) \ 1091#define sSetTxXONChar(ChP,CH) \
1101do { \ 1092do { \
1102 (ChP)->R[0x0b] = (CH); \ 1093 (ChP)->R[0x0b] = (CH); \
1103 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x08]); \ 1094 out32((ChP)->IndexAddr,&(ChP)->R[0x08]); \
1104} while (0) 1095} while (0)
1105 1096
1106/*************************************************************************** 1097/***************************************************************************
@@ -1113,7 +1104,7 @@ Comments: This function is used to start a Rx processor after it was
1113 will restart both the Rx processor and software input flow control. 1104 will restart both the Rx processor and software input flow control.
1114 1105
1115*/ 1106*/
1116#define sStartRxProcessor(ChP) sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0]) 1107#define sStartRxProcessor(ChP) out32((ChP)->IndexAddr,&(ChP)->R[0])
1117 1108
1118/*************************************************************************** 1109/***************************************************************************
1119Function: sWriteTxByte 1110Function: sWriteTxByte