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authorAl Viro <viro@ftp.linux.org.uk>2008-03-19 12:27:48 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-03-19 22:42:36 -0400
commit457fb605834504af294916411be128a9b21fc3f6 (patch)
tree6813daab294e40068269c0564bd8c4f479f73dbc /drivers/char/rocket.c
parent635440c0235537a3f0a90ed5b6f8cd8a5da862de (diff)
drivers/char/rocket portability fixes
unsigned long != __le32, TYVM, and unsigned char[4] is not guaranteed to be aligned for u32. While we are at it, sanitize sOutDW() a bit - have it take Byte_t * and handle dereferencing internally. NB: sWriteTxPrioByte() is almost certainly buggered on big-endian and is missing cpu_to_le16() on assignments to *WordPtr; I've left it alone for now. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Acked-by: "Theodore Ts'o" <tytso@mit.edu> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/char/rocket.c')
-rw-r--r--drivers/char/rocket.c37
1 files changed, 19 insertions, 18 deletions
diff --git a/drivers/char/rocket.c b/drivers/char/rocket.c
index 72f289279d8f..f585bc8579e9 100644
--- a/drivers/char/rocket.c
+++ b/drivers/char/rocket.c
@@ -83,6 +83,7 @@
83#include <linux/pci.h> 83#include <linux/pci.h>
84#include <asm/uaccess.h> 84#include <asm/uaccess.h>
85#include <asm/atomic.h> 85#include <asm/atomic.h>
86#include <asm/unaligned.h>
86#include <linux/bitops.h> 87#include <linux/bitops.h>
87#include <linux/spinlock.h> 88#include <linux/spinlock.h>
88#include <linux/init.h> 89#include <linux/init.h>
@@ -1312,7 +1313,7 @@ static int rp_tiocmset(struct tty_struct *tty, struct file *file,
1312 if (clear & TIOCM_DTR) 1313 if (clear & TIOCM_DTR)
1313 info->channel.TxControl[3] &= ~SET_DTR; 1314 info->channel.TxControl[3] &= ~SET_DTR;
1314 1315
1315 sOutDW(info->channel.IndexAddr, *(DWord_t *) & (info->channel.TxControl[0])); 1316 out32(info->channel.IndexAddr, info->channel.TxControl);
1316 return 0; 1317 return 0;
1317} 1318}
1318 1319
@@ -1748,7 +1749,7 @@ static int rp_write(struct tty_struct *tty,
1748 1749
1749 /* Write remaining data into the port's xmit_buf */ 1750 /* Write remaining data into the port's xmit_buf */
1750 while (1) { 1751 while (1) {
1751 if (info->tty == 0) /* Seemingly obligatory check... */ 1752 if (!info->tty) /* Seemingly obligatory check... */
1752 goto end; 1753 goto end;
1753 1754
1754 c = min(count, min(XMIT_BUF_SIZE - info->xmit_cnt - 1, XMIT_BUF_SIZE - info->xmit_head)); 1755 c = min(count, min(XMIT_BUF_SIZE - info->xmit_cnt - 1, XMIT_BUF_SIZE - info->xmit_head));
@@ -2798,7 +2799,7 @@ static int sReadAiopNumChan(WordIO_t io)
2798 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 }; 2799 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2799 2800
2800 /* write to chan 0 SRAM */ 2801 /* write to chan 0 SRAM */
2801 sOutDW((DWordIO_t) io + _INDX_ADDR, *((DWord_t *) & R[0])); 2802 out32((DWordIO_t) io + _INDX_ADDR, R);
2802 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */ 2803 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2803 x = sInW(io + _INDX_DATA); 2804 x = sInW(io + _INDX_DATA);
2804 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */ 2805 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
@@ -2864,7 +2865,7 @@ static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2864 R[1] = RData[i + 1] + 0x10 * ChanNum; 2865 R[1] = RData[i + 1] + 0x10 * ChanNum;
2865 R[2] = RData[i + 2]; 2866 R[2] = RData[i + 2];
2866 R[3] = RData[i + 3]; 2867 R[3] = RData[i + 3];
2867 sOutDW(ChP->IndexAddr, *((DWord_t *) & R[0])); 2868 out32(ChP->IndexAddr, R);
2868 } 2869 }
2869 2870
2870 ChR = ChP->R; 2871 ChR = ChP->R;
@@ -2887,43 +2888,43 @@ static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2887 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8); 2888 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2888 ChP->BaudDiv[2] = (Byte_t) brd9600; 2889 ChP->BaudDiv[2] = (Byte_t) brd9600;
2889 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8); 2890 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2890 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->BaudDiv[0]); 2891 out32(ChP->IndexAddr, ChP->BaudDiv);
2891 2892
2892 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL); 2893 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2893 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8); 2894 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2894 ChP->TxControl[2] = 0; 2895 ChP->TxControl[2] = 0;
2895 ChP->TxControl[3] = 0; 2896 ChP->TxControl[3] = 0;
2896 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]); 2897 out32(ChP->IndexAddr, ChP->TxControl);
2897 2898
2898 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL); 2899 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2899 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8); 2900 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2900 ChP->RxControl[2] = 0; 2901 ChP->RxControl[2] = 0;
2901 ChP->RxControl[3] = 0; 2902 ChP->RxControl[3] = 0;
2902 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]); 2903 out32(ChP->IndexAddr, ChP->RxControl);
2903 2904
2904 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS); 2905 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2905 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8); 2906 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2906 ChP->TxEnables[2] = 0; 2907 ChP->TxEnables[2] = 0;
2907 ChP->TxEnables[3] = 0; 2908 ChP->TxEnables[3] = 0;
2908 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxEnables[0]); 2909 out32(ChP->IndexAddr, ChP->TxEnables);
2909 2910
2910 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1); 2911 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2911 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8); 2912 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2912 ChP->TxCompare[2] = 0; 2913 ChP->TxCompare[2] = 0;
2913 ChP->TxCompare[3] = 0; 2914 ChP->TxCompare[3] = 0;
2914 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxCompare[0]); 2915 out32(ChP->IndexAddr, ChP->TxCompare);
2915 2916
2916 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1); 2917 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2917 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8); 2918 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2918 ChP->TxReplace1[2] = 0; 2919 ChP->TxReplace1[2] = 0;
2919 ChP->TxReplace1[3] = 0; 2920 ChP->TxReplace1[3] = 0;
2920 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace1[0]); 2921 out32(ChP->IndexAddr, ChP->TxReplace1);
2921 2922
2922 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2); 2923 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2923 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8); 2924 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2924 ChP->TxReplace2[2] = 0; 2925 ChP->TxReplace2[2] = 0;
2925 ChP->TxReplace2[3] = 0; 2926 ChP->TxReplace2[3] = 0;
2926 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace2[0]); 2927 out32(ChP->IndexAddr, ChP->TxReplace2);
2927 2928
2928 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP; 2929 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2929 ChP->TxFIFO = ChOff + _TX_FIFO; 2930 ChP->TxFIFO = ChOff + _TX_FIFO;
@@ -2979,7 +2980,7 @@ static void sStopRxProcessor(CHANNEL_T * ChP)
2979 R[1] = ChP->R[1]; 2980 R[1] = ChP->R[1];
2980 R[2] = 0x0a; 2981 R[2] = 0x0a;
2981 R[3] = ChP->R[3]; 2982 R[3] = ChP->R[3];
2982 sOutDW(ChP->IndexAddr, *(DWord_t *) & R[0]); 2983 out32(ChP->IndexAddr, R);
2983} 2984}
2984 2985
2985/*************************************************************************** 2986/***************************************************************************
@@ -3094,13 +3095,13 @@ static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
3094 *WordPtr = ChP->TxPrioBuf; /* data byte address */ 3095 *WordPtr = ChP->TxPrioBuf; /* data byte address */
3095 3096
3096 DWBuf[2] = Data; /* data byte value */ 3097 DWBuf[2] = Data; /* data byte value */
3097 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */ 3098 out32(IndexAddr, DWBuf); /* write it out */
3098 3099
3099 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */ 3100 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
3100 3101
3101 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */ 3102 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
3102 DWBuf[3] = 0; /* priority buffer pointer */ 3103 DWBuf[3] = 0; /* priority buffer pointer */
3103 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */ 3104 out32(IndexAddr, DWBuf); /* write it out */
3104 } else { /* write it to Tx FIFO */ 3105 } else { /* write it to Tx FIFO */
3105 3106
3106 sWriteTxByte(sGetTxRxDataIO(ChP), Data); 3107 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
@@ -3147,11 +3148,11 @@ static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3147 ChP->RxControl[2] |= 3148 ChP->RxControl[2] |=
3148 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN)); 3149 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3149 3150
3150 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]); 3151 out32(ChP->IndexAddr, ChP->RxControl);
3151 3152
3152 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN); 3153 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3153 3154
3154 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]); 3155 out32(ChP->IndexAddr, ChP->TxControl);
3155 3156
3156 if (Flags & CHANINT_EN) { 3157 if (Flags & CHANINT_EN) {
3157 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum]; 3158 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
@@ -3190,9 +3191,9 @@ static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3190 3191
3191 ChP->RxControl[2] &= 3192 ChP->RxControl[2] &=
3192 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN)); 3193 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3193 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]); 3194 out32(ChP->IndexAddr, ChP->RxControl);
3194 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN); 3195 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3195 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]); 3196 out32(ChP->IndexAddr, ChP->TxControl);
3196 3197
3197 if (Flags & CHANINT_EN) { 3198 if (Flags & CHANINT_EN) {
3198 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum]; 3199 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];