diff options
| author | Andrew Morton <akpm@osdl.org> | 2006-01-11 15:17:49 -0500 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-01-11 21:42:14 -0500 |
| commit | 8d8706e2f86d28814c1b40a116ffdeca35e4c949 (patch) | |
| tree | 146567d7a807feb37a5368fbb4a6ee76d9d7bc7e /drivers/char/rio/rioboard.h | |
| parent | a9415644583ef344e02f84faf5fe24bfadb2af8e (diff) | |
[PATCH] lindent rio drivers
Run all rio files through indent -kr -i8 -bri0 -l255, as requested by Alan.
rioboot.c and rioinit.c were skipped due to worrisome lindent warnings.
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/char/rio/rioboard.h')
| -rw-r--r-- | drivers/char/rio/rioboard.h | 204 |
1 files changed, 102 insertions, 102 deletions
diff --git a/drivers/char/rio/rioboard.h b/drivers/char/rio/rioboard.h index cc6ac6a98f65..822c071a693b 100644 --- a/drivers/char/rio/rioboard.h +++ b/drivers/char/rio/rioboard.h | |||
| @@ -35,7 +35,7 @@ | |||
| 35 | 35 | ||
| 36 | */ | 36 | */ |
| 37 | 37 | ||
| 38 | #ifndef _rioboard_h /* If RIOBOARD.H not already defined */ | 38 | #ifndef _rioboard_h /* If RIOBOARD.H not already defined */ |
| 39 | #define _rioboard_h 1 | 39 | #define _rioboard_h 1 |
| 40 | 40 | ||
| 41 | /***************************************************************************** | 41 | /***************************************************************************** |
| @@ -46,7 +46,7 @@ | |||
| 46 | 46 | ||
| 47 | /* Hardware Registers... */ | 47 | /* Hardware Registers... */ |
| 48 | 48 | ||
| 49 | #define RIO_REG_BASE 0x7C00 /* Base of control registers */ | 49 | #define RIO_REG_BASE 0x7C00 /* Base of control registers */ |
| 50 | 50 | ||
| 51 | #define RIO_CONFIG RIO_REG_BASE + 0x0000 /* WRITE: Configuration Register */ | 51 | #define RIO_CONFIG RIO_REG_BASE + 0x0000 /* WRITE: Configuration Register */ |
| 52 | #define RIO_INTSET RIO_REG_BASE + 0x0080 /* WRITE: Interrupt Set */ | 52 | #define RIO_INTSET RIO_REG_BASE + 0x0080 /* WRITE: Interrupt Set */ |
| @@ -58,30 +58,30 @@ | |||
| 58 | #define RIO_RESETSTAT RIO_REG_BASE + 0x0100 /* READ: Reset Status (Jet boards only) */ | 58 | #define RIO_RESETSTAT RIO_REG_BASE + 0x0100 /* READ: Reset Status (Jet boards only) */ |
| 59 | 59 | ||
| 60 | /* RIO_VPD_ROM definitions... */ | 60 | /* RIO_VPD_ROM definitions... */ |
| 61 | #define VPD_SLX_ID1 0x00 /* READ: Specialix Identifier #1 */ | 61 | #define VPD_SLX_ID1 0x00 /* READ: Specialix Identifier #1 */ |
| 62 | #define VPD_SLX_ID2 0x01 /* READ: Specialix Identifier #2 */ | 62 | #define VPD_SLX_ID2 0x01 /* READ: Specialix Identifier #2 */ |
| 63 | #define VPD_HW_REV 0x02 /* READ: Hardware Revision */ | 63 | #define VPD_HW_REV 0x02 /* READ: Hardware Revision */ |
| 64 | #define VPD_HW_ASSEM 0x03 /* READ: Hardware Assembly Level */ | 64 | #define VPD_HW_ASSEM 0x03 /* READ: Hardware Assembly Level */ |
| 65 | #define VPD_UNIQUEID4 0x04 /* READ: Unique Identifier #4 */ | 65 | #define VPD_UNIQUEID4 0x04 /* READ: Unique Identifier #4 */ |
| 66 | #define VPD_UNIQUEID3 0x05 /* READ: Unique Identifier #3 */ | 66 | #define VPD_UNIQUEID3 0x05 /* READ: Unique Identifier #3 */ |
| 67 | #define VPD_UNIQUEID2 0x06 /* READ: Unique Identifier #2 */ | 67 | #define VPD_UNIQUEID2 0x06 /* READ: Unique Identifier #2 */ |
| 68 | #define VPD_UNIQUEID1 0x07 /* READ: Unique Identifier #1 */ | 68 | #define VPD_UNIQUEID1 0x07 /* READ: Unique Identifier #1 */ |
| 69 | #define VPD_MANU_YEAR 0x08 /* READ: Year Of Manufacture (0 = 1970) */ | 69 | #define VPD_MANU_YEAR 0x08 /* READ: Year Of Manufacture (0 = 1970) */ |
| 70 | #define VPD_MANU_WEEK 0x09 /* READ: Week Of Manufacture (0 = week 1 Jan) */ | 70 | #define VPD_MANU_WEEK 0x09 /* READ: Week Of Manufacture (0 = week 1 Jan) */ |
| 71 | #define VPD_HWFEATURE1 0x0A /* READ: Hardware Feature Byte 1 */ | 71 | #define VPD_HWFEATURE1 0x0A /* READ: Hardware Feature Byte 1 */ |
| 72 | #define VPD_HWFEATURE2 0x0B /* READ: Hardware Feature Byte 2 */ | 72 | #define VPD_HWFEATURE2 0x0B /* READ: Hardware Feature Byte 2 */ |
| 73 | #define VPD_HWFEATURE3 0x0C /* READ: Hardware Feature Byte 3 */ | 73 | #define VPD_HWFEATURE3 0x0C /* READ: Hardware Feature Byte 3 */ |
| 74 | #define VPD_HWFEATURE4 0x0D /* READ: Hardware Feature Byte 4 */ | 74 | #define VPD_HWFEATURE4 0x0D /* READ: Hardware Feature Byte 4 */ |
| 75 | #define VPD_HWFEATURE5 0x0E /* READ: Hardware Feature Byte 5 */ | 75 | #define VPD_HWFEATURE5 0x0E /* READ: Hardware Feature Byte 5 */ |
| 76 | #define VPD_OEMID 0x0F /* READ: OEM Identifier */ | 76 | #define VPD_OEMID 0x0F /* READ: OEM Identifier */ |
| 77 | #define VPD_IDENT 0x10 /* READ: Identifier string (16 bytes) */ | 77 | #define VPD_IDENT 0x10 /* READ: Identifier string (16 bytes) */ |
| 78 | #define VPD_IDENT_LEN 0x10 | 78 | #define VPD_IDENT_LEN 0x10 |
| 79 | 79 | ||
| 80 | /* VPD ROM Definitions... */ | 80 | /* VPD ROM Definitions... */ |
| 81 | #define SLX_ID1 0x4D | 81 | #define SLX_ID1 0x4D |
| 82 | #define SLX_ID2 0x98 | 82 | #define SLX_ID2 0x98 |
| 83 | 83 | ||
| 84 | #define PRODUCT_ID(a) ((a>>4)&0xF) /* Use to obtain Product ID from VPD_UNIQUEID1 */ | 84 | #define PRODUCT_ID(a) ((a>>4)&0xF) /* Use to obtain Product ID from VPD_UNIQUEID1 */ |
| 85 | 85 | ||
| 86 | #define ID_SX_ISA 0x2 | 86 | #define ID_SX_ISA 0x2 |
| 87 | #define ID_RIO_EISA 0x3 | 87 | #define ID_RIO_EISA 0x3 |
| @@ -101,7 +101,7 @@ | |||
| 101 | 101 | ||
| 102 | /* Firmware load position... */ | 102 | /* Firmware load position... */ |
| 103 | 103 | ||
| 104 | #define FIRMWARELOADADDR 0x7C00 /* Firmware is loaded _before_ this address */ | 104 | #define FIRMWARELOADADDR 0x7C00 /* Firmware is loaded _before_ this address */ |
| 105 | 105 | ||
| 106 | /***************************************************************************** | 106 | /***************************************************************************** |
| 107 | ***************************** ***************************** | 107 | ***************************** ***************************** |
| @@ -112,14 +112,14 @@ | |||
| 112 | /* Control Register Definitions... */ | 112 | /* Control Register Definitions... */ |
| 113 | #define RIO_ISA_IDENT "JBJGPGGHINSMJPJR" | 113 | #define RIO_ISA_IDENT "JBJGPGGHINSMJPJR" |
| 114 | 114 | ||
| 115 | #define RIO_ISA_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */ | 115 | #define RIO_ISA_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */ |
| 116 | #define RIO_ISA_CFG_BUSENABLE 0x02 /* Enable processor bus */ | 116 | #define RIO_ISA_CFG_BUSENABLE 0x02 /* Enable processor bus */ |
| 117 | #define RIO_ISA_CFG_IRQMASK 0x30 /* Interrupt mask */ | 117 | #define RIO_ISA_CFG_IRQMASK 0x30 /* Interrupt mask */ |
| 118 | #define RIO_ISA_CFG_IRQ12 0x10 /* Interrupt Level 12 */ | 118 | #define RIO_ISA_CFG_IRQ12 0x10 /* Interrupt Level 12 */ |
| 119 | #define RIO_ISA_CFG_IRQ11 0x20 /* Interrupt Level 11 */ | 119 | #define RIO_ISA_CFG_IRQ11 0x20 /* Interrupt Level 11 */ |
| 120 | #define RIO_ISA_CFG_IRQ9 0x30 /* Interrupt Level 9 */ | 120 | #define RIO_ISA_CFG_IRQ9 0x30 /* Interrupt Level 9 */ |
| 121 | #define RIO_ISA_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */ | 121 | #define RIO_ISA_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */ |
| 122 | #define RIO_ISA_CFG_WAITSTATE0 0x80 /* 0 waitstates, else 1 */ | 122 | #define RIO_ISA_CFG_WAITSTATE0 0x80 /* 0 waitstates, else 1 */ |
| 123 | 123 | ||
| 124 | /***************************************************************************** | 124 | /***************************************************************************** |
| 125 | ***************************** ***************************** | 125 | ***************************** ***************************** |
| @@ -130,17 +130,17 @@ | |||
| 130 | /* Control Register Definitions... */ | 130 | /* Control Register Definitions... */ |
| 131 | #define RIO_ISA2_IDENT "JBJGPGGHINSMJPJR" | 131 | #define RIO_ISA2_IDENT "JBJGPGGHINSMJPJR" |
| 132 | 132 | ||
| 133 | #define RIO_ISA2_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */ | 133 | #define RIO_ISA2_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */ |
| 134 | #define RIO_ISA2_CFG_BUSENABLE 0x02 /* Enable processor bus */ | 134 | #define RIO_ISA2_CFG_BUSENABLE 0x02 /* Enable processor bus */ |
| 135 | #define RIO_ISA2_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */ | 135 | #define RIO_ISA2_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */ |
| 136 | #define RIO_ISA2_CFG_16BIT 0x08 /* 16bit mode, else 8bit */ | 136 | #define RIO_ISA2_CFG_16BIT 0x08 /* 16bit mode, else 8bit */ |
| 137 | #define RIO_ISA2_CFG_IRQMASK 0x30 /* Interrupt mask */ | 137 | #define RIO_ISA2_CFG_IRQMASK 0x30 /* Interrupt mask */ |
| 138 | #define RIO_ISA2_CFG_IRQ15 0x00 /* Interrupt Level 15 */ | 138 | #define RIO_ISA2_CFG_IRQ15 0x00 /* Interrupt Level 15 */ |
| 139 | #define RIO_ISA2_CFG_IRQ12 0x10 /* Interrupt Level 12 */ | 139 | #define RIO_ISA2_CFG_IRQ12 0x10 /* Interrupt Level 12 */ |
| 140 | #define RIO_ISA2_CFG_IRQ11 0x20 /* Interrupt Level 11 */ | 140 | #define RIO_ISA2_CFG_IRQ11 0x20 /* Interrupt Level 11 */ |
| 141 | #define RIO_ISA2_CFG_IRQ9 0x30 /* Interrupt Level 9 */ | 141 | #define RIO_ISA2_CFG_IRQ9 0x30 /* Interrupt Level 9 */ |
| 142 | #define RIO_ISA2_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */ | 142 | #define RIO_ISA2_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */ |
| 143 | #define RIO_ISA2_CFG_WAITSTATE0 0x80 /* 0 waitstates, else 1 */ | 143 | #define RIO_ISA2_CFG_WAITSTATE0 0x80 /* 0 waitstates, else 1 */ |
| 144 | 144 | ||
| 145 | /***************************************************************************** | 145 | /***************************************************************************** |
| 146 | ***************************** ****************************** | 146 | ***************************** ****************************** |
| @@ -151,14 +151,14 @@ | |||
| 151 | /* Control Register Definitions... */ | 151 | /* Control Register Definitions... */ |
| 152 | #define RIO_ISA3_IDENT "JET HOST BY KEV#" | 152 | #define RIO_ISA3_IDENT "JET HOST BY KEV#" |
| 153 | 153 | ||
| 154 | #define RIO_ISA3_CFG_BUSENABLE 0x02 /* Enable processor bus */ | 154 | #define RIO_ISA3_CFG_BUSENABLE 0x02 /* Enable processor bus */ |
| 155 | #define RIO_ISA3_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */ | 155 | #define RIO_ISA3_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */ |
| 156 | #define RIO_ISA32_CFG_IRQMASK 0xF30 /* Interrupt mask */ | 156 | #define RIO_ISA32_CFG_IRQMASK 0xF30 /* Interrupt mask */ |
| 157 | #define RIO_ISA3_CFG_IRQ15 0xF0 /* Interrupt Level 15 */ | 157 | #define RIO_ISA3_CFG_IRQ15 0xF0 /* Interrupt Level 15 */ |
| 158 | #define RIO_ISA3_CFG_IRQ12 0xC0 /* Interrupt Level 12 */ | 158 | #define RIO_ISA3_CFG_IRQ12 0xC0 /* Interrupt Level 12 */ |
| 159 | #define RIO_ISA3_CFG_IRQ11 0xB0 /* Interrupt Level 11 */ | 159 | #define RIO_ISA3_CFG_IRQ11 0xB0 /* Interrupt Level 11 */ |
| 160 | #define RIO_ISA3_CFG_IRQ10 0xA0 /* Interrupt Level 10 */ | 160 | #define RIO_ISA3_CFG_IRQ10 0xA0 /* Interrupt Level 10 */ |
| 161 | #define RIO_ISA3_CFG_IRQ9 0x90 /* Interrupt Level 9 */ | 161 | #define RIO_ISA3_CFG_IRQ9 0x90 /* Interrupt Level 9 */ |
| 162 | 162 | ||
| 163 | /***************************************************************************** | 163 | /***************************************************************************** |
| 164 | ********************************* ******************************** | 164 | ********************************* ******************************** |
| @@ -169,9 +169,9 @@ | |||
| 169 | /* Control Register Definitions... */ | 169 | /* Control Register Definitions... */ |
| 170 | #define RIO_MCA_IDENT "JBJGPGGHINSMJPJR" | 170 | #define RIO_MCA_IDENT "JBJGPGGHINSMJPJR" |
| 171 | 171 | ||
| 172 | #define RIO_MCA_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */ | 172 | #define RIO_MCA_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */ |
| 173 | #define RIO_MCA_CFG_BUSENABLE 0x02 /* Enable processor bus */ | 173 | #define RIO_MCA_CFG_BUSENABLE 0x02 /* Enable processor bus */ |
| 174 | #define RIO_MCA_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */ | 174 | #define RIO_MCA_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */ |
| 175 | 175 | ||
| 176 | /***************************************************************************** | 176 | /***************************************************************************** |
| 177 | ******************************** ******************************** | 177 | ******************************** ******************************** |
| @@ -185,35 +185,35 @@ | |||
| 185 | #define EISA_PRODUCT_NUMBER 0xC82 | 185 | #define EISA_PRODUCT_NUMBER 0xC82 |
| 186 | #define EISA_REVISION_NUMBER 0xC83 | 186 | #define EISA_REVISION_NUMBER 0xC83 |
| 187 | #define EISA_CARD_ENABLE 0xC84 | 187 | #define EISA_CARD_ENABLE 0xC84 |
| 188 | #define EISA_VPD_UNIQUEID4 0xC88 /* READ: Unique Identifier #4 */ | 188 | #define EISA_VPD_UNIQUEID4 0xC88 /* READ: Unique Identifier #4 */ |
| 189 | #define EISA_VPD_UNIQUEID3 0xC8A /* READ: Unique Identifier #3 */ | 189 | #define EISA_VPD_UNIQUEID3 0xC8A /* READ: Unique Identifier #3 */ |
| 190 | #define EISA_VPD_UNIQUEID2 0xC90 /* READ: Unique Identifier #2 */ | 190 | #define EISA_VPD_UNIQUEID2 0xC90 /* READ: Unique Identifier #2 */ |
| 191 | #define EISA_VPD_UNIQUEID1 0xC92 /* READ: Unique Identifier #1 */ | 191 | #define EISA_VPD_UNIQUEID1 0xC92 /* READ: Unique Identifier #1 */ |
| 192 | #define EISA_VPD_MANU_YEAR 0xC98 /* READ: Year Of Manufacture (0 = 1970) */ | 192 | #define EISA_VPD_MANU_YEAR 0xC98 /* READ: Year Of Manufacture (0 = 1970) */ |
| 193 | #define EISA_VPD_MANU_WEEK 0xC9A /* READ: Week Of Manufacture (0 = week 1 Jan) */ | 193 | #define EISA_VPD_MANU_WEEK 0xC9A /* READ: Week Of Manufacture (0 = week 1 Jan) */ |
| 194 | #define EISA_MEM_ADDR_23_16 0xC00 | 194 | #define EISA_MEM_ADDR_23_16 0xC00 |
| 195 | #define EISA_MEM_ADDR_31_24 0xC01 | 195 | #define EISA_MEM_ADDR_31_24 0xC01 |
| 196 | #define EISA_RIO_CONFIG 0xC02 /* WRITE: Configuration Register */ | 196 | #define EISA_RIO_CONFIG 0xC02 /* WRITE: Configuration Register */ |
| 197 | #define EISA_RIO_INTSET 0xC03 /* WRITE: Interrupt Set */ | 197 | #define EISA_RIO_INTSET 0xC03 /* WRITE: Interrupt Set */ |
| 198 | #define EISA_RIO_INTRESET 0xC03 /* READ: Interrupt Reset */ | 198 | #define EISA_RIO_INTRESET 0xC03 /* READ: Interrupt Reset */ |
| 199 | 199 | ||
| 200 | /* Control Register Definitions... */ | 200 | /* Control Register Definitions... */ |
| 201 | #define RIO_EISA_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */ | 201 | #define RIO_EISA_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */ |
| 202 | #define RIO_EISA_CFG_LINK20 0x02 /* 20Mbps link, else 10Mbps */ | 202 | #define RIO_EISA_CFG_LINK20 0x02 /* 20Mbps link, else 10Mbps */ |
| 203 | #define RIO_EISA_CFG_BUSENABLE 0x04 /* Enable processor bus */ | 203 | #define RIO_EISA_CFG_BUSENABLE 0x04 /* Enable processor bus */ |
| 204 | #define RIO_EISA_CFG_PROCRUN 0x08 /* Processor running, else reset */ | 204 | #define RIO_EISA_CFG_PROCRUN 0x08 /* Processor running, else reset */ |
| 205 | #define RIO_EISA_CFG_IRQMASK 0xF0 /* Interrupt mask */ | 205 | #define RIO_EISA_CFG_IRQMASK 0xF0 /* Interrupt mask */ |
| 206 | #define RIO_EISA_CFG_IRQ15 0xF0 /* Interrupt Level 15 */ | 206 | #define RIO_EISA_CFG_IRQ15 0xF0 /* Interrupt Level 15 */ |
| 207 | #define RIO_EISA_CFG_IRQ14 0xE0 /* Interrupt Level 14 */ | 207 | #define RIO_EISA_CFG_IRQ14 0xE0 /* Interrupt Level 14 */ |
| 208 | #define RIO_EISA_CFG_IRQ12 0xC0 /* Interrupt Level 12 */ | 208 | #define RIO_EISA_CFG_IRQ12 0xC0 /* Interrupt Level 12 */ |
| 209 | #define RIO_EISA_CFG_IRQ11 0xB0 /* Interrupt Level 11 */ | 209 | #define RIO_EISA_CFG_IRQ11 0xB0 /* Interrupt Level 11 */ |
| 210 | #define RIO_EISA_CFG_IRQ10 0xA0 /* Interrupt Level 10 */ | 210 | #define RIO_EISA_CFG_IRQ10 0xA0 /* Interrupt Level 10 */ |
| 211 | #define RIO_EISA_CFG_IRQ9 0x90 /* Interrupt Level 9 */ | 211 | #define RIO_EISA_CFG_IRQ9 0x90 /* Interrupt Level 9 */ |
| 212 | #define RIO_EISA_CFG_IRQ7 0x70 /* Interrupt Level 7 */ | 212 | #define RIO_EISA_CFG_IRQ7 0x70 /* Interrupt Level 7 */ |
| 213 | #define RIO_EISA_CFG_IRQ6 0x60 /* Interrupt Level 6 */ | 213 | #define RIO_EISA_CFG_IRQ6 0x60 /* Interrupt Level 6 */ |
| 214 | #define RIO_EISA_CFG_IRQ5 0x50 /* Interrupt Level 5 */ | 214 | #define RIO_EISA_CFG_IRQ5 0x50 /* Interrupt Level 5 */ |
| 215 | #define RIO_EISA_CFG_IRQ4 0x40 /* Interrupt Level 4 */ | 215 | #define RIO_EISA_CFG_IRQ4 0x40 /* Interrupt Level 4 */ |
| 216 | #define RIO_EISA_CFG_IRQ3 0x30 /* Interrupt Level 3 */ | 216 | #define RIO_EISA_CFG_IRQ3 0x30 /* Interrupt Level 3 */ |
| 217 | 217 | ||
| 218 | /***************************************************************************** | 218 | /***************************************************************************** |
| 219 | ******************************** ******************************** | 219 | ******************************** ******************************** |
| @@ -224,20 +224,20 @@ | |||
| 224 | /* Control Register Definitions... */ | 224 | /* Control Register Definitions... */ |
| 225 | #define RIO_SBUS_IDENT "JBPGK#\0\0\0\0\0\0\0\0\0\0" | 225 | #define RIO_SBUS_IDENT "JBPGK#\0\0\0\0\0\0\0\0\0\0" |
| 226 | 226 | ||
| 227 | #define RIO_SBUS_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */ | 227 | #define RIO_SBUS_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */ |
| 228 | #define RIO_SBUS_CFG_BUSENABLE 0x02 /* Enable processor bus */ | 228 | #define RIO_SBUS_CFG_BUSENABLE 0x02 /* Enable processor bus */ |
| 229 | #define RIO_SBUS_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */ | 229 | #define RIO_SBUS_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */ |
| 230 | #define RIO_SBUS_CFG_IRQMASK 0x38 /* Interrupt mask */ | 230 | #define RIO_SBUS_CFG_IRQMASK 0x38 /* Interrupt mask */ |
| 231 | #define RIO_SBUS_CFG_IRQNONE 0x00 /* No Interrupt */ | 231 | #define RIO_SBUS_CFG_IRQNONE 0x00 /* No Interrupt */ |
| 232 | #define RIO_SBUS_CFG_IRQ7 0x38 /* Interrupt Level 7 */ | 232 | #define RIO_SBUS_CFG_IRQ7 0x38 /* Interrupt Level 7 */ |
| 233 | #define RIO_SBUS_CFG_IRQ6 0x30 /* Interrupt Level 6 */ | 233 | #define RIO_SBUS_CFG_IRQ6 0x30 /* Interrupt Level 6 */ |
| 234 | #define RIO_SBUS_CFG_IRQ5 0x28 /* Interrupt Level 5 */ | 234 | #define RIO_SBUS_CFG_IRQ5 0x28 /* Interrupt Level 5 */ |
| 235 | #define RIO_SBUS_CFG_IRQ4 0x20 /* Interrupt Level 4 */ | 235 | #define RIO_SBUS_CFG_IRQ4 0x20 /* Interrupt Level 4 */ |
| 236 | #define RIO_SBUS_CFG_IRQ3 0x18 /* Interrupt Level 3 */ | 236 | #define RIO_SBUS_CFG_IRQ3 0x18 /* Interrupt Level 3 */ |
| 237 | #define RIO_SBUS_CFG_IRQ2 0x10 /* Interrupt Level 2 */ | 237 | #define RIO_SBUS_CFG_IRQ2 0x10 /* Interrupt Level 2 */ |
| 238 | #define RIO_SBUS_CFG_IRQ1 0x08 /* Interrupt Level 1 */ | 238 | #define RIO_SBUS_CFG_IRQ1 0x08 /* Interrupt Level 1 */ |
| 239 | #define RIO_SBUS_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */ | 239 | #define RIO_SBUS_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */ |
| 240 | #define RIO_SBUS_CFG_PROC25 0x80 /* 25Mhz processor clock, else 20Mhz */ | 240 | #define RIO_SBUS_CFG_PROC25 0x80 /* 25Mhz processor clock, else 20Mhz */ |
| 241 | 241 | ||
| 242 | /***************************************************************************** | 242 | /***************************************************************************** |
| 243 | ********************************* ******************************** | 243 | ********************************* ******************************** |
| @@ -248,18 +248,18 @@ | |||
| 248 | /* Control Register Definitions... */ | 248 | /* Control Register Definitions... */ |
| 249 | #define RIO_PCI_IDENT "ECDDPGJGJHJRGSK#" | 249 | #define RIO_PCI_IDENT "ECDDPGJGJHJRGSK#" |
| 250 | 250 | ||
| 251 | #define RIO_PCI_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */ | 251 | #define RIO_PCI_CFG_BOOTRAM 0x01 /* Boot from RAM, else Link */ |
| 252 | #define RIO_PCI_CFG_BUSENABLE 0x02 /* Enable processor bus */ | 252 | #define RIO_PCI_CFG_BUSENABLE 0x02 /* Enable processor bus */ |
| 253 | #define RIO_PCI_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */ | 253 | #define RIO_PCI_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */ |
| 254 | #define RIO_PCI_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */ | 254 | #define RIO_PCI_CFG_LINK20 0x40 /* 20Mbps link, else 10Mbps */ |
| 255 | #define RIO_PCI_CFG_PROC25 0x80 /* 25Mhz processor clock, else 20Mhz */ | 255 | #define RIO_PCI_CFG_PROC25 0x80 /* 25Mhz processor clock, else 20Mhz */ |
| 256 | 256 | ||
| 257 | /* PCI Definitions... */ | 257 | /* PCI Definitions... */ |
| 258 | #define SPX_VENDOR_ID 0x11CB /* Assigned by the PCI SIG */ | 258 | #define SPX_VENDOR_ID 0x11CB /* Assigned by the PCI SIG */ |
| 259 | #define SPX_DEVICE_ID 0x8000 /* RIO bridge boards */ | 259 | #define SPX_DEVICE_ID 0x8000 /* RIO bridge boards */ |
| 260 | #define SPX_PLXDEVICE_ID 0x2000 /* PLX bridge boards */ | 260 | #define SPX_PLXDEVICE_ID 0x2000 /* PLX bridge boards */ |
| 261 | #define SPX_SUB_VENDOR_ID SPX_VENDOR_ID /* Same as vendor id */ | 261 | #define SPX_SUB_VENDOR_ID SPX_VENDOR_ID /* Same as vendor id */ |
| 262 | #define RIO_SUB_SYS_ID 0x0800 /* RIO PCI board */ | 262 | #define RIO_SUB_SYS_ID 0x0800 /* RIO PCI board */ |
| 263 | 263 | ||
| 264 | /***************************************************************************** | 264 | /***************************************************************************** |
| 265 | ***************************** ****************************** | 265 | ***************************** ****************************** |
| @@ -270,11 +270,11 @@ | |||
| 270 | /* Control Register Definitions... */ | 270 | /* Control Register Definitions... */ |
| 271 | #define RIO_PCI2_IDENT "JET HOST BY KEV#" | 271 | #define RIO_PCI2_IDENT "JET HOST BY KEV#" |
| 272 | 272 | ||
| 273 | #define RIO_PCI2_CFG_BUSENABLE 0x02 /* Enable processor bus */ | 273 | #define RIO_PCI2_CFG_BUSENABLE 0x02 /* Enable processor bus */ |
| 274 | #define RIO_PCI2_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */ | 274 | #define RIO_PCI2_CFG_INTENABLE 0x04 /* Interrupt enable, else disable */ |
| 275 | 275 | ||
| 276 | /* PCI Definitions... */ | 276 | /* PCI Definitions... */ |
| 277 | #define RIO2_SUB_SYS_ID 0x0100 /* RIO (Jet) PCI board */ | 277 | #define RIO2_SUB_SYS_ID 0x0100 /* RIO (Jet) PCI board */ |
| 278 | 278 | ||
| 279 | #endif /*_rioboard_h */ | 279 | #endif /*_rioboard_h */ |
| 280 | 280 | ||