diff options
author | Alan Cox <alan@lxorguk.ukuu.org.uk> | 2006-02-03 06:04:07 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-02-03 11:32:04 -0500 |
commit | 84542838a3829f34630c589c1eb570656c455a1c (patch) | |
tree | 401218ce579c354427522d116f67d0bc1cb706ed /drivers/char/rio/cirrus.h | |
parent | 47ba87e0b1269698801310bfd1716b0538282405 (diff) |
[PATCH] rio cleanups
INKERNEL is always defined
HOST is never defined
therefore RTA is also never defined
Strip the relevant garbage out of the headers on this basis.
Signed-off-by: Alan Cox <alan@redhat.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/char/rio/cirrus.h')
-rw-r--r-- | drivers/char/rio/cirrus.h | 142 |
1 files changed, 0 insertions, 142 deletions
diff --git a/drivers/char/rio/cirrus.h b/drivers/char/rio/cirrus.h index 217ff09f2fa1..89bd94eb45be 100644 --- a/drivers/char/rio/cirrus.h +++ b/drivers/char/rio/cirrus.h | |||
@@ -40,148 +40,6 @@ | |||
40 | #endif | 40 | #endif |
41 | #define _cirrus_h 1 | 41 | #define _cirrus_h 1 |
42 | 42 | ||
43 | #ifdef RTA | ||
44 | #define TO_UART RX | ||
45 | #define TO_DRIVER TX | ||
46 | #endif | ||
47 | |||
48 | #ifdef HOST | ||
49 | #define TO_UART TX | ||
50 | #define TO_DRIVER RX | ||
51 | #endif | ||
52 | #ifdef RTA | ||
53 | /* Miscellaneous defines for CIRRUS addresses and related logic for | ||
54 | interrupts etc. | ||
55 | */ | ||
56 | #define MAP(a) ((short *)(cirrus_base + (a))) | ||
57 | #define outp(a,b) (*MAP (a) =(b)) | ||
58 | #define inp(a) ((*MAP (a)) & 0xff) | ||
59 | #define CIRRUS_FIRST (short*)0x7300 | ||
60 | #define CIRRUS_SECOND (short*)0x7200 | ||
61 | #define CIRRUS_THIRD (short*)0x7100 | ||
62 | #define CIRRUS_FOURTH (short*)0x7000 | ||
63 | #define PORTS_ON_CIRRUS 4 | ||
64 | #define CIRRUS_FIFO_SIZE 12 | ||
65 | #define SPACE 0x20 | ||
66 | #define TAB 0x09 | ||
67 | #define LINE_FEED 0x0a | ||
68 | #define CARRIAGE_RETURN 0x0d | ||
69 | #define BACKSPACE 0x08 | ||
70 | #define SPACES_IN_TABS 8 | ||
71 | #define SEND_ESCAPE 0x00 | ||
72 | #define START_BREAK 0x81 | ||
73 | #define TIMER_TICK 0x82 | ||
74 | #define STOP_BREAK 0x83 | ||
75 | #define BASE(a) ((a) < 4 ? (short*)CIRRUS_FIRST : ((a) < 8 ? (short *)CIRRUS_SECOND : ((a) < 12 ? (short*)CIRRUS_THIRD : (short *)CIRRUS_FOURTH))) | ||
76 | #define txack1 ((short *)0x7104) | ||
77 | #define rxack1 ((short *)0x7102) | ||
78 | #define mdack1 ((short *)0x7106) | ||
79 | #define txack2 ((short *)0x7006) | ||
80 | #define rxack2 ((short *)0x7004) | ||
81 | #define mdack2 ((short *)0x7100) | ||
82 | #define int_latch ((short *) 0x7800) | ||
83 | #define int_status ((short *) 0x7c00) | ||
84 | #define tx1_pending 0x20 | ||
85 | #define rx1_pending 0x10 | ||
86 | #define md1_pending 0x40 | ||
87 | #define tx2_pending 0x02 | ||
88 | #define rx2_pending 0x01 | ||
89 | #define md2_pending 0x40 | ||
90 | #define module1_bits 0x07 | ||
91 | #define module1_modern 0x08 | ||
92 | #define module2_bits 0x70 | ||
93 | #define module2_modern 0x80 | ||
94 | #define module_blank 0xf | ||
95 | #define rs232_d25 0x0 | ||
96 | #define rs232_rj45 0x1 | ||
97 | #define rs422_d25 0x3 | ||
98 | #define parallel 0x5 | ||
99 | |||
100 | #define CLK0 0x00 | ||
101 | #define CLK1 0x01 | ||
102 | #define CLK2 0x02 | ||
103 | #define CLK3 0x03 | ||
104 | #define CLK4 0x04 | ||
105 | |||
106 | #define CIRRUS_REVC 0x42 | ||
107 | #define CIRRUS_REVE 0x44 | ||
108 | |||
109 | #define TURNON 1 | ||
110 | #define TURNOFF 0 | ||
111 | |||
112 | /* The list of CIRRUS registers. | ||
113 | NB. These registers are relative values on 8 bit boundaries whereas | ||
114 | on the RTA's the CIRRUS registers are on word boundaries. Use pointer | ||
115 | arithmetic (short *) to obtain the real addresses required */ | ||
116 | #define ccr 0x05 /* Channel Command Register */ | ||
117 | #define ier 0x06 /* Interrupt Enable Register */ | ||
118 | #define cor1 0x08 /* Channel Option Register 1 */ | ||
119 | #define cor2 0x09 /* Channel Option Register 2 */ | ||
120 | #define cor3 0x0a /* Channel Option Register 3 */ | ||
121 | #define cor4 0x1e /* Channel Option Register 4 */ | ||
122 | #define cor5 0x1f /* Channel Option Register 5 */ | ||
123 | |||
124 | #define ccsr 0x0b /* Channel Control Status Register */ | ||
125 | #define rdcr 0x0e /* Receive Data Count Register */ | ||
126 | #define tdcr 0x12 /* Transmit Data Count Register */ | ||
127 | #define mcor1 0x15 /* Modem Change Option Register 1 */ | ||
128 | #define mcor2 0x16 /* Modem Change Option Regsiter 2 */ | ||
129 | |||
130 | #define livr 0x18 /* Local Interrupt Vector Register */ | ||
131 | #define schr1 0x1a /* Special Character Register 1 */ | ||
132 | #define schr2 0x1b /* Special Character Register 2 */ | ||
133 | #define schr3 0x1c /* Special Character Register 3 */ | ||
134 | #define schr4 0x1d /* Special Character Register 4 */ | ||
135 | |||
136 | #define rtr 0x20 /* Receive Timer Register */ | ||
137 | #define rtpr 0x21 /* Receive Timeout Period Register */ | ||
138 | #define lnc 0x24 /* Lnext character */ | ||
139 | |||
140 | #define rivr 0x43 /* Receive Interrupt Vector Register */ | ||
141 | #define tivr 0x42 /* Transmit Interrupt Vector Register */ | ||
142 | #define mivr 0x41 /* Modem Interrupt Vector Register */ | ||
143 | #define gfrcr 0x40 /* Global Firmware Revision code Reg */ | ||
144 | #define ricr 0x44 /* Receive Interrupting Channel Reg */ | ||
145 | #define ticr 0x45 /* Transmit Interrupting Channel Reg */ | ||
146 | #define micr 0x46 /* Modem Interrupting Channel Register */ | ||
147 | |||
148 | #define gcr 0x4b /* Global configuration register */ | ||
149 | #define misr 0x4c /* Modem interrupt status register */ | ||
150 | |||
151 | #define rbusr 0x59 | ||
152 | #define tbusr 0x5a | ||
153 | #define mbusr 0x5b | ||
154 | |||
155 | #define eoir 0x60 /* End Of Interrupt Register */ | ||
156 | #define rdsr 0x62 /* Receive Data / Status Register */ | ||
157 | #define tdr 0x63 /* Transmit Data Register */ | ||
158 | #define svrr 0x67 /* Service Request Register */ | ||
159 | |||
160 | #define car 0x68 /* Channel Access Register */ | ||
161 | #define mir 0x69 /* Modem Interrupt Register */ | ||
162 | #define tir 0x6a /* Transmit Interrupt Register */ | ||
163 | #define rir 0x6b /* Receive Interrupt Register */ | ||
164 | #define msvr1 0x6c /* Modem Signal Value Register 1 */ | ||
165 | #define msvr2 0x6d /* Modem Signal Value Register 2 */ | ||
166 | #define psvr 0x6f /* Printer Signal Value Register */ | ||
167 | |||
168 | #define tbpr 0x72 /* Transmit Baud Rate Period Register */ | ||
169 | #define tcor 0x76 /* Transmit Clock Option Register */ | ||
170 | |||
171 | #define rbpr 0x78 /* Receive Baud Rate Period Register */ | ||
172 | #define rber 0x7a /* Receive Baud Rate Extension Register */ | ||
173 | #define rcor 0x7c /* Receive Clock Option Register */ | ||
174 | #define ppr 0x7e /* Prescalar Period Register */ | ||
175 | |||
176 | /* Misc registers used for forcing the 1400 out of its reset woes */ | ||
177 | #define airl 0x6d | ||
178 | #define airm 0x6e | ||
179 | #define airh 0x6f | ||
180 | #define btcr 0x66 | ||
181 | #define mtcr 0x6c | ||
182 | #define tber 0x74 | ||
183 | |||
184 | #endif /* #ifdef RTA */ | ||
185 | 43 | ||
186 | 44 | ||
187 | /* Bit fields for particular registers */ | 45 | /* Bit fields for particular registers */ |