[PATCH] lindent rio drivers

Run all rio files through indent -kr -i8 -bri0 -l255, as requested by Alan. rioboot.c and rioinit.c were skipped due to worrisome lindent warnings. Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
author: Andrew Morton <akpm@osdl.org> 2006-01-11 15:17:49 -0500
committer: Linus Torvalds <torvalds@g5.osdl.org> 2006-01-11 21:42:14 -0500
commit: 8d8706e2f86d28814c1b40a116ffdeca35e4c949 (patch)
tree: 146567d7a807feb37a5368fbb4a6ee76d9d7bc7e /drivers/char/rio/board.h
parent: a9415644583ef344e02f84faf5fe24bfadb2af8e (diff)
1 files changed, 38 insertions, 45 deletions
diff --git a/drivers/char/rio/board.h b/drivers/char/rio/board.h
index 0b397e1c8f1c..29c980204098 100644
--- a/drivers/char/rio/board.h
+++ b/drivers/char/rio/board.h
@@ -52,63 +52,57 @@ static char *_board_h_sccs_ = "@(#)board.h	1.2";
 /*
 **      The shape of the Host Control area, at offset 0x7C00, Write Only
 */
-struct s_Ctrl
+struct s_Ctrl {
-{
+        BYTE DpCtl;             /* 7C00 */
-        BYTE    DpCtl;                          /* 7C00 */
+        BYTE Dp_Unused2_[127];
-        BYTE    Dp_Unused2_[127];
+        BYTE DpIntSet;          /* 7C80 */
-        BYTE    DpIntSet;                       /* 7C80 */
+        BYTE Dp_Unused3_[127];
-        BYTE    Dp_Unused3_[127];
+        BYTE DpTpuReset;        /* 7D00 */
-        BYTE    DpTpuReset;                     /* 7D00 */
+        BYTE Dp_Unused4_[127];
-        BYTE    Dp_Unused4_[127];
+        BYTE DpIntReset;        /* 7D80 */
-        BYTE    DpIntReset;                     /* 7D80 */
+        BYTE Dp_Unused5_[127];
-        BYTE    Dp_Unused5_[127];
 };
 /*
 ** The PROM data area on the host (0x7C00), Read Only
 */
-struct s_Prom
+struct s_Prom {
-{
+        WORD DpSlxCode[2];
-        WORD    DpSlxCode[2];
+        WORD DpRev;
-        WORD    DpRev;
+        WORD Dp_Unused6_;
-        WORD    Dp_Unused6_;
+        WORD DpUniq[4];
-        WORD    DpUniq[4];
+        WORD DpJahre;
-        WORD    DpJahre;
+        WORD DpWoche;
-        WORD    DpWoche;
+        WORD DpHwFeature[5];
-        WORD    DpHwFeature[5];
+        WORD DpOemId;
-        WORD    DpOemId;
+        WORD DpSiggy[16];
-        WORD    DpSiggy[16];
 };
 /*
 ** Union of the Ctrl and Prom areas
 */
-union u_CtrlProm        /* This is the control/PROM area (0x7C00) */
+union u_CtrlProm {              /* This is the control/PROM area (0x7C00) */
-{
+        struct s_Ctrl DpCtrl;
-        struct s_Ctrl   DpCtrl;
+        struct s_Prom DpProm;
-        struct s_Prom   DpProm;
 };
 /*
 ** The top end of memory!
 */
-struct s_ParmMapS               /* Area containing Parm Map Pointer */
+struct s_ParmMapS {             /* Area containing Parm Map Pointer */
-{
+        BYTE Dp_Unused8_[DP_PARMMAP_ADDR];
-        BYTE    Dp_Unused8_[DP_PARMMAP_ADDR];
+        WORD DpParmMapAd;
-        WORD    DpParmMapAd;
 };
-struct s_StartUpS
+struct s_StartUpS {
-{
+        BYTE Dp_Unused9_[DP_STARTUP_ADDR];
-        BYTE    Dp_Unused9_[DP_STARTUP_ADDR];
+        BYTE Dp_LongJump[0x4];
-        BYTE    Dp_LongJump[0x4];
+        BYTE Dp_Unused10_[2];
-        BYTE    Dp_Unused10_[2];
+        BYTE Dp_ShortJump[0x2];
-        BYTE    Dp_ShortJump[0x2];
 };
-union u_Sram2ParmMap    /* This is the top of memory (0x7E00-0x7FFF) */
+union u_Sram2ParmMap {          /* This is the top of memory (0x7E00-0x7FFF) */
-{
+        BYTE DpSramMem[DP_SRAM2_SIZE];
-        BYTE    DpSramMem[DP_SRAM2_SIZE];
        struct s_ParmMapS DpParmMapS;
        struct s_StartUpS DpStartUpS;
 };
@@ -116,13 +110,12 @@ union u_Sram2ParmMap	/* This is the top of memory (0x7E00-0x7FFF) */
 /*
 **      This is the DP RAM overlay.
 */
-struct DpRam
+struct DpRam {
-{
+        BYTE DpSram1[DP_SRAM1_SIZE];    /* 0000 - 7BFF */
-    BYTE                 DpSram1[DP_SRAM1_SIZE];     /* 0000 - 7BFF */
+        union u_CtrlProm DpCtrlProm;    /* 7C00 - 7DFF */
-    union u_CtrlProm     DpCtrlProm;                 /* 7C00 - 7DFF */
+        union u_Sram2ParmMap DpSram2ParmMap;    /* 7E00 - 7FFF */
-    union u_Sram2ParmMap DpSram2ParmMap;             /* 7E00 - 7FFF */
+        BYTE DpScratch[DP_SCRATCH_SIZE];        /* 8000 - 8FFF */
-    BYTE                 DpScratch[DP_SCRATCH_SIZE]; /* 8000 - 8FFF */
+        BYTE DpSram3[DP_SRAM3_SIZE];    /* 9000 - FFFF */
-    BYTE                 DpSram3[DP_SRAM3_SIZE];     /* 9000 - FFFF */
 };
 #define DpControl       DpCtrlProm.DpCtrl.DpCtl
author	Andrew Morton <akpm@osdl.org>	2006-01-11 15:17:49 -0500
committer	Linus Torvalds <torvalds@g5.osdl.org>	2006-01-11 21:42:14 -0500
commit	8d8706e2f86d28814c1b40a116ffdeca35e4c949 (patch)
tree	146567d7a807feb37a5368fbb4a6ee76d9d7bc7e /drivers/char/rio/board.h
parent	a9415644583ef344e02f84faf5fe24bfadb2af8e (diff)

diff --git a/drivers/char/rio/board.h b/drivers/char/rio/board.h index 0b397e1c8f1c..29c980204098 100644 --- a/drivers/char/rio/board.h +++ b/drivers/char/rio/board.h
@@ -52,63 +52,57 @@ static char *_board_h_sccs_ = "@(#)board.h 1.2";
52	/*	52	/*
53	** The shape of the Host Control area, at offset 0x7C00, Write Only	53	** The shape of the Host Control area, at offset 0x7C00, Write Only
54	*/	54	*/
55	struct s_Ctrl	55	struct s_Ctrl {
56	{	56	BYTE DpCtl; /* 7C00 */
57	BYTE DpCtl; /* 7C00 */	57	BYTE Dp_Unused2_[127];
58	BYTE Dp_Unused2_[127];	58	BYTE DpIntSet; /* 7C80 */
59	BYTE DpIntSet; /* 7C80 */	59	BYTE Dp_Unused3_[127];
60	BYTE Dp_Unused3_[127];	60	BYTE DpTpuReset; /* 7D00 */
61	BYTE DpTpuReset; /* 7D00 */	61	BYTE Dp_Unused4_[127];
62	BYTE Dp_Unused4_[127];	62	BYTE DpIntReset; /* 7D80 */
63	BYTE DpIntReset; /* 7D80 */	63	BYTE Dp_Unused5_[127];
64	BYTE Dp_Unused5_[127];
65	};	64	};
66		65
67	/*	66	/*
68	** The PROM data area on the host (0x7C00), Read Only	67	** The PROM data area on the host (0x7C00), Read Only
69	*/	68	*/
70	struct s_Prom	69	struct s_Prom {
71	{	70	WORD DpSlxCode[2];
72	WORD DpSlxCode[2];	71	WORD DpRev;
73	WORD DpRev;	72	WORD Dp_Unused6_;
74	WORD Dp_Unused6_;	73	WORD DpUniq[4];
75	WORD DpUniq[4];	74	WORD DpJahre;
76	WORD DpJahre;	75	WORD DpWoche;
77	WORD DpWoche;	76	WORD DpHwFeature[5];
78	WORD DpHwFeature[5];	77	WORD DpOemId;
79	WORD DpOemId;	78	WORD DpSiggy[16];
80	WORD DpSiggy[16];
81	};	79	};
82		80
83	/*	81	/*
84	** Union of the Ctrl and Prom areas	82	** Union of the Ctrl and Prom areas
85	*/	83	*/
86	union u_CtrlProm /* This is the control/PROM area (0x7C00) */	84	union u_CtrlProm { /* This is the control/PROM area (0x7C00) */
87	{	85	struct s_Ctrl DpCtrl;
88	struct s_Ctrl DpCtrl;	86	struct s_Prom DpProm;
89	struct s_Prom DpProm;
90	};	87	};
91		88
92	/*	89	/*
93	** The top end of memory!	90	** The top end of memory!
94	*/	91	*/
95	struct s_ParmMapS /* Area containing Parm Map Pointer */	92	struct s_ParmMapS { /* Area containing Parm Map Pointer */
96	{	93	BYTE Dp_Unused8_[DP_PARMMAP_ADDR];
97	BYTE Dp_Unused8_[DP_PARMMAP_ADDR];	94	WORD DpParmMapAd;
98	WORD DpParmMapAd;
99	};	95	};
100		96
101	struct s_StartUpS	97	struct s_StartUpS {
102	{	98	BYTE Dp_Unused9_[DP_STARTUP_ADDR];
103	BYTE Dp_Unused9_[DP_STARTUP_ADDR];	99	BYTE Dp_LongJump[0x4];
104	BYTE Dp_LongJump[0x4];	100	BYTE Dp_Unused10_[2];
105	BYTE Dp_Unused10_[2];	101	BYTE Dp_ShortJump[0x2];
106	BYTE Dp_ShortJump[0x2];
107	};	102	};
108		103
109	union u_Sram2ParmMap /* This is the top of memory (0x7E00-0x7FFF) */	104	union u_Sram2ParmMap { /* This is the top of memory (0x7E00-0x7FFF) */
110	{	105	BYTE DpSramMem[DP_SRAM2_SIZE];
111	BYTE DpSramMem[DP_SRAM2_SIZE];
112	struct s_ParmMapS DpParmMapS;	106	struct s_ParmMapS DpParmMapS;
113	struct s_StartUpS DpStartUpS;	107	struct s_StartUpS DpStartUpS;
114	};	108	};
@@ -116,13 +110,12 @@ union u_Sram2ParmMap /* This is the top of memory (0x7E00-0x7FFF) */
116	/*	110	/*
117	** This is the DP RAM overlay.	111	** This is the DP RAM overlay.
118	*/	112	*/
119	struct DpRam	113	struct DpRam {
120	{	114	BYTE DpSram1[DP_SRAM1_SIZE]; /* 0000 - 7BFF */
121	BYTE DpSram1[DP_SRAM1_SIZE]; /* 0000 - 7BFF */	115	union u_CtrlProm DpCtrlProm; /* 7C00 - 7DFF */
122	union u_CtrlProm DpCtrlProm; /* 7C00 - 7DFF */	116	union u_Sram2ParmMap DpSram2ParmMap; /* 7E00 - 7FFF */
123	union u_Sram2ParmMap DpSram2ParmMap; /* 7E00 - 7FFF */	117	BYTE DpScratch[DP_SCRATCH_SIZE]; /* 8000 - 8FFF */
124	BYTE DpScratch[DP_SCRATCH_SIZE]; /* 8000 - 8FFF */	118	BYTE DpSram3[DP_SRAM3_SIZE]; /* 9000 - FFFF */
125	BYTE DpSram3[DP_SRAM3_SIZE]; /* 9000 - FFFF */
126	};	119	};
127		120
128	#define DpControl DpCtrlProm.DpCtrl.DpCtl	121	#define DpControl DpCtrlProm.DpCtrl.DpCtl