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authorAlan Cox <alan@lxorguk.ukuu.org.uk>2006-03-24 06:18:24 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2006-03-24 10:33:28 -0500
commit74769abfcb430b839914f3fe91e23a4f628d9553 (patch)
treeaf7443e43f236d4d9e6c87ef777989989f1079ec /drivers/char/rio/board.h
parent10e705f83c3e796893a70fb872895ba604901166 (diff)
[PATCH] rio: more header cleanup
Strip some of the typedef mess out Remove a small subset of unused defines and the like. Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/char/rio/board.h')
-rw-r--r--drivers/char/rio/board.h58
1 files changed, 27 insertions, 31 deletions
diff --git a/drivers/char/rio/board.h b/drivers/char/rio/board.h
index 29c980204098..bdea633a9076 100644
--- a/drivers/char/rio/board.h
+++ b/drivers/char/rio/board.h
@@ -33,10 +33,6 @@
33#ifndef __rio_board_h__ 33#ifndef __rio_board_h__
34#define __rio_board_h__ 34#define __rio_board_h__
35 35
36#ifdef SCCS_LABELS
37static char *_board_h_sccs_ = "@(#)board.h 1.2";
38#endif
39
40/* 36/*
41** board.h contains the definitions for the *hardware* of the host cards. 37** board.h contains the definitions for the *hardware* of the host cards.
42** It describes the memory overlay for the dual port RAM area. 38** It describes the memory overlay for the dual port RAM area.
@@ -53,29 +49,29 @@ static char *_board_h_sccs_ = "@(#)board.h 1.2";
53** The shape of the Host Control area, at offset 0x7C00, Write Only 49** The shape of the Host Control area, at offset 0x7C00, Write Only
54*/ 50*/
55struct s_Ctrl { 51struct s_Ctrl {
56 BYTE DpCtl; /* 7C00 */ 52 u8 DpCtl; /* 7C00 */
57 BYTE Dp_Unused2_[127]; 53 u8 Dp_Unused2_[127];
58 BYTE DpIntSet; /* 7C80 */ 54 u8 DpIntSet; /* 7C80 */
59 BYTE Dp_Unused3_[127]; 55 u8 Dp_Unused3_[127];
60 BYTE DpTpuReset; /* 7D00 */ 56 u8 DpTpuReset; /* 7D00 */
61 BYTE Dp_Unused4_[127]; 57 u8 Dp_Unused4_[127];
62 BYTE DpIntReset; /* 7D80 */ 58 u8 DpIntReset; /* 7D80 */
63 BYTE Dp_Unused5_[127]; 59 u8 Dp_Unused5_[127];
64}; 60};
65 61
66/* 62/*
67** The PROM data area on the host (0x7C00), Read Only 63** The PROM data area on the host (0x7C00), Read Only
68*/ 64*/
69struct s_Prom { 65struct s_Prom {
70 WORD DpSlxCode[2]; 66 u16 DpSlxCode[2];
71 WORD DpRev; 67 u16 DpRev;
72 WORD Dp_Unused6_; 68 u16 Dp_Unused6_;
73 WORD DpUniq[4]; 69 u16 DpUniq[4];
74 WORD DpJahre; 70 u16 DpJahre;
75 WORD DpWoche; 71 u16 DpWoche;
76 WORD DpHwFeature[5]; 72 u16 DpHwFeature[5];
77 WORD DpOemId; 73 u16 DpOemId;
78 WORD DpSiggy[16]; 74 u16 DpSiggy[16];
79}; 75};
80 76
81/* 77/*
@@ -90,19 +86,19 @@ union u_CtrlProm { /* This is the control/PROM area (0x7C00) */
90** The top end of memory! 86** The top end of memory!
91*/ 87*/
92struct s_ParmMapS { /* Area containing Parm Map Pointer */ 88struct s_ParmMapS { /* Area containing Parm Map Pointer */
93 BYTE Dp_Unused8_[DP_PARMMAP_ADDR]; 89 u8 Dp_Unused8_[DP_PARMMAP_ADDR];
94 WORD DpParmMapAd; 90 u16 DpParmMapAd;
95}; 91};
96 92
97struct s_StartUpS { 93struct s_StartUpS {
98 BYTE Dp_Unused9_[DP_STARTUP_ADDR]; 94 u8 Dp_Unused9_[DP_STARTUP_ADDR];
99 BYTE Dp_LongJump[0x4]; 95 u8 Dp_LongJump[0x4];
100 BYTE Dp_Unused10_[2]; 96 u8 Dp_Unused10_[2];
101 BYTE Dp_ShortJump[0x2]; 97 u8 Dp_ShortJump[0x2];
102}; 98};
103 99
104union u_Sram2ParmMap { /* This is the top of memory (0x7E00-0x7FFF) */ 100union u_Sram2ParmMap { /* This is the top of memory (0x7E00-0x7FFF) */
105 BYTE DpSramMem[DP_SRAM2_SIZE]; 101 u8 DpSramMem[DP_SRAM2_SIZE];
106 struct s_ParmMapS DpParmMapS; 102 struct s_ParmMapS DpParmMapS;
107 struct s_StartUpS DpStartUpS; 103 struct s_StartUpS DpStartUpS;
108}; 104};
@@ -111,11 +107,11 @@ union u_Sram2ParmMap { /* This is the top of memory (0x7E00-0x7FFF) */
111** This is the DP RAM overlay. 107** This is the DP RAM overlay.
112*/ 108*/
113struct DpRam { 109struct DpRam {
114 BYTE DpSram1[DP_SRAM1_SIZE]; /* 0000 - 7BFF */ 110 u8 DpSram1[DP_SRAM1_SIZE]; /* 0000 - 7BFF */
115 union u_CtrlProm DpCtrlProm; /* 7C00 - 7DFF */ 111 union u_CtrlProm DpCtrlProm; /* 7C00 - 7DFF */
116 union u_Sram2ParmMap DpSram2ParmMap; /* 7E00 - 7FFF */ 112 union u_Sram2ParmMap DpSram2ParmMap; /* 7E00 - 7FFF */
117 BYTE DpScratch[DP_SCRATCH_SIZE]; /* 8000 - 8FFF */ 113 u8 DpScratch[DP_SCRATCH_SIZE]; /* 8000 - 8FFF */
118 BYTE DpSram3[DP_SRAM3_SIZE]; /* 9000 - FFFF */ 114 u8 DpSram3[DP_SRAM3_SIZE]; /* 9000 - FFFF */
119}; 115};
120 116
121#define DpControl DpCtrlProm.DpCtrl.DpCtl 117#define DpControl DpCtrlProm.DpCtrl.DpCtl