diff options
| author | Lucas De Marchi <lucas.demarchi@profusion.mobi> | 2011-03-30 21:57:33 -0400 |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@profusion.mobi> | 2011-03-31 10:26:23 -0400 |
| commit | 25985edcedea6396277003854657b5f3cb31a628 (patch) | |
| tree | f026e810210a2ee7290caeb737c23cb6472b7c38 /drivers/char/mbcs.h | |
| parent | 6aba74f2791287ec407e0f92487a725a25908067 (diff) | |
Fix common misspellings
Fixes generated by 'codespell' and manually reviewed.
Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
Diffstat (limited to 'drivers/char/mbcs.h')
| -rw-r--r-- | drivers/char/mbcs.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/char/mbcs.h b/drivers/char/mbcs.h index ba671589f4cb..1a36884c48b5 100644 --- a/drivers/char/mbcs.h +++ b/drivers/char/mbcs.h | |||
| @@ -36,13 +36,13 @@ | |||
| 36 | #define MBCS_RD_DMA_CTRL 0x0110 /* Read DMA Control */ | 36 | #define MBCS_RD_DMA_CTRL 0x0110 /* Read DMA Control */ |
| 37 | #define MBCS_RD_DMA_AMO_DEST 0x0118 /* Read DMA AMO Destination */ | 37 | #define MBCS_RD_DMA_AMO_DEST 0x0118 /* Read DMA AMO Destination */ |
| 38 | #define MBCS_RD_DMA_INT_DEST 0x0120 /* Read DMA Interrupt Destination */ | 38 | #define MBCS_RD_DMA_INT_DEST 0x0120 /* Read DMA Interrupt Destination */ |
| 39 | #define MBCS_RD_DMA_AUX_STAT 0x0130 /* Read DMA Auxillary Status */ | 39 | #define MBCS_RD_DMA_AUX_STAT 0x0130 /* Read DMA Auxiliary Status */ |
| 40 | #define MBCS_WR_DMA_SYS_ADDR 0x0200 /* Write DMA System Address */ | 40 | #define MBCS_WR_DMA_SYS_ADDR 0x0200 /* Write DMA System Address */ |
| 41 | #define MBCS_WR_DMA_LOC_ADDR 0x0208 /* Write DMA Local Address */ | 41 | #define MBCS_WR_DMA_LOC_ADDR 0x0208 /* Write DMA Local Address */ |
| 42 | #define MBCS_WR_DMA_CTRL 0x0210 /* Write DMA Control */ | 42 | #define MBCS_WR_DMA_CTRL 0x0210 /* Write DMA Control */ |
| 43 | #define MBCS_WR_DMA_AMO_DEST 0x0218 /* Write DMA AMO Destination */ | 43 | #define MBCS_WR_DMA_AMO_DEST 0x0218 /* Write DMA AMO Destination */ |
| 44 | #define MBCS_WR_DMA_INT_DEST 0x0220 /* Write DMA Interrupt Destination */ | 44 | #define MBCS_WR_DMA_INT_DEST 0x0220 /* Write DMA Interrupt Destination */ |
| 45 | #define MBCS_WR_DMA_AUX_STAT 0x0230 /* Write DMA Auxillary Status */ | 45 | #define MBCS_WR_DMA_AUX_STAT 0x0230 /* Write DMA Auxiliary Status */ |
| 46 | #define MBCS_ALG_AMO_DEST 0x0300 /* Algorithm AMO Destination */ | 46 | #define MBCS_ALG_AMO_DEST 0x0300 /* Algorithm AMO Destination */ |
| 47 | #define MBCS_ALG_INT_DEST 0x0308 /* Algorithm Interrupt Destination */ | 47 | #define MBCS_ALG_INT_DEST 0x0308 /* Algorithm Interrupt Destination */ |
| 48 | #define MBCS_ALG_OFFSETS 0x0310 | 48 | #define MBCS_ALG_OFFSETS 0x0310 |