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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/char/ip2/i2ellis.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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1/*******************************************************************************
2*
3* (c) 1999 by Computone Corporation
4*
5********************************************************************************
6*
7*
8* PACKAGE: Linux tty Device Driver for IntelliPort II family of multiport
9* serial I/O controllers.
10*
11* DESCRIPTION: Mainline code for the device driver
12*
13*******************************************************************************/
14//------------------------------------------------------------------------------
15// i2ellis.h
16//
17// IntelliPort-II and IntelliPort-IIEX
18//
19// Extremely
20// Low
21// Level
22// Interface
23// Services
24//
25// Structure Definitions and declarations for "ELLIS" service routines found in
26// i2ellis.c
27//
28// These routines are based on properties of the IntelliPort-II and -IIEX
29// hardware and bootstrap firmware, and are not sensitive to particular
30// conventions of any particular loadware.
31//
32// Unlike i2hw.h, which provides IRONCLAD hardware definitions, the material
33// here and in i2ellis.c is intended to provice a useful, but not required,
34// layer of insulation from the hardware specifics.
35//------------------------------------------------------------------------------
36#ifndef I2ELLIS_H /* To prevent multiple includes */
37#define I2ELLIS_H 1
38//------------------------------------------------
39// Revision History:
40//
41// 30 September 1991 MAG First Draft Started
42// 12 October 1991 ...continued...
43//
44// 20 December 1996 AKM Linux version
45//-------------------------------------------------
46
47//----------------------
48// Mandatory Includes:
49//----------------------
50#include <linux/config.h>
51#include "ip2types.h"
52#include "i2hw.h" // The hardware definitions
53
54//------------------------------------------
55// STAT_BOXIDS packets
56//------------------------------------------
57#define MAX_BOX 4
58
59typedef struct _bidStat
60{
61 unsigned char bid_value[MAX_BOX];
62} bidStat, *bidStatPtr;
63
64// This packet is sent in response to a CMD_GET_BOXIDS bypass command. For -IIEX
65// boards, reports the hardware-specific "asynchronous resource register" on
66// each expansion box. Boxes not present report 0xff. For -II boards, the first
67// element contains 0x80 for 8-port, 0x40 for 4-port boards.
68
69// Box IDs aka ARR or Async Resource Register (more than you want to know)
70// 7 6 5 4 3 2 1 0
71// F F N N L S S S
72// =============================
73// F F - Product Family Designator
74// =====+++++++++++++++++++++++++++++++
75// 0 0 - Intelliport II EX / ISA-8
76// 1 0 - IntelliServer
77// 0 1 - SAC - Port Device (Intelliport III ??? )
78// =====+++++++++++++++++++++++++++++++++++++++
79// N N - Number of Ports
80// 0 0 - 8 (eight)
81// 0 1 - 4 (four)
82// 1 0 - 12 (twelve)
83// 1 1 - 16 (sixteen)
84// =++++++++++++++++++++++++++++++++++
85// L - LCD Display Module Present
86// 0 - No
87// 1 - LCD module present
88// =========+++++++++++++++++++++++++++++++++++++
89// S S S - Async Signals Supported Designator
90// 0 0 0 - 8dss, Mod DCE DB25 Female
91// 0 0 1 - 6dss, RJ-45
92// 0 1 0 - RS-232/422 dss, DB25 Female
93// 0 1 1 - RS-232/422 dss, separate 232/422 DB25 Female
94// 1 0 0 - 6dss, 921.6 I/F with ST654's
95// 1 0 1 - RS-423/232 8dss, RJ-45 10Pin
96// 1 1 0 - 6dss, Mod DCE DB25 Female
97// 1 1 1 - NO BOX PRESENT
98
99#define FF(c) ((c & 0xC0) >> 6)
100#define NN(c) ((c & 0x30) >> 4)
101#define L(c) ((c & 0x08) >> 3)
102#define SSS(c) (c & 0x07)
103
104#define BID_HAS_654(x) (SSS(x) == 0x04)
105#define BID_NO_BOX 0xff /* no box */
106#define BID_8PORT 0x80 /* IP2-8 port */
107#define BID_4PORT 0x81 /* IP2-4 port */
108#define BID_EXP_MASK 0x30 /* IP2-EX */
109#define BID_EXP_8PORT 0x00 /* 8, */
110#define BID_EXP_4PORT 0x10 /* 4, */
111#define BID_EXP_UNDEF 0x20 /* UNDEF, */
112#define BID_EXP_16PORT 0x30 /* 16, */
113#define BID_LCD_CTRL 0x08 /* LCD Controller */
114#define BID_LCD_NONE 0x00 /* - no controller present */
115#define BID_LCD_PRES 0x08 /* - controller present */
116#define BID_CON_MASK 0x07 /* - connector pinouts */
117#define BID_CON_DB25 0x00 /* - DB-25 F */
118#define BID_CON_RJ45 0x01 /* - rj45 */
119
120//------------------------------------------------------------------------------
121// i2eBordStr
122//
123// This structure contains all the information the ELLIS routines require in
124// dealing with a particular board.
125//------------------------------------------------------------------------------
126// There are some queues here which are guaranteed to never contain the entry
127// for a single channel twice. So they must be slightly larger to allow
128// unambiguous full/empty management
129//
130#define CH_QUEUE_SIZE ABS_MOST_PORTS+2
131
132typedef struct _i2eBordStr
133{
134 porStr i2ePom; // Structure containing the power-on message.
135
136 unsigned short i2ePomSize;
137 // The number of bytes actually read if
138 // different from sizeof i2ePom, indicates
139 // there is an error!
140
141 unsigned short i2eStartMail;
142 // Contains whatever inbound mailbox data
143 // present at startup. NO_MAIL_HERE indicates
144 // nothing was present. No special
145 // significance as of this writing, but may be
146 // useful for diagnostic reasons.
147
148 unsigned short i2eValid;
149 // Indicates validity of the structure; if
150 // i2eValid == I2E_MAGIC, then we can trust
151 // the other fields. Some (especially
152 // initialization) functions are good about
153 // checking for validity. Many functions do
154 // not, it being assumed that the larger
155 // context assures we are using a valid
156 // i2eBordStrPtr.
157
158 unsigned short i2eError;
159 // Used for returning an error condition from
160 // several functions which use i2eBordStrPtr
161 // as an argument.
162
163 // Accelerators to characterize separate features of a board, derived from a
164 // number of sources.
165
166 unsigned short i2eFifoSize;
167 // Always, the size of the FIFO. For
168 // IntelliPort-II, always the same, for -IIEX
169 // taken from the Power-On reset message.
170
171 volatile
172 unsigned short i2eFifoRemains;
173 // Used during normal operation to indicate a
174 // lower bound on the amount of data which
175 // might be in the outbound fifo.
176
177 unsigned char i2eFifoStyle;
178 // Accelerator which tells which style (-II or
179 // -IIEX) FIFO we are using.
180
181 unsigned char i2eDataWidth16;
182 // Accelerator which tells whether we should
183 // do 8 or 16-bit data transfers.
184
185 unsigned char i2eMaxIrq;
186 // The highest allowable IRQ, based on the
187 // slot size.
188
189 unsigned char i2eChangeIrq;
190 // Whether tis valid to change IRQ's
191 // ISA = ok, EISA, MicroChannel, no
192
193 // Accelerators for various addresses on the board
194 int i2eBase; // I/O Address of the Board
195 int i2eData; // From here data transfers happen
196 int i2eStatus; // From here status reads happen
197 int i2ePointer; // (IntelliPort-II: pointer/commands)
198 int i2eXMail; // (IntelliPOrt-IIEX: mailboxes
199 int i2eXMask; // (IntelliPort-IIEX: mask write
200
201 //-------------------------------------------------------
202 // Information presented in a common format across boards
203 // For each box, bit map of the channels present. Box closest to
204 // the host is box 0. LSB is channel 0. IntelliPort-II (non-expandable)
205 // is taken to be box 0. These are derived from product i.d. registers.
206
207 unsigned short i2eChannelMap[ABS_MAX_BOXES];
208
209 // Same as above, except each is derived from firmware attempting to detect
210 // the uart presence (by reading a valid GFRCR register). If bits are set in
211 // i2eChannelMap and not in i2eGoodMap, there is a potential problem.
212
213 unsigned short i2eGoodMap[ABS_MAX_BOXES];
214
215 // ---------------------------
216 // For indirect function calls
217
218 // Routine to cause an N-millisecond delay: Patched by the ii2Initialize
219 // function.
220
221 void (*i2eDelay)(unsigned int);
222
223 // Routine to write N bytes to the board through the FIFO. Returns true if
224 // all copacetic, otherwise returns false and error is in i2eError field.
225 // IF COUNT IS ODD, ROUNDS UP TO THE NEXT EVEN NUMBER.
226
227 int (*i2eWriteBuf)(struct _i2eBordStr *, unsigned char *, int);
228
229 // Routine to read N bytes from the board through the FIFO. Returns true if
230 // copacetic, otherwise returns false and error in i2eError.
231 // IF COUNT IS ODD, ROUNDS UP TO THE NEXT EVEN NUMBER.
232
233 int (*i2eReadBuf)(struct _i2eBordStr *, unsigned char *, int);
234
235 // Returns a word from FIFO. Will use 2 byte operations if needed.
236
237 unsigned short (*i2eReadWord)(struct _i2eBordStr *);
238
239 // Writes a word to FIFO. Will use 2 byte operations if needed.
240
241 void (*i2eWriteWord)(struct _i2eBordStr *, unsigned short);
242
243 // Waits specified time for the Transmit FIFO to go empty. Returns true if
244 // ok, otherwise returns false and error in i2eError.
245
246 int (*i2eWaitForTxEmpty)(struct _i2eBordStr *, int);
247
248 // Returns true or false according to whether the outgoing mailbox is empty.
249
250 int (*i2eTxMailEmpty)(struct _i2eBordStr *);
251
252 // Checks whether outgoing mailbox is empty. If so, sends mail and returns
253 // true. Otherwise returns false.
254
255 int (*i2eTrySendMail)(struct _i2eBordStr *, unsigned char);
256
257 // If no mail available, returns NO_MAIL_HERE, else returns the value in the
258 // mailbox (guaranteed can't be NO_MAIL_HERE).
259
260 unsigned short (*i2eGetMail)(struct _i2eBordStr *);
261
262 // Enables the board to interrupt the host when it writes to the mailbox.
263 // Irqs will not occur, however, until the loadware separately enables
264 // interrupt generation to the host. The standard loadware does this in
265 // response to a command packet sent by the host. (Also, disables
266 // any other potential interrupt sources from the board -- other than the
267 // inbound mailbox).
268
269 void (*i2eEnableMailIrq)(struct _i2eBordStr *);
270
271 // Writes an arbitrary value to the mask register.
272
273 void (*i2eWriteMask)(struct _i2eBordStr *, unsigned char);
274
275
276 // State information
277
278 // During downloading, indicates the number of blocks remaining to download
279 // to the board.
280
281 short i2eToLoad;
282
283 // State of board (see manifests below) (e.g., whether in reset condition,
284 // whether standard loadware is installed, etc.
285
286 unsigned char i2eState;
287
288 // These three fields are only valid when there is loadware running on the
289 // board. (i2eState == II_STATE_LOADED or i2eState == II_STATE_STDLOADED )
290
291 unsigned char i2eLVersion; // Loadware version
292 unsigned char i2eLRevision; // Loadware revision
293 unsigned char i2eLSub; // Loadware subrevision
294
295 // Flags which only have meaning in the context of the standard loadware.
296 // Somewhat violates the layering concept, but there is so little additional
297 // needed at the board level (while much additional at the channel level),
298 // that this beats maintaining two different per-board structures.
299
300 // Indicates which IRQ the board has been initialized (from software) to use
301 // For MicroChannel boards, any value different from IRQ_UNDEFINED means
302 // that the software command has been sent to enable interrupts (or specify
303 // they are disabled). Special value: IRQ_UNDEFINED indicates that the
304 // software command to select the interrupt has not yet been sent, therefore
305 // (since the standard loadware insists that it be sent before any other
306 // packets are sent) no other packets should be sent yet.
307
308 unsigned short i2eUsingIrq;
309
310 // This is set when we hit the MB_OUT_STUFFED mailbox, which prevents us
311 // putting more in the mailbox until an appropriate mailbox message is
312 // received.
313
314 unsigned char i2eWaitingForEmptyFifo;
315
316 // Any mailbox bits waiting to be sent to the board are OR'ed in here.
317
318 unsigned char i2eOutMailWaiting;
319
320 // The head of any incoming packet is read into here, is then examined and
321 // we dispatch accordingly.
322
323 unsigned short i2eLeadoffWord[1];
324
325 // Running counter of interrupts where the mailbox indicated incoming data.
326
327 unsigned short i2eFifoInInts;
328
329 // Running counter of interrupts where the mailbox indicated outgoing data
330 // had been stripped.
331
332 unsigned short i2eFifoOutInts;
333
334 // If not void, gives the address of a routine to call if fatal board error
335 // is found (only applies to standard l/w).
336
337 void (*i2eFatalTrap)(struct _i2eBordStr *);
338
339 // Will point to an array of some sort of channel structures (whose format
340 // is unknown at this level, being a function of what loadware is
341 // installed and the code configuration (max sizes of buffers, etc.)).
342
343 void *i2eChannelPtr;
344
345 // Set indicates that the board has gone fatal.
346
347 unsigned short i2eFatal;
348
349 // The number of elements pointed to by i2eChannelPtr.
350
351 unsigned short i2eChannelCnt;
352
353 // Ring-buffers of channel structures whose channels have particular needs.
354
355 rwlock_t Fbuf_spinlock;
356 volatile
357 unsigned short i2Fbuf_strip; // Strip index
358 volatile
359 unsigned short i2Fbuf_stuff; // Stuff index
360 void *i2Fbuf[CH_QUEUE_SIZE]; // An array of channel pointers
361 // of channels who need to send
362 // flow control packets.
363 rwlock_t Dbuf_spinlock;
364 volatile
365 unsigned short i2Dbuf_strip; // Strip index
366 volatile
367 unsigned short i2Dbuf_stuff; // Stuff index
368 void *i2Dbuf[CH_QUEUE_SIZE]; // An array of channel pointers
369 // of channels who need to send
370 // data or in-line command packets.
371 rwlock_t Bbuf_spinlock;
372 volatile
373 unsigned short i2Bbuf_strip; // Strip index
374 volatile
375 unsigned short i2Bbuf_stuff; // Stuff index
376 void *i2Bbuf[CH_QUEUE_SIZE]; // An array of channel pointers
377 // of channels who need to send
378 // bypass command packets.
379
380 /*
381 * A set of flags to indicate that certain events have occurred on at least
382 * one of the ports on this board. We use this to decide whether to spin
383 * through the channels looking for breaks, etc.
384 */
385 int got_input;
386 int status_change;
387 bidStat channelBtypes;
388
389 /*
390 * Debugging counters, etc.
391 */
392 unsigned long debugFlowQueued;
393 unsigned long debugInlineQueued;
394 unsigned long debugDataQueued;
395 unsigned long debugBypassQueued;
396 unsigned long debugFlowCount;
397 unsigned long debugInlineCount;
398 unsigned long debugBypassCount;
399
400 rwlock_t read_fifo_spinlock;
401 rwlock_t write_fifo_spinlock;
402
403// For queuing interrupt bottom half handlers. /\/\|=mhw=|\/\/
404 struct work_struct tqueue_interrupt;
405
406 struct timer_list SendPendingTimer; // Used by iiSendPending
407 unsigned int SendPendingRetry;
408} i2eBordStr, *i2eBordStrPtr;
409
410//-------------------------------------------------------------------
411// Macro Definitions for the indirect calls defined in the i2eBordStr
412//-------------------------------------------------------------------
413//
414#define iiDelay(a,b) (*(a)->i2eDelay)(b)
415#define iiWriteBuf(a,b,c) (*(a)->i2eWriteBuf)(a,b,c)
416#define iiReadBuf(a,b,c) (*(a)->i2eReadBuf)(a,b,c)
417
418#define iiWriteWord(a,b) (*(a)->i2eWriteWord)(a,b)
419#define iiReadWord(a) (*(a)->i2eReadWord)(a)
420
421#define iiWaitForTxEmpty(a,b) (*(a)->i2eWaitForTxEmpty)(a,b)
422
423#define iiTxMailEmpty(a) (*(a)->i2eTxMailEmpty)(a)
424#define iiTrySendMail(a,b) (*(a)->i2eTrySendMail)(a,b)
425
426#define iiGetMail(a) (*(a)->i2eGetMail)(a)
427#define iiEnableMailIrq(a) (*(a)->i2eEnableMailIrq)(a)
428#define iiDisableMailIrq(a) (*(a)->i2eWriteMask)(a,0)
429#define iiWriteMask(a,b) (*(a)->i2eWriteMask)(a,b)
430
431//-------------------------------------------
432// Manifests for i2eBordStr:
433//-------------------------------------------
434
435#define YES 1
436#define NO 0
437
438#define NULLFUNC (void (*)(void))0
439#define NULLPTR (void *)0
440
441typedef void (*delayFunc_t)(unsigned int);
442
443// i2eValid
444//
445#define I2E_MAGIC 0x4251 // Structure is valid.
446#define I2E_INCOMPLETE 0x1122 // Structure failed during init.
447
448
449// i2eError
450//
451#define I2EE_GOOD 0 // Operation successful
452#define I2EE_BADADDR 1 // Address out of range
453#define I2EE_BADSTATE 2 // Attempt to perform a function when the board
454 // structure was in the incorrect state
455#define I2EE_BADMAGIC 3 // Bad magic number from Power On test (i2ePomSize
456 // reflects what was read
457#define I2EE_PORM_SHORT 4 // Power On message too short
458#define I2EE_PORM_LONG 5 // Power On message too long
459#define I2EE_BAD_FAMILY 6 // Un-supported board family type
460#define I2EE_INCONSIST 7 // Firmware reports something impossible,
461 // e.g. unexpected number of ports... Almost no
462 // excuse other than bad FIFO...
463#define I2EE_POSTERR 8 // Power-On self test reported a bad error
464#define I2EE_BADBUS 9 // Unknown Bus type declared in message
465#define I2EE_TXE_TIME 10 // Timed out waiting for TX Fifo to empty
466#define I2EE_INVALID 11 // i2eValid field does not indicate a valid and
467 // complete board structure (for functions which
468 // require this be so.)
469#define I2EE_BAD_PORT 12 // Discrepancy between channels actually found and
470 // what the product is supposed to have. Check
471 // i2eGoodMap vs i2eChannelMap for details.
472#define I2EE_BAD_IRQ 13 // Someone specified an unsupported IRQ
473#define I2EE_NOCHANNELS 14 // No channel structures have been defined (for
474 // functions requiring this).
475
476// i2eFifoStyle
477//
478#define FIFO_II 0 /* IntelliPort-II style: see also i2hw.h */
479#define FIFO_IIEX 1 /* IntelliPort-IIEX style */
480
481// i2eGetMail
482//
483#define NO_MAIL_HERE 0x1111 // Since mail is unsigned char, cannot possibly
484 // promote to 0x1111.
485// i2eState
486//
487#define II_STATE_COLD 0 // Addresses have been defined, but board not even
488 // reset yet.
489#define II_STATE_RESET 1 // Board,if it exists, has just been reset
490#define II_STATE_READY 2 // Board ready for its first block
491#define II_STATE_LOADING 3 // Board continuing load
492#define II_STATE_LOADED 4 // Board has finished load: status ok
493#define II_STATE_BADLOAD 5 // Board has finished load: failed!
494#define II_STATE_STDLOADED 6 // Board has finished load: standard firmware
495
496// i2eUsingIrq
497//
498#define IRQ_UNDEFINED 0x1352 // No valid irq (or polling = 0) can ever
499 // promote to this!
500//------------------------------------------
501// Handy Macros for i2ellis.c and others
502// Note these are common to -II and -IIEX
503//------------------------------------------
504
505// Given a pointer to the board structure, does the input FIFO have any data or
506// not?
507//
508#define HAS_INPUT(pB) !(INB(pB->i2eStatus) & ST_IN_EMPTY)
509#define HAS_NO_INPUT(pB) (INB(pB->i2eStatus) & ST_IN_EMPTY)
510
511// Given a pointer to board structure, read a byte or word from the fifo
512//
513#define BYTE_FROM(pB) (unsigned char)INB(pB->i2eData)
514#define WORD_FROM(pB) (unsigned short)INW(pB->i2eData)
515
516// Given a pointer to board structure, is there room for any data to be written
517// to the data fifo?
518//
519#define HAS_OUTROOM(pB) !(INB(pB->i2eStatus) & ST_OUT_FULL)
520#define HAS_NO_OUTROOM(pB) (INB(pB->i2eStatus) & ST_OUT_FULL)
521
522// Given a pointer to board structure, write a single byte to the fifo
523// structure. Note that for 16-bit interfaces, the high order byte is undefined
524// and unknown.
525//
526#define BYTE_TO(pB, c) OUTB(pB->i2eData,(c))
527
528// Write a word to the fifo structure. For 8-bit interfaces, this may have
529// unknown results.
530//
531#define WORD_TO(pB, c) OUTW(pB->i2eData,(c))
532
533// Given a pointer to the board structure, is there anything in the incoming
534// mailbox?
535//
536#define HAS_MAIL(pB) (INB(pB->i2eStatus) & ST_IN_MAIL)
537
538#define UPDATE_FIFO_ROOM(pB) (pB)->i2eFifoRemains=(pB)->i2eFifoSize
539
540// Handy macro to round up a number (like the buffer write and read routines do)
541//
542#define ROUNDUP(number) (((number)+1) & (~1))
543
544//------------------------------------------
545// Function Declarations for i2ellis.c
546//------------------------------------------
547//
548// Functions called directly
549//
550// Initialization of a board & structure is in four (five!) parts:
551//
552// 0) iiEllisInit() - Initialize iiEllis subsystem.
553// 1) iiSetAddress() - Define the board address & delay function for a board.
554// 2) iiReset() - Reset the board (provided it exists)
555// -- Note you may do this to several boards --
556// 3) iiResetDelay() - Delay for 2 seconds (once for all boards)
557// 4) iiInitialize() - Attempt to read Power-up message; further initialize
558// accelerators
559//
560// Then you may use iiDownloadAll() or iiDownloadFile() (in i2file.c) to write
561// loadware. To change loadware, you must begin again with step 2, resetting
562// the board again (step 1 not needed).
563
564static void iiEllisInit(void);
565static int iiSetAddress(i2eBordStrPtr, int, delayFunc_t );
566static int iiReset(i2eBordStrPtr);
567static int iiResetDelay(i2eBordStrPtr);
568static int iiInitialize(i2eBordStrPtr);
569
570// Routine to validate that all channels expected are there.
571//
572extern int iiValidateChannels(i2eBordStrPtr);
573
574// Routine used to download a block of loadware.
575//
576static int iiDownloadBlock(i2eBordStrPtr, loadHdrStrPtr, int);
577
578// Return values given by iiDownloadBlock, iiDownloadAll, iiDownloadFile:
579//
580#define II_DOWN_BADVALID 0 // board structure is invalid
581#define II_DOWN_CONTINUING 1 // So far, so good, firmware expects more
582#define II_DOWN_GOOD 2 // Download complete, CRC good
583#define II_DOWN_BAD 3 // Download complete, but CRC bad
584#define II_DOWN_BADFILE 4 // Bad magic number in loadware file
585#define II_DOWN_BADSTATE 5 // Board is in an inappropriate state for
586 // downloading loadware. (see i2eState)
587#define II_DOWN_TIMEOUT 6 // Timeout waiting for firmware
588#define II_DOWN_OVER 7 // Too much data
589#define II_DOWN_UNDER 8 // Not enough data
590#define II_DOWN_NOFILE 9 // Loadware file not found
591
592// Routine to download an entire loadware module: Return values are a subset of
593// iiDownloadBlock's, excluding, of course, II_DOWN_CONTINUING
594//
595static int iiDownloadAll(i2eBordStrPtr, loadHdrStrPtr, int, int);
596
597// Called indirectly always. Needed externally so the routine might be
598// SPECIFIED as an argument to iiReset()
599//
600//static void ii2DelayIO(unsigned int); // N-millisecond delay using
601 //hardware spin
602//static void ii2DelayTimer(unsigned int); // N-millisecond delay using Linux
603 //timer
604
605// Many functions defined here return True if good, False otherwise, with an
606// error code in i2eError field. Here is a handy macro for setting the error
607// code and returning.
608//
609#define COMPLETE(pB,code) \
610 if(1){ \
611 pB->i2eError = code; \
612 return (code == I2EE_GOOD);\
613 }
614
615#endif // I2ELLIS_H