diff options
author | Jiri Slaby <jirislaby@gmail.com> | 2008-04-30 03:53:54 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-04-30 11:29:44 -0400 |
commit | cf1c63c3e68679dcac1cc6a37e619d9106ebc0ca (patch) | |
tree | d34d5ad3a81310fbdcf60b70e4abb1d046544dc6 /drivers/char/ip2/i2ellis.c | |
parent | 83e422b7649267067975cbb17a878b5f9dfd2de3 (diff) |
Char: ip2, macros cleanup
- remove i2os.h -- there was only macro to macro renaming or useless
stuff
- remove another uselless stuf (NULLFUNC, NULLPTR, YES, NO)
- use outb/inb directly
- use locking functions directly
- don't define another ROUNDUP, use roundup(x, 2) instead
- some comments and whitespace cleanup
- remove some commented crap
- prepend the rest by I2 prefix to not collide with rest of the world
like in following output (pointed out by akpm)
In file included from drivers/char/ip2/ip2main.c:128:
drivers/char/ip2/i2ellis.h:608:1: warning: "COMPLETE" redefined
In file included from include/net/netns/ipv4.h:8,
from include/net/net_namespace.h:13,
from include/linux/seq_file.h:7,
from include/asm/machdep.h:12,
from include/asm/pci.h:17,
from include/linux/pci.h:951,
from drivers/char/ip2/ip2main.c:95:
include/net/inet_frag.h:28:1: warning: this is the location of the previous definition
Signed-off-by: Jiri Slaby <jirislaby@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/char/ip2/i2ellis.c')
-rw-r--r-- | drivers/char/ip2/i2ellis.c | 194 |
1 files changed, 93 insertions, 101 deletions
diff --git a/drivers/char/ip2/i2ellis.c b/drivers/char/ip2/i2ellis.c index 61ef013b8445..3601017f58cf 100644 --- a/drivers/char/ip2/i2ellis.c +++ b/drivers/char/ip2/i2ellis.c | |||
@@ -53,7 +53,7 @@ static int ii2Safe; // Safe I/O address for delay routine | |||
53 | 53 | ||
54 | static int iiDelayed; // Set when the iiResetDelay function is | 54 | static int iiDelayed; // Set when the iiResetDelay function is |
55 | // called. Cleared when ANY board is reset. | 55 | // called. Cleared when ANY board is reset. |
56 | static rwlock_t Dl_spinlock; | 56 | static DEFINE_RWLOCK(Dl_spinlock); |
57 | 57 | ||
58 | //******** | 58 | //******** |
59 | //* Code * | 59 | //* Code * |
@@ -82,7 +82,6 @@ static rwlock_t Dl_spinlock; | |||
82 | static void | 82 | static void |
83 | iiEllisInit(void) | 83 | iiEllisInit(void) |
84 | { | 84 | { |
85 | LOCK_INIT(&Dl_spinlock); | ||
86 | } | 85 | } |
87 | 86 | ||
88 | //****************************************************************************** | 87 | //****************************************************************************** |
@@ -132,7 +131,7 @@ iiSetAddress( i2eBordStrPtr pB, int address, delayFunc_t delay ) | |||
132 | || (address & 0x7) | 131 | || (address & 0x7) |
133 | ) | 132 | ) |
134 | { | 133 | { |
135 | COMPLETE(pB,I2EE_BADADDR); | 134 | I2_COMPLETE(pB, I2EE_BADADDR); |
136 | } | 135 | } |
137 | 136 | ||
138 | // Initialize accelerators | 137 | // Initialize accelerators |
@@ -152,7 +151,7 @@ iiSetAddress( i2eBordStrPtr pB, int address, delayFunc_t delay ) | |||
152 | pB->i2eValid = I2E_MAGIC; | 151 | pB->i2eValid = I2E_MAGIC; |
153 | pB->i2eState = II_STATE_COLD; | 152 | pB->i2eState = II_STATE_COLD; |
154 | 153 | ||
155 | COMPLETE(pB, I2EE_GOOD); | 154 | I2_COMPLETE(pB, I2EE_GOOD); |
156 | } | 155 | } |
157 | 156 | ||
158 | //****************************************************************************** | 157 | //****************************************************************************** |
@@ -177,12 +176,12 @@ iiReset(i2eBordStrPtr pB) | |||
177 | // Magic number should be set, else even the address is suspect | 176 | // Magic number should be set, else even the address is suspect |
178 | if (pB->i2eValid != I2E_MAGIC) | 177 | if (pB->i2eValid != I2E_MAGIC) |
179 | { | 178 | { |
180 | COMPLETE(pB, I2EE_BADMAGIC); | 179 | I2_COMPLETE(pB, I2EE_BADMAGIC); |
181 | } | 180 | } |
182 | 181 | ||
183 | OUTB(pB->i2eBase + FIFO_RESET, 0); // Any data will do | 182 | outb(0, pB->i2eBase + FIFO_RESET); /* Any data will do */ |
184 | iiDelay(pB, 50); // Pause between resets | 183 | iiDelay(pB, 50); // Pause between resets |
185 | OUTB(pB->i2eBase + FIFO_RESET, 0); // Second reset | 184 | outb(0, pB->i2eBase + FIFO_RESET); /* Second reset */ |
186 | 185 | ||
187 | // We must wait before even attempting to read anything from the FIFO: the | 186 | // We must wait before even attempting to read anything from the FIFO: the |
188 | // board's P.O.S.T may actually attempt to read and write its end of the | 187 | // board's P.O.S.T may actually attempt to read and write its end of the |
@@ -203,7 +202,7 @@ iiReset(i2eBordStrPtr pB) | |||
203 | // Ensure anything which would have been of use to standard loadware is | 202 | // Ensure anything which would have been of use to standard loadware is |
204 | // blanked out, since board has now forgotten everything!. | 203 | // blanked out, since board has now forgotten everything!. |
205 | 204 | ||
206 | pB->i2eUsingIrq = IRQ_UNDEFINED; // Not set up to use an interrupt yet | 205 | pB->i2eUsingIrq = I2_IRQ_UNDEFINED; /* to not use an interrupt so far */ |
207 | pB->i2eWaitingForEmptyFifo = 0; | 206 | pB->i2eWaitingForEmptyFifo = 0; |
208 | pB->i2eOutMailWaiting = 0; | 207 | pB->i2eOutMailWaiting = 0; |
209 | pB->i2eChannelPtr = NULL; | 208 | pB->i2eChannelPtr = NULL; |
@@ -215,7 +214,7 @@ iiReset(i2eBordStrPtr pB) | |||
215 | pB->i2eFatalTrap = NULL; | 214 | pB->i2eFatalTrap = NULL; |
216 | pB->i2eFatal = 0; | 215 | pB->i2eFatal = 0; |
217 | 216 | ||
218 | COMPLETE(pB, I2EE_GOOD); | 217 | I2_COMPLETE(pB, I2EE_GOOD); |
219 | } | 218 | } |
220 | 219 | ||
221 | //****************************************************************************** | 220 | //****************************************************************************** |
@@ -235,14 +234,14 @@ static int | |||
235 | iiResetDelay(i2eBordStrPtr pB) | 234 | iiResetDelay(i2eBordStrPtr pB) |
236 | { | 235 | { |
237 | if (pB->i2eValid != I2E_MAGIC) { | 236 | if (pB->i2eValid != I2E_MAGIC) { |
238 | COMPLETE(pB, I2EE_BADMAGIC); | 237 | I2_COMPLETE(pB, I2EE_BADMAGIC); |
239 | } | 238 | } |
240 | if (pB->i2eState != II_STATE_RESET) { | 239 | if (pB->i2eState != II_STATE_RESET) { |
241 | COMPLETE(pB, I2EE_BADSTATE); | 240 | I2_COMPLETE(pB, I2EE_BADSTATE); |
242 | } | 241 | } |
243 | iiDelay(pB,2000); /* Now we wait for two seconds. */ | 242 | iiDelay(pB,2000); /* Now we wait for two seconds. */ |
244 | iiDelayed = 1; /* Delay has been called: ok to initialize */ | 243 | iiDelayed = 1; /* Delay has been called: ok to initialize */ |
245 | COMPLETE(pB, I2EE_GOOD); | 244 | I2_COMPLETE(pB, I2EE_GOOD); |
246 | } | 245 | } |
247 | 246 | ||
248 | //****************************************************************************** | 247 | //****************************************************************************** |
@@ -273,12 +272,12 @@ iiInitialize(i2eBordStrPtr pB) | |||
273 | 272 | ||
274 | if (pB->i2eValid != I2E_MAGIC) | 273 | if (pB->i2eValid != I2E_MAGIC) |
275 | { | 274 | { |
276 | COMPLETE(pB, I2EE_BADMAGIC); | 275 | I2_COMPLETE(pB, I2EE_BADMAGIC); |
277 | } | 276 | } |
278 | 277 | ||
279 | if (pB->i2eState != II_STATE_RESET || !iiDelayed) | 278 | if (pB->i2eState != II_STATE_RESET || !iiDelayed) |
280 | { | 279 | { |
281 | COMPLETE(pB, I2EE_BADSTATE); | 280 | I2_COMPLETE(pB, I2EE_BADSTATE); |
282 | } | 281 | } |
283 | 282 | ||
284 | // In case there is a failure short of our completely reading the power-up | 283 | // In case there is a failure short of our completely reading the power-up |
@@ -291,13 +290,12 @@ iiInitialize(i2eBordStrPtr pB) | |||
291 | for (itemp = 0; itemp < sizeof(porStr); itemp++) | 290 | for (itemp = 0; itemp < sizeof(porStr); itemp++) |
292 | { | 291 | { |
293 | // We expect the entire message is ready. | 292 | // We expect the entire message is ready. |
294 | if (HAS_NO_INPUT(pB)) | 293 | if (!I2_HAS_INPUT(pB)) { |
295 | { | ||
296 | pB->i2ePomSize = itemp; | 294 | pB->i2ePomSize = itemp; |
297 | COMPLETE(pB, I2EE_PORM_SHORT); | 295 | I2_COMPLETE(pB, I2EE_PORM_SHORT); |
298 | } | 296 | } |
299 | 297 | ||
300 | pB->i2ePom.c[itemp] = c = BYTE_FROM(pB); | 298 | pB->i2ePom.c[itemp] = c = inb(pB->i2eData); |
301 | 299 | ||
302 | // We check the magic numbers as soon as they are supposed to be read | 300 | // We check the magic numbers as soon as they are supposed to be read |
303 | // (rather than after) to minimize effect of reading something we | 301 | // (rather than after) to minimize effect of reading something we |
@@ -306,22 +304,22 @@ iiInitialize(i2eBordStrPtr pB) | |||
306 | (itemp == POR_2_INDEX && c != POR_MAGIC_2)) | 304 | (itemp == POR_2_INDEX && c != POR_MAGIC_2)) |
307 | { | 305 | { |
308 | pB->i2ePomSize = itemp+1; | 306 | pB->i2ePomSize = itemp+1; |
309 | COMPLETE(pB, I2EE_BADMAGIC); | 307 | I2_COMPLETE(pB, I2EE_BADMAGIC); |
310 | } | 308 | } |
311 | } | 309 | } |
312 | 310 | ||
313 | pB->i2ePomSize = itemp; | 311 | pB->i2ePomSize = itemp; |
314 | 312 | ||
315 | // Ensure that this was all the data... | 313 | // Ensure that this was all the data... |
316 | if (HAS_INPUT(pB)) | 314 | if (I2_HAS_INPUT(pB)) |
317 | COMPLETE(pB, I2EE_PORM_LONG); | 315 | I2_COMPLETE(pB, I2EE_PORM_LONG); |
318 | 316 | ||
319 | // For now, we'll fail to initialize if P.O.S.T reports bad chip mapper: | 317 | // For now, we'll fail to initialize if P.O.S.T reports bad chip mapper: |
320 | // Implying we will not be able to download any code either: That's ok: the | 318 | // Implying we will not be able to download any code either: That's ok: the |
321 | // condition is pretty explicit. | 319 | // condition is pretty explicit. |
322 | if (pB->i2ePom.e.porDiag1 & POR_BAD_MAPPER) | 320 | if (pB->i2ePom.e.porDiag1 & POR_BAD_MAPPER) |
323 | { | 321 | { |
324 | COMPLETE(pB, I2EE_POSTERR); | 322 | I2_COMPLETE(pB, I2EE_POSTERR); |
325 | } | 323 | } |
326 | 324 | ||
327 | // Determine anything which must be done differently depending on the family | 325 | // Determine anything which must be done differently depending on the family |
@@ -332,7 +330,7 @@ iiInitialize(i2eBordStrPtr pB) | |||
332 | 330 | ||
333 | pB->i2eFifoStyle = FIFO_II; | 331 | pB->i2eFifoStyle = FIFO_II; |
334 | pB->i2eFifoSize = 512; // 512 bytes, always | 332 | pB->i2eFifoSize = 512; // 512 bytes, always |
335 | pB->i2eDataWidth16 = NO; | 333 | pB->i2eDataWidth16 = false; |
336 | 334 | ||
337 | pB->i2eMaxIrq = 15; // Because board cannot tell us it is in an 8-bit | 335 | pB->i2eMaxIrq = 15; // Because board cannot tell us it is in an 8-bit |
338 | // slot, we do allow it to be done (documentation!) | 336 | // slot, we do allow it to be done (documentation!) |
@@ -354,7 +352,7 @@ iiInitialize(i2eBordStrPtr pB) | |||
354 | // should always be consistent for IntelliPort-II. Ditto below... | 352 | // should always be consistent for IntelliPort-II. Ditto below... |
355 | if (pB->i2ePom.e.porPorts1 != 4) | 353 | if (pB->i2ePom.e.porPorts1 != 4) |
356 | { | 354 | { |
357 | COMPLETE(pB, I2EE_INCONSIST); | 355 | I2_COMPLETE(pB, I2EE_INCONSIST); |
358 | } | 356 | } |
359 | break; | 357 | break; |
360 | 358 | ||
@@ -364,7 +362,7 @@ iiInitialize(i2eBordStrPtr pB) | |||
364 | pB->i2eChannelMap[0] = 0xff; // Eight port | 362 | pB->i2eChannelMap[0] = 0xff; // Eight port |
365 | if (pB->i2ePom.e.porPorts1 != 8) | 363 | if (pB->i2ePom.e.porPorts1 != 8) |
366 | { | 364 | { |
367 | COMPLETE(pB, I2EE_INCONSIST); | 365 | I2_COMPLETE(pB, I2EE_INCONSIST); |
368 | } | 366 | } |
369 | break; | 367 | break; |
370 | 368 | ||
@@ -373,7 +371,7 @@ iiInitialize(i2eBordStrPtr pB) | |||
373 | pB->i2eChannelMap[0] = 0x3f; // Six Port | 371 | pB->i2eChannelMap[0] = 0x3f; // Six Port |
374 | if (pB->i2ePom.e.porPorts1 != 6) | 372 | if (pB->i2ePom.e.porPorts1 != 6) |
375 | { | 373 | { |
376 | COMPLETE(pB, I2EE_INCONSIST); | 374 | I2_COMPLETE(pB, I2EE_INCONSIST); |
377 | } | 375 | } |
378 | break; | 376 | break; |
379 | } | 377 | } |
@@ -402,7 +400,7 @@ iiInitialize(i2eBordStrPtr pB) | |||
402 | 400 | ||
403 | if (itemp < 8 || itemp > 15) | 401 | if (itemp < 8 || itemp > 15) |
404 | { | 402 | { |
405 | COMPLETE(pB, I2EE_INCONSIST); | 403 | I2_COMPLETE(pB, I2EE_INCONSIST); |
406 | } | 404 | } |
407 | pB->i2eFifoSize = (1 << itemp); | 405 | pB->i2eFifoSize = (1 << itemp); |
408 | 406 | ||
@@ -450,26 +448,26 @@ iiInitialize(i2eBordStrPtr pB) | |||
450 | switch (pB->i2ePom.e.porBus & (POR_BUS_SLOT16 | POR_BUS_DIP16) ) | 448 | switch (pB->i2ePom.e.porBus & (POR_BUS_SLOT16 | POR_BUS_DIP16) ) |
451 | { | 449 | { |
452 | case POR_BUS_SLOT16 | POR_BUS_DIP16: | 450 | case POR_BUS_SLOT16 | POR_BUS_DIP16: |
453 | pB->i2eDataWidth16 = YES; | 451 | pB->i2eDataWidth16 = true; |
454 | pB->i2eMaxIrq = 15; | 452 | pB->i2eMaxIrq = 15; |
455 | break; | 453 | break; |
456 | 454 | ||
457 | case POR_BUS_SLOT16: | 455 | case POR_BUS_SLOT16: |
458 | pB->i2eDataWidth16 = NO; | 456 | pB->i2eDataWidth16 = false; |
459 | pB->i2eMaxIrq = 15; | 457 | pB->i2eMaxIrq = 15; |
460 | break; | 458 | break; |
461 | 459 | ||
462 | case 0: | 460 | case 0: |
463 | case POR_BUS_DIP16: // In an 8-bit slot, DIP switch don't care. | 461 | case POR_BUS_DIP16: // In an 8-bit slot, DIP switch don't care. |
464 | default: | 462 | default: |
465 | pB->i2eDataWidth16 = NO; | 463 | pB->i2eDataWidth16 = false; |
466 | pB->i2eMaxIrq = 7; | 464 | pB->i2eMaxIrq = 7; |
467 | break; | 465 | break; |
468 | } | 466 | } |
469 | break; // POR_ID_FIIEX case | 467 | break; // POR_ID_FIIEX case |
470 | 468 | ||
471 | default: // Unknown type of board | 469 | default: // Unknown type of board |
472 | COMPLETE(pB, I2EE_BAD_FAMILY); | 470 | I2_COMPLETE(pB, I2EE_BAD_FAMILY); |
473 | break; | 471 | break; |
474 | } // End the switch based on family | 472 | } // End the switch based on family |
475 | 473 | ||
@@ -483,17 +481,14 @@ iiInitialize(i2eBordStrPtr pB) | |||
483 | { | 481 | { |
484 | case POR_BUS_T_ISA: | 482 | case POR_BUS_T_ISA: |
485 | case POR_BUS_T_UNK: // If the type of bus is undeclared, assume ok. | 483 | case POR_BUS_T_UNK: // If the type of bus is undeclared, assume ok. |
486 | pB->i2eChangeIrq = YES; | ||
487 | break; | ||
488 | case POR_BUS_T_MCA: | 484 | case POR_BUS_T_MCA: |
489 | case POR_BUS_T_EISA: | 485 | case POR_BUS_T_EISA: |
490 | pB->i2eChangeIrq = NO; | ||
491 | break; | 486 | break; |
492 | default: | 487 | default: |
493 | COMPLETE(pB, I2EE_BADBUS); | 488 | I2_COMPLETE(pB, I2EE_BADBUS); |
494 | } | 489 | } |
495 | 490 | ||
496 | if (pB->i2eDataWidth16 == YES) | 491 | if (pB->i2eDataWidth16) |
497 | { | 492 | { |
498 | pB->i2eWriteBuf = iiWriteBuf16; | 493 | pB->i2eWriteBuf = iiWriteBuf16; |
499 | pB->i2eReadBuf = iiReadBuf16; | 494 | pB->i2eReadBuf = iiReadBuf16; |
@@ -529,7 +524,7 @@ iiInitialize(i2eBordStrPtr pB) | |||
529 | break; | 524 | break; |
530 | 525 | ||
531 | default: | 526 | default: |
532 | COMPLETE(pB, I2EE_INCONSIST); | 527 | I2_COMPLETE(pB, I2EE_INCONSIST); |
533 | } | 528 | } |
534 | 529 | ||
535 | // Initialize state information. | 530 | // Initialize state information. |
@@ -549,7 +544,7 @@ iiInitialize(i2eBordStrPtr pB) | |||
549 | // Everything is ok now, return with good status/ | 544 | // Everything is ok now, return with good status/ |
550 | 545 | ||
551 | pB->i2eValid = I2E_MAGIC; | 546 | pB->i2eValid = I2E_MAGIC; |
552 | COMPLETE(pB, I2EE_GOOD); | 547 | I2_COMPLETE(pB, I2EE_GOOD); |
553 | } | 548 | } |
554 | 549 | ||
555 | //****************************************************************************** | 550 | //****************************************************************************** |
@@ -658,7 +653,7 @@ ii2DelayIO(unsigned int mseconds) | |||
658 | while(mseconds--) { | 653 | while(mseconds--) { |
659 | int i = ii2DelValue; | 654 | int i = ii2DelValue; |
660 | while ( i-- ) { | 655 | while ( i-- ) { |
661 | INB ( ii2Safe ); | 656 | inb(ii2Safe); |
662 | } | 657 | } |
663 | } | 658 | } |
664 | } | 659 | } |
@@ -709,11 +704,11 @@ iiWriteBuf16(i2eBordStrPtr pB, unsigned char *address, int count) | |||
709 | { | 704 | { |
710 | // Rudimentary sanity checking here. | 705 | // Rudimentary sanity checking here. |
711 | if (pB->i2eValid != I2E_MAGIC) | 706 | if (pB->i2eValid != I2E_MAGIC) |
712 | COMPLETE(pB, I2EE_INVALID); | 707 | I2_COMPLETE(pB, I2EE_INVALID); |
713 | 708 | ||
714 | OUTSW ( pB->i2eData, address, count); | 709 | I2_OUTSW(pB->i2eData, address, count); |
715 | 710 | ||
716 | COMPLETE(pB, I2EE_GOOD); | 711 | I2_COMPLETE(pB, I2EE_GOOD); |
717 | } | 712 | } |
718 | 713 | ||
719 | //****************************************************************************** | 714 | //****************************************************************************** |
@@ -738,11 +733,11 @@ iiWriteBuf8(i2eBordStrPtr pB, unsigned char *address, int count) | |||
738 | { | 733 | { |
739 | /* Rudimentary sanity checking here */ | 734 | /* Rudimentary sanity checking here */ |
740 | if (pB->i2eValid != I2E_MAGIC) | 735 | if (pB->i2eValid != I2E_MAGIC) |
741 | COMPLETE(pB, I2EE_INVALID); | 736 | I2_COMPLETE(pB, I2EE_INVALID); |
742 | 737 | ||
743 | OUTSB ( pB->i2eData, address, count ); | 738 | I2_OUTSB(pB->i2eData, address, count); |
744 | 739 | ||
745 | COMPLETE(pB, I2EE_GOOD); | 740 | I2_COMPLETE(pB, I2EE_GOOD); |
746 | } | 741 | } |
747 | 742 | ||
748 | //****************************************************************************** | 743 | //****************************************************************************** |
@@ -767,11 +762,11 @@ iiReadBuf16(i2eBordStrPtr pB, unsigned char *address, int count) | |||
767 | { | 762 | { |
768 | // Rudimentary sanity checking here. | 763 | // Rudimentary sanity checking here. |
769 | if (pB->i2eValid != I2E_MAGIC) | 764 | if (pB->i2eValid != I2E_MAGIC) |
770 | COMPLETE(pB, I2EE_INVALID); | 765 | I2_COMPLETE(pB, I2EE_INVALID); |
771 | 766 | ||
772 | INSW ( pB->i2eData, address, count); | 767 | I2_INSW(pB->i2eData, address, count); |
773 | 768 | ||
774 | COMPLETE(pB, I2EE_GOOD); | 769 | I2_COMPLETE(pB, I2EE_GOOD); |
775 | } | 770 | } |
776 | 771 | ||
777 | //****************************************************************************** | 772 | //****************************************************************************** |
@@ -796,11 +791,11 @@ iiReadBuf8(i2eBordStrPtr pB, unsigned char *address, int count) | |||
796 | { | 791 | { |
797 | // Rudimentary sanity checking here. | 792 | // Rudimentary sanity checking here. |
798 | if (pB->i2eValid != I2E_MAGIC) | 793 | if (pB->i2eValid != I2E_MAGIC) |
799 | COMPLETE(pB, I2EE_INVALID); | 794 | I2_COMPLETE(pB, I2EE_INVALID); |
800 | 795 | ||
801 | INSB ( pB->i2eData, address, count); | 796 | I2_INSB(pB->i2eData, address, count); |
802 | 797 | ||
803 | COMPLETE(pB, I2EE_GOOD); | 798 | I2_COMPLETE(pB, I2EE_GOOD); |
804 | } | 799 | } |
805 | 800 | ||
806 | //****************************************************************************** | 801 | //****************************************************************************** |
@@ -820,7 +815,7 @@ iiReadBuf8(i2eBordStrPtr pB, unsigned char *address, int count) | |||
820 | static unsigned short | 815 | static unsigned short |
821 | iiReadWord16(i2eBordStrPtr pB) | 816 | iiReadWord16(i2eBordStrPtr pB) |
822 | { | 817 | { |
823 | return (unsigned short)( INW(pB->i2eData) ); | 818 | return inw(pB->i2eData); |
824 | } | 819 | } |
825 | 820 | ||
826 | //****************************************************************************** | 821 | //****************************************************************************** |
@@ -842,9 +837,9 @@ iiReadWord8(i2eBordStrPtr pB) | |||
842 | { | 837 | { |
843 | unsigned short urs; | 838 | unsigned short urs; |
844 | 839 | ||
845 | urs = INB ( pB->i2eData ); | 840 | urs = inb(pB->i2eData); |
846 | 841 | ||
847 | return ( ( INB ( pB->i2eData ) << 8 ) | urs ); | 842 | return (inb(pB->i2eData) << 8) | urs; |
848 | } | 843 | } |
849 | 844 | ||
850 | //****************************************************************************** | 845 | //****************************************************************************** |
@@ -865,7 +860,7 @@ iiReadWord8(i2eBordStrPtr pB) | |||
865 | static void | 860 | static void |
866 | iiWriteWord16(i2eBordStrPtr pB, unsigned short value) | 861 | iiWriteWord16(i2eBordStrPtr pB, unsigned short value) |
867 | { | 862 | { |
868 | WORD_TO(pB, (int)value); | 863 | outw((int)value, pB->i2eData); |
869 | } | 864 | } |
870 | 865 | ||
871 | //****************************************************************************** | 866 | //****************************************************************************** |
@@ -886,8 +881,8 @@ iiWriteWord16(i2eBordStrPtr pB, unsigned short value) | |||
886 | static void | 881 | static void |
887 | iiWriteWord8(i2eBordStrPtr pB, unsigned short value) | 882 | iiWriteWord8(i2eBordStrPtr pB, unsigned short value) |
888 | { | 883 | { |
889 | BYTE_TO(pB, (char)value); | 884 | outb((char)value, pB->i2eData); |
890 | BYTE_TO(pB, (char)(value >> 8) ); | 885 | outb((char)(value >> 8), pB->i2eData); |
891 | } | 886 | } |
892 | 887 | ||
893 | //****************************************************************************** | 888 | //****************************************************************************** |
@@ -939,30 +934,30 @@ iiWaitForTxEmptyII(i2eBordStrPtr pB, int mSdelay) | |||
939 | // interrupts of any kind. | 934 | // interrupts of any kind. |
940 | 935 | ||
941 | 936 | ||
942 | WRITE_LOCK_IRQSAVE(&Dl_spinlock,flags) | 937 | write_lock_irqsave(&Dl_spinlock, flags); |
943 | OUTB(pB->i2ePointer, SEL_COMMAND); | 938 | outb(SEL_COMMAND, pB->i2ePointer); |
944 | OUTB(pB->i2ePointer, SEL_CMD_SH); | 939 | outb(SEL_CMD_SH, pB->i2ePointer); |
945 | 940 | ||
946 | itemp = INB(pB->i2eStatus); | 941 | itemp = inb(pB->i2eStatus); |
947 | 942 | ||
948 | OUTB(pB->i2ePointer, SEL_COMMAND); | 943 | outb(SEL_COMMAND, pB->i2ePointer); |
949 | OUTB(pB->i2ePointer, SEL_CMD_UNSH); | 944 | outb(SEL_CMD_UNSH, pB->i2ePointer); |
950 | 945 | ||
951 | if (itemp & ST_IN_EMPTY) | 946 | if (itemp & ST_IN_EMPTY) |
952 | { | 947 | { |
953 | UPDATE_FIFO_ROOM(pB); | 948 | I2_UPDATE_FIFO_ROOM(pB); |
954 | WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags) | 949 | write_unlock_irqrestore(&Dl_spinlock, flags); |
955 | COMPLETE(pB, I2EE_GOOD); | 950 | I2_COMPLETE(pB, I2EE_GOOD); |
956 | } | 951 | } |
957 | 952 | ||
958 | WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags) | 953 | write_unlock_irqrestore(&Dl_spinlock, flags); |
959 | 954 | ||
960 | if (mSdelay-- == 0) | 955 | if (mSdelay-- == 0) |
961 | break; | 956 | break; |
962 | 957 | ||
963 | iiDelay(pB, 1); /* 1 mS granularity on checking condition */ | 958 | iiDelay(pB, 1); /* 1 mS granularity on checking condition */ |
964 | } | 959 | } |
965 | COMPLETE(pB, I2EE_TXE_TIME); | 960 | I2_COMPLETE(pB, I2EE_TXE_TIME); |
966 | } | 961 | } |
967 | 962 | ||
968 | //****************************************************************************** | 963 | //****************************************************************************** |
@@ -1002,21 +997,21 @@ iiWaitForTxEmptyIIEX(i2eBordStrPtr pB, int mSdelay) | |||
1002 | // you will generally not want to service interrupts or in any way | 997 | // you will generally not want to service interrupts or in any way |
1003 | // disrupt the assumptions implicit in the larger context. | 998 | // disrupt the assumptions implicit in the larger context. |
1004 | 999 | ||
1005 | WRITE_LOCK_IRQSAVE(&Dl_spinlock,flags) | 1000 | write_lock_irqsave(&Dl_spinlock, flags); |
1006 | 1001 | ||
1007 | if (INB(pB->i2eStatus) & STE_OUT_MT) { | 1002 | if (inb(pB->i2eStatus) & STE_OUT_MT) { |
1008 | UPDATE_FIFO_ROOM(pB); | 1003 | I2_UPDATE_FIFO_ROOM(pB); |
1009 | WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags) | 1004 | write_unlock_irqrestore(&Dl_spinlock, flags); |
1010 | COMPLETE(pB, I2EE_GOOD); | 1005 | I2_COMPLETE(pB, I2EE_GOOD); |
1011 | } | 1006 | } |
1012 | WRITE_UNLOCK_IRQRESTORE(&Dl_spinlock,flags) | 1007 | write_unlock_irqrestore(&Dl_spinlock, flags); |
1013 | 1008 | ||
1014 | if (mSdelay-- == 0) | 1009 | if (mSdelay-- == 0) |
1015 | break; | 1010 | break; |
1016 | 1011 | ||
1017 | iiDelay(pB, 1); // 1 mS granularity on checking condition | 1012 | iiDelay(pB, 1); // 1 mS granularity on checking condition |
1018 | } | 1013 | } |
1019 | COMPLETE(pB, I2EE_TXE_TIME); | 1014 | I2_COMPLETE(pB, I2EE_TXE_TIME); |
1020 | } | 1015 | } |
1021 | 1016 | ||
1022 | //****************************************************************************** | 1017 | //****************************************************************************** |
@@ -1038,8 +1033,8 @@ static int | |||
1038 | iiTxMailEmptyII(i2eBordStrPtr pB) | 1033 | iiTxMailEmptyII(i2eBordStrPtr pB) |
1039 | { | 1034 | { |
1040 | int port = pB->i2ePointer; | 1035 | int port = pB->i2ePointer; |
1041 | OUTB ( port, SEL_OUTMAIL ); | 1036 | outb(SEL_OUTMAIL, port); |
1042 | return ( INB(port) == 0 ); | 1037 | return inb(port) == 0; |
1043 | } | 1038 | } |
1044 | 1039 | ||
1045 | //****************************************************************************** | 1040 | //****************************************************************************** |
@@ -1060,7 +1055,7 @@ iiTxMailEmptyII(i2eBordStrPtr pB) | |||
1060 | static int | 1055 | static int |
1061 | iiTxMailEmptyIIEX(i2eBordStrPtr pB) | 1056 | iiTxMailEmptyIIEX(i2eBordStrPtr pB) |
1062 | { | 1057 | { |
1063 | return !(INB(pB->i2eStatus) & STE_OUT_MAIL); | 1058 | return !(inb(pB->i2eStatus) & STE_OUT_MAIL); |
1064 | } | 1059 | } |
1065 | 1060 | ||
1066 | //****************************************************************************** | 1061 | //****************************************************************************** |
@@ -1084,10 +1079,10 @@ iiTrySendMailII(i2eBordStrPtr pB, unsigned char mail) | |||
1084 | { | 1079 | { |
1085 | int port = pB->i2ePointer; | 1080 | int port = pB->i2ePointer; |
1086 | 1081 | ||
1087 | OUTB(port, SEL_OUTMAIL); | 1082 | outb(SEL_OUTMAIL, port); |
1088 | if (INB(port) == 0) { | 1083 | if (inb(port) == 0) { |
1089 | OUTB(port, SEL_OUTMAIL); | 1084 | outb(SEL_OUTMAIL, port); |
1090 | OUTB(port, mail); | 1085 | outb(mail, port); |
1091 | return 1; | 1086 | return 1; |
1092 | } | 1087 | } |
1093 | return 0; | 1088 | return 0; |
@@ -1112,10 +1107,9 @@ iiTrySendMailII(i2eBordStrPtr pB, unsigned char mail) | |||
1112 | static int | 1107 | static int |
1113 | iiTrySendMailIIEX(i2eBordStrPtr pB, unsigned char mail) | 1108 | iiTrySendMailIIEX(i2eBordStrPtr pB, unsigned char mail) |
1114 | { | 1109 | { |
1115 | if(INB(pB->i2eStatus) & STE_OUT_MAIL) { | 1110 | if (inb(pB->i2eStatus) & STE_OUT_MAIL) |
1116 | return 0; | 1111 | return 0; |
1117 | } | 1112 | outb(mail, pB->i2eXMail); |
1118 | OUTB(pB->i2eXMail, mail); | ||
1119 | return 1; | 1113 | return 1; |
1120 | } | 1114 | } |
1121 | 1115 | ||
@@ -1136,9 +1130,9 @@ iiTrySendMailIIEX(i2eBordStrPtr pB, unsigned char mail) | |||
1136 | static unsigned short | 1130 | static unsigned short |
1137 | iiGetMailII(i2eBordStrPtr pB) | 1131 | iiGetMailII(i2eBordStrPtr pB) |
1138 | { | 1132 | { |
1139 | if (HAS_MAIL(pB)) { | 1133 | if (I2_HAS_MAIL(pB)) { |
1140 | OUTB(pB->i2ePointer, SEL_INMAIL); | 1134 | outb(SEL_INMAIL, pB->i2ePointer); |
1141 | return INB(pB->i2ePointer); | 1135 | return inb(pB->i2ePointer); |
1142 | } else { | 1136 | } else { |
1143 | return NO_MAIL_HERE; | 1137 | return NO_MAIL_HERE; |
1144 | } | 1138 | } |
@@ -1161,11 +1155,10 @@ iiGetMailII(i2eBordStrPtr pB) | |||
1161 | static unsigned short | 1155 | static unsigned short |
1162 | iiGetMailIIEX(i2eBordStrPtr pB) | 1156 | iiGetMailIIEX(i2eBordStrPtr pB) |
1163 | { | 1157 | { |
1164 | if (HAS_MAIL(pB)) { | 1158 | if (I2_HAS_MAIL(pB)) |
1165 | return INB(pB->i2eXMail); | 1159 | return inb(pB->i2eXMail); |
1166 | } else { | 1160 | else |
1167 | return NO_MAIL_HERE; | 1161 | return NO_MAIL_HERE; |
1168 | } | ||
1169 | } | 1162 | } |
1170 | 1163 | ||
1171 | //****************************************************************************** | 1164 | //****************************************************************************** |
@@ -1184,8 +1177,8 @@ iiGetMailIIEX(i2eBordStrPtr pB) | |||
1184 | static void | 1177 | static void |
1185 | iiEnableMailIrqII(i2eBordStrPtr pB) | 1178 | iiEnableMailIrqII(i2eBordStrPtr pB) |
1186 | { | 1179 | { |
1187 | OUTB(pB->i2ePointer, SEL_MASK); | 1180 | outb(SEL_MASK, pB->i2ePointer); |
1188 | OUTB(pB->i2ePointer, ST_IN_MAIL); | 1181 | outb(ST_IN_MAIL, pB->i2ePointer); |
1189 | } | 1182 | } |
1190 | 1183 | ||
1191 | //****************************************************************************** | 1184 | //****************************************************************************** |
@@ -1204,7 +1197,7 @@ iiEnableMailIrqII(i2eBordStrPtr pB) | |||
1204 | static void | 1197 | static void |
1205 | iiEnableMailIrqIIEX(i2eBordStrPtr pB) | 1198 | iiEnableMailIrqIIEX(i2eBordStrPtr pB) |
1206 | { | 1199 | { |
1207 | OUTB(pB->i2eXMask, MX_IN_MAIL); | 1200 | outb(MX_IN_MAIL, pB->i2eXMask); |
1208 | } | 1201 | } |
1209 | 1202 | ||
1210 | //****************************************************************************** | 1203 | //****************************************************************************** |
@@ -1223,8 +1216,8 @@ iiEnableMailIrqIIEX(i2eBordStrPtr pB) | |||
1223 | static void | 1216 | static void |
1224 | iiWriteMaskII(i2eBordStrPtr pB, unsigned char value) | 1217 | iiWriteMaskII(i2eBordStrPtr pB, unsigned char value) |
1225 | { | 1218 | { |
1226 | OUTB(pB->i2ePointer, SEL_MASK); | 1219 | outb(SEL_MASK, pB->i2ePointer); |
1227 | OUTB(pB->i2ePointer, value); | 1220 | outb(value, pB->i2ePointer); |
1228 | } | 1221 | } |
1229 | 1222 | ||
1230 | //****************************************************************************** | 1223 | //****************************************************************************** |
@@ -1243,7 +1236,7 @@ iiWriteMaskII(i2eBordStrPtr pB, unsigned char value) | |||
1243 | static void | 1236 | static void |
1244 | iiWriteMaskIIEX(i2eBordStrPtr pB, unsigned char value) | 1237 | iiWriteMaskIIEX(i2eBordStrPtr pB, unsigned char value) |
1245 | { | 1238 | { |
1246 | OUTB(pB->i2eXMask, value); | 1239 | outb(value, pB->i2eXMask); |
1247 | } | 1240 | } |
1248 | 1241 | ||
1249 | //****************************************************************************** | 1242 | //****************************************************************************** |
@@ -1354,9 +1347,8 @@ iiDownloadBlock ( i2eBordStrPtr pB, loadHdrStrPtr pSource, int isStandard) | |||
1354 | // immediately and be harmless, though not strictly necessary. | 1347 | // immediately and be harmless, though not strictly necessary. |
1355 | itemp = MAX_DLOAD_ACK_TIME/10; | 1348 | itemp = MAX_DLOAD_ACK_TIME/10; |
1356 | while (--itemp) { | 1349 | while (--itemp) { |
1357 | if (HAS_INPUT(pB)) { | 1350 | if (I2_HAS_INPUT(pB)) { |
1358 | switch(BYTE_FROM(pB)) | 1351 | switch (inb(pB->i2eData)) { |
1359 | { | ||
1360 | case LOADWARE_OK: | 1352 | case LOADWARE_OK: |
1361 | pB->i2eState = | 1353 | pB->i2eState = |
1362 | isStandard ? II_STATE_STDLOADED :II_STATE_LOADED; | 1354 | isStandard ? II_STATE_STDLOADED :II_STATE_LOADED; |