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authorDave Airlie <airlied@starflyer.(none)>2005-09-25 00:28:13 -0400
committerDave Airlie <airlied@linux.ie>2005-09-25 00:28:13 -0400
commitb5e89ed53ed8d24f83ba1941c07382af00ed238e (patch)
tree747bae7a565f88a2e1d5974776eeb054a932c505 /drivers/char/drm
parent99a2657a29e2d623c3568cd86b27cac13fb63140 (diff)
drm: lindent the drm directory.
I've been threatening this for a while, so no point hanging around. This lindents the DRM code which was always really bad in tabbing department. I've also fixed some misnamed files in comments and removed some trailing whitespace. Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/char/drm')
-rw-r--r--drivers/char/drm/ati_pcigart.c123
-rw-r--r--drivers/char/drm/drm.h295
-rw-r--r--drivers/char/drm/drmP.h863
-rw-r--r--drivers/char/drm/drm_agpsupport.c150
-rw-r--r--drivers/char/drm/drm_auth.c68
-rw-r--r--drivers/char/drm/drm_bufs.c883
-rw-r--r--drivers/char/drm/drm_context.c304
-rw-r--r--drivers/char/drm/drm_dma.c87
-rw-r--r--drivers/char/drm/drm_drawable.c8
-rw-r--r--drivers/char/drm/drm_drv.c361
-rw-r--r--drivers/char/drm/drm_fops.c293
-rw-r--r--drivers/char/drm/drm_init.c7
-rw-r--r--drivers/char/drm/drm_ioc32.c225
-rw-r--r--drivers/char/drm/drm_ioctl.c168
-rw-r--r--drivers/char/drm/drm_irq.c169
-rw-r--r--drivers/char/drm/drm_lock.c177
-rw-r--r--drivers/char/drm/drm_memory.c54
-rw-r--r--drivers/char/drm/drm_memory.h73
-rw-r--r--drivers/char/drm/drm_memory_debug.h224
-rw-r--r--drivers/char/drm/drm_os_linux.h17
-rw-r--r--drivers/char/drm/drm_pci.c10
-rw-r--r--drivers/char/drm/drm_pciids.h1
-rw-r--r--drivers/char/drm/drm_proc.c272
-rw-r--r--drivers/char/drm/drm_sarea.h30
-rw-r--r--drivers/char/drm/drm_scatter.c183
-rw-r--r--drivers/char/drm/drm_stub.c112
-rw-r--r--drivers/char/drm/drm_vm.c369
-rw-r--r--drivers/char/drm/ffb_context.c230
-rw-r--r--drivers/char/drm/ffb_drv.c139
-rw-r--r--drivers/char/drm/ffb_drv.h433
-rw-r--r--drivers/char/drm/i810_dma.c1101
-rw-r--r--drivers/char/drm/i810_drm.h75
-rw-r--r--drivers/char/drm/i810_drv.c60
-rw-r--r--drivers/char/drm/i810_drv.h38
-rw-r--r--drivers/char/drm/i830_dma.c1328
-rw-r--r--drivers/char/drm/i830_drm.h90
-rw-r--r--drivers/char/drm/i830_drv.c59
-rw-r--r--drivers/char/drm/i830_drv.h67
-rw-r--r--drivers/char/drm/i830_irq.c137
-rw-r--r--drivers/char/drm/i915_dma.c65
-rw-r--r--drivers/char/drm/i915_drv.c61
-rw-r--r--drivers/char/drm/i915_drv.h13
-rw-r--r--drivers/char/drm/i915_ioc32.c64
-rw-r--r--drivers/char/drm/i915_mem.c8
-rw-r--r--drivers/char/drm/mga_dma.c511
-rw-r--r--drivers/char/drm/mga_drm.h142
-rw-r--r--drivers/char/drm/mga_drv.c75
-rw-r--r--drivers/char/drm/mga_drv.h42
-rw-r--r--drivers/char/drm/mga_ioc32.c60
-rw-r--r--drivers/char/drm/mga_irq.c42
-rw-r--r--drivers/char/drm/mga_state.c894
-rw-r--r--drivers/char/drm/mga_ucode.h16070
-rw-r--r--drivers/char/drm/mga_warp.c120
-rw-r--r--drivers/char/drm/r128_cce.c590
-rw-r--r--drivers/char/drm/r128_drm.h32
-rw-r--r--drivers/char/drm/r128_drv.c60
-rw-r--r--drivers/char/drm/r128_drv.h67
-rw-r--r--drivers/char/drm/r128_ioc32.c35
-rw-r--r--drivers/char/drm/r128_irq.c53
-rw-r--r--drivers/char/drm/r128_state.c1386
-rw-r--r--drivers/char/drm/r300_cmdbuf.c502
-rw-r--r--drivers/char/drm/r300_reg.h192
-rw-r--r--drivers/char/drm/radeon_cp.c2480
-rw-r--r--drivers/char/drm/radeon_drm.h276
-rw-r--r--drivers/char/drm/radeon_drv.c61
-rw-r--r--drivers/char/drm/radeon_drv.h149
-rw-r--r--drivers/char/drm/radeon_ioc32.c51
-rw-r--r--drivers/char/drm/radeon_irq.c127
-rw-r--r--drivers/char/drm/radeon_mem.c148
-rw-r--r--drivers/char/drm/radeon_state.c2493
-rw-r--r--drivers/char/drm/savage_bci.c201
-rw-r--r--drivers/char/drm/savage_drm.h53
-rw-r--r--drivers/char/drm/savage_drv.c56
-rw-r--r--drivers/char/drm/savage_drv.h58
-rw-r--r--drivers/char/drm/savage_state.c483
-rw-r--r--drivers/char/drm/sis_drm.h2
-rw-r--r--drivers/char/drm/sis_drv.c58
-rw-r--r--drivers/char/drm/sis_drv.h10
-rw-r--r--drivers/char/drm/sis_ds.c82
-rw-r--r--drivers/char/drm/sis_ds.h40
-rw-r--r--drivers/char/drm/sis_mm.c132
-rw-r--r--drivers/char/drm/tdfx_drv.c52
-rw-r--r--drivers/char/drm/via_3d_reg.h1
-rw-r--r--drivers/char/drm/via_dma.c259
-rw-r--r--drivers/char/drm/via_drm.h4
-rw-r--r--drivers/char/drm/via_drv.c22
-rw-r--r--drivers/char/drm/via_drv.h21
-rw-r--r--drivers/char/drm/via_irq.c106
-rw-r--r--drivers/char/drm/via_map.c4
-rw-r--r--drivers/char/drm/via_mm.c17
-rw-r--r--drivers/char/drm/via_verifier.c483
-rw-r--r--drivers/char/drm/via_verifier.h22
-rw-r--r--drivers/char/drm/via_video.c30
93 files changed, 19197 insertions, 19151 deletions
diff --git a/drivers/char/drm/ati_pcigart.c b/drivers/char/drm/ati_pcigart.c
index 957596c63934..d07ce96e9f4b 100644
--- a/drivers/char/drm/ati_pcigart.c
+++ b/drivers/char/drm/ati_pcigart.c
@@ -1,5 +1,5 @@
1/** 1/**
2 * \file ati_pcigart.h 2 * \file ati_pcigart.c
3 * ATI PCI GART support 3 * ATI PCI GART support
4 * 4 *
5 * \author Gareth Hughes <gareth@valinux.com> 5 * \author Gareth Hughes <gareth@valinux.com>
@@ -52,87 +52,91 @@
52# define ATI_MAX_PCIGART_PAGES 8192 /**< 32 MB aperture, 4K pages */ 52# define ATI_MAX_PCIGART_PAGES 8192 /**< 32 MB aperture, 4K pages */
53# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ 53# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
54 54
55static unsigned long drm_ati_alloc_pcigart_table( void ) 55static unsigned long drm_ati_alloc_pcigart_table(void)
56{ 56{
57 unsigned long address; 57 unsigned long address;
58 struct page *page; 58 struct page *page;
59 int i; 59 int i;
60 DRM_DEBUG( "%s\n", __FUNCTION__ ); 60 DRM_DEBUG("%s\n", __FUNCTION__);
61 61
62 address = __get_free_pages( GFP_KERNEL, ATI_PCIGART_TABLE_ORDER ); 62 address = __get_free_pages(GFP_KERNEL, ATI_PCIGART_TABLE_ORDER);
63 if ( address == 0UL ) { 63 if (address == 0UL) {
64 return 0; 64 return 0;
65 } 65 }
66 66
67 page = virt_to_page( address ); 67 page = virt_to_page(address);
68 68
69 for ( i = 0 ; i < ATI_PCIGART_TABLE_PAGES ; i++, page++ ) { 69 for (i = 0; i < ATI_PCIGART_TABLE_PAGES; i++, page++) {
70 get_page(page); 70 get_page(page);
71 SetPageReserved( page ); 71 SetPageReserved(page);
72 } 72 }
73 73
74 DRM_DEBUG( "%s: returning 0x%08lx\n", __FUNCTION__, address ); 74 DRM_DEBUG("%s: returning 0x%08lx\n", __FUNCTION__, address);
75 return address; 75 return address;
76} 76}
77 77
78static void drm_ati_free_pcigart_table( unsigned long address ) 78static void drm_ati_free_pcigart_table(unsigned long address)
79{ 79{
80 struct page *page; 80 struct page *page;
81 int i; 81 int i;
82 DRM_DEBUG( "%s\n", __FUNCTION__ ); 82 DRM_DEBUG("%s\n", __FUNCTION__);
83 83
84 page = virt_to_page( address ); 84 page = virt_to_page(address);
85 85
86 for ( i = 0 ; i < ATI_PCIGART_TABLE_PAGES ; i++, page++ ) { 86 for (i = 0; i < ATI_PCIGART_TABLE_PAGES; i++, page++) {
87 __put_page(page); 87 __put_page(page);
88 ClearPageReserved( page ); 88 ClearPageReserved(page);
89 } 89 }
90 90
91 free_pages( address, ATI_PCIGART_TABLE_ORDER ); 91 free_pages(address, ATI_PCIGART_TABLE_ORDER);
92} 92}
93 93
94int drm_ati_pcigart_cleanup(drm_device_t *dev, drm_ati_pcigart_info *gart_info) 94int drm_ati_pcigart_cleanup(drm_device_t * dev,
95 drm_ati_pcigart_info * gart_info)
95{ 96{
96 drm_sg_mem_t *entry = dev->sg; 97 drm_sg_mem_t *entry = dev->sg;
97 unsigned long pages; 98 unsigned long pages;
98 int i; 99 int i;
99 100
100 /* we need to support large memory configurations */ 101 /* we need to support large memory configurations */
101 if ( !entry ) { 102 if (!entry) {
102 DRM_ERROR( "no scatter/gather memory!\n" ); 103 DRM_ERROR("no scatter/gather memory!\n");
103 return 0; 104 return 0;
104 } 105 }
105 106
106 if (gart_info->bus_addr) { 107 if (gart_info->bus_addr) {
107 if (gart_info->gart_table_location==DRM_ATI_GART_MAIN) { 108 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
108 pci_unmap_single(dev->pdev, gart_info->bus_addr, 109 pci_unmap_single(dev->pdev, gart_info->bus_addr,
109 ATI_PCIGART_TABLE_PAGES * PAGE_SIZE, 110 ATI_PCIGART_TABLE_PAGES * PAGE_SIZE,
110 PCI_DMA_TODEVICE); 111 PCI_DMA_TODEVICE);
111 } 112 }
112 113
113 pages = ( entry->pages <= ATI_MAX_PCIGART_PAGES ) 114 pages = (entry->pages <= ATI_MAX_PCIGART_PAGES)
114 ? entry->pages : ATI_MAX_PCIGART_PAGES; 115 ? entry->pages : ATI_MAX_PCIGART_PAGES;
115 116
116 for ( i = 0 ; i < pages ; i++ ) { 117 for (i = 0; i < pages; i++) {
117 if ( !entry->busaddr[i] ) break; 118 if (!entry->busaddr[i])
119 break;
118 pci_unmap_single(dev->pdev, entry->busaddr[i], 120 pci_unmap_single(dev->pdev, entry->busaddr[i],
119 PAGE_SIZE, PCI_DMA_TODEVICE); 121 PAGE_SIZE, PCI_DMA_TODEVICE);
120 } 122 }
121 123
122 if (gart_info->gart_table_location==DRM_ATI_GART_MAIN) 124 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
123 gart_info->bus_addr=0; 125 gart_info->bus_addr = 0;
124 } 126 }
125 127
126 if (gart_info->gart_table_location==DRM_ATI_GART_MAIN && gart_info->addr) { 128 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN
129 && gart_info->addr) {
127 drm_ati_free_pcigart_table(gart_info->addr); 130 drm_ati_free_pcigart_table(gart_info->addr);
128 gart_info->addr=0; 131 gart_info->addr = 0;
129 } 132 }
130 133
131 return 1; 134 return 1;
132} 135}
136
133EXPORT_SYMBOL(drm_ati_pcigart_cleanup); 137EXPORT_SYMBOL(drm_ati_pcigart_cleanup);
134 138
135int drm_ati_pcigart_init(drm_device_t *dev, drm_ati_pcigart_info *gart_info) 139int drm_ati_pcigart_init(drm_device_t * dev, drm_ati_pcigart_info * gart_info)
136{ 140{
137 drm_sg_mem_t *entry = dev->sg; 141 drm_sg_mem_t *entry = dev->sg;
138 unsigned long address = 0; 142 unsigned long address = 0;
@@ -140,58 +144,56 @@ int drm_ati_pcigart_init(drm_device_t *dev, drm_ati_pcigart_info *gart_info)
140 u32 *pci_gart, page_base, bus_address = 0; 144 u32 *pci_gart, page_base, bus_address = 0;
141 int i, j, ret = 0; 145 int i, j, ret = 0;
142 146
143 if ( !entry ) { 147 if (!entry) {
144 DRM_ERROR( "no scatter/gather memory!\n" ); 148 DRM_ERROR("no scatter/gather memory!\n");
145 goto done; 149 goto done;
146 } 150 }
147 151
148 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) 152 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
149 {
150 DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n"); 153 DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");
151 154
152 address = drm_ati_alloc_pcigart_table(); 155 address = drm_ati_alloc_pcigart_table();
153 if ( !address ) { 156 if (!address) {
154 DRM_ERROR( "cannot allocate PCI GART page!\n" ); 157 DRM_ERROR("cannot allocate PCI GART page!\n");
155 goto done; 158 goto done;
156 } 159 }
157 160
158 if ( !dev->pdev ) { 161 if (!dev->pdev) {
159 DRM_ERROR( "PCI device unknown!\n" ); 162 DRM_ERROR("PCI device unknown!\n");
160 goto done; 163 goto done;
161 } 164 }
162 165
163 bus_address = pci_map_single(dev->pdev, (void *)address, 166 bus_address = pci_map_single(dev->pdev, (void *)address,
164 ATI_PCIGART_TABLE_PAGES * PAGE_SIZE, 167 ATI_PCIGART_TABLE_PAGES *
165 PCI_DMA_TODEVICE); 168 PAGE_SIZE, PCI_DMA_TODEVICE);
166 if (bus_address == 0) { 169 if (bus_address == 0) {
167 DRM_ERROR( "unable to map PCIGART pages!\n" ); 170 DRM_ERROR("unable to map PCIGART pages!\n");
168 drm_ati_free_pcigart_table( address ); 171 drm_ati_free_pcigart_table(address);
169 address = 0; 172 address = 0;
170 goto done; 173 goto done;
171 } 174 }
172 } 175 } else {
173 else
174 {
175 address = gart_info->addr; 176 address = gart_info->addr;
176 bus_address = gart_info->bus_addr; 177 bus_address = gart_info->bus_addr;
177 DRM_DEBUG("PCI: Gart Table: VRAM %08X mapped at %08lX\n", bus_address, address); 178 DRM_DEBUG("PCI: Gart Table: VRAM %08X mapped at %08lX\n",
179 bus_address, address);
178 } 180 }
179 181
180 pci_gart = (u32 *)address; 182 pci_gart = (u32 *) address;
181 183
182 pages = ( entry->pages <= ATI_MAX_PCIGART_PAGES ) 184 pages = (entry->pages <= ATI_MAX_PCIGART_PAGES)
183 ? entry->pages : ATI_MAX_PCIGART_PAGES; 185 ? entry->pages : ATI_MAX_PCIGART_PAGES;
184 186
185 memset( pci_gart, 0, ATI_MAX_PCIGART_PAGES * sizeof(u32) ); 187 memset(pci_gart, 0, ATI_MAX_PCIGART_PAGES * sizeof(u32));
186 188
187 for ( i = 0 ; i < pages ; i++ ) { 189 for (i = 0; i < pages; i++) {
188 /* we need to support large memory configurations */ 190 /* we need to support large memory configurations */
189 entry->busaddr[i] = pci_map_single(dev->pdev, 191 entry->busaddr[i] = pci_map_single(dev->pdev,
190 page_address( entry->pagelist[i] ), 192 page_address(entry->
191 PAGE_SIZE, 193 pagelist[i]),
192 PCI_DMA_TODEVICE); 194 PAGE_SIZE, PCI_DMA_TODEVICE);
193 if (entry->busaddr[i] == 0) { 195 if (entry->busaddr[i] == 0) {
194 DRM_ERROR( "unable to map PCIGART pages!\n" ); 196 DRM_ERROR("unable to map PCIGART pages!\n");
195 drm_ati_pcigart_cleanup(dev, gart_info); 197 drm_ati_pcigart_cleanup(dev, gart_info);
196 address = 0; 198 address = 0;
197 bus_address = 0; 199 bus_address = 0;
@@ -201,9 +203,9 @@ int drm_ati_pcigart_init(drm_device_t *dev, drm_ati_pcigart_info *gart_info)
201 203
202 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { 204 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
203 if (gart_info->is_pcie) 205 if (gart_info->is_pcie)
204 *pci_gart = (cpu_to_le32(page_base)>>8) | 0xc; 206 *pci_gart = (cpu_to_le32(page_base) >> 8) | 0xc;
205 else 207 else
206 *pci_gart++ = cpu_to_le32( page_base ); 208 *pci_gart++ = cpu_to_le32(page_base);
207 page_base += ATI_PCIGART_PAGE_SIZE; 209 page_base += ATI_PCIGART_PAGE_SIZE;
208 } 210 }
209 } 211 }
@@ -216,9 +218,10 @@ int drm_ati_pcigart_init(drm_device_t *dev, drm_ati_pcigart_info *gart_info)
216 mb(); 218 mb();
217#endif 219#endif
218 220
219done: 221 done:
220 gart_info->addr = address; 222 gart_info->addr = address;
221 gart_info->bus_addr = bus_address; 223 gart_info->bus_addr = bus_address;
222 return ret; 224 return ret;
223} 225}
226
224EXPORT_SYMBOL(drm_ati_pcigart_init); 227EXPORT_SYMBOL(drm_ati_pcigart_init);
diff --git a/drivers/char/drm/drm.h b/drivers/char/drm/drm.h
index fc6598a81acd..64d6237fdd0b 100644
--- a/drivers/char/drm/drm.h
+++ b/drivers/char/drm/drm.h
@@ -1,7 +1,7 @@
1/** 1/**
2 * \file drm.h 2 * \file drm.h
3 * Header for the Direct Rendering Manager 3 * Header for the Direct Rendering Manager
4 * 4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
6 * 6 *
7 * \par Acknowledgments: 7 * \par Acknowledgments:
@@ -33,7 +33,6 @@
33 * OTHER DEALINGS IN THE SOFTWARE. 33 * OTHER DEALINGS IN THE SOFTWARE.
34 */ 34 */
35 35
36
37#ifndef _DRM_H_ 36#ifndef _DRM_H_
38#define _DRM_H_ 37#define _DRM_H_
39 38
@@ -56,7 +55,7 @@
56#define ioctl(a,b,c) xf86ioctl(a,b,c) 55#define ioctl(a,b,c) xf86ioctl(a,b,c)
57#else 56#else
58#include <sys/ioccom.h> 57#include <sys/ioccom.h>
59#endif /* __FreeBSD__ && xf86ioctl */ 58#endif /* __FreeBSD__ && xf86ioctl */
60#define DRM_IOCTL_NR(n) ((n) & 0xff) 59#define DRM_IOCTL_NR(n) ((n) & 0xff)
61#define DRM_IOC_VOID IOC_VOID 60#define DRM_IOC_VOID IOC_VOID
62#define DRM_IOC_READ IOC_OUT 61#define DRM_IOC_READ IOC_OUT
@@ -97,16 +96,14 @@
97#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) 96#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
98#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) 97#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
99 98
100 99typedef unsigned int drm_handle_t;
101typedef unsigned int drm_handle_t; 100typedef unsigned int drm_context_t;
102typedef unsigned int drm_context_t; 101typedef unsigned int drm_drawable_t;
103typedef unsigned int drm_drawable_t; 102typedef unsigned int drm_magic_t;
104typedef unsigned int drm_magic_t;
105
106 103
107/** 104/**
108 * Cliprect. 105 * Cliprect.
109 * 106 *
110 * \warning: If you change this structure, make sure you change 107 * \warning: If you change this structure, make sure you change
111 * XF86DRIClipRectRec in the server as well 108 * XF86DRIClipRectRec in the server as well
112 * 109 *
@@ -114,22 +111,21 @@ typedef unsigned int drm_magic_t;
114 * backwards-compatibility reasons. 111 * backwards-compatibility reasons.
115 */ 112 */
116typedef struct drm_clip_rect { 113typedef struct drm_clip_rect {
117 unsigned short x1; 114 unsigned short x1;
118 unsigned short y1; 115 unsigned short y1;
119 unsigned short x2; 116 unsigned short x2;
120 unsigned short y2; 117 unsigned short y2;
121} drm_clip_rect_t; 118} drm_clip_rect_t;
122 119
123
124/** 120/**
125 * Texture region, 121 * Texture region,
126 */ 122 */
127typedef struct drm_tex_region { 123typedef struct drm_tex_region {
128 unsigned char next; 124 unsigned char next;
129 unsigned char prev; 125 unsigned char prev;
130 unsigned char in_use; 126 unsigned char in_use;
131 unsigned char padding; 127 unsigned char padding;
132 unsigned int age; 128 unsigned int age;
133} drm_tex_region_t; 129} drm_tex_region_t;
134 130
135/** 131/**
@@ -141,28 +137,26 @@ typedef struct drm_tex_region {
141 */ 137 */
142typedef struct drm_hw_lock { 138typedef struct drm_hw_lock {
143 __volatile__ unsigned int lock; /**< lock variable */ 139 __volatile__ unsigned int lock; /**< lock variable */
144 char padding[60]; /**< Pad to cache line */ 140 char padding[60]; /**< Pad to cache line */
145} drm_hw_lock_t; 141} drm_hw_lock_t;
146 142
147
148/** 143/**
149 * DRM_IOCTL_VERSION ioctl argument type. 144 * DRM_IOCTL_VERSION ioctl argument type.
150 * 145 *
151 * \sa drmGetVersion(). 146 * \sa drmGetVersion().
152 */ 147 */
153typedef struct drm_version { 148typedef struct drm_version {
154 int version_major; /**< Major version */ 149 int version_major; /**< Major version */
155 int version_minor; /**< Minor version */ 150 int version_minor; /**< Minor version */
156 int version_patchlevel;/**< Patch level */ 151 int version_patchlevel; /**< Patch level */
157 size_t name_len; /**< Length of name buffer */ 152 size_t name_len; /**< Length of name buffer */
158 char __user *name; /**< Name of driver */ 153 char __user *name; /**< Name of driver */
159 size_t date_len; /**< Length of date buffer */ 154 size_t date_len; /**< Length of date buffer */
160 char __user *date; /**< User-space buffer to hold date */ 155 char __user *date; /**< User-space buffer to hold date */
161 size_t desc_len; /**< Length of desc buffer */ 156 size_t desc_len; /**< Length of desc buffer */
162 char __user *desc; /**< User-space buffer to hold desc */ 157 char __user *desc; /**< User-space buffer to hold desc */
163} drm_version_t; 158} drm_version_t;
164 159
165
166/** 160/**
167 * DRM_IOCTL_GET_UNIQUE ioctl argument type. 161 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
168 * 162 *
@@ -170,21 +164,18 @@ typedef struct drm_version {
170 */ 164 */
171typedef struct drm_unique { 165typedef struct drm_unique {
172 size_t unique_len; /**< Length of unique */ 166 size_t unique_len; /**< Length of unique */
173 char __user *unique; /**< Unique name for driver instantiation */ 167 char __user *unique; /**< Unique name for driver instantiation */
174} drm_unique_t; 168} drm_unique_t;
175 169
176
177typedef struct drm_list { 170typedef struct drm_list {
178 int count; /**< Length of user-space structures */ 171 int count; /**< Length of user-space structures */
179 drm_version_t __user *version; 172 drm_version_t __user *version;
180} drm_list_t; 173} drm_list_t;
181 174
182
183typedef struct drm_block { 175typedef struct drm_block {
184 int unused; 176 int unused;
185} drm_block_t; 177} drm_block_t;
186 178
187
188/** 179/**
189 * DRM_IOCTL_CONTROL ioctl argument type. 180 * DRM_IOCTL_CONTROL ioctl argument type.
190 * 181 *
@@ -196,44 +187,40 @@ typedef struct drm_control {
196 DRM_RM_COMMAND, 187 DRM_RM_COMMAND,
197 DRM_INST_HANDLER, 188 DRM_INST_HANDLER,
198 DRM_UNINST_HANDLER 189 DRM_UNINST_HANDLER
199 } func; 190 } func;
200 int irq; 191 int irq;
201} drm_control_t; 192} drm_control_t;
202 193
203
204/** 194/**
205 * Type of memory to map. 195 * Type of memory to map.
206 */ 196 */
207typedef enum drm_map_type { 197typedef enum drm_map_type {
208 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ 198 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
209 _DRM_REGISTERS = 1, /**< no caching, no core dump */ 199 _DRM_REGISTERS = 1, /**< no caching, no core dump */
210 _DRM_SHM = 2, /**< shared, cached */ 200 _DRM_SHM = 2, /**< shared, cached */
211 _DRM_AGP = 3, /**< AGP/GART */ 201 _DRM_AGP = 3, /**< AGP/GART */
212 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ 202 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
213 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */ 203 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
214} drm_map_type_t; 204} drm_map_type_t;
215 205
216
217/** 206/**
218 * Memory mapping flags. 207 * Memory mapping flags.
219 */ 208 */
220typedef enum drm_map_flags { 209typedef enum drm_map_flags {
221 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ 210 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
222 _DRM_READ_ONLY = 0x02, 211 _DRM_READ_ONLY = 0x02,
223 _DRM_LOCKED = 0x04, /**< shared, cached, locked */ 212 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
224 _DRM_KERNEL = 0x08, /**< kernel requires access */ 213 _DRM_KERNEL = 0x08, /**< kernel requires access */
225 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ 214 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
226 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ 215 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
227 _DRM_REMOVABLE = 0x40 /**< Removable mapping */ 216 _DRM_REMOVABLE = 0x40 /**< Removable mapping */
228} drm_map_flags_t; 217} drm_map_flags_t;
229 218
230
231typedef struct drm_ctx_priv_map { 219typedef struct drm_ctx_priv_map {
232 unsigned int ctx_id; /**< Context requesting private mapping */ 220 unsigned int ctx_id; /**< Context requesting private mapping */
233 void *handle; /**< Handle of map */ 221 void *handle; /**< Handle of map */
234} drm_ctx_priv_map_t; 222} drm_ctx_priv_map_t;
235 223
236
237/** 224/**
238 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls 225 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
239 * argument type. 226 * argument type.
@@ -241,30 +228,28 @@ typedef struct drm_ctx_priv_map {
241 * \sa drmAddMap(). 228 * \sa drmAddMap().
242 */ 229 */
243typedef struct drm_map { 230typedef struct drm_map {
244 unsigned long offset; /**< Requested physical address (0 for SAREA)*/ 231 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
245 unsigned long size; /**< Requested physical size (bytes) */ 232 unsigned long size; /**< Requested physical size (bytes) */
246 drm_map_type_t type; /**< Type of memory to map */ 233 drm_map_type_t type; /**< Type of memory to map */
247 drm_map_flags_t flags; /**< Flags */ 234 drm_map_flags_t flags; /**< Flags */
248 void *handle; /**< User-space: "Handle" to pass to mmap() */ 235 void *handle; /**< User-space: "Handle" to pass to mmap() */
249 /**< Kernel-space: kernel-virtual address */ 236 /**< Kernel-space: kernel-virtual address */
250 int mtrr; /**< MTRR slot used */ 237 int mtrr; /**< MTRR slot used */
251 /* Private data */ 238 /* Private data */
252} drm_map_t; 239} drm_map_t;
253 240
254
255/** 241/**
256 * DRM_IOCTL_GET_CLIENT ioctl argument type. 242 * DRM_IOCTL_GET_CLIENT ioctl argument type.
257 */ 243 */
258typedef struct drm_client { 244typedef struct drm_client {
259 int idx; /**< Which client desired? */ 245 int idx; /**< Which client desired? */
260 int auth; /**< Is client authenticated? */ 246 int auth; /**< Is client authenticated? */
261 unsigned long pid; /**< Process ID */ 247 unsigned long pid; /**< Process ID */
262 unsigned long uid; /**< User ID */ 248 unsigned long uid; /**< User ID */
263 unsigned long magic; /**< Magic */ 249 unsigned long magic; /**< Magic */
264 unsigned long iocs; /**< Ioctl count */ 250 unsigned long iocs; /**< Ioctl count */
265} drm_client_t; 251} drm_client_t;
266 252
267
268typedef enum { 253typedef enum {
269 _DRM_STAT_LOCK, 254 _DRM_STAT_LOCK,
270 _DRM_STAT_OPENS, 255 _DRM_STAT_OPENS,
@@ -282,63 +267,58 @@ typedef enum {
282 _DRM_STAT_DMA, /**< DMA */ 267 _DRM_STAT_DMA, /**< DMA */
283 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ 268 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
284 _DRM_STAT_MISSED /**< Missed DMA opportunity */ 269 _DRM_STAT_MISSED /**< Missed DMA opportunity */
285 270 /* Add to the *END* of the list */
286 /* Add to the *END* of the list */
287} drm_stat_type_t; 271} drm_stat_type_t;
288 272
289
290/** 273/**
291 * DRM_IOCTL_GET_STATS ioctl argument type. 274 * DRM_IOCTL_GET_STATS ioctl argument type.
292 */ 275 */
293typedef struct drm_stats { 276typedef struct drm_stats {
294 unsigned long count; 277 unsigned long count;
295 struct { 278 struct {
296 unsigned long value; 279 unsigned long value;
297 drm_stat_type_t type; 280 drm_stat_type_t type;
298 } data[15]; 281 } data[15];
299} drm_stats_t; 282} drm_stats_t;
300 283
301
302/** 284/**
303 * Hardware locking flags. 285 * Hardware locking flags.
304 */ 286 */
305typedef enum drm_lock_flags { 287typedef enum drm_lock_flags {
306 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ 288 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
307 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ 289 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
308 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ 290 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
309 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ 291 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
310 /* These *HALT* flags aren't supported yet 292 /* These *HALT* flags aren't supported yet
311 -- they will be used to support the 293 -- they will be used to support the
312 full-screen DGA-like mode. */ 294 full-screen DGA-like mode. */
313 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ 295 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
314 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ 296 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
315} drm_lock_flags_t; 297} drm_lock_flags_t;
316 298
317
318/** 299/**
319 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. 300 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
320 * 301 *
321 * \sa drmGetLock() and drmUnlock(). 302 * \sa drmGetLock() and drmUnlock().
322 */ 303 */
323typedef struct drm_lock { 304typedef struct drm_lock {
324 int context; 305 int context;
325 drm_lock_flags_t flags; 306 drm_lock_flags_t flags;
326} drm_lock_t; 307} drm_lock_t;
327 308
328
329/** 309/**
330 * DMA flags 310 * DMA flags
331 * 311 *
332 * \warning 312 * \warning
333 * These values \e must match xf86drm.h. 313 * These values \e must match xf86drm.h.
334 * 314 *
335 * \sa drm_dma. 315 * \sa drm_dma.
336 */ 316 */
337typedef enum drm_dma_flags { 317typedef enum drm_dma_flags {
338 /* Flags for DMA buffer dispatch */ 318 /* Flags for DMA buffer dispatch */
339 _DRM_DMA_BLOCK = 0x01, /**< 319 _DRM_DMA_BLOCK = 0x01, /**<
340 * Block until buffer dispatched. 320 * Block until buffer dispatched.
341 * 321 *
342 * \note The buffer may not yet have 322 * \note The buffer may not yet have
343 * been processed by the hardware -- 323 * been processed by the hardware --
344 * getting a hardware lock with the 324 * getting a hardware lock with the
@@ -347,79 +327,73 @@ typedef enum drm_dma_flags {
347 * processed. 327 * processed.
348 */ 328 */
349 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ 329 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
350 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ 330 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
351 331
352 /* Flags for DMA buffer request */ 332 /* Flags for DMA buffer request */
353 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ 333 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
354 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ 334 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
355 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ 335 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
356} drm_dma_flags_t; 336} drm_dma_flags_t;
357 337
358
359/** 338/**
360 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. 339 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
361 * 340 *
362 * \sa drmAddBufs(). 341 * \sa drmAddBufs().
363 */ 342 */
364typedef struct drm_buf_desc { 343typedef struct drm_buf_desc {
365 int count; /**< Number of buffers of this size */ 344 int count; /**< Number of buffers of this size */
366 int size; /**< Size in bytes */ 345 int size; /**< Size in bytes */
367 int low_mark; /**< Low water mark */ 346 int low_mark; /**< Low water mark */
368 int high_mark; /**< High water mark */ 347 int high_mark; /**< High water mark */
369 enum { 348 enum {
370 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ 349 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
371 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ 350 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
372 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ 351 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
373 _DRM_FB_BUFFER = 0x08 /**< Buffer is in frame buffer */ 352 _DRM_FB_BUFFER = 0x08 /**< Buffer is in frame buffer */
374 } flags; 353 } flags;
375 unsigned long agp_start; /**< 354 unsigned long agp_start; /**<
376 * Start address of where the AGP buffers are 355 * Start address of where the AGP buffers are
377 * in the AGP aperture 356 * in the AGP aperture
378 */ 357 */
379} drm_buf_desc_t; 358} drm_buf_desc_t;
380 359
381
382/** 360/**
383 * DRM_IOCTL_INFO_BUFS ioctl argument type. 361 * DRM_IOCTL_INFO_BUFS ioctl argument type.
384 */ 362 */
385typedef struct drm_buf_info { 363typedef struct drm_buf_info {
386 int count; /**< Entries in list */ 364 int count; /**< Entries in list */
387 drm_buf_desc_t __user *list; 365 drm_buf_desc_t __user *list;
388} drm_buf_info_t; 366} drm_buf_info_t;
389 367
390
391/** 368/**
392 * DRM_IOCTL_FREE_BUFS ioctl argument type. 369 * DRM_IOCTL_FREE_BUFS ioctl argument type.
393 */ 370 */
394typedef struct drm_buf_free { 371typedef struct drm_buf_free {
395 int count; 372 int count;
396 int __user *list; 373 int __user *list;
397} drm_buf_free_t; 374} drm_buf_free_t;
398 375
399
400/** 376/**
401 * Buffer information 377 * Buffer information
402 * 378 *
403 * \sa drm_buf_map. 379 * \sa drm_buf_map.
404 */ 380 */
405typedef struct drm_buf_pub { 381typedef struct drm_buf_pub {
406 int idx; /**< Index into the master buffer list */ 382 int idx; /**< Index into the master buffer list */
407 int total; /**< Buffer size */ 383 int total; /**< Buffer size */
408 int used; /**< Amount of buffer in use (for DMA) */ 384 int used; /**< Amount of buffer in use (for DMA) */
409 void __user *address; /**< Address of buffer */ 385 void __user *address; /**< Address of buffer */
410} drm_buf_pub_t; 386} drm_buf_pub_t;
411 387
412
413/** 388/**
414 * DRM_IOCTL_MAP_BUFS ioctl argument type. 389 * DRM_IOCTL_MAP_BUFS ioctl argument type.
415 */ 390 */
416typedef struct drm_buf_map { 391typedef struct drm_buf_map {
417 int count; /**< Length of the buffer list */ 392 int count; /**< Length of the buffer list */
418 void __user *virtual; /**< Mmap'd area in user-virtual */ 393 void __user *virtual; /**< Mmap'd area in user-virtual */
419 drm_buf_pub_t __user *list; /**< Buffer information */ 394 drm_buf_pub_t __user *list; /**< Buffer information */
420} drm_buf_map_t; 395} drm_buf_map_t;
421 396
422
423/** 397/**
424 * DRM_IOCTL_DMA ioctl argument type. 398 * DRM_IOCTL_DMA ioctl argument type.
425 * 399 *
@@ -428,61 +402,55 @@ typedef struct drm_buf_map {
428 * \sa drmDMA(). 402 * \sa drmDMA().
429 */ 403 */
430typedef struct drm_dma { 404typedef struct drm_dma {
431 int context; /**< Context handle */ 405 int context; /**< Context handle */
432 int send_count; /**< Number of buffers to send */ 406 int send_count; /**< Number of buffers to send */
433 int __user *send_indices; /**< List of handles to buffers */ 407 int __user *send_indices; /**< List of handles to buffers */
434 int __user *send_sizes; /**< Lengths of data to send */ 408 int __user *send_sizes; /**< Lengths of data to send */
435 drm_dma_flags_t flags; /**< Flags */ 409 drm_dma_flags_t flags; /**< Flags */
436 int request_count; /**< Number of buffers requested */ 410 int request_count; /**< Number of buffers requested */
437 int request_size; /**< Desired size for buffers */ 411 int request_size; /**< Desired size for buffers */
438 int __user *request_indices; /**< Buffer information */ 412 int __user *request_indices; /**< Buffer information */
439 int __user *request_sizes; 413 int __user *request_sizes;
440 int granted_count; /**< Number of buffers granted */ 414 int granted_count; /**< Number of buffers granted */
441} drm_dma_t; 415} drm_dma_t;
442 416
443
444typedef enum { 417typedef enum {
445 _DRM_CONTEXT_PRESERVED = 0x01, 418 _DRM_CONTEXT_PRESERVED = 0x01,
446 _DRM_CONTEXT_2DONLY = 0x02 419 _DRM_CONTEXT_2DONLY = 0x02
447} drm_ctx_flags_t; 420} drm_ctx_flags_t;
448 421
449
450/** 422/**
451 * DRM_IOCTL_ADD_CTX ioctl argument type. 423 * DRM_IOCTL_ADD_CTX ioctl argument type.
452 * 424 *
453 * \sa drmCreateContext() and drmDestroyContext(). 425 * \sa drmCreateContext() and drmDestroyContext().
454 */ 426 */
455typedef struct drm_ctx { 427typedef struct drm_ctx {
456 drm_context_t handle; 428 drm_context_t handle;
457 drm_ctx_flags_t flags; 429 drm_ctx_flags_t flags;
458} drm_ctx_t; 430} drm_ctx_t;
459 431
460
461/** 432/**
462 * DRM_IOCTL_RES_CTX ioctl argument type. 433 * DRM_IOCTL_RES_CTX ioctl argument type.
463 */ 434 */
464typedef struct drm_ctx_res { 435typedef struct drm_ctx_res {
465 int count; 436 int count;
466 drm_ctx_t __user *contexts; 437 drm_ctx_t __user *contexts;
467} drm_ctx_res_t; 438} drm_ctx_res_t;
468 439
469
470/** 440/**
471 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. 441 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
472 */ 442 */
473typedef struct drm_draw { 443typedef struct drm_draw {
474 drm_drawable_t handle; 444 drm_drawable_t handle;
475} drm_draw_t; 445} drm_draw_t;
476 446
477
478/** 447/**
479 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. 448 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
480 */ 449 */
481typedef struct drm_auth { 450typedef struct drm_auth {
482 drm_magic_t magic; 451 drm_magic_t magic;
483} drm_auth_t; 452} drm_auth_t;
484 453
485
486/** 454/**
487 * DRM_IOCTL_IRQ_BUSID ioctl argument type. 455 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
488 * 456 *
@@ -495,24 +463,20 @@ typedef struct drm_irq_busid {
495 int funcnum; /**< function number */ 463 int funcnum; /**< function number */
496} drm_irq_busid_t; 464} drm_irq_busid_t;
497 465
498
499typedef enum { 466typedef enum {
500 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ 467 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
501 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ 468 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
502 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */ 469 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
503} drm_vblank_seq_type_t; 470} drm_vblank_seq_type_t;
504 471
505
506#define _DRM_VBLANK_FLAGS_MASK _DRM_VBLANK_SIGNAL 472#define _DRM_VBLANK_FLAGS_MASK _DRM_VBLANK_SIGNAL
507 473
508
509struct drm_wait_vblank_request { 474struct drm_wait_vblank_request {
510 drm_vblank_seq_type_t type; 475 drm_vblank_seq_type_t type;
511 unsigned int sequence; 476 unsigned int sequence;
512 unsigned long signal; 477 unsigned long signal;
513}; 478};
514 479
515
516struct drm_wait_vblank_reply { 480struct drm_wait_vblank_reply {
517 drm_vblank_seq_type_t type; 481 drm_vblank_seq_type_t type;
518 unsigned int sequence; 482 unsigned int sequence;
@@ -520,7 +484,6 @@ struct drm_wait_vblank_reply {
520 long tval_usec; 484 long tval_usec;
521}; 485};
522 486
523
524/** 487/**
525 * DRM_IOCTL_WAIT_VBLANK ioctl argument type. 488 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
526 * 489 *
@@ -531,7 +494,6 @@ typedef union drm_wait_vblank {
531 struct drm_wait_vblank_reply reply; 494 struct drm_wait_vblank_reply reply;
532} drm_wait_vblank_t; 495} drm_wait_vblank_t;
533 496
534
535/** 497/**
536 * DRM_IOCTL_AGP_ENABLE ioctl argument type. 498 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
537 * 499 *
@@ -541,7 +503,6 @@ typedef struct drm_agp_mode {
541 unsigned long mode; /**< AGP mode */ 503 unsigned long mode; /**< AGP mode */
542} drm_agp_mode_t; 504} drm_agp_mode_t;
543 505
544
545/** 506/**
546 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. 507 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
547 * 508 *
@@ -550,22 +511,20 @@ typedef struct drm_agp_mode {
550typedef struct drm_agp_buffer { 511typedef struct drm_agp_buffer {
551 unsigned long size; /**< In bytes -- will round to page boundary */ 512 unsigned long size; /**< In bytes -- will round to page boundary */
552 unsigned long handle; /**< Used for binding / unbinding */ 513 unsigned long handle; /**< Used for binding / unbinding */
553 unsigned long type; /**< Type of memory to allocate */ 514 unsigned long type; /**< Type of memory to allocate */
554 unsigned long physical; /**< Physical used by i810 */ 515 unsigned long physical; /**< Physical used by i810 */
555} drm_agp_buffer_t; 516} drm_agp_buffer_t;
556 517
557
558/** 518/**
559 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. 519 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
560 * 520 *
561 * \sa drmAgpBind() and drmAgpUnbind(). 521 * \sa drmAgpBind() and drmAgpUnbind().
562 */ 522 */
563typedef struct drm_agp_binding { 523typedef struct drm_agp_binding {
564 unsigned long handle; /**< From drm_agp_buffer */ 524 unsigned long handle; /**< From drm_agp_buffer */
565 unsigned long offset; /**< In bytes -- will round to page boundary */ 525 unsigned long offset; /**< In bytes -- will round to page boundary */
566} drm_agp_binding_t; 526} drm_agp_binding_t;
567 527
568
569/** 528/**
570 * DRM_IOCTL_AGP_INFO ioctl argument type. 529 * DRM_IOCTL_AGP_INFO ioctl argument type.
571 * 530 *
@@ -574,20 +533,19 @@ typedef struct drm_agp_binding {
574 * drmAgpVendorId() and drmAgpDeviceId(). 533 * drmAgpVendorId() and drmAgpDeviceId().
575 */ 534 */
576typedef struct drm_agp_info { 535typedef struct drm_agp_info {
577 int agp_version_major; 536 int agp_version_major;
578 int agp_version_minor; 537 int agp_version_minor;
579 unsigned long mode; 538 unsigned long mode;
580 unsigned long aperture_base; /* physical address */ 539 unsigned long aperture_base; /* physical address */
581 unsigned long aperture_size; /* bytes */ 540 unsigned long aperture_size; /* bytes */
582 unsigned long memory_allowed; /* bytes */ 541 unsigned long memory_allowed; /* bytes */
583 unsigned long memory_used; 542 unsigned long memory_used;
584 543
585 /* PCI information */ 544 /* PCI information */
586 unsigned short id_vendor; 545 unsigned short id_vendor;
587 unsigned short id_device; 546 unsigned short id_device;
588} drm_agp_info_t; 547} drm_agp_info_t;
589 548
590
591/** 549/**
592 * DRM_IOCTL_SG_ALLOC ioctl argument type. 550 * DRM_IOCTL_SG_ALLOC ioctl argument type.
593 */ 551 */
@@ -606,7 +564,6 @@ typedef struct drm_set_version {
606 int drm_dd_minor; 564 int drm_dd_minor;
607} drm_set_version_t; 565} drm_set_version_t;
608 566
609
610#define DRM_IOCTL_BASE 'd' 567#define DRM_IOCTL_BASE 'd'
611#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) 568#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
612#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) 569#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
diff --git a/drivers/char/drm/drmP.h b/drivers/char/drm/drmP.h
index 79221783a14c..255a21783d10 100644
--- a/drivers/char/drm/drmP.h
+++ b/drivers/char/drm/drmP.h
@@ -1,7 +1,7 @@
1/** 1/**
2 * \file drmP.h 2 * \file drmP.h
3 * Private header for Direct Rendering Manager 3 * Private header for Direct Rendering Manager
4 * 4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
6 * \author Gareth Hughes <gareth@valinux.com> 6 * \author Gareth Hughes <gareth@valinux.com>
7 */ 7 */
@@ -43,7 +43,7 @@
43 * before static inline funcs in wait.h. Doing this so we 43 * before static inline funcs in wait.h. Doing this so we
44 * can build the DRM (part of PI DRI). 4/21/2000 S + B */ 44 * can build the DRM (part of PI DRI). 4/21/2000 S + B */
45#include <asm/current.h> 45#include <asm/current.h>
46#endif /* __alpha__ */ 46#endif /* __alpha__ */
47#include <linux/config.h> 47#include <linux/config.h>
48#include <linux/module.h> 48#include <linux/module.h>
49#include <linux/kernel.h> 49#include <linux/kernel.h>
@@ -58,7 +58,7 @@
58#include <linux/mm.h> 58#include <linux/mm.h>
59#include <linux/cdev.h> 59#include <linux/cdev.h>
60#if defined(__alpha__) || defined(__powerpc__) 60#if defined(__alpha__) || defined(__powerpc__)
61#include <asm/pgtable.h> /* For pte_wrprotect */ 61#include <asm/pgtable.h> /* For pte_wrprotect */
62#endif 62#endif
63#include <asm/io.h> 63#include <asm/io.h>
64#include <asm/mman.h> 64#include <asm/mman.h>
@@ -138,16 +138,15 @@
138#define DRM_MEM_CTXLIST 21 138#define DRM_MEM_CTXLIST 21
139 139
140#define DRM_MAX_CTXBITMAP (PAGE_SIZE * 8) 140#define DRM_MAX_CTXBITMAP (PAGE_SIZE * 8)
141
142/*@}*/
143 141
142/*@}*/
144 143
145/***********************************************************************/ 144/***********************************************************************/
146/** \name Backward compatibility section */ 145/** \name Backward compatibility section */
147/*@{*/ 146/*@{*/
148 147
149#ifndef MODULE_LICENSE 148#ifndef MODULE_LICENSE
150#define MODULE_LICENSE(x) 149#define MODULE_LICENSE(x)
151#endif 150#endif
152 151
153#ifndef preempt_disable 152#ifndef preempt_disable
@@ -155,7 +154,7 @@
155#define preempt_enable() 154#define preempt_enable()
156#endif 155#endif
157 156
158#ifndef pte_offset_map 157#ifndef pte_offset_map
159#define pte_offset_map pte_offset 158#define pte_offset_map pte_offset
160#define pte_unmap(pte) 159#define pte_unmap(pte)
161#endif 160#endif
@@ -166,7 +165,6 @@
166 165
167/*@}*/ 166/*@}*/
168 167
169
170/***********************************************************************/ 168/***********************************************************************/
171/** \name Macros to make printk easier */ 169/** \name Macros to make printk easier */
172/*@{*/ 170/*@{*/
@@ -195,7 +193,7 @@
195 193
196/** 194/**
197 * Debug output. 195 * Debug output.
198 * 196 *
199 * \param fmt printf() like format string. 197 * \param fmt printf() like format string.
200 * \param arg arguments 198 * \param arg arguments
201 */ 199 */
@@ -223,7 +221,6 @@
223 221
224/*@}*/ 222/*@}*/
225 223
226
227/***********************************************************************/ 224/***********************************************************************/
228/** \name Internal types and structures */ 225/** \name Internal types and structures */
229/*@{*/ 226/*@{*/
@@ -275,7 +272,7 @@ do { \
275 if ( copy_to_user( name, value, len ) ) \ 272 if ( copy_to_user( name, value, len ) ) \
276 return -EFAULT; \ 273 return -EFAULT; \
277 } 274 }
278 275
279/** 276/**
280 * Ioctl function type. 277 * Ioctl function type.
281 * 278 *
@@ -284,25 +281,25 @@ do { \
284 * \param cmd command. 281 * \param cmd command.
285 * \param arg argument. 282 * \param arg argument.
286 */ 283 */
287typedef int drm_ioctl_t( struct inode *inode, struct file *filp, 284typedef int drm_ioctl_t(struct inode *inode, struct file *filp,
288 unsigned int cmd, unsigned long arg ); 285 unsigned int cmd, unsigned long arg);
289 286
290typedef int drm_ioctl_compat_t(struct file *filp, unsigned int cmd, 287typedef int drm_ioctl_compat_t(struct file *filp, unsigned int cmd,
291 unsigned long arg); 288 unsigned long arg);
292 289
293typedef struct drm_ioctl_desc { 290typedef struct drm_ioctl_desc {
294 drm_ioctl_t *func; 291 drm_ioctl_t *func;
295 int auth_needed; 292 int auth_needed;
296 int root_only; 293 int root_only;
297} drm_ioctl_desc_t; 294} drm_ioctl_desc_t;
298 295
299typedef struct drm_devstate { 296typedef struct drm_devstate {
300 pid_t owner; /**< X server pid holding x_lock */ 297 pid_t owner; /**< X server pid holding x_lock */
301} drm_devstate_t; 298} drm_devstate_t;
302 299
303typedef struct drm_magic_entry { 300typedef struct drm_magic_entry {
304 drm_magic_t magic; 301 drm_magic_t magic;
305 struct drm_file *priv; 302 struct drm_file *priv;
306 struct drm_magic_entry *next; 303 struct drm_magic_entry *next;
307} drm_magic_entry_t; 304} drm_magic_entry_t;
308 305
@@ -313,111 +310,110 @@ typedef struct drm_magic_head {
313 310
314typedef struct drm_vma_entry { 311typedef struct drm_vma_entry {
315 struct vm_area_struct *vma; 312 struct vm_area_struct *vma;
316 struct drm_vma_entry *next; 313 struct drm_vma_entry *next;
317 pid_t pid; 314 pid_t pid;
318} drm_vma_entry_t; 315} drm_vma_entry_t;
319 316
320/** 317/**
321 * DMA buffer. 318 * DMA buffer.
322 */ 319 */
323typedef struct drm_buf { 320typedef struct drm_buf {
324 int idx; /**< Index into master buflist */ 321 int idx; /**< Index into master buflist */
325 int total; /**< Buffer size */ 322 int total; /**< Buffer size */
326 int order; /**< log-base-2(total) */ 323 int order; /**< log-base-2(total) */
327 int used; /**< Amount of buffer in use (for DMA) */ 324 int used; /**< Amount of buffer in use (for DMA) */
328 unsigned long offset; /**< Byte offset (used internally) */ 325 unsigned long offset; /**< Byte offset (used internally) */
329 void *address; /**< Address of buffer */ 326 void *address; /**< Address of buffer */
330 unsigned long bus_address; /**< Bus address of buffer */ 327 unsigned long bus_address; /**< Bus address of buffer */
331 struct drm_buf *next; /**< Kernel-only: used for free list */ 328 struct drm_buf *next; /**< Kernel-only: used for free list */
332 __volatile__ int waiting; /**< On kernel DMA queue */ 329 __volatile__ int waiting; /**< On kernel DMA queue */
333 __volatile__ int pending; /**< On hardware DMA queue */ 330 __volatile__ int pending; /**< On hardware DMA queue */
334 wait_queue_head_t dma_wait; /**< Processes waiting */ 331 wait_queue_head_t dma_wait; /**< Processes waiting */
335 struct file *filp; /**< Pointer to holding file descr */ 332 struct file *filp; /**< Pointer to holding file descr */
336 int context; /**< Kernel queue for this buffer */ 333 int context; /**< Kernel queue for this buffer */
337 int while_locked;/**< Dispatch this buffer while locked */ 334 int while_locked; /**< Dispatch this buffer while locked */
338 enum { 335 enum {
339 DRM_LIST_NONE = 0, 336 DRM_LIST_NONE = 0,
340 DRM_LIST_FREE = 1, 337 DRM_LIST_FREE = 1,
341 DRM_LIST_WAIT = 2, 338 DRM_LIST_WAIT = 2,
342 DRM_LIST_PEND = 3, 339 DRM_LIST_PEND = 3,
343 DRM_LIST_PRIO = 4, 340 DRM_LIST_PRIO = 4,
344 DRM_LIST_RECLAIM = 5 341 DRM_LIST_RECLAIM = 5
345 } list; /**< Which list we're on */ 342 } list; /**< Which list we're on */
346 343
347 int dev_priv_size; /**< Size of buffer private storage */ 344 int dev_priv_size; /**< Size of buffer private storage */
348 void *dev_private; /**< Per-buffer private storage */ 345 void *dev_private; /**< Per-buffer private storage */
349} drm_buf_t; 346} drm_buf_t;
350 347
351
352/** bufs is one longer than it has to be */ 348/** bufs is one longer than it has to be */
353typedef struct drm_waitlist { 349typedef struct drm_waitlist {
354 int count; /**< Number of possible buffers */ 350 int count; /**< Number of possible buffers */
355 drm_buf_t **bufs; /**< List of pointers to buffers */ 351 drm_buf_t **bufs; /**< List of pointers to buffers */
356 drm_buf_t **rp; /**< Read pointer */ 352 drm_buf_t **rp; /**< Read pointer */
357 drm_buf_t **wp; /**< Write pointer */ 353 drm_buf_t **wp; /**< Write pointer */
358 drm_buf_t **end; /**< End pointer */ 354 drm_buf_t **end; /**< End pointer */
359 spinlock_t read_lock; 355 spinlock_t read_lock;
360 spinlock_t write_lock; 356 spinlock_t write_lock;
361} drm_waitlist_t; 357} drm_waitlist_t;
362 358
363typedef struct drm_freelist { 359typedef struct drm_freelist {
364 int initialized; /**< Freelist in use */ 360 int initialized; /**< Freelist in use */
365 atomic_t count; /**< Number of free buffers */ 361 atomic_t count; /**< Number of free buffers */
366 drm_buf_t *next; /**< End pointer */ 362 drm_buf_t *next; /**< End pointer */
367 363
368 wait_queue_head_t waiting; /**< Processes waiting on free bufs */ 364 wait_queue_head_t waiting; /**< Processes waiting on free bufs */
369 int low_mark; /**< Low water mark */ 365 int low_mark; /**< Low water mark */
370 int high_mark; /**< High water mark */ 366 int high_mark; /**< High water mark */
371 atomic_t wfh; /**< If waiting for high mark */ 367 atomic_t wfh; /**< If waiting for high mark */
372 spinlock_t lock; 368 spinlock_t lock;
373} drm_freelist_t; 369} drm_freelist_t;
374 370
375/** 371/**
376 * Buffer entry. There is one of this for each buffer size order. 372 * Buffer entry. There is one of this for each buffer size order.
377 */ 373 */
378typedef struct drm_buf_entry { 374typedef struct drm_buf_entry {
379 int buf_size; /**< size */ 375 int buf_size; /**< size */
380 int buf_count; /**< number of buffers */ 376 int buf_count; /**< number of buffers */
381 drm_buf_t *buflist; /**< buffer list */ 377 drm_buf_t *buflist; /**< buffer list */
382 int seg_count; 378 int seg_count;
383 int page_order; 379 int page_order;
384 unsigned long *seglist; 380 unsigned long *seglist;
385 381
386 drm_freelist_t freelist; 382 drm_freelist_t freelist;
387} drm_buf_entry_t; 383} drm_buf_entry_t;
388 384
389/** File private data */ 385/** File private data */
390typedef struct drm_file { 386typedef struct drm_file {
391 int authenticated; 387 int authenticated;
392 int minor; 388 int minor;
393 pid_t pid; 389 pid_t pid;
394 uid_t uid; 390 uid_t uid;
395 drm_magic_t magic; 391 drm_magic_t magic;
396 unsigned long ioctl_count; 392 unsigned long ioctl_count;
397 struct drm_file *next; 393 struct drm_file *next;
398 struct drm_file *prev; 394 struct drm_file *prev;
399 struct drm_head *head; 395 struct drm_head *head;
400 int remove_auth_on_close; 396 int remove_auth_on_close;
401 unsigned long lock_count; 397 unsigned long lock_count;
402 void *driver_priv; 398 void *driver_priv;
403} drm_file_t; 399} drm_file_t;
404 400
405/** Wait queue */ 401/** Wait queue */
406typedef struct drm_queue { 402typedef struct drm_queue {
407 atomic_t use_count; /**< Outstanding uses (+1) */ 403 atomic_t use_count; /**< Outstanding uses (+1) */
408 atomic_t finalization; /**< Finalization in progress */ 404 atomic_t finalization; /**< Finalization in progress */
409 atomic_t block_count; /**< Count of processes waiting */ 405 atomic_t block_count; /**< Count of processes waiting */
410 atomic_t block_read; /**< Queue blocked for reads */ 406 atomic_t block_read; /**< Queue blocked for reads */
411 wait_queue_head_t read_queue; /**< Processes waiting on block_read */ 407 wait_queue_head_t read_queue; /**< Processes waiting on block_read */
412 atomic_t block_write; /**< Queue blocked for writes */ 408 atomic_t block_write; /**< Queue blocked for writes */
413 wait_queue_head_t write_queue; /**< Processes waiting on block_write */ 409 wait_queue_head_t write_queue; /**< Processes waiting on block_write */
414#if 1 410#if 1
415 atomic_t total_queued; /**< Total queued statistic */ 411 atomic_t total_queued; /**< Total queued statistic */
416 atomic_t total_flushed;/**< Total flushes statistic */ 412 atomic_t total_flushed; /**< Total flushes statistic */
417 atomic_t total_locks; /**< Total locks statistics */ 413 atomic_t total_locks; /**< Total locks statistics */
418#endif 414#endif
419 drm_ctx_flags_t flags; /**< Context preserving and 2D-only */ 415 drm_ctx_flags_t flags; /**< Context preserving and 2D-only */
420 drm_waitlist_t waitlist; /**< Pending buffers */ 416 drm_waitlist_t waitlist; /**< Pending buffers */
421 wait_queue_head_t flush_queue; /**< Processes waiting until flush */ 417 wait_queue_head_t flush_queue; /**< Processes waiting until flush */
422} drm_queue_t; 418} drm_queue_t;
423 419
@@ -425,10 +421,10 @@ typedef struct drm_queue {
425 * Lock data. 421 * Lock data.
426 */ 422 */
427typedef struct drm_lock_data { 423typedef struct drm_lock_data {
428 drm_hw_lock_t *hw_lock; /**< Hardware lock */ 424 drm_hw_lock_t *hw_lock; /**< Hardware lock */
429 struct file *filp; /**< File descr of lock holder (0=kernel) */ 425 struct file *filp; /**< File descr of lock holder (0=kernel) */
430 wait_queue_head_t lock_queue; /**< Queue of blocked processes */ 426 wait_queue_head_t lock_queue; /**< Queue of blocked processes */
431 unsigned long lock_time; /**< Time of last lock in jiffies */ 427 unsigned long lock_time; /**< Time of last lock in jiffies */
432} drm_lock_data_t; 428} drm_lock_data_t;
433 429
434/** 430/**
@@ -436,29 +432,29 @@ typedef struct drm_lock_data {
436 */ 432 */
437typedef struct drm_device_dma { 433typedef struct drm_device_dma {
438 434
439 drm_buf_entry_t bufs[DRM_MAX_ORDER+1]; /**< buffers, grouped by their size order */ 435 drm_buf_entry_t bufs[DRM_MAX_ORDER + 1]; /**< buffers, grouped by their size order */
440 int buf_count; /**< total number of buffers */ 436 int buf_count; /**< total number of buffers */
441 drm_buf_t **buflist; /**< Vector of pointers into drm_device_dma::bufs */ 437 drm_buf_t **buflist; /**< Vector of pointers into drm_device_dma::bufs */
442 int seg_count; 438 int seg_count;
443 int page_count; /**< number of pages */ 439 int page_count; /**< number of pages */
444 unsigned long *pagelist; /**< page list */ 440 unsigned long *pagelist; /**< page list */
445 unsigned long byte_count; 441 unsigned long byte_count;
446 enum { 442 enum {
447 _DRM_DMA_USE_AGP = 0x01, 443 _DRM_DMA_USE_AGP = 0x01,
448 _DRM_DMA_USE_SG = 0x02, 444 _DRM_DMA_USE_SG = 0x02,
449 _DRM_DMA_USE_FB = 0x04 445 _DRM_DMA_USE_FB = 0x04
450 } flags; 446 } flags;
451 447
452} drm_device_dma_t; 448} drm_device_dma_t;
453 449
454/** 450/**
455 * AGP memory entry. Stored as a doubly linked list. 451 * AGP memory entry. Stored as a doubly linked list.
456 */ 452 */
457typedef struct drm_agp_mem { 453typedef struct drm_agp_mem {
458 unsigned long handle; /**< handle */ 454 unsigned long handle; /**< handle */
459 DRM_AGP_MEM *memory; 455 DRM_AGP_MEM *memory;
460 unsigned long bound; /**< address */ 456 unsigned long bound; /**< address */
461 int pages; 457 int pages;
462 struct drm_agp_mem *prev; /**< previous entry */ 458 struct drm_agp_mem *prev; /**< previous entry */
463 struct drm_agp_mem *next; /**< next entry */ 459 struct drm_agp_mem *next; /**< next entry */
464} drm_agp_mem_t; 460} drm_agp_mem_t;
@@ -469,31 +465,31 @@ typedef struct drm_agp_mem {
469 * \sa drm_agp_init() and drm_device::agp. 465 * \sa drm_agp_init() and drm_device::agp.
470 */ 466 */
471typedef struct drm_agp_head { 467typedef struct drm_agp_head {
472 DRM_AGP_KERN agp_info; /**< AGP device information */ 468 DRM_AGP_KERN agp_info; /**< AGP device information */
473 drm_agp_mem_t *memory; /**< memory entries */ 469 drm_agp_mem_t *memory; /**< memory entries */
474 unsigned long mode; /**< AGP mode */ 470 unsigned long mode; /**< AGP mode */
475 struct agp_bridge_data *bridge; 471 struct agp_bridge_data *bridge;
476 int enabled; /**< whether the AGP bus as been enabled */ 472 int enabled; /**< whether the AGP bus as been enabled */
477 int acquired; /**< whether the AGP device has been acquired */ 473 int acquired; /**< whether the AGP device has been acquired */
478 unsigned long base; 474 unsigned long base;
479 int agp_mtrr; 475 int agp_mtrr;
480 int cant_use_aperture; 476 int cant_use_aperture;
481 unsigned long page_mask; 477 unsigned long page_mask;
482} drm_agp_head_t; 478} drm_agp_head_t;
483 479
484/** 480/**
485 * Scatter-gather memory. 481 * Scatter-gather memory.
486 */ 482 */
487typedef struct drm_sg_mem { 483typedef struct drm_sg_mem {
488 unsigned long handle; 484 unsigned long handle;
489 void *virtual; 485 void *virtual;
490 int pages; 486 int pages;
491 struct page **pagelist; 487 struct page **pagelist;
492 dma_addr_t *busaddr; 488 dma_addr_t *busaddr;
493} drm_sg_mem_t; 489} drm_sg_mem_t;
494 490
495typedef struct drm_sigdata { 491typedef struct drm_sigdata {
496 int context; 492 int context;
497 drm_hw_lock_t *lock; 493 drm_hw_lock_t *lock;
498} drm_sigdata_t; 494} drm_sigdata_t;
499 495
@@ -507,8 +503,8 @@ typedef struct drm_dma_handle {
507 * Mappings list 503 * Mappings list
508 */ 504 */
509typedef struct drm_map_list { 505typedef struct drm_map_list {
510 struct list_head head; /**< list head */ 506 struct list_head head; /**< list head */
511 drm_map_t *map; /**< mapping */ 507 drm_map_t *map; /**< mapping */
512 unsigned int user_token; 508 unsigned int user_token;
513} drm_map_list_t; 509} drm_map_list_t;
514 510
@@ -518,20 +514,18 @@ typedef drm_map_t drm_local_map_t;
518 * Context handle list 514 * Context handle list
519 */ 515 */
520typedef struct drm_ctx_list { 516typedef struct drm_ctx_list {
521 struct list_head head; /**< list head */ 517 struct list_head head; /**< list head */
522 drm_context_t handle; /**< context handle */ 518 drm_context_t handle; /**< context handle */
523 drm_file_t *tag; /**< associated fd private data */ 519 drm_file_t *tag; /**< associated fd private data */
524} drm_ctx_list_t; 520} drm_ctx_list_t;
525 521
526
527typedef struct drm_vbl_sig { 522typedef struct drm_vbl_sig {
528 struct list_head head; 523 struct list_head head;
529 unsigned int sequence; 524 unsigned int sequence;
530 struct siginfo info; 525 struct siginfo info;
531 struct task_struct *task; 526 struct task_struct *task;
532} drm_vbl_sig_t; 527} drm_vbl_sig_t;
533 528
534
535/* location of GART table */ 529/* location of GART table */
536#define DRM_ATI_GART_MAIN 1 530#define DRM_ATI_GART_MAIN 1
537#define DRM_ATI_GART_FB 2 531#define DRM_ATI_GART_FB 2
@@ -551,24 +545,26 @@ typedef struct ati_pcigart_info {
551struct drm_device; 545struct drm_device;
552 546
553struct drm_driver { 547struct drm_driver {
554 int (*preinit)(struct drm_device *, unsigned long flags); 548 int (*preinit) (struct drm_device *, unsigned long flags);
555 void (*prerelease)(struct drm_device *, struct file *filp); 549 void (*prerelease) (struct drm_device *, struct file * filp);
556 void (*pretakedown)(struct drm_device *); 550 void (*pretakedown) (struct drm_device *);
557 int (*postcleanup)(struct drm_device *); 551 int (*postcleanup) (struct drm_device *);
558 int (*presetup)(struct drm_device *); 552 int (*presetup) (struct drm_device *);
559 int (*postsetup)(struct drm_device *); 553 int (*postsetup) (struct drm_device *);
560 int (*dma_ioctl)( DRM_IOCTL_ARGS ); 554 int (*dma_ioctl) (DRM_IOCTL_ARGS);
561 int (*open_helper)(struct drm_device *, drm_file_t *); 555 int (*open_helper) (struct drm_device *, drm_file_t *);
562 void (*free_filp_priv)(struct drm_device *, drm_file_t *); 556 void (*free_filp_priv) (struct drm_device *, drm_file_t *);
563 void (*release)(struct drm_device *, struct file *filp); 557 void (*release) (struct drm_device *, struct file * filp);
564 void (*dma_ready)(struct drm_device *); 558 void (*dma_ready) (struct drm_device *);
565 int (*dma_quiescent)(struct drm_device *); 559 int (*dma_quiescent) (struct drm_device *);
566 int (*context_ctor)(struct drm_device *dev, int context); 560 int (*context_ctor) (struct drm_device * dev, int context);
567 int (*context_dtor)(struct drm_device *dev, int context); 561 int (*context_dtor) (struct drm_device * dev, int context);
568 int (*kernel_context_switch)(struct drm_device *dev, int old, int new); 562 int (*kernel_context_switch) (struct drm_device * dev, int old,
569 void (*kernel_context_switch_unlock)(struct drm_device *dev, drm_lock_t *lock); 563 int new);
570 int (*vblank_wait)(struct drm_device *dev, unsigned int *sequence); 564 void (*kernel_context_switch_unlock) (struct drm_device * dev,
571 565 drm_lock_t * lock);
566 int (*vblank_wait) (struct drm_device * dev, unsigned int *sequence);
567
572 /** 568 /**
573 * Called by \c drm_device_is_agp. Typically used to determine if a 569 * Called by \c drm_device_is_agp. Typically used to determine if a
574 * card is really attached to AGP or not. 570 * card is really attached to AGP or not.
@@ -583,17 +579,17 @@ struct drm_driver {
583 int (*device_is_agp) (struct drm_device * dev); 579 int (*device_is_agp) (struct drm_device * dev);
584 580
585 /* these have to be filled in */ 581 /* these have to be filled in */
586 582
587 int (*postinit)(struct drm_device *, unsigned long flags); 583 int (*postinit) (struct drm_device *, unsigned long flags);
588 irqreturn_t (*irq_handler)( DRM_IRQ_ARGS ); 584 irqreturn_t(*irq_handler) (DRM_IRQ_ARGS);
589 void (*irq_preinstall)(struct drm_device *dev); 585 void (*irq_preinstall) (struct drm_device * dev);
590 void (*irq_postinstall)(struct drm_device *dev); 586 void (*irq_postinstall) (struct drm_device * dev);
591 void (*irq_uninstall)(struct drm_device *dev); 587 void (*irq_uninstall) (struct drm_device * dev);
592 void (*reclaim_buffers)(struct drm_device *dev, struct file *filp); 588 void (*reclaim_buffers) (struct drm_device * dev, struct file * filp);
593 unsigned long (*get_map_ofs)(drm_map_t *map); 589 unsigned long (*get_map_ofs) (drm_map_t * map);
594 unsigned long (*get_reg_ofs)(struct drm_device *dev); 590 unsigned long (*get_reg_ofs) (struct drm_device * dev);
595 void (*set_version)(struct drm_device *dev, drm_set_version_t *sv); 591 void (*set_version) (struct drm_device * dev, drm_set_version_t * sv);
596 int (*version)(drm_version_t *version); 592 int (*version) (drm_version_t * version);
597 u32 driver_features; 593 u32 driver_features;
598 int dev_priv_size; 594 int dev_priv_size;
599 drm_ioctl_desc_t *ioctls; 595 drm_ioctl_desc_t *ioctls;
@@ -620,128 +616,129 @@ typedef struct drm_head {
620 * may contain multiple heads. 616 * may contain multiple heads.
621 */ 617 */
622typedef struct drm_device { 618typedef struct drm_device {
623 char *unique; /**< Unique identifier: e.g., busid */ 619 char *unique; /**< Unique identifier: e.g., busid */
624 int unique_len; /**< Length of unique field */ 620 int unique_len; /**< Length of unique field */
625 char *devname; /**< For /proc/interrupts */ 621 char *devname; /**< For /proc/interrupts */
626 int if_version; /**< Highest interface version set */ 622 int if_version; /**< Highest interface version set */
627 623
628 int blocked; /**< Blocked due to VC switch? */ 624 int blocked; /**< Blocked due to VC switch? */
629 625
630 /** \name Locks */ 626 /** \name Locks */
631 /*@{*/ 627 /*@{ */
632 spinlock_t count_lock; /**< For inuse, drm_device::open_count, drm_device::buf_use */ 628 spinlock_t count_lock; /**< For inuse, drm_device::open_count, drm_device::buf_use */
633 struct semaphore struct_sem; /**< For others */ 629 struct semaphore struct_sem; /**< For others */
634 /*@}*/ 630 /*@} */
635 631
636 /** \name Usage Counters */ 632 /** \name Usage Counters */
637 /*@{*/ 633 /*@{ */
638 int open_count; /**< Outstanding files open */ 634 int open_count; /**< Outstanding files open */
639 atomic_t ioctl_count; /**< Outstanding IOCTLs pending */ 635 atomic_t ioctl_count; /**< Outstanding IOCTLs pending */
640 atomic_t vma_count; /**< Outstanding vma areas open */ 636 atomic_t vma_count; /**< Outstanding vma areas open */
641 int buf_use; /**< Buffers in use -- cannot alloc */ 637 int buf_use; /**< Buffers in use -- cannot alloc */
642 atomic_t buf_alloc; /**< Buffer allocation in progress */ 638 atomic_t buf_alloc; /**< Buffer allocation in progress */
643 /*@}*/ 639 /*@} */
644 640
645 /** \name Performance counters */ 641 /** \name Performance counters */
646 /*@{*/ 642 /*@{ */
647 unsigned long counters; 643 unsigned long counters;
648 drm_stat_type_t types[15]; 644 drm_stat_type_t types[15];
649 atomic_t counts[15]; 645 atomic_t counts[15];
650 /*@}*/ 646 /*@} */
651 647
652 /** \name Authentication */ 648 /** \name Authentication */
653 /*@{*/ 649 /*@{ */
654 drm_file_t *file_first; /**< file list head */ 650 drm_file_t *file_first; /**< file list head */
655 drm_file_t *file_last; /**< file list tail */ 651 drm_file_t *file_last; /**< file list tail */
656 drm_magic_head_t magiclist[DRM_HASH_SIZE]; /**< magic hash table */ 652 drm_magic_head_t magiclist[DRM_HASH_SIZE]; /**< magic hash table */
657 /*@}*/ 653 /*@} */
658 654
659 /** \name Memory management */ 655 /** \name Memory management */
660 /*@{*/ 656 /*@{ */
661 drm_map_list_t *maplist; /**< Linked list of regions */ 657 drm_map_list_t *maplist; /**< Linked list of regions */
662 int map_count; /**< Number of mappable regions */ 658 int map_count; /**< Number of mappable regions */
663 659
664 /** \name Context handle management */ 660 /** \name Context handle management */
665 /*@{*/ 661 /*@{ */
666 drm_ctx_list_t *ctxlist; /**< Linked list of context handles */ 662 drm_ctx_list_t *ctxlist; /**< Linked list of context handles */
667 int ctx_count; /**< Number of context handles */ 663 int ctx_count; /**< Number of context handles */
668 struct semaphore ctxlist_sem; /**< For ctxlist */ 664 struct semaphore ctxlist_sem; /**< For ctxlist */
669 665
670 drm_map_t **context_sareas; /**< per-context SAREA's */ 666 drm_map_t **context_sareas; /**< per-context SAREA's */
671 int max_context; 667 int max_context;
672 668
673 drm_vma_entry_t *vmalist; /**< List of vmas (for debugging) */ 669 drm_vma_entry_t *vmalist; /**< List of vmas (for debugging) */
674 drm_lock_data_t lock; /**< Information on hardware lock */ 670 drm_lock_data_t lock; /**< Information on hardware lock */
675 /*@}*/ 671 /*@} */
676 672
677 /** \name DMA queues (contexts) */ 673 /** \name DMA queues (contexts) */
678 /*@{*/ 674 /*@{ */
679 int queue_count; /**< Number of active DMA queues */ 675 int queue_count; /**< Number of active DMA queues */
680 int queue_reserved; /**< Number of reserved DMA queues */ 676 int queue_reserved; /**< Number of reserved DMA queues */
681 int queue_slots; /**< Actual length of queuelist */ 677 int queue_slots; /**< Actual length of queuelist */
682 drm_queue_t **queuelist; /**< Vector of pointers to DMA queues */ 678 drm_queue_t **queuelist; /**< Vector of pointers to DMA queues */
683 drm_device_dma_t *dma; /**< Optional pointer for DMA support */ 679 drm_device_dma_t *dma; /**< Optional pointer for DMA support */
684 /*@}*/ 680 /*@} */
685 681
686 /** \name Context support */ 682 /** \name Context support */
687 /*@{*/ 683 /*@{ */
688 int irq; /**< Interrupt used by board */ 684 int irq; /**< Interrupt used by board */
689 int irq_enabled; /**< True if irq handler is enabled */ 685 int irq_enabled; /**< True if irq handler is enabled */
690 __volatile__ long context_flag; /**< Context swapping flag */ 686 __volatile__ long context_flag; /**< Context swapping flag */
691 __volatile__ long interrupt_flag; /**< Interruption handler flag */ 687 __volatile__ long interrupt_flag; /**< Interruption handler flag */
692 __volatile__ long dma_flag; /**< DMA dispatch flag */ 688 __volatile__ long dma_flag; /**< DMA dispatch flag */
693 struct timer_list timer; /**< Timer for delaying ctx switch */ 689 struct timer_list timer; /**< Timer for delaying ctx switch */
694 wait_queue_head_t context_wait; /**< Processes waiting on ctx switch */ 690 wait_queue_head_t context_wait; /**< Processes waiting on ctx switch */
695 int last_checked; /**< Last context checked for DMA */ 691 int last_checked; /**< Last context checked for DMA */
696 int last_context; /**< Last current context */ 692 int last_context; /**< Last current context */
697 unsigned long last_switch; /**< jiffies at last context switch */ 693 unsigned long last_switch; /**< jiffies at last context switch */
698 /*@}*/ 694 /*@} */
699 695
700 struct work_struct work; 696 struct work_struct work;
701 /** \name VBLANK IRQ support */ 697 /** \name VBLANK IRQ support */
702 /*@{*/ 698 /*@{ */
703 699
704 wait_queue_head_t vbl_queue; /**< VBLANK wait queue */ 700 wait_queue_head_t vbl_queue; /**< VBLANK wait queue */
705 atomic_t vbl_received; 701 atomic_t vbl_received;
706 spinlock_t vbl_lock; 702 spinlock_t vbl_lock;
707 drm_vbl_sig_t vbl_sigs; /**< signal list to send on VBLANK */ 703 drm_vbl_sig_t vbl_sigs; /**< signal list to send on VBLANK */
708 unsigned int vbl_pending; 704 unsigned int vbl_pending;
709 705
710 /*@}*/ 706 /*@} */
711 cycles_t ctx_start; 707 cycles_t ctx_start;
712 cycles_t lck_start; 708 cycles_t lck_start;
713 709
714 char buf[DRM_BSZ]; /**< Output buffer */ 710 char buf[DRM_BSZ]; /**< Output buffer */
715 char *buf_rp; /**< Read pointer */ 711 char *buf_rp; /**< Read pointer */
716 char *buf_wp; /**< Write pointer */ 712 char *buf_wp; /**< Write pointer */
717 char *buf_end; /**< End pointer */ 713 char *buf_end; /**< End pointer */
718 struct fasync_struct *buf_async;/**< Processes waiting for SIGIO */ 714 struct fasync_struct *buf_async;/**< Processes waiting for SIGIO */
719 wait_queue_head_t buf_readers; /**< Processes waiting to read */ 715 wait_queue_head_t buf_readers; /**< Processes waiting to read */
720 wait_queue_head_t buf_writers; /**< Processes waiting to ctx switch */ 716 wait_queue_head_t buf_writers; /**< Processes waiting to ctx switch */
721 717
722 drm_agp_head_t *agp; /**< AGP data */ 718 drm_agp_head_t *agp; /**< AGP data */
723 719
724 struct pci_dev *pdev; /**< PCI device structure */ 720 struct pci_dev *pdev; /**< PCI device structure */
725 int pci_domain; /**< PCI bus domain number */ 721 int pci_domain; /**< PCI bus domain number */
726 int pci_bus; /**< PCI bus number */ 722 int pci_bus; /**< PCI bus number */
727 int pci_slot; /**< PCI slot number */ 723 int pci_slot; /**< PCI slot number */
728 int pci_func; /**< PCI function number */ 724 int pci_func; /**< PCI function number */
729#ifdef __alpha__ 725#ifdef __alpha__
730 struct pci_controller *hose; 726 struct pci_controller *hose;
731#endif 727#endif
732 drm_sg_mem_t *sg; /**< Scatter gather memory */ 728 drm_sg_mem_t *sg; /**< Scatter gather memory */
733 unsigned long *ctx_bitmap; /**< context bitmap */ 729 unsigned long *ctx_bitmap; /**< context bitmap */
734 void *dev_private; /**< device private data */ 730 void *dev_private; /**< device private data */
735 drm_sigdata_t sigdata; /**< For block_all_signals */ 731 drm_sigdata_t sigdata; /**< For block_all_signals */
736 sigset_t sigmask; 732 sigset_t sigmask;
737 733
738 struct drm_driver *driver; 734 struct drm_driver *driver;
739 drm_local_map_t *agp_buffer_map; 735 drm_local_map_t *agp_buffer_map;
740 unsigned int agp_buffer_token; 736 unsigned int agp_buffer_token;
741 drm_head_t primary; /**< primary screen head */ 737 drm_head_t primary; /**< primary screen head */
742} drm_device_t; 738} drm_device_t;
743 739
744static __inline__ int drm_core_check_feature(struct drm_device *dev, int feature) 740static __inline__ int drm_core_check_feature(struct drm_device *dev,
741 int feature)
745{ 742{
746 return ((dev->driver->driver_features & feature) ? 1 : 0); 743 return ((dev->driver->driver_features & feature) ? 1 : 0);
747} 744}
@@ -749,7 +746,7 @@ static __inline__ int drm_core_check_feature(struct drm_device *dev, int feature
749#if __OS_HAS_AGP 746#if __OS_HAS_AGP
750static inline int drm_core_has_AGP(struct drm_device *dev) 747static inline int drm_core_has_AGP(struct drm_device *dev)
751{ 748{
752 return drm_core_check_feature(dev, DRIVER_USE_AGP); 749 return drm_core_check_feature(dev, DRIVER_USE_AGP);
753} 750}
754#else 751#else
755#define drm_core_has_AGP(dev) (0) 752#define drm_core_has_AGP(dev) (0)
@@ -758,7 +755,7 @@ static inline int drm_core_has_AGP(struct drm_device *dev)
758#if __OS_HAS_MTRR 755#if __OS_HAS_MTRR
759static inline int drm_core_has_MTRR(struct drm_device *dev) 756static inline int drm_core_has_MTRR(struct drm_device *dev)
760{ 757{
761 return drm_core_check_feature(dev, DRIVER_USE_MTRR); 758 return drm_core_check_feature(dev, DRIVER_USE_MTRR);
762} 759}
763#else 760#else
764#define drm_core_has_MTRR(dev) (0) 761#define drm_core_has_MTRR(dev) (0)
@@ -769,230 +766,229 @@ static inline int drm_core_has_MTRR(struct drm_device *dev)
769/*@{*/ 766/*@{*/
770 767
771 /* Misc. support (drm_init.h) */ 768 /* Misc. support (drm_init.h) */
772extern int drm_flags; 769extern int drm_flags;
773extern void drm_parse_options( char *s ); 770extern void drm_parse_options(char *s);
774extern int drm_cpu_valid( void ); 771extern int drm_cpu_valid(void);
775 772
776 /* Driver support (drm_drv.h) */ 773 /* Driver support (drm_drv.h) */
777extern int drm_init(struct drm_driver *driver); 774extern int drm_init(struct drm_driver *driver);
778extern void drm_exit(struct drm_driver *driver); 775extern void drm_exit(struct drm_driver *driver);
779extern int drm_ioctl(struct inode *inode, struct file *filp, 776extern int drm_ioctl(struct inode *inode, struct file *filp,
780 unsigned int cmd, unsigned long arg); 777 unsigned int cmd, unsigned long arg);
781extern long drm_compat_ioctl(struct file *filp, 778extern long drm_compat_ioctl(struct file *filp,
782 unsigned int cmd, unsigned long arg); 779 unsigned int cmd, unsigned long arg);
783extern int drm_takedown(drm_device_t * dev); 780extern int drm_takedown(drm_device_t * dev);
784 781
785 /* Device support (drm_fops.h) */ 782 /* Device support (drm_fops.h) */
786extern int drm_open(struct inode *inode, struct file *filp); 783extern int drm_open(struct inode *inode, struct file *filp);
787extern int drm_stub_open(struct inode *inode, struct file *filp); 784extern int drm_stub_open(struct inode *inode, struct file *filp);
788extern int drm_flush(struct file *filp); 785extern int drm_flush(struct file *filp);
789extern int drm_fasync(int fd, struct file *filp, int on); 786extern int drm_fasync(int fd, struct file *filp, int on);
790extern int drm_release(struct inode *inode, struct file *filp); 787extern int drm_release(struct inode *inode, struct file *filp);
791 788
792 /* Mapping support (drm_vm.h) */ 789 /* Mapping support (drm_vm.h) */
793extern int drm_mmap(struct file *filp, struct vm_area_struct *vma); 790extern int drm_mmap(struct file *filp, struct vm_area_struct *vma);
794extern unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait); 791extern unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait);
795 792
796 /* Memory management support (drm_memory.h) */ 793 /* Memory management support (drm_memory.h) */
797#include "drm_memory.h" 794#include "drm_memory.h"
798extern void drm_mem_init(void); 795extern void drm_mem_init(void);
799extern int drm_mem_info(char *buf, char **start, off_t offset, 796extern int drm_mem_info(char *buf, char **start, off_t offset,
800 int request, int *eof, void *data); 797 int request, int *eof, void *data);
801extern void *drm_realloc(void *oldpt, size_t oldsize, size_t size, 798extern void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area);
802 int area);
803extern unsigned long drm_alloc_pages(int order, int area); 799extern unsigned long drm_alloc_pages(int order, int area);
804extern void drm_free_pages(unsigned long address, int order, 800extern void drm_free_pages(unsigned long address, int order, int area);
805 int area); 801extern void *drm_ioremap(unsigned long offset, unsigned long size,
806extern void *drm_ioremap(unsigned long offset, unsigned long size, drm_device_t *dev); 802 drm_device_t * dev);
807extern void *drm_ioremap_nocache(unsigned long offset, unsigned long size, 803extern void *drm_ioremap_nocache(unsigned long offset, unsigned long size,
808 drm_device_t *dev); 804 drm_device_t * dev);
809extern void drm_ioremapfree(void *pt, unsigned long size, drm_device_t *dev); 805extern void drm_ioremapfree(void *pt, unsigned long size, drm_device_t * dev);
810 806
811extern DRM_AGP_MEM *drm_alloc_agp(drm_device_t *dev, int pages, u32 type); 807extern DRM_AGP_MEM *drm_alloc_agp(drm_device_t * dev, int pages, u32 type);
812extern int drm_free_agp(DRM_AGP_MEM *handle, int pages); 808extern int drm_free_agp(DRM_AGP_MEM * handle, int pages);
813extern int drm_bind_agp(DRM_AGP_MEM *handle, unsigned int start); 809extern int drm_bind_agp(DRM_AGP_MEM * handle, unsigned int start);
814extern int drm_unbind_agp(DRM_AGP_MEM *handle); 810extern int drm_unbind_agp(DRM_AGP_MEM * handle);
815 811
816 /* Misc. IOCTL support (drm_ioctl.h) */ 812 /* Misc. IOCTL support (drm_ioctl.h) */
817extern int drm_irq_by_busid(struct inode *inode, struct file *filp, 813extern int drm_irq_by_busid(struct inode *inode, struct file *filp,
818 unsigned int cmd, unsigned long arg); 814 unsigned int cmd, unsigned long arg);
819extern int drm_getunique(struct inode *inode, struct file *filp, 815extern int drm_getunique(struct inode *inode, struct file *filp,
820 unsigned int cmd, unsigned long arg); 816 unsigned int cmd, unsigned long arg);
821extern int drm_setunique(struct inode *inode, struct file *filp, 817extern int drm_setunique(struct inode *inode, struct file *filp,
822 unsigned int cmd, unsigned long arg); 818 unsigned int cmd, unsigned long arg);
823extern int drm_getmap(struct inode *inode, struct file *filp, 819extern int drm_getmap(struct inode *inode, struct file *filp,
824 unsigned int cmd, unsigned long arg); 820 unsigned int cmd, unsigned long arg);
825extern int drm_getclient(struct inode *inode, struct file *filp, 821extern int drm_getclient(struct inode *inode, struct file *filp,
826 unsigned int cmd, unsigned long arg); 822 unsigned int cmd, unsigned long arg);
827extern int drm_getstats(struct inode *inode, struct file *filp, 823extern int drm_getstats(struct inode *inode, struct file *filp,
828 unsigned int cmd, unsigned long arg); 824 unsigned int cmd, unsigned long arg);
829extern int drm_setversion(struct inode *inode, struct file *filp, 825extern int drm_setversion(struct inode *inode, struct file *filp,
830 unsigned int cmd, unsigned long arg); 826 unsigned int cmd, unsigned long arg);
831 827
832 /* Context IOCTL support (drm_context.h) */ 828 /* Context IOCTL support (drm_context.h) */
833extern int drm_resctx( struct inode *inode, struct file *filp, 829extern int drm_resctx(struct inode *inode, struct file *filp,
834 unsigned int cmd, unsigned long arg ); 830 unsigned int cmd, unsigned long arg);
835extern int drm_addctx( struct inode *inode, struct file *filp, 831extern int drm_addctx(struct inode *inode, struct file *filp,
836 unsigned int cmd, unsigned long arg ); 832 unsigned int cmd, unsigned long arg);
837extern int drm_modctx( struct inode *inode, struct file *filp, 833extern int drm_modctx(struct inode *inode, struct file *filp,
838 unsigned int cmd, unsigned long arg ); 834 unsigned int cmd, unsigned long arg);
839extern int drm_getctx( struct inode *inode, struct file *filp, 835extern int drm_getctx(struct inode *inode, struct file *filp,
840 unsigned int cmd, unsigned long arg ); 836 unsigned int cmd, unsigned long arg);
841extern int drm_switchctx( struct inode *inode, struct file *filp, 837extern int drm_switchctx(struct inode *inode, struct file *filp,
842 unsigned int cmd, unsigned long arg ); 838 unsigned int cmd, unsigned long arg);
843extern int drm_newctx( struct inode *inode, struct file *filp, 839extern int drm_newctx(struct inode *inode, struct file *filp,
844 unsigned int cmd, unsigned long arg ); 840 unsigned int cmd, unsigned long arg);
845extern int drm_rmctx( struct inode *inode, struct file *filp, 841extern int drm_rmctx(struct inode *inode, struct file *filp,
846 unsigned int cmd, unsigned long arg ); 842 unsigned int cmd, unsigned long arg);
847 843
848extern int drm_ctxbitmap_init( drm_device_t *dev ); 844extern int drm_ctxbitmap_init(drm_device_t * dev);
849extern void drm_ctxbitmap_cleanup( drm_device_t *dev ); 845extern void drm_ctxbitmap_cleanup(drm_device_t * dev);
850extern void drm_ctxbitmap_free( drm_device_t *dev, int ctx_handle ); 846extern void drm_ctxbitmap_free(drm_device_t * dev, int ctx_handle);
851 847
852extern int drm_setsareactx( struct inode *inode, struct file *filp, 848extern int drm_setsareactx(struct inode *inode, struct file *filp,
853 unsigned int cmd, unsigned long arg ); 849 unsigned int cmd, unsigned long arg);
854extern int drm_getsareactx( struct inode *inode, struct file *filp, 850extern int drm_getsareactx(struct inode *inode, struct file *filp,
855 unsigned int cmd, unsigned long arg ); 851 unsigned int cmd, unsigned long arg);
856 852
857 /* Drawable IOCTL support (drm_drawable.h) */ 853 /* Drawable IOCTL support (drm_drawable.h) */
858extern int drm_adddraw(struct inode *inode, struct file *filp, 854extern int drm_adddraw(struct inode *inode, struct file *filp,
859 unsigned int cmd, unsigned long arg); 855 unsigned int cmd, unsigned long arg);
860extern int drm_rmdraw(struct inode *inode, struct file *filp, 856extern int drm_rmdraw(struct inode *inode, struct file *filp,
861 unsigned int cmd, unsigned long arg); 857 unsigned int cmd, unsigned long arg);
862
863 858
864 /* Authentication IOCTL support (drm_auth.h) */ 859 /* Authentication IOCTL support (drm_auth.h) */
865extern int drm_getmagic(struct inode *inode, struct file *filp, 860extern int drm_getmagic(struct inode *inode, struct file *filp,
866 unsigned int cmd, unsigned long arg); 861 unsigned int cmd, unsigned long arg);
867extern int drm_authmagic(struct inode *inode, struct file *filp, 862extern int drm_authmagic(struct inode *inode, struct file *filp,
868 unsigned int cmd, unsigned long arg); 863 unsigned int cmd, unsigned long arg);
869 864
870 /* Placeholder for ioctls past */ 865 /* Placeholder for ioctls past */
871extern int drm_noop(struct inode *inode, struct file *filp, 866extern int drm_noop(struct inode *inode, struct file *filp,
872 unsigned int cmd, unsigned long arg); 867 unsigned int cmd, unsigned long arg);
873 868
874 /* Locking IOCTL support (drm_lock.h) */ 869 /* Locking IOCTL support (drm_lock.h) */
875extern int drm_lock(struct inode *inode, struct file *filp, 870extern int drm_lock(struct inode *inode, struct file *filp,
876 unsigned int cmd, unsigned long arg); 871 unsigned int cmd, unsigned long arg);
877extern int drm_unlock(struct inode *inode, struct file *filp, 872extern int drm_unlock(struct inode *inode, struct file *filp,
878 unsigned int cmd, unsigned long arg); 873 unsigned int cmd, unsigned long arg);
879extern int drm_lock_take(__volatile__ unsigned int *lock, 874extern int drm_lock_take(__volatile__ unsigned int *lock, unsigned int context);
880 unsigned int context); 875extern int drm_lock_free(drm_device_t * dev,
881extern int drm_lock_free(drm_device_t *dev, 876 __volatile__ unsigned int *lock, unsigned int context);
882 __volatile__ unsigned int *lock,
883 unsigned int context);
884 877
885 /* Buffer management support (drm_bufs.h) */ 878 /* Buffer management support (drm_bufs.h) */
886extern int drm_addbufs_agp(drm_device_t *dev, drm_buf_desc_t *request); 879extern int drm_addbufs_agp(drm_device_t * dev, drm_buf_desc_t * request);
887extern int drm_addbufs_pci(drm_device_t *dev, drm_buf_desc_t *request); 880extern int drm_addbufs_pci(drm_device_t * dev, drm_buf_desc_t * request);
888extern int drm_addmap(drm_device_t *dev, unsigned int offset, 881extern int drm_addmap(drm_device_t * dev, unsigned int offset,
889 unsigned int size, drm_map_type_t type, 882 unsigned int size, drm_map_type_t type,
890 drm_map_flags_t flags, drm_local_map_t **map_ptr); 883 drm_map_flags_t flags, drm_local_map_t ** map_ptr);
891extern int drm_addmap_ioctl(struct inode *inode, struct file *filp, 884extern int drm_addmap_ioctl(struct inode *inode, struct file *filp,
892 unsigned int cmd, unsigned long arg); 885 unsigned int cmd, unsigned long arg);
893extern int drm_rmmap(drm_device_t *dev, drm_local_map_t *map); 886extern int drm_rmmap(drm_device_t * dev, drm_local_map_t * map);
894extern int drm_rmmap_locked(drm_device_t *dev, drm_local_map_t *map); 887extern int drm_rmmap_locked(drm_device_t * dev, drm_local_map_t * map);
895extern int drm_rmmap_ioctl(struct inode *inode, struct file *filp, 888extern int drm_rmmap_ioctl(struct inode *inode, struct file *filp,
896 unsigned int cmd, unsigned long arg); 889 unsigned int cmd, unsigned long arg);
897 890
898extern int drm_order( unsigned long size ); 891extern int drm_order(unsigned long size);
899extern int drm_addbufs( struct inode *inode, struct file *filp, 892extern int drm_addbufs(struct inode *inode, struct file *filp,
900 unsigned int cmd, unsigned long arg ); 893 unsigned int cmd, unsigned long arg);
901extern int drm_infobufs( struct inode *inode, struct file *filp, 894extern int drm_infobufs(struct inode *inode, struct file *filp,
902 unsigned int cmd, unsigned long arg ); 895 unsigned int cmd, unsigned long arg);
903extern int drm_markbufs( struct inode *inode, struct file *filp, 896extern int drm_markbufs(struct inode *inode, struct file *filp,
904 unsigned int cmd, unsigned long arg ); 897 unsigned int cmd, unsigned long arg);
905extern int drm_freebufs( struct inode *inode, struct file *filp, 898extern int drm_freebufs(struct inode *inode, struct file *filp,
906 unsigned int cmd, unsigned long arg ); 899 unsigned int cmd, unsigned long arg);
907extern int drm_mapbufs( struct inode *inode, struct file *filp, 900extern int drm_mapbufs(struct inode *inode, struct file *filp,
908 unsigned int cmd, unsigned long arg ); 901 unsigned int cmd, unsigned long arg);
909extern unsigned long drm_get_resource_start(drm_device_t *dev, 902extern unsigned long drm_get_resource_start(drm_device_t * dev,
910 unsigned int resource); 903 unsigned int resource);
911extern unsigned long drm_get_resource_len(drm_device_t *dev, 904extern unsigned long drm_get_resource_len(drm_device_t * dev,
912 unsigned int resource); 905 unsigned int resource);
913 906
914 /* DMA support (drm_dma.h) */ 907 /* DMA support (drm_dma.h) */
915extern int drm_dma_setup(drm_device_t *dev); 908extern int drm_dma_setup(drm_device_t * dev);
916extern void drm_dma_takedown(drm_device_t *dev); 909extern void drm_dma_takedown(drm_device_t * dev);
917extern void drm_free_buffer(drm_device_t *dev, drm_buf_t *buf); 910extern void drm_free_buffer(drm_device_t * dev, drm_buf_t * buf);
918extern void drm_core_reclaim_buffers(drm_device_t *dev, struct file *filp); 911extern void drm_core_reclaim_buffers(drm_device_t * dev, struct file *filp);
919 912
920 /* IRQ support (drm_irq.h) */ 913 /* IRQ support (drm_irq.h) */
921extern int drm_control( struct inode *inode, struct file *filp, 914extern int drm_control(struct inode *inode, struct file *filp,
922 unsigned int cmd, unsigned long arg ); 915 unsigned int cmd, unsigned long arg);
923extern int drm_irq_uninstall( drm_device_t *dev ); 916extern int drm_irq_uninstall(drm_device_t * dev);
924extern irqreturn_t drm_irq_handler( DRM_IRQ_ARGS ); 917extern irqreturn_t drm_irq_handler(DRM_IRQ_ARGS);
925extern void drm_driver_irq_preinstall( drm_device_t *dev ); 918extern void drm_driver_irq_preinstall(drm_device_t * dev);
926extern void drm_driver_irq_postinstall( drm_device_t *dev ); 919extern void drm_driver_irq_postinstall(drm_device_t * dev);
927extern void drm_driver_irq_uninstall( drm_device_t *dev ); 920extern void drm_driver_irq_uninstall(drm_device_t * dev);
928 921
929extern int drm_wait_vblank(struct inode *inode, struct file *filp, 922extern int drm_wait_vblank(struct inode *inode, struct file *filp,
930 unsigned int cmd, unsigned long arg); 923 unsigned int cmd, unsigned long arg);
931extern int drm_vblank_wait(drm_device_t *dev, unsigned int *vbl_seq); 924extern int drm_vblank_wait(drm_device_t * dev, unsigned int *vbl_seq);
932extern void drm_vbl_send_signals( drm_device_t *dev ); 925extern void drm_vbl_send_signals(drm_device_t * dev);
933 926
934 /* AGP/GART support (drm_agpsupport.h) */ 927 /* AGP/GART support (drm_agpsupport.h) */
935extern drm_agp_head_t *drm_agp_init(drm_device_t *dev); 928extern drm_agp_head_t *drm_agp_init(drm_device_t * dev);
936extern int drm_agp_acquire(drm_device_t * dev); 929extern int drm_agp_acquire(drm_device_t * dev);
937extern int drm_agp_acquire_ioctl(struct inode *inode, struct file *filp, 930extern int drm_agp_acquire_ioctl(struct inode *inode, struct file *filp,
938 unsigned int cmd, unsigned long arg); 931 unsigned int cmd, unsigned long arg);
939extern int drm_agp_release(drm_device_t *dev); 932extern int drm_agp_release(drm_device_t * dev);
940extern int drm_agp_release_ioctl(struct inode *inode, struct file *filp, 933extern int drm_agp_release_ioctl(struct inode *inode, struct file *filp,
941 unsigned int cmd, unsigned long arg); 934 unsigned int cmd, unsigned long arg);
942extern int drm_agp_enable(drm_device_t *dev, drm_agp_mode_t mode); 935extern int drm_agp_enable(drm_device_t * dev, drm_agp_mode_t mode);
943extern int drm_agp_enable_ioctl(struct inode *inode, struct file *filp, 936extern int drm_agp_enable_ioctl(struct inode *inode, struct file *filp,
944 unsigned int cmd, unsigned long arg); 937 unsigned int cmd, unsigned long arg);
945extern int drm_agp_info(drm_device_t * dev, drm_agp_info_t *info); 938extern int drm_agp_info(drm_device_t * dev, drm_agp_info_t * info);
946extern int drm_agp_info_ioctl(struct inode *inode, struct file *filp, 939extern int drm_agp_info_ioctl(struct inode *inode, struct file *filp,
940 unsigned int cmd, unsigned long arg);
941extern int drm_agp_alloc(struct inode *inode, struct file *filp,
942 unsigned int cmd, unsigned long arg);
943extern int drm_agp_free(struct inode *inode, struct file *filp,
947 unsigned int cmd, unsigned long arg); 944 unsigned int cmd, unsigned long arg);
948extern int drm_agp_alloc(struct inode *inode, struct file *filp, 945extern int drm_agp_unbind(struct inode *inode, struct file *filp,
949 unsigned int cmd, unsigned long arg); 946 unsigned int cmd, unsigned long arg);
950extern int drm_agp_free(struct inode *inode, struct file *filp, 947extern int drm_agp_bind(struct inode *inode, struct file *filp,
951 unsigned int cmd, unsigned long arg); 948 unsigned int cmd, unsigned long arg);
952extern int drm_agp_unbind(struct inode *inode, struct file *filp, 949extern DRM_AGP_MEM *drm_agp_allocate_memory(struct agp_bridge_data *bridge,
953 unsigned int cmd, unsigned long arg); 950 size_t pages, u32 type);
954extern int drm_agp_bind(struct inode *inode, struct file *filp, 951extern int drm_agp_free_memory(DRM_AGP_MEM * handle);
955 unsigned int cmd, unsigned long arg); 952extern int drm_agp_bind_memory(DRM_AGP_MEM * handle, off_t start);
956extern DRM_AGP_MEM *drm_agp_allocate_memory(struct agp_bridge_data *bridge, size_t pages, u32 type); 953extern int drm_agp_unbind_memory(DRM_AGP_MEM * handle);
957extern int drm_agp_free_memory(DRM_AGP_MEM *handle);
958extern int drm_agp_bind_memory(DRM_AGP_MEM *handle, off_t start);
959extern int drm_agp_unbind_memory(DRM_AGP_MEM *handle);
960 954
961 /* Stub support (drm_stub.h) */ 955 /* Stub support (drm_stub.h) */
962extern int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent, 956extern int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
963 struct drm_driver *driver); 957 struct drm_driver *driver);
964extern int drm_put_dev(drm_device_t * dev); 958extern int drm_put_dev(drm_device_t * dev);
965extern int drm_put_head(drm_head_t * head); 959extern int drm_put_head(drm_head_t * head);
966extern unsigned int drm_debug; 960extern unsigned int drm_debug;
967extern unsigned int drm_cards_limit; 961extern unsigned int drm_cards_limit;
968extern drm_head_t **drm_heads; 962extern drm_head_t **drm_heads;
969extern struct drm_sysfs_class *drm_class; 963extern struct drm_sysfs_class *drm_class;
970extern struct proc_dir_entry *drm_proc_root; 964extern struct proc_dir_entry *drm_proc_root;
971 965
972 /* Proc support (drm_proc.h) */ 966 /* Proc support (drm_proc.h) */
973extern int drm_proc_init(drm_device_t *dev, 967extern int drm_proc_init(drm_device_t * dev,
974 int minor, 968 int minor,
975 struct proc_dir_entry *root, 969 struct proc_dir_entry *root,
976 struct proc_dir_entry **dev_root); 970 struct proc_dir_entry **dev_root);
977extern int drm_proc_cleanup(int minor, 971extern int drm_proc_cleanup(int minor,
978 struct proc_dir_entry *root, 972 struct proc_dir_entry *root,
979 struct proc_dir_entry *dev_root); 973 struct proc_dir_entry *dev_root);
980 974
981 /* Scatter Gather Support (drm_scatter.h) */ 975 /* Scatter Gather Support (drm_scatter.h) */
982extern void drm_sg_cleanup(drm_sg_mem_t *entry); 976extern void drm_sg_cleanup(drm_sg_mem_t * entry);
983extern int drm_sg_alloc(struct inode *inode, struct file *filp, 977extern int drm_sg_alloc(struct inode *inode, struct file *filp,
984 unsigned int cmd, unsigned long arg); 978 unsigned int cmd, unsigned long arg);
985extern int drm_sg_free(struct inode *inode, struct file *filp, 979extern int drm_sg_free(struct inode *inode, struct file *filp,
986 unsigned int cmd, unsigned long arg); 980 unsigned int cmd, unsigned long arg);
987 981
988 /* ATI PCIGART support (ati_pcigart.h) */ 982 /* ATI PCIGART support (ati_pcigart.h) */
989extern int drm_ati_pcigart_init(drm_device_t * dev, drm_ati_pcigart_info *gart_info); 983extern int drm_ati_pcigart_init(drm_device_t * dev,
990extern int drm_ati_pcigart_cleanup(drm_device_t * dev, drm_ati_pcigart_info *gart_info); 984 drm_ati_pcigart_info * gart_info);
985extern int drm_ati_pcigart_cleanup(drm_device_t * dev,
986 drm_ati_pcigart_info * gart_info);
991 987
992extern drm_dma_handle_t *drm_pci_alloc(drm_device_t *dev, size_t size, 988extern drm_dma_handle_t *drm_pci_alloc(drm_device_t * dev, size_t size,
993 size_t align, dma_addr_t maxaddr); 989 size_t align, dma_addr_t maxaddr);
994extern void __drm_pci_free(drm_device_t *dev, drm_dma_handle_t *dmah); 990extern void __drm_pci_free(drm_device_t * dev, drm_dma_handle_t * dmah);
995extern void drm_pci_free(drm_device_t *dev, drm_dma_handle_t *dmah); 991extern void drm_pci_free(drm_device_t * dev, drm_dma_handle_t * dmah);
996 992
997 /* sysfs support (drm_sysfs.c) */ 993 /* sysfs support (drm_sysfs.c) */
998struct drm_sysfs_class; 994struct drm_sysfs_class;
@@ -1005,38 +1001,41 @@ extern struct class_device *drm_sysfs_device_add(struct drm_sysfs_class *cs,
1005 const char *fmt, ...); 1001 const char *fmt, ...);
1006extern void drm_sysfs_device_remove(dev_t dev); 1002extern void drm_sysfs_device_remove(dev_t dev);
1007 1003
1008
1009/* Inline replacements for DRM_IOREMAP macros */ 1004/* Inline replacements for DRM_IOREMAP macros */
1010static __inline__ void drm_core_ioremap(struct drm_map *map, struct drm_device *dev) 1005static __inline__ void drm_core_ioremap(struct drm_map *map,
1006 struct drm_device *dev)
1011{ 1007{
1012 map->handle = drm_ioremap( map->offset, map->size, dev ); 1008 map->handle = drm_ioremap(map->offset, map->size, dev);
1013} 1009}
1014 1010
1015static __inline__ void drm_core_ioremap_nocache(struct drm_map *map, struct drm_device *dev) 1011static __inline__ void drm_core_ioremap_nocache(struct drm_map *map,
1012 struct drm_device *dev)
1016{ 1013{
1017 map->handle = drm_ioremap_nocache(map->offset, map->size, dev); 1014 map->handle = drm_ioremap_nocache(map->offset, map->size, dev);
1018} 1015}
1019 1016
1020static __inline__ void drm_core_ioremapfree(struct drm_map *map, struct drm_device *dev) 1017static __inline__ void drm_core_ioremapfree(struct drm_map *map,
1018 struct drm_device *dev)
1021{ 1019{
1022 if ( map->handle && map->size ) 1020 if (map->handle && map->size)
1023 drm_ioremapfree( map->handle, map->size, dev ); 1021 drm_ioremapfree(map->handle, map->size, dev);
1024} 1022}
1025 1023
1026static __inline__ struct drm_map *drm_core_findmap(struct drm_device *dev, unsigned int token) 1024static __inline__ struct drm_map *drm_core_findmap(struct drm_device *dev,
1025 unsigned int token)
1027{ 1026{
1028 drm_map_list_t *_entry; 1027 drm_map_list_t *_entry;
1029 list_for_each_entry(_entry, &dev->maplist->head, head) 1028 list_for_each_entry(_entry, &dev->maplist->head, head)
1030 if (_entry->user_token == token) 1029 if (_entry->user_token == token)
1031 return _entry->map; 1030 return _entry->map;
1032 return NULL; 1031 return NULL;
1033} 1032}
1034 1033
1035static __inline__ int drm_device_is_agp(drm_device_t *dev) 1034static __inline__ int drm_device_is_agp(drm_device_t * dev)
1036{ 1035{
1037 if ( dev->driver->device_is_agp != NULL ) { 1036 if (dev->driver->device_is_agp != NULL) {
1038 int err = (*dev->driver->device_is_agp)( dev ); 1037 int err = (*dev->driver->device_is_agp) (dev);
1039 1038
1040 if (err != 2) { 1039 if (err != 2) {
1041 return err; 1040 return err;
1042 } 1041 }
@@ -1045,7 +1044,7 @@ static __inline__ int drm_device_is_agp(drm_device_t *dev)
1045 return pci_find_capability(dev->pdev, PCI_CAP_ID_AGP); 1044 return pci_find_capability(dev->pdev, PCI_CAP_ID_AGP);
1046} 1045}
1047 1046
1048static __inline__ int drm_device_is_pcie(drm_device_t *dev) 1047static __inline__ int drm_device_is_pcie(drm_device_t * dev)
1049{ 1048{
1050 return pci_find_capability(dev->pdev, PCI_CAP_ID_EXP); 1049 return pci_find_capability(dev->pdev, PCI_CAP_ID_EXP);
1051} 1050}
@@ -1080,12 +1079,12 @@ extern void *drm_calloc(size_t nmemb, size_t size, int area);
1080 1079
1081/*@}*/ 1080/*@}*/
1082 1081
1083extern unsigned long drm_core_get_map_ofs(drm_map_t *map); 1082extern unsigned long drm_core_get_map_ofs(drm_map_t * map);
1084extern unsigned long drm_core_get_reg_ofs(struct drm_device *dev); 1083extern unsigned long drm_core_get_reg_ofs(struct drm_device *dev);
1085 1084
1086#ifndef pci_pretty_name 1085#ifndef pci_pretty_name
1087#define pci_pretty_name(dev) "" 1086#define pci_pretty_name(dev) ""
1088#endif 1087#endif
1089 1088
1090#endif /* __KERNEL__ */ 1089#endif /* __KERNEL__ */
1091#endif 1090#endif
diff --git a/drivers/char/drm/drm_agpsupport.c b/drivers/char/drm/drm_agpsupport.c
index 8c215adcb4b2..2b6453a9ffce 100644
--- a/drivers/char/drm/drm_agpsupport.c
+++ b/drivers/char/drm/drm_agpsupport.c
@@ -1,7 +1,7 @@
1/** 1/**
2 * \file drm_agpsupport.h 2 * \file drm_agpsupport.h
3 * DRM support for AGP/GART backend 3 * DRM support for AGP/GART backend
4 * 4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
6 * \author Gareth Hughes <gareth@valinux.com> 6 * \author Gareth Hughes <gareth@valinux.com>
7 */ 7 */
@@ -48,30 +48,31 @@
48 * Verifies the AGP device has been initialized and acquired and fills in the 48 * Verifies the AGP device has been initialized and acquired and fills in the
49 * drm_agp_info structure with the information in drm_agp_head::agp_info. 49 * drm_agp_info structure with the information in drm_agp_head::agp_info.
50 */ 50 */
51int drm_agp_info(drm_device_t *dev, drm_agp_info_t *info) 51int drm_agp_info(drm_device_t * dev, drm_agp_info_t * info)
52{ 52{
53 DRM_AGP_KERN *kern; 53 DRM_AGP_KERN *kern;
54 54
55 if (!dev->agp || !dev->agp->acquired) 55 if (!dev->agp || !dev->agp->acquired)
56 return -EINVAL; 56 return -EINVAL;
57 57
58 kern = &dev->agp->agp_info; 58 kern = &dev->agp->agp_info;
59 info->agp_version_major = kern->version.major; 59 info->agp_version_major = kern->version.major;
60 info->agp_version_minor = kern->version.minor; 60 info->agp_version_minor = kern->version.minor;
61 info->mode = kern->mode; 61 info->mode = kern->mode;
62 info->aperture_base = kern->aper_base; 62 info->aperture_base = kern->aper_base;
63 info->aperture_size = kern->aper_size * 1024 * 1024; 63 info->aperture_size = kern->aper_size * 1024 * 1024;
64 info->memory_allowed = kern->max_memory << PAGE_SHIFT; 64 info->memory_allowed = kern->max_memory << PAGE_SHIFT;
65 info->memory_used = kern->current_memory << PAGE_SHIFT; 65 info->memory_used = kern->current_memory << PAGE_SHIFT;
66 info->id_vendor = kern->device->vendor; 66 info->id_vendor = kern->device->vendor;
67 info->id_device = kern->device->device; 67 info->id_device = kern->device->device;
68 68
69 return 0; 69 return 0;
70} 70}
71
71EXPORT_SYMBOL(drm_agp_info); 72EXPORT_SYMBOL(drm_agp_info);
72 73
73int drm_agp_info_ioctl(struct inode *inode, struct file *filp, 74int drm_agp_info_ioctl(struct inode *inode, struct file *filp,
74 unsigned int cmd, unsigned long arg) 75 unsigned int cmd, unsigned long arg)
75{ 76{
76 drm_file_t *priv = filp->private_data; 77 drm_file_t *priv = filp->private_data;
77 drm_device_t *dev = priv->head->dev; 78 drm_device_t *dev = priv->head->dev;
@@ -81,7 +82,7 @@ int drm_agp_info_ioctl(struct inode *inode, struct file *filp,
81 err = drm_agp_info(dev, &info); 82 err = drm_agp_info(dev, &info);
82 if (err) 83 if (err)
83 return err; 84 return err;
84 85
85 if (copy_to_user((drm_agp_info_t __user *) arg, &info, sizeof(info))) 86 if (copy_to_user((drm_agp_info_t __user *) arg, &info, sizeof(info)))
86 return -EFAULT; 87 return -EFAULT;
87 return 0; 88 return 0;
@@ -91,12 +92,12 @@ int drm_agp_info_ioctl(struct inode *inode, struct file *filp,
91 * Acquire the AGP device. 92 * Acquire the AGP device.
92 * 93 *
93 * \param dev DRM device that is to acquire AGP 94 * \param dev DRM device that is to acquire AGP
94 * \return zero on success or a negative number on failure. 95 * \return zero on success or a negative number on failure.
95 * 96 *
96 * Verifies the AGP device hasn't been acquired before and calls 97 * Verifies the AGP device hasn't been acquired before and calls
97 * \c agp_backend_acquire. 98 * \c agp_backend_acquire.
98 */ 99 */
99int drm_agp_acquire(drm_device_t *dev) 100int drm_agp_acquire(drm_device_t * dev)
100{ 101{
101 if (!dev->agp) 102 if (!dev->agp)
102 return -ENODEV; 103 return -ENODEV;
@@ -107,6 +108,7 @@ int drm_agp_acquire(drm_device_t *dev)
107 dev->agp->acquired = 1; 108 dev->agp->acquired = 1;
108 return 0; 109 return 0;
109} 110}
111
110EXPORT_SYMBOL(drm_agp_acquire); 112EXPORT_SYMBOL(drm_agp_acquire);
111 113
112/** 114/**
@@ -125,8 +127,8 @@ int drm_agp_acquire_ioctl(struct inode *inode, struct file *filp,
125 unsigned int cmd, unsigned long arg) 127 unsigned int cmd, unsigned long arg)
126{ 128{
127 drm_file_t *priv = filp->private_data; 129 drm_file_t *priv = filp->private_data;
128 130
129 return drm_agp_acquire( (drm_device_t *) priv->head->dev ); 131 return drm_agp_acquire((drm_device_t *) priv->head->dev);
130} 132}
131 133
132/** 134/**
@@ -137,7 +139,7 @@ int drm_agp_acquire_ioctl(struct inode *inode, struct file *filp,
137 * 139 *
138 * Verifies the AGP device has been acquired and calls \c agp_backend_release. 140 * Verifies the AGP device has been acquired and calls \c agp_backend_release.
139 */ 141 */
140int drm_agp_release(drm_device_t *dev) 142int drm_agp_release(drm_device_t * dev)
141{ 143{
142 if (!dev->agp || !dev->agp->acquired) 144 if (!dev->agp || !dev->agp->acquired)
143 return -EINVAL; 145 return -EINVAL;
@@ -145,6 +147,7 @@ int drm_agp_release(drm_device_t *dev)
145 dev->agp->acquired = 0; 147 dev->agp->acquired = 0;
146 return 0; 148 return 0;
147} 149}
150
148EXPORT_SYMBOL(drm_agp_release); 151EXPORT_SYMBOL(drm_agp_release);
149 152
150int drm_agp_release_ioctl(struct inode *inode, struct file *filp, 153int drm_agp_release_ioctl(struct inode *inode, struct file *filp,
@@ -152,13 +155,13 @@ int drm_agp_release_ioctl(struct inode *inode, struct file *filp,
152{ 155{
153 drm_file_t *priv = filp->private_data; 156 drm_file_t *priv = filp->private_data;
154 drm_device_t *dev = priv->head->dev; 157 drm_device_t *dev = priv->head->dev;
155 158
156 return drm_agp_release(dev); 159 return drm_agp_release(dev);
157} 160}
158 161
159/** 162/**
160 * Enable the AGP bus. 163 * Enable the AGP bus.
161 * 164 *
162 * \param dev DRM device that has previously acquired AGP. 165 * \param dev DRM device that has previously acquired AGP.
163 * \param mode Requested AGP mode. 166 * \param mode Requested AGP mode.
164 * \return zero on success or a negative number on failure. 167 * \return zero on success or a negative number on failure.
@@ -166,27 +169,27 @@ int drm_agp_release_ioctl(struct inode *inode, struct file *filp,
166 * Verifies the AGP device has been acquired but not enabled, and calls 169 * Verifies the AGP device has been acquired but not enabled, and calls
167 * \c agp_enable. 170 * \c agp_enable.
168 */ 171 */
169int drm_agp_enable(drm_device_t *dev, drm_agp_mode_t mode) 172int drm_agp_enable(drm_device_t * dev, drm_agp_mode_t mode)
170{ 173{
171 if (!dev->agp || !dev->agp->acquired) 174 if (!dev->agp || !dev->agp->acquired)
172 return -EINVAL; 175 return -EINVAL;
173 176
174 dev->agp->mode = mode.mode; 177 dev->agp->mode = mode.mode;
175 agp_enable(dev->agp->bridge, mode.mode); 178 agp_enable(dev->agp->bridge, mode.mode);
176 dev->agp->base = dev->agp->agp_info.aper_base; 179 dev->agp->base = dev->agp->agp_info.aper_base;
177 dev->agp->enabled = 1; 180 dev->agp->enabled = 1;
178 return 0; 181 return 0;
179} 182}
183
180EXPORT_SYMBOL(drm_agp_enable); 184EXPORT_SYMBOL(drm_agp_enable);
181 185
182int drm_agp_enable_ioctl(struct inode *inode, struct file *filp, 186int drm_agp_enable_ioctl(struct inode *inode, struct file *filp,
183 unsigned int cmd, unsigned long arg) 187 unsigned int cmd, unsigned long arg)
184{ 188{
185 drm_file_t *priv = filp->private_data; 189 drm_file_t *priv = filp->private_data;
186 drm_device_t *dev = priv->head->dev; 190 drm_device_t *dev = priv->head->dev;
187 drm_agp_mode_t mode; 191 drm_agp_mode_t mode;
188 192
189
190 if (copy_from_user(&mode, (drm_agp_mode_t __user *) arg, sizeof(mode))) 193 if (copy_from_user(&mode, (drm_agp_mode_t __user *) arg, sizeof(mode)))
191 return -EFAULT; 194 return -EFAULT;
192 195
@@ -201,20 +204,20 @@ int drm_agp_enable_ioctl(struct inode *inode, struct file *filp,
201 * \param cmd command. 204 * \param cmd command.
202 * \param arg pointer to a drm_agp_buffer structure. 205 * \param arg pointer to a drm_agp_buffer structure.
203 * \return zero on success or a negative number on failure. 206 * \return zero on success or a negative number on failure.
204 * 207 *
205 * Verifies the AGP device is present and has been acquired, allocates the 208 * Verifies the AGP device is present and has been acquired, allocates the
206 * memory via alloc_agp() and creates a drm_agp_mem entry for it. 209 * memory via alloc_agp() and creates a drm_agp_mem entry for it.
207 */ 210 */
208int drm_agp_alloc(struct inode *inode, struct file *filp, 211int drm_agp_alloc(struct inode *inode, struct file *filp,
209 unsigned int cmd, unsigned long arg) 212 unsigned int cmd, unsigned long arg)
210{ 213{
211 drm_file_t *priv = filp->private_data; 214 drm_file_t *priv = filp->private_data;
212 drm_device_t *dev = priv->head->dev; 215 drm_device_t *dev = priv->head->dev;
213 drm_agp_buffer_t request; 216 drm_agp_buffer_t request;
214 drm_agp_mem_t *entry; 217 drm_agp_mem_t *entry;
215 DRM_AGP_MEM *memory; 218 DRM_AGP_MEM *memory;
216 unsigned long pages; 219 unsigned long pages;
217 u32 type; 220 u32 type;
218 drm_agp_buffer_t __user *argp = (void __user *)arg; 221 drm_agp_buffer_t __user *argp = (void __user *)arg;
219 222
220 if (!dev->agp || !dev->agp->acquired) 223 if (!dev->agp || !dev->agp->acquired)
@@ -224,7 +227,7 @@ int drm_agp_alloc(struct inode *inode, struct file *filp,
224 if (!(entry = drm_alloc(sizeof(*entry), DRM_MEM_AGPLISTS))) 227 if (!(entry = drm_alloc(sizeof(*entry), DRM_MEM_AGPLISTS)))
225 return -ENOMEM; 228 return -ENOMEM;
226 229
227 memset(entry, 0, sizeof(*entry)); 230 memset(entry, 0, sizeof(*entry));
228 231
229 pages = (request.size + PAGE_SIZE - 1) / PAGE_SIZE; 232 pages = (request.size + PAGE_SIZE - 1) / PAGE_SIZE;
230 type = (u32) request.type; 233 type = (u32) request.type;
@@ -234,21 +237,21 @@ int drm_agp_alloc(struct inode *inode, struct file *filp,
234 return -ENOMEM; 237 return -ENOMEM;
235 } 238 }
236 239
237 entry->handle = (unsigned long)memory->key + 1; 240 entry->handle = (unsigned long)memory->key + 1;
238 entry->memory = memory; 241 entry->memory = memory;
239 entry->bound = 0; 242 entry->bound = 0;
240 entry->pages = pages; 243 entry->pages = pages;
241 entry->prev = NULL; 244 entry->prev = NULL;
242 entry->next = dev->agp->memory; 245 entry->next = dev->agp->memory;
243 if (dev->agp->memory) 246 if (dev->agp->memory)
244 dev->agp->memory->prev = entry; 247 dev->agp->memory->prev = entry;
245 dev->agp->memory = entry; 248 dev->agp->memory = entry;
246 249
247 request.handle = entry->handle; 250 request.handle = entry->handle;
248 request.physical = memory->physical; 251 request.physical = memory->physical;
249 252
250 if (copy_to_user(argp, &request, sizeof(request))) { 253 if (copy_to_user(argp, &request, sizeof(request))) {
251 dev->agp->memory = entry->next; 254 dev->agp->memory = entry->next;
252 dev->agp->memory->prev = NULL; 255 dev->agp->memory->prev = NULL;
253 drm_free_agp(memory, pages); 256 drm_free_agp(memory, pages);
254 drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS); 257 drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS);
@@ -263,11 +266,11 @@ int drm_agp_alloc(struct inode *inode, struct file *filp,
263 * \param dev DRM device structure. 266 * \param dev DRM device structure.
264 * \param handle AGP memory handle. 267 * \param handle AGP memory handle.
265 * \return pointer to the drm_agp_mem structure associated with \p handle. 268 * \return pointer to the drm_agp_mem structure associated with \p handle.
266 * 269 *
267 * Walks through drm_agp_head::memory until finding a matching handle. 270 * Walks through drm_agp_head::memory until finding a matching handle.
268 */ 271 */
269static drm_agp_mem_t *drm_agp_lookup_entry(drm_device_t *dev, 272static drm_agp_mem_t *drm_agp_lookup_entry(drm_device_t * dev,
270 unsigned long handle) 273 unsigned long handle)
271{ 274{
272 drm_agp_mem_t *entry; 275 drm_agp_mem_t *entry;
273 276
@@ -291,17 +294,18 @@ static drm_agp_mem_t *drm_agp_lookup_entry(drm_device_t *dev,
291 * entry and passes it to the unbind_agp() function. 294 * entry and passes it to the unbind_agp() function.
292 */ 295 */
293int drm_agp_unbind(struct inode *inode, struct file *filp, 296int drm_agp_unbind(struct inode *inode, struct file *filp,
294 unsigned int cmd, unsigned long arg) 297 unsigned int cmd, unsigned long arg)
295{ 298{
296 drm_file_t *priv = filp->private_data; 299 drm_file_t *priv = filp->private_data;
297 drm_device_t *dev = priv->head->dev; 300 drm_device_t *dev = priv->head->dev;
298 drm_agp_binding_t request; 301 drm_agp_binding_t request;
299 drm_agp_mem_t *entry; 302 drm_agp_mem_t *entry;
300 int ret; 303 int ret;
301 304
302 if (!dev->agp || !dev->agp->acquired) 305 if (!dev->agp || !dev->agp->acquired)
303 return -EINVAL; 306 return -EINVAL;
304 if (copy_from_user(&request, (drm_agp_binding_t __user *)arg, sizeof(request))) 307 if (copy_from_user
308 (&request, (drm_agp_binding_t __user *) arg, sizeof(request)))
305 return -EFAULT; 309 return -EFAULT;
306 if (!(entry = drm_agp_lookup_entry(dev, request.handle))) 310 if (!(entry = drm_agp_lookup_entry(dev, request.handle)))
307 return -EINVAL; 311 return -EINVAL;
@@ -309,7 +313,7 @@ int drm_agp_unbind(struct inode *inode, struct file *filp,
309 return -EINVAL; 313 return -EINVAL;
310 ret = drm_unbind_agp(entry->memory); 314 ret = drm_unbind_agp(entry->memory);
311 if (ret == 0) 315 if (ret == 0)
312 entry->bound = 0; 316 entry->bound = 0;
313 return ret; 317 return ret;
314} 318}
315 319
@@ -327,18 +331,19 @@ int drm_agp_unbind(struct inode *inode, struct file *filp,
327 * it to bind_agp() function. 331 * it to bind_agp() function.
328 */ 332 */
329int drm_agp_bind(struct inode *inode, struct file *filp, 333int drm_agp_bind(struct inode *inode, struct file *filp,
330 unsigned int cmd, unsigned long arg) 334 unsigned int cmd, unsigned long arg)
331{ 335{
332 drm_file_t *priv = filp->private_data; 336 drm_file_t *priv = filp->private_data;
333 drm_device_t *dev = priv->head->dev; 337 drm_device_t *dev = priv->head->dev;
334 drm_agp_binding_t request; 338 drm_agp_binding_t request;
335 drm_agp_mem_t *entry; 339 drm_agp_mem_t *entry;
336 int retcode; 340 int retcode;
337 int page; 341 int page;
338 342
339 if (!dev->agp || !dev->agp->acquired) 343 if (!dev->agp || !dev->agp->acquired)
340 return -EINVAL; 344 return -EINVAL;
341 if (copy_from_user(&request, (drm_agp_binding_t __user *)arg, sizeof(request))) 345 if (copy_from_user
346 (&request, (drm_agp_binding_t __user *) arg, sizeof(request)))
342 return -EFAULT; 347 return -EFAULT;
343 if (!(entry = drm_agp_lookup_entry(dev, request.handle))) 348 if (!(entry = drm_agp_lookup_entry(dev, request.handle)))
344 return -EINVAL; 349 return -EINVAL;
@@ -368,16 +373,17 @@ int drm_agp_bind(struct inode *inode, struct file *filp,
368 * and unlinks from the doubly linked list it's inserted in. 373 * and unlinks from the doubly linked list it's inserted in.
369 */ 374 */
370int drm_agp_free(struct inode *inode, struct file *filp, 375int drm_agp_free(struct inode *inode, struct file *filp,
371 unsigned int cmd, unsigned long arg) 376 unsigned int cmd, unsigned long arg)
372{ 377{
373 drm_file_t *priv = filp->private_data; 378 drm_file_t *priv = filp->private_data;
374 drm_device_t *dev = priv->head->dev; 379 drm_device_t *dev = priv->head->dev;
375 drm_agp_buffer_t request; 380 drm_agp_buffer_t request;
376 drm_agp_mem_t *entry; 381 drm_agp_mem_t *entry;
377 382
378 if (!dev->agp || !dev->agp->acquired) 383 if (!dev->agp || !dev->agp->acquired)
379 return -EINVAL; 384 return -EINVAL;
380 if (copy_from_user(&request, (drm_agp_buffer_t __user *)arg, sizeof(request))) 385 if (copy_from_user
386 (&request, (drm_agp_buffer_t __user *) arg, sizeof(request)))
381 return -EFAULT; 387 return -EFAULT;
382 if (!(entry = drm_agp_lookup_entry(dev, request.handle))) 388 if (!(entry = drm_agp_lookup_entry(dev, request.handle)))
383 return -EINVAL; 389 return -EINVAL;
@@ -403,9 +409,9 @@ int drm_agp_free(struct inode *inode, struct file *filp,
403 * \return pointer to a drm_agp_head structure. 409 * \return pointer to a drm_agp_head structure.
404 * 410 *
405 */ 411 */
406drm_agp_head_t *drm_agp_init(drm_device_t *dev) 412drm_agp_head_t *drm_agp_init(drm_device_t * dev)
407{ 413{
408 drm_agp_head_t *head = NULL; 414 drm_agp_head_t *head = NULL;
409 415
410 if (!(head = drm_alloc(sizeof(*head), DRM_MEM_AGPLISTS))) 416 if (!(head = drm_alloc(sizeof(*head), DRM_MEM_AGPLISTS)))
411 return NULL; 417 return NULL;
@@ -433,13 +439,14 @@ drm_agp_head_t *drm_agp_init(drm_device_t *dev)
433} 439}
434 440
435/** Calls agp_allocate_memory() */ 441/** Calls agp_allocate_memory() */
436DRM_AGP_MEM *drm_agp_allocate_memory(struct agp_bridge_data *bridge, size_t pages, u32 type) 442DRM_AGP_MEM *drm_agp_allocate_memory(struct agp_bridge_data * bridge,
443 size_t pages, u32 type)
437{ 444{
438 return agp_allocate_memory(bridge, pages, type); 445 return agp_allocate_memory(bridge, pages, type);
439} 446}
440 447
441/** Calls agp_free_memory() */ 448/** Calls agp_free_memory() */
442int drm_agp_free_memory(DRM_AGP_MEM *handle) 449int drm_agp_free_memory(DRM_AGP_MEM * handle)
443{ 450{
444 if (!handle) 451 if (!handle)
445 return 0; 452 return 0;
@@ -448,20 +455,21 @@ int drm_agp_free_memory(DRM_AGP_MEM *handle)
448} 455}
449 456
450/** Calls agp_bind_memory() */ 457/** Calls agp_bind_memory() */
451int drm_agp_bind_memory(DRM_AGP_MEM *handle, off_t start) 458int drm_agp_bind_memory(DRM_AGP_MEM * handle, off_t start)
452{ 459{
453 if (!handle) 460 if (!handle)
454 return -EINVAL; 461 return -EINVAL;
455 return agp_bind_memory(handle, start); 462 return agp_bind_memory(handle, start);
456} 463}
464
457EXPORT_SYMBOL(drm_agp_bind_memory); 465EXPORT_SYMBOL(drm_agp_bind_memory);
458 466
459/** Calls agp_unbind_memory() */ 467/** Calls agp_unbind_memory() */
460int drm_agp_unbind_memory(DRM_AGP_MEM *handle) 468int drm_agp_unbind_memory(DRM_AGP_MEM * handle)
461{ 469{
462 if (!handle) 470 if (!handle)
463 return -EINVAL; 471 return -EINVAL;
464 return agp_unbind_memory(handle); 472 return agp_unbind_memory(handle);
465} 473}
466 474
467#endif /* __OS_HAS_AGP */ 475#endif /* __OS_HAS_AGP */
diff --git a/drivers/char/drm/drm_auth.c b/drivers/char/drm/drm_auth.c
index dd140bca8f71..a47b502bc7cc 100644
--- a/drivers/char/drm/drm_auth.c
+++ b/drivers/char/drm/drm_auth.c
@@ -1,5 +1,5 @@
1/** 1/**
2 * \file drm_auth.h 2 * \file drm_auth.c
3 * IOCTLs for authentication 3 * IOCTLs for authentication
4 * 4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
@@ -46,7 +46,7 @@
46 */ 46 */
47static int drm_hash_magic(drm_magic_t magic) 47static int drm_hash_magic(drm_magic_t magic)
48{ 48{
49 return magic & (DRM_HASH_SIZE-1); 49 return magic & (DRM_HASH_SIZE - 1);
50} 50}
51 51
52/** 52/**
@@ -59,11 +59,11 @@ static int drm_hash_magic(drm_magic_t magic)
59 * the one with matching magic number, while holding the drm_device::struct_sem 59 * the one with matching magic number, while holding the drm_device::struct_sem
60 * lock. 60 * lock.
61 */ 61 */
62static drm_file_t *drm_find_file(drm_device_t *dev, drm_magic_t magic) 62static drm_file_t *drm_find_file(drm_device_t * dev, drm_magic_t magic)
63{ 63{
64 drm_file_t *retval = NULL; 64 drm_file_t *retval = NULL;
65 drm_magic_entry_t *pt; 65 drm_magic_entry_t *pt;
66 int hash = drm_hash_magic(magic); 66 int hash = drm_hash_magic(magic);
67 67
68 down(&dev->struct_sem); 68 down(&dev->struct_sem);
69 for (pt = dev->magiclist[hash].head; pt; pt = pt->next) { 69 for (pt = dev->magiclist[hash].head; pt; pt = pt->next) {
@@ -78,7 +78,7 @@ static drm_file_t *drm_find_file(drm_device_t *dev, drm_magic_t magic)
78 78
79/** 79/**
80 * Adds a magic number. 80 * Adds a magic number.
81 * 81 *
82 * \param dev DRM device. 82 * \param dev DRM device.
83 * \param priv file private data. 83 * \param priv file private data.
84 * \param magic magic number. 84 * \param magic magic number.
@@ -87,28 +87,30 @@ static drm_file_t *drm_find_file(drm_device_t *dev, drm_magic_t magic)
87 * associated the magic number hash key in drm_device::magiclist, while holding 87 * associated the magic number hash key in drm_device::magiclist, while holding
88 * the drm_device::struct_sem lock. 88 * the drm_device::struct_sem lock.
89 */ 89 */
90static int drm_add_magic(drm_device_t *dev, drm_file_t *priv, drm_magic_t magic) 90static int drm_add_magic(drm_device_t * dev, drm_file_t * priv,
91 drm_magic_t magic)
91{ 92{
92 int hash; 93 int hash;
93 drm_magic_entry_t *entry; 94 drm_magic_entry_t *entry;
94 95
95 DRM_DEBUG("%d\n", magic); 96 DRM_DEBUG("%d\n", magic);
96 97
97 hash = drm_hash_magic(magic); 98 hash = drm_hash_magic(magic);
98 entry = drm_alloc(sizeof(*entry), DRM_MEM_MAGIC); 99 entry = drm_alloc(sizeof(*entry), DRM_MEM_MAGIC);
99 if (!entry) return -ENOMEM; 100 if (!entry)
101 return -ENOMEM;
100 memset(entry, 0, sizeof(*entry)); 102 memset(entry, 0, sizeof(*entry));
101 entry->magic = magic; 103 entry->magic = magic;
102 entry->priv = priv; 104 entry->priv = priv;
103 entry->next = NULL; 105 entry->next = NULL;
104 106
105 down(&dev->struct_sem); 107 down(&dev->struct_sem);
106 if (dev->magiclist[hash].tail) { 108 if (dev->magiclist[hash].tail) {
107 dev->magiclist[hash].tail->next = entry; 109 dev->magiclist[hash].tail->next = entry;
108 dev->magiclist[hash].tail = entry; 110 dev->magiclist[hash].tail = entry;
109 } else { 111 } else {
110 dev->magiclist[hash].head = entry; 112 dev->magiclist[hash].head = entry;
111 dev->magiclist[hash].tail = entry; 113 dev->magiclist[hash].tail = entry;
112 } 114 }
113 up(&dev->struct_sem); 115 up(&dev->struct_sem);
114 116
@@ -117,19 +119,18 @@ static int drm_add_magic(drm_device_t *dev, drm_file_t *priv, drm_magic_t magic)
117 119
118/** 120/**
119 * Remove a magic number. 121 * Remove a magic number.
120 * 122 *
121 * \param dev DRM device. 123 * \param dev DRM device.
122 * \param magic magic number. 124 * \param magic magic number.
123 * 125 *
124 * Searches and unlinks the entry in drm_device::magiclist with the magic 126 * Searches and unlinks the entry in drm_device::magiclist with the magic
125 * number hash key, while holding the drm_device::struct_sem lock. 127 * number hash key, while holding the drm_device::struct_sem lock.
126 */ 128 */
127static int drm_remove_magic(drm_device_t *dev, drm_magic_t magic) 129static int drm_remove_magic(drm_device_t * dev, drm_magic_t magic)
128{ 130{
129 drm_magic_entry_t *prev = NULL; 131 drm_magic_entry_t *prev = NULL;
130 drm_magic_entry_t *pt; 132 drm_magic_entry_t *pt;
131 int hash; 133 int hash;
132
133 134
134 DRM_DEBUG("%d\n", magic); 135 DRM_DEBUG("%d\n", magic);
135 hash = drm_hash_magic(magic); 136 hash = drm_hash_magic(magic);
@@ -171,21 +172,22 @@ static int drm_remove_magic(drm_device_t *dev, drm_magic_t magic)
171 * filp. 172 * filp.
172 */ 173 */
173int drm_getmagic(struct inode *inode, struct file *filp, 174int drm_getmagic(struct inode *inode, struct file *filp,
174 unsigned int cmd, unsigned long arg) 175 unsigned int cmd, unsigned long arg)
175{ 176{
176 static drm_magic_t sequence = 0; 177 static drm_magic_t sequence = 0;
177 static DEFINE_SPINLOCK(lock); 178 static DEFINE_SPINLOCK(lock);
178 drm_file_t *priv = filp->private_data; 179 drm_file_t *priv = filp->private_data;
179 drm_device_t *dev = priv->head->dev; 180 drm_device_t *dev = priv->head->dev;
180 drm_auth_t auth; 181 drm_auth_t auth;
181 182
182 /* Find unique magic */ 183 /* Find unique magic */
183 if (priv->magic) { 184 if (priv->magic) {
184 auth.magic = priv->magic; 185 auth.magic = priv->magic;
185 } else { 186 } else {
186 do { 187 do {
187 spin_lock(&lock); 188 spin_lock(&lock);
188 if (!sequence) ++sequence; /* reserve 0 */ 189 if (!sequence)
190 ++sequence; /* reserve 0 */
189 auth.magic = sequence++; 191 auth.magic = sequence++;
190 spin_unlock(&lock); 192 spin_unlock(&lock);
191 } while (drm_find_file(dev, auth.magic)); 193 } while (drm_find_file(dev, auth.magic));
@@ -194,7 +196,7 @@ int drm_getmagic(struct inode *inode, struct file *filp,
194 } 196 }
195 197
196 DRM_DEBUG("%u\n", auth.magic); 198 DRM_DEBUG("%u\n", auth.magic);
197 if (copy_to_user((drm_auth_t __user *)arg, &auth, sizeof(auth))) 199 if (copy_to_user((drm_auth_t __user *) arg, &auth, sizeof(auth)))
198 return -EFAULT; 200 return -EFAULT;
199 return 0; 201 return 0;
200} 202}
@@ -211,14 +213,14 @@ int drm_getmagic(struct inode *inode, struct file *filp,
211 * Checks if \p filp is associated with the magic number passed in \arg. 213 * Checks if \p filp is associated with the magic number passed in \arg.
212 */ 214 */
213int drm_authmagic(struct inode *inode, struct file *filp, 215int drm_authmagic(struct inode *inode, struct file *filp,
214 unsigned int cmd, unsigned long arg) 216 unsigned int cmd, unsigned long arg)
215{ 217{
216 drm_file_t *priv = filp->private_data; 218 drm_file_t *priv = filp->private_data;
217 drm_device_t *dev = priv->head->dev; 219 drm_device_t *dev = priv->head->dev;
218 drm_auth_t auth; 220 drm_auth_t auth;
219 drm_file_t *file; 221 drm_file_t *file;
220 222
221 if (copy_from_user(&auth, (drm_auth_t __user *)arg, sizeof(auth))) 223 if (copy_from_user(&auth, (drm_auth_t __user *) arg, sizeof(auth)))
222 return -EFAULT; 224 return -EFAULT;
223 DRM_DEBUG("%u\n", auth.magic); 225 DRM_DEBUG("%u\n", auth.magic);
224 if ((file = drm_find_file(dev, auth.magic))) { 226 if ((file = drm_find_file(dev, auth.magic))) {
diff --git a/drivers/char/drm/drm_bufs.c b/drivers/char/drm/drm_bufs.c
index f28e70ae6606..bb989ccea5a0 100644
--- a/drivers/char/drm/drm_bufs.c
+++ b/drivers/char/drm/drm_bufs.c
@@ -1,7 +1,7 @@
1/** 1/**
2 * \file drm_bufs.h 2 * \file drm_bufs.c
3 * Generic buffer template 3 * Generic buffer template
4 * 4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
6 * \author Gareth Hughes <gareth@valinux.com> 6 * \author Gareth Hughes <gareth@valinux.com>
7 */ 7 */
@@ -36,20 +36,22 @@
36#include <linux/vmalloc.h> 36#include <linux/vmalloc.h>
37#include "drmP.h" 37#include "drmP.h"
38 38
39unsigned long drm_get_resource_start(drm_device_t *dev, unsigned int resource) 39unsigned long drm_get_resource_start(drm_device_t * dev, unsigned int resource)
40{ 40{
41 return pci_resource_start(dev->pdev, resource); 41 return pci_resource_start(dev->pdev, resource);
42} 42}
43
43EXPORT_SYMBOL(drm_get_resource_start); 44EXPORT_SYMBOL(drm_get_resource_start);
44 45
45unsigned long drm_get_resource_len(drm_device_t *dev, unsigned int resource) 46unsigned long drm_get_resource_len(drm_device_t * dev, unsigned int resource)
46{ 47{
47 return pci_resource_len(dev->pdev, resource); 48 return pci_resource_len(dev->pdev, resource);
48} 49}
50
49EXPORT_SYMBOL(drm_get_resource_len); 51EXPORT_SYMBOL(drm_get_resource_len);
50 52
51static drm_map_list_t *drm_find_matching_map(drm_device_t *dev, 53static drm_map_list_t *drm_find_matching_map(drm_device_t * dev,
52 drm_local_map_t *map) 54 drm_local_map_t * map)
53{ 55{
54 struct list_head *list; 56 struct list_head *list;
55 57
@@ -71,7 +73,8 @@ static drm_map_list_t *drm_find_matching_map(drm_device_t *dev,
71#define END_RANGE 0x40000000 73#define END_RANGE 0x40000000
72 74
73#ifdef _LP64 75#ifdef _LP64
74static __inline__ unsigned int HandleID(unsigned long lhandle, drm_device_t *dev) 76static __inline__ unsigned int HandleID(unsigned long lhandle,
77 drm_device_t * dev)
75{ 78{
76 static unsigned int map32_handle = START_RANGE; 79 static unsigned int map32_handle = START_RANGE;
77 unsigned int hash; 80 unsigned int hash;
@@ -81,12 +84,12 @@ static __inline__ unsigned int HandleID(unsigned long lhandle, drm_device_t *dev
81 map32_handle += PAGE_SIZE; 84 map32_handle += PAGE_SIZE;
82 if (map32_handle > END_RANGE) 85 if (map32_handle > END_RANGE)
83 map32_handle = START_RANGE; 86 map32_handle = START_RANGE;
84 } else 87 } else
85 hash = lhandle; 88 hash = lhandle;
86 89
87 while (1) { 90 while (1) {
88 drm_map_list_t *_entry; 91 drm_map_list_t *_entry;
89 list_for_each_entry(_entry, &dev->maplist->head,head) { 92 list_for_each_entry(_entry, &dev->maplist->head, head) {
90 if (_entry->user_token == hash) 93 if (_entry->user_token == hash)
91 break; 94 break;
92 } 95 }
@@ -116,14 +119,14 @@ static __inline__ unsigned int HandleID(unsigned long lhandle, drm_device_t *dev
116 */ 119 */
117int drm_addmap_core(drm_device_t * dev, unsigned int offset, 120int drm_addmap_core(drm_device_t * dev, unsigned int offset,
118 unsigned int size, drm_map_type_t type, 121 unsigned int size, drm_map_type_t type,
119 drm_map_flags_t flags, drm_map_list_t **maplist) 122 drm_map_flags_t flags, drm_map_list_t ** maplist)
120{ 123{
121 drm_map_t *map; 124 drm_map_t *map;
122 drm_map_list_t *list; 125 drm_map_list_t *list;
123 drm_dma_handle_t *dmah; 126 drm_dma_handle_t *dmah;
124 127
125 map = drm_alloc( sizeof(*map), DRM_MEM_MAPS ); 128 map = drm_alloc(sizeof(*map), DRM_MEM_MAPS);
126 if ( !map ) 129 if (!map)
127 return -ENOMEM; 130 return -ENOMEM;
128 131
129 map->offset = offset; 132 map->offset = offset;
@@ -135,26 +138,26 @@ int drm_addmap_core(drm_device_t * dev, unsigned int offset,
135 * book keeping information about shared memory to allow for removal 138 * book keeping information about shared memory to allow for removal
136 * when processes fork. 139 * when processes fork.
137 */ 140 */
138 if ( (map->flags & _DRM_REMOVABLE) && map->type != _DRM_SHM ) { 141 if ((map->flags & _DRM_REMOVABLE) && map->type != _DRM_SHM) {
139 drm_free( map, sizeof(*map), DRM_MEM_MAPS ); 142 drm_free(map, sizeof(*map), DRM_MEM_MAPS);
140 return -EINVAL; 143 return -EINVAL;
141 } 144 }
142 DRM_DEBUG( "offset = 0x%08lx, size = 0x%08lx, type = %d\n", 145 DRM_DEBUG("offset = 0x%08lx, size = 0x%08lx, type = %d\n",
143 map->offset, map->size, map->type ); 146 map->offset, map->size, map->type);
144 if ( (map->offset & (~PAGE_MASK)) || (map->size & (~PAGE_MASK)) ) { 147 if ((map->offset & (~PAGE_MASK)) || (map->size & (~PAGE_MASK))) {
145 drm_free( map, sizeof(*map), DRM_MEM_MAPS ); 148 drm_free(map, sizeof(*map), DRM_MEM_MAPS);
146 return -EINVAL; 149 return -EINVAL;
147 } 150 }
148 map->mtrr = -1; 151 map->mtrr = -1;
149 map->handle = NULL; 152 map->handle = NULL;
150 153
151 switch ( map->type ) { 154 switch (map->type) {
152 case _DRM_REGISTERS: 155 case _DRM_REGISTERS:
153 case _DRM_FRAME_BUFFER: 156 case _DRM_FRAME_BUFFER:
154#if !defined(__sparc__) && !defined(__alpha__) && !defined(__ia64__) && !defined(__powerpc64__) && !defined(__x86_64__) 157#if !defined(__sparc__) && !defined(__alpha__) && !defined(__ia64__) && !defined(__powerpc64__) && !defined(__x86_64__)
155 if ( map->offset + map->size < map->offset || 158 if (map->offset + map->size < map->offset ||
156 map->offset < virt_to_phys(high_memory) ) { 159 map->offset < virt_to_phys(high_memory)) {
157 drm_free( map, sizeof(*map), DRM_MEM_MAPS ); 160 drm_free(map, sizeof(*map), DRM_MEM_MAPS);
158 return -EINVAL; 161 return -EINVAL;
159 } 162 }
160#endif 163#endif
@@ -169,8 +172,9 @@ int drm_addmap_core(drm_device_t * dev, unsigned int offset,
169 if (list != NULL) { 172 if (list != NULL) {
170 if (list->map->size != map->size) { 173 if (list->map->size != map->size) {
171 DRM_DEBUG("Matching maps of type %d with " 174 DRM_DEBUG("Matching maps of type %d with "
172 "mismatched sizes, (%ld vs %ld)\n", 175 "mismatched sizes, (%ld vs %ld)\n",
173 map->type, map->size, list->map->size); 176 map->type, map->size,
177 list->map->size);
174 list->map->size = map->size; 178 list->map->size = map->size;
175 } 179 }
176 180
@@ -180,35 +184,33 @@ int drm_addmap_core(drm_device_t * dev, unsigned int offset,
180 } 184 }
181 185
182 if (drm_core_has_MTRR(dev)) { 186 if (drm_core_has_MTRR(dev)) {
183 if ( map->type == _DRM_FRAME_BUFFER || 187 if (map->type == _DRM_FRAME_BUFFER ||
184 (map->flags & _DRM_WRITE_COMBINING) ) { 188 (map->flags & _DRM_WRITE_COMBINING)) {
185 map->mtrr = mtrr_add( map->offset, map->size, 189 map->mtrr = mtrr_add(map->offset, map->size,
186 MTRR_TYPE_WRCOMB, 1 ); 190 MTRR_TYPE_WRCOMB, 1);
187 } 191 }
188 } 192 }
189 if (map->type == _DRM_REGISTERS) 193 if (map->type == _DRM_REGISTERS)
190 map->handle = drm_ioremap( map->offset, map->size, 194 map->handle = drm_ioremap(map->offset, map->size, dev);
191 dev );
192 break; 195 break;
193 196
194 case _DRM_SHM: 197 case _DRM_SHM:
195 map->handle = vmalloc_32(map->size); 198 map->handle = vmalloc_32(map->size);
196 DRM_DEBUG( "%lu %d %p\n", 199 DRM_DEBUG("%lu %d %p\n",
197 map->size, drm_order( map->size ), map->handle ); 200 map->size, drm_order(map->size), map->handle);
198 if ( !map->handle ) { 201 if (!map->handle) {
199 drm_free( map, sizeof(*map), DRM_MEM_MAPS ); 202 drm_free(map, sizeof(*map), DRM_MEM_MAPS);
200 return -ENOMEM; 203 return -ENOMEM;
201 } 204 }
202 map->offset = (unsigned long)map->handle; 205 map->offset = (unsigned long)map->handle;
203 if ( map->flags & _DRM_CONTAINS_LOCK ) { 206 if (map->flags & _DRM_CONTAINS_LOCK) {
204 /* Prevent a 2nd X Server from creating a 2nd lock */ 207 /* Prevent a 2nd X Server from creating a 2nd lock */
205 if (dev->lock.hw_lock != NULL) { 208 if (dev->lock.hw_lock != NULL) {
206 vfree( map->handle ); 209 vfree(map->handle);
207 drm_free( map, sizeof(*map), DRM_MEM_MAPS ); 210 drm_free(map, sizeof(*map), DRM_MEM_MAPS);
208 return -EBUSY; 211 return -EBUSY;
209 } 212 }
210 dev->sigdata.lock = 213 dev->sigdata.lock = dev->lock.hw_lock = map->handle; /* Pointer to lock */
211 dev->lock.hw_lock = map->handle; /* Pointer to lock */
212 } 214 }
213 break; 215 break;
214 case _DRM_AGP: 216 case _DRM_AGP:
@@ -217,7 +219,7 @@ int drm_addmap_core(drm_device_t * dev, unsigned int offset,
217 map->offset += dev->hose->mem_space->start; 219 map->offset += dev->hose->mem_space->start;
218#endif 220#endif
219 map->offset += dev->agp->base; 221 map->offset += dev->agp->base;
220 map->mtrr = dev->agp->agp_mtrr; /* for getmap */ 222 map->mtrr = dev->agp->agp_mtrr; /* for getmap */
221 } 223 }
222 break; 224 break;
223 case _DRM_SCATTER_GATHER: 225 case _DRM_SCATTER_GATHER:
@@ -227,7 +229,7 @@ int drm_addmap_core(drm_device_t * dev, unsigned int offset,
227 } 229 }
228 map->offset += (unsigned long)dev->sg->virtual; 230 map->offset += (unsigned long)dev->sg->virtual;
229 break; 231 break;
230 case _DRM_CONSISTENT: 232 case _DRM_CONSISTENT:
231 /* dma_addr_t is 64bit on i386 with CONFIG_HIGHMEM64G, 233 /* dma_addr_t is 64bit on i386 with CONFIG_HIGHMEM64G,
232 * As we're limiting the address to 2^32-1 (or less), 234 * As we're limiting the address to 2^32-1 (or less),
233 * casting it down to 32 bits is no problem, but we 235 * casting it down to 32 bits is no problem, but we
@@ -242,12 +244,12 @@ int drm_addmap_core(drm_device_t * dev, unsigned int offset,
242 kfree(dmah); 244 kfree(dmah);
243 break; 245 break;
244 default: 246 default:
245 drm_free( map, sizeof(*map), DRM_MEM_MAPS ); 247 drm_free(map, sizeof(*map), DRM_MEM_MAPS);
246 return -EINVAL; 248 return -EINVAL;
247 } 249 }
248 250
249 list = drm_alloc(sizeof(*list), DRM_MEM_MAPS); 251 list = drm_alloc(sizeof(*list), DRM_MEM_MAPS);
250 if(!list) { 252 if (!list) {
251 drm_free(map, sizeof(*map), DRM_MEM_MAPS); 253 drm_free(map, sizeof(*map), DRM_MEM_MAPS);
252 return -EINVAL; 254 return -EINVAL;
253 } 255 }
@@ -258,18 +260,18 @@ int drm_addmap_core(drm_device_t * dev, unsigned int offset,
258 list_add(&list->head, &dev->maplist->head); 260 list_add(&list->head, &dev->maplist->head);
259 /* Assign a 32-bit handle */ 261 /* Assign a 32-bit handle */
260 /* We do it here so that dev->struct_sem protects the increment */ 262 /* We do it here so that dev->struct_sem protects the increment */
261 list->user_token = HandleID(map->type==_DRM_SHM 263 list->user_token = HandleID(map->type == _DRM_SHM
262 ? (unsigned long)map->handle 264 ? (unsigned long)map->handle
263 : map->offset, dev); 265 : map->offset, dev);
264 up(&dev->struct_sem); 266 up(&dev->struct_sem);
265 267
266 *maplist = list; 268 *maplist = list;
267 return 0; 269 return 0;
268} 270}
269 271
270int drm_addmap(drm_device_t *dev, unsigned int offset, 272int drm_addmap(drm_device_t * dev, unsigned int offset,
271 unsigned int size, drm_map_type_t type, 273 unsigned int size, drm_map_type_t type,
272 drm_map_flags_t flags, drm_local_map_t **map_ptr) 274 drm_map_flags_t flags, drm_local_map_t ** map_ptr)
273{ 275{
274 drm_map_list_t *list; 276 drm_map_list_t *list;
275 int rc; 277 int rc;
@@ -279,6 +281,7 @@ int drm_addmap(drm_device_t *dev, unsigned int offset,
279 *map_ptr = list->map; 281 *map_ptr = list->map;
280 return rc; 282 return rc;
281} 283}
284
282EXPORT_SYMBOL(drm_addmap); 285EXPORT_SYMBOL(drm_addmap);
283 286
284int drm_addmap_ioctl(struct inode *inode, struct file *filp, 287int drm_addmap_ioctl(struct inode *inode, struct file *filp,
@@ -294,14 +297,14 @@ int drm_addmap_ioctl(struct inode *inode, struct file *filp,
294 if (!(filp->f_mode & 3)) 297 if (!(filp->f_mode & 3))
295 return -EACCES; /* Require read/write */ 298 return -EACCES; /* Require read/write */
296 299
297 if (copy_from_user(& map, argp, sizeof(map))) { 300 if (copy_from_user(&map, argp, sizeof(map))) {
298 return -EFAULT; 301 return -EFAULT;
299 } 302 }
300 303
301 err = drm_addmap_core(dev, map.offset, map.size, map.type, map.flags, 304 err = drm_addmap_core(dev, map.offset, map.size, map.type, map.flags,
302 &maplist); 305 &maplist);
303 306
304 if (err) 307 if (err)
305 return err; 308 return err;
306 309
307 if (copy_to_user(argp, maplist->map, sizeof(drm_map_t))) 310 if (copy_to_user(argp, maplist->map, sizeof(drm_map_t)))
@@ -311,7 +314,6 @@ int drm_addmap_ioctl(struct inode *inode, struct file *filp,
311 return 0; 314 return 0;
312} 315}
313 316
314
315/** 317/**
316 * Remove a map private from list and deallocate resources if the mapping 318 * Remove a map private from list and deallocate resources if the mapping
317 * isn't in use. 319 * isn't in use.
@@ -328,7 +330,7 @@ int drm_addmap_ioctl(struct inode *inode, struct file *filp,
328 * 330 *
329 * \sa drm_addmap 331 * \sa drm_addmap
330 */ 332 */
331int drm_rmmap_locked(drm_device_t *dev, drm_local_map_t *map) 333int drm_rmmap_locked(drm_device_t * dev, drm_local_map_t * map)
332{ 334{
333 struct list_head *list; 335 struct list_head *list;
334 drm_map_list_t *r_list = NULL; 336 drm_map_list_t *r_list = NULL;
@@ -359,9 +361,8 @@ int drm_rmmap_locked(drm_device_t *dev, drm_local_map_t *map)
359 case _DRM_FRAME_BUFFER: 361 case _DRM_FRAME_BUFFER:
360 if (drm_core_has_MTRR(dev) && map->mtrr >= 0) { 362 if (drm_core_has_MTRR(dev) && map->mtrr >= 0) {
361 int retcode; 363 int retcode;
362 retcode = mtrr_del(map->mtrr, map->offset, 364 retcode = mtrr_del(map->mtrr, map->offset, map->size);
363 map->size); 365 DRM_DEBUG("mtrr_del=%d\n", retcode);
364 DRM_DEBUG ("mtrr_del=%d\n", retcode);
365 } 366 }
366 break; 367 break;
367 case _DRM_SHM: 368 case _DRM_SHM:
@@ -381,9 +382,10 @@ int drm_rmmap_locked(drm_device_t *dev, drm_local_map_t *map)
381 382
382 return 0; 383 return 0;
383} 384}
385
384EXPORT_SYMBOL(drm_rmmap_locked); 386EXPORT_SYMBOL(drm_rmmap_locked);
385 387
386int drm_rmmap(drm_device_t *dev, drm_local_map_t *map) 388int drm_rmmap(drm_device_t * dev, drm_local_map_t * map)
387{ 389{
388 int ret; 390 int ret;
389 391
@@ -393,6 +395,7 @@ int drm_rmmap(drm_device_t *dev, drm_local_map_t *map)
393 395
394 return ret; 396 return ret;
395} 397}
398
396EXPORT_SYMBOL(drm_rmmap); 399EXPORT_SYMBOL(drm_rmmap);
397 400
398/* The rmmap ioctl appears to be unnecessary. All mappings are torn down on 401/* The rmmap ioctl appears to be unnecessary. All mappings are torn down on
@@ -414,7 +417,7 @@ int drm_rmmap_ioctl(struct inode *inode, struct file *filp,
414 struct list_head *list; 417 struct list_head *list;
415 int ret; 418 int ret;
416 419
417 if (copy_from_user(&request, (drm_map_t __user *)arg, sizeof(request))) { 420 if (copy_from_user(&request, (drm_map_t __user *) arg, sizeof(request))) {
418 return -EFAULT; 421 return -EFAULT;
419 } 422 }
420 423
@@ -423,7 +426,7 @@ int drm_rmmap_ioctl(struct inode *inode, struct file *filp,
423 drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head); 426 drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head);
424 427
425 if (r_list->map && 428 if (r_list->map &&
426 r_list->user_token == (unsigned long) request.handle && 429 r_list->user_token == (unsigned long)request.handle &&
427 r_list->map->flags & _DRM_REMOVABLE) { 430 r_list->map->flags & _DRM_REMOVABLE) {
428 map = r_list->map; 431 map = r_list->map;
429 break; 432 break;
@@ -462,7 +465,7 @@ int drm_rmmap_ioctl(struct inode *inode, struct file *filp,
462 * 465 *
463 * Frees any pages and buffers associated with the given entry. 466 * Frees any pages and buffers associated with the given entry.
464 */ 467 */
465static void drm_cleanup_buf_error(drm_device_t *dev, drm_buf_entry_t *entry) 468static void drm_cleanup_buf_error(drm_device_t * dev, drm_buf_entry_t * entry)
466{ 469{
467 int i; 470 int i;
468 471
@@ -470,30 +473,27 @@ static void drm_cleanup_buf_error(drm_device_t *dev, drm_buf_entry_t *entry)
470 for (i = 0; i < entry->seg_count; i++) { 473 for (i = 0; i < entry->seg_count; i++) {
471 if (entry->seglist[i]) { 474 if (entry->seglist[i]) {
472 drm_free_pages(entry->seglist[i], 475 drm_free_pages(entry->seglist[i],
473 entry->page_order, 476 entry->page_order, DRM_MEM_DMA);
474 DRM_MEM_DMA);
475 } 477 }
476 } 478 }
477 drm_free(entry->seglist, 479 drm_free(entry->seglist,
478 entry->seg_count * 480 entry->seg_count *
479 sizeof(*entry->seglist), 481 sizeof(*entry->seglist), DRM_MEM_SEGS);
480 DRM_MEM_SEGS);
481 482
482 entry->seg_count = 0; 483 entry->seg_count = 0;
483 } 484 }
484 485
485 if (entry->buf_count) { 486 if (entry->buf_count) {
486 for (i = 0; i < entry->buf_count; i++) { 487 for (i = 0; i < entry->buf_count; i++) {
487 if (entry->buflist[i].dev_private) { 488 if (entry->buflist[i].dev_private) {
488 drm_free(entry->buflist[i].dev_private, 489 drm_free(entry->buflist[i].dev_private,
489 entry->buflist[i].dev_priv_size, 490 entry->buflist[i].dev_priv_size,
490 DRM_MEM_BUFS); 491 DRM_MEM_BUFS);
491 } 492 }
492 } 493 }
493 drm_free(entry->buflist, 494 drm_free(entry->buflist,
494 entry->buf_count * 495 entry->buf_count *
495 sizeof(*entry->buflist), 496 sizeof(*entry->buflist), DRM_MEM_BUFS);
496 DRM_MEM_BUFS);
497 497
498 entry->buf_count = 0; 498 entry->buf_count = 0;
499 } 499 }
@@ -506,12 +506,12 @@ static void drm_cleanup_buf_error(drm_device_t *dev, drm_buf_entry_t *entry)
506 * \param dev drm_device_t to which the buffers are to be added. 506 * \param dev drm_device_t to which the buffers are to be added.
507 * \param request pointer to a drm_buf_desc_t describing the request. 507 * \param request pointer to a drm_buf_desc_t describing the request.
508 * \return zero on success or a negative number on failure. 508 * \return zero on success or a negative number on failure.
509 * 509 *
510 * After some sanity checks creates a drm_buf structure for each buffer and 510 * After some sanity checks creates a drm_buf structure for each buffer and
511 * reallocates the buffer list of the same size order to accommodate the new 511 * reallocates the buffer list of the same size order to accommodate the new
512 * buffers. 512 * buffers.
513 */ 513 */
514int drm_addbufs_agp(drm_device_t *dev, drm_buf_desc_t *request) 514int drm_addbufs_agp(drm_device_t * dev, drm_buf_desc_t * request)
515{ 515{
516 drm_device_dma_t *dma = dev->dma; 516 drm_device_dma_t *dma = dev->dma;
517 drm_buf_entry_t *entry; 517 drm_buf_entry_t *entry;
@@ -528,144 +528,145 @@ int drm_addbufs_agp(drm_device_t *dev, drm_buf_desc_t *request)
528 int i; 528 int i;
529 drm_buf_t **temp_buflist; 529 drm_buf_t **temp_buflist;
530 530
531 if ( !dma ) return -EINVAL; 531 if (!dma)
532 return -EINVAL;
532 533
533 count = request->count; 534 count = request->count;
534 order = drm_order(request->size); 535 order = drm_order(request->size);
535 size = 1 << order; 536 size = 1 << order;
536 537
537 alignment = (request->flags & _DRM_PAGE_ALIGN) 538 alignment = (request->flags & _DRM_PAGE_ALIGN)
538 ? PAGE_ALIGN(size) : size; 539 ? PAGE_ALIGN(size) : size;
539 page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0; 540 page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0;
540 total = PAGE_SIZE << page_order; 541 total = PAGE_SIZE << page_order;
541 542
542 byte_count = 0; 543 byte_count = 0;
543 agp_offset = dev->agp->base + request->agp_start; 544 agp_offset = dev->agp->base + request->agp_start;
544 545
545 DRM_DEBUG( "count: %d\n", count ); 546 DRM_DEBUG("count: %d\n", count);
546 DRM_DEBUG( "order: %d\n", order ); 547 DRM_DEBUG("order: %d\n", order);
547 DRM_DEBUG( "size: %d\n", size ); 548 DRM_DEBUG("size: %d\n", size);
548 DRM_DEBUG( "agp_offset: %lu\n", agp_offset ); 549 DRM_DEBUG("agp_offset: %lu\n", agp_offset);
549 DRM_DEBUG( "alignment: %d\n", alignment ); 550 DRM_DEBUG("alignment: %d\n", alignment);
550 DRM_DEBUG( "page_order: %d\n", page_order ); 551 DRM_DEBUG("page_order: %d\n", page_order);
551 DRM_DEBUG( "total: %d\n", total ); 552 DRM_DEBUG("total: %d\n", total);
552 553
553 if ( order < DRM_MIN_ORDER || order > DRM_MAX_ORDER ) return -EINVAL; 554 if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER)
554 if ( dev->queue_count ) return -EBUSY; /* Not while in use */ 555 return -EINVAL;
556 if (dev->queue_count)
557 return -EBUSY; /* Not while in use */
555 558
556 spin_lock( &dev->count_lock ); 559 spin_lock(&dev->count_lock);
557 if ( dev->buf_use ) { 560 if (dev->buf_use) {
558 spin_unlock( &dev->count_lock ); 561 spin_unlock(&dev->count_lock);
559 return -EBUSY; 562 return -EBUSY;
560 } 563 }
561 atomic_inc( &dev->buf_alloc ); 564 atomic_inc(&dev->buf_alloc);
562 spin_unlock( &dev->count_lock ); 565 spin_unlock(&dev->count_lock);
563 566
564 down( &dev->struct_sem ); 567 down(&dev->struct_sem);
565 entry = &dma->bufs[order]; 568 entry = &dma->bufs[order];
566 if ( entry->buf_count ) { 569 if (entry->buf_count) {
567 up( &dev->struct_sem ); 570 up(&dev->struct_sem);
568 atomic_dec( &dev->buf_alloc ); 571 atomic_dec(&dev->buf_alloc);
569 return -ENOMEM; /* May only call once for each order */ 572 return -ENOMEM; /* May only call once for each order */
570 } 573 }
571 574
572 if (count < 0 || count > 4096) { 575 if (count < 0 || count > 4096) {
573 up( &dev->struct_sem ); 576 up(&dev->struct_sem);
574 atomic_dec( &dev->buf_alloc ); 577 atomic_dec(&dev->buf_alloc);
575 return -EINVAL; 578 return -EINVAL;
576 } 579 }
577 580
578 entry->buflist = drm_alloc( count * sizeof(*entry->buflist), 581 entry->buflist = drm_alloc(count * sizeof(*entry->buflist),
579 DRM_MEM_BUFS ); 582 DRM_MEM_BUFS);
580 if ( !entry->buflist ) { 583 if (!entry->buflist) {
581 up( &dev->struct_sem ); 584 up(&dev->struct_sem);
582 atomic_dec( &dev->buf_alloc ); 585 atomic_dec(&dev->buf_alloc);
583 return -ENOMEM; 586 return -ENOMEM;
584 } 587 }
585 memset( entry->buflist, 0, count * sizeof(*entry->buflist) ); 588 memset(entry->buflist, 0, count * sizeof(*entry->buflist));
586 589
587 entry->buf_size = size; 590 entry->buf_size = size;
588 entry->page_order = page_order; 591 entry->page_order = page_order;
589 592
590 offset = 0; 593 offset = 0;
591 594
592 while ( entry->buf_count < count ) { 595 while (entry->buf_count < count) {
593 buf = &entry->buflist[entry->buf_count]; 596 buf = &entry->buflist[entry->buf_count];
594 buf->idx = dma->buf_count + entry->buf_count; 597 buf->idx = dma->buf_count + entry->buf_count;
595 buf->total = alignment; 598 buf->total = alignment;
596 buf->order = order; 599 buf->order = order;
597 buf->used = 0; 600 buf->used = 0;
598 601
599 buf->offset = (dma->byte_count + offset); 602 buf->offset = (dma->byte_count + offset);
600 buf->bus_address = agp_offset + offset; 603 buf->bus_address = agp_offset + offset;
601 buf->address = (void *)(agp_offset + offset); 604 buf->address = (void *)(agp_offset + offset);
602 buf->next = NULL; 605 buf->next = NULL;
603 buf->waiting = 0; 606 buf->waiting = 0;
604 buf->pending = 0; 607 buf->pending = 0;
605 init_waitqueue_head( &buf->dma_wait ); 608 init_waitqueue_head(&buf->dma_wait);
606 buf->filp = NULL; 609 buf->filp = NULL;
607 610
608 buf->dev_priv_size = dev->driver->dev_priv_size; 611 buf->dev_priv_size = dev->driver->dev_priv_size;
609 buf->dev_private = drm_alloc( buf->dev_priv_size, 612 buf->dev_private = drm_alloc(buf->dev_priv_size, DRM_MEM_BUFS);
610 DRM_MEM_BUFS ); 613 if (!buf->dev_private) {
611 if(!buf->dev_private) {
612 /* Set count correctly so we free the proper amount. */ 614 /* Set count correctly so we free the proper amount. */
613 entry->buf_count = count; 615 entry->buf_count = count;
614 drm_cleanup_buf_error(dev,entry); 616 drm_cleanup_buf_error(dev, entry);
615 up( &dev->struct_sem ); 617 up(&dev->struct_sem);
616 atomic_dec( &dev->buf_alloc ); 618 atomic_dec(&dev->buf_alloc);
617 return -ENOMEM; 619 return -ENOMEM;
618 } 620 }
619 memset( buf->dev_private, 0, buf->dev_priv_size ); 621 memset(buf->dev_private, 0, buf->dev_priv_size);
620 622
621 DRM_DEBUG( "buffer %d @ %p\n", 623 DRM_DEBUG("buffer %d @ %p\n", entry->buf_count, buf->address);
622 entry->buf_count, buf->address );
623 624
624 offset += alignment; 625 offset += alignment;
625 entry->buf_count++; 626 entry->buf_count++;
626 byte_count += PAGE_SIZE << page_order; 627 byte_count += PAGE_SIZE << page_order;
627 } 628 }
628 629
629 DRM_DEBUG( "byte_count: %d\n", byte_count ); 630 DRM_DEBUG("byte_count: %d\n", byte_count);
630 631
631 temp_buflist = drm_realloc( dma->buflist, 632 temp_buflist = drm_realloc(dma->buflist,
632 dma->buf_count * sizeof(*dma->buflist), 633 dma->buf_count * sizeof(*dma->buflist),
633 (dma->buf_count + entry->buf_count) 634 (dma->buf_count + entry->buf_count)
634 * sizeof(*dma->buflist), 635 * sizeof(*dma->buflist), DRM_MEM_BUFS);
635 DRM_MEM_BUFS ); 636 if (!temp_buflist) {
636 if(!temp_buflist) {
637 /* Free the entry because it isn't valid */ 637 /* Free the entry because it isn't valid */
638 drm_cleanup_buf_error(dev,entry); 638 drm_cleanup_buf_error(dev, entry);
639 up( &dev->struct_sem ); 639 up(&dev->struct_sem);
640 atomic_dec( &dev->buf_alloc ); 640 atomic_dec(&dev->buf_alloc);
641 return -ENOMEM; 641 return -ENOMEM;
642 } 642 }
643 dma->buflist = temp_buflist; 643 dma->buflist = temp_buflist;
644 644
645 for ( i = 0 ; i < entry->buf_count ; i++ ) { 645 for (i = 0; i < entry->buf_count; i++) {
646 dma->buflist[i + dma->buf_count] = &entry->buflist[i]; 646 dma->buflist[i + dma->buf_count] = &entry->buflist[i];
647 } 647 }
648 648
649 dma->buf_count += entry->buf_count; 649 dma->buf_count += entry->buf_count;
650 dma->byte_count += byte_count; 650 dma->byte_count += byte_count;
651 651
652 DRM_DEBUG( "dma->buf_count : %d\n", dma->buf_count ); 652 DRM_DEBUG("dma->buf_count : %d\n", dma->buf_count);
653 DRM_DEBUG( "entry->buf_count : %d\n", entry->buf_count ); 653 DRM_DEBUG("entry->buf_count : %d\n", entry->buf_count);
654 654
655 up( &dev->struct_sem ); 655 up(&dev->struct_sem);
656 656
657 request->count = entry->buf_count; 657 request->count = entry->buf_count;
658 request->size = size; 658 request->size = size;
659 659
660 dma->flags = _DRM_DMA_USE_AGP; 660 dma->flags = _DRM_DMA_USE_AGP;
661 661
662 atomic_dec( &dev->buf_alloc ); 662 atomic_dec(&dev->buf_alloc);
663 return 0; 663 return 0;
664} 664}
665
665EXPORT_SYMBOL(drm_addbufs_agp); 666EXPORT_SYMBOL(drm_addbufs_agp);
666#endif /* __OS_HAS_AGP */ 667#endif /* __OS_HAS_AGP */
667 668
668int drm_addbufs_pci(drm_device_t *dev, drm_buf_desc_t *request) 669int drm_addbufs_pci(drm_device_t * dev, drm_buf_desc_t * request)
669{ 670{
670 drm_device_dma_t *dma = dev->dma; 671 drm_device_dma_t *dma = dev->dma;
671 int count; 672 int count;
@@ -684,178 +685,174 @@ int drm_addbufs_pci(drm_device_t *dev, drm_buf_desc_t *request)
684 unsigned long *temp_pagelist; 685 unsigned long *temp_pagelist;
685 drm_buf_t **temp_buflist; 686 drm_buf_t **temp_buflist;
686 687
687 if (!drm_core_check_feature(dev, DRIVER_PCI_DMA)) return -EINVAL; 688 if (!drm_core_check_feature(dev, DRIVER_PCI_DMA))
688 if ( !dma ) return -EINVAL; 689 return -EINVAL;
690 if (!dma)
691 return -EINVAL;
689 692
690 count = request->count; 693 count = request->count;
691 order = drm_order(request->size); 694 order = drm_order(request->size);
692 size = 1 << order; 695 size = 1 << order;
693 696
694 DRM_DEBUG( "count=%d, size=%d (%d), order=%d, queue_count=%d\n", 697 DRM_DEBUG("count=%d, size=%d (%d), order=%d, queue_count=%d\n",
695 request->count, request->size, size, 698 request->count, request->size, size, order, dev->queue_count);
696 order, dev->queue_count );
697 699
698 if ( order < DRM_MIN_ORDER || order > DRM_MAX_ORDER ) return -EINVAL; 700 if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER)
699 if ( dev->queue_count ) return -EBUSY; /* Not while in use */ 701 return -EINVAL;
702 if (dev->queue_count)
703 return -EBUSY; /* Not while in use */
700 704
701 alignment = (request->flags & _DRM_PAGE_ALIGN) 705 alignment = (request->flags & _DRM_PAGE_ALIGN)
702 ? PAGE_ALIGN(size) : size; 706 ? PAGE_ALIGN(size) : size;
703 page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0; 707 page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0;
704 total = PAGE_SIZE << page_order; 708 total = PAGE_SIZE << page_order;
705 709
706 spin_lock( &dev->count_lock ); 710 spin_lock(&dev->count_lock);
707 if ( dev->buf_use ) { 711 if (dev->buf_use) {
708 spin_unlock( &dev->count_lock ); 712 spin_unlock(&dev->count_lock);
709 return -EBUSY; 713 return -EBUSY;
710 } 714 }
711 atomic_inc( &dev->buf_alloc ); 715 atomic_inc(&dev->buf_alloc);
712 spin_unlock( &dev->count_lock ); 716 spin_unlock(&dev->count_lock);
713 717
714 down( &dev->struct_sem ); 718 down(&dev->struct_sem);
715 entry = &dma->bufs[order]; 719 entry = &dma->bufs[order];
716 if ( entry->buf_count ) { 720 if (entry->buf_count) {
717 up( &dev->struct_sem ); 721 up(&dev->struct_sem);
718 atomic_dec( &dev->buf_alloc ); 722 atomic_dec(&dev->buf_alloc);
719 return -ENOMEM; /* May only call once for each order */ 723 return -ENOMEM; /* May only call once for each order */
720 } 724 }
721 725
722 if (count < 0 || count > 4096) { 726 if (count < 0 || count > 4096) {
723 up( &dev->struct_sem ); 727 up(&dev->struct_sem);
724 atomic_dec( &dev->buf_alloc ); 728 atomic_dec(&dev->buf_alloc);
725 return -EINVAL; 729 return -EINVAL;
726 } 730 }
727 731
728 entry->buflist = drm_alloc( count * sizeof(*entry->buflist), 732 entry->buflist = drm_alloc(count * sizeof(*entry->buflist),
729 DRM_MEM_BUFS ); 733 DRM_MEM_BUFS);
730 if ( !entry->buflist ) { 734 if (!entry->buflist) {
731 up( &dev->struct_sem ); 735 up(&dev->struct_sem);
732 atomic_dec( &dev->buf_alloc ); 736 atomic_dec(&dev->buf_alloc);
733 return -ENOMEM; 737 return -ENOMEM;
734 } 738 }
735 memset( entry->buflist, 0, count * sizeof(*entry->buflist) ); 739 memset(entry->buflist, 0, count * sizeof(*entry->buflist));
736 740
737 entry->seglist = drm_alloc( count * sizeof(*entry->seglist), 741 entry->seglist = drm_alloc(count * sizeof(*entry->seglist),
738 DRM_MEM_SEGS ); 742 DRM_MEM_SEGS);
739 if ( !entry->seglist ) { 743 if (!entry->seglist) {
740 drm_free( entry->buflist, 744 drm_free(entry->buflist,
741 count * sizeof(*entry->buflist), 745 count * sizeof(*entry->buflist), DRM_MEM_BUFS);
742 DRM_MEM_BUFS ); 746 up(&dev->struct_sem);
743 up( &dev->struct_sem ); 747 atomic_dec(&dev->buf_alloc);
744 atomic_dec( &dev->buf_alloc );
745 return -ENOMEM; 748 return -ENOMEM;
746 } 749 }
747 memset( entry->seglist, 0, count * sizeof(*entry->seglist) ); 750 memset(entry->seglist, 0, count * sizeof(*entry->seglist));
748 751
749 /* Keep the original pagelist until we know all the allocations 752 /* Keep the original pagelist until we know all the allocations
750 * have succeeded 753 * have succeeded
751 */ 754 */
752 temp_pagelist = drm_alloc( (dma->page_count + (count << page_order)) 755 temp_pagelist = drm_alloc((dma->page_count + (count << page_order))
753 * sizeof(*dma->pagelist), 756 * sizeof(*dma->pagelist), DRM_MEM_PAGES);
754 DRM_MEM_PAGES );
755 if (!temp_pagelist) { 757 if (!temp_pagelist) {
756 drm_free( entry->buflist, 758 drm_free(entry->buflist,
757 count * sizeof(*entry->buflist), 759 count * sizeof(*entry->buflist), DRM_MEM_BUFS);
758 DRM_MEM_BUFS ); 760 drm_free(entry->seglist,
759 drm_free( entry->seglist, 761 count * sizeof(*entry->seglist), DRM_MEM_SEGS);
760 count * sizeof(*entry->seglist), 762 up(&dev->struct_sem);
761 DRM_MEM_SEGS ); 763 atomic_dec(&dev->buf_alloc);
762 up( &dev->struct_sem );
763 atomic_dec( &dev->buf_alloc );
764 return -ENOMEM; 764 return -ENOMEM;
765 } 765 }
766 memcpy(temp_pagelist, 766 memcpy(temp_pagelist,
767 dma->pagelist, 767 dma->pagelist, dma->page_count * sizeof(*dma->pagelist));
768 dma->page_count * sizeof(*dma->pagelist)); 768 DRM_DEBUG("pagelist: %d entries\n",
769 DRM_DEBUG( "pagelist: %d entries\n", 769 dma->page_count + (count << page_order));
770 dma->page_count + (count << page_order) );
771 770
772 entry->buf_size = size; 771 entry->buf_size = size;
773 entry->page_order = page_order; 772 entry->page_order = page_order;
774 byte_count = 0; 773 byte_count = 0;
775 page_count = 0; 774 page_count = 0;
776 775
777 while ( entry->buf_count < count ) { 776 while (entry->buf_count < count) {
778 page = drm_alloc_pages( page_order, DRM_MEM_DMA ); 777 page = drm_alloc_pages(page_order, DRM_MEM_DMA);
779 if ( !page ) { 778 if (!page) {
780 /* Set count correctly so we free the proper amount. */ 779 /* Set count correctly so we free the proper amount. */
781 entry->buf_count = count; 780 entry->buf_count = count;
782 entry->seg_count = count; 781 entry->seg_count = count;
783 drm_cleanup_buf_error(dev, entry); 782 drm_cleanup_buf_error(dev, entry);
784 drm_free( temp_pagelist, 783 drm_free(temp_pagelist,
785 (dma->page_count + (count << page_order)) 784 (dma->page_count + (count << page_order))
786 * sizeof(*dma->pagelist), 785 * sizeof(*dma->pagelist), DRM_MEM_PAGES);
787 DRM_MEM_PAGES ); 786 up(&dev->struct_sem);
788 up( &dev->struct_sem ); 787 atomic_dec(&dev->buf_alloc);
789 atomic_dec( &dev->buf_alloc );
790 return -ENOMEM; 788 return -ENOMEM;
791 } 789 }
792 entry->seglist[entry->seg_count++] = page; 790 entry->seglist[entry->seg_count++] = page;
793 for ( i = 0 ; i < (1 << page_order) ; i++ ) { 791 for (i = 0; i < (1 << page_order); i++) {
794 DRM_DEBUG( "page %d @ 0x%08lx\n", 792 DRM_DEBUG("page %d @ 0x%08lx\n",
795 dma->page_count + page_count, 793 dma->page_count + page_count,
796 page + PAGE_SIZE * i ); 794 page + PAGE_SIZE * i);
797 temp_pagelist[dma->page_count + page_count++] 795 temp_pagelist[dma->page_count + page_count++]
798 = page + PAGE_SIZE * i; 796 = page + PAGE_SIZE * i;
799 } 797 }
800 for ( offset = 0 ; 798 for (offset = 0;
801 offset + size <= total && entry->buf_count < count ; 799 offset + size <= total && entry->buf_count < count;
802 offset += alignment, ++entry->buf_count ) { 800 offset += alignment, ++entry->buf_count) {
803 buf = &entry->buflist[entry->buf_count]; 801 buf = &entry->buflist[entry->buf_count];
804 buf->idx = dma->buf_count + entry->buf_count; 802 buf->idx = dma->buf_count + entry->buf_count;
805 buf->total = alignment; 803 buf->total = alignment;
806 buf->order = order; 804 buf->order = order;
807 buf->used = 0; 805 buf->used = 0;
808 buf->offset = (dma->byte_count + byte_count + offset); 806 buf->offset = (dma->byte_count + byte_count + offset);
809 buf->address = (void *)(page + offset); 807 buf->address = (void *)(page + offset);
810 buf->next = NULL; 808 buf->next = NULL;
811 buf->waiting = 0; 809 buf->waiting = 0;
812 buf->pending = 0; 810 buf->pending = 0;
813 init_waitqueue_head( &buf->dma_wait ); 811 init_waitqueue_head(&buf->dma_wait);
814 buf->filp = NULL; 812 buf->filp = NULL;
815 813
816 buf->dev_priv_size = dev->driver->dev_priv_size; 814 buf->dev_priv_size = dev->driver->dev_priv_size;
817 buf->dev_private = drm_alloc( buf->dev_priv_size, 815 buf->dev_private = drm_alloc(buf->dev_priv_size,
818 DRM_MEM_BUFS ); 816 DRM_MEM_BUFS);
819 if(!buf->dev_private) { 817 if (!buf->dev_private) {
820 /* Set count correctly so we free the proper amount. */ 818 /* Set count correctly so we free the proper amount. */
821 entry->buf_count = count; 819 entry->buf_count = count;
822 entry->seg_count = count; 820 entry->seg_count = count;
823 drm_cleanup_buf_error(dev,entry); 821 drm_cleanup_buf_error(dev, entry);
824 drm_free( temp_pagelist, 822 drm_free(temp_pagelist,
825 (dma->page_count + (count << page_order)) 823 (dma->page_count +
826 * sizeof(*dma->pagelist), 824 (count << page_order))
827 DRM_MEM_PAGES ); 825 * sizeof(*dma->pagelist),
828 up( &dev->struct_sem ); 826 DRM_MEM_PAGES);
829 atomic_dec( &dev->buf_alloc ); 827 up(&dev->struct_sem);
828 atomic_dec(&dev->buf_alloc);
830 return -ENOMEM; 829 return -ENOMEM;
831 } 830 }
832 memset( buf->dev_private, 0, buf->dev_priv_size ); 831 memset(buf->dev_private, 0, buf->dev_priv_size);
833 832
834 DRM_DEBUG( "buffer %d @ %p\n", 833 DRM_DEBUG("buffer %d @ %p\n",
835 entry->buf_count, buf->address ); 834 entry->buf_count, buf->address);
836 } 835 }
837 byte_count += PAGE_SIZE << page_order; 836 byte_count += PAGE_SIZE << page_order;
838 } 837 }
839 838
840 temp_buflist = drm_realloc( dma->buflist, 839 temp_buflist = drm_realloc(dma->buflist,
841 dma->buf_count * sizeof(*dma->buflist), 840 dma->buf_count * sizeof(*dma->buflist),
842 (dma->buf_count + entry->buf_count) 841 (dma->buf_count + entry->buf_count)
843 * sizeof(*dma->buflist), 842 * sizeof(*dma->buflist), DRM_MEM_BUFS);
844 DRM_MEM_BUFS );
845 if (!temp_buflist) { 843 if (!temp_buflist) {
846 /* Free the entry because it isn't valid */ 844 /* Free the entry because it isn't valid */
847 drm_cleanup_buf_error(dev,entry); 845 drm_cleanup_buf_error(dev, entry);
848 drm_free( temp_pagelist, 846 drm_free(temp_pagelist,
849 (dma->page_count + (count << page_order)) 847 (dma->page_count + (count << page_order))
850 * sizeof(*dma->pagelist), 848 * sizeof(*dma->pagelist), DRM_MEM_PAGES);
851 DRM_MEM_PAGES ); 849 up(&dev->struct_sem);
852 up( &dev->struct_sem ); 850 atomic_dec(&dev->buf_alloc);
853 atomic_dec( &dev->buf_alloc );
854 return -ENOMEM; 851 return -ENOMEM;
855 } 852 }
856 dma->buflist = temp_buflist; 853 dma->buflist = temp_buflist;
857 854
858 for ( i = 0 ; i < entry->buf_count ; i++ ) { 855 for (i = 0; i < entry->buf_count; i++) {
859 dma->buflist[i + dma->buf_count] = &entry->buflist[i]; 856 dma->buflist[i + dma->buf_count] = &entry->buflist[i];
860 } 857 }
861 858
@@ -864,8 +861,8 @@ int drm_addbufs_pci(drm_device_t *dev, drm_buf_desc_t *request)
864 */ 861 */
865 if (dma->page_count) { 862 if (dma->page_count) {
866 drm_free(dma->pagelist, 863 drm_free(dma->pagelist,
867 dma->page_count * sizeof(*dma->pagelist), 864 dma->page_count * sizeof(*dma->pagelist),
868 DRM_MEM_PAGES); 865 DRM_MEM_PAGES);
869 } 866 }
870 dma->pagelist = temp_pagelist; 867 dma->pagelist = temp_pagelist;
871 868
@@ -874,18 +871,19 @@ int drm_addbufs_pci(drm_device_t *dev, drm_buf_desc_t *request)
874 dma->page_count += entry->seg_count << page_order; 871 dma->page_count += entry->seg_count << page_order;
875 dma->byte_count += PAGE_SIZE * (entry->seg_count << page_order); 872 dma->byte_count += PAGE_SIZE * (entry->seg_count << page_order);
876 873
877 up( &dev->struct_sem ); 874 up(&dev->struct_sem);
878 875
879 request->count = entry->buf_count; 876 request->count = entry->buf_count;
880 request->size = size; 877 request->size = size;
881 878
882 atomic_dec( &dev->buf_alloc ); 879 atomic_dec(&dev->buf_alloc);
883 return 0; 880 return 0;
884 881
885} 882}
883
886EXPORT_SYMBOL(drm_addbufs_pci); 884EXPORT_SYMBOL(drm_addbufs_pci);
887 885
888static int drm_addbufs_sg(drm_device_t *dev, drm_buf_desc_t *request) 886static int drm_addbufs_sg(drm_device_t * dev, drm_buf_desc_t * request)
889{ 887{
890 drm_device_dma_t *dma = dev->dma; 888 drm_device_dma_t *dma = dev->dma;
891 drm_buf_entry_t *entry; 889 drm_buf_entry_t *entry;
@@ -902,146 +900,147 @@ static int drm_addbufs_sg(drm_device_t *dev, drm_buf_desc_t *request)
902 int i; 900 int i;
903 drm_buf_t **temp_buflist; 901 drm_buf_t **temp_buflist;
904 902
905 if (!drm_core_check_feature(dev, DRIVER_SG)) return -EINVAL; 903 if (!drm_core_check_feature(dev, DRIVER_SG))
906 904 return -EINVAL;
907 if ( !dma ) return -EINVAL; 905
906 if (!dma)
907 return -EINVAL;
908 908
909 count = request->count; 909 count = request->count;
910 order = drm_order(request->size); 910 order = drm_order(request->size);
911 size = 1 << order; 911 size = 1 << order;
912 912
913 alignment = (request->flags & _DRM_PAGE_ALIGN) 913 alignment = (request->flags & _DRM_PAGE_ALIGN)
914 ? PAGE_ALIGN(size) : size; 914 ? PAGE_ALIGN(size) : size;
915 page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0; 915 page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0;
916 total = PAGE_SIZE << page_order; 916 total = PAGE_SIZE << page_order;
917 917
918 byte_count = 0; 918 byte_count = 0;
919 agp_offset = request->agp_start; 919 agp_offset = request->agp_start;
920 920
921 DRM_DEBUG( "count: %d\n", count ); 921 DRM_DEBUG("count: %d\n", count);
922 DRM_DEBUG( "order: %d\n", order ); 922 DRM_DEBUG("order: %d\n", order);
923 DRM_DEBUG( "size: %d\n", size ); 923 DRM_DEBUG("size: %d\n", size);
924 DRM_DEBUG( "agp_offset: %lu\n", agp_offset ); 924 DRM_DEBUG("agp_offset: %lu\n", agp_offset);
925 DRM_DEBUG( "alignment: %d\n", alignment ); 925 DRM_DEBUG("alignment: %d\n", alignment);
926 DRM_DEBUG( "page_order: %d\n", page_order ); 926 DRM_DEBUG("page_order: %d\n", page_order);
927 DRM_DEBUG( "total: %d\n", total ); 927 DRM_DEBUG("total: %d\n", total);
928 928
929 if ( order < DRM_MIN_ORDER || order > DRM_MAX_ORDER ) return -EINVAL; 929 if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER)
930 if ( dev->queue_count ) return -EBUSY; /* Not while in use */ 930 return -EINVAL;
931 if (dev->queue_count)
932 return -EBUSY; /* Not while in use */
931 933
932 spin_lock( &dev->count_lock ); 934 spin_lock(&dev->count_lock);
933 if ( dev->buf_use ) { 935 if (dev->buf_use) {
934 spin_unlock( &dev->count_lock ); 936 spin_unlock(&dev->count_lock);
935 return -EBUSY; 937 return -EBUSY;
936 } 938 }
937 atomic_inc( &dev->buf_alloc ); 939 atomic_inc(&dev->buf_alloc);
938 spin_unlock( &dev->count_lock ); 940 spin_unlock(&dev->count_lock);
939 941
940 down( &dev->struct_sem ); 942 down(&dev->struct_sem);
941 entry = &dma->bufs[order]; 943 entry = &dma->bufs[order];
942 if ( entry->buf_count ) { 944 if (entry->buf_count) {
943 up( &dev->struct_sem ); 945 up(&dev->struct_sem);
944 atomic_dec( &dev->buf_alloc ); 946 atomic_dec(&dev->buf_alloc);
945 return -ENOMEM; /* May only call once for each order */ 947 return -ENOMEM; /* May only call once for each order */
946 } 948 }
947 949
948 if (count < 0 || count > 4096) { 950 if (count < 0 || count > 4096) {
949 up( &dev->struct_sem ); 951 up(&dev->struct_sem);
950 atomic_dec( &dev->buf_alloc ); 952 atomic_dec(&dev->buf_alloc);
951 return -EINVAL; 953 return -EINVAL;
952 } 954 }
953 955
954 entry->buflist = drm_alloc( count * sizeof(*entry->buflist), 956 entry->buflist = drm_alloc(count * sizeof(*entry->buflist),
955 DRM_MEM_BUFS ); 957 DRM_MEM_BUFS);
956 if ( !entry->buflist ) { 958 if (!entry->buflist) {
957 up( &dev->struct_sem ); 959 up(&dev->struct_sem);
958 atomic_dec( &dev->buf_alloc ); 960 atomic_dec(&dev->buf_alloc);
959 return -ENOMEM; 961 return -ENOMEM;
960 } 962 }
961 memset( entry->buflist, 0, count * sizeof(*entry->buflist) ); 963 memset(entry->buflist, 0, count * sizeof(*entry->buflist));
962 964
963 entry->buf_size = size; 965 entry->buf_size = size;
964 entry->page_order = page_order; 966 entry->page_order = page_order;
965 967
966 offset = 0; 968 offset = 0;
967 969
968 while ( entry->buf_count < count ) { 970 while (entry->buf_count < count) {
969 buf = &entry->buflist[entry->buf_count]; 971 buf = &entry->buflist[entry->buf_count];
970 buf->idx = dma->buf_count + entry->buf_count; 972 buf->idx = dma->buf_count + entry->buf_count;
971 buf->total = alignment; 973 buf->total = alignment;
972 buf->order = order; 974 buf->order = order;
973 buf->used = 0; 975 buf->used = 0;
974 976
975 buf->offset = (dma->byte_count + offset); 977 buf->offset = (dma->byte_count + offset);
976 buf->bus_address = agp_offset + offset; 978 buf->bus_address = agp_offset + offset;
977 buf->address = (void *)(agp_offset + offset 979 buf->address = (void *)(agp_offset + offset
978 + (unsigned long)dev->sg->virtual); 980 + (unsigned long)dev->sg->virtual);
979 buf->next = NULL; 981 buf->next = NULL;
980 buf->waiting = 0; 982 buf->waiting = 0;
981 buf->pending = 0; 983 buf->pending = 0;
982 init_waitqueue_head( &buf->dma_wait ); 984 init_waitqueue_head(&buf->dma_wait);
983 buf->filp = NULL; 985 buf->filp = NULL;
984 986
985 buf->dev_priv_size = dev->driver->dev_priv_size; 987 buf->dev_priv_size = dev->driver->dev_priv_size;
986 buf->dev_private = drm_alloc( buf->dev_priv_size, 988 buf->dev_private = drm_alloc(buf->dev_priv_size, DRM_MEM_BUFS);
987 DRM_MEM_BUFS ); 989 if (!buf->dev_private) {
988 if(!buf->dev_private) {
989 /* Set count correctly so we free the proper amount. */ 990 /* Set count correctly so we free the proper amount. */
990 entry->buf_count = count; 991 entry->buf_count = count;
991 drm_cleanup_buf_error(dev,entry); 992 drm_cleanup_buf_error(dev, entry);
992 up( &dev->struct_sem ); 993 up(&dev->struct_sem);
993 atomic_dec( &dev->buf_alloc ); 994 atomic_dec(&dev->buf_alloc);
994 return -ENOMEM; 995 return -ENOMEM;
995 } 996 }
996 997
997 memset( buf->dev_private, 0, buf->dev_priv_size ); 998 memset(buf->dev_private, 0, buf->dev_priv_size);
998 999
999 DRM_DEBUG( "buffer %d @ %p\n", 1000 DRM_DEBUG("buffer %d @ %p\n", entry->buf_count, buf->address);
1000 entry->buf_count, buf->address );
1001 1001
1002 offset += alignment; 1002 offset += alignment;
1003 entry->buf_count++; 1003 entry->buf_count++;
1004 byte_count += PAGE_SIZE << page_order; 1004 byte_count += PAGE_SIZE << page_order;
1005 } 1005 }
1006 1006
1007 DRM_DEBUG( "byte_count: %d\n", byte_count ); 1007 DRM_DEBUG("byte_count: %d\n", byte_count);
1008 1008
1009 temp_buflist = drm_realloc( dma->buflist, 1009 temp_buflist = drm_realloc(dma->buflist,
1010 dma->buf_count * sizeof(*dma->buflist), 1010 dma->buf_count * sizeof(*dma->buflist),
1011 (dma->buf_count + entry->buf_count) 1011 (dma->buf_count + entry->buf_count)
1012 * sizeof(*dma->buflist), 1012 * sizeof(*dma->buflist), DRM_MEM_BUFS);
1013 DRM_MEM_BUFS ); 1013 if (!temp_buflist) {
1014 if(!temp_buflist) {
1015 /* Free the entry because it isn't valid */ 1014 /* Free the entry because it isn't valid */
1016 drm_cleanup_buf_error(dev,entry); 1015 drm_cleanup_buf_error(dev, entry);
1017 up( &dev->struct_sem ); 1016 up(&dev->struct_sem);
1018 atomic_dec( &dev->buf_alloc ); 1017 atomic_dec(&dev->buf_alloc);
1019 return -ENOMEM; 1018 return -ENOMEM;
1020 } 1019 }
1021 dma->buflist = temp_buflist; 1020 dma->buflist = temp_buflist;
1022 1021
1023 for ( i = 0 ; i < entry->buf_count ; i++ ) { 1022 for (i = 0; i < entry->buf_count; i++) {
1024 dma->buflist[i + dma->buf_count] = &entry->buflist[i]; 1023 dma->buflist[i + dma->buf_count] = &entry->buflist[i];
1025 } 1024 }
1026 1025
1027 dma->buf_count += entry->buf_count; 1026 dma->buf_count += entry->buf_count;
1028 dma->byte_count += byte_count; 1027 dma->byte_count += byte_count;
1029 1028
1030 DRM_DEBUG( "dma->buf_count : %d\n", dma->buf_count ); 1029 DRM_DEBUG("dma->buf_count : %d\n", dma->buf_count);
1031 DRM_DEBUG( "entry->buf_count : %d\n", entry->buf_count ); 1030 DRM_DEBUG("entry->buf_count : %d\n", entry->buf_count);
1032 1031
1033 up( &dev->struct_sem ); 1032 up(&dev->struct_sem);
1034 1033
1035 request->count = entry->buf_count; 1034 request->count = entry->buf_count;
1036 request->size = size; 1035 request->size = size;
1037 1036
1038 dma->flags = _DRM_DMA_USE_SG; 1037 dma->flags = _DRM_DMA_USE_SG;
1039 1038
1040 atomic_dec( &dev->buf_alloc ); 1039 atomic_dec(&dev->buf_alloc);
1041 return 0; 1040 return 0;
1042} 1041}
1043 1042
1044static int drm_addbufs_fb(drm_device_t *dev, drm_buf_desc_t *request) 1043static int drm_addbufs_fb(drm_device_t * dev, drm_buf_desc_t * request)
1045{ 1044{
1046 drm_device_dma_t *dma = dev->dma; 1045 drm_device_dma_t *dma = dev->dma;
1047 drm_buf_entry_t *entry; 1046 drm_buf_entry_t *entry;
@@ -1060,7 +1059,7 @@ static int drm_addbufs_fb(drm_device_t *dev, drm_buf_desc_t *request)
1060 1059
1061 if (!drm_core_check_feature(dev, DRIVER_FB_DMA)) 1060 if (!drm_core_check_feature(dev, DRIVER_FB_DMA))
1062 return -EINVAL; 1061 return -EINVAL;
1063 1062
1064 if (!dma) 1063 if (!dma)
1065 return -EINVAL; 1064 return -EINVAL;
1066 1065
@@ -1210,43 +1209,41 @@ static int drm_addbufs_fb(drm_device_t *dev, drm_buf_desc_t *request)
1210 * addbufs_sg() or addbufs_pci() for AGP, scatter-gather or consistent 1209 * addbufs_sg() or addbufs_pci() for AGP, scatter-gather or consistent
1211 * PCI memory respectively. 1210 * PCI memory respectively.
1212 */ 1211 */
1213int drm_addbufs( struct inode *inode, struct file *filp, 1212int drm_addbufs(struct inode *inode, struct file *filp,
1214 unsigned int cmd, unsigned long arg ) 1213 unsigned int cmd, unsigned long arg)
1215{ 1214{
1216 drm_buf_desc_t request; 1215 drm_buf_desc_t request;
1217 drm_file_t *priv = filp->private_data; 1216 drm_file_t *priv = filp->private_data;
1218 drm_device_t *dev = priv->head->dev; 1217 drm_device_t *dev = priv->head->dev;
1219 int ret; 1218 int ret;
1220 1219
1221 if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA)) 1220 if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA))
1222 return -EINVAL; 1221 return -EINVAL;
1223 1222
1224 if ( copy_from_user( &request, (drm_buf_desc_t __user *)arg, 1223 if (copy_from_user(&request, (drm_buf_desc_t __user *) arg,
1225 sizeof(request) ) ) 1224 sizeof(request)))
1226 return -EFAULT; 1225 return -EFAULT;
1227 1226
1228#if __OS_HAS_AGP 1227#if __OS_HAS_AGP
1229 if ( request.flags & _DRM_AGP_BUFFER ) 1228 if (request.flags & _DRM_AGP_BUFFER)
1230 ret=drm_addbufs_agp(dev, &request); 1229 ret = drm_addbufs_agp(dev, &request);
1231 else 1230 else
1232#endif 1231#endif
1233 if ( request.flags & _DRM_SG_BUFFER ) 1232 if (request.flags & _DRM_SG_BUFFER)
1234 ret=drm_addbufs_sg(dev, &request); 1233 ret = drm_addbufs_sg(dev, &request);
1235 else if ( request.flags & _DRM_FB_BUFFER) 1234 else if (request.flags & _DRM_FB_BUFFER)
1236 ret=drm_addbufs_fb(dev, &request); 1235 ret = drm_addbufs_fb(dev, &request);
1237 else 1236 else
1238 ret=drm_addbufs_pci(dev, &request); 1237 ret = drm_addbufs_pci(dev, &request);
1239 1238
1240 if (ret==0) { 1239 if (ret == 0) {
1241 if (copy_to_user((void __user *)arg, &request, 1240 if (copy_to_user((void __user *)arg, &request, sizeof(request))) {
1242 sizeof(request))) {
1243 ret = -EFAULT; 1241 ret = -EFAULT;
1244 } 1242 }
1245 } 1243 }
1246 return ret; 1244 return ret;
1247} 1245}
1248 1246
1249
1250/** 1247/**
1251 * Get information about the buffer mappings. 1248 * Get information about the buffer mappings.
1252 * 1249 *
@@ -1264,8 +1261,8 @@ int drm_addbufs( struct inode *inode, struct file *filp,
1264 * lock, preventing of allocating more buffers after this call. Information 1261 * lock, preventing of allocating more buffers after this call. Information
1265 * about each requested buffer is then copied into user space. 1262 * about each requested buffer is then copied into user space.
1266 */ 1263 */
1267int drm_infobufs( struct inode *inode, struct file *filp, 1264int drm_infobufs(struct inode *inode, struct file *filp,
1268 unsigned int cmd, unsigned long arg ) 1265 unsigned int cmd, unsigned long arg)
1269{ 1266{
1270 drm_file_t *priv = filp->private_data; 1267 drm_file_t *priv = filp->private_data;
1271 drm_device_t *dev = priv->head->dev; 1268 drm_device_t *dev = priv->head->dev;
@@ -1278,58 +1275,61 @@ int drm_infobufs( struct inode *inode, struct file *filp,
1278 if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA)) 1275 if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA))
1279 return -EINVAL; 1276 return -EINVAL;
1280 1277
1281 if ( !dma ) return -EINVAL; 1278 if (!dma)
1279 return -EINVAL;
1282 1280
1283 spin_lock( &dev->count_lock ); 1281 spin_lock(&dev->count_lock);
1284 if ( atomic_read( &dev->buf_alloc ) ) { 1282 if (atomic_read(&dev->buf_alloc)) {
1285 spin_unlock( &dev->count_lock ); 1283 spin_unlock(&dev->count_lock);
1286 return -EBUSY; 1284 return -EBUSY;
1287 } 1285 }
1288 ++dev->buf_use; /* Can't allocate more after this call */ 1286 ++dev->buf_use; /* Can't allocate more after this call */
1289 spin_unlock( &dev->count_lock ); 1287 spin_unlock(&dev->count_lock);
1290 1288
1291 if ( copy_from_user( &request, argp, sizeof(request) ) ) 1289 if (copy_from_user(&request, argp, sizeof(request)))
1292 return -EFAULT; 1290 return -EFAULT;
1293 1291
1294 for ( i = 0, count = 0 ; i < DRM_MAX_ORDER + 1 ; i++ ) { 1292 for (i = 0, count = 0; i < DRM_MAX_ORDER + 1; i++) {
1295 if ( dma->bufs[i].buf_count ) ++count; 1293 if (dma->bufs[i].buf_count)
1294 ++count;
1296 } 1295 }
1297 1296
1298 DRM_DEBUG( "count = %d\n", count ); 1297 DRM_DEBUG("count = %d\n", count);
1299 1298
1300 if ( request.count >= count ) { 1299 if (request.count >= count) {
1301 for ( i = 0, count = 0 ; i < DRM_MAX_ORDER + 1 ; i++ ) { 1300 for (i = 0, count = 0; i < DRM_MAX_ORDER + 1; i++) {
1302 if ( dma->bufs[i].buf_count ) { 1301 if (dma->bufs[i].buf_count) {
1303 drm_buf_desc_t __user *to = &request.list[count]; 1302 drm_buf_desc_t __user *to =
1303 &request.list[count];
1304 drm_buf_entry_t *from = &dma->bufs[i]; 1304 drm_buf_entry_t *from = &dma->bufs[i];
1305 drm_freelist_t *list = &dma->bufs[i].freelist; 1305 drm_freelist_t *list = &dma->bufs[i].freelist;
1306 if ( copy_to_user( &to->count, 1306 if (copy_to_user(&to->count,
1307 &from->buf_count, 1307 &from->buf_count,
1308 sizeof(from->buf_count) ) || 1308 sizeof(from->buf_count)) ||
1309 copy_to_user( &to->size, 1309 copy_to_user(&to->size,
1310 &from->buf_size, 1310 &from->buf_size,
1311 sizeof(from->buf_size) ) || 1311 sizeof(from->buf_size)) ||
1312 copy_to_user( &to->low_mark, 1312 copy_to_user(&to->low_mark,
1313 &list->low_mark, 1313 &list->low_mark,
1314 sizeof(list->low_mark) ) || 1314 sizeof(list->low_mark)) ||
1315 copy_to_user( &to->high_mark, 1315 copy_to_user(&to->high_mark,
1316 &list->high_mark, 1316 &list->high_mark,
1317 sizeof(list->high_mark) ) ) 1317 sizeof(list->high_mark)))
1318 return -EFAULT; 1318 return -EFAULT;
1319 1319
1320 DRM_DEBUG( "%d %d %d %d %d\n", 1320 DRM_DEBUG("%d %d %d %d %d\n",
1321 i, 1321 i,
1322 dma->bufs[i].buf_count, 1322 dma->bufs[i].buf_count,
1323 dma->bufs[i].buf_size, 1323 dma->bufs[i].buf_size,
1324 dma->bufs[i].freelist.low_mark, 1324 dma->bufs[i].freelist.low_mark,
1325 dma->bufs[i].freelist.high_mark ); 1325 dma->bufs[i].freelist.high_mark);
1326 ++count; 1326 ++count;
1327 } 1327 }
1328 } 1328 }
1329 } 1329 }
1330 request.count = count; 1330 request.count = count;
1331 1331
1332 if ( copy_to_user( argp, &request, sizeof(request) ) ) 1332 if (copy_to_user(argp, &request, sizeof(request)))
1333 return -EFAULT; 1333 return -EFAULT;
1334 1334
1335 return 0; 1335 return 0;
@@ -1349,8 +1349,8 @@ int drm_infobufs( struct inode *inode, struct file *filp,
1349 * 1349 *
1350 * \note This ioctl is deprecated and mostly never used. 1350 * \note This ioctl is deprecated and mostly never used.
1351 */ 1351 */
1352int drm_markbufs( struct inode *inode, struct file *filp, 1352int drm_markbufs(struct inode *inode, struct file *filp,
1353 unsigned int cmd, unsigned long arg ) 1353 unsigned int cmd, unsigned long arg)
1354{ 1354{
1355 drm_file_t *priv = filp->private_data; 1355 drm_file_t *priv = filp->private_data;
1356 drm_device_t *dev = priv->head->dev; 1356 drm_device_t *dev = priv->head->dev;
@@ -1362,44 +1362,45 @@ int drm_markbufs( struct inode *inode, struct file *filp,
1362 if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA)) 1362 if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA))
1363 return -EINVAL; 1363 return -EINVAL;
1364 1364
1365 if ( !dma ) return -EINVAL; 1365 if (!dma)
1366 return -EINVAL;
1366 1367
1367 if ( copy_from_user( &request, 1368 if (copy_from_user(&request,
1368 (drm_buf_desc_t __user *)arg, 1369 (drm_buf_desc_t __user *) arg, sizeof(request)))
1369 sizeof(request) ) )
1370 return -EFAULT; 1370 return -EFAULT;
1371 1371
1372 DRM_DEBUG( "%d, %d, %d\n", 1372 DRM_DEBUG("%d, %d, %d\n",
1373 request.size, request.low_mark, request.high_mark ); 1373 request.size, request.low_mark, request.high_mark);
1374 order = drm_order( request.size ); 1374 order = drm_order(request.size);
1375 if ( order < DRM_MIN_ORDER || order > DRM_MAX_ORDER ) return -EINVAL; 1375 if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER)
1376 return -EINVAL;
1376 entry = &dma->bufs[order]; 1377 entry = &dma->bufs[order];
1377 1378
1378 if ( request.low_mark < 0 || request.low_mark > entry->buf_count ) 1379 if (request.low_mark < 0 || request.low_mark > entry->buf_count)
1379 return -EINVAL; 1380 return -EINVAL;
1380 if ( request.high_mark < 0 || request.high_mark > entry->buf_count ) 1381 if (request.high_mark < 0 || request.high_mark > entry->buf_count)
1381 return -EINVAL; 1382 return -EINVAL;
1382 1383
1383 entry->freelist.low_mark = request.low_mark; 1384 entry->freelist.low_mark = request.low_mark;
1384 entry->freelist.high_mark = request.high_mark; 1385 entry->freelist.high_mark = request.high_mark;
1385 1386
1386 return 0; 1387 return 0;
1387} 1388}
1388 1389
1389/** 1390/**
1390 * Unreserve the buffers in list, previously reserved using drmDMA. 1391 * Unreserve the buffers in list, previously reserved using drmDMA.
1391 * 1392 *
1392 * \param inode device inode. 1393 * \param inode device inode.
1393 * \param filp file pointer. 1394 * \param filp file pointer.
1394 * \param cmd command. 1395 * \param cmd command.
1395 * \param arg pointer to a drm_buf_free structure. 1396 * \param arg pointer to a drm_buf_free structure.
1396 * \return zero on success or a negative number on failure. 1397 * \return zero on success or a negative number on failure.
1397 * 1398 *
1398 * Calls free_buffer() for each used buffer. 1399 * Calls free_buffer() for each used buffer.
1399 * This function is primarily used for debugging. 1400 * This function is primarily used for debugging.
1400 */ 1401 */
1401int drm_freebufs( struct inode *inode, struct file *filp, 1402int drm_freebufs(struct inode *inode, struct file *filp,
1402 unsigned int cmd, unsigned long arg ) 1403 unsigned int cmd, unsigned long arg)
1403{ 1404{
1404 drm_file_t *priv = filp->private_data; 1405 drm_file_t *priv = filp->private_data;
1405 drm_device_t *dev = priv->head->dev; 1406 drm_device_t *dev = priv->head->dev;
@@ -1412,31 +1413,29 @@ int drm_freebufs( struct inode *inode, struct file *filp,
1412 if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA)) 1413 if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA))
1413 return -EINVAL; 1414 return -EINVAL;
1414 1415
1415 if ( !dma ) return -EINVAL; 1416 if (!dma)
1417 return -EINVAL;
1416 1418
1417 if ( copy_from_user( &request, 1419 if (copy_from_user(&request,
1418 (drm_buf_free_t __user *)arg, 1420 (drm_buf_free_t __user *) arg, sizeof(request)))
1419 sizeof(request) ) )
1420 return -EFAULT; 1421 return -EFAULT;
1421 1422
1422 DRM_DEBUG( "%d\n", request.count ); 1423 DRM_DEBUG("%d\n", request.count);
1423 for ( i = 0 ; i < request.count ; i++ ) { 1424 for (i = 0; i < request.count; i++) {
1424 if ( copy_from_user( &idx, 1425 if (copy_from_user(&idx, &request.list[i], sizeof(idx)))
1425 &request.list[i],
1426 sizeof(idx) ) )
1427 return -EFAULT; 1426 return -EFAULT;
1428 if ( idx < 0 || idx >= dma->buf_count ) { 1427 if (idx < 0 || idx >= dma->buf_count) {
1429 DRM_ERROR( "Index %d (of %d max)\n", 1428 DRM_ERROR("Index %d (of %d max)\n",
1430 idx, dma->buf_count - 1 ); 1429 idx, dma->buf_count - 1);
1431 return -EINVAL; 1430 return -EINVAL;
1432 } 1431 }
1433 buf = dma->buflist[idx]; 1432 buf = dma->buflist[idx];
1434 if ( buf->filp != filp ) { 1433 if (buf->filp != filp) {
1435 DRM_ERROR( "Process %d freeing buffer not owned\n", 1434 DRM_ERROR("Process %d freeing buffer not owned\n",
1436 current->pid ); 1435 current->pid);
1437 return -EINVAL; 1436 return -EINVAL;
1438 } 1437 }
1439 drm_free_buffer( dev, buf ); 1438 drm_free_buffer(dev, buf);
1440 } 1439 }
1441 1440
1442 return 0; 1441 return 0;
@@ -1455,8 +1454,8 @@ int drm_freebufs( struct inode *inode, struct file *filp,
1455 * about each buffer into user space. The PCI buffers are already mapped on the 1454 * about each buffer into user space. The PCI buffers are already mapped on the
1456 * addbufs_pci() call. 1455 * addbufs_pci() call.
1457 */ 1456 */
1458int drm_mapbufs( struct inode *inode, struct file *filp, 1457int drm_mapbufs(struct inode *inode, struct file *filp,
1459 unsigned int cmd, unsigned long arg ) 1458 unsigned int cmd, unsigned long arg)
1460{ 1459{
1461 drm_file_t *priv = filp->private_data; 1460 drm_file_t *priv = filp->private_data;
1462 drm_device_t *dev = priv->head->dev; 1461 drm_device_t *dev = priv->head->dev;
@@ -1472,86 +1471,84 @@ int drm_mapbufs( struct inode *inode, struct file *filp,
1472 if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA)) 1471 if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA))
1473 return -EINVAL; 1472 return -EINVAL;
1474 1473
1475 if ( !dma ) return -EINVAL; 1474 if (!dma)
1475 return -EINVAL;
1476 1476
1477 spin_lock( &dev->count_lock ); 1477 spin_lock(&dev->count_lock);
1478 if ( atomic_read( &dev->buf_alloc ) ) { 1478 if (atomic_read(&dev->buf_alloc)) {
1479 spin_unlock( &dev->count_lock ); 1479 spin_unlock(&dev->count_lock);
1480 return -EBUSY; 1480 return -EBUSY;
1481 } 1481 }
1482 dev->buf_use++; /* Can't allocate more after this call */ 1482 dev->buf_use++; /* Can't allocate more after this call */
1483 spin_unlock( &dev->count_lock ); 1483 spin_unlock(&dev->count_lock);
1484 1484
1485 if ( copy_from_user( &request, argp, sizeof(request) ) ) 1485 if (copy_from_user(&request, argp, sizeof(request)))
1486 return -EFAULT; 1486 return -EFAULT;
1487 1487
1488 if ( request.count >= dma->buf_count ) { 1488 if (request.count >= dma->buf_count) {
1489 if ((drm_core_has_AGP(dev) && (dma->flags & _DRM_DMA_USE_AGP)) 1489 if ((drm_core_has_AGP(dev) && (dma->flags & _DRM_DMA_USE_AGP))
1490 || (drm_core_check_feature(dev, DRIVER_SG) 1490 || (drm_core_check_feature(dev, DRIVER_SG)
1491 && (dma->flags & _DRM_DMA_USE_SG)) 1491 && (dma->flags & _DRM_DMA_USE_SG))
1492 || (drm_core_check_feature(dev, DRIVER_FB_DMA) 1492 || (drm_core_check_feature(dev, DRIVER_FB_DMA)
1493 && (dma->flags & _DRM_DMA_USE_FB))) { 1493 && (dma->flags & _DRM_DMA_USE_FB))) {
1494 drm_map_t *map = dev->agp_buffer_map; 1494 drm_map_t *map = dev->agp_buffer_map;
1495 unsigned long token = dev->agp_buffer_token; 1495 unsigned long token = dev->agp_buffer_token;
1496 1496
1497 if ( !map ) { 1497 if (!map) {
1498 retcode = -EINVAL; 1498 retcode = -EINVAL;
1499 goto done; 1499 goto done;
1500 } 1500 }
1501 1501
1502 down_write( &current->mm->mmap_sem ); 1502 down_write(&current->mm->mmap_sem);
1503 virtual = do_mmap( filp, 0, map->size, 1503 virtual = do_mmap(filp, 0, map->size,
1504 PROT_READ | PROT_WRITE, 1504 PROT_READ | PROT_WRITE,
1505 MAP_SHARED, 1505 MAP_SHARED, token);
1506 token ); 1506 up_write(&current->mm->mmap_sem);
1507 up_write( &current->mm->mmap_sem );
1508 } else { 1507 } else {
1509 down_write( &current->mm->mmap_sem ); 1508 down_write(&current->mm->mmap_sem);
1510 virtual = do_mmap( filp, 0, dma->byte_count, 1509 virtual = do_mmap(filp, 0, dma->byte_count,
1511 PROT_READ | PROT_WRITE, 1510 PROT_READ | PROT_WRITE,
1512 MAP_SHARED, 0 ); 1511 MAP_SHARED, 0);
1513 up_write( &current->mm->mmap_sem ); 1512 up_write(&current->mm->mmap_sem);
1514 } 1513 }
1515 if ( virtual > -1024UL ) { 1514 if (virtual > -1024UL) {
1516 /* Real error */ 1515 /* Real error */
1517 retcode = (signed long)virtual; 1516 retcode = (signed long)virtual;
1518 goto done; 1517 goto done;
1519 } 1518 }
1520 request.virtual = (void __user *)virtual; 1519 request.virtual = (void __user *)virtual;
1521 1520
1522 for ( i = 0 ; i < dma->buf_count ; i++ ) { 1521 for (i = 0; i < dma->buf_count; i++) {
1523 if ( copy_to_user( &request.list[i].idx, 1522 if (copy_to_user(&request.list[i].idx,
1524 &dma->buflist[i]->idx, 1523 &dma->buflist[i]->idx,
1525 sizeof(request.list[0].idx) ) ) { 1524 sizeof(request.list[0].idx))) {
1526 retcode = -EFAULT; 1525 retcode = -EFAULT;
1527 goto done; 1526 goto done;
1528 } 1527 }
1529 if ( copy_to_user( &request.list[i].total, 1528 if (copy_to_user(&request.list[i].total,
1530 &dma->buflist[i]->total, 1529 &dma->buflist[i]->total,
1531 sizeof(request.list[0].total) ) ) { 1530 sizeof(request.list[0].total))) {
1532 retcode = -EFAULT; 1531 retcode = -EFAULT;
1533 goto done; 1532 goto done;
1534 } 1533 }
1535 if ( copy_to_user( &request.list[i].used, 1534 if (copy_to_user(&request.list[i].used,
1536 &zero, 1535 &zero, sizeof(zero))) {
1537 sizeof(zero) ) ) {
1538 retcode = -EFAULT; 1536 retcode = -EFAULT;
1539 goto done; 1537 goto done;
1540 } 1538 }
1541 address = virtual + dma->buflist[i]->offset; /* *** */ 1539 address = virtual + dma->buflist[i]->offset; /* *** */
1542 if ( copy_to_user( &request.list[i].address, 1540 if (copy_to_user(&request.list[i].address,
1543 &address, 1541 &address, sizeof(address))) {
1544 sizeof(address) ) ) {
1545 retcode = -EFAULT; 1542 retcode = -EFAULT;
1546 goto done; 1543 goto done;
1547 } 1544 }
1548 } 1545 }
1549 } 1546 }
1550 done: 1547 done:
1551 request.count = dma->buf_count; 1548 request.count = dma->buf_count;
1552 DRM_DEBUG( "%d buffers, retcode = %d\n", request.count, retcode ); 1549 DRM_DEBUG("%d buffers, retcode = %d\n", request.count, retcode);
1553 1550
1554 if ( copy_to_user( argp, &request, sizeof(request) ) ) 1551 if (copy_to_user(argp, &request, sizeof(request)))
1555 return -EFAULT; 1552 return -EFAULT;
1556 1553
1557 return retcode; 1554 return retcode;
@@ -1560,23 +1557,23 @@ int drm_mapbufs( struct inode *inode, struct file *filp,
1560/** 1557/**
1561 * Compute size order. Returns the exponent of the smaller power of two which 1558 * Compute size order. Returns the exponent of the smaller power of two which
1562 * is greater or equal to given number. 1559 * is greater or equal to given number.
1563 * 1560 *
1564 * \param size size. 1561 * \param size size.
1565 * \return order. 1562 * \return order.
1566 * 1563 *
1567 * \todo Can be made faster. 1564 * \todo Can be made faster.
1568 */ 1565 */
1569int drm_order( unsigned long size ) 1566int drm_order(unsigned long size)
1570{ 1567{
1571 int order; 1568 int order;
1572 unsigned long tmp; 1569 unsigned long tmp;
1573 1570
1574 for (order = 0, tmp = size >> 1; tmp; tmp >>= 1, order++) 1571 for (order = 0, tmp = size >> 1; tmp; tmp >>= 1, order++) ;
1575 ;
1576 1572
1577 if (size & (size - 1)) 1573 if (size & (size - 1))
1578 ++order; 1574 ++order;
1579 1575
1580 return order; 1576 return order;
1581} 1577}
1578
1582EXPORT_SYMBOL(drm_order); 1579EXPORT_SYMBOL(drm_order);
diff --git a/drivers/char/drm/drm_context.c b/drivers/char/drm/drm_context.c
index 502892794c16..6380127be281 100644
--- a/drivers/char/drm/drm_context.c
+++ b/drivers/char/drm/drm_context.c
@@ -1,7 +1,7 @@
1/** 1/**
2 * \file drm_context.h 2 * \file drm_context.c
3 * IOCTLs for generic contexts 3 * IOCTLs for generic contexts
4 * 4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
6 * \author Gareth Hughes <gareth@valinux.com> 6 * \author Gareth Hughes <gareth@valinux.com>
7 */ 7 */
@@ -56,25 +56,26 @@
56 * in drm_device::context_sareas, while holding the drm_device::struct_sem 56 * in drm_device::context_sareas, while holding the drm_device::struct_sem
57 * lock. 57 * lock.
58 */ 58 */
59void drm_ctxbitmap_free( drm_device_t *dev, int ctx_handle ) 59void drm_ctxbitmap_free(drm_device_t * dev, int ctx_handle)
60{ 60{
61 if ( ctx_handle < 0 ) goto failed; 61 if (ctx_handle < 0)
62 if ( !dev->ctx_bitmap ) goto failed; 62 goto failed;
63 if (!dev->ctx_bitmap)
64 goto failed;
63 65
64 if ( ctx_handle < DRM_MAX_CTXBITMAP ) { 66 if (ctx_handle < DRM_MAX_CTXBITMAP) {
65 down(&dev->struct_sem); 67 down(&dev->struct_sem);
66 clear_bit( ctx_handle, dev->ctx_bitmap ); 68 clear_bit(ctx_handle, dev->ctx_bitmap);
67 dev->context_sareas[ctx_handle] = NULL; 69 dev->context_sareas[ctx_handle] = NULL;
68 up(&dev->struct_sem); 70 up(&dev->struct_sem);
69 return; 71 return;
70 } 72 }
71failed: 73 failed:
72 DRM_ERROR( "Attempt to free invalid context handle: %d\n", 74 DRM_ERROR("Attempt to free invalid context handle: %d\n", ctx_handle);
73 ctx_handle ); 75 return;
74 return;
75} 76}
76 77
77/** 78/**
78 * Context bitmap allocation. 79 * Context bitmap allocation.
79 * 80 *
80 * \param dev DRM device. 81 * \param dev DRM device.
@@ -84,29 +85,33 @@ failed:
84 * drm_device::context_sareas to accommodate the new entry while holding the 85 * drm_device::context_sareas to accommodate the new entry while holding the
85 * drm_device::struct_sem lock. 86 * drm_device::struct_sem lock.
86 */ 87 */
87static int drm_ctxbitmap_next( drm_device_t *dev ) 88static int drm_ctxbitmap_next(drm_device_t * dev)
88{ 89{
89 int bit; 90 int bit;
90 91
91 if(!dev->ctx_bitmap) return -1; 92 if (!dev->ctx_bitmap)
93 return -1;
92 94
93 down(&dev->struct_sem); 95 down(&dev->struct_sem);
94 bit = find_first_zero_bit( dev->ctx_bitmap, DRM_MAX_CTXBITMAP ); 96 bit = find_first_zero_bit(dev->ctx_bitmap, DRM_MAX_CTXBITMAP);
95 if ( bit < DRM_MAX_CTXBITMAP ) { 97 if (bit < DRM_MAX_CTXBITMAP) {
96 set_bit( bit, dev->ctx_bitmap ); 98 set_bit(bit, dev->ctx_bitmap);
97 DRM_DEBUG( "drm_ctxbitmap_next bit : %d\n", bit ); 99 DRM_DEBUG("drm_ctxbitmap_next bit : %d\n", bit);
98 if((bit+1) > dev->max_context) { 100 if ((bit + 1) > dev->max_context) {
99 dev->max_context = (bit+1); 101 dev->max_context = (bit + 1);
100 if(dev->context_sareas) { 102 if (dev->context_sareas) {
101 drm_map_t **ctx_sareas; 103 drm_map_t **ctx_sareas;
102 104
103 ctx_sareas = drm_realloc(dev->context_sareas, 105 ctx_sareas = drm_realloc(dev->context_sareas,
104 (dev->max_context - 1) * 106 (dev->max_context -
105 sizeof(*dev->context_sareas), 107 1) *
106 dev->max_context * 108 sizeof(*dev->
107 sizeof(*dev->context_sareas), 109 context_sareas),
108 DRM_MEM_MAPS); 110 dev->max_context *
109 if(!ctx_sareas) { 111 sizeof(*dev->
112 context_sareas),
113 DRM_MEM_MAPS);
114 if (!ctx_sareas) {
110 clear_bit(bit, dev->ctx_bitmap); 115 clear_bit(bit, dev->ctx_bitmap);
111 up(&dev->struct_sem); 116 up(&dev->struct_sem);
112 return -1; 117 return -1;
@@ -115,11 +120,11 @@ static int drm_ctxbitmap_next( drm_device_t *dev )
115 dev->context_sareas[bit] = NULL; 120 dev->context_sareas[bit] = NULL;
116 } else { 121 } else {
117 /* max_context == 1 at this point */ 122 /* max_context == 1 at this point */
118 dev->context_sareas = drm_alloc( 123 dev->context_sareas =
119 dev->max_context * 124 drm_alloc(dev->max_context *
120 sizeof(*dev->context_sareas), 125 sizeof(*dev->context_sareas),
121 DRM_MEM_MAPS); 126 DRM_MEM_MAPS);
122 if(!dev->context_sareas) { 127 if (!dev->context_sareas) {
123 clear_bit(bit, dev->ctx_bitmap); 128 clear_bit(bit, dev->ctx_bitmap);
124 up(&dev->struct_sem); 129 up(&dev->struct_sem);
125 return -1; 130 return -1;
@@ -142,26 +147,26 @@ static int drm_ctxbitmap_next( drm_device_t *dev )
142 * Allocates and initialize drm_device::ctx_bitmap and drm_device::context_sareas, while holding 147 * Allocates and initialize drm_device::ctx_bitmap and drm_device::context_sareas, while holding
143 * the drm_device::struct_sem lock. 148 * the drm_device::struct_sem lock.
144 */ 149 */
145int drm_ctxbitmap_init( drm_device_t *dev ) 150int drm_ctxbitmap_init(drm_device_t * dev)
146{ 151{
147 int i; 152 int i;
148 int temp; 153 int temp;
149 154
150 down(&dev->struct_sem); 155 down(&dev->struct_sem);
151 dev->ctx_bitmap = (unsigned long *) drm_alloc( PAGE_SIZE, 156 dev->ctx_bitmap = (unsigned long *)drm_alloc(PAGE_SIZE,
152 DRM_MEM_CTXBITMAP ); 157 DRM_MEM_CTXBITMAP);
153 if ( dev->ctx_bitmap == NULL ) { 158 if (dev->ctx_bitmap == NULL) {
154 up(&dev->struct_sem); 159 up(&dev->struct_sem);
155 return -ENOMEM; 160 return -ENOMEM;
156 } 161 }
157 memset( (void *)dev->ctx_bitmap, 0, PAGE_SIZE ); 162 memset((void *)dev->ctx_bitmap, 0, PAGE_SIZE);
158 dev->context_sareas = NULL; 163 dev->context_sareas = NULL;
159 dev->max_context = -1; 164 dev->max_context = -1;
160 up(&dev->struct_sem); 165 up(&dev->struct_sem);
161 166
162 for ( i = 0 ; i < DRM_RESERVED_CONTEXTS ; i++ ) { 167 for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) {
163 temp = drm_ctxbitmap_next( dev ); 168 temp = drm_ctxbitmap_next(dev);
164 DRM_DEBUG( "drm_ctxbitmap_init : %d\n", temp ); 169 DRM_DEBUG("drm_ctxbitmap_init : %d\n", temp);
165 } 170 }
166 171
167 return 0; 172 return 0;
@@ -175,14 +180,14 @@ int drm_ctxbitmap_init( drm_device_t *dev )
175 * Frees drm_device::ctx_bitmap and drm_device::context_sareas, while holding 180 * Frees drm_device::ctx_bitmap and drm_device::context_sareas, while holding
176 * the drm_device::struct_sem lock. 181 * the drm_device::struct_sem lock.
177 */ 182 */
178void drm_ctxbitmap_cleanup( drm_device_t *dev ) 183void drm_ctxbitmap_cleanup(drm_device_t * dev)
179{ 184{
180 down(&dev->struct_sem); 185 down(&dev->struct_sem);
181 if( dev->context_sareas ) drm_free( dev->context_sareas, 186 if (dev->context_sareas)
182 sizeof(*dev->context_sareas) * 187 drm_free(dev->context_sareas,
183 dev->max_context, 188 sizeof(*dev->context_sareas) *
184 DRM_MEM_MAPS ); 189 dev->max_context, DRM_MEM_MAPS);
185 drm_free( (void *)dev->ctx_bitmap, PAGE_SIZE, DRM_MEM_CTXBITMAP ); 190 drm_free((void *)dev->ctx_bitmap, PAGE_SIZE, DRM_MEM_CTXBITMAP);
186 up(&dev->struct_sem); 191 up(&dev->struct_sem);
187} 192}
188 193
@@ -194,7 +199,7 @@ void drm_ctxbitmap_cleanup( drm_device_t *dev )
194 199
195/** 200/**
196 * Get per-context SAREA. 201 * Get per-context SAREA.
197 * 202 *
198 * \param inode device inode. 203 * \param inode device inode.
199 * \param filp file pointer. 204 * \param filp file pointer.
200 * \param cmd command. 205 * \param cmd command.
@@ -205,10 +210,10 @@ void drm_ctxbitmap_cleanup( drm_device_t *dev )
205 * returns its handle. 210 * returns its handle.
206 */ 211 */
207int drm_getsareactx(struct inode *inode, struct file *filp, 212int drm_getsareactx(struct inode *inode, struct file *filp,
208 unsigned int cmd, unsigned long arg) 213 unsigned int cmd, unsigned long arg)
209{ 214{
210 drm_file_t *priv = filp->private_data; 215 drm_file_t *priv = filp->private_data;
211 drm_device_t *dev = priv->head->dev; 216 drm_device_t *dev = priv->head->dev;
212 drm_ctx_priv_map_t __user *argp = (void __user *)arg; 217 drm_ctx_priv_map_t __user *argp = (void __user *)arg;
213 drm_ctx_priv_map_t request; 218 drm_ctx_priv_map_t request;
214 drm_map_t *map; 219 drm_map_t *map;
@@ -218,7 +223,8 @@ int drm_getsareactx(struct inode *inode, struct file *filp,
218 return -EFAULT; 223 return -EFAULT;
219 224
220 down(&dev->struct_sem); 225 down(&dev->struct_sem);
221 if (dev->max_context < 0 || request.ctx_id >= (unsigned) dev->max_context) { 226 if (dev->max_context < 0
227 || request.ctx_id >= (unsigned)dev->max_context) {
222 up(&dev->struct_sem); 228 up(&dev->struct_sem);
223 return -EINVAL; 229 return -EINVAL;
224 } 230 }
@@ -227,16 +233,16 @@ int drm_getsareactx(struct inode *inode, struct file *filp,
227 up(&dev->struct_sem); 233 up(&dev->struct_sem);
228 234
229 request.handle = 0; 235 request.handle = 0;
230 list_for_each_entry(_entry, &dev->maplist->head,head) { 236 list_for_each_entry(_entry, &dev->maplist->head, head) {
231 if (_entry->map == map) { 237 if (_entry->map == map) {
232 request.handle = (void *)(unsigned long)_entry->user_token; 238 request.handle =
239 (void *)(unsigned long)_entry->user_token;
233 break; 240 break;
234 } 241 }
235 } 242 }
236 if (request.handle == 0) 243 if (request.handle == 0)
237 return -EINVAL; 244 return -EINVAL;
238 245
239
240 if (copy_to_user(argp, &request, sizeof(request))) 246 if (copy_to_user(argp, &request, sizeof(request)))
241 return -EFAULT; 247 return -EFAULT;
242 return 0; 248 return 0;
@@ -244,7 +250,7 @@ int drm_getsareactx(struct inode *inode, struct file *filp,
244 250
245/** 251/**
246 * Set per-context SAREA. 252 * Set per-context SAREA.
247 * 253 *
248 * \param inode device inode. 254 * \param inode device inode.
249 * \param filp file pointer. 255 * \param filp file pointer.
250 * \param cmd command. 256 * \param cmd command.
@@ -255,37 +261,37 @@ int drm_getsareactx(struct inode *inode, struct file *filp,
255 * drm_device::context_sareas with it. 261 * drm_device::context_sareas with it.
256 */ 262 */
257int drm_setsareactx(struct inode *inode, struct file *filp, 263int drm_setsareactx(struct inode *inode, struct file *filp,
258 unsigned int cmd, unsigned long arg) 264 unsigned int cmd, unsigned long arg)
259{ 265{
260 drm_file_t *priv = filp->private_data; 266 drm_file_t *priv = filp->private_data;
261 drm_device_t *dev = priv->head->dev; 267 drm_device_t *dev = priv->head->dev;
262 drm_ctx_priv_map_t request; 268 drm_ctx_priv_map_t request;
263 drm_map_t *map = NULL; 269 drm_map_t *map = NULL;
264 drm_map_list_t *r_list = NULL; 270 drm_map_list_t *r_list = NULL;
265 struct list_head *list; 271 struct list_head *list;
266 272
267 if (copy_from_user(&request, 273 if (copy_from_user(&request,
268 (drm_ctx_priv_map_t __user *)arg, 274 (drm_ctx_priv_map_t __user *) arg, sizeof(request)))
269 sizeof(request)))
270 return -EFAULT; 275 return -EFAULT;
271 276
272 down(&dev->struct_sem); 277 down(&dev->struct_sem);
273 list_for_each(list, &dev->maplist->head) { 278 list_for_each(list, &dev->maplist->head) {
274 r_list = list_entry(list, drm_map_list_t, head); 279 r_list = list_entry(list, drm_map_list_t, head);
275 if (r_list->map 280 if (r_list->map
276 && r_list->user_token == (unsigned long) request.handle) 281 && r_list->user_token == (unsigned long)request.handle)
277 goto found; 282 goto found;
278 } 283 }
279bad: 284 bad:
280 up(&dev->struct_sem); 285 up(&dev->struct_sem);
281 return -EINVAL; 286 return -EINVAL;
282 287
283found: 288 found:
284 map = r_list->map; 289 map = r_list->map;
285 if (!map) goto bad; 290 if (!map)
291 goto bad;
286 if (dev->max_context < 0) 292 if (dev->max_context < 0)
287 goto bad; 293 goto bad;
288 if (request.ctx_id >= (unsigned) dev->max_context) 294 if (request.ctx_id >= (unsigned)dev->max_context)
289 goto bad; 295 goto bad;
290 dev->context_sareas[request.ctx_id] = map; 296 dev->context_sareas[request.ctx_id] = map;
291 up(&dev->struct_sem); 297 up(&dev->struct_sem);
@@ -308,22 +314,21 @@ found:
308 * 314 *
309 * Attempt to set drm_device::context_flag. 315 * Attempt to set drm_device::context_flag.
310 */ 316 */
311static int drm_context_switch( drm_device_t *dev, int old, int new ) 317static int drm_context_switch(drm_device_t * dev, int old, int new)
312{ 318{
313 if ( test_and_set_bit( 0, &dev->context_flag ) ) { 319 if (test_and_set_bit(0, &dev->context_flag)) {
314 DRM_ERROR( "Reentering -- FIXME\n" ); 320 DRM_ERROR("Reentering -- FIXME\n");
315 return -EBUSY; 321 return -EBUSY;
316 } 322 }
317
318 323
319 DRM_DEBUG( "Context switch from %d to %d\n", old, new ); 324 DRM_DEBUG("Context switch from %d to %d\n", old, new);
320 325
321 if ( new == dev->last_context ) { 326 if (new == dev->last_context) {
322 clear_bit( 0, &dev->context_flag ); 327 clear_bit(0, &dev->context_flag);
323 return 0; 328 return 0;
324 } 329 }
325 330
326 return 0; 331 return 0;
327} 332}
328 333
329/** 334/**
@@ -337,22 +342,22 @@ static int drm_context_switch( drm_device_t *dev, int old, int new )
337 * hardware lock is held, clears the drm_device::context_flag and wakes up 342 * hardware lock is held, clears the drm_device::context_flag and wakes up
338 * drm_device::context_wait. 343 * drm_device::context_wait.
339 */ 344 */
340static int drm_context_switch_complete( drm_device_t *dev, int new ) 345static int drm_context_switch_complete(drm_device_t * dev, int new)
341{ 346{
342 dev->last_context = new; /* PRE/POST: This is the _only_ writer. */ 347 dev->last_context = new; /* PRE/POST: This is the _only_ writer. */
343 dev->last_switch = jiffies; 348 dev->last_switch = jiffies;
344 349
345 if ( !_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock) ) { 350 if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
346 DRM_ERROR( "Lock isn't held after context switch\n" ); 351 DRM_ERROR("Lock isn't held after context switch\n");
347 } 352 }
348 353
349 /* If a context switch is ever initiated 354 /* If a context switch is ever initiated
350 when the kernel holds the lock, release 355 when the kernel holds the lock, release
351 that lock here. */ 356 that lock here. */
352 clear_bit( 0, &dev->context_flag ); 357 clear_bit(0, &dev->context_flag);
353 wake_up( &dev->context_wait ); 358 wake_up(&dev->context_wait);
354 359
355 return 0; 360 return 0;
356} 361}
357 362
358/** 363/**
@@ -364,29 +369,28 @@ static int drm_context_switch_complete( drm_device_t *dev, int new )
364 * \param arg user argument pointing to a drm_ctx_res structure. 369 * \param arg user argument pointing to a drm_ctx_res structure.
365 * \return zero on success or a negative number on failure. 370 * \return zero on success or a negative number on failure.
366 */ 371 */
367int drm_resctx( struct inode *inode, struct file *filp, 372int drm_resctx(struct inode *inode, struct file *filp,
368 unsigned int cmd, unsigned long arg ) 373 unsigned int cmd, unsigned long arg)
369{ 374{
370 drm_ctx_res_t res; 375 drm_ctx_res_t res;
371 drm_ctx_t __user *argp = (void __user *)arg; 376 drm_ctx_t __user *argp = (void __user *)arg;
372 drm_ctx_t ctx; 377 drm_ctx_t ctx;
373 int i; 378 int i;
374 379
375 if ( copy_from_user( &res, argp, sizeof(res) ) ) 380 if (copy_from_user(&res, argp, sizeof(res)))
376 return -EFAULT; 381 return -EFAULT;
377 382
378 if ( res.count >= DRM_RESERVED_CONTEXTS ) { 383 if (res.count >= DRM_RESERVED_CONTEXTS) {
379 memset( &ctx, 0, sizeof(ctx) ); 384 memset(&ctx, 0, sizeof(ctx));
380 for ( i = 0 ; i < DRM_RESERVED_CONTEXTS ; i++ ) { 385 for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) {
381 ctx.handle = i; 386 ctx.handle = i;
382 if ( copy_to_user( &res.contexts[i], 387 if (copy_to_user(&res.contexts[i], &ctx, sizeof(ctx)))
383 &ctx, sizeof(ctx) ) )
384 return -EFAULT; 388 return -EFAULT;
385 } 389 }
386 } 390 }
387 res.count = DRM_RESERVED_CONTEXTS; 391 res.count = DRM_RESERVED_CONTEXTS;
388 392
389 if ( copy_to_user( argp, &res, sizeof(res) ) ) 393 if (copy_to_user(argp, &res, sizeof(res)))
390 return -EFAULT; 394 return -EFAULT;
391 return 0; 395 return 0;
392} 396}
@@ -402,58 +406,57 @@ int drm_resctx( struct inode *inode, struct file *filp,
402 * 406 *
403 * Get a new handle for the context and copy to userspace. 407 * Get a new handle for the context and copy to userspace.
404 */ 408 */
405int drm_addctx( struct inode *inode, struct file *filp, 409int drm_addctx(struct inode *inode, struct file *filp,
406 unsigned int cmd, unsigned long arg ) 410 unsigned int cmd, unsigned long arg)
407{ 411{
408 drm_file_t *priv = filp->private_data; 412 drm_file_t *priv = filp->private_data;
409 drm_device_t *dev = priv->head->dev; 413 drm_device_t *dev = priv->head->dev;
410 drm_ctx_list_t * ctx_entry; 414 drm_ctx_list_t *ctx_entry;
411 drm_ctx_t __user *argp = (void __user *)arg; 415 drm_ctx_t __user *argp = (void __user *)arg;
412 drm_ctx_t ctx; 416 drm_ctx_t ctx;
413 417
414 if ( copy_from_user( &ctx, argp, sizeof(ctx) ) ) 418 if (copy_from_user(&ctx, argp, sizeof(ctx)))
415 return -EFAULT; 419 return -EFAULT;
416 420
417 ctx.handle = drm_ctxbitmap_next( dev ); 421 ctx.handle = drm_ctxbitmap_next(dev);
418 if ( ctx.handle == DRM_KERNEL_CONTEXT ) { 422 if (ctx.handle == DRM_KERNEL_CONTEXT) {
419 /* Skip kernel's context and get a new one. */ 423 /* Skip kernel's context and get a new one. */
420 ctx.handle = drm_ctxbitmap_next( dev ); 424 ctx.handle = drm_ctxbitmap_next(dev);
421 } 425 }
422 DRM_DEBUG( "%d\n", ctx.handle ); 426 DRM_DEBUG("%d\n", ctx.handle);
423 if ( ctx.handle == -1 ) { 427 if (ctx.handle == -1) {
424 DRM_DEBUG( "Not enough free contexts.\n" ); 428 DRM_DEBUG("Not enough free contexts.\n");
425 /* Should this return -EBUSY instead? */ 429 /* Should this return -EBUSY instead? */
426 return -ENOMEM; 430 return -ENOMEM;
427 } 431 }
428 432
429 if ( ctx.handle != DRM_KERNEL_CONTEXT ) 433 if (ctx.handle != DRM_KERNEL_CONTEXT) {
430 {
431 if (dev->driver->context_ctor) 434 if (dev->driver->context_ctor)
432 dev->driver->context_ctor(dev, ctx.handle); 435 dev->driver->context_ctor(dev, ctx.handle);
433 } 436 }
434 437
435 ctx_entry = drm_alloc( sizeof(*ctx_entry), DRM_MEM_CTXLIST ); 438 ctx_entry = drm_alloc(sizeof(*ctx_entry), DRM_MEM_CTXLIST);
436 if ( !ctx_entry ) { 439 if (!ctx_entry) {
437 DRM_DEBUG("out of memory\n"); 440 DRM_DEBUG("out of memory\n");
438 return -ENOMEM; 441 return -ENOMEM;
439 } 442 }
440 443
441 INIT_LIST_HEAD( &ctx_entry->head ); 444 INIT_LIST_HEAD(&ctx_entry->head);
442 ctx_entry->handle = ctx.handle; 445 ctx_entry->handle = ctx.handle;
443 ctx_entry->tag = priv; 446 ctx_entry->tag = priv;
444 447
445 down( &dev->ctxlist_sem ); 448 down(&dev->ctxlist_sem);
446 list_add( &ctx_entry->head, &dev->ctxlist->head ); 449 list_add(&ctx_entry->head, &dev->ctxlist->head);
447 ++dev->ctx_count; 450 ++dev->ctx_count;
448 up( &dev->ctxlist_sem ); 451 up(&dev->ctxlist_sem);
449 452
450 if ( copy_to_user( argp, &ctx, sizeof(ctx) ) ) 453 if (copy_to_user(argp, &ctx, sizeof(ctx)))
451 return -EFAULT; 454 return -EFAULT;
452 return 0; 455 return 0;
453} 456}
454 457
455int drm_modctx( struct inode *inode, struct file *filp, 458int drm_modctx(struct inode *inode, struct file *filp,
456 unsigned int cmd, unsigned long arg ) 459 unsigned int cmd, unsigned long arg)
457{ 460{
458 /* This does nothing */ 461 /* This does nothing */
459 return 0; 462 return 0;
@@ -468,19 +471,19 @@ int drm_modctx( struct inode *inode, struct file *filp,
468 * \param arg user argument pointing to a drm_ctx structure. 471 * \param arg user argument pointing to a drm_ctx structure.
469 * \return zero on success or a negative number on failure. 472 * \return zero on success or a negative number on failure.
470 */ 473 */
471int drm_getctx( struct inode *inode, struct file *filp, 474int drm_getctx(struct inode *inode, struct file *filp,
472 unsigned int cmd, unsigned long arg ) 475 unsigned int cmd, unsigned long arg)
473{ 476{
474 drm_ctx_t __user *argp = (void __user *)arg; 477 drm_ctx_t __user *argp = (void __user *)arg;
475 drm_ctx_t ctx; 478 drm_ctx_t ctx;
476 479
477 if ( copy_from_user( &ctx, argp, sizeof(ctx) ) ) 480 if (copy_from_user(&ctx, argp, sizeof(ctx)))
478 return -EFAULT; 481 return -EFAULT;
479 482
480 /* This is 0, because we don't handle any context flags */ 483 /* This is 0, because we don't handle any context flags */
481 ctx.flags = 0; 484 ctx.flags = 0;
482 485
483 if ( copy_to_user( argp, &ctx, sizeof(ctx) ) ) 486 if (copy_to_user(argp, &ctx, sizeof(ctx)))
484 return -EFAULT; 487 return -EFAULT;
485 return 0; 488 return 0;
486} 489}
@@ -496,18 +499,18 @@ int drm_getctx( struct inode *inode, struct file *filp,
496 * 499 *
497 * Calls context_switch(). 500 * Calls context_switch().
498 */ 501 */
499int drm_switchctx( struct inode *inode, struct file *filp, 502int drm_switchctx(struct inode *inode, struct file *filp,
500 unsigned int cmd, unsigned long arg ) 503 unsigned int cmd, unsigned long arg)
501{ 504{
502 drm_file_t *priv = filp->private_data; 505 drm_file_t *priv = filp->private_data;
503 drm_device_t *dev = priv->head->dev; 506 drm_device_t *dev = priv->head->dev;
504 drm_ctx_t ctx; 507 drm_ctx_t ctx;
505 508
506 if ( copy_from_user( &ctx, (drm_ctx_t __user *)arg, sizeof(ctx) ) ) 509 if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx)))
507 return -EFAULT; 510 return -EFAULT;
508 511
509 DRM_DEBUG( "%d\n", ctx.handle ); 512 DRM_DEBUG("%d\n", ctx.handle);
510 return drm_context_switch( dev, dev->last_context, ctx.handle ); 513 return drm_context_switch(dev, dev->last_context, ctx.handle);
511} 514}
512 515
513/** 516/**
@@ -521,18 +524,18 @@ int drm_switchctx( struct inode *inode, struct file *filp,
521 * 524 *
522 * Calls context_switch_complete(). 525 * Calls context_switch_complete().
523 */ 526 */
524int drm_newctx( struct inode *inode, struct file *filp, 527int drm_newctx(struct inode *inode, struct file *filp,
525 unsigned int cmd, unsigned long arg ) 528 unsigned int cmd, unsigned long arg)
526{ 529{
527 drm_file_t *priv = filp->private_data; 530 drm_file_t *priv = filp->private_data;
528 drm_device_t *dev = priv->head->dev; 531 drm_device_t *dev = priv->head->dev;
529 drm_ctx_t ctx; 532 drm_ctx_t ctx;
530 533
531 if ( copy_from_user( &ctx, (drm_ctx_t __user *)arg, sizeof(ctx) ) ) 534 if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx)))
532 return -EFAULT; 535 return -EFAULT;
533 536
534 DRM_DEBUG( "%d\n", ctx.handle ); 537 DRM_DEBUG("%d\n", ctx.handle);
535 drm_context_switch_complete( dev, ctx.handle ); 538 drm_context_switch_complete(dev, ctx.handle);
536 539
537 return 0; 540 return 0;
538} 541}
@@ -548,42 +551,41 @@ int drm_newctx( struct inode *inode, struct file *filp,
548 * 551 *
549 * If not the special kernel context, calls ctxbitmap_free() to free the specified context. 552 * If not the special kernel context, calls ctxbitmap_free() to free the specified context.
550 */ 553 */
551int drm_rmctx( struct inode *inode, struct file *filp, 554int drm_rmctx(struct inode *inode, struct file *filp,
552 unsigned int cmd, unsigned long arg ) 555 unsigned int cmd, unsigned long arg)
553{ 556{
554 drm_file_t *priv = filp->private_data; 557 drm_file_t *priv = filp->private_data;
555 drm_device_t *dev = priv->head->dev; 558 drm_device_t *dev = priv->head->dev;
556 drm_ctx_t ctx; 559 drm_ctx_t ctx;
557 560
558 if ( copy_from_user( &ctx, (drm_ctx_t __user *)arg, sizeof(ctx) ) ) 561 if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx)))
559 return -EFAULT; 562 return -EFAULT;
560 563
561 DRM_DEBUG( "%d\n", ctx.handle ); 564 DRM_DEBUG("%d\n", ctx.handle);
562 if ( ctx.handle == DRM_KERNEL_CONTEXT + 1 ) { 565 if (ctx.handle == DRM_KERNEL_CONTEXT + 1) {
563 priv->remove_auth_on_close = 1; 566 priv->remove_auth_on_close = 1;
564 } 567 }
565 if ( ctx.handle != DRM_KERNEL_CONTEXT ) { 568 if (ctx.handle != DRM_KERNEL_CONTEXT) {
566 if (dev->driver->context_dtor) 569 if (dev->driver->context_dtor)
567 dev->driver->context_dtor(dev, ctx.handle); 570 dev->driver->context_dtor(dev, ctx.handle);
568 drm_ctxbitmap_free( dev, ctx.handle ); 571 drm_ctxbitmap_free(dev, ctx.handle);
569 } 572 }
570 573
571 down( &dev->ctxlist_sem ); 574 down(&dev->ctxlist_sem);
572 if ( !list_empty( &dev->ctxlist->head ) ) { 575 if (!list_empty(&dev->ctxlist->head)) {
573 drm_ctx_list_t *pos, *n; 576 drm_ctx_list_t *pos, *n;
574 577
575 list_for_each_entry_safe( pos, n, &dev->ctxlist->head, head ) { 578 list_for_each_entry_safe(pos, n, &dev->ctxlist->head, head) {
576 if ( pos->handle == ctx.handle ) { 579 if (pos->handle == ctx.handle) {
577 list_del( &pos->head ); 580 list_del(&pos->head);
578 drm_free( pos, sizeof(*pos), DRM_MEM_CTXLIST ); 581 drm_free(pos, sizeof(*pos), DRM_MEM_CTXLIST);
579 --dev->ctx_count; 582 --dev->ctx_count;
580 } 583 }
581 } 584 }
582 } 585 }
583 up( &dev->ctxlist_sem ); 586 up(&dev->ctxlist_sem);
584 587
585 return 0; 588 return 0;
586} 589}
587 590
588/*@}*/ 591/*@}*/
589
diff --git a/drivers/char/drm/drm_dma.c b/drivers/char/drm/drm_dma.c
index 4a28c053c98b..2afab95ca036 100644
--- a/drivers/char/drm/drm_dma.c
+++ b/drivers/char/drm/drm_dma.c
@@ -1,5 +1,5 @@
1/** 1/**
2 * \file drm_dma.h 2 * \file drm_dma.c
3 * DMA IOCTL and function support 3 * DMA IOCTL and function support
4 * 4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
@@ -37,23 +37,23 @@
37 37
38/** 38/**
39 * Initialize the DMA data. 39 * Initialize the DMA data.
40 * 40 *
41 * \param dev DRM device. 41 * \param dev DRM device.
42 * \return zero on success or a negative value on failure. 42 * \return zero on success or a negative value on failure.
43 * 43 *
44 * Allocate and initialize a drm_device_dma structure. 44 * Allocate and initialize a drm_device_dma structure.
45 */ 45 */
46int drm_dma_setup( drm_device_t *dev ) 46int drm_dma_setup(drm_device_t * dev)
47{ 47{
48 int i; 48 int i;
49 49
50 dev->dma = drm_alloc( sizeof(*dev->dma), DRM_MEM_DRIVER ); 50 dev->dma = drm_alloc(sizeof(*dev->dma), DRM_MEM_DRIVER);
51 if ( !dev->dma ) 51 if (!dev->dma)
52 return -ENOMEM; 52 return -ENOMEM;
53 53
54 memset( dev->dma, 0, sizeof(*dev->dma) ); 54 memset(dev->dma, 0, sizeof(*dev->dma));
55 55
56 for ( i = 0 ; i <= DRM_MAX_ORDER ; i++ ) 56 for (i = 0; i <= DRM_MAX_ORDER; i++)
57 memset(&dev->dma->bufs[i], 0, sizeof(dev->dma->bufs[0])); 57 memset(&dev->dma->bufs[i], 0, sizeof(dev->dma->bufs[0]));
58 58
59 return 0; 59 return 0;
@@ -67,14 +67,15 @@ int drm_dma_setup( drm_device_t *dev )
67 * Free all pages associated with DMA buffers, the buffers and pages lists, and 67 * Free all pages associated with DMA buffers, the buffers and pages lists, and
68 * finally the the drm_device::dma structure itself. 68 * finally the the drm_device::dma structure itself.
69 */ 69 */
70void drm_dma_takedown(drm_device_t *dev) 70void drm_dma_takedown(drm_device_t * dev)
71{ 71{
72 drm_device_dma_t *dma = dev->dma; 72 drm_device_dma_t *dma = dev->dma;
73 int i, j; 73 int i, j;
74 74
75 if (!dma) return; 75 if (!dma)
76 return;
76 77
77 /* Clear dma buffers */ 78 /* Clear dma buffers */
78 for (i = 0; i <= DRM_MAX_ORDER; i++) { 79 for (i = 0; i <= DRM_MAX_ORDER; i++) {
79 if (dma->bufs[i].seg_count) { 80 if (dma->bufs[i].seg_count) {
80 DRM_DEBUG("order %d: buf_count = %d," 81 DRM_DEBUG("order %d: buf_count = %d,"
@@ -85,64 +86,63 @@ void drm_dma_takedown(drm_device_t *dev)
85 for (j = 0; j < dma->bufs[i].seg_count; j++) { 86 for (j = 0; j < dma->bufs[i].seg_count; j++) {
86 if (dma->bufs[i].seglist[j]) { 87 if (dma->bufs[i].seglist[j]) {
87 drm_free_pages(dma->bufs[i].seglist[j], 88 drm_free_pages(dma->bufs[i].seglist[j],
88 dma->bufs[i].page_order, 89 dma->bufs[i].page_order,
89 DRM_MEM_DMA); 90 DRM_MEM_DMA);
90 } 91 }
91 } 92 }
92 drm_free(dma->bufs[i].seglist, 93 drm_free(dma->bufs[i].seglist,
93 dma->bufs[i].seg_count 94 dma->bufs[i].seg_count
94 * sizeof(*dma->bufs[0].seglist), 95 * sizeof(*dma->bufs[0].seglist), DRM_MEM_SEGS);
95 DRM_MEM_SEGS);
96 } 96 }
97 if (dma->bufs[i].buf_count) { 97 if (dma->bufs[i].buf_count) {
98 for (j = 0; j < dma->bufs[i].buf_count; j++) { 98 for (j = 0; j < dma->bufs[i].buf_count; j++) {
99 if (dma->bufs[i].buflist[j].dev_private) { 99 if (dma->bufs[i].buflist[j].dev_private) {
100 drm_free(dma->bufs[i].buflist[j].dev_private, 100 drm_free(dma->bufs[i].buflist[j].
101 dma->bufs[i].buflist[j].dev_priv_size, 101 dev_private,
102 DRM_MEM_BUFS); 102 dma->bufs[i].buflist[j].
103 dev_priv_size, DRM_MEM_BUFS);
103 } 104 }
104 } 105 }
105 drm_free(dma->bufs[i].buflist, 106 drm_free(dma->bufs[i].buflist,
106 dma->bufs[i].buf_count * 107 dma->bufs[i].buf_count *
107 sizeof(*dma->bufs[0].buflist), 108 sizeof(*dma->bufs[0].buflist), DRM_MEM_BUFS);
108 DRM_MEM_BUFS);
109 } 109 }
110 } 110 }
111 111
112 if (dma->buflist) { 112 if (dma->buflist) {
113 drm_free(dma->buflist, 113 drm_free(dma->buflist,
114 dma->buf_count * sizeof(*dma->buflist), 114 dma->buf_count * sizeof(*dma->buflist), DRM_MEM_BUFS);
115 DRM_MEM_BUFS);
116 } 115 }
117 116
118 if (dma->pagelist) { 117 if (dma->pagelist) {
119 drm_free(dma->pagelist, 118 drm_free(dma->pagelist,
120 dma->page_count * sizeof(*dma->pagelist), 119 dma->page_count * sizeof(*dma->pagelist),
121 DRM_MEM_PAGES); 120 DRM_MEM_PAGES);
122 } 121 }
123 drm_free(dev->dma, sizeof(*dev->dma), DRM_MEM_DRIVER); 122 drm_free(dev->dma, sizeof(*dev->dma), DRM_MEM_DRIVER);
124 dev->dma = NULL; 123 dev->dma = NULL;
125} 124}
126 125
127
128/** 126/**
129 * Free a buffer. 127 * Free a buffer.
130 * 128 *
131 * \param dev DRM device. 129 * \param dev DRM device.
132 * \param buf buffer to free. 130 * \param buf buffer to free.
133 * 131 *
134 * Resets the fields of \p buf. 132 * Resets the fields of \p buf.
135 */ 133 */
136void drm_free_buffer(drm_device_t *dev, drm_buf_t *buf) 134void drm_free_buffer(drm_device_t * dev, drm_buf_t * buf)
137{ 135{
138 if (!buf) return; 136 if (!buf)
137 return;
139 138
140 buf->waiting = 0; 139 buf->waiting = 0;
141 buf->pending = 0; 140 buf->pending = 0;
142 buf->filp = NULL; 141 buf->filp = NULL;
143 buf->used = 0; 142 buf->used = 0;
144 143
145 if (drm_core_check_feature(dev, DRIVER_DMA_QUEUE) && waitqueue_active(&buf->dma_wait)) { 144 if (drm_core_check_feature(dev, DRIVER_DMA_QUEUE)
145 && waitqueue_active(&buf->dma_wait)) {
146 wake_up_interruptible(&buf->dma_wait); 146 wake_up_interruptible(&buf->dma_wait);
147 } 147 }
148} 148}
@@ -154,12 +154,13 @@ void drm_free_buffer(drm_device_t *dev, drm_buf_t *buf)
154 * 154 *
155 * Frees each buffer associated with \p filp not already on the hardware. 155 * Frees each buffer associated with \p filp not already on the hardware.
156 */ 156 */
157void drm_core_reclaim_buffers(drm_device_t *dev, struct file *filp) 157void drm_core_reclaim_buffers(drm_device_t * dev, struct file *filp)
158{ 158{
159 drm_device_dma_t *dma = dev->dma; 159 drm_device_dma_t *dma = dev->dma;
160 int i; 160 int i;
161 161
162 if (!dma) return; 162 if (!dma)
163 return;
163 for (i = 0; i < dma->buf_count; i++) { 164 for (i = 0; i < dma->buf_count; i++) {
164 if (dma->buflist[i]->filp == filp) { 165 if (dma->buflist[i]->filp == filp) {
165 switch (dma->buflist[i]->list) { 166 switch (dma->buflist[i]->list) {
@@ -176,5 +177,5 @@ void drm_core_reclaim_buffers(drm_device_t *dev, struct file *filp)
176 } 177 }
177 } 178 }
178} 179}
179EXPORT_SYMBOL(drm_core_reclaim_buffers);
180 180
181EXPORT_SYMBOL(drm_core_reclaim_buffers);
diff --git a/drivers/char/drm/drm_drawable.c b/drivers/char/drm/drm_drawable.c
index e8e8e42be4c7..7857453c4f48 100644
--- a/drivers/char/drm/drm_drawable.c
+++ b/drivers/char/drm/drm_drawable.c
@@ -1,5 +1,5 @@
1/** 1/**
2 * \file drm_drawable.h 2 * \file drm_drawable.c
3 * IOCTLs for drawables 3 * IOCTLs for drawables
4 * 4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
@@ -37,20 +37,20 @@
37 37
38/** No-op. */ 38/** No-op. */
39int drm_adddraw(struct inode *inode, struct file *filp, 39int drm_adddraw(struct inode *inode, struct file *filp,
40 unsigned int cmd, unsigned long arg) 40 unsigned int cmd, unsigned long arg)
41{ 41{
42 drm_draw_t draw; 42 drm_draw_t draw;
43 43
44 draw.handle = 0; /* NOOP */ 44 draw.handle = 0; /* NOOP */
45 DRM_DEBUG("%d\n", draw.handle); 45 DRM_DEBUG("%d\n", draw.handle);
46 if (copy_to_user((drm_draw_t __user *)arg, &draw, sizeof(draw))) 46 if (copy_to_user((drm_draw_t __user *) arg, &draw, sizeof(draw)))
47 return -EFAULT; 47 return -EFAULT;
48 return 0; 48 return 0;
49} 49}
50 50
51/** No-op. */ 51/** No-op. */
52int drm_rmdraw(struct inode *inode, struct file *filp, 52int drm_rmdraw(struct inode *inode, struct file *filp,
53 unsigned int cmd, unsigned long arg) 53 unsigned int cmd, unsigned long arg)
54{ 54{
55 return 0; /* NOOP */ 55 return 0; /* NOOP */
56} 56}
diff --git a/drivers/char/drm/drm_drv.c b/drivers/char/drm/drm_drv.c
index 6ba48f346fcf..26733248ff4a 100644
--- a/drivers/char/drm/drm_drv.c
+++ b/drivers/char/drm/drm_drv.c
@@ -1,5 +1,5 @@
1/** 1/**
2 * \file drm_drv.h 2 * \file drm_drv.c
3 * Generic driver template 3 * Generic driver template
4 * 4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
@@ -55,67 +55,67 @@ static int drm_version(struct inode *inode, struct file *filp,
55 unsigned int cmd, unsigned long arg); 55 unsigned int cmd, unsigned long arg);
56 56
57/** Ioctl table */ 57/** Ioctl table */
58static drm_ioctl_desc_t drm_ioctls[] = { 58static drm_ioctl_desc_t drm_ioctls[] = {
59 [DRM_IOCTL_NR(DRM_IOCTL_VERSION)] = { drm_version, 0, 0 }, 59 [DRM_IOCTL_NR(DRM_IOCTL_VERSION)] = {drm_version, 0, 0},
60 [DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)] = { drm_getunique, 0, 0 }, 60 [DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)] = {drm_getunique, 0, 0},
61 [DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)] = { drm_getmagic, 0, 0 }, 61 [DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)] = {drm_getmagic, 0, 0},
62 [DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)] = { drm_irq_by_busid, 0, 1 }, 62 [DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)] = {drm_irq_by_busid, 0, 1},
63 [DRM_IOCTL_NR(DRM_IOCTL_GET_MAP)] = { drm_getmap, 0, 0 }, 63 [DRM_IOCTL_NR(DRM_IOCTL_GET_MAP)] = {drm_getmap, 0, 0},
64 [DRM_IOCTL_NR(DRM_IOCTL_GET_CLIENT)] = { drm_getclient, 0, 0 }, 64 [DRM_IOCTL_NR(DRM_IOCTL_GET_CLIENT)] = {drm_getclient, 0, 0},
65 [DRM_IOCTL_NR(DRM_IOCTL_GET_STATS)] = { drm_getstats, 0, 0 }, 65 [DRM_IOCTL_NR(DRM_IOCTL_GET_STATS)] = {drm_getstats, 0, 0},
66 [DRM_IOCTL_NR(DRM_IOCTL_SET_VERSION)] = { drm_setversion, 0, 1 }, 66 [DRM_IOCTL_NR(DRM_IOCTL_SET_VERSION)] = {drm_setversion, 0, 1},
67 67
68 [DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)] = { drm_setunique, 1, 1 }, 68 [DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)] = {drm_setunique, 1, 1},
69 [DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = { drm_noop, 1, 1 }, 69 [DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = {drm_noop, 1, 1},
70 [DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = { drm_noop, 1, 1 }, 70 [DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = {drm_noop, 1, 1},
71 [DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = { drm_authmagic, 1, 1 }, 71 [DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = {drm_authmagic, 1, 1},
72 72
73 [DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = { drm_addmap_ioctl,1, 1 }, 73 [DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = {drm_addmap_ioctl, 1, 1},
74 [DRM_IOCTL_NR(DRM_IOCTL_RM_MAP)] = { drm_rmmap_ioctl, 1, 0 }, 74 [DRM_IOCTL_NR(DRM_IOCTL_RM_MAP)] = {drm_rmmap_ioctl, 1, 0},
75 75
76 [DRM_IOCTL_NR(DRM_IOCTL_SET_SAREA_CTX)] = { drm_setsareactx, 1, 1 }, 76 [DRM_IOCTL_NR(DRM_IOCTL_SET_SAREA_CTX)] = {drm_setsareactx, 1, 1},
77 [DRM_IOCTL_NR(DRM_IOCTL_GET_SAREA_CTX)] = { drm_getsareactx, 1, 0 }, 77 [DRM_IOCTL_NR(DRM_IOCTL_GET_SAREA_CTX)] = {drm_getsareactx, 1, 0},
78 78
79 [DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)] = { drm_addctx, 1, 1 }, 79 [DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)] = {drm_addctx, 1, 1},
80 [DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)] = { drm_rmctx, 1, 1 }, 80 [DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)] = {drm_rmctx, 1, 1},
81 [DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)] = { drm_modctx, 1, 1 }, 81 [DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)] = {drm_modctx, 1, 1},
82 [DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)] = { drm_getctx, 1, 0 }, 82 [DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)] = {drm_getctx, 1, 0},
83 [DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)] = { drm_switchctx, 1, 1 }, 83 [DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)] = {drm_switchctx, 1, 1},
84 [DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)] = { drm_newctx, 1, 1 }, 84 [DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)] = {drm_newctx, 1, 1},
85 [DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)] = { drm_resctx, 1, 0 }, 85 [DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)] = {drm_resctx, 1, 0},
86 86
87 [DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)] = { drm_adddraw, 1, 1 }, 87 [DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)] = {drm_adddraw, 1, 1},
88 [DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)] = { drm_rmdraw, 1, 1 }, 88 [DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)] = {drm_rmdraw, 1, 1},
89 89
90 [DRM_IOCTL_NR(DRM_IOCTL_LOCK)] = { drm_lock, 1, 0 }, 90 [DRM_IOCTL_NR(DRM_IOCTL_LOCK)] = {drm_lock, 1, 0},
91 [DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)] = { drm_unlock, 1, 0 }, 91 [DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)] = {drm_unlock, 1, 0},
92 92
93 [DRM_IOCTL_NR(DRM_IOCTL_FINISH)] = { drm_noop, 1, 0 }, 93 [DRM_IOCTL_NR(DRM_IOCTL_FINISH)] = {drm_noop, 1, 0},
94 94
95 [DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)] = { drm_addbufs, 1, 1 }, 95 [DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)] = {drm_addbufs, 1, 1},
96 [DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)] = { drm_markbufs, 1, 1 }, 96 [DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)] = {drm_markbufs, 1, 1},
97 [DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)] = { drm_infobufs, 1, 0 }, 97 [DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)] = {drm_infobufs, 1, 0},
98 [DRM_IOCTL_NR(DRM_IOCTL_MAP_BUFS)] = { drm_mapbufs, 1, 0 }, 98 [DRM_IOCTL_NR(DRM_IOCTL_MAP_BUFS)] = {drm_mapbufs, 1, 0},
99 [DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)] = { drm_freebufs, 1, 0 }, 99 [DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)] = {drm_freebufs, 1, 0},
100 /* The DRM_IOCTL_DMA ioctl should be defined by the driver. */ 100 /* The DRM_IOCTL_DMA ioctl should be defined by the driver. */
101 101
102 [DRM_IOCTL_NR(DRM_IOCTL_CONTROL)] = { drm_control, 1, 1 }, 102 [DRM_IOCTL_NR(DRM_IOCTL_CONTROL)] = {drm_control, 1, 1},
103 103
104#if __OS_HAS_AGP 104#if __OS_HAS_AGP
105 [DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)] = { drm_agp_acquire_ioctl, 1, 1 }, 105 [DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)] = {drm_agp_acquire_ioctl, 1, 1},
106 [DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)] = { drm_agp_release_ioctl, 1, 1 }, 106 [DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)] = {drm_agp_release_ioctl, 1, 1},
107 [DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)] = { drm_agp_enable_ioctl, 1, 1 }, 107 [DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)] = {drm_agp_enable_ioctl, 1, 1},
108 [DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)] = { drm_agp_info_ioctl, 1, 0 }, 108 [DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)] = {drm_agp_info_ioctl, 1, 0},
109 [DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)] = { drm_agp_alloc, 1, 1 }, 109 [DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)] = {drm_agp_alloc, 1, 1},
110 [DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)] = { drm_agp_free, 1, 1 }, 110 [DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)] = {drm_agp_free, 1, 1},
111 [DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)] = { drm_agp_bind, 1, 1 }, 111 [DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)] = {drm_agp_bind, 1, 1},
112 [DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)] = { drm_agp_unbind, 1, 1 }, 112 [DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)] = {drm_agp_unbind, 1, 1},
113#endif 113#endif
114 114
115 [DRM_IOCTL_NR(DRM_IOCTL_SG_ALLOC)] = { drm_sg_alloc, 1, 1 }, 115 [DRM_IOCTL_NR(DRM_IOCTL_SG_ALLOC)] = {drm_sg_alloc, 1, 1},
116 [DRM_IOCTL_NR(DRM_IOCTL_SG_FREE)] = { drm_sg_free, 1, 1 }, 116 [DRM_IOCTL_NR(DRM_IOCTL_SG_FREE)] = {drm_sg_free, 1, 1},
117 117
118 [DRM_IOCTL_NR(DRM_IOCTL_WAIT_VBLANK)] = { drm_wait_vblank, 0, 0 }, 118 [DRM_IOCTL_NR(DRM_IOCTL_WAIT_VBLANK)] = {drm_wait_vblank, 0, 0},
119}; 119};
120 120
121#define DRIVER_IOCTL_COUNT DRM_ARRAY_SIZE( drm_ioctls ) 121#define DRIVER_IOCTL_COUNT DRM_ARRAY_SIZE( drm_ioctls )
@@ -129,17 +129,17 @@ static drm_ioctl_desc_t drm_ioctls[] = {
129 * 129 *
130 * \sa drm_device 130 * \sa drm_device
131 */ 131 */
132int drm_takedown( drm_device_t *dev ) 132int drm_takedown(drm_device_t * dev)
133{ 133{
134 drm_magic_entry_t *pt, *next; 134 drm_magic_entry_t *pt, *next;
135 drm_map_list_t *r_list; 135 drm_map_list_t *r_list;
136 drm_vma_entry_t *vma, *vma_next; 136 drm_vma_entry_t *vma, *vma_next;
137 int i; 137 int i;
138 138
139 DRM_DEBUG( "\n" ); 139 DRM_DEBUG("\n");
140 140
141 if (dev->driver->pretakedown) 141 if (dev->driver->pretakedown)
142 dev->driver->pretakedown(dev); 142 dev->driver->pretakedown(dev);
143 DRM_DEBUG("driver pretakedown completed\n"); 143 DRM_DEBUG("driver pretakedown completed\n");
144 144
145 if (dev->unique) { 145 if (dev->unique) {
@@ -148,95 +148,95 @@ int drm_takedown( drm_device_t *dev )
148 dev->unique_len = 0; 148 dev->unique_len = 0;
149 } 149 }
150 150
151 if ( dev->irq_enabled ) drm_irq_uninstall( dev ); 151 if (dev->irq_enabled)
152 drm_irq_uninstall(dev);
152 153
153 down( &dev->struct_sem ); 154 down(&dev->struct_sem);
154 del_timer( &dev->timer ); 155 del_timer(&dev->timer);
155 156
156 /* Clear pid list */ 157 /* Clear pid list */
157 for ( i = 0 ; i < DRM_HASH_SIZE ; i++ ) { 158 for (i = 0; i < DRM_HASH_SIZE; i++) {
158 for ( pt = dev->magiclist[i].head ; pt ; pt = next ) { 159 for (pt = dev->magiclist[i].head; pt; pt = next) {
159 next = pt->next; 160 next = pt->next;
160 drm_free( pt, sizeof(*pt), DRM_MEM_MAGIC ); 161 drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC);
161 } 162 }
162 dev->magiclist[i].head = dev->magiclist[i].tail = NULL; 163 dev->magiclist[i].head = dev->magiclist[i].tail = NULL;
163 } 164 }
164 165
165 /* Clear AGP information */ 166 /* Clear AGP information */
166 if (drm_core_has_AGP(dev) && dev->agp) { 167 if (drm_core_has_AGP(dev) && dev->agp) {
167 drm_agp_mem_t *entry; 168 drm_agp_mem_t *entry;
168 drm_agp_mem_t *nexte; 169 drm_agp_mem_t *nexte;
169 170
170 /* Remove AGP resources, but leave dev->agp 171 /* Remove AGP resources, but leave dev->agp
171 intact until drv_cleanup is called. */ 172 intact until drv_cleanup is called. */
172 for ( entry = dev->agp->memory ; entry ; entry = nexte ) { 173 for (entry = dev->agp->memory; entry; entry = nexte) {
173 nexte = entry->next; 174 nexte = entry->next;
174 if ( entry->bound ) drm_unbind_agp( entry->memory ); 175 if (entry->bound)
175 drm_free_agp( entry->memory, entry->pages ); 176 drm_unbind_agp(entry->memory);
176 drm_free( entry, sizeof(*entry), DRM_MEM_AGPLISTS ); 177 drm_free_agp(entry->memory, entry->pages);
178 drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS);
177 } 179 }
178 dev->agp->memory = NULL; 180 dev->agp->memory = NULL;
179 181
180 if (dev->agp->acquired) 182 if (dev->agp->acquired)
181 drm_agp_release(dev); 183 drm_agp_release(dev);
182 184
183 dev->agp->acquired = 0; 185 dev->agp->acquired = 0;
184 dev->agp->enabled = 0; 186 dev->agp->enabled = 0;
185 } 187 }
186 if (drm_core_check_feature(dev, DRIVER_SG) && dev->sg) { 188 if (drm_core_check_feature(dev, DRIVER_SG) && dev->sg) {
187 drm_sg_cleanup(dev->sg); 189 drm_sg_cleanup(dev->sg);
188 dev->sg = NULL; 190 dev->sg = NULL;
189 } 191 }
190 192
191 /* Clear vma list (only built for debugging) */ 193 /* Clear vma list (only built for debugging) */
192 if ( dev->vmalist ) { 194 if (dev->vmalist) {
193 for ( vma = dev->vmalist ; vma ; vma = vma_next ) { 195 for (vma = dev->vmalist; vma; vma = vma_next) {
194 vma_next = vma->next; 196 vma_next = vma->next;
195 drm_free( vma, sizeof(*vma), DRM_MEM_VMAS ); 197 drm_free(vma, sizeof(*vma), DRM_MEM_VMAS);
196 } 198 }
197 dev->vmalist = NULL; 199 dev->vmalist = NULL;
198 } 200 }
199 201
200 if( dev->maplist ) { 202 if (dev->maplist) {
201 while (!list_empty(&dev->maplist->head)) { 203 while (!list_empty(&dev->maplist->head)) {
202 struct list_head *list = dev->maplist->head.next; 204 struct list_head *list = dev->maplist->head.next;
203 r_list = list_entry(list, drm_map_list_t, head); 205 r_list = list_entry(list, drm_map_list_t, head);
204 drm_rmmap_locked(dev, r_list->map); 206 drm_rmmap_locked(dev, r_list->map);
205 } 207 }
206 } 208 }
207 209
208 if (drm_core_check_feature(dev, DRIVER_DMA_QUEUE) && dev->queuelist ) { 210 if (drm_core_check_feature(dev, DRIVER_DMA_QUEUE) && dev->queuelist) {
209 for ( i = 0 ; i < dev->queue_count ; i++ ) { 211 for (i = 0; i < dev->queue_count; i++) {
210 if ( dev->queuelist[i] ) { 212 if (dev->queuelist[i]) {
211 drm_free( dev->queuelist[i], 213 drm_free(dev->queuelist[i],
212 sizeof(*dev->queuelist[0]), 214 sizeof(*dev->queuelist[0]),
213 DRM_MEM_QUEUES ); 215 DRM_MEM_QUEUES);
214 dev->queuelist[i] = NULL; 216 dev->queuelist[i] = NULL;
215 } 217 }
216 } 218 }
217 drm_free( dev->queuelist, 219 drm_free(dev->queuelist,
218 dev->queue_slots * sizeof(*dev->queuelist), 220 dev->queue_slots * sizeof(*dev->queuelist),
219 DRM_MEM_QUEUES ); 221 DRM_MEM_QUEUES);
220 dev->queuelist = NULL; 222 dev->queuelist = NULL;
221 } 223 }
222 dev->queue_count = 0; 224 dev->queue_count = 0;
223 225
224 if (drm_core_check_feature(dev, DRIVER_HAVE_DMA)) 226 if (drm_core_check_feature(dev, DRIVER_HAVE_DMA))
225 drm_dma_takedown( dev ); 227 drm_dma_takedown(dev);
226 228
227 if ( dev->lock.hw_lock ) { 229 if (dev->lock.hw_lock) {
228 dev->sigdata.lock = dev->lock.hw_lock = NULL; /* SHM removed */ 230 dev->sigdata.lock = dev->lock.hw_lock = NULL; /* SHM removed */
229 dev->lock.filp = NULL; 231 dev->lock.filp = NULL;
230 wake_up_interruptible( &dev->lock.lock_queue ); 232 wake_up_interruptible(&dev->lock.lock_queue);
231 } 233 }
232 up( &dev->struct_sem ); 234 up(&dev->struct_sem);
233 235
234 DRM_DEBUG("takedown completed\n"); 236 DRM_DEBUG("takedown completed\n");
235 return 0; 237 return 0;
236} 238}
237 239
238
239
240/** 240/**
241 * Module initialization. Called via init_module at module load time, or via 241 * Module initialization. Called via init_module at module load time, or via
242 * linux/init/main.c (this is not currently supported). 242 * linux/init/main.c (this is not currently supported).
@@ -246,26 +246,28 @@ int drm_takedown( drm_device_t *dev )
246 * Initializes an array of drm_device structures, and attempts to 246 * Initializes an array of drm_device structures, and attempts to
247 * initialize all available devices, using consecutive minors, registering the 247 * initialize all available devices, using consecutive minors, registering the
248 * stubs and initializing the AGP device. 248 * stubs and initializing the AGP device.
249 * 249 *
250 * Expands the \c DRIVER_PREINIT and \c DRIVER_POST_INIT macros before and 250 * Expands the \c DRIVER_PREINIT and \c DRIVER_POST_INIT macros before and
251 * after the initialization for driver customization. 251 * after the initialization for driver customization.
252 */ 252 */
253int drm_init( struct drm_driver *driver ) 253int drm_init(struct drm_driver *driver)
254{ 254{
255 struct pci_dev *pdev = NULL; 255 struct pci_dev *pdev = NULL;
256 struct pci_device_id *pid; 256 struct pci_device_id *pid;
257 int i; 257 int i;
258 258
259 DRM_DEBUG( "\n" ); 259 DRM_DEBUG("\n");
260 260
261 drm_mem_init(); 261 drm_mem_init();
262 262
263 for (i=0; driver->pci_driver.id_table[i].vendor != 0; i++) { 263 for (i = 0; driver->pci_driver.id_table[i].vendor != 0; i++) {
264 pid = (struct pci_device_id *)&driver->pci_driver.id_table[i]; 264 pid = (struct pci_device_id *)&driver->pci_driver.id_table[i];
265 265
266 pdev=NULL; 266 pdev = NULL;
267 /* pass back in pdev to account for multiple identical cards */ 267 /* pass back in pdev to account for multiple identical cards */
268 while ((pdev = pci_get_subsys(pid->vendor, pid->device, pid->subvendor, pid->subdevice, pdev)) != NULL) { 268 while ((pdev =
269 pci_get_subsys(pid->vendor, pid->device, pid->subvendor,
270 pid->subdevice, pdev)) != NULL) {
269 /* stealth mode requires a manual probe */ 271 /* stealth mode requires a manual probe */
270 pci_dev_get(pdev); 272 pci_dev_get(pdev);
271 drm_get_dev(pdev, pid, driver); 273 drm_get_dev(pdev, pid, driver);
@@ -273,62 +275,63 @@ int drm_init( struct drm_driver *driver )
273 } 275 }
274 return 0; 276 return 0;
275} 277}
278
276EXPORT_SYMBOL(drm_init); 279EXPORT_SYMBOL(drm_init);
277 280
278/** 281/**
279 * Called via cleanup_module() at module unload time. 282 * Called via cleanup_module() at module unload time.
280 * 283 *
281 * Cleans up all DRM device, calling takedown(). 284 * Cleans up all DRM device, calling takedown().
282 * 285 *
283 * \sa drm_init 286 * \sa drm_init
284 */ 287 */
285static void drm_cleanup( drm_device_t *dev ) 288static void drm_cleanup(drm_device_t * dev)
286{ 289{
287 DRM_DEBUG( "\n" ); 290 DRM_DEBUG("\n");
288 291
289 if (!dev) { 292 if (!dev) {
290 DRM_ERROR("cleanup called no dev\n"); 293 DRM_ERROR("cleanup called no dev\n");
291 return; 294 return;
292 } 295 }
293 296
294 drm_takedown( dev ); 297 drm_takedown(dev);
295 298
296 if (dev->maplist) { 299 if (dev->maplist) {
297 drm_free(dev->maplist, sizeof(*dev->maplist), DRM_MEM_MAPS); 300 drm_free(dev->maplist, sizeof(*dev->maplist), DRM_MEM_MAPS);
298 dev->maplist = NULL; 301 dev->maplist = NULL;
299 } 302 }
300 303
301 drm_ctxbitmap_cleanup( dev ); 304 drm_ctxbitmap_cleanup(dev);
302 305
303 if (drm_core_has_MTRR(dev) && drm_core_has_AGP(dev) && 306 if (drm_core_has_MTRR(dev) && drm_core_has_AGP(dev) &&
304 dev->agp && dev->agp->agp_mtrr >= 0) { 307 dev->agp && dev->agp->agp_mtrr >= 0) {
305 int retval; 308 int retval;
306 retval = mtrr_del( dev->agp->agp_mtrr, 309 retval = mtrr_del(dev->agp->agp_mtrr,
307 dev->agp->agp_info.aper_base, 310 dev->agp->agp_info.aper_base,
308 dev->agp->agp_info.aper_size*1024*1024 ); 311 dev->agp->agp_info.aper_size * 1024 * 1024);
309 DRM_DEBUG( "mtrr_del=%d\n", retval ); 312 DRM_DEBUG("mtrr_del=%d\n", retval);
310 } 313 }
311 314
312 if (drm_core_has_AGP(dev) && dev->agp ) { 315 if (drm_core_has_AGP(dev) && dev->agp) {
313 drm_free( dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS ); 316 drm_free(dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS);
314 dev->agp = NULL; 317 dev->agp = NULL;
315 } 318 }
316 319
317 if (dev->driver->postcleanup) 320 if (dev->driver->postcleanup)
318 dev->driver->postcleanup(dev); 321 dev->driver->postcleanup(dev);
319 322
320 drm_put_head(&dev->primary); 323 drm_put_head(&dev->primary);
321 if ( drm_put_dev(dev) ) 324 if (drm_put_dev(dev))
322 DRM_ERROR( "Cannot unload module\n" ); 325 DRM_ERROR("Cannot unload module\n");
323} 326}
324 327
325void drm_exit (struct drm_driver *driver) 328void drm_exit(struct drm_driver *driver)
326{ 329{
327 int i; 330 int i;
328 drm_device_t *dev = NULL; 331 drm_device_t *dev = NULL;
329 drm_head_t *head; 332 drm_head_t *head;
330 333
331 DRM_DEBUG( "\n" ); 334 DRM_DEBUG("\n");
332 335
333 for (i = 0; i < drm_cards_limit; i++) { 336 for (i = 0; i < drm_cards_limit; i++) {
334 head = drm_heads[i]; 337 head = drm_heads[i];
@@ -336,9 +339,9 @@ void drm_exit (struct drm_driver *driver)
336 continue; 339 continue;
337 if (!head->dev) 340 if (!head->dev)
338 continue; 341 continue;
339 if (head->dev->driver!=driver) 342 if (head->dev->driver != driver)
340 continue; 343 continue;
341 dev=head->dev; 344 dev = head->dev;
342 } 345 }
343 if (dev) { 346 if (dev) {
344 /* release the pci driver */ 347 /* release the pci driver */
@@ -346,32 +349,35 @@ void drm_exit (struct drm_driver *driver)
346 pci_dev_put(dev->pdev); 349 pci_dev_put(dev->pdev);
347 drm_cleanup(dev); 350 drm_cleanup(dev);
348 } 351 }
349 DRM_INFO( "Module unloaded\n" ); 352 DRM_INFO("Module unloaded\n");
350} 353}
354
351EXPORT_SYMBOL(drm_exit); 355EXPORT_SYMBOL(drm_exit);
352 356
353/** File operations structure */ 357/** File operations structure */
354static struct file_operations drm_stub_fops = { 358static struct file_operations drm_stub_fops = {
355 .owner = THIS_MODULE, 359 .owner = THIS_MODULE,
356 .open = drm_stub_open 360 .open = drm_stub_open
357}; 361};
358 362
359static int __init drm_core_init(void) 363static int __init drm_core_init(void)
360{ 364{
361 int ret = -ENOMEM; 365 int ret = -ENOMEM;
362 366
363 drm_cards_limit = (drm_cards_limit < DRM_MAX_MINOR + 1 ? drm_cards_limit : DRM_MAX_MINOR + 1); 367 drm_cards_limit =
364 drm_heads = drm_calloc(drm_cards_limit, 368 (drm_cards_limit <
365 sizeof(*drm_heads), DRM_MEM_STUB); 369 DRM_MAX_MINOR + 1 ? drm_cards_limit : DRM_MAX_MINOR + 1);
366 if(!drm_heads) 370 drm_heads =
371 drm_calloc(drm_cards_limit, sizeof(*drm_heads), DRM_MEM_STUB);
372 if (!drm_heads)
367 goto err_p1; 373 goto err_p1;
368 374
369 if (register_chrdev(DRM_MAJOR, "drm", &drm_stub_fops)) 375 if (register_chrdev(DRM_MAJOR, "drm", &drm_stub_fops))
370 goto err_p1; 376 goto err_p1;
371 377
372 drm_class = drm_sysfs_create(THIS_MODULE, "drm"); 378 drm_class = drm_sysfs_create(THIS_MODULE, "drm");
373 if (IS_ERR(drm_class)) { 379 if (IS_ERR(drm_class)) {
374 printk (KERN_ERR "DRM: Error creating drm class.\n"); 380 printk(KERN_ERR "DRM: Error creating drm class.\n");
375 ret = PTR_ERR(drm_class); 381 ret = PTR_ERR(drm_class);
376 goto err_p2; 382 goto err_p2;
377 } 383 }
@@ -382,35 +388,31 @@ static int __init drm_core_init(void)
382 ret = -1; 388 ret = -1;
383 goto err_p3; 389 goto err_p3;
384 } 390 }
385 391
386 DRM_INFO( "Initialized %s %d.%d.%d %s\n", 392 DRM_INFO("Initialized %s %d.%d.%d %s\n",
387 CORE_NAME, CORE_MAJOR, CORE_MINOR, CORE_PATCHLEVEL, 393 CORE_NAME, CORE_MAJOR, CORE_MINOR, CORE_PATCHLEVEL, CORE_DATE);
388 CORE_DATE);
389 return 0; 394 return 0;
390err_p3: 395 err_p3:
391 drm_sysfs_destroy(drm_class); 396 drm_sysfs_destroy(drm_class);
392err_p2: 397 err_p2:
393 unregister_chrdev(DRM_MAJOR, "drm"); 398 unregister_chrdev(DRM_MAJOR, "drm");
394 drm_free(drm_heads, sizeof(*drm_heads) * drm_cards_limit, DRM_MEM_STUB); 399 drm_free(drm_heads, sizeof(*drm_heads) * drm_cards_limit, DRM_MEM_STUB);
395err_p1: 400 err_p1:
396 return ret; 401 return ret;
397} 402}
398 403
399static void __exit drm_core_exit (void) 404static void __exit drm_core_exit(void)
400{ 405{
401 remove_proc_entry("dri", NULL); 406 remove_proc_entry("dri", NULL);
402 drm_sysfs_destroy(drm_class); 407 drm_sysfs_destroy(drm_class);
403 408
404 unregister_chrdev(DRM_MAJOR, "drm"); 409 unregister_chrdev(DRM_MAJOR, "drm");
405 410
406 drm_free(drm_heads, sizeof(*drm_heads) * 411 drm_free(drm_heads, sizeof(*drm_heads) * drm_cards_limit, DRM_MEM_STUB);
407 drm_cards_limit, DRM_MEM_STUB);
408} 412}
409 413
410 414module_init(drm_core_init);
411module_init( drm_core_init ); 415module_exit(drm_core_exit);
412module_exit( drm_core_exit );
413
414 416
415/** 417/**
416 * Get version information 418 * Get version information
@@ -423,8 +425,8 @@ module_exit( drm_core_exit );
423 * 425 *
424 * Fills in the version information in \p arg. 426 * Fills in the version information in \p arg.
425 */ 427 */
426static int drm_version( struct inode *inode, struct file *filp, 428static int drm_version(struct inode *inode, struct file *filp,
427 unsigned int cmd, unsigned long arg ) 429 unsigned int cmd, unsigned long arg)
428{ 430{
429 drm_file_t *priv = filp->private_data; 431 drm_file_t *priv = filp->private_data;
430 drm_device_t *dev = priv->head->dev; 432 drm_device_t *dev = priv->head->dev;
@@ -432,21 +434,19 @@ static int drm_version( struct inode *inode, struct file *filp,
432 drm_version_t version; 434 drm_version_t version;
433 int ret; 435 int ret;
434 436
435 if ( copy_from_user( &version, argp, sizeof(version) ) ) 437 if (copy_from_user(&version, argp, sizeof(version)))
436 return -EFAULT; 438 return -EFAULT;
437 439
438 /* version is a required function to return the personality module version */ 440 /* version is a required function to return the personality module version */
439 if ((ret = dev->driver->version(&version))) 441 if ((ret = dev->driver->version(&version)))
440 return ret; 442 return ret;
441 443
442 if ( copy_to_user( argp, &version, sizeof(version) ) ) 444 if (copy_to_user(argp, &version, sizeof(version)))
443 return -EFAULT; 445 return -EFAULT;
444 return 0; 446 return 0;
445} 447}
446 448
447 449/**
448
449/**
450 * Called whenever a process performs an ioctl on /dev/drm. 450 * Called whenever a process performs an ioctl on /dev/drm.
451 * 451 *
452 * \param inode device inode. 452 * \param inode device inode.
@@ -458,8 +458,8 @@ static int drm_version( struct inode *inode, struct file *filp,
458 * Looks up the ioctl function in the ::ioctls table, checking for root 458 * Looks up the ioctl function in the ::ioctls table, checking for root
459 * previleges if so required, and dispatches to the respective function. 459 * previleges if so required, and dispatches to the respective function.
460 */ 460 */
461int drm_ioctl( struct inode *inode, struct file *filp, 461int drm_ioctl(struct inode *inode, struct file *filp,
462 unsigned int cmd, unsigned long arg ) 462 unsigned int cmd, unsigned long arg)
463{ 463{
464 drm_file_t *priv = filp->private_data; 464 drm_file_t *priv = filp->private_data;
465 drm_device_t *dev = priv->head->dev; 465 drm_device_t *dev = priv->head->dev;
@@ -468,40 +468,43 @@ int drm_ioctl( struct inode *inode, struct file *filp,
468 unsigned int nr = DRM_IOCTL_NR(cmd); 468 unsigned int nr = DRM_IOCTL_NR(cmd);
469 int retcode = -EINVAL; 469 int retcode = -EINVAL;
470 470
471 atomic_inc( &dev->ioctl_count ); 471 atomic_inc(&dev->ioctl_count);
472 atomic_inc( &dev->counts[_DRM_STAT_IOCTLS] ); 472 atomic_inc(&dev->counts[_DRM_STAT_IOCTLS]);
473 ++priv->ioctl_count; 473 ++priv->ioctl_count;
474 474
475 DRM_DEBUG( "pid=%d, cmd=0x%02x, nr=0x%02x, dev 0x%lx, auth=%d\n", 475 DRM_DEBUG("pid=%d, cmd=0x%02x, nr=0x%02x, dev 0x%lx, auth=%d\n",
476 current->pid, cmd, nr, (long)old_encode_dev(priv->head->device), 476 current->pid, cmd, nr,
477 priv->authenticated ); 477 (long)old_encode_dev(priv->head->device),
478 478 priv->authenticated);
479
479 if (nr < DRIVER_IOCTL_COUNT) 480 if (nr < DRIVER_IOCTL_COUNT)
480 ioctl = &drm_ioctls[nr]; 481 ioctl = &drm_ioctls[nr];
481 else if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) 482 else if ((nr >= DRM_COMMAND_BASE)
483 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls))
482 ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE]; 484 ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE];
483 else 485 else
484 goto err_i1; 486 goto err_i1;
485 487
486 func = ioctl->func; 488 func = ioctl->func;
487 /* is there a local override? */ 489 /* is there a local override? */
488 if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->driver->dma_ioctl) 490 if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->driver->dma_ioctl)
489 func = dev->driver->dma_ioctl; 491 func = dev->driver->dma_ioctl;
490 492
491 if ( !func ) { 493 if (!func) {
492 DRM_DEBUG( "no function\n" ); 494 DRM_DEBUG("no function\n");
493 retcode = -EINVAL; 495 retcode = -EINVAL;
494 } else if ( ( ioctl->root_only && !capable( CAP_SYS_ADMIN ) )|| 496 } else if ((ioctl->root_only && !capable(CAP_SYS_ADMIN)) ||
495 ( ioctl->auth_needed && !priv->authenticated ) ) { 497 (ioctl->auth_needed && !priv->authenticated)) {
496 retcode = -EACCES; 498 retcode = -EACCES;
497 } else { 499 } else {
498 retcode = func( inode, filp, cmd, arg ); 500 retcode = func(inode, filp, cmd, arg);
499 } 501 }
500 502
501err_i1: 503 err_i1:
502 atomic_dec( &dev->ioctl_count ); 504 atomic_dec(&dev->ioctl_count);
503 if (retcode) DRM_DEBUG( "ret = %x\n", retcode); 505 if (retcode)
506 DRM_DEBUG("ret = %x\n", retcode);
504 return retcode; 507 return retcode;
505} 508}
506EXPORT_SYMBOL(drm_ioctl);
507 509
510EXPORT_SYMBOL(drm_ioctl);
diff --git a/drivers/char/drm/drm_fops.c b/drivers/char/drm/drm_fops.c
index a1f4e9cd64ed..e0124a9ba14a 100644
--- a/drivers/char/drm/drm_fops.c
+++ b/drivers/char/drm/drm_fops.c
@@ -1,7 +1,7 @@
1/** 1/**
2 * \file drm_fops.h 2 * \file drm_fops.c
3 * File operations for DRM 3 * File operations for DRM
4 * 4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
6 * \author Daryll Strauss <daryll@valinux.com> 6 * \author Daryll Strauss <daryll@valinux.com>
7 * \author Gareth Hughes <gareth@valinux.com> 7 * \author Gareth Hughes <gareth@valinux.com>
@@ -37,49 +37,48 @@
37#include "drmP.h" 37#include "drmP.h"
38#include <linux/poll.h> 38#include <linux/poll.h>
39 39
40static int drm_open_helper(struct inode *inode, struct file *filp, drm_device_t *dev); 40static int drm_open_helper(struct inode *inode, struct file *filp,
41 drm_device_t * dev);
41 42
42static int drm_setup( drm_device_t *dev ) 43static int drm_setup(drm_device_t * dev)
43{ 44{
44 int i; 45 int i;
45 int ret; 46 int ret;
46 47
47 if (dev->driver->presetup) 48 if (dev->driver->presetup) {
48 { 49 ret = dev->driver->presetup(dev);
49 ret=dev->driver->presetup(dev); 50 if (ret != 0)
50 if (ret!=0)
51 return ret; 51 return ret;
52 } 52 }
53 53
54 atomic_set( &dev->ioctl_count, 0 ); 54 atomic_set(&dev->ioctl_count, 0);
55 atomic_set( &dev->vma_count, 0 ); 55 atomic_set(&dev->vma_count, 0);
56 dev->buf_use = 0; 56 dev->buf_use = 0;
57 atomic_set( &dev->buf_alloc, 0 ); 57 atomic_set(&dev->buf_alloc, 0);
58 58
59 if (drm_core_check_feature(dev, DRIVER_HAVE_DMA)) 59 if (drm_core_check_feature(dev, DRIVER_HAVE_DMA)) {
60 { 60 i = drm_dma_setup(dev);
61 i = drm_dma_setup( dev ); 61 if (i < 0)
62 if ( i < 0 )
63 return i; 62 return i;
64 } 63 }
65 64
66 for ( i = 0 ; i < DRM_ARRAY_SIZE(dev->counts) ; i++ ) 65 for (i = 0; i < DRM_ARRAY_SIZE(dev->counts); i++)
67 atomic_set( &dev->counts[i], 0 ); 66 atomic_set(&dev->counts[i], 0);
68 67
69 for ( i = 0 ; i < DRM_HASH_SIZE ; i++ ) { 68 for (i = 0; i < DRM_HASH_SIZE; i++) {
70 dev->magiclist[i].head = NULL; 69 dev->magiclist[i].head = NULL;
71 dev->magiclist[i].tail = NULL; 70 dev->magiclist[i].tail = NULL;
72 } 71 }
73 72
74 dev->ctxlist = drm_alloc(sizeof(*dev->ctxlist), 73 dev->ctxlist = drm_alloc(sizeof(*dev->ctxlist), DRM_MEM_CTXLIST);
75 DRM_MEM_CTXLIST); 74 if (dev->ctxlist == NULL)
76 if(dev->ctxlist == NULL) return -ENOMEM; 75 return -ENOMEM;
77 memset(dev->ctxlist, 0, sizeof(*dev->ctxlist)); 76 memset(dev->ctxlist, 0, sizeof(*dev->ctxlist));
78 INIT_LIST_HEAD(&dev->ctxlist->head); 77 INIT_LIST_HEAD(&dev->ctxlist->head);
79 78
80 dev->vmalist = NULL; 79 dev->vmalist = NULL;
81 dev->sigdata.lock = dev->lock.hw_lock = NULL; 80 dev->sigdata.lock = dev->lock.hw_lock = NULL;
82 init_waitqueue_head( &dev->lock.lock_queue ); 81 init_waitqueue_head(&dev->lock.lock_queue);
83 dev->queue_count = 0; 82 dev->queue_count = 0;
84 dev->queue_reserved = 0; 83 dev->queue_reserved = 0;
85 dev->queue_slots = 0; 84 dev->queue_slots = 0;
@@ -91,7 +90,7 @@ static int drm_setup( drm_device_t *dev )
91 dev->last_context = 0; 90 dev->last_context = 0;
92 dev->last_switch = 0; 91 dev->last_switch = 0;
93 dev->last_checked = 0; 92 dev->last_checked = 0;
94 init_waitqueue_head( &dev->context_wait ); 93 init_waitqueue_head(&dev->context_wait);
95 dev->if_version = 0; 94 dev->if_version = 0;
96 95
97 dev->ctx_start = 0; 96 dev->ctx_start = 0;
@@ -101,14 +100,14 @@ static int drm_setup( drm_device_t *dev )
101 dev->buf_wp = dev->buf; 100 dev->buf_wp = dev->buf;
102 dev->buf_end = dev->buf + DRM_BSZ; 101 dev->buf_end = dev->buf + DRM_BSZ;
103 dev->buf_async = NULL; 102 dev->buf_async = NULL;
104 init_waitqueue_head( &dev->buf_readers ); 103 init_waitqueue_head(&dev->buf_readers);
105 init_waitqueue_head( &dev->buf_writers ); 104 init_waitqueue_head(&dev->buf_writers);
106 105
107 DRM_DEBUG( "\n" ); 106 DRM_DEBUG("\n");
108 107
109 /* 108 /*
110 * The kernel's context could be created here, but is now created 109 * The kernel's context could be created here, but is now created
111 * in drm_dma_enqueue. This is more resource-efficient for 110 * in drm_dma_enqueue. This is more resource-efficient for
112 * hardware that does not do DMA, but may mean that 111 * hardware that does not do DMA, but may mean that
113 * drm_select_queue fails between the time the interrupt is 112 * drm_select_queue fails between the time the interrupt is
114 * initialized and the time the queues are initialized. 113 * initialized and the time the queues are initialized.
@@ -121,7 +120,7 @@ static int drm_setup( drm_device_t *dev )
121 120
122/** 121/**
123 * Open file. 122 * Open file.
124 * 123 *
125 * \param inode device inode 124 * \param inode device inode
126 * \param filp file pointer. 125 * \param filp file pointer.
127 * \return zero on success or a negative number on failure. 126 * \return zero on success or a negative number on failure.
@@ -130,7 +129,7 @@ static int drm_setup( drm_device_t *dev )
130 * increments the device open count. If the open count was previous at zero, 129 * increments the device open count. If the open count was previous at zero,
131 * i.e., it's the first that the device is open, then calls setup(). 130 * i.e., it's the first that the device is open, then calls setup().
132 */ 131 */
133int drm_open( struct inode *inode, struct file *filp ) 132int drm_open(struct inode *inode, struct file *filp)
134{ 133{
135 drm_device_t *dev = NULL; 134 drm_device_t *dev = NULL;
136 int minor = iminor(inode); 135 int minor = iminor(inode);
@@ -138,26 +137,27 @@ int drm_open( struct inode *inode, struct file *filp )
138 137
139 if (!((minor >= 0) && (minor < drm_cards_limit))) 138 if (!((minor >= 0) && (minor < drm_cards_limit)))
140 return -ENODEV; 139 return -ENODEV;
141 140
142 if (!drm_heads[minor]) 141 if (!drm_heads[minor])
143 return -ENODEV; 142 return -ENODEV;
144 143
145 if (!(dev = drm_heads[minor]->dev)) 144 if (!(dev = drm_heads[minor]->dev))
146 return -ENODEV; 145 return -ENODEV;
147 146
148 retcode = drm_open_helper( inode, filp, dev ); 147 retcode = drm_open_helper(inode, filp, dev);
149 if ( !retcode ) { 148 if (!retcode) {
150 atomic_inc( &dev->counts[_DRM_STAT_OPENS] ); 149 atomic_inc(&dev->counts[_DRM_STAT_OPENS]);
151 spin_lock( &dev->count_lock ); 150 spin_lock(&dev->count_lock);
152 if ( !dev->open_count++ ) { 151 if (!dev->open_count++) {
153 spin_unlock( &dev->count_lock ); 152 spin_unlock(&dev->count_lock);
154 return drm_setup( dev ); 153 return drm_setup(dev);
155 } 154 }
156 spin_unlock( &dev->count_lock ); 155 spin_unlock(&dev->count_lock);
157 } 156 }
158 157
159 return retcode; 158 return retcode;
160} 159}
160
161EXPORT_SYMBOL(drm_open); 161EXPORT_SYMBOL(drm_open);
162 162
163/** 163/**
@@ -172,7 +172,7 @@ EXPORT_SYMBOL(drm_open);
172 * data from its list and free it. Decreases the open count and if it reaches 172 * data from its list and free it. Decreases the open count and if it reaches
173 * zero calls takedown(). 173 * zero calls takedown().
174 */ 174 */
175int drm_release( struct inode *inode, struct file *filp ) 175int drm_release(struct inode *inode, struct file *filp)
176{ 176{
177 drm_file_t *priv = filp->private_data; 177 drm_file_t *priv = filp->private_data;
178 drm_device_t *dev; 178 drm_device_t *dev;
@@ -181,7 +181,7 @@ int drm_release( struct inode *inode, struct file *filp )
181 lock_kernel(); 181 lock_kernel();
182 dev = priv->head->dev; 182 dev = priv->head->dev;
183 183
184 DRM_DEBUG( "open_count = %d\n", dev->open_count ); 184 DRM_DEBUG("open_count = %d\n", dev->open_count);
185 185
186 if (dev->driver->prerelease) 186 if (dev->driver->prerelease)
187 dev->driver->prerelease(dev, filp); 187 dev->driver->prerelease(dev, filp);
@@ -190,194 +190,199 @@ int drm_release( struct inode *inode, struct file *filp )
190 * Begin inline drm_release 190 * Begin inline drm_release
191 */ 191 */
192 192
193 DRM_DEBUG( "pid = %d, device = 0x%lx, open_count = %d\n", 193 DRM_DEBUG("pid = %d, device = 0x%lx, open_count = %d\n",
194 current->pid, (long)old_encode_dev(priv->head->device), dev->open_count ); 194 current->pid, (long)old_encode_dev(priv->head->device),
195 dev->open_count);
196
197 if (priv->lock_count && dev->lock.hw_lock &&
198 _DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock) &&
199 dev->lock.filp == filp) {
200 DRM_DEBUG("File %p released, freeing lock for context %d\n",
201 filp, _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock));
195 202
196 if ( priv->lock_count && dev->lock.hw_lock &&
197 _DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock) &&
198 dev->lock.filp == filp ) {
199 DRM_DEBUG( "File %p released, freeing lock for context %d\n",
200 filp,
201 _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock) );
202
203 if (dev->driver->release) 203 if (dev->driver->release)
204 dev->driver->release(dev, filp); 204 dev->driver->release(dev, filp);
205 205
206 drm_lock_free( dev, &dev->lock.hw_lock->lock, 206 drm_lock_free(dev, &dev->lock.hw_lock->lock,
207 _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock) ); 207 _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock));
208 208
209 /* FIXME: may require heavy-handed reset of 209 /* FIXME: may require heavy-handed reset of
210 hardware at this point, possibly 210 hardware at this point, possibly
211 processed via a callback to the X 211 processed via a callback to the X
212 server. */ 212 server. */
213 } 213 } else if (dev->driver->release && priv->lock_count
214 else if ( dev->driver->release && priv->lock_count && dev->lock.hw_lock ) { 214 && dev->lock.hw_lock) {
215 /* The lock is required to reclaim buffers */ 215 /* The lock is required to reclaim buffers */
216 DECLARE_WAITQUEUE( entry, current ); 216 DECLARE_WAITQUEUE(entry, current);
217 217
218 add_wait_queue( &dev->lock.lock_queue, &entry ); 218 add_wait_queue(&dev->lock.lock_queue, &entry);
219 for (;;) { 219 for (;;) {
220 __set_current_state(TASK_INTERRUPTIBLE); 220 __set_current_state(TASK_INTERRUPTIBLE);
221 if ( !dev->lock.hw_lock ) { 221 if (!dev->lock.hw_lock) {
222 /* Device has been unregistered */ 222 /* Device has been unregistered */
223 retcode = -EINTR; 223 retcode = -EINTR;
224 break; 224 break;
225 } 225 }
226 if ( drm_lock_take( &dev->lock.hw_lock->lock, 226 if (drm_lock_take(&dev->lock.hw_lock->lock,
227 DRM_KERNEL_CONTEXT ) ) { 227 DRM_KERNEL_CONTEXT)) {
228 dev->lock.filp = filp; 228 dev->lock.filp = filp;
229 dev->lock.lock_time = jiffies; 229 dev->lock.lock_time = jiffies;
230 atomic_inc( &dev->counts[_DRM_STAT_LOCKS] ); 230 atomic_inc(&dev->counts[_DRM_STAT_LOCKS]);
231 break; /* Got lock */ 231 break; /* Got lock */
232 } 232 }
233 /* Contention */ 233 /* Contention */
234 schedule(); 234 schedule();
235 if ( signal_pending( current ) ) { 235 if (signal_pending(current)) {
236 retcode = -ERESTARTSYS; 236 retcode = -ERESTARTSYS;
237 break; 237 break;
238 } 238 }
239 } 239 }
240 __set_current_state(TASK_RUNNING); 240 __set_current_state(TASK_RUNNING);
241 remove_wait_queue( &dev->lock.lock_queue, &entry ); 241 remove_wait_queue(&dev->lock.lock_queue, &entry);
242 if( !retcode ) { 242 if (!retcode) {
243 if (dev->driver->release) 243 if (dev->driver->release)
244 dev->driver->release(dev, filp); 244 dev->driver->release(dev, filp);
245 drm_lock_free( dev, &dev->lock.hw_lock->lock, 245 drm_lock_free(dev, &dev->lock.hw_lock->lock,
246 DRM_KERNEL_CONTEXT ); 246 DRM_KERNEL_CONTEXT);
247 } 247 }
248 } 248 }
249 249
250 if (drm_core_check_feature(dev, DRIVER_HAVE_DMA) && !dev->driver->release) 250 if (drm_core_check_feature(dev, DRIVER_HAVE_DMA)
251 { 251 && !dev->driver->release) {
252 dev->driver->reclaim_buffers(dev, filp); 252 dev->driver->reclaim_buffers(dev, filp);
253 } 253 }
254 254
255 drm_fasync( -1, filp, 0 ); 255 drm_fasync(-1, filp, 0);
256 256
257 down( &dev->ctxlist_sem ); 257 down(&dev->ctxlist_sem);
258 if ( dev->ctxlist && (!list_empty(&dev->ctxlist->head))) { 258 if (dev->ctxlist && (!list_empty(&dev->ctxlist->head))) {
259 drm_ctx_list_t *pos, *n; 259 drm_ctx_list_t *pos, *n;
260 260
261 list_for_each_entry_safe( pos, n, &dev->ctxlist->head, head ) { 261 list_for_each_entry_safe(pos, n, &dev->ctxlist->head, head) {
262 if ( pos->tag == priv && 262 if (pos->tag == priv &&
263 pos->handle != DRM_KERNEL_CONTEXT ) { 263 pos->handle != DRM_KERNEL_CONTEXT) {
264 if (dev->driver->context_dtor) 264 if (dev->driver->context_dtor)
265 dev->driver->context_dtor(dev, pos->handle); 265 dev->driver->context_dtor(dev,
266 pos->handle);
266 267
267 drm_ctxbitmap_free( dev, pos->handle ); 268 drm_ctxbitmap_free(dev, pos->handle);
268 269
269 list_del( &pos->head ); 270 list_del(&pos->head);
270 drm_free( pos, sizeof(*pos), DRM_MEM_CTXLIST ); 271 drm_free(pos, sizeof(*pos), DRM_MEM_CTXLIST);
271 --dev->ctx_count; 272 --dev->ctx_count;
272 } 273 }
273 } 274 }
274 } 275 }
275 up( &dev->ctxlist_sem ); 276 up(&dev->ctxlist_sem);
276 277
277 down( &dev->struct_sem ); 278 down(&dev->struct_sem);
278 if ( priv->remove_auth_on_close == 1 ) { 279 if (priv->remove_auth_on_close == 1) {
279 drm_file_t *temp = dev->file_first; 280 drm_file_t *temp = dev->file_first;
280 while ( temp ) { 281 while (temp) {
281 temp->authenticated = 0; 282 temp->authenticated = 0;
282 temp = temp->next; 283 temp = temp->next;
283 } 284 }
284 } 285 }
285 if ( priv->prev ) { 286 if (priv->prev) {
286 priv->prev->next = priv->next; 287 priv->prev->next = priv->next;
287 } else { 288 } else {
288 dev->file_first = priv->next; 289 dev->file_first = priv->next;
289 } 290 }
290 if ( priv->next ) { 291 if (priv->next) {
291 priv->next->prev = priv->prev; 292 priv->next->prev = priv->prev;
292 } else { 293 } else {
293 dev->file_last = priv->prev; 294 dev->file_last = priv->prev;
294 } 295 }
295 up( &dev->struct_sem ); 296 up(&dev->struct_sem);
296 297
297 if (dev->driver->free_filp_priv) 298 if (dev->driver->free_filp_priv)
298 dev->driver->free_filp_priv(dev, priv); 299 dev->driver->free_filp_priv(dev, priv);
299 300
300 drm_free( priv, sizeof(*priv), DRM_MEM_FILES ); 301 drm_free(priv, sizeof(*priv), DRM_MEM_FILES);
301 302
302 /* ======================================================== 303 /* ========================================================
303 * End inline drm_release 304 * End inline drm_release
304 */ 305 */
305 306
306 atomic_inc( &dev->counts[_DRM_STAT_CLOSES] ); 307 atomic_inc(&dev->counts[_DRM_STAT_CLOSES]);
307 spin_lock( &dev->count_lock ); 308 spin_lock(&dev->count_lock);
308 if ( !--dev->open_count ) { 309 if (!--dev->open_count) {
309 if ( atomic_read( &dev->ioctl_count ) || dev->blocked ) { 310 if (atomic_read(&dev->ioctl_count) || dev->blocked) {
310 DRM_ERROR( "Device busy: %d %d\n", 311 DRM_ERROR("Device busy: %d %d\n",
311 atomic_read( &dev->ioctl_count ), 312 atomic_read(&dev->ioctl_count), dev->blocked);
312 dev->blocked ); 313 spin_unlock(&dev->count_lock);
313 spin_unlock( &dev->count_lock );
314 unlock_kernel(); 314 unlock_kernel();
315 return -EBUSY; 315 return -EBUSY;
316 } 316 }
317 spin_unlock( &dev->count_lock ); 317 spin_unlock(&dev->count_lock);
318 unlock_kernel(); 318 unlock_kernel();
319 return drm_takedown( dev ); 319 return drm_takedown(dev);
320 } 320 }
321 spin_unlock( &dev->count_lock ); 321 spin_unlock(&dev->count_lock);
322 322
323 unlock_kernel(); 323 unlock_kernel();
324 324
325 return retcode; 325 return retcode;
326} 326}
327
327EXPORT_SYMBOL(drm_release); 328EXPORT_SYMBOL(drm_release);
328 329
329/** 330/**
330 * Called whenever a process opens /dev/drm. 331 * Called whenever a process opens /dev/drm.
331 * 332 *
332 * \param inode device inode. 333 * \param inode device inode.
333 * \param filp file pointer. 334 * \param filp file pointer.
334 * \param dev device. 335 * \param dev device.
335 * \return zero on success or a negative number on failure. 336 * \return zero on success or a negative number on failure.
336 * 337 *
337 * Creates and initializes a drm_file structure for the file private data in \p 338 * Creates and initializes a drm_file structure for the file private data in \p
338 * filp and add it into the double linked list in \p dev. 339 * filp and add it into the double linked list in \p dev.
339 */ 340 */
340static int drm_open_helper(struct inode *inode, struct file *filp, drm_device_t *dev) 341static int drm_open_helper(struct inode *inode, struct file *filp,
342 drm_device_t * dev)
341{ 343{
342 int minor = iminor(inode); 344 int minor = iminor(inode);
343 drm_file_t *priv; 345 drm_file_t *priv;
344 int ret; 346 int ret;
345 347
346 if (filp->f_flags & O_EXCL) return -EBUSY; /* No exclusive opens */ 348 if (filp->f_flags & O_EXCL)
347 if (!drm_cpu_valid()) return -EINVAL; 349 return -EBUSY; /* No exclusive opens */
350 if (!drm_cpu_valid())
351 return -EINVAL;
348 352
349 DRM_DEBUG("pid = %d, minor = %d\n", current->pid, minor); 353 DRM_DEBUG("pid = %d, minor = %d\n", current->pid, minor);
350 354
351 priv = drm_alloc(sizeof(*priv), DRM_MEM_FILES); 355 priv = drm_alloc(sizeof(*priv), DRM_MEM_FILES);
352 if(!priv) return -ENOMEM; 356 if (!priv)
357 return -ENOMEM;
353 358
354 memset(priv, 0, sizeof(*priv)); 359 memset(priv, 0, sizeof(*priv));
355 filp->private_data = priv; 360 filp->private_data = priv;
356 priv->uid = current->euid; 361 priv->uid = current->euid;
357 priv->pid = current->pid; 362 priv->pid = current->pid;
358 priv->minor = minor; 363 priv->minor = minor;
359 priv->head = drm_heads[minor]; 364 priv->head = drm_heads[minor];
360 priv->ioctl_count = 0; 365 priv->ioctl_count = 0;
361 priv->authenticated = capable(CAP_SYS_ADMIN); 366 priv->authenticated = capable(CAP_SYS_ADMIN);
362 priv->lock_count = 0; 367 priv->lock_count = 0;
363 368
364 if (dev->driver->open_helper) { 369 if (dev->driver->open_helper) {
365 ret=dev->driver->open_helper(dev, priv); 370 ret = dev->driver->open_helper(dev, priv);
366 if (ret < 0) 371 if (ret < 0)
367 goto out_free; 372 goto out_free;
368 } 373 }
369 374
370 down(&dev->struct_sem); 375 down(&dev->struct_sem);
371 if (!dev->file_last) { 376 if (!dev->file_last) {
372 priv->next = NULL; 377 priv->next = NULL;
373 priv->prev = NULL; 378 priv->prev = NULL;
374 dev->file_first = priv; 379 dev->file_first = priv;
375 dev->file_last = priv; 380 dev->file_last = priv;
376 } else { 381 } else {
377 priv->next = NULL; 382 priv->next = NULL;
378 priv->prev = dev->file_last; 383 priv->prev = dev->file_last;
379 dev->file_last->next = priv; 384 dev->file_last->next = priv;
380 dev->file_last = priv; 385 dev->file_last = priv;
381 } 386 }
382 up(&dev->struct_sem); 387 up(&dev->struct_sem);
383 388
@@ -394,42 +399,48 @@ static int drm_open_helper(struct inode *inode, struct file *filp, drm_device_t
394 } 399 }
395 if (!dev->hose) { 400 if (!dev->hose) {
396 struct pci_bus *b = pci_bus_b(pci_root_buses.next); 401 struct pci_bus *b = pci_bus_b(pci_root_buses.next);
397 if (b) dev->hose = b->sysdata; 402 if (b)
403 dev->hose = b->sysdata;
398 } 404 }
399 } 405 }
400#endif 406#endif
401 407
402 return 0; 408 return 0;
403out_free: 409 out_free:
404 drm_free(priv, sizeof(*priv), DRM_MEM_FILES); 410 drm_free(priv, sizeof(*priv), DRM_MEM_FILES);
405 filp->private_data=NULL; 411 filp->private_data = NULL;
406 return ret; 412 return ret;
407} 413}
408 414
409/** No-op. */ 415/** No-op. */
410int drm_flush(struct file *filp) 416int drm_flush(struct file *filp)
411{ 417{
412 drm_file_t *priv = filp->private_data; 418 drm_file_t *priv = filp->private_data;
413 drm_device_t *dev = priv->head->dev; 419 drm_device_t *dev = priv->head->dev;
414 420
415 DRM_DEBUG("pid = %d, device = 0x%lx, open_count = %d\n", 421 DRM_DEBUG("pid = %d, device = 0x%lx, open_count = %d\n",
416 current->pid, (long)old_encode_dev(priv->head->device), dev->open_count); 422 current->pid, (long)old_encode_dev(priv->head->device),
423 dev->open_count);
417 return 0; 424 return 0;
418} 425}
426
419EXPORT_SYMBOL(drm_flush); 427EXPORT_SYMBOL(drm_flush);
420 428
421/** No-op. */ 429/** No-op. */
422int drm_fasync(int fd, struct file *filp, int on) 430int drm_fasync(int fd, struct file *filp, int on)
423{ 431{
424 drm_file_t *priv = filp->private_data; 432 drm_file_t *priv = filp->private_data;
425 drm_device_t *dev = priv->head->dev; 433 drm_device_t *dev = priv->head->dev;
426 int retcode; 434 int retcode;
427 435
428 DRM_DEBUG("fd = %d, device = 0x%lx\n", fd, (long)old_encode_dev(priv->head->device)); 436 DRM_DEBUG("fd = %d, device = 0x%lx\n", fd,
437 (long)old_encode_dev(priv->head->device));
429 retcode = fasync_helper(fd, filp, on, &dev->buf_async); 438 retcode = fasync_helper(fd, filp, on, &dev->buf_async);
430 if (retcode < 0) return retcode; 439 if (retcode < 0)
440 return retcode;
431 return 0; 441 return 0;
432} 442}
443
433EXPORT_SYMBOL(drm_fasync); 444EXPORT_SYMBOL(drm_fasync);
434 445
435/** No-op. */ 446/** No-op. */
@@ -437,5 +448,5 @@ unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait)
437{ 448{
438 return 0; 449 return 0;
439} 450}
440EXPORT_SYMBOL(drm_poll);
441 451
452EXPORT_SYMBOL(drm_poll);
diff --git a/drivers/char/drm/drm_init.c b/drivers/char/drm/drm_init.c
index 62883b749e97..754b934715c4 100644
--- a/drivers/char/drm/drm_init.c
+++ b/drivers/char/drm/drm_init.c
@@ -1,5 +1,5 @@
1/** 1/**
2 * \file drm_init.h 2 * \file drm_init.c
3 * Setup/Cleanup for DRM 3 * Setup/Cleanup for DRM
4 * 4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
@@ -43,10 +43,11 @@
43int drm_cpu_valid(void) 43int drm_cpu_valid(void)
44{ 44{
45#if defined(__i386__) 45#if defined(__i386__)
46 if (boot_cpu_data.x86 == 3) return 0; /* No cmpxchg on a 386 */ 46 if (boot_cpu_data.x86 == 3)
47 return 0; /* No cmpxchg on a 386 */
47#endif 48#endif
48#if defined(__sparc__) && !defined(__sparc_v9__) 49#if defined(__sparc__) && !defined(__sparc_v9__)
49 return 0; /* No cmpxchg before v9 sparc. */ 50 return 0; /* No cmpxchg before v9 sparc. */
50#endif 51#endif
51 return 1; 52 return 1;
52} 53}
diff --git a/drivers/char/drm/drm_ioc32.c b/drivers/char/drm/drm_ioc32.c
index 8087a9636399..dd91ff6b474c 100644
--- a/drivers/char/drm/drm_ioc32.c
+++ b/drivers/char/drm/drm_ioc32.c
@@ -68,15 +68,15 @@
68#define DRM_IOCTL_WAIT_VBLANK32 DRM_IOWR(0x3a, drm_wait_vblank32_t) 68#define DRM_IOCTL_WAIT_VBLANK32 DRM_IOWR(0x3a, drm_wait_vblank32_t)
69 69
70typedef struct drm_version_32 { 70typedef struct drm_version_32 {
71 int version_major; /**< Major version */ 71 int version_major; /**< Major version */
72 int version_minor; /**< Minor version */ 72 int version_minor; /**< Minor version */
73 int version_patchlevel;/**< Patch level */ 73 int version_patchlevel; /**< Patch level */
74 u32 name_len; /**< Length of name buffer */ 74 u32 name_len; /**< Length of name buffer */
75 u32 name; /**< Name of driver */ 75 u32 name; /**< Name of driver */
76 u32 date_len; /**< Length of date buffer */ 76 u32 date_len; /**< Length of date buffer */
77 u32 date; /**< User-space buffer to hold date */ 77 u32 date; /**< User-space buffer to hold date */
78 u32 desc_len; /**< Length of desc buffer */ 78 u32 desc_len; /**< Length of desc buffer */
79 u32 desc; /**< User-space buffer to hold desc */ 79 u32 desc; /**< User-space buffer to hold desc */
80} drm_version32_t; 80} drm_version32_t;
81 81
82static int compat_drm_version(struct file *file, unsigned int cmd, 82static int compat_drm_version(struct file *file, unsigned int cmd,
@@ -86,7 +86,7 @@ static int compat_drm_version(struct file *file, unsigned int cmd,
86 drm_version_t __user *version; 86 drm_version_t __user *version;
87 int err; 87 int err;
88 88
89 if (copy_from_user(&v32, (void __user *) arg, sizeof(v32))) 89 if (copy_from_user(&v32, (void __user *)arg, sizeof(v32)))
90 return -EFAULT; 90 return -EFAULT;
91 91
92 version = compat_alloc_user_space(sizeof(*version)); 92 version = compat_alloc_user_space(sizeof(*version));
@@ -104,7 +104,7 @@ static int compat_drm_version(struct file *file, unsigned int cmd,
104 return -EFAULT; 104 return -EFAULT;
105 105
106 err = drm_ioctl(file->f_dentry->d_inode, file, 106 err = drm_ioctl(file->f_dentry->d_inode, file,
107 DRM_IOCTL_VERSION, (unsigned long) version); 107 DRM_IOCTL_VERSION, (unsigned long)version);
108 if (err) 108 if (err)
109 return err; 109 return err;
110 110
@@ -116,7 +116,7 @@ static int compat_drm_version(struct file *file, unsigned int cmd,
116 || __get_user(v32.desc_len, &version->desc_len)) 116 || __get_user(v32.desc_len, &version->desc_len))
117 return -EFAULT; 117 return -EFAULT;
118 118
119 if (copy_to_user((void __user *) arg, &v32, sizeof(v32))) 119 if (copy_to_user((void __user *)arg, &v32, sizeof(v32)))
120 return -EFAULT; 120 return -EFAULT;
121 return 0; 121 return 0;
122} 122}
@@ -133,25 +133,25 @@ static int compat_drm_getunique(struct file *file, unsigned int cmd,
133 drm_unique_t __user *u; 133 drm_unique_t __user *u;
134 int err; 134 int err;
135 135
136 if (copy_from_user(&uq32, (void __user *) arg, sizeof(uq32))) 136 if (copy_from_user(&uq32, (void __user *)arg, sizeof(uq32)))
137 return -EFAULT; 137 return -EFAULT;
138 138
139 u = compat_alloc_user_space(sizeof(*u)); 139 u = compat_alloc_user_space(sizeof(*u));
140 if (!access_ok(VERIFY_WRITE, u, sizeof(*u))) 140 if (!access_ok(VERIFY_WRITE, u, sizeof(*u)))
141 return -EFAULT; 141 return -EFAULT;
142 if (__put_user(uq32.unique_len, &u->unique_len) 142 if (__put_user(uq32.unique_len, &u->unique_len)
143 || __put_user((void __user *)(unsigned long) uq32.unique, 143 || __put_user((void __user *)(unsigned long)uq32.unique,
144 &u->unique)) 144 &u->unique))
145 return -EFAULT; 145 return -EFAULT;
146 146
147 err = drm_ioctl(file->f_dentry->d_inode, file, 147 err = drm_ioctl(file->f_dentry->d_inode, file,
148 DRM_IOCTL_GET_UNIQUE, (unsigned long) u); 148 DRM_IOCTL_GET_UNIQUE, (unsigned long)u);
149 if (err) 149 if (err)
150 return err; 150 return err;
151 151
152 if (__get_user(uq32.unique_len, &u->unique_len)) 152 if (__get_user(uq32.unique_len, &u->unique_len))
153 return -EFAULT; 153 return -EFAULT;
154 if (copy_to_user((void __user *) arg, &uq32, sizeof(uq32))) 154 if (copy_to_user((void __user *)arg, &uq32, sizeof(uq32)))
155 return -EFAULT; 155 return -EFAULT;
156 return 0; 156 return 0;
157} 157}
@@ -162,28 +162,28 @@ static int compat_drm_setunique(struct file *file, unsigned int cmd,
162 drm_unique32_t uq32; 162 drm_unique32_t uq32;
163 drm_unique_t __user *u; 163 drm_unique_t __user *u;
164 164
165 if (copy_from_user(&uq32, (void __user *) arg, sizeof(uq32))) 165 if (copy_from_user(&uq32, (void __user *)arg, sizeof(uq32)))
166 return -EFAULT; 166 return -EFAULT;
167 167
168 u = compat_alloc_user_space(sizeof(*u)); 168 u = compat_alloc_user_space(sizeof(*u));
169 if (!access_ok(VERIFY_WRITE, u, sizeof(*u))) 169 if (!access_ok(VERIFY_WRITE, u, sizeof(*u)))
170 return -EFAULT; 170 return -EFAULT;
171 if (__put_user(uq32.unique_len, &u->unique_len) 171 if (__put_user(uq32.unique_len, &u->unique_len)
172 || __put_user((void __user *)(unsigned long) uq32.unique, 172 || __put_user((void __user *)(unsigned long)uq32.unique,
173 &u->unique)) 173 &u->unique))
174 return -EFAULT; 174 return -EFAULT;
175 175
176 return drm_ioctl(file->f_dentry->d_inode, file, 176 return drm_ioctl(file->f_dentry->d_inode, file,
177 DRM_IOCTL_SET_UNIQUE, (unsigned long) u); 177 DRM_IOCTL_SET_UNIQUE, (unsigned long)u);
178} 178}
179 179
180typedef struct drm_map32 { 180typedef struct drm_map32 {
181 u32 offset; /**< Requested physical address (0 for SAREA)*/ 181 u32 offset; /**< Requested physical address (0 for SAREA)*/
182 u32 size; /**< Requested physical size (bytes) */ 182 u32 size; /**< Requested physical size (bytes) */
183 drm_map_type_t type; /**< Type of memory to map */ 183 drm_map_type_t type; /**< Type of memory to map */
184 drm_map_flags_t flags; /**< Flags */ 184 drm_map_flags_t flags; /**< Flags */
185 u32 handle; /**< User-space: "Handle" to pass to mmap() */ 185 u32 handle; /**< User-space: "Handle" to pass to mmap() */
186 int mtrr; /**< MTRR slot used */ 186 int mtrr; /**< MTRR slot used */
187} drm_map32_t; 187} drm_map32_t;
188 188
189static int compat_drm_getmap(struct file *file, unsigned int cmd, 189static int compat_drm_getmap(struct file *file, unsigned int cmd,
@@ -205,7 +205,7 @@ static int compat_drm_getmap(struct file *file, unsigned int cmd,
205 return -EFAULT; 205 return -EFAULT;
206 206
207 err = drm_ioctl(file->f_dentry->d_inode, file, 207 err = drm_ioctl(file->f_dentry->d_inode, file,
208 DRM_IOCTL_GET_MAP, (unsigned long) map); 208 DRM_IOCTL_GET_MAP, (unsigned long)map);
209 if (err) 209 if (err)
210 return err; 210 return err;
211 211
@@ -217,7 +217,7 @@ static int compat_drm_getmap(struct file *file, unsigned int cmd,
217 || __get_user(m32.mtrr, &map->mtrr)) 217 || __get_user(m32.mtrr, &map->mtrr))
218 return -EFAULT; 218 return -EFAULT;
219 219
220 m32.handle = (unsigned long) handle; 220 m32.handle = (unsigned long)handle;
221 if (copy_to_user(argp, &m32, sizeof(m32))) 221 if (copy_to_user(argp, &m32, sizeof(m32)))
222 return -EFAULT; 222 return -EFAULT;
223 return 0; 223 return 0;
@@ -246,7 +246,7 @@ static int compat_drm_addmap(struct file *file, unsigned int cmd,
246 return -EFAULT; 246 return -EFAULT;
247 247
248 err = drm_ioctl(file->f_dentry->d_inode, file, 248 err = drm_ioctl(file->f_dentry->d_inode, file,
249 DRM_IOCTL_ADD_MAP, (unsigned long) map); 249 DRM_IOCTL_ADD_MAP, (unsigned long)map);
250 if (err) 250 if (err)
251 return err; 251 return err;
252 252
@@ -255,8 +255,8 @@ static int compat_drm_addmap(struct file *file, unsigned int cmd,
255 || __get_user(handle, &map->handle)) 255 || __get_user(handle, &map->handle))
256 return -EFAULT; 256 return -EFAULT;
257 257
258 m32.handle = (unsigned long) handle; 258 m32.handle = (unsigned long)handle;
259 if (m32.handle != (unsigned long) handle && printk_ratelimit()) 259 if (m32.handle != (unsigned long)handle && printk_ratelimit())
260 printk(KERN_ERR "compat_drm_addmap truncated handle" 260 printk(KERN_ERR "compat_drm_addmap truncated handle"
261 " %p for type %d offset %x\n", 261 " %p for type %d offset %x\n",
262 handle, m32.type, m32.offset); 262 handle, m32.type, m32.offset);
@@ -280,20 +280,20 @@ static int compat_drm_rmmap(struct file *file, unsigned int cmd,
280 map = compat_alloc_user_space(sizeof(*map)); 280 map = compat_alloc_user_space(sizeof(*map));
281 if (!access_ok(VERIFY_WRITE, map, sizeof(*map))) 281 if (!access_ok(VERIFY_WRITE, map, sizeof(*map)))
282 return -EFAULT; 282 return -EFAULT;
283 if (__put_user((void *)(unsigned long) handle, &map->handle)) 283 if (__put_user((void *)(unsigned long)handle, &map->handle))
284 return -EFAULT; 284 return -EFAULT;
285 285
286 return drm_ioctl(file->f_dentry->d_inode, file, 286 return drm_ioctl(file->f_dentry->d_inode, file,
287 DRM_IOCTL_RM_MAP, (unsigned long) map); 287 DRM_IOCTL_RM_MAP, (unsigned long)map);
288} 288}
289 289
290typedef struct drm_client32 { 290typedef struct drm_client32 {
291 int idx; /**< Which client desired? */ 291 int idx; /**< Which client desired? */
292 int auth; /**< Is client authenticated? */ 292 int auth; /**< Is client authenticated? */
293 u32 pid; /**< Process ID */ 293 u32 pid; /**< Process ID */
294 u32 uid; /**< User ID */ 294 u32 uid; /**< User ID */
295 u32 magic; /**< Magic */ 295 u32 magic; /**< Magic */
296 u32 iocs; /**< Ioctl count */ 296 u32 iocs; /**< Ioctl count */
297} drm_client32_t; 297} drm_client32_t;
298 298
299static int compat_drm_getclient(struct file *file, unsigned int cmd, 299static int compat_drm_getclient(struct file *file, unsigned int cmd,
@@ -314,7 +314,7 @@ static int compat_drm_getclient(struct file *file, unsigned int cmd,
314 return -EFAULT; 314 return -EFAULT;
315 315
316 err = drm_ioctl(file->f_dentry->d_inode, file, 316 err = drm_ioctl(file->f_dentry->d_inode, file,
317 DRM_IOCTL_GET_CLIENT, (unsigned long) client); 317 DRM_IOCTL_GET_CLIENT, (unsigned long)client);
318 if (err) 318 if (err)
319 return err; 319 return err;
320 320
@@ -351,7 +351,7 @@ static int compat_drm_getstats(struct file *file, unsigned int cmd,
351 return -EFAULT; 351 return -EFAULT;
352 352
353 err = drm_ioctl(file->f_dentry->d_inode, file, 353 err = drm_ioctl(file->f_dentry->d_inode, file,
354 DRM_IOCTL_GET_STATS, (unsigned long) stats); 354 DRM_IOCTL_GET_STATS, (unsigned long)stats);
355 if (err) 355 if (err)
356 return err; 356 return err;
357 357
@@ -368,12 +368,12 @@ static int compat_drm_getstats(struct file *file, unsigned int cmd,
368} 368}
369 369
370typedef struct drm_buf_desc32 { 370typedef struct drm_buf_desc32 {
371 int count; /**< Number of buffers of this size */ 371 int count; /**< Number of buffers of this size */
372 int size; /**< Size in bytes */ 372 int size; /**< Size in bytes */
373 int low_mark; /**< Low water mark */ 373 int low_mark; /**< Low water mark */
374 int high_mark; /**< High water mark */ 374 int high_mark; /**< High water mark */
375 int flags; 375 int flags;
376 u32 agp_start; /**< Start address in the AGP aperture */ 376 u32 agp_start; /**< Start address in the AGP aperture */
377} drm_buf_desc32_t; 377} drm_buf_desc32_t;
378 378
379static int compat_drm_addbufs(struct file *file, unsigned int cmd, 379static int compat_drm_addbufs(struct file *file, unsigned int cmd,
@@ -395,7 +395,7 @@ static int compat_drm_addbufs(struct file *file, unsigned int cmd,
395 return -EFAULT; 395 return -EFAULT;
396 396
397 err = drm_ioctl(file->f_dentry->d_inode, file, 397 err = drm_ioctl(file->f_dentry->d_inode, file,
398 DRM_IOCTL_ADD_BUFS, (unsigned long) buf); 398 DRM_IOCTL_ADD_BUFS, (unsigned long)buf);
399 if (err) 399 if (err)
400 return err; 400 return err;
401 401
@@ -427,12 +427,12 @@ static int compat_drm_markbufs(struct file *file, unsigned int cmd,
427 return -EFAULT; 427 return -EFAULT;
428 428
429 return drm_ioctl(file->f_dentry->d_inode, file, 429 return drm_ioctl(file->f_dentry->d_inode, file,
430 DRM_IOCTL_MARK_BUFS, (unsigned long) buf); 430 DRM_IOCTL_MARK_BUFS, (unsigned long)buf);
431} 431}
432 432
433typedef struct drm_buf_info32 { 433typedef struct drm_buf_info32 {
434 int count; /**< Entries in list */ 434 int count; /**< Entries in list */
435 u32 list; 435 u32 list;
436} drm_buf_info32_t; 436} drm_buf_info32_t;
437 437
438static int compat_drm_infobufs(struct file *file, unsigned int cmd, 438static int compat_drm_infobufs(struct file *file, unsigned int cmd,
@@ -451,7 +451,7 @@ static int compat_drm_infobufs(struct file *file, unsigned int cmd,
451 return -EFAULT; 451 return -EFAULT;
452 452
453 count = req32.count; 453 count = req32.count;
454 to = (drm_buf_desc32_t __user *)(unsigned long) req32.list; 454 to = (drm_buf_desc32_t __user *) (unsigned long)req32.list;
455 if (count < 0) 455 if (count < 0)
456 count = 0; 456 count = 0;
457 if (count > 0 457 if (count > 0
@@ -469,7 +469,7 @@ static int compat_drm_infobufs(struct file *file, unsigned int cmd,
469 return -EFAULT; 469 return -EFAULT;
470 470
471 err = drm_ioctl(file->f_dentry->d_inode, file, 471 err = drm_ioctl(file->f_dentry->d_inode, file,
472 DRM_IOCTL_INFO_BUFS, (unsigned long) request); 472 DRM_IOCTL_INFO_BUFS, (unsigned long)request);
473 if (err) 473 if (err)
474 return err; 474 return err;
475 475
@@ -488,16 +488,16 @@ static int compat_drm_infobufs(struct file *file, unsigned int cmd,
488} 488}
489 489
490typedef struct drm_buf_pub32 { 490typedef struct drm_buf_pub32 {
491 int idx; /**< Index into the master buffer list */ 491 int idx; /**< Index into the master buffer list */
492 int total; /**< Buffer size */ 492 int total; /**< Buffer size */
493 int used; /**< Amount of buffer in use (for DMA) */ 493 int used; /**< Amount of buffer in use (for DMA) */
494 u32 address; /**< Address of buffer */ 494 u32 address; /**< Address of buffer */
495} drm_buf_pub32_t; 495} drm_buf_pub32_t;
496 496
497typedef struct drm_buf_map32 { 497typedef struct drm_buf_map32 {
498 int count; /**< Length of the buffer list */ 498 int count; /**< Length of the buffer list */
499 u32 virtual; /**< Mmap'd area in user-virtual */ 499 u32 virtual; /**< Mmap'd area in user-virtual */
500 u32 list; /**< Buffer information */ 500 u32 list; /**< Buffer information */
501} drm_buf_map32_t; 501} drm_buf_map32_t;
502 502
503static int compat_drm_mapbufs(struct file *file, unsigned int cmd, 503static int compat_drm_mapbufs(struct file *file, unsigned int cmd,
@@ -531,7 +531,7 @@ static int compat_drm_mapbufs(struct file *file, unsigned int cmd,
531 return -EFAULT; 531 return -EFAULT;
532 532
533 err = drm_ioctl(file->f_dentry->d_inode, file, 533 err = drm_ioctl(file->f_dentry->d_inode, file,
534 DRM_IOCTL_MAP_BUFS, (unsigned long) request); 534 DRM_IOCTL_MAP_BUFS, (unsigned long)request);
535 if (err) 535 if (err)
536 return err; 536 return err;
537 537
@@ -542,21 +542,21 @@ static int compat_drm_mapbufs(struct file *file, unsigned int cmd,
542 if (__copy_in_user(&list32[i], &list[i], 542 if (__copy_in_user(&list32[i], &list[i],
543 offsetof(drm_buf_pub_t, address)) 543 offsetof(drm_buf_pub_t, address))
544 || __get_user(addr, &list[i].address) 544 || __get_user(addr, &list[i].address)
545 || __put_user((unsigned long) addr, 545 || __put_user((unsigned long)addr,
546 &list32[i].address)) 546 &list32[i].address))
547 return -EFAULT; 547 return -EFAULT;
548 548
549 if (__put_user(actual, &argp->count) 549 if (__put_user(actual, &argp->count)
550 || __get_user(addr, &request->virtual) 550 || __get_user(addr, &request->virtual)
551 || __put_user((unsigned long) addr, &argp->virtual)) 551 || __put_user((unsigned long)addr, &argp->virtual))
552 return -EFAULT; 552 return -EFAULT;
553 553
554 return 0; 554 return 0;
555} 555}
556 556
557typedef struct drm_buf_free32 { 557typedef struct drm_buf_free32 {
558 int count; 558 int count;
559 u32 list; 559 u32 list;
560} drm_buf_free32_t; 560} drm_buf_free32_t;
561 561
562static int compat_drm_freebufs(struct file *file, unsigned int cmd, 562static int compat_drm_freebufs(struct file *file, unsigned int cmd,
@@ -573,17 +573,17 @@ static int compat_drm_freebufs(struct file *file, unsigned int cmd,
573 if (!access_ok(VERIFY_WRITE, request, sizeof(*request))) 573 if (!access_ok(VERIFY_WRITE, request, sizeof(*request)))
574 return -EFAULT; 574 return -EFAULT;
575 if (__put_user(req32.count, &request->count) 575 if (__put_user(req32.count, &request->count)
576 || __put_user((int __user *)(unsigned long) req32.list, 576 || __put_user((int __user *)(unsigned long)req32.list,
577 &request->list)) 577 &request->list))
578 return -EFAULT; 578 return -EFAULT;
579 579
580 return drm_ioctl(file->f_dentry->d_inode, file, 580 return drm_ioctl(file->f_dentry->d_inode, file,
581 DRM_IOCTL_FREE_BUFS, (unsigned long) request); 581 DRM_IOCTL_FREE_BUFS, (unsigned long)request);
582} 582}
583 583
584typedef struct drm_ctx_priv_map32 { 584typedef struct drm_ctx_priv_map32 {
585 unsigned int ctx_id; /**< Context requesting private mapping */ 585 unsigned int ctx_id; /**< Context requesting private mapping */
586 u32 handle; /**< Handle of map */ 586 u32 handle; /**< Handle of map */
587} drm_ctx_priv_map32_t; 587} drm_ctx_priv_map32_t;
588 588
589static int compat_drm_setsareactx(struct file *file, unsigned int cmd, 589static int compat_drm_setsareactx(struct file *file, unsigned int cmd,
@@ -600,12 +600,12 @@ static int compat_drm_setsareactx(struct file *file, unsigned int cmd,
600 if (!access_ok(VERIFY_WRITE, request, sizeof(*request))) 600 if (!access_ok(VERIFY_WRITE, request, sizeof(*request)))
601 return -EFAULT; 601 return -EFAULT;
602 if (__put_user(req32.ctx_id, &request->ctx_id) 602 if (__put_user(req32.ctx_id, &request->ctx_id)
603 || __put_user((void *)(unsigned long) req32.handle, 603 || __put_user((void *)(unsigned long)req32.handle,
604 &request->handle)) 604 &request->handle))
605 return -EFAULT; 605 return -EFAULT;
606 606
607 return drm_ioctl(file->f_dentry->d_inode, file, 607 return drm_ioctl(file->f_dentry->d_inode, file,
608 DRM_IOCTL_SET_SAREA_CTX, (unsigned long) request); 608 DRM_IOCTL_SET_SAREA_CTX, (unsigned long)request);
609} 609}
610 610
611static int compat_drm_getsareactx(struct file *file, unsigned int cmd, 611static int compat_drm_getsareactx(struct file *file, unsigned int cmd,
@@ -628,20 +628,20 @@ static int compat_drm_getsareactx(struct file *file, unsigned int cmd,
628 return -EFAULT; 628 return -EFAULT;
629 629
630 err = drm_ioctl(file->f_dentry->d_inode, file, 630 err = drm_ioctl(file->f_dentry->d_inode, file,
631 DRM_IOCTL_GET_SAREA_CTX, (unsigned long) request); 631 DRM_IOCTL_GET_SAREA_CTX, (unsigned long)request);
632 if (err) 632 if (err)
633 return err; 633 return err;
634 634
635 if (__get_user(handle, &request->handle) 635 if (__get_user(handle, &request->handle)
636 || __put_user((unsigned long) handle, &argp->handle)) 636 || __put_user((unsigned long)handle, &argp->handle))
637 return -EFAULT; 637 return -EFAULT;
638 638
639 return 0; 639 return 0;
640} 640}
641 641
642typedef struct drm_ctx_res32 { 642typedef struct drm_ctx_res32 {
643 int count; 643 int count;
644 u32 contexts; 644 u32 contexts;
645} drm_ctx_res32_t; 645} drm_ctx_res32_t;
646 646
647static int compat_drm_resctx(struct file *file, unsigned int cmd, 647static int compat_drm_resctx(struct file *file, unsigned int cmd,
@@ -659,12 +659,12 @@ static int compat_drm_resctx(struct file *file, unsigned int cmd,
659 if (!access_ok(VERIFY_WRITE, res, sizeof(*res))) 659 if (!access_ok(VERIFY_WRITE, res, sizeof(*res)))
660 return -EFAULT; 660 return -EFAULT;
661 if (__put_user(res32.count, &res->count) 661 if (__put_user(res32.count, &res->count)
662 || __put_user((drm_ctx_t __user *)(unsigned long) res32.contexts, 662 || __put_user((drm_ctx_t __user *) (unsigned long)res32.contexts,
663 &res->contexts)) 663 &res->contexts))
664 return -EFAULT; 664 return -EFAULT;
665 665
666 err = drm_ioctl(file->f_dentry->d_inode, file, 666 err = drm_ioctl(file->f_dentry->d_inode, file,
667 DRM_IOCTL_RES_CTX, (unsigned long) res); 667 DRM_IOCTL_RES_CTX, (unsigned long)res);
668 if (err) 668 if (err)
669 return err; 669 return err;
670 670
@@ -676,23 +676,23 @@ static int compat_drm_resctx(struct file *file, unsigned int cmd,
676} 676}
677 677
678typedef struct drm_dma32 { 678typedef struct drm_dma32 {
679 int context; /**< Context handle */ 679 int context; /**< Context handle */
680 int send_count; /**< Number of buffers to send */ 680 int send_count; /**< Number of buffers to send */
681 u32 send_indices; /**< List of handles to buffers */ 681 u32 send_indices; /**< List of handles to buffers */
682 u32 send_sizes; /**< Lengths of data to send */ 682 u32 send_sizes; /**< Lengths of data to send */
683 drm_dma_flags_t flags; /**< Flags */ 683 drm_dma_flags_t flags; /**< Flags */
684 int request_count; /**< Number of buffers requested */ 684 int request_count; /**< Number of buffers requested */
685 int request_size; /**< Desired size for buffers */ 685 int request_size; /**< Desired size for buffers */
686 u32 request_indices; /**< Buffer information */ 686 u32 request_indices; /**< Buffer information */
687 u32 request_sizes; 687 u32 request_sizes;
688 int granted_count; /**< Number of buffers granted */ 688 int granted_count; /**< Number of buffers granted */
689} drm_dma32_t; 689} drm_dma32_t;
690 690
691static int compat_drm_dma(struct file *file, unsigned int cmd, 691static int compat_drm_dma(struct file *file, unsigned int cmd,
692 unsigned long arg) 692 unsigned long arg)
693{ 693{
694 drm_dma32_t d32; 694 drm_dma32_t d32;
695 drm_dma32_t __user *argp = (void __user *) arg; 695 drm_dma32_t __user *argp = (void __user *)arg;
696 drm_dma_t __user *d; 696 drm_dma_t __user *d;
697 int err; 697 int err;
698 698
@@ -705,20 +705,20 @@ static int compat_drm_dma(struct file *file, unsigned int cmd,
705 705
706 if (__put_user(d32.context, &d->context) 706 if (__put_user(d32.context, &d->context)
707 || __put_user(d32.send_count, &d->send_count) 707 || __put_user(d32.send_count, &d->send_count)
708 || __put_user((int __user *)(unsigned long) d32.send_indices, 708 || __put_user((int __user *)(unsigned long)d32.send_indices,
709 &d->send_indices) 709 &d->send_indices)
710 || __put_user((int __user *)(unsigned long) d32.send_sizes, 710 || __put_user((int __user *)(unsigned long)d32.send_sizes,
711 &d->send_sizes) 711 &d->send_sizes)
712 || __put_user(d32.flags, &d->flags) 712 || __put_user(d32.flags, &d->flags)
713 || __put_user(d32.request_count, &d->request_count) 713 || __put_user(d32.request_count, &d->request_count)
714 || __put_user((int __user *)(unsigned long) d32.request_indices, 714 || __put_user((int __user *)(unsigned long)d32.request_indices,
715 &d->request_indices) 715 &d->request_indices)
716 || __put_user((int __user *)(unsigned long) d32.request_sizes, 716 || __put_user((int __user *)(unsigned long)d32.request_sizes,
717 &d->request_sizes)) 717 &d->request_sizes))
718 return -EFAULT; 718 return -EFAULT;
719 719
720 err = drm_ioctl(file->f_dentry->d_inode, file, 720 err = drm_ioctl(file->f_dentry->d_inode, file,
721 DRM_IOCTL_DMA, (unsigned long) d); 721 DRM_IOCTL_DMA, (unsigned long)d);
722 if (err) 722 if (err)
723 return err; 723 return err;
724 724
@@ -751,19 +751,19 @@ static int compat_drm_agp_enable(struct file *file, unsigned int cmd,
751 return -EFAULT; 751 return -EFAULT;
752 752
753 return drm_ioctl(file->f_dentry->d_inode, file, 753 return drm_ioctl(file->f_dentry->d_inode, file,
754 DRM_IOCTL_AGP_ENABLE, (unsigned long) mode); 754 DRM_IOCTL_AGP_ENABLE, (unsigned long)mode);
755} 755}
756 756
757typedef struct drm_agp_info32 { 757typedef struct drm_agp_info32 {
758 int agp_version_major; 758 int agp_version_major;
759 int agp_version_minor; 759 int agp_version_minor;
760 u32 mode; 760 u32 mode;
761 u32 aperture_base; /* physical address */ 761 u32 aperture_base; /* physical address */
762 u32 aperture_size; /* bytes */ 762 u32 aperture_size; /* bytes */
763 u32 memory_allowed; /* bytes */ 763 u32 memory_allowed; /* bytes */
764 u32 memory_used; 764 u32 memory_used;
765 765
766 /* PCI information */ 766 /* PCI information */
767 unsigned short id_vendor; 767 unsigned short id_vendor;
768 unsigned short id_device; 768 unsigned short id_device;
769} drm_agp_info32_t; 769} drm_agp_info32_t;
@@ -781,7 +781,7 @@ static int compat_drm_agp_info(struct file *file, unsigned int cmd,
781 return -EFAULT; 781 return -EFAULT;
782 782
783 err = drm_ioctl(file->f_dentry->d_inode, file, 783 err = drm_ioctl(file->f_dentry->d_inode, file,
784 DRM_IOCTL_AGP_INFO, (unsigned long) info); 784 DRM_IOCTL_AGP_INFO, (unsigned long)info);
785 if (err) 785 if (err)
786 return err; 786 return err;
787 787
@@ -806,7 +806,7 @@ typedef struct drm_agp_buffer32 {
806 u32 size; /**< In bytes -- will round to page boundary */ 806 u32 size; /**< In bytes -- will round to page boundary */
807 u32 handle; /**< Used for binding / unbinding */ 807 u32 handle; /**< Used for binding / unbinding */
808 u32 type; /**< Type of memory to allocate */ 808 u32 type; /**< Type of memory to allocate */
809 u32 physical; /**< Physical used by i810 */ 809 u32 physical; /**< Physical used by i810 */
810} drm_agp_buffer32_t; 810} drm_agp_buffer32_t;
811 811
812static int compat_drm_agp_alloc(struct file *file, unsigned int cmd, 812static int compat_drm_agp_alloc(struct file *file, unsigned int cmd,
@@ -827,7 +827,7 @@ static int compat_drm_agp_alloc(struct file *file, unsigned int cmd,
827 return -EFAULT; 827 return -EFAULT;
828 828
829 err = drm_ioctl(file->f_dentry->d_inode, file, 829 err = drm_ioctl(file->f_dentry->d_inode, file,
830 DRM_IOCTL_AGP_ALLOC, (unsigned long) request); 830 DRM_IOCTL_AGP_ALLOC, (unsigned long)request);
831 if (err) 831 if (err)
832 return err; 832 return err;
833 833
@@ -835,7 +835,7 @@ static int compat_drm_agp_alloc(struct file *file, unsigned int cmd,
835 || __get_user(req32.physical, &request->physical) 835 || __get_user(req32.physical, &request->physical)
836 || copy_to_user(argp, &req32, sizeof(req32))) { 836 || copy_to_user(argp, &req32, sizeof(req32))) {
837 drm_ioctl(file->f_dentry->d_inode, file, 837 drm_ioctl(file->f_dentry->d_inode, file,
838 DRM_IOCTL_AGP_FREE, (unsigned long) request); 838 DRM_IOCTL_AGP_FREE, (unsigned long)request);
839 return -EFAULT; 839 return -EFAULT;
840 } 840 }
841 841
@@ -856,7 +856,7 @@ static int compat_drm_agp_free(struct file *file, unsigned int cmd,
856 return -EFAULT; 856 return -EFAULT;
857 857
858 return drm_ioctl(file->f_dentry->d_inode, file, 858 return drm_ioctl(file->f_dentry->d_inode, file,
859 DRM_IOCTL_AGP_FREE, (unsigned long) request); 859 DRM_IOCTL_AGP_FREE, (unsigned long)request);
860} 860}
861 861
862typedef struct drm_agp_binding32 { 862typedef struct drm_agp_binding32 {
@@ -881,7 +881,7 @@ static int compat_drm_agp_bind(struct file *file, unsigned int cmd,
881 return -EFAULT; 881 return -EFAULT;
882 882
883 return drm_ioctl(file->f_dentry->d_inode, file, 883 return drm_ioctl(file->f_dentry->d_inode, file,
884 DRM_IOCTL_AGP_BIND, (unsigned long) request); 884 DRM_IOCTL_AGP_BIND, (unsigned long)request);
885} 885}
886 886
887static int compat_drm_agp_unbind(struct file *file, unsigned int cmd, 887static int compat_drm_agp_unbind(struct file *file, unsigned int cmd,
@@ -898,9 +898,9 @@ static int compat_drm_agp_unbind(struct file *file, unsigned int cmd,
898 return -EFAULT; 898 return -EFAULT;
899 899
900 return drm_ioctl(file->f_dentry->d_inode, file, 900 return drm_ioctl(file->f_dentry->d_inode, file,
901 DRM_IOCTL_AGP_UNBIND, (unsigned long) request); 901 DRM_IOCTL_AGP_UNBIND, (unsigned long)request);
902} 902}
903#endif /* __OS_HAS_AGP */ 903#endif /* __OS_HAS_AGP */
904 904
905typedef struct drm_scatter_gather32 { 905typedef struct drm_scatter_gather32 {
906 u32 size; /**< In bytes -- will round to page boundary */ 906 u32 size; /**< In bytes -- will round to page boundary */
@@ -923,7 +923,7 @@ static int compat_drm_sg_alloc(struct file *file, unsigned int cmd,
923 return -EFAULT; 923 return -EFAULT;
924 924
925 err = drm_ioctl(file->f_dentry->d_inode, file, 925 err = drm_ioctl(file->f_dentry->d_inode, file,
926 DRM_IOCTL_SG_ALLOC, (unsigned long) request); 926 DRM_IOCTL_SG_ALLOC, (unsigned long)request);
927 if (err) 927 if (err)
928 return err; 928 return err;
929 929
@@ -950,7 +950,7 @@ static int compat_drm_sg_free(struct file *file, unsigned int cmd,
950 return -EFAULT; 950 return -EFAULT;
951 951
952 return drm_ioctl(file->f_dentry->d_inode, file, 952 return drm_ioctl(file->f_dentry->d_inode, file,
953 DRM_IOCTL_SG_FREE, (unsigned long) request); 953 DRM_IOCTL_SG_FREE, (unsigned long)request);
954} 954}
955 955
956struct drm_wait_vblank_request32 { 956struct drm_wait_vblank_request32 {
@@ -990,7 +990,7 @@ static int compat_drm_wait_vblank(struct file *file, unsigned int cmd,
990 return -EFAULT; 990 return -EFAULT;
991 991
992 err = drm_ioctl(file->f_dentry->d_inode, file, 992 err = drm_ioctl(file->f_dentry->d_inode, file,
993 DRM_IOCTL_WAIT_VBLANK, (unsigned long) request); 993 DRM_IOCTL_WAIT_VBLANK, (unsigned long)request);
994 if (err) 994 if (err)
995 return err; 995 return err;
996 996
@@ -1059,11 +1059,12 @@ long drm_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
1059 1059
1060 lock_kernel(); /* XXX for now */ 1060 lock_kernel(); /* XXX for now */
1061 if (fn != NULL) 1061 if (fn != NULL)
1062 ret = (*fn)(filp, cmd, arg); 1062 ret = (*fn) (filp, cmd, arg);
1063 else 1063 else
1064 ret = drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg); 1064 ret = drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg);
1065 unlock_kernel(); 1065 unlock_kernel();
1066 1066
1067 return ret; 1067 return ret;
1068} 1068}
1069
1069EXPORT_SYMBOL(drm_compat_ioctl); 1070EXPORT_SYMBOL(drm_compat_ioctl);
diff --git a/drivers/char/drm/drm_ioctl.c b/drivers/char/drm/drm_ioctl.c
index d2ed3ba5aca9..9b0feba6b063 100644
--- a/drivers/char/drm/drm_ioctl.c
+++ b/drivers/char/drm/drm_ioctl.c
@@ -1,5 +1,5 @@
1/** 1/**
2 * \file drm_ioctl.h 2 * \file drm_ioctl.c
3 * IOCTL processing for DRM 3 * IOCTL processing for DRM
4 * 4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
@@ -40,7 +40,7 @@
40 40
41/** 41/**
42 * Get the bus id. 42 * Get the bus id.
43 * 43 *
44 * \param inode device inode. 44 * \param inode device inode.
45 * \param filp file pointer. 45 * \param filp file pointer.
46 * \param cmd command. 46 * \param cmd command.
@@ -50,12 +50,12 @@
50 * Copies the bus id from drm_device::unique into user space. 50 * Copies the bus id from drm_device::unique into user space.
51 */ 51 */
52int drm_getunique(struct inode *inode, struct file *filp, 52int drm_getunique(struct inode *inode, struct file *filp,
53 unsigned int cmd, unsigned long arg) 53 unsigned int cmd, unsigned long arg)
54{ 54{
55 drm_file_t *priv = filp->private_data; 55 drm_file_t *priv = filp->private_data;
56 drm_device_t *dev = priv->head->dev; 56 drm_device_t *dev = priv->head->dev;
57 drm_unique_t __user *argp = (void __user *)arg; 57 drm_unique_t __user *argp = (void __user *)arg;
58 drm_unique_t u; 58 drm_unique_t u;
59 59
60 if (copy_from_user(&u, argp, sizeof(u))) 60 if (copy_from_user(&u, argp, sizeof(u)))
61 return -EFAULT; 61 return -EFAULT;
@@ -71,7 +71,7 @@ int drm_getunique(struct inode *inode, struct file *filp,
71 71
72/** 72/**
73 * Set the bus id. 73 * Set the bus id.
74 * 74 *
75 * \param inode device inode. 75 * \param inode device inode.
76 * \param filp file pointer. 76 * \param filp file pointer.
77 * \param cmd command. 77 * \param cmd command.
@@ -84,34 +84,39 @@ int drm_getunique(struct inode *inode, struct file *filp,
84 * version 1.1 or greater. 84 * version 1.1 or greater.
85 */ 85 */
86int drm_setunique(struct inode *inode, struct file *filp, 86int drm_setunique(struct inode *inode, struct file *filp,
87 unsigned int cmd, unsigned long arg) 87 unsigned int cmd, unsigned long arg)
88{ 88{
89 drm_file_t *priv = filp->private_data; 89 drm_file_t *priv = filp->private_data;
90 drm_device_t *dev = priv->head->dev; 90 drm_device_t *dev = priv->head->dev;
91 drm_unique_t u; 91 drm_unique_t u;
92 int domain, bus, slot, func, ret; 92 int domain, bus, slot, func, ret;
93 93
94 if (dev->unique_len || dev->unique) return -EBUSY; 94 if (dev->unique_len || dev->unique)
95 return -EBUSY;
95 96
96 if (copy_from_user(&u, (drm_unique_t __user *)arg, sizeof(u))) 97 if (copy_from_user(&u, (drm_unique_t __user *) arg, sizeof(u)))
97 return -EFAULT; 98 return -EFAULT;
98 99
99 if (!u.unique_len || u.unique_len > 1024) return -EINVAL; 100 if (!u.unique_len || u.unique_len > 1024)
101 return -EINVAL;
100 102
101 dev->unique_len = u.unique_len; 103 dev->unique_len = u.unique_len;
102 dev->unique = drm_alloc(u.unique_len + 1, DRM_MEM_DRIVER); 104 dev->unique = drm_alloc(u.unique_len + 1, DRM_MEM_DRIVER);
103 if(!dev->unique) return -ENOMEM; 105 if (!dev->unique)
106 return -ENOMEM;
104 if (copy_from_user(dev->unique, u.unique, dev->unique_len)) 107 if (copy_from_user(dev->unique, u.unique, dev->unique_len))
105 return -EFAULT; 108 return -EFAULT;
106 109
107 dev->unique[dev->unique_len] = '\0'; 110 dev->unique[dev->unique_len] = '\0';
108 111
109 dev->devname = drm_alloc(strlen(dev->driver->pci_driver.name) + strlen(dev->unique) + 2, 112 dev->devname =
110 DRM_MEM_DRIVER); 113 drm_alloc(strlen(dev->driver->pci_driver.name) +
114 strlen(dev->unique) + 2, DRM_MEM_DRIVER);
111 if (!dev->devname) 115 if (!dev->devname)
112 return -ENOMEM; 116 return -ENOMEM;
113 117
114 sprintf(dev->devname, "%s@%s", dev->driver->pci_driver.name, dev->unique); 118 sprintf(dev->devname, "%s@%s", dev->driver->pci_driver.name,
119 dev->unique);
115 120
116 /* Return error if the busid submitted doesn't match the device's actual 121 /* Return error if the busid submitted doesn't match the device's actual
117 * busid. 122 * busid.
@@ -121,18 +126,16 @@ int drm_setunique(struct inode *inode, struct file *filp,
121 return DRM_ERR(EINVAL); 126 return DRM_ERR(EINVAL);
122 domain = bus >> 8; 127 domain = bus >> 8;
123 bus &= 0xff; 128 bus &= 0xff;
124 129
125 if ((domain != dev->pci_domain) || 130 if ((domain != dev->pci_domain) ||
126 (bus != dev->pci_bus) || 131 (bus != dev->pci_bus) ||
127 (slot != dev->pci_slot) || 132 (slot != dev->pci_slot) || (func != dev->pci_func))
128 (func != dev->pci_func))
129 return -EINVAL; 133 return -EINVAL;
130 134
131 return 0; 135 return 0;
132} 136}
133 137
134static int 138static int drm_set_busid(drm_device_t * dev)
135drm_set_busid(drm_device_t *dev)
136{ 139{
137 if (dev->unique != NULL) 140 if (dev->unique != NULL)
138 return EBUSY; 141 return EBUSY;
@@ -143,19 +146,20 @@ drm_set_busid(drm_device_t *dev)
143 return ENOMEM; 146 return ENOMEM;
144 147
145 snprintf(dev->unique, dev->unique_len, "pci:%04x:%02x:%02x.%d", 148 snprintf(dev->unique, dev->unique_len, "pci:%04x:%02x:%02x.%d",
146 dev->pci_domain, dev->pci_bus, dev->pci_slot, dev->pci_func); 149 dev->pci_domain, dev->pci_bus, dev->pci_slot, dev->pci_func);
147 150
148 dev->devname = drm_alloc(strlen(dev->driver->pci_driver.name) + dev->unique_len + 2, 151 dev->devname =
149 DRM_MEM_DRIVER); 152 drm_alloc(strlen(dev->driver->pci_driver.name) + dev->unique_len +
153 2, DRM_MEM_DRIVER);
150 if (dev->devname == NULL) 154 if (dev->devname == NULL)
151 return ENOMEM; 155 return ENOMEM;
152 156
153 sprintf(dev->devname, "%s@%s", dev->driver->pci_driver.name, dev->unique); 157 sprintf(dev->devname, "%s@%s", dev->driver->pci_driver.name,
158 dev->unique);
154 159
155 return 0; 160 return 0;
156} 161}
157 162
158
159/** 163/**
160 * Get a mapping information. 164 * Get a mapping information.
161 * 165 *
@@ -163,23 +167,23 @@ drm_set_busid(drm_device_t *dev)
163 * \param filp file pointer. 167 * \param filp file pointer.
164 * \param cmd command. 168 * \param cmd command.
165 * \param arg user argument, pointing to a drm_map structure. 169 * \param arg user argument, pointing to a drm_map structure.
166 * 170 *
167 * \return zero on success or a negative number on failure. 171 * \return zero on success or a negative number on failure.
168 * 172 *
169 * Searches for the mapping with the specified offset and copies its information 173 * Searches for the mapping with the specified offset and copies its information
170 * into userspace 174 * into userspace
171 */ 175 */
172int drm_getmap( struct inode *inode, struct file *filp, 176int drm_getmap(struct inode *inode, struct file *filp,
173 unsigned int cmd, unsigned long arg ) 177 unsigned int cmd, unsigned long arg)
174{ 178{
175 drm_file_t *priv = filp->private_data; 179 drm_file_t *priv = filp->private_data;
176 drm_device_t *dev = priv->head->dev; 180 drm_device_t *dev = priv->head->dev;
177 drm_map_t __user *argp = (void __user *)arg; 181 drm_map_t __user *argp = (void __user *)arg;
178 drm_map_t map; 182 drm_map_t map;
179 drm_map_list_t *r_list = NULL; 183 drm_map_list_t *r_list = NULL;
180 struct list_head *list; 184 struct list_head *list;
181 int idx; 185 int idx;
182 int i; 186 int i;
183 187
184 if (copy_from_user(&map, argp, sizeof(map))) 188 if (copy_from_user(&map, argp, sizeof(map)))
185 return -EFAULT; 189 return -EFAULT;
@@ -193,26 +197,27 @@ int drm_getmap( struct inode *inode, struct file *filp,
193 197
194 i = 0; 198 i = 0;
195 list_for_each(list, &dev->maplist->head) { 199 list_for_each(list, &dev->maplist->head) {
196 if(i == idx) { 200 if (i == idx) {
197 r_list = list_entry(list, drm_map_list_t, head); 201 r_list = list_entry(list, drm_map_list_t, head);
198 break; 202 break;
199 } 203 }
200 i++; 204 i++;
201 } 205 }
202 if(!r_list || !r_list->map) { 206 if (!r_list || !r_list->map) {
203 up(&dev->struct_sem); 207 up(&dev->struct_sem);
204 return -EINVAL; 208 return -EINVAL;
205 } 209 }
206 210
207 map.offset = r_list->map->offset; 211 map.offset = r_list->map->offset;
208 map.size = r_list->map->size; 212 map.size = r_list->map->size;
209 map.type = r_list->map->type; 213 map.type = r_list->map->type;
210 map.flags = r_list->map->flags; 214 map.flags = r_list->map->flags;
211 map.handle = (void *)(unsigned long) r_list->user_token; 215 map.handle = (void *)(unsigned long)r_list->user_token;
212 map.mtrr = r_list->map->mtrr; 216 map.mtrr = r_list->map->mtrr;
213 up(&dev->struct_sem); 217 up(&dev->struct_sem);
214 218
215 if (copy_to_user(argp, &map, sizeof(map))) return -EFAULT; 219 if (copy_to_user(argp, &map, sizeof(map)))
220 return -EFAULT;
216 return 0; 221 return 0;
217} 222}
218 223
@@ -223,83 +228,81 @@ int drm_getmap( struct inode *inode, struct file *filp,
223 * \param filp file pointer. 228 * \param filp file pointer.
224 * \param cmd command. 229 * \param cmd command.
225 * \param arg user argument, pointing to a drm_client structure. 230 * \param arg user argument, pointing to a drm_client structure.
226 * 231 *
227 * \return zero on success or a negative number on failure. 232 * \return zero on success or a negative number on failure.
228 * 233 *
229 * Searches for the client with the specified index and copies its information 234 * Searches for the client with the specified index and copies its information
230 * into userspace 235 * into userspace
231 */ 236 */
232int drm_getclient( struct inode *inode, struct file *filp, 237int drm_getclient(struct inode *inode, struct file *filp,
233 unsigned int cmd, unsigned long arg ) 238 unsigned int cmd, unsigned long arg)
234{ 239{
235 drm_file_t *priv = filp->private_data; 240 drm_file_t *priv = filp->private_data;
236 drm_device_t *dev = priv->head->dev; 241 drm_device_t *dev = priv->head->dev;
237 drm_client_t __user *argp = (void __user *)arg; 242 drm_client_t __user *argp = (void __user *)arg;
238 drm_client_t client; 243 drm_client_t client;
239 drm_file_t *pt; 244 drm_file_t *pt;
240 int idx; 245 int idx;
241 int i; 246 int i;
242 247
243 if (copy_from_user(&client, argp, sizeof(client))) 248 if (copy_from_user(&client, argp, sizeof(client)))
244 return -EFAULT; 249 return -EFAULT;
245 idx = client.idx; 250 idx = client.idx;
246 down(&dev->struct_sem); 251 down(&dev->struct_sem);
247 for (i = 0, pt = dev->file_first; i < idx && pt; i++, pt = pt->next) 252 for (i = 0, pt = dev->file_first; i < idx && pt; i++, pt = pt->next) ;
248 ;
249 253
250 if (!pt) { 254 if (!pt) {
251 up(&dev->struct_sem); 255 up(&dev->struct_sem);
252 return -EINVAL; 256 return -EINVAL;
253 } 257 }
254 client.auth = pt->authenticated; 258 client.auth = pt->authenticated;
255 client.pid = pt->pid; 259 client.pid = pt->pid;
256 client.uid = pt->uid; 260 client.uid = pt->uid;
257 client.magic = pt->magic; 261 client.magic = pt->magic;
258 client.iocs = pt->ioctl_count; 262 client.iocs = pt->ioctl_count;
259 up(&dev->struct_sem); 263 up(&dev->struct_sem);
260 264
261 if (copy_to_user((drm_client_t __user *)arg, &client, sizeof(client))) 265 if (copy_to_user((drm_client_t __user *) arg, &client, sizeof(client)))
262 return -EFAULT; 266 return -EFAULT;
263 return 0; 267 return 0;
264} 268}
265 269
266/** 270/**
267 * Get statistics information. 271 * Get statistics information.
268 * 272 *
269 * \param inode device inode. 273 * \param inode device inode.
270 * \param filp file pointer. 274 * \param filp file pointer.
271 * \param cmd command. 275 * \param cmd command.
272 * \param arg user argument, pointing to a drm_stats structure. 276 * \param arg user argument, pointing to a drm_stats structure.
273 * 277 *
274 * \return zero on success or a negative number on failure. 278 * \return zero on success or a negative number on failure.
275 */ 279 */
276int drm_getstats( struct inode *inode, struct file *filp, 280int drm_getstats(struct inode *inode, struct file *filp,
277 unsigned int cmd, unsigned long arg ) 281 unsigned int cmd, unsigned long arg)
278{ 282{
279 drm_file_t *priv = filp->private_data; 283 drm_file_t *priv = filp->private_data;
280 drm_device_t *dev = priv->head->dev; 284 drm_device_t *dev = priv->head->dev;
281 drm_stats_t stats; 285 drm_stats_t stats;
282 int i; 286 int i;
283 287
284 memset(&stats, 0, sizeof(stats)); 288 memset(&stats, 0, sizeof(stats));
285 289
286 down(&dev->struct_sem); 290 down(&dev->struct_sem);
287 291
288 for (i = 0; i < dev->counters; i++) { 292 for (i = 0; i < dev->counters; i++) {
289 if (dev->types[i] == _DRM_STAT_LOCK) 293 if (dev->types[i] == _DRM_STAT_LOCK)
290 stats.data[i].value 294 stats.data[i].value
291 = (dev->lock.hw_lock 295 = (dev->lock.hw_lock ? dev->lock.hw_lock->lock : 0);
292 ? dev->lock.hw_lock->lock : 0); 296 else
293 else
294 stats.data[i].value = atomic_read(&dev->counts[i]); 297 stats.data[i].value = atomic_read(&dev->counts[i]);
295 stats.data[i].type = dev->types[i]; 298 stats.data[i].type = dev->types[i];
296 } 299 }
297 300
298 stats.count = dev->counters; 301 stats.count = dev->counters;
299 302
300 up(&dev->struct_sem); 303 up(&dev->struct_sem);
301 304
302 if (copy_to_user((drm_stats_t __user *)arg, &stats, sizeof(stats))) 305 if (copy_to_user((drm_stats_t __user *) arg, &stats, sizeof(stats)))
303 return -EFAULT; 306 return -EFAULT;
304 return 0; 307 return 0;
305} 308}
@@ -352,7 +355,8 @@ int drm_setversion(DRM_IOCTL_ARGS)
352 355
353 if (sv.drm_dd_major != -1) { 356 if (sv.drm_dd_major != -1) {
354 if (sv.drm_dd_major != version.version_major || 357 if (sv.drm_dd_major != version.version_major ||
355 sv.drm_dd_minor < 0 || sv.drm_dd_minor > version.version_minor) 358 sv.drm_dd_minor < 0
359 || sv.drm_dd_minor > version.version_minor)
356 return EINVAL; 360 return EINVAL;
357 361
358 if (dev->driver->set_version) 362 if (dev->driver->set_version)
@@ -363,7 +367,7 @@ int drm_setversion(DRM_IOCTL_ARGS)
363 367
364/** No-op ioctl. */ 368/** No-op ioctl. */
365int drm_noop(struct inode *inode, struct file *filp, unsigned int cmd, 369int drm_noop(struct inode *inode, struct file *filp, unsigned int cmd,
366 unsigned long arg) 370 unsigned long arg)
367{ 371{
368 DRM_DEBUG("\n"); 372 DRM_DEBUG("\n");
369 return 0; 373 return 0;
diff --git a/drivers/char/drm/drm_irq.c b/drivers/char/drm/drm_irq.c
index cdd4aecd25e2..b0d4b236e837 100644
--- a/drivers/char/drm/drm_irq.c
+++ b/drivers/char/drm/drm_irq.c
@@ -1,5 +1,5 @@
1/** 1/**
2 * \file drm_irq.h 2 * \file drm_irq.c
3 * IRQ support 3 * IRQ support
4 * 4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
@@ -39,19 +39,19 @@
39 39
40/** 40/**
41 * Get interrupt from bus id. 41 * Get interrupt from bus id.
42 * 42 *
43 * \param inode device inode. 43 * \param inode device inode.
44 * \param filp file pointer. 44 * \param filp file pointer.
45 * \param cmd command. 45 * \param cmd command.
46 * \param arg user argument, pointing to a drm_irq_busid structure. 46 * \param arg user argument, pointing to a drm_irq_busid structure.
47 * \return zero on success or a negative number on failure. 47 * \return zero on success or a negative number on failure.
48 * 48 *
49 * Finds the PCI device with the specified bus id and gets its IRQ number. 49 * Finds the PCI device with the specified bus id and gets its IRQ number.
50 * This IOCTL is deprecated, and will now return EINVAL for any busid not equal 50 * This IOCTL is deprecated, and will now return EINVAL for any busid not equal
51 * to that of the device that this DRM instance attached to. 51 * to that of the device that this DRM instance attached to.
52 */ 52 */
53int drm_irq_by_busid(struct inode *inode, struct file *filp, 53int drm_irq_by_busid(struct inode *inode, struct file *filp,
54 unsigned int cmd, unsigned long arg) 54 unsigned int cmd, unsigned long arg)
55{ 55{
56 drm_file_t *priv = filp->private_data; 56 drm_file_t *priv = filp->private_data;
57 drm_device_t *dev = priv->head->dev; 57 drm_device_t *dev = priv->head->dev;
@@ -66,14 +66,12 @@ int drm_irq_by_busid(struct inode *inode, struct file *filp,
66 66
67 if ((p.busnum >> 8) != dev->pci_domain || 67 if ((p.busnum >> 8) != dev->pci_domain ||
68 (p.busnum & 0xff) != dev->pci_bus || 68 (p.busnum & 0xff) != dev->pci_bus ||
69 p.devnum != dev->pci_slot || 69 p.devnum != dev->pci_slot || p.funcnum != dev->pci_func)
70 p.funcnum != dev->pci_func)
71 return -EINVAL; 70 return -EINVAL;
72 71
73 p.irq = dev->irq; 72 p.irq = dev->irq;
74 73
75 DRM_DEBUG("%d:%d:%d => IRQ %d\n", 74 DRM_DEBUG("%d:%d:%d => IRQ %d\n", p.busnum, p.devnum, p.funcnum, p.irq);
76 p.busnum, p.devnum, p.funcnum, p.irq);
77 if (copy_to_user(argp, &p, sizeof(p))) 75 if (copy_to_user(argp, &p, sizeof(p)))
78 return -EFAULT; 76 return -EFAULT;
79 return 0; 77 return 0;
@@ -89,61 +87,61 @@ int drm_irq_by_busid(struct inode *inode, struct file *filp,
89 * \c drm_driver_irq_preinstall() and \c drm_driver_irq_postinstall() functions 87 * \c drm_driver_irq_preinstall() and \c drm_driver_irq_postinstall() functions
90 * before and after the installation. 88 * before and after the installation.
91 */ 89 */
92static int drm_irq_install( drm_device_t *dev ) 90static int drm_irq_install(drm_device_t * dev)
93{ 91{
94 int ret; 92 int ret;
95 unsigned long sh_flags=0; 93 unsigned long sh_flags = 0;
96 94
97 if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ)) 95 if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
98 return -EINVAL; 96 return -EINVAL;
99 97
100 if ( dev->irq == 0 ) 98 if (dev->irq == 0)
101 return -EINVAL; 99 return -EINVAL;
102 100
103 down( &dev->struct_sem ); 101 down(&dev->struct_sem);
104 102
105 /* Driver must have been initialized */ 103 /* Driver must have been initialized */
106 if ( !dev->dev_private ) { 104 if (!dev->dev_private) {
107 up( &dev->struct_sem ); 105 up(&dev->struct_sem);
108 return -EINVAL; 106 return -EINVAL;
109 } 107 }
110 108
111 if ( dev->irq_enabled ) { 109 if (dev->irq_enabled) {
112 up( &dev->struct_sem ); 110 up(&dev->struct_sem);
113 return -EBUSY; 111 return -EBUSY;
114 } 112 }
115 dev->irq_enabled = 1; 113 dev->irq_enabled = 1;
116 up( &dev->struct_sem ); 114 up(&dev->struct_sem);
117 115
118 DRM_DEBUG( "%s: irq=%d\n", __FUNCTION__, dev->irq ); 116 DRM_DEBUG("%s: irq=%d\n", __FUNCTION__, dev->irq);
119 117
120 if (drm_core_check_feature(dev, DRIVER_IRQ_VBL)) { 118 if (drm_core_check_feature(dev, DRIVER_IRQ_VBL)) {
121 init_waitqueue_head(&dev->vbl_queue); 119 init_waitqueue_head(&dev->vbl_queue);
122 120
123 spin_lock_init( &dev->vbl_lock ); 121 spin_lock_init(&dev->vbl_lock);
124 122
125 INIT_LIST_HEAD( &dev->vbl_sigs.head ); 123 INIT_LIST_HEAD(&dev->vbl_sigs.head);
126 124
127 dev->vbl_pending = 0; 125 dev->vbl_pending = 0;
128 } 126 }
129 127
130 /* Before installing handler */ 128 /* Before installing handler */
131 dev->driver->irq_preinstall(dev); 129 dev->driver->irq_preinstall(dev);
132 130
133 /* Install handler */ 131 /* Install handler */
134 if (drm_core_check_feature(dev, DRIVER_IRQ_SHARED)) 132 if (drm_core_check_feature(dev, DRIVER_IRQ_SHARED))
135 sh_flags = SA_SHIRQ; 133 sh_flags = SA_SHIRQ;
136 134
137 ret = request_irq( dev->irq, dev->driver->irq_handler, 135 ret = request_irq(dev->irq, dev->driver->irq_handler,
138 sh_flags, dev->devname, dev ); 136 sh_flags, dev->devname, dev);
139 if ( ret < 0 ) { 137 if (ret < 0) {
140 down( &dev->struct_sem ); 138 down(&dev->struct_sem);
141 dev->irq_enabled = 0; 139 dev->irq_enabled = 0;
142 up( &dev->struct_sem ); 140 up(&dev->struct_sem);
143 return ret; 141 return ret;
144 } 142 }
145 143
146 /* After installing handler */ 144 /* After installing handler */
147 dev->driver->irq_postinstall(dev); 145 dev->driver->irq_postinstall(dev);
148 146
149 return 0; 147 return 0;
@@ -156,29 +154,30 @@ static int drm_irq_install( drm_device_t *dev )
156 * 154 *
157 * Calls the driver's \c drm_driver_irq_uninstall() function, and stops the irq. 155 * Calls the driver's \c drm_driver_irq_uninstall() function, and stops the irq.
158 */ 156 */
159int drm_irq_uninstall( drm_device_t *dev ) 157int drm_irq_uninstall(drm_device_t * dev)
160{ 158{
161 int irq_enabled; 159 int irq_enabled;
162 160
163 if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ)) 161 if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
164 return -EINVAL; 162 return -EINVAL;
165 163
166 down( &dev->struct_sem ); 164 down(&dev->struct_sem);
167 irq_enabled = dev->irq_enabled; 165 irq_enabled = dev->irq_enabled;
168 dev->irq_enabled = 0; 166 dev->irq_enabled = 0;
169 up( &dev->struct_sem ); 167 up(&dev->struct_sem);
170 168
171 if ( !irq_enabled ) 169 if (!irq_enabled)
172 return -EINVAL; 170 return -EINVAL;
173 171
174 DRM_DEBUG( "%s: irq=%d\n", __FUNCTION__, dev->irq ); 172 DRM_DEBUG("%s: irq=%d\n", __FUNCTION__, dev->irq);
175 173
176 dev->driver->irq_uninstall(dev); 174 dev->driver->irq_uninstall(dev);
177 175
178 free_irq( dev->irq, dev ); 176 free_irq(dev->irq, dev);
179 177
180 return 0; 178 return 0;
181} 179}
180
182EXPORT_SYMBOL(drm_irq_uninstall); 181EXPORT_SYMBOL(drm_irq_uninstall);
183 182
184/** 183/**
@@ -192,30 +191,30 @@ EXPORT_SYMBOL(drm_irq_uninstall);
192 * 191 *
193 * Calls irq_install() or irq_uninstall() according to \p arg. 192 * Calls irq_install() or irq_uninstall() according to \p arg.
194 */ 193 */
195int drm_control( struct inode *inode, struct file *filp, 194int drm_control(struct inode *inode, struct file *filp,
196 unsigned int cmd, unsigned long arg ) 195 unsigned int cmd, unsigned long arg)
197{ 196{
198 drm_file_t *priv = filp->private_data; 197 drm_file_t *priv = filp->private_data;
199 drm_device_t *dev = priv->head->dev; 198 drm_device_t *dev = priv->head->dev;
200 drm_control_t ctl; 199 drm_control_t ctl;
201 200
202 /* if we haven't irq we fallback for compatibility reasons - this used to be a separate function in drm_dma.h */ 201 /* if we haven't irq we fallback for compatibility reasons - this used to be a separate function in drm_dma.h */
203 202
204 if ( copy_from_user( &ctl, (drm_control_t __user *)arg, sizeof(ctl) ) ) 203 if (copy_from_user(&ctl, (drm_control_t __user *) arg, sizeof(ctl)))
205 return -EFAULT; 204 return -EFAULT;
206 205
207 switch ( ctl.func ) { 206 switch (ctl.func) {
208 case DRM_INST_HANDLER: 207 case DRM_INST_HANDLER:
209 if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ)) 208 if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
210 return 0; 209 return 0;
211 if (dev->if_version < DRM_IF_VERSION(1, 2) && 210 if (dev->if_version < DRM_IF_VERSION(1, 2) &&
212 ctl.irq != dev->irq) 211 ctl.irq != dev->irq)
213 return -EINVAL; 212 return -EINVAL;
214 return drm_irq_install( dev ); 213 return drm_irq_install(dev);
215 case DRM_UNINST_HANDLER: 214 case DRM_UNINST_HANDLER:
216 if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ)) 215 if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
217 return 0; 216 return 0;
218 return drm_irq_uninstall( dev ); 217 return drm_irq_uninstall(dev);
219 default: 218 default:
220 return -EINVAL; 219 return -EINVAL;
221 } 220 }
@@ -230,7 +229,7 @@ int drm_control( struct inode *inode, struct file *filp,
230 * \param data user argument, pointing to a drm_wait_vblank structure. 229 * \param data user argument, pointing to a drm_wait_vblank structure.
231 * \return zero on success or a negative number on failure. 230 * \return zero on success or a negative number on failure.
232 * 231 *
233 * Verifies the IRQ is installed. 232 * Verifies the IRQ is installed.
234 * 233 *
235 * If a signal is requested checks if this task has already scheduled the same signal 234 * If a signal is requested checks if this task has already scheduled the same signal
236 * for the same vblank sequence number - nothing to be done in 235 * for the same vblank sequence number - nothing to be done in
@@ -240,7 +239,7 @@ int drm_control( struct inode *inode, struct file *filp,
240 * 239 *
241 * If a signal is not requested, then calls vblank_wait(). 240 * If a signal is not requested, then calls vblank_wait().
242 */ 241 */
243int drm_wait_vblank( DRM_IOCTL_ARGS ) 242int drm_wait_vblank(DRM_IOCTL_ARGS)
244{ 243{
245 drm_file_t *priv = filp->private_data; 244 drm_file_t *priv = filp->private_data;
246 drm_device_t *dev = priv->head->dev; 245 drm_device_t *dev = priv->head->dev;
@@ -256,11 +255,11 @@ int drm_wait_vblank( DRM_IOCTL_ARGS )
256 if (!dev->irq) 255 if (!dev->irq)
257 return -EINVAL; 256 return -EINVAL;
258 257
259 DRM_COPY_FROM_USER_IOCTL( vblwait, argp, sizeof(vblwait) ); 258 DRM_COPY_FROM_USER_IOCTL(vblwait, argp, sizeof(vblwait));
260 259
261 switch ( vblwait.request.type & ~_DRM_VBLANK_FLAGS_MASK ) { 260 switch (vblwait.request.type & ~_DRM_VBLANK_FLAGS_MASK) {
262 case _DRM_VBLANK_RELATIVE: 261 case _DRM_VBLANK_RELATIVE:
263 vblwait.request.sequence += atomic_read( &dev->vbl_received ); 262 vblwait.request.sequence += atomic_read(&dev->vbl_received);
264 vblwait.request.type &= ~_DRM_VBLANK_RELATIVE; 263 vblwait.request.type &= ~_DRM_VBLANK_RELATIVE;
265 case _DRM_VBLANK_ABSOLUTE: 264 case _DRM_VBLANK_ABSOLUTE:
266 break; 265 break;
@@ -269,64 +268,68 @@ int drm_wait_vblank( DRM_IOCTL_ARGS )
269 } 268 }
270 269
271 flags = vblwait.request.type & _DRM_VBLANK_FLAGS_MASK; 270 flags = vblwait.request.type & _DRM_VBLANK_FLAGS_MASK;
272 271
273 if ( flags & _DRM_VBLANK_SIGNAL ) { 272 if (flags & _DRM_VBLANK_SIGNAL) {
274 unsigned long irqflags; 273 unsigned long irqflags;
275 drm_vbl_sig_t *vbl_sig; 274 drm_vbl_sig_t *vbl_sig;
276
277 vblwait.reply.sequence = atomic_read( &dev->vbl_received );
278 275
279 spin_lock_irqsave( &dev->vbl_lock, irqflags ); 276 vblwait.reply.sequence = atomic_read(&dev->vbl_received);
277
278 spin_lock_irqsave(&dev->vbl_lock, irqflags);
280 279
281 /* Check if this task has already scheduled the same signal 280 /* Check if this task has already scheduled the same signal
282 * for the same vblank sequence number; nothing to be done in 281 * for the same vblank sequence number; nothing to be done in
283 * that case 282 * that case
284 */ 283 */
285 list_for_each_entry( vbl_sig, &dev->vbl_sigs.head, head ) { 284 list_for_each_entry(vbl_sig, &dev->vbl_sigs.head, head) {
286 if (vbl_sig->sequence == vblwait.request.sequence 285 if (vbl_sig->sequence == vblwait.request.sequence
287 && vbl_sig->info.si_signo == vblwait.request.signal 286 && vbl_sig->info.si_signo == vblwait.request.signal
288 && vbl_sig->task == current) 287 && vbl_sig->task == current) {
289 { 288 spin_unlock_irqrestore(&dev->vbl_lock,
290 spin_unlock_irqrestore( &dev->vbl_lock, irqflags ); 289 irqflags);
291 goto done; 290 goto done;
292 } 291 }
293 } 292 }
294 293
295 if ( dev->vbl_pending >= 100 ) { 294 if (dev->vbl_pending >= 100) {
296 spin_unlock_irqrestore( &dev->vbl_lock, irqflags ); 295 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
297 return -EBUSY; 296 return -EBUSY;
298 } 297 }
299 298
300 dev->vbl_pending++; 299 dev->vbl_pending++;
301 300
302 spin_unlock_irqrestore( &dev->vbl_lock, irqflags ); 301 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
303 302
304 if ( !( vbl_sig = drm_alloc( sizeof( drm_vbl_sig_t ), DRM_MEM_DRIVER ) ) ) { 303 if (!
304 (vbl_sig =
305 drm_alloc(sizeof(drm_vbl_sig_t), DRM_MEM_DRIVER))) {
305 return -ENOMEM; 306 return -ENOMEM;
306 } 307 }
307 308
308 memset( (void *)vbl_sig, 0, sizeof(*vbl_sig) ); 309 memset((void *)vbl_sig, 0, sizeof(*vbl_sig));
309 310
310 vbl_sig->sequence = vblwait.request.sequence; 311 vbl_sig->sequence = vblwait.request.sequence;
311 vbl_sig->info.si_signo = vblwait.request.signal; 312 vbl_sig->info.si_signo = vblwait.request.signal;
312 vbl_sig->task = current; 313 vbl_sig->task = current;
313 314
314 spin_lock_irqsave( &dev->vbl_lock, irqflags ); 315 spin_lock_irqsave(&dev->vbl_lock, irqflags);
315 316
316 list_add_tail( (struct list_head *) vbl_sig, &dev->vbl_sigs.head ); 317 list_add_tail((struct list_head *)vbl_sig, &dev->vbl_sigs.head);
317 318
318 spin_unlock_irqrestore( &dev->vbl_lock, irqflags ); 319 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
319 } else { 320 } else {
320 if (dev->driver->vblank_wait) 321 if (dev->driver->vblank_wait)
321 ret = dev->driver->vblank_wait( dev, &vblwait.request.sequence ); 322 ret =
323 dev->driver->vblank_wait(dev,
324 &vblwait.request.sequence);
322 325
323 do_gettimeofday( &now ); 326 do_gettimeofday(&now);
324 vblwait.reply.tval_sec = now.tv_sec; 327 vblwait.reply.tval_sec = now.tv_sec;
325 vblwait.reply.tval_usec = now.tv_usec; 328 vblwait.reply.tval_usec = now.tv_usec;
326 } 329 }
327 330
328done: 331 done:
329 DRM_COPY_TO_USER_IOCTL( argp, vblwait, sizeof(vblwait) ); 332 DRM_COPY_TO_USER_IOCTL(argp, vblwait, sizeof(vblwait));
330 333
331 return ret; 334 return ret;
332} 335}
@@ -340,31 +343,31 @@ done:
340 * 343 *
341 * If a signal is not requested, then calls vblank_wait(). 344 * If a signal is not requested, then calls vblank_wait().
342 */ 345 */
343void drm_vbl_send_signals( drm_device_t *dev ) 346void drm_vbl_send_signals(drm_device_t * dev)
344{ 347{
345 struct list_head *list, *tmp; 348 struct list_head *list, *tmp;
346 drm_vbl_sig_t *vbl_sig; 349 drm_vbl_sig_t *vbl_sig;
347 unsigned int vbl_seq = atomic_read( &dev->vbl_received ); 350 unsigned int vbl_seq = atomic_read(&dev->vbl_received);
348 unsigned long flags; 351 unsigned long flags;
349 352
350 spin_lock_irqsave( &dev->vbl_lock, flags ); 353 spin_lock_irqsave(&dev->vbl_lock, flags);
351 354
352 list_for_each_safe( list, tmp, &dev->vbl_sigs.head ) { 355 list_for_each_safe(list, tmp, &dev->vbl_sigs.head) {
353 vbl_sig = list_entry( list, drm_vbl_sig_t, head ); 356 vbl_sig = list_entry(list, drm_vbl_sig_t, head);
354 if ( ( vbl_seq - vbl_sig->sequence ) <= (1<<23) ) { 357 if ((vbl_seq - vbl_sig->sequence) <= (1 << 23)) {
355 vbl_sig->info.si_code = vbl_seq; 358 vbl_sig->info.si_code = vbl_seq;
356 send_sig_info( vbl_sig->info.si_signo, &vbl_sig->info, vbl_sig->task ); 359 send_sig_info(vbl_sig->info.si_signo, &vbl_sig->info,
360 vbl_sig->task);
357 361
358 list_del( list ); 362 list_del(list);
359 363
360 drm_free( vbl_sig, sizeof(*vbl_sig), DRM_MEM_DRIVER ); 364 drm_free(vbl_sig, sizeof(*vbl_sig), DRM_MEM_DRIVER);
361 365
362 dev->vbl_pending--; 366 dev->vbl_pending--;
363 } 367 }
364 } 368 }
365 369
366 spin_unlock_irqrestore( &dev->vbl_lock, flags ); 370 spin_unlock_irqrestore(&dev->vbl_lock, flags);
367} 371}
368EXPORT_SYMBOL(drm_vbl_send_signals);
369
370 372
373EXPORT_SYMBOL(drm_vbl_send_signals);
diff --git a/drivers/char/drm/drm_lock.c b/drivers/char/drm/drm_lock.c
index 4702d863bcc6..b276ae8a6633 100644
--- a/drivers/char/drm/drm_lock.c
+++ b/drivers/char/drm/drm_lock.c
@@ -1,7 +1,7 @@
1/** 1/**
2 * \file drm_lock.h 2 * \file drm_lock.c
3 * IOCTLs for locking 3 * IOCTLs for locking
4 * 4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
6 * \author Gareth Hughes <gareth@valinux.com> 6 * \author Gareth Hughes <gareth@valinux.com>
7 */ 7 */
@@ -35,12 +35,12 @@
35 35
36#include "drmP.h" 36#include "drmP.h"
37 37
38static int drm_lock_transfer(drm_device_t *dev, 38static int drm_lock_transfer(drm_device_t * dev,
39 __volatile__ unsigned int *lock, 39 __volatile__ unsigned int *lock,
40 unsigned int context); 40 unsigned int context);
41static int drm_notifier(void *priv); 41static int drm_notifier(void *priv);
42 42
43/** 43/**
44 * Lock ioctl. 44 * Lock ioctl.
45 * 45 *
46 * \param inode device inode. 46 * \param inode device inode.
@@ -51,91 +51,89 @@ static int drm_notifier(void *priv);
51 * 51 *
52 * Add the current task to the lock wait queue, and attempt to take to lock. 52 * Add the current task to the lock wait queue, and attempt to take to lock.
53 */ 53 */
54int drm_lock( struct inode *inode, struct file *filp, 54int drm_lock(struct inode *inode, struct file *filp,
55 unsigned int cmd, unsigned long arg ) 55 unsigned int cmd, unsigned long arg)
56{ 56{
57 drm_file_t *priv = filp->private_data; 57 drm_file_t *priv = filp->private_data;
58 drm_device_t *dev = priv->head->dev; 58 drm_device_t *dev = priv->head->dev;
59 DECLARE_WAITQUEUE( entry, current ); 59 DECLARE_WAITQUEUE(entry, current);
60 drm_lock_t lock; 60 drm_lock_t lock;
61 int ret = 0; 61 int ret = 0;
62 62
63 ++priv->lock_count; 63 ++priv->lock_count;
64 64
65 if ( copy_from_user( &lock, (drm_lock_t __user *)arg, sizeof(lock) ) ) 65 if (copy_from_user(&lock, (drm_lock_t __user *) arg, sizeof(lock)))
66 return -EFAULT; 66 return -EFAULT;
67 67
68 if ( lock.context == DRM_KERNEL_CONTEXT ) { 68 if (lock.context == DRM_KERNEL_CONTEXT) {
69 DRM_ERROR( "Process %d using kernel context %d\n", 69 DRM_ERROR("Process %d using kernel context %d\n",
70 current->pid, lock.context ); 70 current->pid, lock.context);
71 return -EINVAL; 71 return -EINVAL;
72 } 72 }
73 73
74 DRM_DEBUG( "%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n", 74 DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n",
75 lock.context, current->pid, 75 lock.context, current->pid,
76 dev->lock.hw_lock->lock, lock.flags ); 76 dev->lock.hw_lock->lock, lock.flags);
77 77
78 if (drm_core_check_feature(dev, DRIVER_DMA_QUEUE)) 78 if (drm_core_check_feature(dev, DRIVER_DMA_QUEUE))
79 if ( lock.context < 0 ) 79 if (lock.context < 0)
80 return -EINVAL; 80 return -EINVAL;
81 81
82 add_wait_queue( &dev->lock.lock_queue, &entry ); 82 add_wait_queue(&dev->lock.lock_queue, &entry);
83 for (;;) { 83 for (;;) {
84 __set_current_state(TASK_INTERRUPTIBLE); 84 __set_current_state(TASK_INTERRUPTIBLE);
85 if ( !dev->lock.hw_lock ) { 85 if (!dev->lock.hw_lock) {
86 /* Device has been unregistered */ 86 /* Device has been unregistered */
87 ret = -EINTR; 87 ret = -EINTR;
88 break; 88 break;
89 } 89 }
90 if ( drm_lock_take( &dev->lock.hw_lock->lock, 90 if (drm_lock_take(&dev->lock.hw_lock->lock, lock.context)) {
91 lock.context ) ) { 91 dev->lock.filp = filp;
92 dev->lock.filp = filp;
93 dev->lock.lock_time = jiffies; 92 dev->lock.lock_time = jiffies;
94 atomic_inc( &dev->counts[_DRM_STAT_LOCKS] ); 93 atomic_inc(&dev->counts[_DRM_STAT_LOCKS]);
95 break; /* Got lock */ 94 break; /* Got lock */
96 } 95 }
97 96
98 /* Contention */ 97 /* Contention */
99 schedule(); 98 schedule();
100 if ( signal_pending( current ) ) { 99 if (signal_pending(current)) {
101 ret = -ERESTARTSYS; 100 ret = -ERESTARTSYS;
102 break; 101 break;
103 } 102 }
104 } 103 }
105 __set_current_state(TASK_RUNNING); 104 __set_current_state(TASK_RUNNING);
106 remove_wait_queue( &dev->lock.lock_queue, &entry ); 105 remove_wait_queue(&dev->lock.lock_queue, &entry);
107 106
108 sigemptyset( &dev->sigmask ); 107 sigemptyset(&dev->sigmask);
109 sigaddset( &dev->sigmask, SIGSTOP ); 108 sigaddset(&dev->sigmask, SIGSTOP);
110 sigaddset( &dev->sigmask, SIGTSTP ); 109 sigaddset(&dev->sigmask, SIGTSTP);
111 sigaddset( &dev->sigmask, SIGTTIN ); 110 sigaddset(&dev->sigmask, SIGTTIN);
112 sigaddset( &dev->sigmask, SIGTTOU ); 111 sigaddset(&dev->sigmask, SIGTTOU);
113 dev->sigdata.context = lock.context; 112 dev->sigdata.context = lock.context;
114 dev->sigdata.lock = dev->lock.hw_lock; 113 dev->sigdata.lock = dev->lock.hw_lock;
115 block_all_signals( drm_notifier, 114 block_all_signals(drm_notifier, &dev->sigdata, &dev->sigmask);
116 &dev->sigdata, &dev->sigmask ); 115
117
118 if (dev->driver->dma_ready && (lock.flags & _DRM_LOCK_READY)) 116 if (dev->driver->dma_ready && (lock.flags & _DRM_LOCK_READY))
119 dev->driver->dma_ready(dev); 117 dev->driver->dma_ready(dev);
120 118
121 if ( dev->driver->dma_quiescent && (lock.flags & _DRM_LOCK_QUIESCENT )) 119 if (dev->driver->dma_quiescent && (lock.flags & _DRM_LOCK_QUIESCENT))
122 return dev->driver->dma_quiescent(dev); 120 return dev->driver->dma_quiescent(dev);
123 121
124 /* dev->driver->kernel_context_switch isn't used by any of the x86 122 /* dev->driver->kernel_context_switch isn't used by any of the x86
125 * drivers but is used by the Sparc driver. 123 * drivers but is used by the Sparc driver.
126 */ 124 */
127 125
128 if (dev->driver->kernel_context_switch && 126 if (dev->driver->kernel_context_switch &&
129 dev->last_context != lock.context) { 127 dev->last_context != lock.context) {
130 dev->driver->kernel_context_switch(dev, dev->last_context, 128 dev->driver->kernel_context_switch(dev, dev->last_context,
131 lock.context); 129 lock.context);
132 } 130 }
133 DRM_DEBUG( "%d %s\n", lock.context, ret ? "interrupted" : "has lock" ); 131 DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock");
134 132
135 return ret; 133 return ret;
136} 134}
137 135
138/** 136/**
139 * Unlock ioctl. 137 * Unlock ioctl.
140 * 138 *
141 * \param inode device inode. 139 * \param inode device inode.
@@ -146,23 +144,23 @@ int drm_lock( struct inode *inode, struct file *filp,
146 * 144 *
147 * Transfer and free the lock. 145 * Transfer and free the lock.
148 */ 146 */
149int drm_unlock( struct inode *inode, struct file *filp, 147int drm_unlock(struct inode *inode, struct file *filp,
150 unsigned int cmd, unsigned long arg ) 148 unsigned int cmd, unsigned long arg)
151{ 149{
152 drm_file_t *priv = filp->private_data; 150 drm_file_t *priv = filp->private_data;
153 drm_device_t *dev = priv->head->dev; 151 drm_device_t *dev = priv->head->dev;
154 drm_lock_t lock; 152 drm_lock_t lock;
155 153
156 if ( copy_from_user( &lock, (drm_lock_t __user *)arg, sizeof(lock) ) ) 154 if (copy_from_user(&lock, (drm_lock_t __user *) arg, sizeof(lock)))
157 return -EFAULT; 155 return -EFAULT;
158 156
159 if ( lock.context == DRM_KERNEL_CONTEXT ) { 157 if (lock.context == DRM_KERNEL_CONTEXT) {
160 DRM_ERROR( "Process %d using kernel context %d\n", 158 DRM_ERROR("Process %d using kernel context %d\n",
161 current->pid, lock.context ); 159 current->pid, lock.context);
162 return -EINVAL; 160 return -EINVAL;
163 } 161 }
164 162
165 atomic_inc( &dev->counts[_DRM_STAT_UNLOCKS] ); 163 atomic_inc(&dev->counts[_DRM_STAT_UNLOCKS]);
166 164
167 /* kernel_context_switch isn't used by any of the x86 drm 165 /* kernel_context_switch isn't used by any of the x86 drm
168 * modules but is required by the Sparc driver. 166 * modules but is required by the Sparc driver.
@@ -170,12 +168,12 @@ int drm_unlock( struct inode *inode, struct file *filp,
170 if (dev->driver->kernel_context_switch_unlock) 168 if (dev->driver->kernel_context_switch_unlock)
171 dev->driver->kernel_context_switch_unlock(dev, &lock); 169 dev->driver->kernel_context_switch_unlock(dev, &lock);
172 else { 170 else {
173 drm_lock_transfer( dev, &dev->lock.hw_lock->lock, 171 drm_lock_transfer(dev, &dev->lock.hw_lock->lock,
174 DRM_KERNEL_CONTEXT ); 172 DRM_KERNEL_CONTEXT);
175 173
176 if ( drm_lock_free( dev, &dev->lock.hw_lock->lock, 174 if (drm_lock_free(dev, &dev->lock.hw_lock->lock,
177 DRM_KERNEL_CONTEXT ) ) { 175 DRM_KERNEL_CONTEXT)) {
178 DRM_ERROR( "\n" ); 176 DRM_ERROR("\n");
179 } 177 }
180 } 178 }
181 179
@@ -198,8 +196,10 @@ int drm_lock_take(__volatile__ unsigned int *lock, unsigned int context)
198 196
199 do { 197 do {
200 old = *lock; 198 old = *lock;
201 if (old & _DRM_LOCK_HELD) new = old | _DRM_LOCK_CONT; 199 if (old & _DRM_LOCK_HELD)
202 else new = context | _DRM_LOCK_HELD; 200 new = old | _DRM_LOCK_CONT;
201 else
202 new = context | _DRM_LOCK_HELD;
203 prev = cmpxchg(lock, old, new); 203 prev = cmpxchg(lock, old, new);
204 } while (prev != old); 204 } while (prev != old);
205 if (_DRM_LOCKING_CONTEXT(old) == context) { 205 if (_DRM_LOCKING_CONTEXT(old) == context) {
@@ -212,7 +212,7 @@ int drm_lock_take(__volatile__ unsigned int *lock, unsigned int context)
212 } 212 }
213 } 213 }
214 if (new == (context | _DRM_LOCK_HELD)) { 214 if (new == (context | _DRM_LOCK_HELD)) {
215 /* Have lock */ 215 /* Have lock */
216 return 1; 216 return 1;
217 } 217 }
218 return 0; 218 return 0;
@@ -220,8 +220,8 @@ int drm_lock_take(__volatile__ unsigned int *lock, unsigned int context)
220 220
221/** 221/**
222 * This takes a lock forcibly and hands it to context. Should ONLY be used 222 * This takes a lock forcibly and hands it to context. Should ONLY be used
223 * inside *_unlock to give lock to kernel before calling *_dma_schedule. 223 * inside *_unlock to give lock to kernel before calling *_dma_schedule.
224 * 224 *
225 * \param dev DRM device. 225 * \param dev DRM device.
226 * \param lock lock pointer. 226 * \param lock lock pointer.
227 * \param context locking context. 227 * \param context locking context.
@@ -230,7 +230,7 @@ int drm_lock_take(__volatile__ unsigned int *lock, unsigned int context)
230 * Resets the lock file pointer. 230 * Resets the lock file pointer.
231 * Marks the lock as held by the given context, via the \p cmpxchg instruction. 231 * Marks the lock as held by the given context, via the \p cmpxchg instruction.
232 */ 232 */
233static int drm_lock_transfer(drm_device_t *dev, 233static int drm_lock_transfer(drm_device_t * dev,
234 __volatile__ unsigned int *lock, 234 __volatile__ unsigned int *lock,
235 unsigned int context) 235 unsigned int context)
236{ 236{
@@ -238,8 +238,8 @@ static int drm_lock_transfer(drm_device_t *dev,
238 238
239 dev->lock.filp = NULL; 239 dev->lock.filp = NULL;
240 do { 240 do {
241 old = *lock; 241 old = *lock;
242 new = context | _DRM_LOCK_HELD; 242 new = context | _DRM_LOCK_HELD;
243 prev = cmpxchg(lock, old, new); 243 prev = cmpxchg(lock, old, new);
244 } while (prev != old); 244 } while (prev != old);
245 return 1; 245 return 1;
@@ -247,30 +247,29 @@ static int drm_lock_transfer(drm_device_t *dev,
247 247
248/** 248/**
249 * Free lock. 249 * Free lock.
250 * 250 *
251 * \param dev DRM device. 251 * \param dev DRM device.
252 * \param lock lock. 252 * \param lock lock.
253 * \param context context. 253 * \param context context.
254 * 254 *
255 * Resets the lock file pointer. 255 * Resets the lock file pointer.
256 * Marks the lock as not held, via the \p cmpxchg instruction. Wakes any task 256 * Marks the lock as not held, via the \p cmpxchg instruction. Wakes any task
257 * waiting on the lock queue. 257 * waiting on the lock queue.
258 */ 258 */
259int drm_lock_free(drm_device_t *dev, 259int drm_lock_free(drm_device_t * dev,
260 __volatile__ unsigned int *lock, unsigned int context) 260 __volatile__ unsigned int *lock, unsigned int context)
261{ 261{
262 unsigned int old, new, prev; 262 unsigned int old, new, prev;
263 263
264 dev->lock.filp = NULL; 264 dev->lock.filp = NULL;
265 do { 265 do {
266 old = *lock; 266 old = *lock;
267 new = 0; 267 new = 0;
268 prev = cmpxchg(lock, old, new); 268 prev = cmpxchg(lock, old, new);
269 } while (prev != old); 269 } while (prev != old);
270 if (_DRM_LOCK_IS_HELD(old) && _DRM_LOCKING_CONTEXT(old) != context) { 270 if (_DRM_LOCK_IS_HELD(old) && _DRM_LOCKING_CONTEXT(old) != context) {
271 DRM_ERROR("%d freed heavyweight lock held by %d\n", 271 DRM_ERROR("%d freed heavyweight lock held by %d\n",
272 context, 272 context, _DRM_LOCKING_CONTEXT(old));
273 _DRM_LOCKING_CONTEXT(old));
274 return 1; 273 return 1;
275 } 274 }
276 wake_up_interruptible(&dev->lock.lock_queue); 275 wake_up_interruptible(&dev->lock.lock_queue);
@@ -290,19 +289,19 @@ int drm_lock_free(drm_device_t *dev,
290 */ 289 */
291static int drm_notifier(void *priv) 290static int drm_notifier(void *priv)
292{ 291{
293 drm_sigdata_t *s = (drm_sigdata_t *)priv; 292 drm_sigdata_t *s = (drm_sigdata_t *) priv;
294 unsigned int old, new, prev; 293 unsigned int old, new, prev;
295
296 294
297 /* Allow signal delivery if lock isn't held */ 295 /* Allow signal delivery if lock isn't held */
298 if (!s->lock || !_DRM_LOCK_IS_HELD(s->lock->lock) 296 if (!s->lock || !_DRM_LOCK_IS_HELD(s->lock->lock)
299 || _DRM_LOCKING_CONTEXT(s->lock->lock) != s->context) return 1; 297 || _DRM_LOCKING_CONTEXT(s->lock->lock) != s->context)
298 return 1;
300 299
301 /* Otherwise, set flag to force call to 300 /* Otherwise, set flag to force call to
302 drmUnlock */ 301 drmUnlock */
303 do { 302 do {
304 old = s->lock->lock; 303 old = s->lock->lock;
305 new = old | _DRM_LOCK_CONT; 304 new = old | _DRM_LOCK_CONT;
306 prev = cmpxchg(&s->lock->lock, old, new); 305 prev = cmpxchg(&s->lock->lock, old, new);
307 } while (prev != old); 306 } while (prev != old);
308 return 0; 307 return 0;
diff --git a/drivers/char/drm/drm_memory.c b/drivers/char/drm/drm_memory.c
index ff483fb418aa..2c74155aa84f 100644
--- a/drivers/char/drm/drm_memory.c
+++ b/drivers/char/drm/drm_memory.c
@@ -1,12 +1,12 @@
1/** 1/**
2 * \file drm_memory.h 2 * \file drm_memory.c
3 * Memory management wrappers for DRM 3 * Memory management wrappers for DRM
4 * 4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
6 * \author Gareth Hughes <gareth@valinux.com> 6 * \author Gareth Hughes <gareth@valinux.com>
7 */ 7 */
8 8
9/* 9/*
10 * Created: Thu Feb 4 14:00:34 1999 by faith@valinux.com 10 * Created: Thu Feb 4 14:00:34 1999 by faith@valinux.com
11 * 11 *
12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
@@ -48,7 +48,7 @@ void drm_mem_init(void)
48 48
49/** 49/**
50 * Called when "/proc/dri/%dev%/mem" is read. 50 * Called when "/proc/dri/%dev%/mem" is read.
51 * 51 *
52 * \param buf output buffer. 52 * \param buf output buffer.
53 * \param start start of output data. 53 * \param start start of output data.
54 * \param offset requested start offset. 54 * \param offset requested start offset.
@@ -57,10 +57,10 @@ void drm_mem_init(void)
57 * \param data private data. 57 * \param data private data.
58 * \return number of written bytes. 58 * \return number of written bytes.
59 * 59 *
60 * No-op. 60 * No-op.
61 */ 61 */
62int drm_mem_info(char *buf, char **start, off_t offset, 62int drm_mem_info(char *buf, char **start, off_t offset,
63 int len, int *eof, void *data) 63 int len, int *eof, void *data)
64{ 64{
65 return 0; 65 return 0;
66} 66}
@@ -70,7 +70,8 @@ void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area)
70{ 70{
71 void *pt; 71 void *pt;
72 72
73 if (!(pt = kmalloc(size, GFP_KERNEL))) return NULL; 73 if (!(pt = kmalloc(size, GFP_KERNEL)))
74 return NULL;
74 if (oldpt && oldsize) { 75 if (oldpt && oldsize) {
75 memcpy(pt, oldpt, oldsize); 76 memcpy(pt, oldpt, oldsize);
76 kfree(oldpt); 77 kfree(oldpt);
@@ -90,21 +91,20 @@ void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area)
90unsigned long drm_alloc_pages(int order, int area) 91unsigned long drm_alloc_pages(int order, int area)
91{ 92{
92 unsigned long address; 93 unsigned long address;
93 unsigned long bytes = PAGE_SIZE << order; 94 unsigned long bytes = PAGE_SIZE << order;
94 unsigned long addr; 95 unsigned long addr;
95 unsigned int sz; 96 unsigned int sz;
96 97
97 address = __get_free_pages(GFP_KERNEL, order); 98 address = __get_free_pages(GFP_KERNEL, order);
98 if (!address) 99 if (!address)
99 return 0; 100 return 0;
100 101
101 /* Zero */ 102 /* Zero */
102 memset((void *)address, 0, bytes); 103 memset((void *)address, 0, bytes);
103 104
104 /* Reserve */ 105 /* Reserve */
105 for (addr = address, sz = bytes; 106 for (addr = address, sz = bytes;
106 sz > 0; 107 sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) {
107 addr += PAGE_SIZE, sz -= PAGE_SIZE) {
108 SetPageReserved(virt_to_page(addr)); 108 SetPageReserved(virt_to_page(addr));
109 } 109 }
110 110
@@ -113,7 +113,7 @@ unsigned long drm_alloc_pages(int order, int area)
113 113
114/** 114/**
115 * Free pages. 115 * Free pages.
116 * 116 *
117 * \param address address of the pages to free. 117 * \param address address of the pages to free.
118 * \param order size order. 118 * \param order size order.
119 * \param area memory area. (Not used.) 119 * \param area memory area. (Not used.)
@@ -124,49 +124,51 @@ void drm_free_pages(unsigned long address, int order, int area)
124{ 124{
125 unsigned long bytes = PAGE_SIZE << order; 125 unsigned long bytes = PAGE_SIZE << order;
126 unsigned long addr; 126 unsigned long addr;
127 unsigned int sz; 127 unsigned int sz;
128 128
129 if (!address) 129 if (!address)
130 return; 130 return;
131 131
132 /* Unreserve */ 132 /* Unreserve */
133 for (addr = address, sz = bytes; 133 for (addr = address, sz = bytes;
134 sz > 0; 134 sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) {
135 addr += PAGE_SIZE, sz -= PAGE_SIZE) {
136 ClearPageReserved(virt_to_page(addr)); 135 ClearPageReserved(virt_to_page(addr));
137 } 136 }
138 137
139 free_pages(address, order); 138 free_pages(address, order);
140} 139}
141 140
142
143#if __OS_HAS_AGP 141#if __OS_HAS_AGP
144/** Wrapper around agp_allocate_memory() */ 142/** Wrapper around agp_allocate_memory() */
145DRM_AGP_MEM *drm_alloc_agp(drm_device_t *dev, int pages, u32 type) 143DRM_AGP_MEM *drm_alloc_agp(drm_device_t * dev, int pages, u32 type)
146{ 144{
147 return drm_agp_allocate_memory(dev->agp->bridge, pages, type); 145 return drm_agp_allocate_memory(dev->agp->bridge, pages, type);
148} 146}
147
149EXPORT_SYMBOL(drm_alloc_agp); 148EXPORT_SYMBOL(drm_alloc_agp);
150 149
151/** Wrapper around agp_free_memory() */ 150/** Wrapper around agp_free_memory() */
152int drm_free_agp(DRM_AGP_MEM *handle, int pages) 151int drm_free_agp(DRM_AGP_MEM * handle, int pages)
153{ 152{
154 return drm_agp_free_memory(handle) ? 0 : -EINVAL; 153 return drm_agp_free_memory(handle) ? 0 : -EINVAL;
155} 154}
155
156EXPORT_SYMBOL(drm_free_agp); 156EXPORT_SYMBOL(drm_free_agp);
157 157
158/** Wrapper around agp_bind_memory() */ 158/** Wrapper around agp_bind_memory() */
159int drm_bind_agp(DRM_AGP_MEM *handle, unsigned int start) 159int drm_bind_agp(DRM_AGP_MEM * handle, unsigned int start)
160{ 160{
161 return drm_agp_bind_memory(handle, start); 161 return drm_agp_bind_memory(handle, start);
162} 162}
163
163EXPORT_SYMBOL(drm_bind_agp); 164EXPORT_SYMBOL(drm_bind_agp);
164 165
165/** Wrapper around agp_unbind_memory() */ 166/** Wrapper around agp_unbind_memory() */
166int drm_unbind_agp(DRM_AGP_MEM *handle) 167int drm_unbind_agp(DRM_AGP_MEM * handle)
167{ 168{
168 return drm_agp_unbind_memory(handle); 169 return drm_agp_unbind_memory(handle);
169} 170}
171
170EXPORT_SYMBOL(drm_unbind_agp); 172EXPORT_SYMBOL(drm_unbind_agp);
171#endif /* agp */ 173#endif /* agp */
172#endif /* debug_memory */ 174#endif /* debug_memory */
diff --git a/drivers/char/drm/drm_memory.h b/drivers/char/drm/drm_memory.h
index 422b94268709..3732a61c3762 100644
--- a/drivers/char/drm/drm_memory.h
+++ b/drivers/char/drm/drm_memory.h
@@ -1,12 +1,12 @@
1/** 1/**
2 * \file drm_memory.h 2 * \file drm_memory.h
3 * Memory management wrappers for DRM 3 * Memory management wrappers for DRM
4 * 4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
6 * \author Gareth Hughes <gareth@valinux.com> 6 * \author Gareth Hughes <gareth@valinux.com>
7 */ 7 */
8 8
9/* 9/*
10 * Created: Thu Feb 4 14:00:34 1999 by faith@valinux.com 10 * Created: Thu Feb 4 14:00:34 1999 by faith@valinux.com
11 * 11 *
12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
@@ -40,7 +40,7 @@
40 40
41/** 41/**
42 * Cut down version of drm_memory_debug.h, which used to be called 42 * Cut down version of drm_memory_debug.h, which used to be called
43 * drm_memory.h. 43 * drm_memory.h.
44 */ 44 */
45 45
46#if __OS_HAS_AGP 46#if __OS_HAS_AGP
@@ -60,8 +60,8 @@
60/* 60/*
61 * Find the drm_map that covers the range [offset, offset+size). 61 * Find the drm_map that covers the range [offset, offset+size).
62 */ 62 */
63static inline drm_map_t * 63static inline drm_map_t *drm_lookup_map(unsigned long offset,
64drm_lookup_map (unsigned long offset, unsigned long size, drm_device_t *dev) 64 unsigned long size, drm_device_t * dev)
65{ 65{
66 struct list_head *list; 66 struct list_head *list;
67 drm_map_list_t *r_list; 67 drm_map_list_t *r_list;
@@ -72,16 +72,18 @@ drm_lookup_map (unsigned long offset, unsigned long size, drm_device_t *dev)
72 map = r_list->map; 72 map = r_list->map;
73 if (!map) 73 if (!map)
74 continue; 74 continue;
75 if (map->offset <= offset && (offset + size) <= (map->offset + map->size)) 75 if (map->offset <= offset
76 && (offset + size) <= (map->offset + map->size))
76 return map; 77 return map;
77 } 78 }
78 return NULL; 79 return NULL;
79} 80}
80 81
81static inline void * 82static inline void *agp_remap(unsigned long offset, unsigned long size,
82agp_remap (unsigned long offset, unsigned long size, drm_device_t *dev) 83 drm_device_t * dev)
83{ 84{
84 unsigned long *phys_addr_map, i, num_pages = PAGE_ALIGN(size) / PAGE_SIZE; 85 unsigned long *phys_addr_map, i, num_pages =
86 PAGE_ALIGN(size) / PAGE_SIZE;
85 struct drm_agp_mem *agpmem; 87 struct drm_agp_mem *agpmem;
86 struct page **page_map; 88 struct page **page_map;
87 void *addr; 89 void *addr;
@@ -94,7 +96,8 @@ agp_remap (unsigned long offset, unsigned long size, drm_device_t *dev)
94 96
95 for (agpmem = dev->agp->memory; agpmem; agpmem = agpmem->next) 97 for (agpmem = dev->agp->memory; agpmem; agpmem = agpmem->next)
96 if (agpmem->bound <= offset 98 if (agpmem->bound <= offset
97 && (agpmem->bound + (agpmem->pages << PAGE_SHIFT)) >= (offset + size)) 99 && (agpmem->bound + (agpmem->pages << PAGE_SHIFT)) >=
100 (offset + size))
98 break; 101 break;
99 if (!agpmem) 102 if (!agpmem)
100 return NULL; 103 return NULL;
@@ -109,7 +112,8 @@ agp_remap (unsigned long offset, unsigned long size, drm_device_t *dev)
109 if (!page_map) 112 if (!page_map)
110 return NULL; 113 return NULL;
111 114
112 phys_addr_map = agpmem->memory->memory + (offset - agpmem->bound) / PAGE_SIZE; 115 phys_addr_map =
116 agpmem->memory->memory + (offset - agpmem->bound) / PAGE_SIZE;
113 for (i = 0; i < num_pages; ++i) 117 for (i = 0; i < num_pages; ++i)
114 page_map[i] = pfn_to_page(phys_addr_map[i] >> PAGE_SHIFT); 118 page_map[i] = pfn_to_page(phys_addr_map[i] >> PAGE_SHIFT);
115 addr = vmap(page_map, num_pages, VM_IOREMAP, PAGE_AGP); 119 addr = vmap(page_map, num_pages, VM_IOREMAP, PAGE_AGP);
@@ -118,36 +122,38 @@ agp_remap (unsigned long offset, unsigned long size, drm_device_t *dev)
118 return addr; 122 return addr;
119} 123}
120 124
121static inline unsigned long 125static inline unsigned long drm_follow_page(void *vaddr)
122drm_follow_page (void *vaddr)
123{ 126{
124 pgd_t *pgd = pgd_offset_k((unsigned long) vaddr); 127 pgd_t *pgd = pgd_offset_k((unsigned long)vaddr);
125 pud_t *pud = pud_offset(pgd, (unsigned long) vaddr); 128 pud_t *pud = pud_offset(pgd, (unsigned long)vaddr);
126 pmd_t *pmd = pmd_offset(pud, (unsigned long) vaddr); 129 pmd_t *pmd = pmd_offset(pud, (unsigned long)vaddr);
127 pte_t *ptep = pte_offset_kernel(pmd, (unsigned long) vaddr); 130 pte_t *ptep = pte_offset_kernel(pmd, (unsigned long)vaddr);
128 return pte_pfn(*ptep) << PAGE_SHIFT; 131 return pte_pfn(*ptep) << PAGE_SHIFT;
129} 132}
130 133
131#else /* __OS_HAS_AGP */ 134#else /* __OS_HAS_AGP */
132 135
133static inline drm_map_t *drm_lookup_map(unsigned long offset, unsigned long size, drm_device_t *dev) 136static inline drm_map_t *drm_lookup_map(unsigned long offset,
137 unsigned long size, drm_device_t * dev)
134{ 138{
135 return NULL; 139 return NULL;
136} 140}
137 141
138static inline void *agp_remap(unsigned long offset, unsigned long size, drm_device_t *dev) 142static inline void *agp_remap(unsigned long offset, unsigned long size,
143 drm_device_t * dev)
139{ 144{
140 return NULL; 145 return NULL;
141} 146}
142 147
143static inline unsigned long drm_follow_page (void *vaddr) 148static inline unsigned long drm_follow_page(void *vaddr)
144{ 149{
145 return 0; 150 return 0;
146} 151}
147 152
148#endif 153#endif
149 154
150static inline void *drm_ioremap(unsigned long offset, unsigned long size, drm_device_t *dev) 155static inline void *drm_ioremap(unsigned long offset, unsigned long size,
156 drm_device_t * dev)
151{ 157{
152 if (drm_core_has_AGP(dev) && dev->agp && dev->agp->cant_use_aperture) { 158 if (drm_core_has_AGP(dev) && dev->agp && dev->agp->cant_use_aperture) {
153 drm_map_t *map = drm_lookup_map(offset, size, dev); 159 drm_map_t *map = drm_lookup_map(offset, size, dev);
@@ -158,8 +164,8 @@ static inline void *drm_ioremap(unsigned long offset, unsigned long size, drm_de
158 return ioremap(offset, size); 164 return ioremap(offset, size);
159} 165}
160 166
161static inline void *drm_ioremap_nocache(unsigned long offset, unsigned long size, 167static inline void *drm_ioremap_nocache(unsigned long offset,
162 drm_device_t *dev) 168 unsigned long size, drm_device_t * dev)
163{ 169{
164 if (drm_core_has_AGP(dev) && dev->agp && dev->agp->cant_use_aperture) { 170 if (drm_core_has_AGP(dev) && dev->agp && dev->agp->cant_use_aperture) {
165 drm_map_t *map = drm_lookup_map(offset, size, dev); 171 drm_map_t *map = drm_lookup_map(offset, size, dev);
@@ -170,7 +176,8 @@ static inline void *drm_ioremap_nocache(unsigned long offset, unsigned long size
170 return ioremap_nocache(offset, size); 176 return ioremap_nocache(offset, size);
171} 177}
172 178
173static inline void drm_ioremapfree(void *pt, unsigned long size, drm_device_t *dev) 179static inline void drm_ioremapfree(void *pt, unsigned long size,
180 drm_device_t * dev)
174{ 181{
175 /* 182 /*
176 * This is a bit ugly. It would be much cleaner if the DRM API would use separate 183 * This is a bit ugly. It would be much cleaner if the DRM API would use separate
@@ -178,12 +185,12 @@ static inline void drm_ioremapfree(void *pt, unsigned long size, drm_device_t *d
178 * a future revision of the interface... 185 * a future revision of the interface...
179 */ 186 */
180 if (drm_core_has_AGP(dev) && dev->agp && dev->agp->cant_use_aperture 187 if (drm_core_has_AGP(dev) && dev->agp && dev->agp->cant_use_aperture
181 && ((unsigned long) pt >= VMALLOC_START && (unsigned long) pt < VMALLOC_END)) 188 && ((unsigned long)pt >= VMALLOC_START
182 { 189 && (unsigned long)pt < VMALLOC_END)) {
183 unsigned long offset; 190 unsigned long offset;
184 drm_map_t *map; 191 drm_map_t *map;
185 192
186 offset = drm_follow_page(pt) | ((unsigned long) pt & ~PAGE_MASK); 193 offset = drm_follow_page(pt) | ((unsigned long)pt & ~PAGE_MASK);
187 map = drm_lookup_map(offset, size, dev); 194 map = drm_lookup_map(offset, size, dev);
188 if (map && map->type == _DRM_AGP) { 195 if (map && map->type == _DRM_AGP) {
189 vunmap(pt); 196 vunmap(pt);
@@ -193,5 +200,3 @@ static inline void drm_ioremapfree(void *pt, unsigned long size, drm_device_t *d
193 200
194 iounmap(pt); 201 iounmap(pt);
195} 202}
196
197
diff --git a/drivers/char/drm/drm_memory_debug.h b/drivers/char/drm/drm_memory_debug.h
index 2c82e69a7fd2..4542353195bd 100644
--- a/drivers/char/drm/drm_memory_debug.h
+++ b/drivers/char/drm/drm_memory_debug.h
@@ -1,5 +1,5 @@
1/** 1/**
2 * \file drm_memory.h 2 * \file drm_memory.h
3 * Memory management wrappers for DRM. 3 * Memory management wrappers for DRM.
4 * 4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
@@ -35,75 +35,75 @@
35#include "drmP.h" 35#include "drmP.h"
36 36
37typedef struct drm_mem_stats { 37typedef struct drm_mem_stats {
38 const char *name; 38 const char *name;
39 int succeed_count; 39 int succeed_count;
40 int free_count; 40 int free_count;
41 int fail_count; 41 int fail_count;
42 unsigned long bytes_allocated; 42 unsigned long bytes_allocated;
43 unsigned long bytes_freed; 43 unsigned long bytes_freed;
44} drm_mem_stats_t; 44} drm_mem_stats_t;
45 45
46static DEFINE_SPINLOCK(DRM(mem_lock)); 46static DEFINE_SPINLOCK(DRM(mem_lock));
47static unsigned long DRM(ram_available) = 0; /* In pages */ 47static unsigned long DRM(ram_available) = 0; /* In pages */
48static unsigned long DRM(ram_used) = 0; 48static unsigned long DRM(ram_used) = 0;
49static drm_mem_stats_t DRM(mem_stats)[] = { 49static drm_mem_stats_t DRM(mem_stats)[] =
50 [DRM_MEM_DMA] = { "dmabufs" }, 50{
51 [DRM_MEM_SAREA] = { "sareas" }, 51 [DRM_MEM_DMA] = {
52 [DRM_MEM_DRIVER] = { "driver" }, 52 "dmabufs"},[DRM_MEM_SAREA] = {
53 [DRM_MEM_MAGIC] = { "magic" }, 53 "sareas"},[DRM_MEM_DRIVER] = {
54 [DRM_MEM_IOCTLS] = { "ioctltab" }, 54 "driver"},[DRM_MEM_MAGIC] = {
55 [DRM_MEM_MAPS] = { "maplist" }, 55 "magic"},[DRM_MEM_IOCTLS] = {
56 [DRM_MEM_VMAS] = { "vmalist" }, 56 "ioctltab"},[DRM_MEM_MAPS] = {
57 [DRM_MEM_BUFS] = { "buflist" }, 57 "maplist"},[DRM_MEM_VMAS] = {
58 [DRM_MEM_SEGS] = { "seglist" }, 58 "vmalist"},[DRM_MEM_BUFS] = {
59 [DRM_MEM_PAGES] = { "pagelist" }, 59 "buflist"},[DRM_MEM_SEGS] = {
60 [DRM_MEM_FILES] = { "files" }, 60 "seglist"},[DRM_MEM_PAGES] = {
61 [DRM_MEM_QUEUES] = { "queues" }, 61 "pagelist"},[DRM_MEM_FILES] = {
62 [DRM_MEM_CMDS] = { "commands" }, 62 "files"},[DRM_MEM_QUEUES] = {
63 [DRM_MEM_MAPPINGS] = { "mappings" }, 63 "queues"},[DRM_MEM_CMDS] = {
64 [DRM_MEM_BUFLISTS] = { "buflists" }, 64 "commands"},[DRM_MEM_MAPPINGS] = {
65 [DRM_MEM_AGPLISTS] = { "agplist" }, 65 "mappings"},[DRM_MEM_BUFLISTS] = {
66 [DRM_MEM_SGLISTS] = { "sglist" }, 66 "buflists"},[DRM_MEM_AGPLISTS] = {
67 [DRM_MEM_TOTALAGP] = { "totalagp" }, 67 "agplist"},[DRM_MEM_SGLISTS] = {
68 [DRM_MEM_BOUNDAGP] = { "boundagp" }, 68 "sglist"},[DRM_MEM_TOTALAGP] = {
69 [DRM_MEM_CTXBITMAP] = { "ctxbitmap"}, 69 "totalagp"},[DRM_MEM_BOUNDAGP] = {
70 [DRM_MEM_CTXLIST] = { "ctxlist" }, 70 "boundagp"},[DRM_MEM_CTXBITMAP] = {
71 [DRM_MEM_STUB] = { "stub" }, 71 "ctxbitmap"},[DRM_MEM_CTXLIST] = {
72 { NULL, 0, } /* Last entry must be null */ 72 "ctxlist"},[DRM_MEM_STUB] = {
73 "stub"}, {
74 NULL, 0,} /* Last entry must be null */
73}; 75};
74 76
75void DRM(mem_init)(void) 77void DRM(mem_init) (void) {
76{
77 drm_mem_stats_t *mem; 78 drm_mem_stats_t *mem;
78 struct sysinfo si; 79 struct sysinfo si;
79 80
80 for (mem = DRM(mem_stats); mem->name; ++mem) { 81 for (mem = DRM(mem_stats); mem->name; ++mem) {
81 mem->succeed_count = 0; 82 mem->succeed_count = 0;
82 mem->free_count = 0; 83 mem->free_count = 0;
83 mem->fail_count = 0; 84 mem->fail_count = 0;
84 mem->bytes_allocated = 0; 85 mem->bytes_allocated = 0;
85 mem->bytes_freed = 0; 86 mem->bytes_freed = 0;
86 } 87 }
87 88
88 si_meminfo(&si); 89 si_meminfo(&si);
89 DRM(ram_available) = si.totalram; 90 DRM(ram_available) = si.totalram;
90 DRM(ram_used) = 0; 91 DRM(ram_used) = 0;
91} 92}
92 93
93/* drm_mem_info is called whenever a process reads /dev/drm/mem. */ 94/* drm_mem_info is called whenever a process reads /dev/drm/mem. */
94 95
95static int DRM(_mem_info)(char *buf, char **start, off_t offset, 96static int DRM(_mem_info) (char *buf, char **start, off_t offset,
96 int request, int *eof, void *data) 97 int request, int *eof, void *data) {
97{
98 drm_mem_stats_t *pt; 98 drm_mem_stats_t *pt;
99 int len = 0; 99 int len = 0;
100 100
101 if (offset > DRM_PROC_LIMIT) { 101 if (offset > DRM_PROC_LIMIT) {
102 *eof = 1; 102 *eof = 1;
103 return 0; 103 return 0;
104 } 104 }
105 105
106 *eof = 0; 106 *eof = 0;
107 *start = &buf[offset]; 107 *start = &buf[offset];
108 108
109 DRM_PROC_PRINT(" total counts " 109 DRM_PROC_PRINT(" total counts "
@@ -129,24 +129,23 @@ static int DRM(_mem_info)(char *buf, char **start, off_t offset,
129 - (long)pt->bytes_freed); 129 - (long)pt->bytes_freed);
130 } 130 }
131 131
132 if (len > request + offset) return request; 132 if (len > request + offset)
133 return request;
133 *eof = 1; 134 *eof = 1;
134 return len - offset; 135 return len - offset;
135} 136}
136 137
137int DRM(mem_info)(char *buf, char **start, off_t offset, 138int DRM(mem_info) (char *buf, char **start, off_t offset,
138 int len, int *eof, void *data) 139 int len, int *eof, void *data) {
139{
140 int ret; 140 int ret;
141 141
142 spin_lock(&DRM(mem_lock)); 142 spin_lock(&DRM(mem_lock));
143 ret = DRM(_mem_info)(buf, start, offset, len, eof, data); 143 ret = DRM(_mem_info) (buf, start, offset, len, eof, data);
144 spin_unlock(&DRM(mem_lock)); 144 spin_unlock(&DRM(mem_lock));
145 return ret; 145 return ret;
146} 146}
147 147
148void *DRM(alloc)(size_t size, int area) 148void *DRM(alloc) (size_t size, int area) {
149{
150 void *pt; 149 void *pt;
151 150
152 if (!size) { 151 if (!size) {
@@ -167,40 +166,40 @@ void *DRM(alloc)(size_t size, int area)
167 return pt; 166 return pt;
168} 167}
169 168
170void *DRM(calloc)(size_t nmemb, size_t size, int area) 169void *DRM(calloc) (size_t nmemb, size_t size, int area) {
171{
172 void *addr; 170 void *addr;
173 171
174 addr = DRM(alloc)(nmemb * size, area); 172 addr = DRM(alloc) (nmemb * size, area);
175 if (addr != NULL) 173 if (addr != NULL)
176 memset((void *)addr, 0, size * nmemb); 174 memset((void *)addr, 0, size * nmemb);
177 175
178 return addr; 176 return addr;
179} 177}
180 178
181void *DRM(realloc)(void *oldpt, size_t oldsize, size_t size, int area) 179void *DRM(realloc) (void *oldpt, size_t oldsize, size_t size, int area) {
182{
183 void *pt; 180 void *pt;
184 181
185 if (!(pt = DRM(alloc)(size, area))) return NULL; 182 if (!(pt = DRM(alloc) (size, area)))
183 return NULL;
186 if (oldpt && oldsize) { 184 if (oldpt && oldsize) {
187 memcpy(pt, oldpt, oldsize); 185 memcpy(pt, oldpt, oldsize);
188 DRM(free)(oldpt, oldsize, area); 186 DRM(free) (oldpt, oldsize, area);
189 } 187 }
190 return pt; 188 return pt;
191} 189}
192 190
193void DRM(free)(void *pt, size_t size, int area) 191void DRM(free) (void *pt, size_t size, int area) {
194{
195 int alloc_count; 192 int alloc_count;
196 int free_count; 193 int free_count;
197 194
198 if (!pt) DRM_MEM_ERROR(area, "Attempt to free NULL pointer\n"); 195 if (!pt)
199 else kfree(pt); 196 DRM_MEM_ERROR(area, "Attempt to free NULL pointer\n");
197 else
198 kfree(pt);
200 spin_lock(&DRM(mem_lock)); 199 spin_lock(&DRM(mem_lock));
201 DRM(mem_stats)[area].bytes_freed += size; 200 DRM(mem_stats)[area].bytes_freed += size;
202 free_count = ++DRM(mem_stats)[area].free_count; 201 free_count = ++DRM(mem_stats)[area].free_count;
203 alloc_count = DRM(mem_stats)[area].succeed_count; 202 alloc_count = DRM(mem_stats)[area].succeed_count;
204 spin_unlock(&DRM(mem_lock)); 203 spin_unlock(&DRM(mem_lock));
205 if (free_count > alloc_count) { 204 if (free_count > alloc_count) {
206 DRM_MEM_ERROR(area, "Excess frees: %d frees, %d allocs\n", 205 DRM_MEM_ERROR(area, "Excess frees: %d frees, %d allocs\n",
@@ -208,12 +207,11 @@ void DRM(free)(void *pt, size_t size, int area)
208 } 207 }
209} 208}
210 209
211unsigned long DRM(alloc_pages)(int order, int area) 210unsigned long DRM(alloc_pages) (int order, int area) {
212{
213 unsigned long address; 211 unsigned long address;
214 unsigned long bytes = PAGE_SIZE << order; 212 unsigned long bytes = PAGE_SIZE << order;
215 unsigned long addr; 213 unsigned long addr;
216 unsigned int sz; 214 unsigned int sz;
217 215
218 spin_lock(&DRM(mem_lock)); 216 spin_lock(&DRM(mem_lock));
219 if ((DRM(ram_used) >> PAGE_SHIFT) 217 if ((DRM(ram_used) >> PAGE_SHIFT)
@@ -233,48 +231,44 @@ unsigned long DRM(alloc_pages)(int order, int area)
233 spin_lock(&DRM(mem_lock)); 231 spin_lock(&DRM(mem_lock));
234 ++DRM(mem_stats)[area].succeed_count; 232 ++DRM(mem_stats)[area].succeed_count;
235 DRM(mem_stats)[area].bytes_allocated += bytes; 233 DRM(mem_stats)[area].bytes_allocated += bytes;
236 DRM(ram_used) += bytes; 234 DRM(ram_used) += bytes;
237 spin_unlock(&DRM(mem_lock)); 235 spin_unlock(&DRM(mem_lock));
238 236
239 237 /* Zero outside the lock */
240 /* Zero outside the lock */
241 memset((void *)address, 0, bytes); 238 memset((void *)address, 0, bytes);
242 239
243 /* Reserve */ 240 /* Reserve */
244 for (addr = address, sz = bytes; 241 for (addr = address, sz = bytes;
245 sz > 0; 242 sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) {
246 addr += PAGE_SIZE, sz -= PAGE_SIZE) {
247 SetPageReserved(virt_to_page(addr)); 243 SetPageReserved(virt_to_page(addr));
248 } 244 }
249 245
250 return address; 246 return address;
251} 247}
252 248
253void DRM(free_pages)(unsigned long address, int order, int area) 249void DRM(free_pages) (unsigned long address, int order, int area) {
254{
255 unsigned long bytes = PAGE_SIZE << order; 250 unsigned long bytes = PAGE_SIZE << order;
256 int alloc_count; 251 int alloc_count;
257 int free_count; 252 int free_count;
258 unsigned long addr; 253 unsigned long addr;
259 unsigned int sz; 254 unsigned int sz;
260 255
261 if (!address) { 256 if (!address) {
262 DRM_MEM_ERROR(area, "Attempt to free address 0\n"); 257 DRM_MEM_ERROR(area, "Attempt to free address 0\n");
263 } else { 258 } else {
264 /* Unreserve */ 259 /* Unreserve */
265 for (addr = address, sz = bytes; 260 for (addr = address, sz = bytes;
266 sz > 0; 261 sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) {
267 addr += PAGE_SIZE, sz -= PAGE_SIZE) {
268 ClearPageReserved(virt_to_page(addr)); 262 ClearPageReserved(virt_to_page(addr));
269 } 263 }
270 free_pages(address, order); 264 free_pages(address, order);
271 } 265 }
272 266
273 spin_lock(&DRM(mem_lock)); 267 spin_lock(&DRM(mem_lock));
274 free_count = ++DRM(mem_stats)[area].free_count; 268 free_count = ++DRM(mem_stats)[area].free_count;
275 alloc_count = DRM(mem_stats)[area].succeed_count; 269 alloc_count = DRM(mem_stats)[area].succeed_count;
276 DRM(mem_stats)[area].bytes_freed += bytes; 270 DRM(mem_stats)[area].bytes_freed += bytes;
277 DRM(ram_used) -= bytes; 271 DRM(ram_used) -= bytes;
278 spin_unlock(&DRM(mem_lock)); 272 spin_unlock(&DRM(mem_lock));
279 if (free_count > alloc_count) { 273 if (free_count > alloc_count) {
280 DRM_MEM_ERROR(area, 274 DRM_MEM_ERROR(area,
@@ -283,8 +277,8 @@ void DRM(free_pages)(unsigned long address, int order, int area)
283 } 277 }
284} 278}
285 279
286void *DRM(ioremap)(unsigned long offset, unsigned long size, drm_device_t *dev) 280void *DRM(ioremap) (unsigned long offset, unsigned long size,
287{ 281 drm_device_t * dev) {
288 void *pt; 282 void *pt;
289 283
290 if (!size) { 284 if (!size) {
@@ -306,8 +300,8 @@ void *DRM(ioremap)(unsigned long offset, unsigned long size, drm_device_t *dev)
306 return pt; 300 return pt;
307} 301}
308 302
309void *DRM(ioremap_nocache)(unsigned long offset, unsigned long size, drm_device_t *dev) 303void *DRM(ioremap_nocache) (unsigned long offset, unsigned long size,
310{ 304 drm_device_t * dev) {
311 void *pt; 305 void *pt;
312 306
313 if (!size) { 307 if (!size) {
@@ -329,8 +323,7 @@ void *DRM(ioremap_nocache)(unsigned long offset, unsigned long size, drm_device_
329 return pt; 323 return pt;
330} 324}
331 325
332void DRM(ioremapfree)(void *pt, unsigned long size, drm_device_t *dev) 326void DRM(ioremapfree) (void *pt, unsigned long size, drm_device_t * dev) {
333{
334 int alloc_count; 327 int alloc_count;
335 int free_count; 328 int free_count;
336 329
@@ -342,8 +335,8 @@ void DRM(ioremapfree)(void *pt, unsigned long size, drm_device_t *dev)
342 335
343 spin_lock(&DRM(mem_lock)); 336 spin_lock(&DRM(mem_lock));
344 DRM(mem_stats)[DRM_MEM_MAPPINGS].bytes_freed += size; 337 DRM(mem_stats)[DRM_MEM_MAPPINGS].bytes_freed += size;
345 free_count = ++DRM(mem_stats)[DRM_MEM_MAPPINGS].free_count; 338 free_count = ++DRM(mem_stats)[DRM_MEM_MAPPINGS].free_count;
346 alloc_count = DRM(mem_stats)[DRM_MEM_MAPPINGS].succeed_count; 339 alloc_count = DRM(mem_stats)[DRM_MEM_MAPPINGS].succeed_count;
347 spin_unlock(&DRM(mem_lock)); 340 spin_unlock(&DRM(mem_lock));
348 if (free_count > alloc_count) { 341 if (free_count > alloc_count) {
349 DRM_MEM_ERROR(DRM_MEM_MAPPINGS, 342 DRM_MEM_ERROR(DRM_MEM_MAPPINGS,
@@ -354,8 +347,7 @@ void DRM(ioremapfree)(void *pt, unsigned long size, drm_device_t *dev)
354 347
355#if __OS_HAS_AGP 348#if __OS_HAS_AGP
356 349
357DRM_AGP_MEM *DRM(alloc_agp)(int pages, u32 type) 350DRM_AGP_MEM *DRM(alloc_agp) (int pages, u32 type) {
358{
359 DRM_AGP_MEM *handle; 351 DRM_AGP_MEM *handle;
360 352
361 if (!pages) { 353 if (!pages) {
@@ -363,11 +355,11 @@ DRM_AGP_MEM *DRM(alloc_agp)(int pages, u32 type)
363 return NULL; 355 return NULL;
364 } 356 }
365 357
366 if ((handle = DRM(agp_allocate_memory)(pages, type))) { 358 if ((handle = DRM(agp_allocate_memory) (pages, type))) {
367 spin_lock(&DRM(mem_lock)); 359 spin_lock(&DRM(mem_lock));
368 ++DRM(mem_stats)[DRM_MEM_TOTALAGP].succeed_count; 360 ++DRM(mem_stats)[DRM_MEM_TOTALAGP].succeed_count;
369 DRM(mem_stats)[DRM_MEM_TOTALAGP].bytes_allocated 361 DRM(mem_stats)[DRM_MEM_TOTALAGP].bytes_allocated
370 += pages << PAGE_SHIFT; 362 += pages << PAGE_SHIFT;
371 spin_unlock(&DRM(mem_lock)); 363 spin_unlock(&DRM(mem_lock));
372 return handle; 364 return handle;
373 } 365 }
@@ -377,11 +369,10 @@ DRM_AGP_MEM *DRM(alloc_agp)(int pages, u32 type)
377 return NULL; 369 return NULL;
378} 370}
379 371
380int DRM(free_agp)(DRM_AGP_MEM *handle, int pages) 372int DRM(free_agp) (DRM_AGP_MEM * handle, int pages) {
381{ 373 int alloc_count;
382 int alloc_count; 374 int free_count;
383 int free_count; 375 int retval = -EINVAL;
384 int retval = -EINVAL;
385 376
386 if (!handle) { 377 if (!handle) {
387 DRM_MEM_ERROR(DRM_MEM_TOTALAGP, 378 DRM_MEM_ERROR(DRM_MEM_TOTALAGP,
@@ -389,12 +380,12 @@ int DRM(free_agp)(DRM_AGP_MEM *handle, int pages)
389 return retval; 380 return retval;
390 } 381 }
391 382
392 if (DRM(agp_free_memory)(handle)) { 383 if (DRM(agp_free_memory) (handle)) {
393 spin_lock(&DRM(mem_lock)); 384 spin_lock(&DRM(mem_lock));
394 free_count = ++DRM(mem_stats)[DRM_MEM_TOTALAGP].free_count; 385 free_count = ++DRM(mem_stats)[DRM_MEM_TOTALAGP].free_count;
395 alloc_count = DRM(mem_stats)[DRM_MEM_TOTALAGP].succeed_count; 386 alloc_count = DRM(mem_stats)[DRM_MEM_TOTALAGP].succeed_count;
396 DRM(mem_stats)[DRM_MEM_TOTALAGP].bytes_freed 387 DRM(mem_stats)[DRM_MEM_TOTALAGP].bytes_freed
397 += pages << PAGE_SHIFT; 388 += pages << PAGE_SHIFT;
398 spin_unlock(&DRM(mem_lock)); 389 spin_unlock(&DRM(mem_lock));
399 if (free_count > alloc_count) { 390 if (free_count > alloc_count) {
400 DRM_MEM_ERROR(DRM_MEM_TOTALAGP, 391 DRM_MEM_ERROR(DRM_MEM_TOTALAGP,
@@ -406,8 +397,7 @@ int DRM(free_agp)(DRM_AGP_MEM *handle, int pages)
406 return retval; 397 return retval;
407} 398}
408 399
409int DRM(bind_agp)(DRM_AGP_MEM *handle, unsigned int start) 400int DRM(bind_agp) (DRM_AGP_MEM * handle, unsigned int start) {
410{
411 int retcode = -EINVAL; 401 int retcode = -EINVAL;
412 402
413 if (!handle) { 403 if (!handle) {
@@ -416,11 +406,11 @@ int DRM(bind_agp)(DRM_AGP_MEM *handle, unsigned int start)
416 return retcode; 406 return retcode;
417 } 407 }
418 408
419 if (!(retcode = DRM(agp_bind_memory)(handle, start))) { 409 if (!(retcode = DRM(agp_bind_memory) (handle, start))) {
420 spin_lock(&DRM(mem_lock)); 410 spin_lock(&DRM(mem_lock));
421 ++DRM(mem_stats)[DRM_MEM_BOUNDAGP].succeed_count; 411 ++DRM(mem_stats)[DRM_MEM_BOUNDAGP].succeed_count;
422 DRM(mem_stats)[DRM_MEM_BOUNDAGP].bytes_allocated 412 DRM(mem_stats)[DRM_MEM_BOUNDAGP].bytes_allocated
423 += handle->page_count << PAGE_SHIFT; 413 += handle->page_count << PAGE_SHIFT;
424 spin_unlock(&DRM(mem_lock)); 414 spin_unlock(&DRM(mem_lock));
425 return retcode; 415 return retcode;
426 } 416 }
@@ -430,8 +420,7 @@ int DRM(bind_agp)(DRM_AGP_MEM *handle, unsigned int start)
430 return retcode; 420 return retcode;
431} 421}
432 422
433int DRM(unbind_agp)(DRM_AGP_MEM *handle) 423int DRM(unbind_agp) (DRM_AGP_MEM * handle) {
434{
435 int alloc_count; 424 int alloc_count;
436 int free_count; 425 int free_count;
437 int retcode = -EINVAL; 426 int retcode = -EINVAL;
@@ -442,12 +431,13 @@ int DRM(unbind_agp)(DRM_AGP_MEM *handle)
442 return retcode; 431 return retcode;
443 } 432 }
444 433
445 if ((retcode = DRM(agp_unbind_memory)(handle))) return retcode; 434 if ((retcode = DRM(agp_unbind_memory) (handle)))
435 return retcode;
446 spin_lock(&DRM(mem_lock)); 436 spin_lock(&DRM(mem_lock));
447 free_count = ++DRM(mem_stats)[DRM_MEM_BOUNDAGP].free_count; 437 free_count = ++DRM(mem_stats)[DRM_MEM_BOUNDAGP].free_count;
448 alloc_count = DRM(mem_stats)[DRM_MEM_BOUNDAGP].succeed_count; 438 alloc_count = DRM(mem_stats)[DRM_MEM_BOUNDAGP].succeed_count;
449 DRM(mem_stats)[DRM_MEM_BOUNDAGP].bytes_freed 439 DRM(mem_stats)[DRM_MEM_BOUNDAGP].bytes_freed
450 += handle->page_count << PAGE_SHIFT; 440 += handle->page_count << PAGE_SHIFT;
451 spin_unlock(&DRM(mem_lock)); 441 spin_unlock(&DRM(mem_lock));
452 if (free_count > alloc_count) { 442 if (free_count > alloc_count) {
453 DRM_MEM_ERROR(DRM_MEM_BOUNDAGP, 443 DRM_MEM_ERROR(DRM_MEM_BOUNDAGP,
diff --git a/drivers/char/drm/drm_os_linux.h b/drivers/char/drm/drm_os_linux.h
index b14cd370dea5..d51aeb4966f4 100644
--- a/drivers/char/drm/drm_os_linux.h
+++ b/drivers/char/drm/drm_os_linux.h
@@ -3,7 +3,6 @@
3 * OS abstraction macros. 3 * OS abstraction macros.
4 */ 4 */
5 5
6
7#include <linux/interrupt.h> /* For task queue support */ 6#include <linux/interrupt.h> /* For task queue support */
8#include <linux/delay.h> 7#include <linux/delay.h>
9 8
@@ -47,25 +46,25 @@
47#else 46#else
48/* define some dummy types for non AGP supporting kernels */ 47/* define some dummy types for non AGP supporting kernels */
49struct no_agp_kern { 48struct no_agp_kern {
50 unsigned long aper_base; 49 unsigned long aper_base;
51 unsigned long aper_size; 50 unsigned long aper_size;
52}; 51};
53#define DRM_AGP_MEM int 52#define DRM_AGP_MEM int
54#define DRM_AGP_KERN struct no_agp_kern 53#define DRM_AGP_KERN struct no_agp_kern
55#endif 54#endif
56 55
57#if !(__OS_HAS_MTRR) 56#if !(__OS_HAS_MTRR)
58static __inline__ int mtrr_add (unsigned long base, unsigned long size, 57static __inline__ int mtrr_add(unsigned long base, unsigned long size,
59 unsigned int type, char increment) 58 unsigned int type, char increment)
60{ 59{
61 return -ENODEV; 60 return -ENODEV;
62} 61}
63 62
64static __inline__ int mtrr_del (int reg, unsigned long base, 63static __inline__ int mtrr_del(int reg, unsigned long base, unsigned long size)
65 unsigned long size)
66{ 64{
67 return -ENODEV; 65 return -ENODEV;
68} 66}
67
69#define MTRR_TYPE_WRCOMB 1 68#define MTRR_TYPE_WRCOMB 1
70 69
71#endif 70#endif
@@ -99,7 +98,7 @@ static __inline__ int mtrr_del (int reg, unsigned long base,
99 98
100#define DRM_GET_PRIV_WITH_RETURN(_priv, _filp) _priv = _filp->private_data 99#define DRM_GET_PRIV_WITH_RETURN(_priv, _filp) _priv = _filp->private_data
101 100
102/** 101/**
103 * Get the pointer to the SAREA. 102 * Get the pointer to the SAREA.
104 * 103 *
105 * Searches the SAREA on the mapping lists and points drm_device::sarea to it. 104 * Searches the SAREA on the mapping lists and points drm_device::sarea to it.
@@ -143,7 +142,5 @@ do { \
143 remove_wait_queue(&(queue), &entry); \ 142 remove_wait_queue(&(queue), &entry); \
144} while (0) 143} while (0)
145 144
146
147#define DRM_WAKEUP( queue ) wake_up_interruptible( queue ) 145#define DRM_WAKEUP( queue ) wake_up_interruptible( queue )
148#define DRM_INIT_WAITQUEUE( queue ) init_waitqueue_head( queue ) 146#define DRM_INIT_WAITQUEUE( queue ) init_waitqueue_head( queue )
149
diff --git a/drivers/char/drm/drm_pci.c b/drivers/char/drm/drm_pci.c
index 09ed712c1a7f..1fd7ff164817 100644
--- a/drivers/char/drm/drm_pci.c
+++ b/drivers/char/drm/drm_pci.c
@@ -77,7 +77,7 @@ drm_dma_handle_t *drm_pci_alloc(drm_device_t * dev, size_t size, size_t align,
77 dmah = kmalloc(sizeof(drm_dma_handle_t), GFP_KERNEL); 77 dmah = kmalloc(sizeof(drm_dma_handle_t), GFP_KERNEL);
78 if (!dmah) 78 if (!dmah)
79 return NULL; 79 return NULL;
80 80
81 dmah->size = size; 81 dmah->size = size;
82 dmah->vaddr = pci_alloc_consistent(dev->pdev, size, &dmah->busaddr); 82 dmah->vaddr = pci_alloc_consistent(dev->pdev, size, &dmah->busaddr);
83 83
@@ -106,6 +106,7 @@ drm_dma_handle_t *drm_pci_alloc(drm_device_t * dev, size_t size, size_t align,
106 106
107 return dmah; 107 return dmah;
108} 108}
109
109EXPORT_SYMBOL(drm_pci_alloc); 110EXPORT_SYMBOL(drm_pci_alloc);
110 111
111/** 112/**
@@ -113,8 +114,7 @@ EXPORT_SYMBOL(drm_pci_alloc);
113 * 114 *
114 * This function is for internal use in the Linux-specific DRM core code. 115 * This function is for internal use in the Linux-specific DRM core code.
115 */ 116 */
116void 117void __drm_pci_free(drm_device_t * dev, drm_dma_handle_t * dmah)
117__drm_pci_free(drm_device_t * dev, drm_dma_handle_t *dmah)
118{ 118{
119#ifdef DRM_DEBUG_MEMORY 119#ifdef DRM_DEBUG_MEMORY
120 int area = DRM_MEM_DMA; 120 int area = DRM_MEM_DMA;
@@ -150,12 +150,12 @@ __drm_pci_free(drm_device_t * dev, drm_dma_handle_t *dmah)
150/** 150/**
151 * \brief Free a PCI consistent memory block 151 * \brief Free a PCI consistent memory block
152 */ 152 */
153void 153void drm_pci_free(drm_device_t * dev, drm_dma_handle_t * dmah)
154drm_pci_free(drm_device_t *dev, drm_dma_handle_t *dmah)
155{ 154{
156 __drm_pci_free(dev, dmah); 155 __drm_pci_free(dev, dmah);
157 kfree(dmah); 156 kfree(dmah);
158} 157}
158
159EXPORT_SYMBOL(drm_pci_free); 159EXPORT_SYMBOL(drm_pci_free);
160 160
161/*@}*/ 161/*@}*/
diff --git a/drivers/char/drm/drm_pciids.h b/drivers/char/drm/drm_pciids.h
index 58b1747cd440..d66dc55e29a0 100644
--- a/drivers/char/drm/drm_pciids.h
+++ b/drivers/char/drm/drm_pciids.h
@@ -234,4 +234,3 @@
234 {0x8086, 0x2592, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 234 {0x8086, 0x2592, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
235 {0x8086, 0x2772, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 235 {0x8086, 0x2772, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
236 {0, 0, 0} 236 {0, 0, 0}
237
diff --git a/drivers/char/drm/drm_proc.c b/drivers/char/drm/drm_proc.c
index 32d2bb99462c..8ec2156b97a9 100644
--- a/drivers/char/drm/drm_proc.c
+++ b/drivers/char/drm/drm_proc.c
@@ -1,5 +1,5 @@
1/** 1/**
2 * \file drm_proc.h 2 * \file drm_proc.c
3 * /proc support for DRM 3 * /proc support for DRM
4 * 4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
@@ -39,19 +39,19 @@
39 39
40#include "drmP.h" 40#include "drmP.h"
41 41
42static int drm_name_info(char *buf, char **start, off_t offset, 42static int drm_name_info(char *buf, char **start, off_t offset,
43 int request, int *eof, void *data); 43 int request, int *eof, void *data);
44static int drm_vm_info(char *buf, char **start, off_t offset, 44static int drm_vm_info(char *buf, char **start, off_t offset,
45 int request, int *eof, void *data); 45 int request, int *eof, void *data);
46static int drm_clients_info(char *buf, char **start, off_t offset, 46static int drm_clients_info(char *buf, char **start, off_t offset,
47 int request, int *eof, void *data); 47 int request, int *eof, void *data);
48static int drm_queues_info(char *buf, char **start, off_t offset, 48static int drm_queues_info(char *buf, char **start, off_t offset,
49 int request, int *eof, void *data); 49 int request, int *eof, void *data);
50static int drm_bufs_info(char *buf, char **start, off_t offset, 50static int drm_bufs_info(char *buf, char **start, off_t offset,
51 int request, int *eof, void *data); 51 int request, int *eof, void *data);
52#if DRM_DEBUG_CODE 52#if DRM_DEBUG_CODE
53static int drm_vma_info(char *buf, char **start, off_t offset, 53static int drm_vma_info(char *buf, char **start, off_t offset,
54 int request, int *eof, void *data); 54 int request, int *eof, void *data);
55#endif 55#endif
56 56
57/** 57/**
@@ -59,18 +59,21 @@ static int drm_vma_info(char *buf, char **start, off_t offset,
59 */ 59 */
60static struct drm_proc_list { 60static struct drm_proc_list {
61 const char *name; /**< file name */ 61 const char *name; /**< file name */
62 int (*f)(char *, char **, off_t, int, int *, void *); /**< proc callback*/ 62 int (*f) (char *, char **, off_t, int, int *, void *); /**< proc callback*/
63} drm_proc_list[] = { 63} drm_proc_list[] = {
64 { "name", drm_name_info }, 64 {
65 { "mem", drm_mem_info }, 65 "name", drm_name_info}, {
66 { "vm", drm_vm_info }, 66 "mem", drm_mem_info}, {
67 { "clients", drm_clients_info }, 67 "vm", drm_vm_info}, {
68 { "queues", drm_queues_info }, 68 "clients", drm_clients_info}, {
69 { "bufs", drm_bufs_info }, 69 "queues", drm_queues_info}, {
70 "bufs", drm_bufs_info},
70#if DRM_DEBUG_CODE 71#if DRM_DEBUG_CODE
71 { "vma", drm_vma_info }, 72 {
73 "vma", drm_vma_info},
72#endif 74#endif
73}; 75};
76
74#define DRM_PROC_ENTRIES (sizeof(drm_proc_list)/sizeof(drm_proc_list[0])) 77#define DRM_PROC_ENTRIES (sizeof(drm_proc_list)/sizeof(drm_proc_list[0]))
75 78
76/** 79/**
@@ -81,18 +84,17 @@ static struct drm_proc_list {
81 * \param root DRI proc dir entry. 84 * \param root DRI proc dir entry.
82 * \param dev_root resulting DRI device proc dir entry. 85 * \param dev_root resulting DRI device proc dir entry.
83 * \return root entry pointer on success, or NULL on failure. 86 * \return root entry pointer on success, or NULL on failure.
84 * 87 *
85 * Create the DRI proc root entry "/proc/dri", the device proc root entry 88 * Create the DRI proc root entry "/proc/dri", the device proc root entry
86 * "/proc/dri/%minor%/", and each entry in proc_list as 89 * "/proc/dri/%minor%/", and each entry in proc_list as
87 * "/proc/dri/%minor%/%name%". 90 * "/proc/dri/%minor%/%name%".
88 */ 91 */
89int drm_proc_init(drm_device_t *dev, int minor, 92int drm_proc_init(drm_device_t * dev, int minor,
90 struct proc_dir_entry *root, 93 struct proc_dir_entry *root, struct proc_dir_entry **dev_root)
91 struct proc_dir_entry **dev_root)
92{ 94{
93 struct proc_dir_entry *ent; 95 struct proc_dir_entry *ent;
94 int i, j; 96 int i, j;
95 char name[64]; 97 char name[64];
96 98
97 sprintf(name, "%d", minor); 99 sprintf(name, "%d", minor);
98 *dev_root = create_proc_entry(name, S_IFDIR, root); 100 *dev_root = create_proc_entry(name, S_IFDIR, root);
@@ -103,7 +105,7 @@ int drm_proc_init(drm_device_t *dev, int minor,
103 105
104 for (i = 0; i < DRM_PROC_ENTRIES; i++) { 106 for (i = 0; i < DRM_PROC_ENTRIES; i++) {
105 ent = create_proc_entry(drm_proc_list[i].name, 107 ent = create_proc_entry(drm_proc_list[i].name,
106 S_IFREG|S_IRUGO, *dev_root); 108 S_IFREG | S_IRUGO, *dev_root);
107 if (!ent) { 109 if (!ent) {
108 DRM_ERROR("Cannot create /proc/dri/%s/%s\n", 110 DRM_ERROR("Cannot create /proc/dri/%s/%s\n",
109 name, drm_proc_list[i].name); 111 name, drm_proc_list[i].name);
@@ -114,13 +116,12 @@ int drm_proc_init(drm_device_t *dev, int minor,
114 return -1; 116 return -1;
115 } 117 }
116 ent->read_proc = drm_proc_list[i].f; 118 ent->read_proc = drm_proc_list[i].f;
117 ent->data = dev; 119 ent->data = dev;
118 } 120 }
119 121
120 return 0; 122 return 0;
121} 123}
122 124
123
124/** 125/**
125 * Cleanup the proc filesystem resources. 126 * Cleanup the proc filesystem resources.
126 * 127 *
@@ -132,12 +133,13 @@ int drm_proc_init(drm_device_t *dev, int minor,
132 * Remove all proc entries created by proc_init(). 133 * Remove all proc entries created by proc_init().
133 */ 134 */
134int drm_proc_cleanup(int minor, struct proc_dir_entry *root, 135int drm_proc_cleanup(int minor, struct proc_dir_entry *root,
135 struct proc_dir_entry *dev_root) 136 struct proc_dir_entry *dev_root)
136{ 137{
137 int i; 138 int i;
138 char name[64]; 139 char name[64];
139 140
140 if (!root || !dev_root) return 0; 141 if (!root || !dev_root)
142 return 0;
141 143
142 for (i = 0; i < DRM_PROC_ENTRIES; i++) 144 for (i = 0; i < DRM_PROC_ENTRIES; i++)
143 remove_proc_entry(drm_proc_list[i].name, dev_root); 145 remove_proc_entry(drm_proc_list[i].name, dev_root);
@@ -149,7 +151,7 @@ int drm_proc_cleanup(int minor, struct proc_dir_entry *root,
149 151
150/** 152/**
151 * Called when "/proc/dri/.../name" is read. 153 * Called when "/proc/dri/.../name" is read.
152 * 154 *
153 * \param buf output buffer. 155 * \param buf output buffer.
154 * \param start start of output data. 156 * \param start start of output data.
155 * \param offset requested start offset. 157 * \param offset requested start offset.
@@ -157,14 +159,14 @@ int drm_proc_cleanup(int minor, struct proc_dir_entry *root,
157 * \param eof whether there is no more data to return. 159 * \param eof whether there is no more data to return.
158 * \param data private data. 160 * \param data private data.
159 * \return number of written bytes. 161 * \return number of written bytes.
160 * 162 *
161 * Prints the device name together with the bus id if available. 163 * Prints the device name together with the bus id if available.
162 */ 164 */
163static int drm_name_info(char *buf, char **start, off_t offset, int request, 165static int drm_name_info(char *buf, char **start, off_t offset, int request,
164 int *eof, void *data) 166 int *eof, void *data)
165{ 167{
166 drm_device_t *dev = (drm_device_t *)data; 168 drm_device_t *dev = (drm_device_t *) data;
167 int len = 0; 169 int len = 0;
168 170
169 if (offset > DRM_PROC_LIMIT) { 171 if (offset > DRM_PROC_LIMIT) {
170 *eof = 1; 172 *eof = 1;
@@ -172,23 +174,26 @@ static int drm_name_info(char *buf, char **start, off_t offset, int request,
172 } 174 }
173 175
174 *start = &buf[offset]; 176 *start = &buf[offset];
175 *eof = 0; 177 *eof = 0;
176 178
177 if (dev->unique) { 179 if (dev->unique) {
178 DRM_PROC_PRINT("%s %s %s\n", 180 DRM_PROC_PRINT("%s %s %s\n",
179 dev->driver->pci_driver.name, pci_name(dev->pdev), dev->unique); 181 dev->driver->pci_driver.name,
182 pci_name(dev->pdev), dev->unique);
180 } else { 183 } else {
181 DRM_PROC_PRINT("%s %s\n", dev->driver->pci_driver.name, pci_name(dev->pdev)); 184 DRM_PROC_PRINT("%s %s\n", dev->driver->pci_driver.name,
185 pci_name(dev->pdev));
182 } 186 }
183 187
184 if (len > request + offset) return request; 188 if (len > request + offset)
189 return request;
185 *eof = 1; 190 *eof = 1;
186 return len - offset; 191 return len - offset;
187} 192}
188 193
189/** 194/**
190 * Called when "/proc/dri/.../vm" is read. 195 * Called when "/proc/dri/.../vm" is read.
191 * 196 *
192 * \param buf output buffer. 197 * \param buf output buffer.
193 * \param start start of output data. 198 * \param start start of output data.
194 * \param offset requested start offset. 199 * \param offset requested start offset.
@@ -196,24 +201,24 @@ static int drm_name_info(char *buf, char **start, off_t offset, int request,
196 * \param eof whether there is no more data to return. 201 * \param eof whether there is no more data to return.
197 * \param data private data. 202 * \param data private data.
198 * \return number of written bytes. 203 * \return number of written bytes.
199 * 204 *
200 * Prints information about all mappings in drm_device::maplist. 205 * Prints information about all mappings in drm_device::maplist.
201 */ 206 */
202static int drm__vm_info(char *buf, char **start, off_t offset, int request, 207static int drm__vm_info(char *buf, char **start, off_t offset, int request,
203 int *eof, void *data) 208 int *eof, void *data)
204{ 209{
205 drm_device_t *dev = (drm_device_t *)data; 210 drm_device_t *dev = (drm_device_t *) data;
206 int len = 0; 211 int len = 0;
207 drm_map_t *map; 212 drm_map_t *map;
208 drm_map_list_t *r_list; 213 drm_map_list_t *r_list;
209 struct list_head *list; 214 struct list_head *list;
210 215
211 /* Hardcoded from _DRM_FRAME_BUFFER, 216 /* Hardcoded from _DRM_FRAME_BUFFER,
212 _DRM_REGISTERS, _DRM_SHM, _DRM_AGP, and 217 _DRM_REGISTERS, _DRM_SHM, _DRM_AGP, and
213 _DRM_SCATTER_GATHER and _DRM_CONSISTENT */ 218 _DRM_SCATTER_GATHER and _DRM_CONSISTENT */
214 const char *types[] = { "FB", "REG", "SHM", "AGP", "SG", "PCI" }; 219 const char *types[] = { "FB", "REG", "SHM", "AGP", "SG", "PCI" };
215 const char *type; 220 const char *type;
216 int i; 221 int i;
217 222
218 if (offset > DRM_PROC_LIMIT) { 223 if (offset > DRM_PROC_LIMIT) {
219 *eof = 1; 224 *eof = 1;
@@ -221,36 +226,35 @@ static int drm__vm_info(char *buf, char **start, off_t offset, int request,
221 } 226 }
222 227
223 *start = &buf[offset]; 228 *start = &buf[offset];
224 *eof = 0; 229 *eof = 0;
225 230
226 DRM_PROC_PRINT("slot offset size type flags " 231 DRM_PROC_PRINT("slot offset size type flags "
227 "address mtrr\n\n"); 232 "address mtrr\n\n");
228 i = 0; 233 i = 0;
229 if (dev->maplist != NULL) list_for_each(list, &dev->maplist->head) { 234 if (dev->maplist != NULL)
235 list_for_each(list, &dev->maplist->head) {
230 r_list = list_entry(list, drm_map_list_t, head); 236 r_list = list_entry(list, drm_map_list_t, head);
231 map = r_list->map; 237 map = r_list->map;
232 if(!map) 238 if (!map)
233 continue; 239 continue;
234 if (map->type < 0 || map->type > 5) 240 if (map->type < 0 || map->type > 5)
235 type = "??"; 241 type = "??";
236 else 242 else
237 type = types[map->type]; 243 type = types[map->type];
238 DRM_PROC_PRINT("%4d 0x%08lx 0x%08lx %4.4s 0x%02x 0x%08x ", 244 DRM_PROC_PRINT("%4d 0x%08lx 0x%08lx %4.4s 0x%02x 0x%08x ",
239 i, 245 i,
240 map->offset, 246 map->offset,
241 map->size, 247 map->size, type, map->flags, r_list->user_token);
242 type,
243 map->flags,
244 r_list->user_token);
245 if (map->mtrr < 0) { 248 if (map->mtrr < 0) {
246 DRM_PROC_PRINT("none\n"); 249 DRM_PROC_PRINT("none\n");
247 } else { 250 } else {
248 DRM_PROC_PRINT("%4d\n", map->mtrr); 251 DRM_PROC_PRINT("%4d\n", map->mtrr);
249 } 252 }
250 i++; 253 i++;
251 } 254 }
252 255
253 if (len > request + offset) return request; 256 if (len > request + offset)
257 return request;
254 *eof = 1; 258 *eof = 1;
255 return len - offset; 259 return len - offset;
256} 260}
@@ -259,10 +263,10 @@ static int drm__vm_info(char *buf, char **start, off_t offset, int request,
259 * Simply calls _vm_info() while holding the drm_device::struct_sem lock. 263 * Simply calls _vm_info() while holding the drm_device::struct_sem lock.
260 */ 264 */
261static int drm_vm_info(char *buf, char **start, off_t offset, int request, 265static int drm_vm_info(char *buf, char **start, off_t offset, int request,
262 int *eof, void *data) 266 int *eof, void *data)
263{ 267{
264 drm_device_t *dev = (drm_device_t *)data; 268 drm_device_t *dev = (drm_device_t *) data;
265 int ret; 269 int ret;
266 270
267 down(&dev->struct_sem); 271 down(&dev->struct_sem);
268 ret = drm__vm_info(buf, start, offset, request, eof, data); 272 ret = drm__vm_info(buf, start, offset, request, eof, data);
@@ -272,7 +276,7 @@ static int drm_vm_info(char *buf, char **start, off_t offset, int request,
272 276
273/** 277/**
274 * Called when "/proc/dri/.../queues" is read. 278 * Called when "/proc/dri/.../queues" is read.
275 * 279 *
276 * \param buf output buffer. 280 * \param buf output buffer.
277 * \param start start of output data. 281 * \param start start of output data.
278 * \param offset requested start offset. 282 * \param offset requested start offset.
@@ -282,12 +286,12 @@ static int drm_vm_info(char *buf, char **start, off_t offset, int request,
282 * \return number of written bytes. 286 * \return number of written bytes.
283 */ 287 */
284static int drm__queues_info(char *buf, char **start, off_t offset, 288static int drm__queues_info(char *buf, char **start, off_t offset,
285 int request, int *eof, void *data) 289 int request, int *eof, void *data)
286{ 290{
287 drm_device_t *dev = (drm_device_t *)data; 291 drm_device_t *dev = (drm_device_t *) data;
288 int len = 0; 292 int len = 0;
289 int i; 293 int i;
290 drm_queue_t *q; 294 drm_queue_t *q;
291 295
292 if (offset > DRM_PROC_LIMIT) { 296 if (offset > DRM_PROC_LIMIT) {
293 *eof = 1; 297 *eof = 1;
@@ -295,7 +299,7 @@ static int drm__queues_info(char *buf, char **start, off_t offset,
295 } 299 }
296 300
297 *start = &buf[offset]; 301 *start = &buf[offset];
298 *eof = 0; 302 *eof = 0;
299 303
300 DRM_PROC_PRINT(" ctx/flags use fin" 304 DRM_PROC_PRINT(" ctx/flags use fin"
301 " blk/rw/rwf wait flushed queued" 305 " blk/rw/rwf wait flushed queued"
@@ -313,14 +317,17 @@ static int drm__queues_info(char *buf, char **start, off_t offset,
313 atomic_read(&q->block_count), 317 atomic_read(&q->block_count),
314 atomic_read(&q->block_read) ? 'r' : '-', 318 atomic_read(&q->block_read) ? 'r' : '-',
315 atomic_read(&q->block_write) ? 'w' : '-', 319 atomic_read(&q->block_write) ? 'w' : '-',
316 waitqueue_active(&q->read_queue) ? 'r':'-', 320 waitqueue_active(&q->read_queue) ? 'r' : '-',
317 waitqueue_active(&q->write_queue) ? 'w':'-', 321 waitqueue_active(&q->
318 waitqueue_active(&q->flush_queue) ? 'f':'-', 322 write_queue) ? 'w' : '-',
323 waitqueue_active(&q->
324 flush_queue) ? 'f' : '-',
319 DRM_BUFCOUNT(&q->waitlist)); 325 DRM_BUFCOUNT(&q->waitlist));
320 atomic_dec(&q->use_count); 326 atomic_dec(&q->use_count);
321 } 327 }
322 328
323 if (len > request + offset) return request; 329 if (len > request + offset)
330 return request;
324 *eof = 1; 331 *eof = 1;
325 return len - offset; 332 return len - offset;
326} 333}
@@ -329,10 +336,10 @@ static int drm__queues_info(char *buf, char **start, off_t offset,
329 * Simply calls _queues_info() while holding the drm_device::struct_sem lock. 336 * Simply calls _queues_info() while holding the drm_device::struct_sem lock.
330 */ 337 */
331static int drm_queues_info(char *buf, char **start, off_t offset, int request, 338static int drm_queues_info(char *buf, char **start, off_t offset, int request,
332 int *eof, void *data) 339 int *eof, void *data)
333{ 340{
334 drm_device_t *dev = (drm_device_t *)data; 341 drm_device_t *dev = (drm_device_t *) data;
335 int ret; 342 int ret;
336 343
337 down(&dev->struct_sem); 344 down(&dev->struct_sem);
338 ret = drm__queues_info(buf, start, offset, request, eof, data); 345 ret = drm__queues_info(buf, start, offset, request, eof, data);
@@ -342,7 +349,7 @@ static int drm_queues_info(char *buf, char **start, off_t offset, int request,
342 349
343/** 350/**
344 * Called when "/proc/dri/.../bufs" is read. 351 * Called when "/proc/dri/.../bufs" is read.
345 * 352 *
346 * \param buf output buffer. 353 * \param buf output buffer.
347 * \param start start of output data. 354 * \param start start of output data.
348 * \param offset requested start offset. 355 * \param offset requested start offset.
@@ -352,12 +359,12 @@ static int drm_queues_info(char *buf, char **start, off_t offset, int request,
352 * \return number of written bytes. 359 * \return number of written bytes.
353 */ 360 */
354static int drm__bufs_info(char *buf, char **start, off_t offset, int request, 361static int drm__bufs_info(char *buf, char **start, off_t offset, int request,
355 int *eof, void *data) 362 int *eof, void *data)
356{ 363{
357 drm_device_t *dev = (drm_device_t *)data; 364 drm_device_t *dev = (drm_device_t *) data;
358 int len = 0; 365 int len = 0;
359 drm_device_dma_t *dma = dev->dma; 366 drm_device_dma_t *dma = dev->dma;
360 int i; 367 int i;
361 368
362 if (!dma || offset > DRM_PROC_LIMIT) { 369 if (!dma || offset > DRM_PROC_LIMIT) {
363 *eof = 1; 370 *eof = 1;
@@ -365,7 +372,7 @@ static int drm__bufs_info(char *buf, char **start, off_t offset, int request,
365 } 372 }
366 373
367 *start = &buf[offset]; 374 *start = &buf[offset];
368 *eof = 0; 375 *eof = 0;
369 376
370 DRM_PROC_PRINT(" o size count free segs pages kB\n\n"); 377 DRM_PROC_PRINT(" o size count free segs pages kB\n\n");
371 for (i = 0; i <= DRM_MAX_ORDER; i++) { 378 for (i = 0; i <= DRM_MAX_ORDER; i++) {
@@ -378,19 +385,21 @@ static int drm__bufs_info(char *buf, char **start, off_t offset, int request,
378 .freelist.count), 385 .freelist.count),
379 dma->bufs[i].seg_count, 386 dma->bufs[i].seg_count,
380 dma->bufs[i].seg_count 387 dma->bufs[i].seg_count
381 *(1 << dma->bufs[i].page_order), 388 * (1 << dma->bufs[i].page_order),
382 (dma->bufs[i].seg_count 389 (dma->bufs[i].seg_count
383 * (1 << dma->bufs[i].page_order)) 390 * (1 << dma->bufs[i].page_order))
384 * PAGE_SIZE / 1024); 391 * PAGE_SIZE / 1024);
385 } 392 }
386 DRM_PROC_PRINT("\n"); 393 DRM_PROC_PRINT("\n");
387 for (i = 0; i < dma->buf_count; i++) { 394 for (i = 0; i < dma->buf_count; i++) {
388 if (i && !(i%32)) DRM_PROC_PRINT("\n"); 395 if (i && !(i % 32))
396 DRM_PROC_PRINT("\n");
389 DRM_PROC_PRINT(" %d", dma->buflist[i]->list); 397 DRM_PROC_PRINT(" %d", dma->buflist[i]->list);
390 } 398 }
391 DRM_PROC_PRINT("\n"); 399 DRM_PROC_PRINT("\n");
392 400
393 if (len > request + offset) return request; 401 if (len > request + offset)
402 return request;
394 *eof = 1; 403 *eof = 1;
395 return len - offset; 404 return len - offset;
396} 405}
@@ -399,10 +408,10 @@ static int drm__bufs_info(char *buf, char **start, off_t offset, int request,
399 * Simply calls _bufs_info() while holding the drm_device::struct_sem lock. 408 * Simply calls _bufs_info() while holding the drm_device::struct_sem lock.
400 */ 409 */
401static int drm_bufs_info(char *buf, char **start, off_t offset, int request, 410static int drm_bufs_info(char *buf, char **start, off_t offset, int request,
402 int *eof, void *data) 411 int *eof, void *data)
403{ 412{
404 drm_device_t *dev = (drm_device_t *)data; 413 drm_device_t *dev = (drm_device_t *) data;
405 int ret; 414 int ret;
406 415
407 down(&dev->struct_sem); 416 down(&dev->struct_sem);
408 ret = drm__bufs_info(buf, start, offset, request, eof, data); 417 ret = drm__bufs_info(buf, start, offset, request, eof, data);
@@ -412,7 +421,7 @@ static int drm_bufs_info(char *buf, char **start, off_t offset, int request,
412 421
413/** 422/**
414 * Called when "/proc/dri/.../clients" is read. 423 * Called when "/proc/dri/.../clients" is read.
415 * 424 *
416 * \param buf output buffer. 425 * \param buf output buffer.
417 * \param start start of output data. 426 * \param start start of output data.
418 * \param offset requested start offset. 427 * \param offset requested start offset.
@@ -422,11 +431,11 @@ static int drm_bufs_info(char *buf, char **start, off_t offset, int request,
422 * \return number of written bytes. 431 * \return number of written bytes.
423 */ 432 */
424static int drm__clients_info(char *buf, char **start, off_t offset, 433static int drm__clients_info(char *buf, char **start, off_t offset,
425 int request, int *eof, void *data) 434 int request, int *eof, void *data)
426{ 435{
427 drm_device_t *dev = (drm_device_t *)data; 436 drm_device_t *dev = (drm_device_t *) data;
428 int len = 0; 437 int len = 0;
429 drm_file_t *priv; 438 drm_file_t *priv;
430 439
431 if (offset > DRM_PROC_LIMIT) { 440 if (offset > DRM_PROC_LIMIT) {
432 *eof = 1; 441 *eof = 1;
@@ -434,7 +443,7 @@ static int drm__clients_info(char *buf, char **start, off_t offset,
434 } 443 }
435 444
436 *start = &buf[offset]; 445 *start = &buf[offset];
437 *eof = 0; 446 *eof = 0;
438 447
439 DRM_PROC_PRINT("a dev pid uid magic ioctls\n\n"); 448 DRM_PROC_PRINT("a dev pid uid magic ioctls\n\n");
440 for (priv = dev->file_first; priv; priv = priv->next) { 449 for (priv = dev->file_first; priv; priv = priv->next) {
@@ -442,12 +451,11 @@ static int drm__clients_info(char *buf, char **start, off_t offset,
442 priv->authenticated ? 'y' : 'n', 451 priv->authenticated ? 'y' : 'n',
443 priv->minor, 452 priv->minor,
444 priv->pid, 453 priv->pid,
445 priv->uid, 454 priv->uid, priv->magic, priv->ioctl_count);
446 priv->magic,
447 priv->ioctl_count);
448 } 455 }
449 456
450 if (len > request + offset) return request; 457 if (len > request + offset)
458 return request;
451 *eof = 1; 459 *eof = 1;
452 return len - offset; 460 return len - offset;
453} 461}
@@ -456,10 +464,10 @@ static int drm__clients_info(char *buf, char **start, off_t offset,
456 * Simply calls _clients_info() while holding the drm_device::struct_sem lock. 464 * Simply calls _clients_info() while holding the drm_device::struct_sem lock.
457 */ 465 */
458static int drm_clients_info(char *buf, char **start, off_t offset, 466static int drm_clients_info(char *buf, char **start, off_t offset,
459 int request, int *eof, void *data) 467 int request, int *eof, void *data)
460{ 468{
461 drm_device_t *dev = (drm_device_t *)data; 469 drm_device_t *dev = (drm_device_t *) data;
462 int ret; 470 int ret;
463 471
464 down(&dev->struct_sem); 472 down(&dev->struct_sem);
465 ret = drm__clients_info(buf, start, offset, request, eof, data); 473 ret = drm__clients_info(buf, start, offset, request, eof, data);
@@ -470,14 +478,14 @@ static int drm_clients_info(char *buf, char **start, off_t offset,
470#if DRM_DEBUG_CODE 478#if DRM_DEBUG_CODE
471 479
472static int drm__vma_info(char *buf, char **start, off_t offset, int request, 480static int drm__vma_info(char *buf, char **start, off_t offset, int request,
473 int *eof, void *data) 481 int *eof, void *data)
474{ 482{
475 drm_device_t *dev = (drm_device_t *)data; 483 drm_device_t *dev = (drm_device_t *) data;
476 int len = 0; 484 int len = 0;
477 drm_vma_entry_t *pt; 485 drm_vma_entry_t *pt;
478 struct vm_area_struct *vma; 486 struct vm_area_struct *vma;
479#if defined(__i386__) 487#if defined(__i386__)
480 unsigned int pgprot; 488 unsigned int pgprot;
481#endif 489#endif
482 490
483 if (offset > DRM_PROC_LIMIT) { 491 if (offset > DRM_PROC_LIMIT) {
@@ -486,51 +494,53 @@ static int drm__vma_info(char *buf, char **start, off_t offset, int request,
486 } 494 }
487 495
488 *start = &buf[offset]; 496 *start = &buf[offset];
489 *eof = 0; 497 *eof = 0;
490 498
491 DRM_PROC_PRINT("vma use count: %d, high_memory = %p, 0x%08lx\n", 499 DRM_PROC_PRINT("vma use count: %d, high_memory = %p, 0x%08lx\n",
492 atomic_read(&dev->vma_count), 500 atomic_read(&dev->vma_count),
493 high_memory, virt_to_phys(high_memory)); 501 high_memory, virt_to_phys(high_memory));
494 for (pt = dev->vmalist; pt; pt = pt->next) { 502 for (pt = dev->vmalist; pt; pt = pt->next) {
495 if (!(vma = pt->vma)) continue; 503 if (!(vma = pt->vma))
504 continue;
496 DRM_PROC_PRINT("\n%5d 0x%08lx-0x%08lx %c%c%c%c%c%c 0x%08lx", 505 DRM_PROC_PRINT("\n%5d 0x%08lx-0x%08lx %c%c%c%c%c%c 0x%08lx",
497 pt->pid, 506 pt->pid,
498 vma->vm_start, 507 vma->vm_start,
499 vma->vm_end, 508 vma->vm_end,
500 vma->vm_flags & VM_READ ? 'r' : '-', 509 vma->vm_flags & VM_READ ? 'r' : '-',
501 vma->vm_flags & VM_WRITE ? 'w' : '-', 510 vma->vm_flags & VM_WRITE ? 'w' : '-',
502 vma->vm_flags & VM_EXEC ? 'x' : '-', 511 vma->vm_flags & VM_EXEC ? 'x' : '-',
503 vma->vm_flags & VM_MAYSHARE ? 's' : 'p', 512 vma->vm_flags & VM_MAYSHARE ? 's' : 'p',
504 vma->vm_flags & VM_LOCKED ? 'l' : '-', 513 vma->vm_flags & VM_LOCKED ? 'l' : '-',
505 vma->vm_flags & VM_IO ? 'i' : '-', 514 vma->vm_flags & VM_IO ? 'i' : '-',
506 VM_OFFSET(vma)); 515 VM_OFFSET(vma));
507 516
508#if defined(__i386__) 517#if defined(__i386__)
509 pgprot = pgprot_val(vma->vm_page_prot); 518 pgprot = pgprot_val(vma->vm_page_prot);
510 DRM_PROC_PRINT(" %c%c%c%c%c%c%c%c%c", 519 DRM_PROC_PRINT(" %c%c%c%c%c%c%c%c%c",
511 pgprot & _PAGE_PRESENT ? 'p' : '-', 520 pgprot & _PAGE_PRESENT ? 'p' : '-',
512 pgprot & _PAGE_RW ? 'w' : 'r', 521 pgprot & _PAGE_RW ? 'w' : 'r',
513 pgprot & _PAGE_USER ? 'u' : 's', 522 pgprot & _PAGE_USER ? 'u' : 's',
514 pgprot & _PAGE_PWT ? 't' : 'b', 523 pgprot & _PAGE_PWT ? 't' : 'b',
515 pgprot & _PAGE_PCD ? 'u' : 'c', 524 pgprot & _PAGE_PCD ? 'u' : 'c',
516 pgprot & _PAGE_ACCESSED ? 'a' : '-', 525 pgprot & _PAGE_ACCESSED ? 'a' : '-',
517 pgprot & _PAGE_DIRTY ? 'd' : '-', 526 pgprot & _PAGE_DIRTY ? 'd' : '-',
518 pgprot & _PAGE_PSE ? 'm' : 'k', 527 pgprot & _PAGE_PSE ? 'm' : 'k',
519 pgprot & _PAGE_GLOBAL ? 'g' : 'l' ); 528 pgprot & _PAGE_GLOBAL ? 'g' : 'l');
520#endif 529#endif
521 DRM_PROC_PRINT("\n"); 530 DRM_PROC_PRINT("\n");
522 } 531 }
523 532
524 if (len > request + offset) return request; 533 if (len > request + offset)
534 return request;
525 *eof = 1; 535 *eof = 1;
526 return len - offset; 536 return len - offset;
527} 537}
528 538
529static int drm_vma_info(char *buf, char **start, off_t offset, int request, 539static int drm_vma_info(char *buf, char **start, off_t offset, int request,
530 int *eof, void *data) 540 int *eof, void *data)
531{ 541{
532 drm_device_t *dev = (drm_device_t *)data; 542 drm_device_t *dev = (drm_device_t *) data;
533 int ret; 543 int ret;
534 544
535 down(&dev->struct_sem); 545 down(&dev->struct_sem);
536 ret = drm__vma_info(buf, start, offset, request, eof, data); 546 ret = drm__vma_info(buf, start, offset, request, eof, data);
@@ -538,5 +548,3 @@ static int drm_vma_info(char *buf, char **start, off_t offset, int request,
538 return ret; 548 return ret;
539} 549}
540#endif 550#endif
541
542
diff --git a/drivers/char/drm/drm_sarea.h b/drivers/char/drm/drm_sarea.h
index de782ed2f03a..e94297b751b8 100644
--- a/drivers/char/drm/drm_sarea.h
+++ b/drivers/char/drm/drm_sarea.h
@@ -1,5 +1,5 @@
1/** 1/**
2 * \file drm_sarea.h 2 * \file drm_sarea.h
3 * \brief SAREA definitions 3 * \brief SAREA definitions
4 * 4 *
5 * \author Michel Dänzer <michel@daenzer.net> 5 * \author Michel Dänzer <michel@daenzer.net>
@@ -38,7 +38,7 @@
38#if defined(__alpha__) 38#if defined(__alpha__)
39#define SAREA_MAX 0x2000 39#define SAREA_MAX 0x2000
40#elif defined(__ia64__) 40#elif defined(__ia64__)
41#define SAREA_MAX 0x10000 /* 64kB */ 41#define SAREA_MAX 0x10000 /* 64kB */
42#else 42#else
43/* Intel 830M driver needs at least 8k SAREA */ 43/* Intel 830M driver needs at least 8k SAREA */
44#define SAREA_MAX 0x2000 44#define SAREA_MAX 0x2000
@@ -51,28 +51,28 @@
51 51
52/** SAREA drawable */ 52/** SAREA drawable */
53typedef struct drm_sarea_drawable { 53typedef struct drm_sarea_drawable {
54 unsigned int stamp; 54 unsigned int stamp;
55 unsigned int flags; 55 unsigned int flags;
56} drm_sarea_drawable_t; 56} drm_sarea_drawable_t;
57 57
58/** SAREA frame */ 58/** SAREA frame */
59typedef struct drm_sarea_frame { 59typedef struct drm_sarea_frame {
60 unsigned int x; 60 unsigned int x;
61 unsigned int y; 61 unsigned int y;
62 unsigned int width; 62 unsigned int width;
63 unsigned int height; 63 unsigned int height;
64 unsigned int fullscreen; 64 unsigned int fullscreen;
65} drm_sarea_frame_t; 65} drm_sarea_frame_t;
66 66
67/** SAREA */ 67/** SAREA */
68typedef struct drm_sarea { 68typedef struct drm_sarea {
69 /** first thing is always the DRM locking structure */ 69 /** first thing is always the DRM locking structure */
70 drm_hw_lock_t lock; 70 drm_hw_lock_t lock;
71 /** \todo Use readers/writer lock for drm_sarea::drawable_lock */ 71 /** \todo Use readers/writer lock for drm_sarea::drawable_lock */
72 drm_hw_lock_t drawable_lock; 72 drm_hw_lock_t drawable_lock;
73 drm_sarea_drawable_t drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */ 73 drm_sarea_drawable_t drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */
74 drm_sarea_frame_t frame; /**< frame */ 74 drm_sarea_frame_t frame; /**< frame */
75 drm_context_t dummy_context; 75 drm_context_t dummy_context;
76} drm_sarea_t; 76} drm_sarea_t;
77 77
78#endif /* _DRM_SAREA_H_ */ 78#endif /* _DRM_SAREA_H_ */
diff --git a/drivers/char/drm/drm_scatter.c b/drivers/char/drm/drm_scatter.c
index ed267d49bc6a..ce81bf248200 100644
--- a/drivers/char/drm/drm_scatter.c
+++ b/drivers/char/drm/drm_scatter.c
@@ -1,5 +1,5 @@
1/** 1/**
2 * \file drm_scatter.h 2 * \file drm_scatter.c
3 * IOCTLs to manage scatter/gather memory 3 * IOCTLs to manage scatter/gather memory
4 * 4 *
5 * \author Gareth Hughes <gareth@valinux.com> 5 * \author Gareth Hughes <gareth@valinux.com>
@@ -37,28 +37,24 @@
37 37
38#define DEBUG_SCATTER 0 38#define DEBUG_SCATTER 0
39 39
40void drm_sg_cleanup( drm_sg_mem_t *entry ) 40void drm_sg_cleanup(drm_sg_mem_t * entry)
41{ 41{
42 struct page *page; 42 struct page *page;
43 int i; 43 int i;
44 44
45 for ( i = 0 ; i < entry->pages ; i++ ) { 45 for (i = 0; i < entry->pages; i++) {
46 page = entry->pagelist[i]; 46 page = entry->pagelist[i];
47 if ( page ) 47 if (page)
48 ClearPageReserved( page ); 48 ClearPageReserved(page);
49 } 49 }
50 50
51 vfree( entry->virtual ); 51 vfree(entry->virtual);
52 52
53 drm_free( entry->busaddr, 53 drm_free(entry->busaddr,
54 entry->pages * sizeof(*entry->busaddr), 54 entry->pages * sizeof(*entry->busaddr), DRM_MEM_PAGES);
55 DRM_MEM_PAGES ); 55 drm_free(entry->pagelist,
56 drm_free( entry->pagelist, 56 entry->pages * sizeof(*entry->pagelist), DRM_MEM_PAGES);
57 entry->pages * sizeof(*entry->pagelist), 57 drm_free(entry, sizeof(*entry), DRM_MEM_SGLISTS);
58 DRM_MEM_PAGES );
59 drm_free( entry,
60 sizeof(*entry),
61 DRM_MEM_SGLISTS );
62} 58}
63 59
64#ifdef _LP64 60#ifdef _LP64
@@ -67,8 +63,8 @@ void drm_sg_cleanup( drm_sg_mem_t *entry )
67# define ScatterHandle(x) (unsigned int)(x) 63# define ScatterHandle(x) (unsigned int)(x)
68#endif 64#endif
69 65
70int drm_sg_alloc( struct inode *inode, struct file *filp, 66int drm_sg_alloc(struct inode *inode, struct file *filp,
71 unsigned int cmd, unsigned long arg ) 67 unsigned int cmd, unsigned long arg)
72{ 68{
73 drm_file_t *priv = filp->private_data; 69 drm_file_t *priv = filp->private_data;
74 drm_device_t *dev = priv->head->dev; 70 drm_device_t *dev = priv->head->dev;
@@ -77,75 +73,70 @@ int drm_sg_alloc( struct inode *inode, struct file *filp,
77 drm_sg_mem_t *entry; 73 drm_sg_mem_t *entry;
78 unsigned long pages, i, j; 74 unsigned long pages, i, j;
79 75
80 DRM_DEBUG( "%s\n", __FUNCTION__ ); 76 DRM_DEBUG("%s\n", __FUNCTION__);
81 77
82 if (!drm_core_check_feature(dev, DRIVER_SG)) 78 if (!drm_core_check_feature(dev, DRIVER_SG))
83 return -EINVAL; 79 return -EINVAL;
84 80
85 if ( dev->sg ) 81 if (dev->sg)
86 return -EINVAL; 82 return -EINVAL;
87 83
88 if ( copy_from_user( &request, argp, sizeof(request) ) ) 84 if (copy_from_user(&request, argp, sizeof(request)))
89 return -EFAULT; 85 return -EFAULT;
90 86
91 entry = drm_alloc( sizeof(*entry), DRM_MEM_SGLISTS ); 87 entry = drm_alloc(sizeof(*entry), DRM_MEM_SGLISTS);
92 if ( !entry ) 88 if (!entry)
93 return -ENOMEM; 89 return -ENOMEM;
94 90
95 memset( entry, 0, sizeof(*entry) ); 91 memset(entry, 0, sizeof(*entry));
96 92
97 pages = (request.size + PAGE_SIZE - 1) / PAGE_SIZE; 93 pages = (request.size + PAGE_SIZE - 1) / PAGE_SIZE;
98 DRM_DEBUG( "sg size=%ld pages=%ld\n", request.size, pages ); 94 DRM_DEBUG("sg size=%ld pages=%ld\n", request.size, pages);
99 95
100 entry->pages = pages; 96 entry->pages = pages;
101 entry->pagelist = drm_alloc( pages * sizeof(*entry->pagelist), 97 entry->pagelist = drm_alloc(pages * sizeof(*entry->pagelist),
102 DRM_MEM_PAGES ); 98 DRM_MEM_PAGES);
103 if ( !entry->pagelist ) { 99 if (!entry->pagelist) {
104 drm_free( entry, sizeof(*entry), DRM_MEM_SGLISTS ); 100 drm_free(entry, sizeof(*entry), DRM_MEM_SGLISTS);
105 return -ENOMEM; 101 return -ENOMEM;
106 } 102 }
107 103
108 memset(entry->pagelist, 0, pages * sizeof(*entry->pagelist)); 104 memset(entry->pagelist, 0, pages * sizeof(*entry->pagelist));
109 105
110 entry->busaddr = drm_alloc( pages * sizeof(*entry->busaddr), 106 entry->busaddr = drm_alloc(pages * sizeof(*entry->busaddr),
111 DRM_MEM_PAGES ); 107 DRM_MEM_PAGES);
112 if ( !entry->busaddr ) { 108 if (!entry->busaddr) {
113 drm_free( entry->pagelist, 109 drm_free(entry->pagelist,
114 entry->pages * sizeof(*entry->pagelist), 110 entry->pages * sizeof(*entry->pagelist),
115 DRM_MEM_PAGES ); 111 DRM_MEM_PAGES);
116 drm_free( entry, 112 drm_free(entry, sizeof(*entry), DRM_MEM_SGLISTS);
117 sizeof(*entry),
118 DRM_MEM_SGLISTS );
119 return -ENOMEM; 113 return -ENOMEM;
120 } 114 }
121 memset( (void *)entry->busaddr, 0, pages * sizeof(*entry->busaddr) ); 115 memset((void *)entry->busaddr, 0, pages * sizeof(*entry->busaddr));
122 116
123 entry->virtual = vmalloc_32( pages << PAGE_SHIFT ); 117 entry->virtual = vmalloc_32(pages << PAGE_SHIFT);
124 if ( !entry->virtual ) { 118 if (!entry->virtual) {
125 drm_free( entry->busaddr, 119 drm_free(entry->busaddr,
126 entry->pages * sizeof(*entry->busaddr), 120 entry->pages * sizeof(*entry->busaddr), DRM_MEM_PAGES);
127 DRM_MEM_PAGES ); 121 drm_free(entry->pagelist,
128 drm_free( entry->pagelist, 122 entry->pages * sizeof(*entry->pagelist),
129 entry->pages * sizeof(*entry->pagelist), 123 DRM_MEM_PAGES);
130 DRM_MEM_PAGES ); 124 drm_free(entry, sizeof(*entry), DRM_MEM_SGLISTS);
131 drm_free( entry,
132 sizeof(*entry),
133 DRM_MEM_SGLISTS );
134 return -ENOMEM; 125 return -ENOMEM;
135 } 126 }
136 127
137 /* This also forces the mapping of COW pages, so our page list 128 /* This also forces the mapping of COW pages, so our page list
138 * will be valid. Please don't remove it... 129 * will be valid. Please don't remove it...
139 */ 130 */
140 memset( entry->virtual, 0, pages << PAGE_SHIFT ); 131 memset(entry->virtual, 0, pages << PAGE_SHIFT);
141 132
142 entry->handle = ScatterHandle((unsigned long)entry->virtual); 133 entry->handle = ScatterHandle((unsigned long)entry->virtual);
143 134
144 DRM_DEBUG( "sg alloc handle = %08lx\n", entry->handle ); 135 DRM_DEBUG("sg alloc handle = %08lx\n", entry->handle);
145 DRM_DEBUG( "sg alloc virtual = %p\n", entry->virtual ); 136 DRM_DEBUG("sg alloc virtual = %p\n", entry->virtual);
146 137
147 for (i = (unsigned long)entry->virtual, j = 0; j < pages; 138 for (i = (unsigned long)entry->virtual, j = 0; j < pages;
148 i += PAGE_SIZE, j++) { 139 i += PAGE_SIZE, j++) {
149 entry->pagelist[j] = vmalloc_to_page((void *)i); 140 entry->pagelist[j] = vmalloc_to_page((void *)i);
150 if (!entry->pagelist[j]) 141 if (!entry->pagelist[j])
151 goto failed; 142 goto failed;
@@ -154,8 +145,8 @@ int drm_sg_alloc( struct inode *inode, struct file *filp,
154 145
155 request.handle = entry->handle; 146 request.handle = entry->handle;
156 147
157 if ( copy_to_user( argp, &request, sizeof(request) ) ) { 148 if (copy_to_user(argp, &request, sizeof(request))) {
158 drm_sg_cleanup( entry ); 149 drm_sg_cleanup(entry);
159 return -EFAULT; 150 return -EFAULT;
160 } 151 }
161 152
@@ -166,50 +157,50 @@ int drm_sg_alloc( struct inode *inode, struct file *filp,
166 * versa. 157 * versa.
167 */ 158 */
168 { 159 {
169 int error = 0; 160 int error = 0;
170 161
171 for ( i = 0 ; i < pages ; i++ ) { 162 for (i = 0; i < pages; i++) {
172 unsigned long *tmp; 163 unsigned long *tmp;
173 164
174 tmp = page_address( entry->pagelist[i] ); 165 tmp = page_address(entry->pagelist[i]);
175 for ( j = 0 ; 166 for (j = 0;
176 j < PAGE_SIZE / sizeof(unsigned long) ; 167 j < PAGE_SIZE / sizeof(unsigned long);
177 j++, tmp++ ) { 168 j++, tmp++) {
178 *tmp = 0xcafebabe; 169 *tmp = 0xcafebabe;
179 } 170 }
180 tmp = (unsigned long *)((u8 *)entry->virtual + 171 tmp = (unsigned long *)((u8 *) entry->virtual +
181 (PAGE_SIZE * i)); 172 (PAGE_SIZE * i));
182 for( j = 0 ; 173 for (j = 0;
183 j < PAGE_SIZE / sizeof(unsigned long) ; 174 j < PAGE_SIZE / sizeof(unsigned long);
184 j++, tmp++ ) { 175 j++, tmp++) {
185 if ( *tmp != 0xcafebabe && error == 0 ) { 176 if (*tmp != 0xcafebabe && error == 0) {
186 error = 1; 177 error = 1;
187 DRM_ERROR( "Scatter allocation error, " 178 DRM_ERROR("Scatter allocation error, "
188 "pagelist does not match " 179 "pagelist does not match "
189 "virtual mapping\n" ); 180 "virtual mapping\n");
181 }
182 }
183 tmp = page_address(entry->pagelist[i]);
184 for (j = 0;
185 j < PAGE_SIZE / sizeof(unsigned long);
186 j++, tmp++) {
187 *tmp = 0;
190 } 188 }
191 } 189 }
192 tmp = page_address( entry->pagelist[i] ); 190 if (error == 0)
193 for(j = 0 ; 191 DRM_ERROR("Scatter allocation matches pagelist\n");
194 j < PAGE_SIZE / sizeof(unsigned long) ;
195 j++, tmp++) {
196 *tmp = 0;
197 }
198 }
199 if (error == 0)
200 DRM_ERROR( "Scatter allocation matches pagelist\n" );
201 } 192 }
202#endif 193#endif
203 194
204 return 0; 195 return 0;
205 196
206 failed: 197 failed:
207 drm_sg_cleanup( entry ); 198 drm_sg_cleanup(entry);
208 return -ENOMEM; 199 return -ENOMEM;
209} 200}
210 201
211int drm_sg_free( struct inode *inode, struct file *filp, 202int drm_sg_free(struct inode *inode, struct file *filp,
212 unsigned int cmd, unsigned long arg ) 203 unsigned int cmd, unsigned long arg)
213{ 204{
214 drm_file_t *priv = filp->private_data; 205 drm_file_t *priv = filp->private_data;
215 drm_device_t *dev = priv->head->dev; 206 drm_device_t *dev = priv->head->dev;
@@ -219,20 +210,20 @@ int drm_sg_free( struct inode *inode, struct file *filp,
219 if (!drm_core_check_feature(dev, DRIVER_SG)) 210 if (!drm_core_check_feature(dev, DRIVER_SG))
220 return -EINVAL; 211 return -EINVAL;
221 212
222 if ( copy_from_user( &request, 213 if (copy_from_user(&request,
223 (drm_scatter_gather_t __user *)arg, 214 (drm_scatter_gather_t __user *) arg,
224 sizeof(request) ) ) 215 sizeof(request)))
225 return -EFAULT; 216 return -EFAULT;
226 217
227 entry = dev->sg; 218 entry = dev->sg;
228 dev->sg = NULL; 219 dev->sg = NULL;
229 220
230 if ( !entry || entry->handle != request.handle ) 221 if (!entry || entry->handle != request.handle)
231 return -EINVAL; 222 return -EINVAL;
232 223
233 DRM_DEBUG( "sg free virtual = %p\n", entry->virtual ); 224 DRM_DEBUG("sg free virtual = %p\n", entry->virtual);
234 225
235 drm_sg_cleanup( entry ); 226 drm_sg_cleanup(entry);
236 227
237 return 0; 228 return 0;
238} 229}
diff --git a/drivers/char/drm/drm_stub.c b/drivers/char/drm/drm_stub.c
index 95a976c96eb8..7cb7234d6288 100644
--- a/drivers/char/drm/drm_stub.c
+++ b/drivers/char/drm/drm_stub.c
@@ -37,11 +37,11 @@
37#include "drm_core.h" 37#include "drm_core.h"
38 38
39unsigned int drm_cards_limit = 16; /* Enough for one machine */ 39unsigned int drm_cards_limit = 16; /* Enough for one machine */
40unsigned int drm_debug = 0; /* 1 to enable debug output */ 40unsigned int drm_debug = 0; /* 1 to enable debug output */
41EXPORT_SYMBOL(drm_debug); 41EXPORT_SYMBOL(drm_debug);
42 42
43MODULE_AUTHOR( CORE_AUTHOR ); 43MODULE_AUTHOR(CORE_AUTHOR);
44MODULE_DESCRIPTION( CORE_DESC ); 44MODULE_DESCRIPTION(CORE_DESC);
45MODULE_LICENSE("GPL and additional rights"); 45MODULE_LICENSE("GPL and additional rights");
46MODULE_PARM_DESC(cards_limit, "Maximum number of graphics cards"); 46MODULE_PARM_DESC(cards_limit, "Maximum number of graphics cards");
47MODULE_PARM_DESC(debug, "Enable debug output"); 47MODULE_PARM_DESC(debug, "Enable debug output");
@@ -53,19 +53,21 @@ drm_head_t **drm_heads;
53struct drm_sysfs_class *drm_class; 53struct drm_sysfs_class *drm_class;
54struct proc_dir_entry *drm_proc_root; 54struct proc_dir_entry *drm_proc_root;
55 55
56static int drm_fill_in_dev(drm_device_t *dev, struct pci_dev *pdev, const struct pci_device_id *ent, struct drm_driver *driver) 56static int drm_fill_in_dev(drm_device_t * dev, struct pci_dev *pdev,
57 const struct pci_device_id *ent,
58 struct drm_driver *driver)
57{ 59{
58 int retcode; 60 int retcode;
59 61
60 spin_lock_init(&dev->count_lock); 62 spin_lock_init(&dev->count_lock);
61 init_timer( &dev->timer ); 63 init_timer(&dev->timer);
62 sema_init( &dev->struct_sem, 1 ); 64 sema_init(&dev->struct_sem, 1);
63 sema_init( &dev->ctxlist_sem, 1 ); 65 sema_init(&dev->ctxlist_sem, 1);
64 66
65 dev->pdev = pdev; 67 dev->pdev = pdev;
66 68
67#ifdef __alpha__ 69#ifdef __alpha__
68 dev->hose = pdev->sysdata; 70 dev->hose = pdev->sysdata;
69 dev->pci_domain = dev->hose->bus->number; 71 dev->pci_domain = dev->hose->bus->number;
70#else 72#else
71 dev->pci_domain = 0; 73 dev->pci_domain = 0;
@@ -82,15 +84,15 @@ static int drm_fill_in_dev(drm_device_t *dev, struct pci_dev *pdev, const struct
82 84
83 /* the DRM has 6 basic counters */ 85 /* the DRM has 6 basic counters */
84 dev->counters = 6; 86 dev->counters = 6;
85 dev->types[0] = _DRM_STAT_LOCK; 87 dev->types[0] = _DRM_STAT_LOCK;
86 dev->types[1] = _DRM_STAT_OPENS; 88 dev->types[1] = _DRM_STAT_OPENS;
87 dev->types[2] = _DRM_STAT_CLOSES; 89 dev->types[2] = _DRM_STAT_CLOSES;
88 dev->types[3] = _DRM_STAT_IOCTLS; 90 dev->types[3] = _DRM_STAT_IOCTLS;
89 dev->types[4] = _DRM_STAT_LOCKS; 91 dev->types[4] = _DRM_STAT_LOCKS;
90 dev->types[5] = _DRM_STAT_UNLOCKS; 92 dev->types[5] = _DRM_STAT_UNLOCKS;
91 93
92 dev->driver = driver; 94 dev->driver = driver;
93 95
94 if (dev->driver->preinit) 96 if (dev->driver->preinit)
95 if ((retcode = dev->driver->preinit(dev, ent->driver_data))) 97 if ((retcode = dev->driver->preinit(dev, ent->driver_data)))
96 goto error_out_unreg; 98 goto error_out_unreg;
@@ -98,29 +100,30 @@ static int drm_fill_in_dev(drm_device_t *dev, struct pci_dev *pdev, const struct
98 if (drm_core_has_AGP(dev)) { 100 if (drm_core_has_AGP(dev)) {
99 if (drm_device_is_agp(dev)) 101 if (drm_device_is_agp(dev))
100 dev->agp = drm_agp_init(dev); 102 dev->agp = drm_agp_init(dev);
101 if (drm_core_check_feature(dev, DRIVER_REQUIRE_AGP) && (dev->agp == NULL)) { 103 if (drm_core_check_feature(dev, DRIVER_REQUIRE_AGP)
102 DRM_ERROR( "Cannot initialize the agpgart module.\n" ); 104 && (dev->agp == NULL)) {
105 DRM_ERROR("Cannot initialize the agpgart module.\n");
103 retcode = -EINVAL; 106 retcode = -EINVAL;
104 goto error_out_unreg; 107 goto error_out_unreg;
105 } 108 }
106 if (drm_core_has_MTRR(dev)) { 109 if (drm_core_has_MTRR(dev)) {
107 if (dev->agp) 110 if (dev->agp)
108 dev->agp->agp_mtrr = mtrr_add( dev->agp->agp_info.aper_base, 111 dev->agp->agp_mtrr =
109 dev->agp->agp_info.aper_size*1024*1024, 112 mtrr_add(dev->agp->agp_info.aper_base,
110 MTRR_TYPE_WRCOMB, 113 dev->agp->agp_info.aper_size *
111 1 ); 114 1024 * 1024, MTRR_TYPE_WRCOMB, 1);
112 } 115 }
113 } 116 }
114 117
115 retcode = drm_ctxbitmap_init( dev ); 118 retcode = drm_ctxbitmap_init(dev);
116 if( retcode ) { 119 if (retcode) {
117 DRM_ERROR( "Cannot allocate memory for context bitmap.\n" ); 120 DRM_ERROR("Cannot allocate memory for context bitmap.\n");
118 goto error_out_unreg; 121 goto error_out_unreg;
119 } 122 }
120 123
121 return 0; 124 return 0;
122 125
123error_out_unreg: 126 error_out_unreg:
124 drm_takedown(dev); 127 drm_takedown(dev);
125 return retcode; 128 return retcode;
126} 129}
@@ -140,7 +143,7 @@ int drm_stub_open(struct inode *inode, struct file *filp)
140 int minor = iminor(inode); 143 int minor = iminor(inode);
141 int err = -ENODEV; 144 int err = -ENODEV;
142 struct file_operations *old_fops; 145 struct file_operations *old_fops;
143 146
144 DRM_DEBUG("\n"); 147 DRM_DEBUG("\n");
145 148
146 if (!((minor >= 0) && (minor < drm_cards_limit))) 149 if (!((minor >= 0) && (minor < drm_cards_limit)))
@@ -148,7 +151,7 @@ int drm_stub_open(struct inode *inode, struct file *filp)
148 151
149 if (!drm_heads[minor]) 152 if (!drm_heads[minor])
150 return -ENODEV; 153 return -ENODEV;
151 154
152 if (!(dev = drm_heads[minor]->dev)) 155 if (!(dev = drm_heads[minor]->dev))
153 return -ENODEV; 156 return -ENODEV;
154 157
@@ -174,7 +177,7 @@ int drm_stub_open(struct inode *inode, struct file *filp)
174 * create the proc init entry via proc_init(). This routines assigns 177 * create the proc init entry via proc_init(). This routines assigns
175 * minor numbers to secondary heads of multi-headed cards 178 * minor numbers to secondary heads of multi-headed cards
176 */ 179 */
177static int drm_get_head(drm_device_t *dev, drm_head_t *head) 180static int drm_get_head(drm_device_t * dev, drm_head_t * head)
178{ 181{
179 drm_head_t **heads = drm_heads; 182 drm_head_t **heads = drm_heads;
180 int ret; 183 int ret;
@@ -184,26 +187,27 @@ static int drm_get_head(drm_device_t *dev, drm_head_t *head)
184 187
185 for (minor = 0; minor < drm_cards_limit; minor++, heads++) { 188 for (minor = 0; minor < drm_cards_limit; minor++, heads++) {
186 if (!*heads) { 189 if (!*heads) {
187 190
188 *head = (drm_head_t) { 191 *head = (drm_head_t) {
189 .dev = dev, 192 .dev = dev,.device =
190 .device = MKDEV(DRM_MAJOR, minor), 193 MKDEV(DRM_MAJOR, minor),.minor = minor,};
191 .minor = minor, 194
192 }; 195 if ((ret =
193 196 drm_proc_init(dev, minor, drm_proc_root,
194 if ((ret = drm_proc_init(dev, minor, drm_proc_root, &head->dev_root))) { 197 &head->dev_root))) {
195 printk (KERN_ERR "DRM: Failed to initialize /proc/dri.\n"); 198 printk(KERN_ERR
199 "DRM: Failed to initialize /proc/dri.\n");
196 goto err_g1; 200 goto err_g1;
197 } 201 }
198 202
199
200 head->dev_class = drm_sysfs_device_add(drm_class, 203 head->dev_class = drm_sysfs_device_add(drm_class,
201 MKDEV(DRM_MAJOR, 204 MKDEV(DRM_MAJOR,
202 minor), 205 minor),
203 &dev->pdev->dev, 206 &dev->pdev->dev,
204 "card%d", minor); 207 "card%d", minor);
205 if (IS_ERR(head->dev_class)) { 208 if (IS_ERR(head->dev_class)) {
206 printk(KERN_ERR "DRM: Error sysfs_device_add.\n"); 209 printk(KERN_ERR
210 "DRM: Error sysfs_device_add.\n");
207 ret = PTR_ERR(head->dev_class); 211 ret = PTR_ERR(head->dev_class);
208 goto err_g2; 212 goto err_g2;
209 } 213 }
@@ -215,13 +219,14 @@ static int drm_get_head(drm_device_t *dev, drm_head_t *head)
215 } 219 }
216 DRM_ERROR("out of minors\n"); 220 DRM_ERROR("out of minors\n");
217 return -ENOMEM; 221 return -ENOMEM;
218err_g2: 222 err_g2:
219 drm_proc_cleanup(minor, drm_proc_root, head->dev_root); 223 drm_proc_cleanup(minor, drm_proc_root, head->dev_root);
220err_g1: 224 err_g1:
221 *head = (drm_head_t) {.dev = NULL}; 225 *head = (drm_head_t) {
226 .dev = NULL};
222 return ret; 227 return ret;
223} 228}
224 229
225/** 230/**
226 * Register. 231 * Register.
227 * 232 *
@@ -234,7 +239,7 @@ err_g1:
234 * Try and register, if we fail to register, backout previous work. 239 * Try and register, if we fail to register, backout previous work.
235 */ 240 */
236int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent, 241int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
237 struct drm_driver *driver) 242 struct drm_driver *driver)
238{ 243{
239 drm_device_t *dev; 244 drm_device_t *dev;
240 int ret; 245 int ret;
@@ -261,10 +266,11 @@ int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
261 266
262 return 0; 267 return 0;
263 268
264err_g1: 269 err_g1:
265 drm_free(dev, sizeof(*dev), DRM_MEM_STUB); 270 drm_free(dev, sizeof(*dev), DRM_MEM_STUB);
266 return ret; 271 return ret;
267} 272}
273
268EXPORT_SYMBOL(drm_get_dev); 274EXPORT_SYMBOL(drm_get_dev);
269 275
270/** 276/**
@@ -305,19 +311,19 @@ int drm_put_dev(drm_device_t * dev)
305 * last minor released. 311 * last minor released.
306 * 312 *
307 */ 313 */
308int drm_put_head(drm_head_t *head) 314int drm_put_head(drm_head_t * head)
309{ 315{
310 int minor = head->minor; 316 int minor = head->minor;
311 317
312 DRM_DEBUG("release secondary minor %d\n", minor); 318 DRM_DEBUG("release secondary minor %d\n", minor);
313 319
314 drm_proc_cleanup(minor, drm_proc_root, head->dev_root); 320 drm_proc_cleanup(minor, drm_proc_root, head->dev_root);
315 drm_sysfs_device_remove(MKDEV(DRM_MAJOR, head->minor)); 321 drm_sysfs_device_remove(MKDEV(DRM_MAJOR, head->minor));
316 322
317 *head = (drm_head_t){.dev = NULL}; 323 *head = (drm_head_t) {
324 .dev = NULL};
318 325
319 drm_heads[minor] = NULL; 326 drm_heads[minor] = NULL;
320 327
321 return 0; 328 return 0;
322} 329}
323
diff --git a/drivers/char/drm/drm_vm.c b/drivers/char/drm/drm_vm.c
index a13d07f44202..e84a7876a1b3 100644
--- a/drivers/char/drm/drm_vm.c
+++ b/drivers/char/drm/drm_vm.c
@@ -1,7 +1,7 @@
1/** 1/**
2 * \file drm_vm.h 2 * \file drm_vm.c
3 * Memory mapping for DRM 3 * Memory mapping for DRM
4 * 4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
6 * \author Gareth Hughes <gareth@valinux.com> 6 * \author Gareth Hughes <gareth@valinux.com>
7 */ 7 */
@@ -47,32 +47,34 @@ static void drm_vm_close(struct vm_area_struct *vma);
47 * \param vma virtual memory area. 47 * \param vma virtual memory area.
48 * \param address access address. 48 * \param address access address.
49 * \return pointer to the page structure. 49 * \return pointer to the page structure.
50 * 50 *
51 * Find the right map and if it's AGP memory find the real physical page to 51 * Find the right map and if it's AGP memory find the real physical page to
52 * map, get the page, increment the use count and return it. 52 * map, get the page, increment the use count and return it.
53 */ 53 */
54#if __OS_HAS_AGP 54#if __OS_HAS_AGP
55static __inline__ struct page *drm_do_vm_nopage(struct vm_area_struct *vma, 55static __inline__ struct page *drm_do_vm_nopage(struct vm_area_struct *vma,
56 unsigned long address) 56 unsigned long address)
57{ 57{
58 drm_file_t *priv = vma->vm_file->private_data; 58 drm_file_t *priv = vma->vm_file->private_data;
59 drm_device_t *dev = priv->head->dev; 59 drm_device_t *dev = priv->head->dev;
60 drm_map_t *map = NULL; 60 drm_map_t *map = NULL;
61 drm_map_list_t *r_list; 61 drm_map_list_t *r_list;
62 struct list_head *list; 62 struct list_head *list;
63 63
64 /* 64 /*
65 * Find the right map 65 * Find the right map
66 */ 66 */
67 if (!drm_core_has_AGP(dev)) 67 if (!drm_core_has_AGP(dev))
68 goto vm_nopage_error; 68 goto vm_nopage_error;
69 69
70 if(!dev->agp || !dev->agp->cant_use_aperture) goto vm_nopage_error; 70 if (!dev->agp || !dev->agp->cant_use_aperture)
71 goto vm_nopage_error;
71 72
72 list_for_each(list, &dev->maplist->head) { 73 list_for_each(list, &dev->maplist->head) {
73 r_list = list_entry(list, drm_map_list_t, head); 74 r_list = list_entry(list, drm_map_list_t, head);
74 map = r_list->map; 75 map = r_list->map;
75 if (!map) continue; 76 if (!map)
77 continue;
76 if (r_list->user_token == VM_OFFSET(vma)) 78 if (r_list->user_token == VM_OFFSET(vma))
77 break; 79 break;
78 } 80 }
@@ -85,45 +87,47 @@ static __inline__ struct page *drm_do_vm_nopage(struct vm_area_struct *vma,
85 87
86#ifdef __alpha__ 88#ifdef __alpha__
87 /* 89 /*
88 * Adjust to a bus-relative address 90 * Adjust to a bus-relative address
89 */ 91 */
90 baddr -= dev->hose->mem_space->start; 92 baddr -= dev->hose->mem_space->start;
91#endif 93#endif
92 94
93 /* 95 /*
94 * It's AGP memory - find the real physical page to map 96 * It's AGP memory - find the real physical page to map
95 */ 97 */
96 for(agpmem = dev->agp->memory; agpmem; agpmem = agpmem->next) { 98 for (agpmem = dev->agp->memory; agpmem; agpmem = agpmem->next) {
97 if (agpmem->bound <= baddr && 99 if (agpmem->bound <= baddr &&
98 agpmem->bound + agpmem->pages * PAGE_SIZE > baddr) 100 agpmem->bound + agpmem->pages * PAGE_SIZE > baddr)
99 break; 101 break;
100 } 102 }
101 103
102 if (!agpmem) goto vm_nopage_error; 104 if (!agpmem)
105 goto vm_nopage_error;
103 106
104 /* 107 /*
105 * Get the page, inc the use count, and return it 108 * Get the page, inc the use count, and return it
106 */ 109 */
107 offset = (baddr - agpmem->bound) >> PAGE_SHIFT; 110 offset = (baddr - agpmem->bound) >> PAGE_SHIFT;
108 page = virt_to_page(__va(agpmem->memory->memory[offset])); 111 page = virt_to_page(__va(agpmem->memory->memory[offset]));
109 get_page(page); 112 get_page(page);
110 113
111 DRM_DEBUG("baddr = 0x%lx page = 0x%p, offset = 0x%lx, count=%d\n", 114 DRM_DEBUG
112 baddr, __va(agpmem->memory->memory[offset]), offset, 115 ("baddr = 0x%lx page = 0x%p, offset = 0x%lx, count=%d\n",
113 page_count(page)); 116 baddr, __va(agpmem->memory->memory[offset]), offset,
117 page_count(page));
114 118
115 return page; 119 return page;
116 } 120 }
117vm_nopage_error: 121 vm_nopage_error:
118 return NOPAGE_SIGBUS; /* Disallow mremap */ 122 return NOPAGE_SIGBUS; /* Disallow mremap */
119} 123}
120#else /* __OS_HAS_AGP */ 124#else /* __OS_HAS_AGP */
121static __inline__ struct page *drm_do_vm_nopage(struct vm_area_struct *vma, 125static __inline__ struct page *drm_do_vm_nopage(struct vm_area_struct *vma,
122 unsigned long address) 126 unsigned long address)
123{ 127{
124 return NOPAGE_SIGBUS; 128 return NOPAGE_SIGBUS;
125} 129}
126#endif /* __OS_HAS_AGP */ 130#endif /* __OS_HAS_AGP */
127 131
128/** 132/**
129 * \c nopage method for shared virtual memory. 133 * \c nopage method for shared virtual memory.
@@ -131,25 +135,27 @@ static __inline__ struct page *drm_do_vm_nopage(struct vm_area_struct *vma,
131 * \param vma virtual memory area. 135 * \param vma virtual memory area.
132 * \param address access address. 136 * \param address access address.
133 * \return pointer to the page structure. 137 * \return pointer to the page structure.
134 * 138 *
135 * Get the the mapping, find the real physical page to map, get the page, and 139 * Get the the mapping, find the real physical page to map, get the page, and
136 * return it. 140 * return it.
137 */ 141 */
138static __inline__ struct page *drm_do_vm_shm_nopage(struct vm_area_struct *vma, 142static __inline__ struct page *drm_do_vm_shm_nopage(struct vm_area_struct *vma,
139 unsigned long address) 143 unsigned long address)
140{ 144{
141 drm_map_t *map = (drm_map_t *)vma->vm_private_data; 145 drm_map_t *map = (drm_map_t *) vma->vm_private_data;
142 unsigned long offset; 146 unsigned long offset;
143 unsigned long i; 147 unsigned long i;
144 struct page *page; 148 struct page *page;
145 149
146 if (address > vma->vm_end) return NOPAGE_SIGBUS; /* Disallow mremap */ 150 if (address > vma->vm_end)
147 if (!map) return NOPAGE_OOM; /* Nothing allocated */ 151 return NOPAGE_SIGBUS; /* Disallow mremap */
152 if (!map)
153 return NOPAGE_OOM; /* Nothing allocated */
148 154
149 offset = address - vma->vm_start; 155 offset = address - vma->vm_start;
150 i = (unsigned long)map->handle + offset; 156 i = (unsigned long)map->handle + offset;
151 page = (map->type == _DRM_CONSISTENT) ? 157 page = (map->type == _DRM_CONSISTENT) ?
152 virt_to_page((void *)i) : vmalloc_to_page((void *)i); 158 virt_to_page((void *)i) : vmalloc_to_page((void *)i);
153 if (!page) 159 if (!page)
154 return NOPAGE_OOM; 160 return NOPAGE_OOM;
155 get_page(page); 161 get_page(page);
@@ -158,19 +164,18 @@ static __inline__ struct page *drm_do_vm_shm_nopage(struct vm_area_struct *vma,
158 return page; 164 return page;
159} 165}
160 166
161
162/** 167/**
163 * \c close method for shared virtual memory. 168 * \c close method for shared virtual memory.
164 * 169 *
165 * \param vma virtual memory area. 170 * \param vma virtual memory area.
166 * 171 *
167 * Deletes map information if we are the last 172 * Deletes map information if we are the last
168 * person to close a mapping and it's not in the global maplist. 173 * person to close a mapping and it's not in the global maplist.
169 */ 174 */
170static void drm_vm_shm_close(struct vm_area_struct *vma) 175static void drm_vm_shm_close(struct vm_area_struct *vma)
171{ 176{
172 drm_file_t *priv = vma->vm_file->private_data; 177 drm_file_t *priv = vma->vm_file->private_data;
173 drm_device_t *dev = priv->head->dev; 178 drm_device_t *dev = priv->head->dev;
174 drm_vma_entry_t *pt, *prev, *next; 179 drm_vma_entry_t *pt, *prev, *next;
175 drm_map_t *map; 180 drm_map_t *map;
176 drm_map_list_t *r_list; 181 drm_map_list_t *r_list;
@@ -186,7 +191,8 @@ static void drm_vm_shm_close(struct vm_area_struct *vma)
186 down(&dev->struct_sem); 191 down(&dev->struct_sem);
187 for (pt = dev->vmalist, prev = NULL; pt; pt = next) { 192 for (pt = dev->vmalist, prev = NULL; pt; pt = next) {
188 next = pt->next; 193 next = pt->next;
189 if (pt->vma->vm_private_data == map) found_maps++; 194 if (pt->vma->vm_private_data == map)
195 found_maps++;
190 if (pt->vma == vma) { 196 if (pt->vma == vma) {
191 if (prev) { 197 if (prev) {
192 prev->next = pt->next; 198 prev->next = pt->next;
@@ -199,8 +205,7 @@ static void drm_vm_shm_close(struct vm_area_struct *vma)
199 } 205 }
200 } 206 }
201 /* We were the only map that was found */ 207 /* We were the only map that was found */
202 if(found_maps == 1 && 208 if (found_maps == 1 && map->flags & _DRM_REMOVABLE) {
203 map->flags & _DRM_REMOVABLE) {
204 /* Check to see if we are in the maplist, if we are not, then 209 /* Check to see if we are in the maplist, if we are not, then
205 * we delete this mappings information. 210 * we delete this mappings information.
206 */ 211 */
@@ -208,10 +213,11 @@ static void drm_vm_shm_close(struct vm_area_struct *vma)
208 list = &dev->maplist->head; 213 list = &dev->maplist->head;
209 list_for_each(list, &dev->maplist->head) { 214 list_for_each(list, &dev->maplist->head) {
210 r_list = list_entry(list, drm_map_list_t, head); 215 r_list = list_entry(list, drm_map_list_t, head);
211 if (r_list->map == map) found_maps++; 216 if (r_list->map == map)
217 found_maps++;
212 } 218 }
213 219
214 if(!found_maps) { 220 if (!found_maps) {
215 drm_dma_handle_t dmah; 221 drm_dma_handle_t dmah;
216 222
217 switch (map->type) { 223 switch (map->type) {
@@ -251,27 +257,29 @@ static void drm_vm_shm_close(struct vm_area_struct *vma)
251 * \param vma virtual memory area. 257 * \param vma virtual memory area.
252 * \param address access address. 258 * \param address access address.
253 * \return pointer to the page structure. 259 * \return pointer to the page structure.
254 * 260 *
255 * Determine the page number from the page offset and get it from drm_device_dma::pagelist. 261 * Determine the page number from the page offset and get it from drm_device_dma::pagelist.
256 */ 262 */
257static __inline__ struct page *drm_do_vm_dma_nopage(struct vm_area_struct *vma, 263static __inline__ struct page *drm_do_vm_dma_nopage(struct vm_area_struct *vma,
258 unsigned long address) 264 unsigned long address)
259{ 265{
260 drm_file_t *priv = vma->vm_file->private_data; 266 drm_file_t *priv = vma->vm_file->private_data;
261 drm_device_t *dev = priv->head->dev; 267 drm_device_t *dev = priv->head->dev;
262 drm_device_dma_t *dma = dev->dma; 268 drm_device_dma_t *dma = dev->dma;
263 unsigned long offset; 269 unsigned long offset;
264 unsigned long page_nr; 270 unsigned long page_nr;
265 struct page *page; 271 struct page *page;
266 272
267 if (!dma) return NOPAGE_SIGBUS; /* Error */ 273 if (!dma)
268 if (address > vma->vm_end) return NOPAGE_SIGBUS; /* Disallow mremap */ 274 return NOPAGE_SIGBUS; /* Error */
269 if (!dma->pagelist) return NOPAGE_OOM ; /* Nothing allocated */ 275 if (address > vma->vm_end)
270 276 return NOPAGE_SIGBUS; /* Disallow mremap */
271 offset = address - vma->vm_start; /* vm_[pg]off[set] should be 0 */ 277 if (!dma->pagelist)
272 page_nr = offset >> PAGE_SHIFT; 278 return NOPAGE_OOM; /* Nothing allocated */
273 page = virt_to_page((dma->pagelist[page_nr] + 279
274 (offset & (~PAGE_MASK)))); 280 offset = address - vma->vm_start; /* vm_[pg]off[set] should be 0 */
281 page_nr = offset >> PAGE_SHIFT;
282 page = virt_to_page((dma->pagelist[page_nr] + (offset & (~PAGE_MASK))));
275 283
276 get_page(page); 284 get_page(page);
277 285
@@ -285,13 +293,13 @@ static __inline__ struct page *drm_do_vm_dma_nopage(struct vm_area_struct *vma,
285 * \param vma virtual memory area. 293 * \param vma virtual memory area.
286 * \param address access address. 294 * \param address access address.
287 * \return pointer to the page structure. 295 * \return pointer to the page structure.
288 * 296 *
289 * Determine the map offset from the page offset and get it from drm_sg_mem::pagelist. 297 * Determine the map offset from the page offset and get it from drm_sg_mem::pagelist.
290 */ 298 */
291static __inline__ struct page *drm_do_vm_sg_nopage(struct vm_area_struct *vma, 299static __inline__ struct page *drm_do_vm_sg_nopage(struct vm_area_struct *vma,
292 unsigned long address) 300 unsigned long address)
293{ 301{
294 drm_map_t *map = (drm_map_t *)vma->vm_private_data; 302 drm_map_t *map = (drm_map_t *) vma->vm_private_data;
295 drm_file_t *priv = vma->vm_file->private_data; 303 drm_file_t *priv = vma->vm_file->private_data;
296 drm_device_t *dev = priv->head->dev; 304 drm_device_t *dev = priv->head->dev;
297 drm_sg_mem_t *entry = dev->sg; 305 drm_sg_mem_t *entry = dev->sg;
@@ -300,10 +308,12 @@ static __inline__ struct page *drm_do_vm_sg_nopage(struct vm_area_struct *vma,
300 unsigned long page_offset; 308 unsigned long page_offset;
301 struct page *page; 309 struct page *page;
302 310
303 if (!entry) return NOPAGE_SIGBUS; /* Error */ 311 if (!entry)
304 if (address > vma->vm_end) return NOPAGE_SIGBUS; /* Disallow mremap */ 312 return NOPAGE_SIGBUS; /* Error */
305 if (!entry->pagelist) return NOPAGE_OOM ; /* Nothing allocated */ 313 if (address > vma->vm_end)
306 314 return NOPAGE_SIGBUS; /* Disallow mremap */
315 if (!entry->pagelist)
316 return NOPAGE_OOM; /* Nothing allocated */
307 317
308 offset = address - vma->vm_start; 318 offset = address - vma->vm_start;
309 map_offset = map->offset - (unsigned long)dev->sg->virtual; 319 map_offset = map->offset - (unsigned long)dev->sg->virtual;
@@ -314,76 +324,78 @@ static __inline__ struct page *drm_do_vm_sg_nopage(struct vm_area_struct *vma,
314 return page; 324 return page;
315} 325}
316 326
317
318static struct page *drm_vm_nopage(struct vm_area_struct *vma, 327static struct page *drm_vm_nopage(struct vm_area_struct *vma,
319 unsigned long address, 328 unsigned long address, int *type)
320 int *type) { 329{
321 if (type) *type = VM_FAULT_MINOR; 330 if (type)
331 *type = VM_FAULT_MINOR;
322 return drm_do_vm_nopage(vma, address); 332 return drm_do_vm_nopage(vma, address);
323} 333}
324 334
325static struct page *drm_vm_shm_nopage(struct vm_area_struct *vma, 335static struct page *drm_vm_shm_nopage(struct vm_area_struct *vma,
326 unsigned long address, 336 unsigned long address, int *type)
327 int *type) { 337{
328 if (type) *type = VM_FAULT_MINOR; 338 if (type)
339 *type = VM_FAULT_MINOR;
329 return drm_do_vm_shm_nopage(vma, address); 340 return drm_do_vm_shm_nopage(vma, address);
330} 341}
331 342
332static struct page *drm_vm_dma_nopage(struct vm_area_struct *vma, 343static struct page *drm_vm_dma_nopage(struct vm_area_struct *vma,
333 unsigned long address, 344 unsigned long address, int *type)
334 int *type) { 345{
335 if (type) *type = VM_FAULT_MINOR; 346 if (type)
347 *type = VM_FAULT_MINOR;
336 return drm_do_vm_dma_nopage(vma, address); 348 return drm_do_vm_dma_nopage(vma, address);
337} 349}
338 350
339static struct page *drm_vm_sg_nopage(struct vm_area_struct *vma, 351static struct page *drm_vm_sg_nopage(struct vm_area_struct *vma,
340 unsigned long address, 352 unsigned long address, int *type)
341 int *type) { 353{
342 if (type) *type = VM_FAULT_MINOR; 354 if (type)
355 *type = VM_FAULT_MINOR;
343 return drm_do_vm_sg_nopage(vma, address); 356 return drm_do_vm_sg_nopage(vma, address);
344} 357}
345 358
346/** AGP virtual memory operations */ 359/** AGP virtual memory operations */
347static struct vm_operations_struct drm_vm_ops = { 360static struct vm_operations_struct drm_vm_ops = {
348 .nopage = drm_vm_nopage, 361 .nopage = drm_vm_nopage,
349 .open = drm_vm_open, 362 .open = drm_vm_open,
350 .close = drm_vm_close, 363 .close = drm_vm_close,
351}; 364};
352 365
353/** Shared virtual memory operations */ 366/** Shared virtual memory operations */
354static struct vm_operations_struct drm_vm_shm_ops = { 367static struct vm_operations_struct drm_vm_shm_ops = {
355 .nopage = drm_vm_shm_nopage, 368 .nopage = drm_vm_shm_nopage,
356 .open = drm_vm_open, 369 .open = drm_vm_open,
357 .close = drm_vm_shm_close, 370 .close = drm_vm_shm_close,
358}; 371};
359 372
360/** DMA virtual memory operations */ 373/** DMA virtual memory operations */
361static struct vm_operations_struct drm_vm_dma_ops = { 374static struct vm_operations_struct drm_vm_dma_ops = {
362 .nopage = drm_vm_dma_nopage, 375 .nopage = drm_vm_dma_nopage,
363 .open = drm_vm_open, 376 .open = drm_vm_open,
364 .close = drm_vm_close, 377 .close = drm_vm_close,
365}; 378};
366 379
367/** Scatter-gather virtual memory operations */ 380/** Scatter-gather virtual memory operations */
368static struct vm_operations_struct drm_vm_sg_ops = { 381static struct vm_operations_struct drm_vm_sg_ops = {
369 .nopage = drm_vm_sg_nopage, 382 .nopage = drm_vm_sg_nopage,
370 .open = drm_vm_open, 383 .open = drm_vm_open,
371 .close = drm_vm_close, 384 .close = drm_vm_close,
372}; 385};
373 386
374
375/** 387/**
376 * \c open method for shared virtual memory. 388 * \c open method for shared virtual memory.
377 * 389 *
378 * \param vma virtual memory area. 390 * \param vma virtual memory area.
379 * 391 *
380 * Create a new drm_vma_entry structure as the \p vma private data entry and 392 * Create a new drm_vma_entry structure as the \p vma private data entry and
381 * add it to drm_device::vmalist. 393 * add it to drm_device::vmalist.
382 */ 394 */
383static void drm_vm_open(struct vm_area_struct *vma) 395static void drm_vm_open(struct vm_area_struct *vma)
384{ 396{
385 drm_file_t *priv = vma->vm_file->private_data; 397 drm_file_t *priv = vma->vm_file->private_data;
386 drm_device_t *dev = priv->head->dev; 398 drm_device_t *dev = priv->head->dev;
387 drm_vma_entry_t *vma_entry; 399 drm_vma_entry_t *vma_entry;
388 400
389 DRM_DEBUG("0x%08lx,0x%08lx\n", 401 DRM_DEBUG("0x%08lx,0x%08lx\n",
@@ -393,26 +405,26 @@ static void drm_vm_open(struct vm_area_struct *vma)
393 vma_entry = drm_alloc(sizeof(*vma_entry), DRM_MEM_VMAS); 405 vma_entry = drm_alloc(sizeof(*vma_entry), DRM_MEM_VMAS);
394 if (vma_entry) { 406 if (vma_entry) {
395 down(&dev->struct_sem); 407 down(&dev->struct_sem);
396 vma_entry->vma = vma; 408 vma_entry->vma = vma;
397 vma_entry->next = dev->vmalist; 409 vma_entry->next = dev->vmalist;
398 vma_entry->pid = current->pid; 410 vma_entry->pid = current->pid;
399 dev->vmalist = vma_entry; 411 dev->vmalist = vma_entry;
400 up(&dev->struct_sem); 412 up(&dev->struct_sem);
401 } 413 }
402} 414}
403 415
404/** 416/**
405 * \c close method for all virtual memory types. 417 * \c close method for all virtual memory types.
406 * 418 *
407 * \param vma virtual memory area. 419 * \param vma virtual memory area.
408 * 420 *
409 * Search the \p vma private data entry in drm_device::vmalist, unlink it, and 421 * Search the \p vma private data entry in drm_device::vmalist, unlink it, and
410 * free it. 422 * free it.
411 */ 423 */
412static void drm_vm_close(struct vm_area_struct *vma) 424static void drm_vm_close(struct vm_area_struct *vma)
413{ 425{
414 drm_file_t *priv = vma->vm_file->private_data; 426 drm_file_t *priv = vma->vm_file->private_data;
415 drm_device_t *dev = priv->head->dev; 427 drm_device_t *dev = priv->head->dev;
416 drm_vma_entry_t *pt, *prev; 428 drm_vma_entry_t *pt, *prev;
417 429
418 DRM_DEBUG("0x%08lx,0x%08lx\n", 430 DRM_DEBUG("0x%08lx,0x%08lx\n",
@@ -440,43 +452,44 @@ static void drm_vm_close(struct vm_area_struct *vma)
440 * \param filp file pointer. 452 * \param filp file pointer.
441 * \param vma virtual memory area. 453 * \param vma virtual memory area.
442 * \return zero on success or a negative number on failure. 454 * \return zero on success or a negative number on failure.
443 * 455 *
444 * Sets the virtual memory area operations structure to vm_dma_ops, the file 456 * Sets the virtual memory area operations structure to vm_dma_ops, the file
445 * pointer, and calls vm_open(). 457 * pointer, and calls vm_open().
446 */ 458 */
447static int drm_mmap_dma(struct file *filp, struct vm_area_struct *vma) 459static int drm_mmap_dma(struct file *filp, struct vm_area_struct *vma)
448{ 460{
449 drm_file_t *priv = filp->private_data; 461 drm_file_t *priv = filp->private_data;
450 drm_device_t *dev; 462 drm_device_t *dev;
451 drm_device_dma_t *dma; 463 drm_device_dma_t *dma;
452 unsigned long length = vma->vm_end - vma->vm_start; 464 unsigned long length = vma->vm_end - vma->vm_start;
453 465
454 lock_kernel(); 466 lock_kernel();
455 dev = priv->head->dev; 467 dev = priv->head->dev;
456 dma = dev->dma; 468 dma = dev->dma;
457 DRM_DEBUG("start = 0x%lx, end = 0x%lx, offset = 0x%lx\n", 469 DRM_DEBUG("start = 0x%lx, end = 0x%lx, offset = 0x%lx\n",
458 vma->vm_start, vma->vm_end, VM_OFFSET(vma)); 470 vma->vm_start, vma->vm_end, VM_OFFSET(vma));
459 471
460 /* Length must match exact page count */ 472 /* Length must match exact page count */
461 if (!dma || (length >> PAGE_SHIFT) != dma->page_count) { 473 if (!dma || (length >> PAGE_SHIFT) != dma->page_count) {
462 unlock_kernel(); 474 unlock_kernel();
463 return -EINVAL; 475 return -EINVAL;
464 } 476 }
465 unlock_kernel(); 477 unlock_kernel();
466 478
467 vma->vm_ops = &drm_vm_dma_ops; 479 vma->vm_ops = &drm_vm_dma_ops;
468 480
469 vma->vm_flags |= VM_RESERVED; /* Don't swap */ 481 vma->vm_flags |= VM_RESERVED; /* Don't swap */
470 482
471 vma->vm_file = filp; /* Needed for drm_vm_open() */ 483 vma->vm_file = filp; /* Needed for drm_vm_open() */
472 drm_vm_open(vma); 484 drm_vm_open(vma);
473 return 0; 485 return 0;
474} 486}
475 487
476unsigned long drm_core_get_map_ofs(drm_map_t *map) 488unsigned long drm_core_get_map_ofs(drm_map_t * map)
477{ 489{
478 return map->offset; 490 return map->offset;
479} 491}
492
480EXPORT_SYMBOL(drm_core_get_map_ofs); 493EXPORT_SYMBOL(drm_core_get_map_ofs);
481 494
482unsigned long drm_core_get_reg_ofs(struct drm_device *dev) 495unsigned long drm_core_get_reg_ofs(struct drm_device *dev)
@@ -487,6 +500,7 @@ unsigned long drm_core_get_reg_ofs(struct drm_device *dev)
487 return 0; 500 return 0;
488#endif 501#endif
489} 502}
503
490EXPORT_SYMBOL(drm_core_get_reg_ofs); 504EXPORT_SYMBOL(drm_core_get_reg_ofs);
491 505
492/** 506/**
@@ -495,7 +509,7 @@ EXPORT_SYMBOL(drm_core_get_reg_ofs);
495 * \param filp file pointer. 509 * \param filp file pointer.
496 * \param vma virtual memory area. 510 * \param vma virtual memory area.
497 * \return zero on success or a negative number on failure. 511 * \return zero on success or a negative number on failure.
498 * 512 *
499 * If the virtual memory area has no offset associated with it then it's a DMA 513 * If the virtual memory area has no offset associated with it then it's a DMA
500 * area, so calls mmap_dma(). Otherwise searches the map in drm_device::maplist, 514 * area, so calls mmap_dma(). Otherwise searches the map in drm_device::maplist,
501 * checks that the restricted flag is not set, sets the virtual memory operations 515 * checks that the restricted flag is not set, sets the virtual memory operations
@@ -504,17 +518,18 @@ EXPORT_SYMBOL(drm_core_get_reg_ofs);
504 */ 518 */
505int drm_mmap(struct file *filp, struct vm_area_struct *vma) 519int drm_mmap(struct file *filp, struct vm_area_struct *vma)
506{ 520{
507 drm_file_t *priv = filp->private_data; 521 drm_file_t *priv = filp->private_data;
508 drm_device_t *dev = priv->head->dev; 522 drm_device_t *dev = priv->head->dev;
509 drm_map_t *map = NULL; 523 drm_map_t *map = NULL;
510 drm_map_list_t *r_list; 524 drm_map_list_t *r_list;
511 unsigned long offset = 0; 525 unsigned long offset = 0;
512 struct list_head *list; 526 struct list_head *list;
513 527
514 DRM_DEBUG("start = 0x%lx, end = 0x%lx, offset = 0x%lx\n", 528 DRM_DEBUG("start = 0x%lx, end = 0x%lx, offset = 0x%lx\n",
515 vma->vm_start, vma->vm_end, VM_OFFSET(vma)); 529 vma->vm_start, vma->vm_end, VM_OFFSET(vma));
516 530
517 if ( !priv->authenticated ) return -EACCES; 531 if (!priv->authenticated)
532 return -EACCES;
518 533
519 /* We check for "dma". On Apple's UniNorth, it's valid to have 534 /* We check for "dma". On Apple's UniNorth, it's valid to have
520 * the AGP mapped at physical address 0 535 * the AGP mapped at physical address 0
@@ -522,61 +537,66 @@ int drm_mmap(struct file *filp, struct vm_area_struct *vma)
522 */ 537 */
523 if (!VM_OFFSET(vma) 538 if (!VM_OFFSET(vma)
524#if __OS_HAS_AGP 539#if __OS_HAS_AGP
525 && (!dev->agp || dev->agp->agp_info.device->vendor != PCI_VENDOR_ID_APPLE) 540 && (!dev->agp
541 || dev->agp->agp_info.device->vendor != PCI_VENDOR_ID_APPLE)
526#endif 542#endif
527 ) 543 )
528 return drm_mmap_dma(filp, vma); 544 return drm_mmap_dma(filp, vma);
529 545
530 /* A sequential search of a linked list is 546 /* A sequential search of a linked list is
531 fine here because: 1) there will only be 547 fine here because: 1) there will only be
532 about 5-10 entries in the list and, 2) a 548 about 5-10 entries in the list and, 2) a
533 DRI client only has to do this mapping 549 DRI client only has to do this mapping
534 once, so it doesn't have to be optimized 550 once, so it doesn't have to be optimized
535 for performance, even if the list was a 551 for performance, even if the list was a
536 bit longer. */ 552 bit longer. */
537 list_for_each(list, &dev->maplist->head) { 553 list_for_each(list, &dev->maplist->head) {
538 554
539 r_list = list_entry(list, drm_map_list_t, head); 555 r_list = list_entry(list, drm_map_list_t, head);
540 map = r_list->map; 556 map = r_list->map;
541 if (!map) continue; 557 if (!map)
558 continue;
542 if (r_list->user_token == VM_OFFSET(vma)) 559 if (r_list->user_token == VM_OFFSET(vma))
543 break; 560 break;
544 } 561 }
545 562
546 if (!map || ((map->flags&_DRM_RESTRICTED) && !capable(CAP_SYS_ADMIN))) 563 if (!map || ((map->flags & _DRM_RESTRICTED) && !capable(CAP_SYS_ADMIN)))
547 return -EPERM; 564 return -EPERM;
548 565
549 /* Check for valid size. */ 566 /* Check for valid size. */
550 if (map->size != vma->vm_end - vma->vm_start) return -EINVAL; 567 if (map->size != vma->vm_end - vma->vm_start)
568 return -EINVAL;
551 569
552 if (!capable(CAP_SYS_ADMIN) && (map->flags & _DRM_READ_ONLY)) { 570 if (!capable(CAP_SYS_ADMIN) && (map->flags & _DRM_READ_ONLY)) {
553 vma->vm_flags &= ~(VM_WRITE | VM_MAYWRITE); 571 vma->vm_flags &= ~(VM_WRITE | VM_MAYWRITE);
554#if defined(__i386__) || defined(__x86_64__) 572#if defined(__i386__) || defined(__x86_64__)
555 pgprot_val(vma->vm_page_prot) &= ~_PAGE_RW; 573 pgprot_val(vma->vm_page_prot) &= ~_PAGE_RW;
556#else 574#else
557 /* Ye gads this is ugly. With more thought 575 /* Ye gads this is ugly. With more thought
558 we could move this up higher and use 576 we could move this up higher and use
559 `protection_map' instead. */ 577 `protection_map' instead. */
560 vma->vm_page_prot = __pgprot(pte_val(pte_wrprotect( 578 vma->vm_page_prot =
561 __pte(pgprot_val(vma->vm_page_prot))))); 579 __pgprot(pte_val
580 (pte_wrprotect
581 (__pte(pgprot_val(vma->vm_page_prot)))));
562#endif 582#endif
563 } 583 }
564 584
565 switch (map->type) { 585 switch (map->type) {
566 case _DRM_AGP: 586 case _DRM_AGP:
567 if (drm_core_has_AGP(dev) && dev->agp->cant_use_aperture) { 587 if (drm_core_has_AGP(dev) && dev->agp->cant_use_aperture) {
568 /* 588 /*
569 * On some platforms we can't talk to bus dma address from the CPU, so for 589 * On some platforms we can't talk to bus dma address from the CPU, so for
570 * memory of type DRM_AGP, we'll deal with sorting out the real physical 590 * memory of type DRM_AGP, we'll deal with sorting out the real physical
571 * pages and mappings in nopage() 591 * pages and mappings in nopage()
572 */ 592 */
573#if defined(__powerpc__) 593#if defined(__powerpc__)
574 pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE; 594 pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE;
575#endif 595#endif
576 vma->vm_ops = &drm_vm_ops; 596 vma->vm_ops = &drm_vm_ops;
577 break; 597 break;
578 } 598 }
579 /* fall through to _DRM_FRAME_BUFFER... */ 599 /* fall through to _DRM_FRAME_BUFFER... */
580 case _DRM_FRAME_BUFFER: 600 case _DRM_FRAME_BUFFER:
581 case _DRM_REGISTERS: 601 case _DRM_REGISTERS:
582#if defined(__i386__) || defined(__x86_64__) 602#if defined(__i386__) || defined(__x86_64__)
@@ -591,27 +611,25 @@ int drm_mmap(struct file *filp, struct vm_area_struct *vma)
591#endif 611#endif
592 vma->vm_flags |= VM_IO; /* not in core dump */ 612 vma->vm_flags |= VM_IO; /* not in core dump */
593#if defined(__ia64__) 613#if defined(__ia64__)
594 if (efi_range_is_wc(vma->vm_start, vma->vm_end - 614 if (efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start))
595 vma->vm_start))
596 vma->vm_page_prot = 615 vma->vm_page_prot =
597 pgprot_writecombine(vma->vm_page_prot); 616 pgprot_writecombine(vma->vm_page_prot);
598 else 617 else
599 vma->vm_page_prot = 618 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
600 pgprot_noncached(vma->vm_page_prot);
601#endif 619#endif
602 offset = dev->driver->get_reg_ofs(dev); 620 offset = dev->driver->get_reg_ofs(dev);
603#ifdef __sparc__ 621#ifdef __sparc__
604 if (io_remap_pfn_range(DRM_RPR_ARG(vma) vma->vm_start, 622 if (io_remap_pfn_range(DRM_RPR_ARG(vma) vma->vm_start,
605 (map->offset + offset) >> PAGE_SHIFT, 623 (map->offset + offset) >> PAGE_SHIFT,
606 vma->vm_end - vma->vm_start, 624 vma->vm_end - vma->vm_start,
607 vma->vm_page_prot)) 625 vma->vm_page_prot))
608#else 626#else
609 if (io_remap_pfn_range(vma, vma->vm_start, 627 if (io_remap_pfn_range(vma, vma->vm_start,
610 (map->offset + offset) >> PAGE_SHIFT, 628 (map->offset + offset) >> PAGE_SHIFT,
611 vma->vm_end - vma->vm_start, 629 vma->vm_end - vma->vm_start,
612 vma->vm_page_prot)) 630 vma->vm_page_prot))
613#endif 631#endif
614 return -EAGAIN; 632 return -EAGAIN;
615 DRM_DEBUG(" Type = %d; start = 0x%lx, end = 0x%lx," 633 DRM_DEBUG(" Type = %d; start = 0x%lx, end = 0x%lx,"
616 " offset = 0x%lx\n", 634 " offset = 0x%lx\n",
617 map->type, 635 map->type,
@@ -624,22 +642,23 @@ int drm_mmap(struct file *filp, struct vm_area_struct *vma)
624 * allocate in a different way */ 642 * allocate in a different way */
625 vma->vm_ops = &drm_vm_shm_ops; 643 vma->vm_ops = &drm_vm_shm_ops;
626 vma->vm_private_data = (void *)map; 644 vma->vm_private_data = (void *)map;
627 /* Don't let this area swap. Change when 645 /* Don't let this area swap. Change when
628 DRM_KERNEL advisory is supported. */ 646 DRM_KERNEL advisory is supported. */
629 vma->vm_flags |= VM_RESERVED; 647 vma->vm_flags |= VM_RESERVED;
630 break; 648 break;
631 case _DRM_SCATTER_GATHER: 649 case _DRM_SCATTER_GATHER:
632 vma->vm_ops = &drm_vm_sg_ops; 650 vma->vm_ops = &drm_vm_sg_ops;
633 vma->vm_private_data = (void *)map; 651 vma->vm_private_data = (void *)map;
634 vma->vm_flags |= VM_RESERVED; 652 vma->vm_flags |= VM_RESERVED;
635 break; 653 break;
636 default: 654 default:
637 return -EINVAL; /* This should never happen. */ 655 return -EINVAL; /* This should never happen. */
638 } 656 }
639 vma->vm_flags |= VM_RESERVED; /* Don't swap */ 657 vma->vm_flags |= VM_RESERVED; /* Don't swap */
640 658
641 vma->vm_file = filp; /* Needed for drm_vm_open() */ 659 vma->vm_file = filp; /* Needed for drm_vm_open() */
642 drm_vm_open(vma); 660 drm_vm_open(vma);
643 return 0; 661 return 0;
644} 662}
663
645EXPORT_SYMBOL(drm_mmap); 664EXPORT_SYMBOL(drm_mmap);
diff --git a/drivers/char/drm/ffb_context.c b/drivers/char/drm/ffb_context.c
index f51812078010..8a6cc2751bc9 100644
--- a/drivers/char/drm/ffb_context.c
+++ b/drivers/char/drm/ffb_context.c
@@ -15,8 +15,7 @@
15 15
16#include "ffb_drv.h" 16#include "ffb_drv.h"
17 17
18static int DRM(alloc_queue)(drm_device_t *dev, int is_2d_only) 18static int DRM(alloc_queue) (drm_device_t * dev, int is_2d_only) {
19{
20 ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; 19 ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
21 int i; 20 int i;
22 21
@@ -37,7 +36,7 @@ static int DRM(alloc_queue)(drm_device_t *dev, int is_2d_only)
37 return i + 1; 36 return i + 1;
38} 37}
39 38
40static void ffb_save_context(ffb_dev_priv_t *fpriv, int idx) 39static void ffb_save_context(ffb_dev_priv_t * fpriv, int idx)
41{ 40{
42 ffb_fbcPtr ffb = fpriv->regs; 41 ffb_fbcPtr ffb = fpriv->regs;
43 struct ffb_hw_context *ctx; 42 struct ffb_hw_context *ctx;
@@ -94,36 +93,36 @@ static void ffb_save_context(ffb_dev_priv_t *fpriv, int idx)
94 93
95 /* Capture rendering attributes. */ 94 /* Capture rendering attributes. */
96 95
97 ctx->ppc = upa_readl(&ffb->ppc); /* Pixel Processor Control */ 96 ctx->ppc = upa_readl(&ffb->ppc); /* Pixel Processor Control */
98 ctx->wid = upa_readl(&ffb->wid); /* Current WID */ 97 ctx->wid = upa_readl(&ffb->wid); /* Current WID */
99 ctx->fg = upa_readl(&ffb->fg); /* Constant FG color */ 98 ctx->fg = upa_readl(&ffb->fg); /* Constant FG color */
100 ctx->bg = upa_readl(&ffb->bg); /* Constant BG color */ 99 ctx->bg = upa_readl(&ffb->bg); /* Constant BG color */
101 ctx->consty = upa_readl(&ffb->consty); /* Constant Y */ 100 ctx->consty = upa_readl(&ffb->consty); /* Constant Y */
102 ctx->constz = upa_readl(&ffb->constz); /* Constant Z */ 101 ctx->constz = upa_readl(&ffb->constz); /* Constant Z */
103 ctx->xclip = upa_readl(&ffb->xclip); /* X plane clip */ 102 ctx->xclip = upa_readl(&ffb->xclip); /* X plane clip */
104 ctx->dcss = upa_readl(&ffb->dcss); /* Depth Cue Scale Slope */ 103 ctx->dcss = upa_readl(&ffb->dcss); /* Depth Cue Scale Slope */
105 ctx->vclipmin = upa_readl(&ffb->vclipmin); /* Primary XY clip, minimum */ 104 ctx->vclipmin = upa_readl(&ffb->vclipmin); /* Primary XY clip, minimum */
106 ctx->vclipmax = upa_readl(&ffb->vclipmax); /* Primary XY clip, maximum */ 105 ctx->vclipmax = upa_readl(&ffb->vclipmax); /* Primary XY clip, maximum */
107 ctx->vclipzmin = upa_readl(&ffb->vclipzmin); /* Primary Z clip, minimum */ 106 ctx->vclipzmin = upa_readl(&ffb->vclipzmin); /* Primary Z clip, minimum */
108 ctx->vclipzmax = upa_readl(&ffb->vclipzmax); /* Primary Z clip, maximum */ 107 ctx->vclipzmax = upa_readl(&ffb->vclipzmax); /* Primary Z clip, maximum */
109 ctx->dcsf = upa_readl(&ffb->dcsf); /* Depth Cue Scale Front Bound */ 108 ctx->dcsf = upa_readl(&ffb->dcsf); /* Depth Cue Scale Front Bound */
110 ctx->dcsb = upa_readl(&ffb->dcsb); /* Depth Cue Scale Back Bound */ 109 ctx->dcsb = upa_readl(&ffb->dcsb); /* Depth Cue Scale Back Bound */
111 ctx->dczf = upa_readl(&ffb->dczf); /* Depth Cue Scale Z Front */ 110 ctx->dczf = upa_readl(&ffb->dczf); /* Depth Cue Scale Z Front */
112 ctx->dczb = upa_readl(&ffb->dczb); /* Depth Cue Scale Z Back */ 111 ctx->dczb = upa_readl(&ffb->dczb); /* Depth Cue Scale Z Back */
113 ctx->blendc = upa_readl(&ffb->blendc); /* Alpha Blend Control */ 112 ctx->blendc = upa_readl(&ffb->blendc); /* Alpha Blend Control */
114 ctx->blendc1 = upa_readl(&ffb->blendc1); /* Alpha Blend Color 1 */ 113 ctx->blendc1 = upa_readl(&ffb->blendc1); /* Alpha Blend Color 1 */
115 ctx->blendc2 = upa_readl(&ffb->blendc2); /* Alpha Blend Color 2 */ 114 ctx->blendc2 = upa_readl(&ffb->blendc2); /* Alpha Blend Color 2 */
116 ctx->fbc = upa_readl(&ffb->fbc); /* Frame Buffer Control */ 115 ctx->fbc = upa_readl(&ffb->fbc); /* Frame Buffer Control */
117 ctx->rop = upa_readl(&ffb->rop); /* Raster Operation */ 116 ctx->rop = upa_readl(&ffb->rop); /* Raster Operation */
118 ctx->cmp = upa_readl(&ffb->cmp); /* Compare Controls */ 117 ctx->cmp = upa_readl(&ffb->cmp); /* Compare Controls */
119 ctx->matchab = upa_readl(&ffb->matchab); /* Buffer A/B Match Ops */ 118 ctx->matchab = upa_readl(&ffb->matchab); /* Buffer A/B Match Ops */
120 ctx->matchc = upa_readl(&ffb->matchc); /* Buffer C Match Ops */ 119 ctx->matchc = upa_readl(&ffb->matchc); /* Buffer C Match Ops */
121 ctx->magnab = upa_readl(&ffb->magnab); /* Buffer A/B Magnitude Ops */ 120 ctx->magnab = upa_readl(&ffb->magnab); /* Buffer A/B Magnitude Ops */
122 ctx->magnc = upa_readl(&ffb->magnc); /* Buffer C Magnitude Ops */ 121 ctx->magnc = upa_readl(&ffb->magnc); /* Buffer C Magnitude Ops */
123 ctx->pmask = upa_readl(&ffb->pmask); /* RGB Plane Mask */ 122 ctx->pmask = upa_readl(&ffb->pmask); /* RGB Plane Mask */
124 ctx->xpmask = upa_readl(&ffb->xpmask); /* X Plane Mask */ 123 ctx->xpmask = upa_readl(&ffb->xpmask); /* X Plane Mask */
125 ctx->ypmask = upa_readl(&ffb->ypmask); /* Y Plane Mask */ 124 ctx->ypmask = upa_readl(&ffb->ypmask); /* Y Plane Mask */
126 ctx->zpmask = upa_readl(&ffb->zpmask); /* Z Plane Mask */ 125 ctx->zpmask = upa_readl(&ffb->zpmask); /* Z Plane Mask */
127 126
128 /* Auxiliary Clips. */ 127 /* Auxiliary Clips. */
129 ctx->auxclip0min = upa_readl(&ffb->auxclip[0].min); 128 ctx->auxclip0min = upa_readl(&ffb->auxclip[0].min);
@@ -135,9 +134,9 @@ static void ffb_save_context(ffb_dev_priv_t *fpriv, int idx)
135 ctx->auxclip3min = upa_readl(&ffb->auxclip[3].min); 134 ctx->auxclip3min = upa_readl(&ffb->auxclip[3].min);
136 ctx->auxclip3max = upa_readl(&ffb->auxclip[3].max); 135 ctx->auxclip3max = upa_readl(&ffb->auxclip[3].max);
137 136
138 ctx->lpat = upa_readl(&ffb->lpat); /* Line Pattern */ 137 ctx->lpat = upa_readl(&ffb->lpat); /* Line Pattern */
139 ctx->fontxy = upa_readl(&ffb->fontxy); /* XY Font Coordinate */ 138 ctx->fontxy = upa_readl(&ffb->fontxy); /* XY Font Coordinate */
140 ctx->fontw = upa_readl(&ffb->fontw); /* Font Width */ 139 ctx->fontw = upa_readl(&ffb->fontw); /* Font Width */
141 ctx->fontinc = upa_readl(&ffb->fontinc); /* Font X/Y Increment */ 140 ctx->fontinc = upa_readl(&ffb->fontinc); /* Font X/Y Increment */
142 141
143 /* These registers/features only exist on FFB2 and later chips. */ 142 /* These registers/features only exist on FFB2 and later chips. */
@@ -145,12 +144,12 @@ static void ffb_save_context(ffb_dev_priv_t *fpriv, int idx)
145 ctx->dcss1 = upa_readl(&ffb->dcss1); /* Depth Cue Scale Slope 1 */ 144 ctx->dcss1 = upa_readl(&ffb->dcss1); /* Depth Cue Scale Slope 1 */
146 ctx->dcss2 = upa_readl(&ffb->dcss2); /* Depth Cue Scale Slope 2 */ 145 ctx->dcss2 = upa_readl(&ffb->dcss2); /* Depth Cue Scale Slope 2 */
147 ctx->dcss2 = upa_readl(&ffb->dcss3); /* Depth Cue Scale Slope 3 */ 146 ctx->dcss2 = upa_readl(&ffb->dcss3); /* Depth Cue Scale Slope 3 */
148 ctx->dcs2 = upa_readl(&ffb->dcs2); /* Depth Cue Scale 2 */ 147 ctx->dcs2 = upa_readl(&ffb->dcs2); /* Depth Cue Scale 2 */
149 ctx->dcs3 = upa_readl(&ffb->dcs3); /* Depth Cue Scale 3 */ 148 ctx->dcs3 = upa_readl(&ffb->dcs3); /* Depth Cue Scale 3 */
150 ctx->dcs4 = upa_readl(&ffb->dcs4); /* Depth Cue Scale 4 */ 149 ctx->dcs4 = upa_readl(&ffb->dcs4); /* Depth Cue Scale 4 */
151 ctx->dcd2 = upa_readl(&ffb->dcd2); /* Depth Cue Depth 2 */ 150 ctx->dcd2 = upa_readl(&ffb->dcd2); /* Depth Cue Depth 2 */
152 ctx->dcd3 = upa_readl(&ffb->dcd3); /* Depth Cue Depth 3 */ 151 ctx->dcd3 = upa_readl(&ffb->dcd3); /* Depth Cue Depth 3 */
153 ctx->dcd4 = upa_readl(&ffb->dcd4); /* Depth Cue Depth 4 */ 152 ctx->dcd4 = upa_readl(&ffb->dcd4); /* Depth Cue Depth 4 */
154 153
155 /* And stencil/stencilctl only exists on FFB2+ and later 154 /* And stencil/stencilctl only exists on FFB2+ and later
156 * due to the introduction of 3DRAM-III. 155 * due to the introduction of 3DRAM-III.
@@ -170,7 +169,7 @@ static void ffb_save_context(ffb_dev_priv_t *fpriv, int idx)
170 ctx->ucsr = upa_readl(&ffb->ucsr); 169 ctx->ucsr = upa_readl(&ffb->ucsr);
171} 170}
172 171
173static void ffb_restore_context(ffb_dev_priv_t *fpriv, int old, int idx) 172static void ffb_restore_context(ffb_dev_priv_t * fpriv, int old, int idx)
174{ 173{
175 ffb_fbcPtr ffb = fpriv->regs; 174 ffb_fbcPtr ffb = fpriv->regs;
176 struct ffb_hw_context *ctx; 175 struct ffb_hw_context *ctx;
@@ -193,7 +192,7 @@ static void ffb_restore_context(ffb_dev_priv_t *fpriv, int old, int idx)
193 192
194 upa_writel(ctx->ppc, &ffb->ppc); 193 upa_writel(ctx->ppc, &ffb->ppc);
195 upa_writel(ctx->wid, &ffb->wid); 194 upa_writel(ctx->wid, &ffb->wid);
196 upa_writel(ctx->fg, &ffb->fg); 195 upa_writel(ctx->fg, &ffb->fg);
197 upa_writel(ctx->bg, &ffb->bg); 196 upa_writel(ctx->bg, &ffb->bg);
198 upa_writel(ctx->xclip, &ffb->xclip); 197 upa_writel(ctx->xclip, &ffb->xclip);
199 upa_writel(ctx->fbc, &ffb->fbc); 198 upa_writel(ctx->fbc, &ffb->fbc);
@@ -237,36 +236,36 @@ static void ffb_restore_context(ffb_dev_priv_t *fpriv, int old, int idx)
237 236
238 /* Restore rendering attributes. */ 237 /* Restore rendering attributes. */
239 238
240 upa_writel(ctx->ppc, &ffb->ppc); /* Pixel Processor Control */ 239 upa_writel(ctx->ppc, &ffb->ppc); /* Pixel Processor Control */
241 upa_writel(ctx->wid, &ffb->wid); /* Current WID */ 240 upa_writel(ctx->wid, &ffb->wid); /* Current WID */
242 upa_writel(ctx->fg, &ffb->fg); /* Constant FG color */ 241 upa_writel(ctx->fg, &ffb->fg); /* Constant FG color */
243 upa_writel(ctx->bg, &ffb->bg); /* Constant BG color */ 242 upa_writel(ctx->bg, &ffb->bg); /* Constant BG color */
244 upa_writel(ctx->consty, &ffb->consty); /* Constant Y */ 243 upa_writel(ctx->consty, &ffb->consty); /* Constant Y */
245 upa_writel(ctx->constz, &ffb->constz); /* Constant Z */ 244 upa_writel(ctx->constz, &ffb->constz); /* Constant Z */
246 upa_writel(ctx->xclip, &ffb->xclip); /* X plane clip */ 245 upa_writel(ctx->xclip, &ffb->xclip); /* X plane clip */
247 upa_writel(ctx->dcss, &ffb->dcss); /* Depth Cue Scale Slope */ 246 upa_writel(ctx->dcss, &ffb->dcss); /* Depth Cue Scale Slope */
248 upa_writel(ctx->vclipmin, &ffb->vclipmin); /* Primary XY clip, minimum */ 247 upa_writel(ctx->vclipmin, &ffb->vclipmin); /* Primary XY clip, minimum */
249 upa_writel(ctx->vclipmax, &ffb->vclipmax); /* Primary XY clip, maximum */ 248 upa_writel(ctx->vclipmax, &ffb->vclipmax); /* Primary XY clip, maximum */
250 upa_writel(ctx->vclipzmin, &ffb->vclipzmin); /* Primary Z clip, minimum */ 249 upa_writel(ctx->vclipzmin, &ffb->vclipzmin); /* Primary Z clip, minimum */
251 upa_writel(ctx->vclipzmax, &ffb->vclipzmax); /* Primary Z clip, maximum */ 250 upa_writel(ctx->vclipzmax, &ffb->vclipzmax); /* Primary Z clip, maximum */
252 upa_writel(ctx->dcsf, &ffb->dcsf); /* Depth Cue Scale Front Bound */ 251 upa_writel(ctx->dcsf, &ffb->dcsf); /* Depth Cue Scale Front Bound */
253 upa_writel(ctx->dcsb, &ffb->dcsb); /* Depth Cue Scale Back Bound */ 252 upa_writel(ctx->dcsb, &ffb->dcsb); /* Depth Cue Scale Back Bound */
254 upa_writel(ctx->dczf, &ffb->dczf); /* Depth Cue Scale Z Front */ 253 upa_writel(ctx->dczf, &ffb->dczf); /* Depth Cue Scale Z Front */
255 upa_writel(ctx->dczb, &ffb->dczb); /* Depth Cue Scale Z Back */ 254 upa_writel(ctx->dczb, &ffb->dczb); /* Depth Cue Scale Z Back */
256 upa_writel(ctx->blendc, &ffb->blendc); /* Alpha Blend Control */ 255 upa_writel(ctx->blendc, &ffb->blendc); /* Alpha Blend Control */
257 upa_writel(ctx->blendc1, &ffb->blendc1); /* Alpha Blend Color 1 */ 256 upa_writel(ctx->blendc1, &ffb->blendc1); /* Alpha Blend Color 1 */
258 upa_writel(ctx->blendc2, &ffb->blendc2); /* Alpha Blend Color 2 */ 257 upa_writel(ctx->blendc2, &ffb->blendc2); /* Alpha Blend Color 2 */
259 upa_writel(ctx->fbc, &ffb->fbc); /* Frame Buffer Control */ 258 upa_writel(ctx->fbc, &ffb->fbc); /* Frame Buffer Control */
260 upa_writel(ctx->rop, &ffb->rop); /* Raster Operation */ 259 upa_writel(ctx->rop, &ffb->rop); /* Raster Operation */
261 upa_writel(ctx->cmp, &ffb->cmp); /* Compare Controls */ 260 upa_writel(ctx->cmp, &ffb->cmp); /* Compare Controls */
262 upa_writel(ctx->matchab, &ffb->matchab); /* Buffer A/B Match Ops */ 261 upa_writel(ctx->matchab, &ffb->matchab); /* Buffer A/B Match Ops */
263 upa_writel(ctx->matchc, &ffb->matchc); /* Buffer C Match Ops */ 262 upa_writel(ctx->matchc, &ffb->matchc); /* Buffer C Match Ops */
264 upa_writel(ctx->magnab, &ffb->magnab); /* Buffer A/B Magnitude Ops */ 263 upa_writel(ctx->magnab, &ffb->magnab); /* Buffer A/B Magnitude Ops */
265 upa_writel(ctx->magnc, &ffb->magnc); /* Buffer C Magnitude Ops */ 264 upa_writel(ctx->magnc, &ffb->magnc); /* Buffer C Magnitude Ops */
266 upa_writel(ctx->pmask, &ffb->pmask); /* RGB Plane Mask */ 265 upa_writel(ctx->pmask, &ffb->pmask); /* RGB Plane Mask */
267 upa_writel(ctx->xpmask, &ffb->xpmask); /* X Plane Mask */ 266 upa_writel(ctx->xpmask, &ffb->xpmask); /* X Plane Mask */
268 upa_writel(ctx->ypmask, &ffb->ypmask); /* Y Plane Mask */ 267 upa_writel(ctx->ypmask, &ffb->ypmask); /* Y Plane Mask */
269 upa_writel(ctx->zpmask, &ffb->zpmask); /* Z Plane Mask */ 268 upa_writel(ctx->zpmask, &ffb->zpmask); /* Z Plane Mask */
270 269
271 /* Auxiliary Clips. */ 270 /* Auxiliary Clips. */
272 upa_writel(ctx->auxclip0min, &ffb->auxclip[0].min); 271 upa_writel(ctx->auxclip0min, &ffb->auxclip[0].min);
@@ -278,9 +277,9 @@ static void ffb_restore_context(ffb_dev_priv_t *fpriv, int old, int idx)
278 upa_writel(ctx->auxclip3min, &ffb->auxclip[3].min); 277 upa_writel(ctx->auxclip3min, &ffb->auxclip[3].min);
279 upa_writel(ctx->auxclip3max, &ffb->auxclip[3].max); 278 upa_writel(ctx->auxclip3max, &ffb->auxclip[3].max);
280 279
281 upa_writel(ctx->lpat, &ffb->lpat); /* Line Pattern */ 280 upa_writel(ctx->lpat, &ffb->lpat); /* Line Pattern */
282 upa_writel(ctx->fontxy, &ffb->fontxy); /* XY Font Coordinate */ 281 upa_writel(ctx->fontxy, &ffb->fontxy); /* XY Font Coordinate */
283 upa_writel(ctx->fontw, &ffb->fontw); /* Font Width */ 282 upa_writel(ctx->fontw, &ffb->fontw); /* Font Width */
284 upa_writel(ctx->fontinc, &ffb->fontinc); /* Font X/Y Increment */ 283 upa_writel(ctx->fontinc, &ffb->fontinc); /* Font X/Y Increment */
285 284
286 /* These registers/features only exist on FFB2 and later chips. */ 285 /* These registers/features only exist on FFB2 and later chips. */
@@ -354,91 +353,87 @@ static void FFBWait(ffb_fbcPtr ffb)
354 } while (--limit); 353 } while (--limit);
355} 354}
356 355
357int ffb_driver_context_switch(drm_device_t *dev, int old, int new) 356int ffb_driver_context_switch(drm_device_t * dev, int old, int new)
358{ 357{
359 ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; 358 ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
360 359
361#ifdef DRM_DMA_HISTOGRAM 360#ifdef DRM_DMA_HISTOGRAM
362 dev->ctx_start = get_cycles(); 361 dev->ctx_start = get_cycles();
363#endif 362#endif
364
365 DRM_DEBUG("Context switch from %d to %d\n", old, new);
366 363
367 if (new == dev->last_context || 364 DRM_DEBUG("Context switch from %d to %d\n", old, new);
368 dev->last_context == 0) { 365
366 if (new == dev->last_context || dev->last_context == 0) {
369 dev->last_context = new; 367 dev->last_context = new;
370 return 0; 368 return 0;
371 } 369 }
372 370
373 FFBWait(fpriv->regs); 371 FFBWait(fpriv->regs);
374 ffb_save_context(fpriv, old); 372 ffb_save_context(fpriv, old);
375 ffb_restore_context(fpriv, old, new); 373 ffb_restore_context(fpriv, old, new);
376 FFBWait(fpriv->regs); 374 FFBWait(fpriv->regs);
377 375
378 dev->last_context = new; 376 dev->last_context = new;
379 377
380 return 0; 378 return 0;
381} 379}
382 380
383int ffb_driver_resctx(struct inode *inode, struct file *filp, unsigned int cmd, 381int ffb_driver_resctx(struct inode *inode, struct file *filp, unsigned int cmd,
384 unsigned long arg) 382 unsigned long arg)
385{ 383{
386 drm_ctx_res_t res; 384 drm_ctx_res_t res;
387 drm_ctx_t ctx; 385 drm_ctx_t ctx;
388 int i; 386 int i;
389 387
390 DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS); 388 DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS);
391 if (copy_from_user(&res, (drm_ctx_res_t __user *)arg, sizeof(res))) 389 if (copy_from_user(&res, (drm_ctx_res_t __user *) arg, sizeof(res)))
392 return -EFAULT; 390 return -EFAULT;
393 if (res.count >= DRM_RESERVED_CONTEXTS) { 391 if (res.count >= DRM_RESERVED_CONTEXTS) {
394 memset(&ctx, 0, sizeof(ctx)); 392 memset(&ctx, 0, sizeof(ctx));
395 for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) { 393 for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) {
396 ctx.handle = i; 394 ctx.handle = i;
397 if (copy_to_user(&res.contexts[i], 395 if (copy_to_user(&res.contexts[i], &i, sizeof(i)))
398 &i,
399 sizeof(i)))
400 return -EFAULT; 396 return -EFAULT;
401 } 397 }
402 } 398 }
403 res.count = DRM_RESERVED_CONTEXTS; 399 res.count = DRM_RESERVED_CONTEXTS;
404 if (copy_to_user((drm_ctx_res_t __user *)arg, &res, sizeof(res))) 400 if (copy_to_user((drm_ctx_res_t __user *) arg, &res, sizeof(res)))
405 return -EFAULT; 401 return -EFAULT;
406 return 0; 402 return 0;
407} 403}
408 404
409
410int ffb_driver_addctx(struct inode *inode, struct file *filp, unsigned int cmd, 405int ffb_driver_addctx(struct inode *inode, struct file *filp, unsigned int cmd,
411 unsigned long arg) 406 unsigned long arg)
412{ 407{
413 drm_file_t *priv = filp->private_data; 408 drm_file_t *priv = filp->private_data;
414 drm_device_t *dev = priv->dev; 409 drm_device_t *dev = priv->dev;
415 drm_ctx_t ctx; 410 drm_ctx_t ctx;
416 int idx; 411 int idx;
417 412
418 if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) 413 if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx)))
419 return -EFAULT; 414 return -EFAULT;
420 idx = DRM(alloc_queue)(dev, (ctx.flags & _DRM_CONTEXT_2DONLY)); 415 idx = DRM(alloc_queue) (dev, (ctx.flags & _DRM_CONTEXT_2DONLY));
421 if (idx < 0) 416 if (idx < 0)
422 return -ENFILE; 417 return -ENFILE;
423 418
424 DRM_DEBUG("%d\n", ctx.handle); 419 DRM_DEBUG("%d\n", ctx.handle);
425 ctx.handle = idx; 420 ctx.handle = idx;
426 if (copy_to_user((drm_ctx_t __user *)arg, &ctx, sizeof(ctx))) 421 if (copy_to_user((drm_ctx_t __user *) arg, &ctx, sizeof(ctx)))
427 return -EFAULT; 422 return -EFAULT;
428 return 0; 423 return 0;
429} 424}
430 425
431int ffb_driver_modctx(struct inode *inode, struct file *filp, unsigned int cmd, 426int ffb_driver_modctx(struct inode *inode, struct file *filp, unsigned int cmd,
432 unsigned long arg) 427 unsigned long arg)
433{ 428{
434 drm_file_t *priv = filp->private_data; 429 drm_file_t *priv = filp->private_data;
435 drm_device_t *dev = priv->dev; 430 drm_device_t *dev = priv->dev;
436 ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; 431 ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
437 struct ffb_hw_context *hwctx; 432 struct ffb_hw_context *hwctx;
438 drm_ctx_t ctx; 433 drm_ctx_t ctx;
439 int idx; 434 int idx;
440 435
441 if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) 436 if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx)))
442 return -EFAULT; 437 return -EFAULT;
443 438
444 idx = ctx.handle; 439 idx = ctx.handle;
@@ -458,16 +453,16 @@ int ffb_driver_modctx(struct inode *inode, struct file *filp, unsigned int cmd,
458} 453}
459 454
460int ffb_driver_getctx(struct inode *inode, struct file *filp, unsigned int cmd, 455int ffb_driver_getctx(struct inode *inode, struct file *filp, unsigned int cmd,
461 unsigned long arg) 456 unsigned long arg)
462{ 457{
463 drm_file_t *priv = filp->private_data; 458 drm_file_t *priv = filp->private_data;
464 drm_device_t *dev = priv->dev; 459 drm_device_t *dev = priv->dev;
465 ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; 460 ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
466 struct ffb_hw_context *hwctx; 461 struct ffb_hw_context *hwctx;
467 drm_ctx_t ctx; 462 drm_ctx_t ctx;
468 int idx; 463 int idx;
469 464
470 if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) 465 if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx)))
471 return -EFAULT; 466 return -EFAULT;
472 467
473 idx = ctx.handle; 468 idx = ctx.handle;
@@ -483,31 +478,31 @@ int ffb_driver_getctx(struct inode *inode, struct file *filp, unsigned int cmd,
483 else 478 else
484 ctx.flags = 0; 479 ctx.flags = 0;
485 480
486 if (copy_to_user((drm_ctx_t __user *)arg, &ctx, sizeof(ctx))) 481 if (copy_to_user((drm_ctx_t __user *) arg, &ctx, sizeof(ctx)))
487 return -EFAULT; 482 return -EFAULT;
488 483
489 return 0; 484 return 0;
490} 485}
491 486
492int ffb_driver_switchctx(struct inode *inode, struct file *filp, unsigned int cmd, 487int ffb_driver_switchctx(struct inode *inode, struct file *filp,
493 unsigned long arg) 488 unsigned int cmd, unsigned long arg)
494{ 489{
495 drm_file_t *priv = filp->private_data; 490 drm_file_t *priv = filp->private_data;
496 drm_device_t *dev = priv->dev; 491 drm_device_t *dev = priv->dev;
497 drm_ctx_t ctx; 492 drm_ctx_t ctx;
498 493
499 if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) 494 if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx)))
500 return -EFAULT; 495 return -EFAULT;
501 DRM_DEBUG("%d\n", ctx.handle); 496 DRM_DEBUG("%d\n", ctx.handle);
502 return ffb_driver_context_switch(dev, dev->last_context, ctx.handle); 497 return ffb_driver_context_switch(dev, dev->last_context, ctx.handle);
503} 498}
504 499
505int ffb_driver_newctx(struct inode *inode, struct file *filp, unsigned int cmd, 500int ffb_driver_newctx(struct inode *inode, struct file *filp, unsigned int cmd,
506 unsigned long arg) 501 unsigned long arg)
507{ 502{
508 drm_ctx_t ctx; 503 drm_ctx_t ctx;
509 504
510 if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) 505 if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx)))
511 return -EFAULT; 506 return -EFAULT;
512 DRM_DEBUG("%d\n", ctx.handle); 507 DRM_DEBUG("%d\n", ctx.handle);
513 508
@@ -515,15 +510,15 @@ int ffb_driver_newctx(struct inode *inode, struct file *filp, unsigned int cmd,
515} 510}
516 511
517int ffb_driver_rmctx(struct inode *inode, struct file *filp, unsigned int cmd, 512int ffb_driver_rmctx(struct inode *inode, struct file *filp, unsigned int cmd,
518 unsigned long arg) 513 unsigned long arg)
519{ 514{
520 drm_ctx_t ctx; 515 drm_ctx_t ctx;
521 drm_file_t *priv = filp->private_data; 516 drm_file_t *priv = filp->private_data;
522 drm_device_t *dev = priv->dev; 517 drm_device_t *dev = priv->dev;
523 ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; 518 ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
524 int idx; 519 int idx;
525 520
526 if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) 521 if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx)))
527 return -EFAULT; 522 return -EFAULT;
528 DRM_DEBUG("%d\n", ctx.handle); 523 DRM_DEBUG("%d\n", ctx.handle);
529 524
@@ -544,7 +539,8 @@ void ffb_set_context_ioctls(void)
544 DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)].func = ffb_driver_rmctx; 539 DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)].func = ffb_driver_rmctx;
545 DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)].func = ffb_driver_modctx; 540 DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)].func = ffb_driver_modctx;
546 DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)].func = ffb_driver_getctx; 541 DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)].func = ffb_driver_getctx;
547 DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)].func = ffb_driver_switchctx; 542 DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)].func =
543 ffb_driver_switchctx;
548 DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)].func = ffb_driver_newctx; 544 DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)].func = ffb_driver_newctx;
549 DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)].func = ffb_driver_resctx; 545 DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)].func = ffb_driver_resctx;
550 546
diff --git a/drivers/char/drm/ffb_drv.c b/drivers/char/drm/ffb_drv.c
index 1bd0d55ee0f0..5c121d6df9f2 100644
--- a/drivers/char/drm/ffb_drv.c
+++ b/drivers/char/drm/ffb_drv.c
@@ -33,13 +33,13 @@ typedef struct _ffb_position_t {
33 33
34static ffb_position_t *ffb_position; 34static ffb_position_t *ffb_position;
35 35
36static void get_ffb_type(ffb_dev_priv_t *ffb_priv, int instance) 36static void get_ffb_type(ffb_dev_priv_t * ffb_priv, int instance)
37{ 37{
38 volatile unsigned char *strap_bits; 38 volatile unsigned char *strap_bits;
39 unsigned char val; 39 unsigned char val;
40 40
41 strap_bits = (volatile unsigned char *) 41 strap_bits = (volatile unsigned char *)
42 (ffb_priv->card_phys_base + 0x00200000UL); 42 (ffb_priv->card_phys_base + 0x00200000UL);
43 43
44 /* Don't ask, you have to read the value twice for whatever 44 /* Don't ask, you have to read the value twice for whatever
45 * reason to get correct contents. 45 * reason to get correct contents.
@@ -61,7 +61,8 @@ static void get_ffb_type(ffb_dev_priv_t *ffb_priv, int instance)
61 break; 61 break;
62 case (0x1 << 5) | (0x0 << 3): 62 case (0x1 << 5) | (0x0 << 3):
63 ffb_priv->ffb_type = ffb2_prototype; 63 ffb_priv->ffb_type = ffb2_prototype;
64 printk("ffb%d: Detected FFB2/vertical pre-FCS prototype\n", instance); 64 printk("ffb%d: Detected FFB2/vertical pre-FCS prototype\n",
65 instance);
65 break; 66 break;
66 case (0x1 << 5) | (0x1 << 3): 67 case (0x1 << 5) | (0x1 << 3):
67 ffb_priv->ffb_type = ffb2_vertical; 68 ffb_priv->ffb_type = ffb2_vertical;
@@ -81,12 +82,13 @@ static void get_ffb_type(ffb_dev_priv_t *ffb_priv, int instance)
81 break; 82 break;
82 default: 83 default:
83 ffb_priv->ffb_type = ffb2_vertical; 84 ffb_priv->ffb_type = ffb2_vertical;
84 printk("ffb%d: Unknown boardID[%08x], assuming FFB2\n", instance, val); 85 printk("ffb%d: Unknown boardID[%08x], assuming FFB2\n",
86 instance, val);
85 break; 87 break;
86 }; 88 };
87} 89}
88 90
89static void ffb_apply_upa_parent_ranges(int parent, 91static void ffb_apply_upa_parent_ranges(int parent,
90 struct linux_prom64_registers *regs) 92 struct linux_prom64_registers *regs)
91{ 93{
92 struct linux_prom64_ranges ranges[PROMREG_MAX]; 94 struct linux_prom64_ranges ranges[PROMREG_MAX];
@@ -97,7 +99,8 @@ static void ffb_apply_upa_parent_ranges(int parent,
97 if (strcmp(name, "upa") != 0) 99 if (strcmp(name, "upa") != 0)
98 return; 100 return;
99 101
100 len = prom_getproperty(parent, "ranges", (void *) ranges, sizeof(ranges)); 102 len =
103 prom_getproperty(parent, "ranges", (void *)ranges, sizeof(ranges));
101 if (len <= 0) 104 if (len <= 0)
102 return; 105 return;
103 106
@@ -117,11 +120,11 @@ static void ffb_apply_upa_parent_ranges(int parent,
117 return; 120 return;
118} 121}
119 122
120static int ffb_init_one(drm_device_t *dev, int prom_node, int parent_node, 123static int ffb_init_one(drm_device_t * dev, int prom_node, int parent_node,
121 int instance) 124 int instance)
122{ 125{
123 struct linux_prom64_registers regs[2*PROMREG_MAX]; 126 struct linux_prom64_registers regs[2 * PROMREG_MAX];
124 ffb_dev_priv_t *ffb_priv = (ffb_dev_priv_t *)dev->dev_private; 127 ffb_dev_priv_t *ffb_priv = (ffb_dev_priv_t *) dev->dev_private;
125 int i; 128 int i;
126 129
127 ffb_priv->prom_node = prom_node; 130 ffb_priv->prom_node = prom_node;
@@ -132,27 +135,27 @@ static int ffb_init_one(drm_device_t *dev, int prom_node, int parent_node,
132 ffb_apply_upa_parent_ranges(parent_node, &regs[0]); 135 ffb_apply_upa_parent_ranges(parent_node, &regs[0]);
133 ffb_priv->card_phys_base = regs[0].phys_addr; 136 ffb_priv->card_phys_base = regs[0].phys_addr;
134 ffb_priv->regs = (ffb_fbcPtr) 137 ffb_priv->regs = (ffb_fbcPtr)
135 (regs[0].phys_addr + 0x00600000UL); 138 (regs[0].phys_addr + 0x00600000UL);
136 get_ffb_type(ffb_priv, instance); 139 get_ffb_type(ffb_priv, instance);
137 for (i = 0; i < FFB_MAX_CTXS; i++) 140 for (i = 0; i < FFB_MAX_CTXS; i++)
138 ffb_priv->hw_state[i] = NULL; 141 ffb_priv->hw_state[i] = NULL;
139 142
140 return 0; 143 return 0;
141} 144}
142 145
143static drm_map_t *ffb_find_map(struct file *filp, unsigned long off) 146static drm_map_t *ffb_find_map(struct file *filp, unsigned long off)
144{ 147{
145 drm_file_t *priv = filp->private_data; 148 drm_file_t *priv = filp->private_data;
146 drm_device_t *dev; 149 drm_device_t *dev;
147 drm_map_list_t *r_list; 150 drm_map_list_t *r_list;
148 struct list_head *list; 151 struct list_head *list;
149 drm_map_t *map; 152 drm_map_t *map;
150 153
151 if (!priv || (dev = priv->dev) == NULL) 154 if (!priv || (dev = priv->dev) == NULL)
152 return NULL; 155 return NULL;
153 156
154 list_for_each(list, &dev->maplist->head) { 157 list_for_each(list, &dev->maplist->head) {
155 r_list = (drm_map_list_t *)list; 158 r_list = (drm_map_list_t *) list;
156 map = r_list->map; 159 map = r_list->map;
157 if (!map) 160 if (!map)
158 continue; 161 continue;
@@ -166,8 +169,7 @@ static drm_map_t *ffb_find_map(struct file *filp, unsigned long off)
166unsigned long ffb_get_unmapped_area(struct file *filp, 169unsigned long ffb_get_unmapped_area(struct file *filp,
167 unsigned long hint, 170 unsigned long hint,
168 unsigned long len, 171 unsigned long len,
169 unsigned long pgoff, 172 unsigned long pgoff, unsigned long flags)
170 unsigned long flags)
171{ 173{
172 drm_map_t *map = ffb_find_map(filp, pgoff << PAGE_SHIFT); 174 drm_map_t *map = ffb_find_map(filp, pgoff << PAGE_SHIFT);
173 unsigned long addr = -ENOMEM; 175 unsigned long addr = -ENOMEM;
@@ -175,8 +177,7 @@ unsigned long ffb_get_unmapped_area(struct file *filp,
175 if (!map) 177 if (!map)
176 return get_unmapped_area(NULL, hint, len, pgoff, flags); 178 return get_unmapped_area(NULL, hint, len, pgoff, flags);
177 179
178 if (map->type == _DRM_FRAME_BUFFER || 180 if (map->type == _DRM_FRAME_BUFFER || map->type == _DRM_REGISTERS) {
179 map->type == _DRM_REGISTERS) {
180#ifdef HAVE_ARCH_FB_UNMAPPED_AREA 181#ifdef HAVE_ARCH_FB_UNMAPPED_AREA
181 addr = get_fb_unmapped_area(filp, hint, len, pgoff, flags); 182 addr = get_fb_unmapped_area(filp, hint, len, pgoff, flags);
182#else 183#else
@@ -187,7 +188,7 @@ unsigned long ffb_get_unmapped_area(struct file *filp,
187 188
188 addr = get_unmapped_area(NULL, hint, len + slack, pgoff, flags); 189 addr = get_unmapped_area(NULL, hint, len + slack, pgoff, flags);
189 if (!(addr & ~PAGE_MASK)) { 190 if (!(addr & ~PAGE_MASK)) {
190 unsigned long kvirt = (unsigned long) map->handle; 191 unsigned long kvirt = (unsigned long)map->handle;
191 192
192 if ((kvirt & (SHMLBA - 1)) != (addr & (SHMLBA - 1))) { 193 if ((kvirt & (SHMLBA - 1)) != (addr & (SHMLBA - 1))) {
193 unsigned long koff, aoff; 194 unsigned long koff, aoff;
@@ -207,9 +208,9 @@ unsigned long ffb_get_unmapped_area(struct file *filp,
207 return addr; 208 return addr;
208} 209}
209 210
210static int ffb_presetup(drm_device_t *dev) 211static int ffb_presetup(drm_device_t * dev)
211{ 212{
212 ffb_dev_priv_t *ffb_priv; 213 ffb_dev_priv_t *ffb_priv;
213 int ret = 0; 214 int ret = 0;
214 int i = 0; 215 int i = 0;
215 216
@@ -224,14 +225,11 @@ static int ffb_presetup(drm_device_t *dev)
224 memset(ffb_priv, 0, sizeof(*ffb_priv)); 225 memset(ffb_priv, 0, sizeof(*ffb_priv));
225 dev->dev_private = ffb_priv; 226 dev->dev_private = ffb_priv;
226 227
227 ret = ffb_init_one(dev, 228 ret = ffb_init_one(dev, ffb_position[i].node, ffb_position[i].root, i);
228 ffb_position[i].node,
229 ffb_position[i].root,
230 i);
231 return ret; 229 return ret;
232} 230}
233 231
234static void ffb_driver_release(drm_device_t *dev, struct file *filp) 232static void ffb_driver_release(drm_device_t * dev, struct file *filp)
235{ 233{
236 ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; 234 ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private;
237 int context = _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock); 235 int context = _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock);
@@ -239,84 +237,82 @@ static void ffb_driver_release(drm_device_t *dev, struct file *filp)
239 237
240 idx = context - 1; 238 idx = context - 1;
241 if (fpriv && 239 if (fpriv &&
242 context != DRM_KERNEL_CONTEXT && 240 context != DRM_KERNEL_CONTEXT && fpriv->hw_state[idx] != NULL) {
243 fpriv->hw_state[idx] != NULL) {
244 kfree(fpriv->hw_state[idx]); 241 kfree(fpriv->hw_state[idx]);
245 fpriv->hw_state[idx] = NULL; 242 fpriv->hw_state[idx] = NULL;
246 } 243 }
247} 244}
248 245
249static void ffb_driver_pretakedown(drm_device_t *dev) 246static void ffb_driver_pretakedown(drm_device_t * dev)
250{ 247{
251 if (dev->dev_private) kfree(dev->dev_private); 248 if (dev->dev_private)
249 kfree(dev->dev_private);
252} 250}
253 251
254static int ffb_driver_postcleanup(drm_device_t *dev) 252static int ffb_driver_postcleanup(drm_device_t * dev)
255{ 253{
256 if (ffb_position != NULL) kfree(ffb_position); 254 if (ffb_position != NULL)
255 kfree(ffb_position);
257 return 0; 256 return 0;
258} 257}
259 258
260static void ffb_driver_kernel_context_switch_unlock(struct drm_device *dev, drm_lock_t *lock) 259static void ffb_driver_kernel_context_switch_unlock(struct drm_device *dev,
260 drm_lock_t * lock)
261{ 261{
262 dev->lock.filp = 0; 262 dev->lock.filp = 0;
263 { 263 {
264 __volatile__ unsigned int *plock = &dev->lock.hw_lock->lock; 264 __volatile__ unsigned int *plock = &dev->lock.hw_lock->lock;
265 unsigned int old, new, prev, ctx; 265 unsigned int old, new, prev, ctx;
266 266
267 ctx = lock->context; 267 ctx = lock->context;
268 do { 268 do {
269 old = *plock; 269 old = *plock;
270 new = ctx; 270 new = ctx;
271 prev = cmpxchg(plock, old, new); 271 prev = cmpxchg(plock, old, new);
272 } while (prev != old); 272 } while (prev != old);
273 } 273 }
274 wake_up_interruptible(&dev->lock.lock_queue); 274 wake_up_interruptible(&dev->lock.lock_queue);
275} 275}
276 276
277static unsigned long ffb_driver_get_map_ofs(drm_map_t *map) 277static unsigned long ffb_driver_get_map_ofs(drm_map_t * map)
278{ 278{
279 return (map->offset & 0xffffffff); 279 return (map->offset & 0xffffffff);
280} 280}
281 281
282static unsigned long ffb_driver_get_reg_ofs(drm_device_t *dev) 282static unsigned long ffb_driver_get_reg_ofs(drm_device_t * dev)
283{ 283{
284 ffb_dev_priv_t *ffb_priv = (ffb_dev_priv_t *)dev->dev_private; 284 ffb_dev_priv_t *ffb_priv = (ffb_dev_priv_t *) dev->dev_private;
285 285
286 if (ffb_priv) 286 if (ffb_priv)
287 return ffb_priv->card_phys_base; 287 return ffb_priv->card_phys_base;
288 288
289 return 0; 289 return 0;
290} 290}
291 291
292static int postinit( struct drm_device *dev, unsigned long flags ) 292static int postinit(struct drm_device *dev, unsigned long flags)
293{ 293{
294 DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d\n", 294 DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n",
295 DRIVER_NAME, 295 DRIVER_NAME,
296 DRIVER_MAJOR, 296 DRIVER_MAJOR,
297 DRIVER_MINOR, 297 DRIVER_MINOR, DRIVER_PATCHLEVEL, DRIVER_DATE, dev->minor);
298 DRIVER_PATCHLEVEL,
299 DRIVER_DATE,
300 dev->minor
301 );
302 return 0; 298 return 0;
303} 299}
304 300
305static int version( drm_version_t *version ) 301static int version(drm_version_t * version)
306{ 302{
307 int len; 303 int len;
308 304
309 version->version_major = DRIVER_MAJOR; 305 version->version_major = DRIVER_MAJOR;
310 version->version_minor = DRIVER_MINOR; 306 version->version_minor = DRIVER_MINOR;
311 version->version_patchlevel = DRIVER_PATCHLEVEL; 307 version->version_patchlevel = DRIVER_PATCHLEVEL;
312 DRM_COPY( version->name, DRIVER_NAME ); 308 DRM_COPY(version->name, DRIVER_NAME);
313 DRM_COPY( version->date, DRIVER_DATE ); 309 DRM_COPY(version->date, DRIVER_DATE);
314 DRM_COPY( version->desc, DRIVER_DESC ); 310 DRM_COPY(version->desc, DRIVER_DESC);
315 return 0; 311 return 0;
316} 312}
317 313
318static drm_ioctl_desc_t ioctls[] = { 314static drm_ioctl_desc_t ioctls[] = {
319 315
320}; 316};
321 317
322static struct drm_driver driver = { 318static struct drm_driver driver = {
@@ -335,14 +331,15 @@ static struct drm_driver driver = {
335 .ioctls = ioctls, 331 .ioctls = ioctls,
336 .num_ioctls = DRM_ARRAY_SIZE(ioctls), 332 .num_ioctls = DRM_ARRAY_SIZE(ioctls),
337 .fops = { 333 .fops = {
338 .owner = THIS_MODULE, 334 .owner = THIS_MODULE,
339 .open = drm_open, 335 .open = drm_open,
340 .release = drm_release, 336 .release = drm_release,
341 .ioctl = drm_ioctl, 337 .ioctl = drm_ioctl,
342 .mmap = drm_mmap, 338 .mmap = drm_mmap,
343 .poll = drm_poll, 339 .poll = drm_poll,
344 .fasync = drm_fasync, 340 .fasync = drm_fasync,
345 }, 341 }
342 ,
346}; 343};
347 344
348static int __init ffb_init(void) 345static int __init ffb_init(void)
@@ -357,6 +354,6 @@ static void __exit ffb_exit(void)
357module_init(ffb_init); 354module_init(ffb_init);
358module_exit(ffb_exit); 355module_exit(ffb_exit);
359 356
360MODULE_AUTHOR( DRIVER_AUTHOR ); 357MODULE_AUTHOR(DRIVER_AUTHOR);
361MODULE_DESCRIPTION( DRIVER_DESC ); 358MODULE_DESCRIPTION(DRIVER_DESC);
362MODULE_LICENSE("GPL and additional rights"); 359MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/char/drm/ffb_drv.h b/drivers/char/drm/ffb_drv.h
index 8bf7f1e143f1..582afa6dd2b4 100644
--- a/drivers/char/drm/ffb_drv.h
+++ b/drivers/char/drm/ffb_drv.h
@@ -5,7 +5,7 @@
5 */ 5 */
6 6
7/* Auxilliary clips. */ 7/* Auxilliary clips. */
8typedef struct { 8typedef struct {
9 volatile unsigned int min; 9 volatile unsigned int min;
10 volatile unsigned int max; 10 volatile unsigned int max;
11} ffb_auxclip, *ffb_auxclipPtr; 11} ffb_auxclip, *ffb_auxclipPtr;
@@ -15,172 +15,265 @@ typedef struct _ffb_fbc {
15 /* Next vertex registers, on the right we list which drawops 15 /* Next vertex registers, on the right we list which drawops
16 * use said register and the logical name the register has in 16 * use said register and the logical name the register has in
17 * that context. 17 * that context.
18 */ /* DESCRIPTION DRAWOP(NAME) */ 18 *//* DESCRIPTION DRAWOP(NAME) */
19/*0x00*/unsigned int pad1[3]; /* Reserved */ 19 /*0x00*/ unsigned int pad1[3];
20/*0x0c*/volatile unsigned int alpha; /* ALPHA Transparency */ 20 /* Reserved */
21/*0x10*/volatile unsigned int red; /* RED */ 21 /*0x0c*/ volatile unsigned int alpha;
22/*0x14*/volatile unsigned int green; /* GREEN */ 22 /* ALPHA Transparency */
23/*0x18*/volatile unsigned int blue; /* BLUE */ 23 /*0x10*/ volatile unsigned int red;
24/*0x1c*/volatile unsigned int z; /* DEPTH */ 24 /* RED */
25/*0x20*/volatile unsigned int y; /* Y triangle(DOYF) */ 25 /*0x14*/ volatile unsigned int green;
26 /* aadot(DYF) */ 26 /* GREEN */
27 /* ddline(DYF) */ 27 /*0x18*/ volatile unsigned int blue;
28 /* aaline(DYF) */ 28 /* BLUE */
29/*0x24*/volatile unsigned int x; /* X triangle(DOXF) */ 29 /*0x1c*/ volatile unsigned int z;
30 /* aadot(DXF) */ 30 /* DEPTH */
31 /* ddline(DXF) */ 31 /*0x20*/ volatile unsigned int y;
32 /* aaline(DXF) */ 32 /* Y triangle(DOYF) */
33/*0x28*/unsigned int pad2[2]; /* Reserved */ 33 /* aadot(DYF) */
34/*0x30*/volatile unsigned int ryf; /* Y (alias to DOYF) ddline(RYF) */ 34 /* ddline(DYF) */
35 /* aaline(RYF) */ 35 /* aaline(DYF) */
36 /* triangle(RYF) */ 36 /*0x24*/ volatile unsigned int x;
37/*0x34*/volatile unsigned int rxf; /* X ddline(RXF) */ 37 /* X triangle(DOXF) */
38 /* aaline(RXF) */ 38 /* aadot(DXF) */
39 /* triangle(RXF) */ 39 /* ddline(DXF) */
40/*0x38*/unsigned int pad3[2]; /* Reserved */ 40 /* aaline(DXF) */
41/*0x40*/volatile unsigned int dmyf; /* Y (alias to DOYF) triangle(DMYF) */ 41 /*0x28*/ unsigned int pad2[2];
42/*0x44*/volatile unsigned int dmxf; /* X triangle(DMXF) */ 42 /* Reserved */
43/*0x48*/unsigned int pad4[2]; /* Reserved */ 43 /*0x30*/ volatile unsigned int ryf;
44/*0x50*/volatile unsigned int ebyi; /* Y (alias to RYI) polygon(EBYI) */ 44 /* Y (alias to DOYF) ddline(RYF) */
45/*0x54*/volatile unsigned int ebxi; /* X polygon(EBXI) */ 45 /* aaline(RYF) */
46/*0x58*/unsigned int pad5[2]; /* Reserved */ 46 /* triangle(RYF) */
47/*0x60*/volatile unsigned int by; /* Y brline(RYI) */ 47 /*0x34*/ volatile unsigned int rxf;
48 /* fastfill(OP) */ 48 /* X ddline(RXF) */
49 /* polygon(YI) */ 49 /* aaline(RXF) */
50 /* rectangle(YI) */ 50 /* triangle(RXF) */
51 /* bcopy(SRCY) */ 51 /*0x38*/ unsigned int pad3[2];
52 /* vscroll(SRCY) */ 52 /* Reserved */
53/*0x64*/volatile unsigned int bx; /* X brline(RXI) */ 53 /*0x40*/ volatile unsigned int dmyf;
54 /* polygon(XI) */ 54 /* Y (alias to DOYF) triangle(DMYF) */
55 /* rectangle(XI) */ 55 /*0x44*/ volatile unsigned int dmxf;
56 /* bcopy(SRCX) */ 56 /* X triangle(DMXF) */
57 /* vscroll(SRCX) */ 57 /*0x48*/ unsigned int pad4[2];
58 /* fastfill(GO) */ 58 /* Reserved */
59/*0x68*/volatile unsigned int dy; /* destination Y fastfill(DSTY) */ 59 /*0x50*/ volatile unsigned int ebyi;
60 /* bcopy(DSRY) */ 60 /* Y (alias to RYI) polygon(EBYI) */
61 /* vscroll(DSRY) */ 61 /*0x54*/ volatile unsigned int ebxi;
62/*0x6c*/volatile unsigned int dx; /* destination X fastfill(DSTX) */ 62 /* X polygon(EBXI) */
63 /* bcopy(DSTX) */ 63 /*0x58*/ unsigned int pad5[2];
64 /* vscroll(DSTX) */ 64 /* Reserved */
65/*0x70*/volatile unsigned int bh; /* Y (alias to RYI) brline(DYI) */ 65 /*0x60*/ volatile unsigned int by;
66 /* dot(DYI) */ 66 /* Y brline(RYI) */
67 /* polygon(ETYI) */ 67 /* fastfill(OP) */
68 /* Height fastfill(H) */ 68 /* polygon(YI) */
69 /* bcopy(H) */ 69 /* rectangle(YI) */
70 /* vscroll(H) */ 70 /* bcopy(SRCY) */
71 /* Y count fastfill(NY) */ 71 /* vscroll(SRCY) */
72/*0x74*/volatile unsigned int bw; /* X dot(DXI) */ 72 /*0x64*/ volatile unsigned int bx;
73 /* brline(DXI) */ 73 /* X brline(RXI) */
74 /* polygon(ETXI) */ 74 /* polygon(XI) */
75 /* fastfill(W) */ 75 /* rectangle(XI) */
76 /* bcopy(W) */ 76 /* bcopy(SRCX) */
77 /* vscroll(W) */ 77 /* vscroll(SRCX) */
78 /* fastfill(NX) */ 78 /* fastfill(GO) */
79/*0x78*/unsigned int pad6[2]; /* Reserved */ 79 /*0x68*/ volatile unsigned int dy;
80/*0x80*/unsigned int pad7[32]; /* Reserved */ 80 /* destination Y fastfill(DSTY) */
81 81 /* bcopy(DSRY) */
82 /* vscroll(DSRY) */
83 /*0x6c*/ volatile unsigned int dx;
84 /* destination X fastfill(DSTX) */
85 /* bcopy(DSTX) */
86 /* vscroll(DSTX) */
87 /*0x70*/ volatile unsigned int bh;
88 /* Y (alias to RYI) brline(DYI) */
89 /* dot(DYI) */
90 /* polygon(ETYI) */
91 /* Height fastfill(H) */
92 /* bcopy(H) */
93 /* vscroll(H) */
94 /* Y count fastfill(NY) */
95 /*0x74*/ volatile unsigned int bw;
96 /* X dot(DXI) */
97 /* brline(DXI) */
98 /* polygon(ETXI) */
99 /* fastfill(W) */
100 /* bcopy(W) */
101 /* vscroll(W) */
102 /* fastfill(NX) */
103 /*0x78*/ unsigned int pad6[2];
104 /* Reserved */
105 /*0x80*/ unsigned int pad7[32];
106 /* Reserved */
107
82 /* Setup Unit's vertex state register */ 108 /* Setup Unit's vertex state register */
83/*100*/ volatile unsigned int suvtx; 109/*100*/ volatile unsigned int suvtx;
84/*104*/ unsigned int pad8[63]; /* Reserved */ 110 /*104*/ unsigned int pad8[63];
85 111 /* Reserved */
112
86 /* Frame Buffer Control Registers */ 113 /* Frame Buffer Control Registers */
87/*200*/ volatile unsigned int ppc; /* Pixel Processor Control */ 114 /*200*/ volatile unsigned int ppc;
88/*204*/ volatile unsigned int wid; /* Current WID */ 115 /* Pixel Processor Control */
89/*208*/ volatile unsigned int fg; /* FG data */ 116 /*204*/ volatile unsigned int wid;
90/*20c*/ volatile unsigned int bg; /* BG data */ 117 /* Current WID */
91/*210*/ volatile unsigned int consty; /* Constant Y */ 118 /*208*/ volatile unsigned int fg;
92/*214*/ volatile unsigned int constz; /* Constant Z */ 119 /* FG data */
93/*218*/ volatile unsigned int xclip; /* X Clip */ 120 /*20c*/ volatile unsigned int bg;
94/*21c*/ volatile unsigned int dcss; /* Depth Cue Scale Slope */ 121 /* BG data */
95/*220*/ volatile unsigned int vclipmin; /* Viewclip XY Min Bounds */ 122 /*210*/ volatile unsigned int consty;
96/*224*/ volatile unsigned int vclipmax; /* Viewclip XY Max Bounds */ 123 /* Constant Y */
97/*228*/ volatile unsigned int vclipzmin; /* Viewclip Z Min Bounds */ 124 /*214*/ volatile unsigned int constz;
98/*22c*/ volatile unsigned int vclipzmax; /* Viewclip Z Max Bounds */ 125 /* Constant Z */
99/*230*/ volatile unsigned int dcsf; /* Depth Cue Scale Front Bound */ 126 /*218*/ volatile unsigned int xclip;
100/*234*/ volatile unsigned int dcsb; /* Depth Cue Scale Back Bound */ 127 /* X Clip */
101/*238*/ volatile unsigned int dczf; /* Depth Cue Z Front */ 128 /*21c*/ volatile unsigned int dcss;
102/*23c*/ volatile unsigned int dczb; /* Depth Cue Z Back */ 129 /* Depth Cue Scale Slope */
103/*240*/ unsigned int pad9; /* Reserved */ 130 /*220*/ volatile unsigned int vclipmin;
104/*244*/ volatile unsigned int blendc; /* Alpha Blend Control */ 131 /* Viewclip XY Min Bounds */
105/*248*/ volatile unsigned int blendc1; /* Alpha Blend Color 1 */ 132 /*224*/ volatile unsigned int vclipmax;
106/*24c*/ volatile unsigned int blendc2; /* Alpha Blend Color 2 */ 133 /* Viewclip XY Max Bounds */
107/*250*/ volatile unsigned int fbramitc; /* FB RAM Interleave Test Control */ 134 /*228*/ volatile unsigned int vclipzmin;
108/*254*/ volatile unsigned int fbc; /* Frame Buffer Control */ 135 /* Viewclip Z Min Bounds */
109/*258*/ volatile unsigned int rop; /* Raster OPeration */ 136 /*22c*/ volatile unsigned int vclipzmax;
110/*25c*/ volatile unsigned int cmp; /* Frame Buffer Compare */ 137 /* Viewclip Z Max Bounds */
111/*260*/ volatile unsigned int matchab; /* Buffer AB Match Mask */ 138 /*230*/ volatile unsigned int dcsf;
112/*264*/ volatile unsigned int matchc; /* Buffer C(YZ) Match Mask */ 139 /* Depth Cue Scale Front Bound */
113/*268*/ volatile unsigned int magnab; /* Buffer AB Magnitude Mask */ 140 /*234*/ volatile unsigned int dcsb;
114/*26c*/ volatile unsigned int magnc; /* Buffer C(YZ) Magnitude Mask */ 141 /* Depth Cue Scale Back Bound */
115/*270*/ volatile unsigned int fbcfg0; /* Frame Buffer Config 0 */ 142 /*238*/ volatile unsigned int dczf;
116/*274*/ volatile unsigned int fbcfg1; /* Frame Buffer Config 1 */ 143 /* Depth Cue Z Front */
117/*278*/ volatile unsigned int fbcfg2; /* Frame Buffer Config 2 */ 144 /*23c*/ volatile unsigned int dczb;
118/*27c*/ volatile unsigned int fbcfg3; /* Frame Buffer Config 3 */ 145 /* Depth Cue Z Back */
119/*280*/ volatile unsigned int ppcfg; /* Pixel Processor Config */ 146 /*240*/ unsigned int pad9;
120/*284*/ volatile unsigned int pick; /* Picking Control */ 147 /* Reserved */
121/*288*/ volatile unsigned int fillmode; /* FillMode */ 148 /*244*/ volatile unsigned int blendc;
122/*28c*/ volatile unsigned int fbramwac; /* FB RAM Write Address Control */ 149 /* Alpha Blend Control */
123/*290*/ volatile unsigned int pmask; /* RGB PlaneMask */ 150 /*248*/ volatile unsigned int blendc1;
124/*294*/ volatile unsigned int xpmask; /* X PlaneMask */ 151 /* Alpha Blend Color 1 */
125/*298*/ volatile unsigned int ypmask; /* Y PlaneMask */ 152 /*24c*/ volatile unsigned int blendc2;
126/*29c*/ volatile unsigned int zpmask; /* Z PlaneMask */ 153 /* Alpha Blend Color 2 */
127/*2a0*/ ffb_auxclip auxclip[4]; /* Auxilliary Viewport Clip */ 154 /*250*/ volatile unsigned int fbramitc;
128 155 /* FB RAM Interleave Test Control */
156 /*254*/ volatile unsigned int fbc;
157 /* Frame Buffer Control */
158 /*258*/ volatile unsigned int rop;
159 /* Raster OPeration */
160 /*25c*/ volatile unsigned int cmp;
161 /* Frame Buffer Compare */
162 /*260*/ volatile unsigned int matchab;
163 /* Buffer AB Match Mask */
164 /*264*/ volatile unsigned int matchc;
165 /* Buffer C(YZ) Match Mask */
166 /*268*/ volatile unsigned int magnab;
167 /* Buffer AB Magnitude Mask */
168 /*26c*/ volatile unsigned int magnc;
169 /* Buffer C(YZ) Magnitude Mask */
170 /*270*/ volatile unsigned int fbcfg0;
171 /* Frame Buffer Config 0 */
172 /*274*/ volatile unsigned int fbcfg1;
173 /* Frame Buffer Config 1 */
174 /*278*/ volatile unsigned int fbcfg2;
175 /* Frame Buffer Config 2 */
176 /*27c*/ volatile unsigned int fbcfg3;
177 /* Frame Buffer Config 3 */
178 /*280*/ volatile unsigned int ppcfg;
179 /* Pixel Processor Config */
180 /*284*/ volatile unsigned int pick;
181 /* Picking Control */
182 /*288*/ volatile unsigned int fillmode;
183 /* FillMode */
184 /*28c*/ volatile unsigned int fbramwac;
185 /* FB RAM Write Address Control */
186 /*290*/ volatile unsigned int pmask;
187 /* RGB PlaneMask */
188 /*294*/ volatile unsigned int xpmask;
189 /* X PlaneMask */
190 /*298*/ volatile unsigned int ypmask;
191 /* Y PlaneMask */
192 /*29c*/ volatile unsigned int zpmask;
193 /* Z PlaneMask */
194 /*2a0*/ ffb_auxclip auxclip[4];
195 /* Auxilliary Viewport Clip */
196
129 /* New 3dRAM III support regs */ 197 /* New 3dRAM III support regs */
130/*2c0*/ volatile unsigned int rawblend2; 198/*2c0*/ volatile unsigned int rawblend2;
131/*2c4*/ volatile unsigned int rawpreblend; 199/*2c4*/ volatile unsigned int rawpreblend;
132/*2c8*/ volatile unsigned int rawstencil; 200/*2c8*/ volatile unsigned int rawstencil;
133/*2cc*/ volatile unsigned int rawstencilctl; 201/*2cc*/ volatile unsigned int rawstencilctl;
134/*2d0*/ volatile unsigned int threedram1; 202/*2d0*/ volatile unsigned int threedram1;
135/*2d4*/ volatile unsigned int threedram2; 203/*2d4*/ volatile unsigned int threedram2;
136/*2d8*/ volatile unsigned int passin; 204/*2d8*/ volatile unsigned int passin;
137/*2dc*/ volatile unsigned int rawclrdepth; 205/*2dc*/ volatile unsigned int rawclrdepth;
138/*2e0*/ volatile unsigned int rawpmask; 206/*2e0*/ volatile unsigned int rawpmask;
139/*2e4*/ volatile unsigned int rawcsrc; 207/*2e4*/ volatile unsigned int rawcsrc;
140/*2e8*/ volatile unsigned int rawmatch; 208/*2e8*/ volatile unsigned int rawmatch;
141/*2ec*/ volatile unsigned int rawmagn; 209/*2ec*/ volatile unsigned int rawmagn;
142/*2f0*/ volatile unsigned int rawropblend; 210/*2f0*/ volatile unsigned int rawropblend;
143/*2f4*/ volatile unsigned int rawcmp; 211/*2f4*/ volatile unsigned int rawcmp;
144/*2f8*/ volatile unsigned int rawwac; 212/*2f8*/ volatile unsigned int rawwac;
145/*2fc*/ volatile unsigned int fbramid; 213/*2fc*/ volatile unsigned int fbramid;
146 214
147/*300*/ volatile unsigned int drawop; /* Draw OPeration */ 215 /*300*/ volatile unsigned int drawop;
148/*304*/ unsigned int pad10[2]; /* Reserved */ 216 /* Draw OPeration */
149/*30c*/ volatile unsigned int lpat; /* Line Pattern control */ 217 /*304*/ unsigned int pad10[2];
150/*310*/ unsigned int pad11; /* Reserved */ 218 /* Reserved */
151/*314*/ volatile unsigned int fontxy; /* XY Font coordinate */ 219 /*30c*/ volatile unsigned int lpat;
152/*318*/ volatile unsigned int fontw; /* Font Width */ 220 /* Line Pattern control */
153/*31c*/ volatile unsigned int fontinc; /* Font Increment */ 221 /*310*/ unsigned int pad11;
154/*320*/ volatile unsigned int font; /* Font bits */ 222 /* Reserved */
155/*324*/ unsigned int pad12[3]; /* Reserved */ 223 /*314*/ volatile unsigned int fontxy;
156/*330*/ volatile unsigned int blend2; 224 /* XY Font coordinate */
157/*334*/ volatile unsigned int preblend; 225 /*318*/ volatile unsigned int fontw;
158/*338*/ volatile unsigned int stencil; 226 /* Font Width */
159/*33c*/ volatile unsigned int stencilctl; 227 /*31c*/ volatile unsigned int fontinc;
228 /* Font Increment */
229 /*320*/ volatile unsigned int font;
230 /* Font bits */
231 /*324*/ unsigned int pad12[3];
232 /* Reserved */
233/*330*/ volatile unsigned int blend2;
234/*334*/ volatile unsigned int preblend;
235/*338*/ volatile unsigned int stencil;
236/*33c*/ volatile unsigned int stencilctl;
160 237
161/*340*/ unsigned int pad13[4]; /* Reserved */ 238 /*340*/ unsigned int pad13[4];
162/*350*/ volatile unsigned int dcss1; /* Depth Cue Scale Slope 1 */ 239 /* Reserved */
163/*354*/ volatile unsigned int dcss2; /* Depth Cue Scale Slope 2 */ 240 /*350*/ volatile unsigned int dcss1;
164/*358*/ volatile unsigned int dcss3; /* Depth Cue Scale Slope 3 */ 241 /* Depth Cue Scale Slope 1 */
165/*35c*/ volatile unsigned int widpmask; 242 /*354*/ volatile unsigned int dcss2;
166/*360*/ volatile unsigned int dcs2; 243 /* Depth Cue Scale Slope 2 */
167/*364*/ volatile unsigned int dcs3; 244 /*358*/ volatile unsigned int dcss3;
168/*368*/ volatile unsigned int dcs4; 245 /* Depth Cue Scale Slope 3 */
169/*36c*/ unsigned int pad14; /* Reserved */ 246/*35c*/ volatile unsigned int widpmask;
170/*370*/ volatile unsigned int dcd2; 247/*360*/ volatile unsigned int dcs2;
171/*374*/ volatile unsigned int dcd3; 248/*364*/ volatile unsigned int dcs3;
172/*378*/ volatile unsigned int dcd4; 249/*368*/ volatile unsigned int dcs4;
173/*37c*/ unsigned int pad15; /* Reserved */ 250 /*36c*/ unsigned int pad14;
174/*380*/ volatile unsigned int pattern[32]; /* area Pattern */ 251 /* Reserved */
175/*400*/ unsigned int pad16[8]; /* Reserved */ 252/*370*/ volatile unsigned int dcd2;
176/*420*/ volatile unsigned int reset; /* chip RESET */ 253/*374*/ volatile unsigned int dcd3;
177/*424*/ unsigned int pad17[247]; /* Reserved */ 254/*378*/ volatile unsigned int dcd4;
178/*800*/ volatile unsigned int devid; /* Device ID */ 255 /*37c*/ unsigned int pad15;
179/*804*/ unsigned int pad18[63]; /* Reserved */ 256 /* Reserved */
180/*900*/ volatile unsigned int ucsr; /* User Control & Status Register */ 257 /*380*/ volatile unsigned int pattern[32];
181/*904*/ unsigned int pad19[31]; /* Reserved */ 258 /* area Pattern */
182/*980*/ volatile unsigned int mer; /* Mode Enable Register */ 259 /*400*/ unsigned int pad16[8];
183/*984*/ unsigned int pad20[1439]; /* Reserved */ 260 /* Reserved */
261 /*420*/ volatile unsigned int reset;
262 /* chip RESET */
263 /*424*/ unsigned int pad17[247];
264 /* Reserved */
265 /*800*/ volatile unsigned int devid;
266 /* Device ID */
267 /*804*/ unsigned int pad18[63];
268 /* Reserved */
269 /*900*/ volatile unsigned int ucsr;
270 /* User Control & Status Register */
271 /*904*/ unsigned int pad19[31];
272 /* Reserved */
273 /*980*/ volatile unsigned int mer;
274 /* Mode Enable Register */
275 /*984*/ unsigned int pad20[1439];
276 /* Reserved */
184} ffb_fbc, *ffb_fbcPtr; 277} ffb_fbc, *ffb_fbcPtr;
185 278
186struct ffb_hw_context { 279struct ffb_hw_context {
@@ -263,16 +356,16 @@ enum ffb_chip_type {
263 356
264typedef struct ffb_dev_priv { 357typedef struct ffb_dev_priv {
265 /* Misc software state. */ 358 /* Misc software state. */
266 int prom_node; 359 int prom_node;
267 enum ffb_chip_type ffb_type; 360 enum ffb_chip_type ffb_type;
268 u64 card_phys_base; 361 u64 card_phys_base;
269 struct miscdevice miscdev; 362 struct miscdevice miscdev;
270 363
271 /* Controller registers. */ 364 /* Controller registers. */
272 ffb_fbcPtr regs; 365 ffb_fbcPtr regs;
273 366
274 /* Context table. */ 367 /* Context table. */
275 struct ffb_hw_context *hw_state[FFB_MAX_CTXS]; 368 struct ffb_hw_context *hw_state[FFB_MAX_CTXS];
276} ffb_dev_priv_t; 369} ffb_dev_priv_t;
277 370
278extern unsigned long ffb_get_unmapped_area(struct file *filp, 371extern unsigned long ffb_get_unmapped_area(struct file *filp,
@@ -283,4 +376,4 @@ extern unsigned long ffb_get_unmapped_area(struct file *filp,
283extern void ffb_set_context_ioctls(void); 376extern void ffb_set_context_ioctls(void);
284extern drm_ioctl_desc_t DRM(ioctls)[]; 377extern drm_ioctl_desc_t DRM(ioctls)[];
285 378
286extern int ffb_driver_context_switch(drm_device_t *dev, int old, int new); 379extern int ffb_driver_context_switch(drm_device_t * dev, int old, int new);
diff --git a/drivers/char/drm/i810_dma.c b/drivers/char/drm/i810_dma.c
index 2f1659b96fd1..810625093c06 100644
--- a/drivers/char/drm/i810_dma.c
+++ b/drivers/char/drm/i810_dma.c
@@ -45,102 +45,101 @@
45#define I810_BUF_UNMAPPED 0 45#define I810_BUF_UNMAPPED 0
46#define I810_BUF_MAPPED 1 46#define I810_BUF_MAPPED 1
47 47
48static drm_buf_t *i810_freelist_get(drm_device_t *dev) 48static drm_buf_t *i810_freelist_get(drm_device_t * dev)
49{ 49{
50 drm_device_dma_t *dma = dev->dma; 50 drm_device_dma_t *dma = dev->dma;
51 int i; 51 int i;
52 int used; 52 int used;
53 53
54 /* Linear search might not be the best solution */ 54 /* Linear search might not be the best solution */
55 55
56 for (i = 0; i < dma->buf_count; i++) { 56 for (i = 0; i < dma->buf_count; i++) {
57 drm_buf_t *buf = dma->buflist[ i ]; 57 drm_buf_t *buf = dma->buflist[i];
58 drm_i810_buf_priv_t *buf_priv = buf->dev_private; 58 drm_i810_buf_priv_t *buf_priv = buf->dev_private;
59 /* In use is already a pointer */ 59 /* In use is already a pointer */
60 used = cmpxchg(buf_priv->in_use, I810_BUF_FREE, 60 used = cmpxchg(buf_priv->in_use, I810_BUF_FREE,
61 I810_BUF_CLIENT); 61 I810_BUF_CLIENT);
62 if (used == I810_BUF_FREE) { 62 if (used == I810_BUF_FREE) {
63 return buf; 63 return buf;
64 } 64 }
65 } 65 }
66 return NULL; 66 return NULL;
67} 67}
68 68
69/* This should only be called if the buffer is not sent to the hardware 69/* This should only be called if the buffer is not sent to the hardware
70 * yet, the hardware updates in use for us once its on the ring buffer. 70 * yet, the hardware updates in use for us once its on the ring buffer.
71 */ 71 */
72 72
73static int i810_freelist_put(drm_device_t *dev, drm_buf_t *buf) 73static int i810_freelist_put(drm_device_t * dev, drm_buf_t * buf)
74{ 74{
75 drm_i810_buf_priv_t *buf_priv = buf->dev_private; 75 drm_i810_buf_priv_t *buf_priv = buf->dev_private;
76 int used; 76 int used;
77 77
78 /* In use is already a pointer */ 78 /* In use is already a pointer */
79 used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE); 79 used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE);
80 if (used != I810_BUF_CLIENT) { 80 if (used != I810_BUF_CLIENT) {
81 DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx); 81 DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
82 return -EINVAL; 82 return -EINVAL;
83 } 83 }
84 84
85 return 0; 85 return 0;
86} 86}
87 87
88static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma) 88static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
89{ 89{
90 drm_file_t *priv = filp->private_data; 90 drm_file_t *priv = filp->private_data;
91 drm_device_t *dev; 91 drm_device_t *dev;
92 drm_i810_private_t *dev_priv; 92 drm_i810_private_t *dev_priv;
93 drm_buf_t *buf; 93 drm_buf_t *buf;
94 drm_i810_buf_priv_t *buf_priv; 94 drm_i810_buf_priv_t *buf_priv;
95 95
96 lock_kernel(); 96 lock_kernel();
97 dev = priv->head->dev; 97 dev = priv->head->dev;
98 dev_priv = dev->dev_private; 98 dev_priv = dev->dev_private;
99 buf = dev_priv->mmap_buffer; 99 buf = dev_priv->mmap_buffer;
100 buf_priv = buf->dev_private; 100 buf_priv = buf->dev_private;
101 101
102 vma->vm_flags |= (VM_IO | VM_DONTCOPY); 102 vma->vm_flags |= (VM_IO | VM_DONTCOPY);
103 vma->vm_file = filp; 103 vma->vm_file = filp;
104 104
105 buf_priv->currently_mapped = I810_BUF_MAPPED; 105 buf_priv->currently_mapped = I810_BUF_MAPPED;
106 unlock_kernel(); 106 unlock_kernel();
107 107
108 if (io_remap_pfn_range(vma, vma->vm_start, 108 if (io_remap_pfn_range(vma, vma->vm_start,
109 VM_OFFSET(vma) >> PAGE_SHIFT, 109 VM_OFFSET(vma) >> PAGE_SHIFT,
110 vma->vm_end - vma->vm_start, 110 vma->vm_end - vma->vm_start, vma->vm_page_prot))
111 vma->vm_page_prot)) return -EAGAIN; 111 return -EAGAIN;
112 return 0; 112 return 0;
113} 113}
114 114
115static struct file_operations i810_buffer_fops = { 115static struct file_operations i810_buffer_fops = {
116 .open = drm_open, 116 .open = drm_open,
117 .flush = drm_flush, 117 .flush = drm_flush,
118 .release = drm_release, 118 .release = drm_release,
119 .ioctl = drm_ioctl, 119 .ioctl = drm_ioctl,
120 .mmap = i810_mmap_buffers, 120 .mmap = i810_mmap_buffers,
121 .fasync = drm_fasync, 121 .fasync = drm_fasync,
122}; 122};
123 123
124static int i810_map_buffer(drm_buf_t *buf, struct file *filp) 124static int i810_map_buffer(drm_buf_t * buf, struct file *filp)
125{ 125{
126 drm_file_t *priv = filp->private_data; 126 drm_file_t *priv = filp->private_data;
127 drm_device_t *dev = priv->head->dev; 127 drm_device_t *dev = priv->head->dev;
128 drm_i810_buf_priv_t *buf_priv = buf->dev_private; 128 drm_i810_buf_priv_t *buf_priv = buf->dev_private;
129 drm_i810_private_t *dev_priv = dev->dev_private; 129 drm_i810_private_t *dev_priv = dev->dev_private;
130 struct file_operations *old_fops; 130 struct file_operations *old_fops;
131 int retcode = 0; 131 int retcode = 0;
132 132
133 if (buf_priv->currently_mapped == I810_BUF_MAPPED) 133 if (buf_priv->currently_mapped == I810_BUF_MAPPED)
134 return -EINVAL; 134 return -EINVAL;
135 135
136 down_write( &current->mm->mmap_sem ); 136 down_write(&current->mm->mmap_sem);
137 old_fops = filp->f_op; 137 old_fops = filp->f_op;
138 filp->f_op = &i810_buffer_fops; 138 filp->f_op = &i810_buffer_fops;
139 dev_priv->mmap_buffer = buf; 139 dev_priv->mmap_buffer = buf;
140 buf_priv->virtual = (void *)do_mmap(filp, 0, buf->total, 140 buf_priv->virtual = (void *)do_mmap(filp, 0, buf->total,
141 PROT_READ|PROT_WRITE, 141 PROT_READ | PROT_WRITE,
142 MAP_SHARED, 142 MAP_SHARED, buf->bus_address);
143 buf->bus_address);
144 dev_priv->mmap_buffer = NULL; 143 dev_priv->mmap_buffer = NULL;
145 filp->f_op = old_fops; 144 filp->f_op = old_fops;
146 if ((unsigned long)buf_priv->virtual > -1024UL) { 145 if ((unsigned long)buf_priv->virtual > -1024UL) {
@@ -149,12 +148,12 @@ static int i810_map_buffer(drm_buf_t *buf, struct file *filp)
149 retcode = (signed int)buf_priv->virtual; 148 retcode = (signed int)buf_priv->virtual;
150 buf_priv->virtual = NULL; 149 buf_priv->virtual = NULL;
151 } 150 }
152 up_write( &current->mm->mmap_sem ); 151 up_write(&current->mm->mmap_sem);
153 152
154 return retcode; 153 return retcode;
155} 154}
156 155
157static int i810_unmap_buffer(drm_buf_t *buf) 156static int i810_unmap_buffer(drm_buf_t * buf)
158{ 157{
159 drm_i810_buf_priv_t *buf_priv = buf->dev_private; 158 drm_i810_buf_priv_t *buf_priv = buf->dev_private;
160 int retcode = 0; 159 int retcode = 0;
@@ -168,43 +167,43 @@ static int i810_unmap_buffer(drm_buf_t *buf)
168 (size_t) buf->total); 167 (size_t) buf->total);
169 up_write(&current->mm->mmap_sem); 168 up_write(&current->mm->mmap_sem);
170 169
171 buf_priv->currently_mapped = I810_BUF_UNMAPPED; 170 buf_priv->currently_mapped = I810_BUF_UNMAPPED;
172 buf_priv->virtual = NULL; 171 buf_priv->virtual = NULL;
173 172
174 return retcode; 173 return retcode;
175} 174}
176 175
177static int i810_dma_get_buffer(drm_device_t *dev, drm_i810_dma_t *d, 176static int i810_dma_get_buffer(drm_device_t * dev, drm_i810_dma_t * d,
178 struct file *filp) 177 struct file *filp)
179{ 178{
180 drm_buf_t *buf; 179 drm_buf_t *buf;
181 drm_i810_buf_priv_t *buf_priv; 180 drm_i810_buf_priv_t *buf_priv;
182 int retcode = 0; 181 int retcode = 0;
183 182
184 buf = i810_freelist_get(dev); 183 buf = i810_freelist_get(dev);
185 if (!buf) { 184 if (!buf) {
186 retcode = -ENOMEM; 185 retcode = -ENOMEM;
187 DRM_DEBUG("retcode=%d\n", retcode); 186 DRM_DEBUG("retcode=%d\n", retcode);
188 return retcode; 187 return retcode;
189 } 188 }
190 189
191 retcode = i810_map_buffer(buf, filp); 190 retcode = i810_map_buffer(buf, filp);
192 if (retcode) { 191 if (retcode) {
193 i810_freelist_put(dev, buf); 192 i810_freelist_put(dev, buf);
194 DRM_ERROR("mapbuf failed, retcode %d\n", retcode); 193 DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
195 return retcode; 194 return retcode;
196 } 195 }
197 buf->filp = filp; 196 buf->filp = filp;
198 buf_priv = buf->dev_private; 197 buf_priv = buf->dev_private;
199 d->granted = 1; 198 d->granted = 1;
200 d->request_idx = buf->idx; 199 d->request_idx = buf->idx;
201 d->request_size = buf->total; 200 d->request_size = buf->total;
202 d->virtual = buf_priv->virtual; 201 d->virtual = buf_priv->virtual;
203 202
204 return retcode; 203 return retcode;
205} 204}
206 205
207static int i810_dma_cleanup(drm_device_t *dev) 206static int i810_dma_cleanup(drm_device_t * dev)
208{ 207{
209 drm_device_dma_t *dma = dev->dma; 208 drm_device_dma_t *dma = dev->dma;
210 209
@@ -217,165 +216,167 @@ static int i810_dma_cleanup(drm_device_t *dev)
217 216
218 if (dev->dev_private) { 217 if (dev->dev_private) {
219 int i; 218 int i;
220 drm_i810_private_t *dev_priv = 219 drm_i810_private_t *dev_priv =
221 (drm_i810_private_t *) dev->dev_private; 220 (drm_i810_private_t *) dev->dev_private;
222 221
223 if (dev_priv->ring.virtual_start) { 222 if (dev_priv->ring.virtual_start) {
224 drm_ioremapfree((void *) dev_priv->ring.virtual_start, 223 drm_ioremapfree((void *)dev_priv->ring.virtual_start,
225 dev_priv->ring.Size, dev); 224 dev_priv->ring.Size, dev);
226 } 225 }
227 if (dev_priv->hw_status_page) { 226 if (dev_priv->hw_status_page) {
228 pci_free_consistent(dev->pdev, PAGE_SIZE, 227 pci_free_consistent(dev->pdev, PAGE_SIZE,
229 dev_priv->hw_status_page, 228 dev_priv->hw_status_page,
230 dev_priv->dma_status_page); 229 dev_priv->dma_status_page);
231 /* Need to rewrite hardware status page */ 230 /* Need to rewrite hardware status page */
232 I810_WRITE(0x02080, 0x1ffff000); 231 I810_WRITE(0x02080, 0x1ffff000);
233 } 232 }
234 drm_free(dev->dev_private, sizeof(drm_i810_private_t), 233 drm_free(dev->dev_private, sizeof(drm_i810_private_t),
235 DRM_MEM_DRIVER); 234 DRM_MEM_DRIVER);
236 dev->dev_private = NULL; 235 dev->dev_private = NULL;
237 236
238 for (i = 0; i < dma->buf_count; i++) { 237 for (i = 0; i < dma->buf_count; i++) {
239 drm_buf_t *buf = dma->buflist[ i ]; 238 drm_buf_t *buf = dma->buflist[i];
240 drm_i810_buf_priv_t *buf_priv = buf->dev_private; 239 drm_i810_buf_priv_t *buf_priv = buf->dev_private;
241 if ( buf_priv->kernel_virtual && buf->total ) 240 if (buf_priv->kernel_virtual && buf->total)
242 drm_ioremapfree(buf_priv->kernel_virtual, buf->total, dev); 241 drm_ioremapfree(buf_priv->kernel_virtual,
242 buf->total, dev);
243 } 243 }
244 } 244 }
245 return 0; 245 return 0;
246} 246}
247 247
248static int i810_wait_ring(drm_device_t *dev, int n) 248static int i810_wait_ring(drm_device_t * dev, int n)
249{ 249{
250 drm_i810_private_t *dev_priv = dev->dev_private; 250 drm_i810_private_t *dev_priv = dev->dev_private;
251 drm_i810_ring_buffer_t *ring = &(dev_priv->ring); 251 drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
252 int iters = 0; 252 int iters = 0;
253 unsigned long end; 253 unsigned long end;
254 unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; 254 unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
255 255
256 end = jiffies + (HZ*3); 256 end = jiffies + (HZ * 3);
257 while (ring->space < n) { 257 while (ring->space < n) {
258 ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; 258 ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
259 ring->space = ring->head - (ring->tail+8); 259 ring->space = ring->head - (ring->tail + 8);
260 if (ring->space < 0) ring->space += ring->Size; 260 if (ring->space < 0)
261 261 ring->space += ring->Size;
262
262 if (ring->head != last_head) { 263 if (ring->head != last_head) {
263 end = jiffies + (HZ*3); 264 end = jiffies + (HZ * 3);
264 last_head = ring->head; 265 last_head = ring->head;
265 } 266 }
266 267
267 iters++; 268 iters++;
268 if (time_before(end, jiffies)) { 269 if (time_before(end, jiffies)) {
269 DRM_ERROR("space: %d wanted %d\n", ring->space, n); 270 DRM_ERROR("space: %d wanted %d\n", ring->space, n);
270 DRM_ERROR("lockup\n"); 271 DRM_ERROR("lockup\n");
271 goto out_wait_ring; 272 goto out_wait_ring;
272 } 273 }
273 udelay(1); 274 udelay(1);
274 } 275 }
275 276
276out_wait_ring: 277 out_wait_ring:
277 return iters; 278 return iters;
278} 279}
279 280
280static void i810_kernel_lost_context(drm_device_t *dev) 281static void i810_kernel_lost_context(drm_device_t * dev)
281{ 282{
282 drm_i810_private_t *dev_priv = dev->dev_private; 283 drm_i810_private_t *dev_priv = dev->dev_private;
283 drm_i810_ring_buffer_t *ring = &(dev_priv->ring); 284 drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
284 285
285 ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; 286 ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
286 ring->tail = I810_READ(LP_RING + RING_TAIL); 287 ring->tail = I810_READ(LP_RING + RING_TAIL);
287 ring->space = ring->head - (ring->tail+8); 288 ring->space = ring->head - (ring->tail + 8);
288 if (ring->space < 0) ring->space += ring->Size; 289 if (ring->space < 0)
290 ring->space += ring->Size;
289} 291}
290 292
291static int i810_freelist_init(drm_device_t *dev, drm_i810_private_t *dev_priv) 293static int i810_freelist_init(drm_device_t * dev, drm_i810_private_t * dev_priv)
292{ 294{
293 drm_device_dma_t *dma = dev->dma; 295 drm_device_dma_t *dma = dev->dma;
294 int my_idx = 24; 296 int my_idx = 24;
295 u32 *hw_status = (u32 *)(dev_priv->hw_status_page + my_idx); 297 u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx);
296 int i; 298 int i;
297 299
298 if (dma->buf_count > 1019) { 300 if (dma->buf_count > 1019) {
299 /* Not enough space in the status page for the freelist */ 301 /* Not enough space in the status page for the freelist */
300 return -EINVAL; 302 return -EINVAL;
301 } 303 }
302 304
303 for (i = 0; i < dma->buf_count; i++) { 305 for (i = 0; i < dma->buf_count; i++) {
304 drm_buf_t *buf = dma->buflist[ i ]; 306 drm_buf_t *buf = dma->buflist[i];
305 drm_i810_buf_priv_t *buf_priv = buf->dev_private; 307 drm_i810_buf_priv_t *buf_priv = buf->dev_private;
306 308
307 buf_priv->in_use = hw_status++; 309 buf_priv->in_use = hw_status++;
308 buf_priv->my_use_idx = my_idx; 310 buf_priv->my_use_idx = my_idx;
309 my_idx += 4; 311 my_idx += 4;
310 312
311 *buf_priv->in_use = I810_BUF_FREE; 313 *buf_priv->in_use = I810_BUF_FREE;
312 314
313 buf_priv->kernel_virtual = drm_ioremap(buf->bus_address, 315 buf_priv->kernel_virtual = drm_ioremap(buf->bus_address,
314 buf->total, dev); 316 buf->total, dev);
315 } 317 }
316 return 0; 318 return 0;
317} 319}
318 320
319static int i810_dma_initialize(drm_device_t *dev, 321static int i810_dma_initialize(drm_device_t * dev,
320 drm_i810_private_t *dev_priv, 322 drm_i810_private_t * dev_priv,
321 drm_i810_init_t *init) 323 drm_i810_init_t * init)
322{ 324{
323 struct list_head *list; 325 struct list_head *list;
324 326
325 memset(dev_priv, 0, sizeof(drm_i810_private_t)); 327 memset(dev_priv, 0, sizeof(drm_i810_private_t));
326 328
327 list_for_each(list, &dev->maplist->head) { 329 list_for_each(list, &dev->maplist->head) {
328 drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head); 330 drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head);
329 if (r_list->map && 331 if (r_list->map &&
330 r_list->map->type == _DRM_SHM && 332 r_list->map->type == _DRM_SHM &&
331 r_list->map->flags & _DRM_CONTAINS_LOCK ) { 333 r_list->map->flags & _DRM_CONTAINS_LOCK) {
332 dev_priv->sarea_map = r_list->map; 334 dev_priv->sarea_map = r_list->map;
333 break; 335 break;
334 } 336 }
335 } 337 }
336 if (!dev_priv->sarea_map) { 338 if (!dev_priv->sarea_map) {
337 dev->dev_private = (void *)dev_priv; 339 dev->dev_private = (void *)dev_priv;
338 i810_dma_cleanup(dev); 340 i810_dma_cleanup(dev);
339 DRM_ERROR("can not find sarea!\n"); 341 DRM_ERROR("can not find sarea!\n");
340 return -EINVAL; 342 return -EINVAL;
341 } 343 }
342 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset); 344 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
343 if (!dev_priv->mmio_map) { 345 if (!dev_priv->mmio_map) {
344 dev->dev_private = (void *)dev_priv; 346 dev->dev_private = (void *)dev_priv;
345 i810_dma_cleanup(dev); 347 i810_dma_cleanup(dev);
346 DRM_ERROR("can not find mmio map!\n"); 348 DRM_ERROR("can not find mmio map!\n");
347 return -EINVAL; 349 return -EINVAL;
348 } 350 }
349 dev->agp_buffer_token = init->buffers_offset; 351 dev->agp_buffer_token = init->buffers_offset;
350 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 352 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
351 if (!dev->agp_buffer_map) { 353 if (!dev->agp_buffer_map) {
352 dev->dev_private = (void *)dev_priv; 354 dev->dev_private = (void *)dev_priv;
353 i810_dma_cleanup(dev); 355 i810_dma_cleanup(dev);
354 DRM_ERROR("can not find dma buffer map!\n"); 356 DRM_ERROR("can not find dma buffer map!\n");
355 return -EINVAL; 357 return -EINVAL;
356 } 358 }
357 359
358 dev_priv->sarea_priv = (drm_i810_sarea_t *) 360 dev_priv->sarea_priv = (drm_i810_sarea_t *)
359 ((u8 *)dev_priv->sarea_map->handle + 361 ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset);
360 init->sarea_priv_offset);
361 362
362 dev_priv->ring.Start = init->ring_start; 363 dev_priv->ring.Start = init->ring_start;
363 dev_priv->ring.End = init->ring_end; 364 dev_priv->ring.End = init->ring_end;
364 dev_priv->ring.Size = init->ring_size; 365 dev_priv->ring.Size = init->ring_size;
365 366
366 dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base + 367 dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base +
367 init->ring_start, 368 init->ring_start,
368 init->ring_size, dev); 369 init->ring_size, dev);
369 370
370 if (dev_priv->ring.virtual_start == NULL) { 371 if (dev_priv->ring.virtual_start == NULL) {
371 dev->dev_private = (void *) dev_priv; 372 dev->dev_private = (void *)dev_priv;
372 i810_dma_cleanup(dev); 373 i810_dma_cleanup(dev);
373 DRM_ERROR("can not ioremap virtual address for" 374 DRM_ERROR("can not ioremap virtual address for"
374 " ring buffer\n"); 375 " ring buffer\n");
375 return -ENOMEM; 376 return -ENOMEM;
376 } 377 }
377 378
378 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; 379 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
379 380
380 dev_priv->w = init->w; 381 dev_priv->w = init->w;
381 dev_priv->h = init->h; 382 dev_priv->h = init->h;
@@ -391,33 +392,33 @@ static int i810_dma_initialize(drm_device_t *dev,
391 dev_priv->back_di1 = init->back_offset | init->pitch_bits; 392 dev_priv->back_di1 = init->back_offset | init->pitch_bits;
392 dev_priv->zi1 = init->depth_offset | init->pitch_bits; 393 dev_priv->zi1 = init->depth_offset | init->pitch_bits;
393 394
394 /* Program Hardware Status Page */ 395 /* Program Hardware Status Page */
395 dev_priv->hw_status_page = 396 dev_priv->hw_status_page =
396 pci_alloc_consistent(dev->pdev, PAGE_SIZE, 397 pci_alloc_consistent(dev->pdev, PAGE_SIZE,
397 &dev_priv->dma_status_page); 398 &dev_priv->dma_status_page);
398 if (!dev_priv->hw_status_page) { 399 if (!dev_priv->hw_status_page) {
399 dev->dev_private = (void *)dev_priv; 400 dev->dev_private = (void *)dev_priv;
400 i810_dma_cleanup(dev); 401 i810_dma_cleanup(dev);
401 DRM_ERROR("Can not allocate hardware status page\n"); 402 DRM_ERROR("Can not allocate hardware status page\n");
402 return -ENOMEM; 403 return -ENOMEM;
403 } 404 }
404 memset(dev_priv->hw_status_page, 0, PAGE_SIZE); 405 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
405 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); 406 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
406 407
407 I810_WRITE(0x02080, dev_priv->dma_status_page); 408 I810_WRITE(0x02080, dev_priv->dma_status_page);
408 DRM_DEBUG("Enabled hardware status page\n"); 409 DRM_DEBUG("Enabled hardware status page\n");
409 410
410 /* Now we need to init our freelist */ 411 /* Now we need to init our freelist */
411 if (i810_freelist_init(dev, dev_priv) != 0) { 412 if (i810_freelist_init(dev, dev_priv) != 0) {
412 dev->dev_private = (void *)dev_priv; 413 dev->dev_private = (void *)dev_priv;
413 i810_dma_cleanup(dev); 414 i810_dma_cleanup(dev);
414 DRM_ERROR("Not enough space in the status page for" 415 DRM_ERROR("Not enough space in the status page for"
415 " the freelist\n"); 416 " the freelist\n");
416 return -ENOMEM; 417 return -ENOMEM;
417 } 418 }
418 dev->dev_private = (void *)dev_priv; 419 dev->dev_private = (void *)dev_priv;
419 420
420 return 0; 421 return 0;
421} 422}
422 423
423/* i810 DRM version 1.1 used a smaller init structure with different 424/* i810 DRM version 1.1 used a smaller init structure with different
@@ -431,12 +432,12 @@ static int i810_dma_initialize(drm_device_t *dev,
431 * If it isn't then we have a v1.1 client. Fix up params. 432 * If it isn't then we have a v1.1 client. Fix up params.
432 * If it is, then we have a 1.2 client... get the rest of the data. 433 * If it is, then we have a 1.2 client... get the rest of the data.
433 */ 434 */
434static int i810_dma_init_compat(drm_i810_init_t *init, unsigned long arg) 435static int i810_dma_init_compat(drm_i810_init_t * init, unsigned long arg)
435{ 436{
436 437
437 /* Get v1.1 init data */ 438 /* Get v1.1 init data */
438 if (copy_from_user(init, (drm_i810_pre12_init_t __user *)arg, 439 if (copy_from_user(init, (drm_i810_pre12_init_t __user *) arg,
439 sizeof(drm_i810_pre12_init_t))) { 440 sizeof(drm_i810_pre12_init_t))) {
440 return -EFAULT; 441 return -EFAULT;
441 } 442 }
442 443
@@ -444,7 +445,7 @@ static int i810_dma_init_compat(drm_i810_init_t *init, unsigned long arg)
444 445
445 /* This is a v1.2 client, just get the v1.2 init data */ 446 /* This is a v1.2 client, just get the v1.2 init data */
446 DRM_INFO("Using POST v1.2 init.\n"); 447 DRM_INFO("Using POST v1.2 init.\n");
447 if (copy_from_user(init, (drm_i810_init_t __user *)arg, 448 if (copy_from_user(init, (drm_i810_init_t __user *) arg,
448 sizeof(drm_i810_init_t))) { 449 sizeof(drm_i810_init_t))) {
449 return -EFAULT; 450 return -EFAULT;
450 } 451 }
@@ -452,246 +453,239 @@ static int i810_dma_init_compat(drm_i810_init_t *init, unsigned long arg)
452 453
453 /* This is a v1.1 client, fix the params */ 454 /* This is a v1.1 client, fix the params */
454 DRM_INFO("Using PRE v1.2 init.\n"); 455 DRM_INFO("Using PRE v1.2 init.\n");
455 init->pitch_bits = init->h; 456 init->pitch_bits = init->h;
456 init->pitch = init->w; 457 init->pitch = init->w;
457 init->h = init->overlay_physical; 458 init->h = init->overlay_physical;
458 init->w = init->overlay_offset; 459 init->w = init->overlay_offset;
459 init->overlay_physical = 0; 460 init->overlay_physical = 0;
460 init->overlay_offset = 0; 461 init->overlay_offset = 0;
461 } 462 }
462 463
463 return 0; 464 return 0;
464} 465}
465 466
466static int i810_dma_init(struct inode *inode, struct file *filp, 467static int i810_dma_init(struct inode *inode, struct file *filp,
467 unsigned int cmd, unsigned long arg) 468 unsigned int cmd, unsigned long arg)
468{ 469{
469 drm_file_t *priv = filp->private_data; 470 drm_file_t *priv = filp->private_data;
470 drm_device_t *dev = priv->head->dev; 471 drm_device_t *dev = priv->head->dev;
471 drm_i810_private_t *dev_priv; 472 drm_i810_private_t *dev_priv;
472 drm_i810_init_t init; 473 drm_i810_init_t init;
473 int retcode = 0; 474 int retcode = 0;
474 475
475 /* Get only the init func */ 476 /* Get only the init func */
476 if (copy_from_user(&init, (void __user *)arg, sizeof(drm_i810_init_func_t))) 477 if (copy_from_user
478 (&init, (void __user *)arg, sizeof(drm_i810_init_func_t)))
477 return -EFAULT; 479 return -EFAULT;
478 480
479 switch(init.func) { 481 switch (init.func) {
480 case I810_INIT_DMA: 482 case I810_INIT_DMA:
481 /* This case is for backward compatibility. It 483 /* This case is for backward compatibility. It
482 * handles XFree 4.1.0 and 4.2.0, and has to 484 * handles XFree 4.1.0 and 4.2.0, and has to
483 * do some parameter checking as described below. 485 * do some parameter checking as described below.
484 * It will someday go away. 486 * It will someday go away.
485 */ 487 */
486 retcode = i810_dma_init_compat(&init, arg); 488 retcode = i810_dma_init_compat(&init, arg);
487 if (retcode) 489 if (retcode)
488 return retcode; 490 return retcode;
489 491
490 dev_priv = drm_alloc(sizeof(drm_i810_private_t), 492 dev_priv = drm_alloc(sizeof(drm_i810_private_t),
491 DRM_MEM_DRIVER); 493 DRM_MEM_DRIVER);
492 if (dev_priv == NULL) 494 if (dev_priv == NULL)
493 return -ENOMEM; 495 return -ENOMEM;
494 retcode = i810_dma_initialize(dev, dev_priv, &init); 496 retcode = i810_dma_initialize(dev, dev_priv, &init);
495 break; 497 break;
496 498
497 default: 499 default:
498 case I810_INIT_DMA_1_4: 500 case I810_INIT_DMA_1_4:
499 DRM_INFO("Using v1.4 init.\n"); 501 DRM_INFO("Using v1.4 init.\n");
500 if (copy_from_user(&init, (drm_i810_init_t __user *)arg, 502 if (copy_from_user(&init, (drm_i810_init_t __user *) arg,
501 sizeof(drm_i810_init_t))) { 503 sizeof(drm_i810_init_t))) {
502 return -EFAULT; 504 return -EFAULT;
503 } 505 }
504 dev_priv = drm_alloc(sizeof(drm_i810_private_t), 506 dev_priv = drm_alloc(sizeof(drm_i810_private_t),
505 DRM_MEM_DRIVER); 507 DRM_MEM_DRIVER);
506 if (dev_priv == NULL) 508 if (dev_priv == NULL)
507 return -ENOMEM; 509 return -ENOMEM;
508 retcode = i810_dma_initialize(dev, dev_priv, &init); 510 retcode = i810_dma_initialize(dev, dev_priv, &init);
509 break; 511 break;
510 512
511 case I810_CLEANUP_DMA: 513 case I810_CLEANUP_DMA:
512 DRM_INFO("DMA Cleanup\n"); 514 DRM_INFO("DMA Cleanup\n");
513 retcode = i810_dma_cleanup(dev); 515 retcode = i810_dma_cleanup(dev);
514 break; 516 break;
515 } 517 }
516 518
517 return retcode; 519 return retcode;
518} 520}
519 521
520
521
522/* Most efficient way to verify state for the i810 is as it is 522/* Most efficient way to verify state for the i810 is as it is
523 * emitted. Non-conformant state is silently dropped. 523 * emitted. Non-conformant state is silently dropped.
524 * 524 *
525 * Use 'volatile' & local var tmp to force the emitted values to be 525 * Use 'volatile' & local var tmp to force the emitted values to be
526 * identical to the verified ones. 526 * identical to the verified ones.
527 */ 527 */
528static void i810EmitContextVerified( drm_device_t *dev, 528static void i810EmitContextVerified(drm_device_t * dev,
529 volatile unsigned int *code ) 529 volatile unsigned int *code)
530{ 530{
531 drm_i810_private_t *dev_priv = dev->dev_private; 531 drm_i810_private_t *dev_priv = dev->dev_private;
532 int i, j = 0; 532 int i, j = 0;
533 unsigned int tmp; 533 unsigned int tmp;
534 RING_LOCALS; 534 RING_LOCALS;
535 535
536 BEGIN_LP_RING( I810_CTX_SETUP_SIZE ); 536 BEGIN_LP_RING(I810_CTX_SETUP_SIZE);
537 537
538 OUT_RING( GFX_OP_COLOR_FACTOR ); 538 OUT_RING(GFX_OP_COLOR_FACTOR);
539 OUT_RING( code[I810_CTXREG_CF1] ); 539 OUT_RING(code[I810_CTXREG_CF1]);
540 540
541 OUT_RING( GFX_OP_STIPPLE ); 541 OUT_RING(GFX_OP_STIPPLE);
542 OUT_RING( code[I810_CTXREG_ST1] ); 542 OUT_RING(code[I810_CTXREG_ST1]);
543 543
544 for ( i = 4 ; i < I810_CTX_SETUP_SIZE ; i++ ) { 544 for (i = 4; i < I810_CTX_SETUP_SIZE; i++) {
545 tmp = code[i]; 545 tmp = code[i];
546 546
547 if ((tmp & (7<<29)) == (3<<29) && 547 if ((tmp & (7 << 29)) == (3 << 29) &&
548 (tmp & (0x1f<<24)) < (0x1d<<24)) 548 (tmp & (0x1f << 24)) < (0x1d << 24)) {
549 { 549 OUT_RING(tmp);
550 OUT_RING( tmp );
551 j++; 550 j++;
552 } 551 } else
553 else printk("constext state dropped!!!\n"); 552 printk("constext state dropped!!!\n");
554 } 553 }
555 554
556 if (j & 1) 555 if (j & 1)
557 OUT_RING( 0 ); 556 OUT_RING(0);
558 557
559 ADVANCE_LP_RING(); 558 ADVANCE_LP_RING();
560} 559}
561 560
562static void i810EmitTexVerified( drm_device_t *dev, 561static void i810EmitTexVerified(drm_device_t * dev, volatile unsigned int *code)
563 volatile unsigned int *code )
564{ 562{
565 drm_i810_private_t *dev_priv = dev->dev_private; 563 drm_i810_private_t *dev_priv = dev->dev_private;
566 int i, j = 0; 564 int i, j = 0;
567 unsigned int tmp; 565 unsigned int tmp;
568 RING_LOCALS; 566 RING_LOCALS;
569 567
570 BEGIN_LP_RING( I810_TEX_SETUP_SIZE ); 568 BEGIN_LP_RING(I810_TEX_SETUP_SIZE);
571 569
572 OUT_RING( GFX_OP_MAP_INFO ); 570 OUT_RING(GFX_OP_MAP_INFO);
573 OUT_RING( code[I810_TEXREG_MI1] ); 571 OUT_RING(code[I810_TEXREG_MI1]);
574 OUT_RING( code[I810_TEXREG_MI2] ); 572 OUT_RING(code[I810_TEXREG_MI2]);
575 OUT_RING( code[I810_TEXREG_MI3] ); 573 OUT_RING(code[I810_TEXREG_MI3]);
576 574
577 for ( i = 4 ; i < I810_TEX_SETUP_SIZE ; i++ ) { 575 for (i = 4; i < I810_TEX_SETUP_SIZE; i++) {
578 tmp = code[i]; 576 tmp = code[i];
579 577
580 if ((tmp & (7<<29)) == (3<<29) && 578 if ((tmp & (7 << 29)) == (3 << 29) &&
581 (tmp & (0x1f<<24)) < (0x1d<<24)) 579 (tmp & (0x1f << 24)) < (0x1d << 24)) {
582 { 580 OUT_RING(tmp);
583 OUT_RING( tmp );
584 j++; 581 j++;
585 } 582 } else
586 else printk("texture state dropped!!!\n"); 583 printk("texture state dropped!!!\n");
587 } 584 }
588 585
589 if (j & 1) 586 if (j & 1)
590 OUT_RING( 0 ); 587 OUT_RING(0);
591 588
592 ADVANCE_LP_RING(); 589 ADVANCE_LP_RING();
593} 590}
594 591
595
596/* Need to do some additional checking when setting the dest buffer. 592/* Need to do some additional checking when setting the dest buffer.
597 */ 593 */
598static void i810EmitDestVerified( drm_device_t *dev, 594static void i810EmitDestVerified(drm_device_t * dev,
599 volatile unsigned int *code ) 595 volatile unsigned int *code)
600{ 596{
601 drm_i810_private_t *dev_priv = dev->dev_private; 597 drm_i810_private_t *dev_priv = dev->dev_private;
602 unsigned int tmp; 598 unsigned int tmp;
603 RING_LOCALS; 599 RING_LOCALS;
604 600
605 BEGIN_LP_RING( I810_DEST_SETUP_SIZE + 2 ); 601 BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
606 602
607 tmp = code[I810_DESTREG_DI1]; 603 tmp = code[I810_DESTREG_DI1];
608 if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) { 604 if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
609 OUT_RING( CMD_OP_DESTBUFFER_INFO ); 605 OUT_RING(CMD_OP_DESTBUFFER_INFO);
610 OUT_RING( tmp ); 606 OUT_RING(tmp);
611 } else 607 } else
612 DRM_DEBUG("bad di1 %x (allow %x or %x)\n", 608 DRM_DEBUG("bad di1 %x (allow %x or %x)\n",
613 tmp, dev_priv->front_di1, dev_priv->back_di1); 609 tmp, dev_priv->front_di1, dev_priv->back_di1);
614 610
615 /* invarient: 611 /* invarient:
616 */ 612 */
617 OUT_RING( CMD_OP_Z_BUFFER_INFO ); 613 OUT_RING(CMD_OP_Z_BUFFER_INFO);
618 OUT_RING( dev_priv->zi1 ); 614 OUT_RING(dev_priv->zi1);
619 615
620 OUT_RING( GFX_OP_DESTBUFFER_VARS ); 616 OUT_RING(GFX_OP_DESTBUFFER_VARS);
621 OUT_RING( code[I810_DESTREG_DV1] ); 617 OUT_RING(code[I810_DESTREG_DV1]);
622 618
623 OUT_RING( GFX_OP_DRAWRECT_INFO ); 619 OUT_RING(GFX_OP_DRAWRECT_INFO);
624 OUT_RING( code[I810_DESTREG_DR1] ); 620 OUT_RING(code[I810_DESTREG_DR1]);
625 OUT_RING( code[I810_DESTREG_DR2] ); 621 OUT_RING(code[I810_DESTREG_DR2]);
626 OUT_RING( code[I810_DESTREG_DR3] ); 622 OUT_RING(code[I810_DESTREG_DR3]);
627 OUT_RING( code[I810_DESTREG_DR4] ); 623 OUT_RING(code[I810_DESTREG_DR4]);
628 OUT_RING( 0 ); 624 OUT_RING(0);
629 625
630 ADVANCE_LP_RING(); 626 ADVANCE_LP_RING();
631} 627}
632 628
633 629static void i810EmitState(drm_device_t * dev)
634
635static void i810EmitState( drm_device_t *dev )
636{ 630{
637 drm_i810_private_t *dev_priv = dev->dev_private; 631 drm_i810_private_t *dev_priv = dev->dev_private;
638 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; 632 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
639 unsigned int dirty = sarea_priv->dirty; 633 unsigned int dirty = sarea_priv->dirty;
640 634
641 DRM_DEBUG("%s %x\n", __FUNCTION__, dirty); 635 DRM_DEBUG("%s %x\n", __FUNCTION__, dirty);
642 636
643 if (dirty & I810_UPLOAD_BUFFERS) { 637 if (dirty & I810_UPLOAD_BUFFERS) {
644 i810EmitDestVerified( dev, sarea_priv->BufferState ); 638 i810EmitDestVerified(dev, sarea_priv->BufferState);
645 sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS; 639 sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
646 } 640 }
647 641
648 if (dirty & I810_UPLOAD_CTX) { 642 if (dirty & I810_UPLOAD_CTX) {
649 i810EmitContextVerified( dev, sarea_priv->ContextState ); 643 i810EmitContextVerified(dev, sarea_priv->ContextState);
650 sarea_priv->dirty &= ~I810_UPLOAD_CTX; 644 sarea_priv->dirty &= ~I810_UPLOAD_CTX;
651 } 645 }
652 646
653 if (dirty & I810_UPLOAD_TEX0) { 647 if (dirty & I810_UPLOAD_TEX0) {
654 i810EmitTexVerified( dev, sarea_priv->TexState[0] ); 648 i810EmitTexVerified(dev, sarea_priv->TexState[0]);
655 sarea_priv->dirty &= ~I810_UPLOAD_TEX0; 649 sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
656 } 650 }
657 651
658 if (dirty & I810_UPLOAD_TEX1) { 652 if (dirty & I810_UPLOAD_TEX1) {
659 i810EmitTexVerified( dev, sarea_priv->TexState[1] ); 653 i810EmitTexVerified(dev, sarea_priv->TexState[1]);
660 sarea_priv->dirty &= ~I810_UPLOAD_TEX1; 654 sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
661 } 655 }
662} 656}
663 657
664
665
666/* need to verify 658/* need to verify
667 */ 659 */
668static void i810_dma_dispatch_clear( drm_device_t *dev, int flags, 660static void i810_dma_dispatch_clear(drm_device_t * dev, int flags,
669 unsigned int clear_color, 661 unsigned int clear_color,
670 unsigned int clear_zval ) 662 unsigned int clear_zval)
671{ 663{
672 drm_i810_private_t *dev_priv = dev->dev_private; 664 drm_i810_private_t *dev_priv = dev->dev_private;
673 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; 665 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
674 int nbox = sarea_priv->nbox; 666 int nbox = sarea_priv->nbox;
675 drm_clip_rect_t *pbox = sarea_priv->boxes; 667 drm_clip_rect_t *pbox = sarea_priv->boxes;
676 int pitch = dev_priv->pitch; 668 int pitch = dev_priv->pitch;
677 int cpp = 2; 669 int cpp = 2;
678 int i; 670 int i;
679 RING_LOCALS; 671 RING_LOCALS;
680 672
681 if ( dev_priv->current_page == 1 ) { 673 if (dev_priv->current_page == 1) {
682 unsigned int tmp = flags; 674 unsigned int tmp = flags;
683 675
684 flags &= ~(I810_FRONT | I810_BACK); 676 flags &= ~(I810_FRONT | I810_BACK);
685 if (tmp & I810_FRONT) flags |= I810_BACK; 677 if (tmp & I810_FRONT)
686 if (tmp & I810_BACK) flags |= I810_FRONT; 678 flags |= I810_BACK;
679 if (tmp & I810_BACK)
680 flags |= I810_FRONT;
687 } 681 }
688 682
689 i810_kernel_lost_context(dev); 683 i810_kernel_lost_context(dev);
690 684
691 if (nbox > I810_NR_SAREA_CLIPRECTS) 685 if (nbox > I810_NR_SAREA_CLIPRECTS)
692 nbox = I810_NR_SAREA_CLIPRECTS; 686 nbox = I810_NR_SAREA_CLIPRECTS;
693 687
694 for (i = 0 ; i < nbox ; i++, pbox++) { 688 for (i = 0; i < nbox; i++, pbox++) {
695 unsigned int x = pbox->x1; 689 unsigned int x = pbox->x1;
696 unsigned int y = pbox->y1; 690 unsigned int y = pbox->y1;
697 unsigned int width = (pbox->x2 - x) * cpp; 691 unsigned int width = (pbox->x2 - x) * cpp;
@@ -700,52 +694,48 @@ static void i810_dma_dispatch_clear( drm_device_t *dev, int flags,
700 694
701 if (pbox->x1 > pbox->x2 || 695 if (pbox->x1 > pbox->x2 ||
702 pbox->y1 > pbox->y2 || 696 pbox->y1 > pbox->y2 ||
703 pbox->x2 > dev_priv->w || 697 pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
704 pbox->y2 > dev_priv->h)
705 continue; 698 continue;
706 699
707 if ( flags & I810_FRONT ) { 700 if (flags & I810_FRONT) {
708 BEGIN_LP_RING( 6 ); 701 BEGIN_LP_RING(6);
709 OUT_RING( BR00_BITBLT_CLIENT | 702 OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
710 BR00_OP_COLOR_BLT | 0x3 ); 703 OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
711 OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch ); 704 OUT_RING((height << 16) | width);
712 OUT_RING( (height << 16) | width ); 705 OUT_RING(start);
713 OUT_RING( start ); 706 OUT_RING(clear_color);
714 OUT_RING( clear_color ); 707 OUT_RING(0);
715 OUT_RING( 0 );
716 ADVANCE_LP_RING(); 708 ADVANCE_LP_RING();
717 } 709 }
718 710
719 if ( flags & I810_BACK ) { 711 if (flags & I810_BACK) {
720 BEGIN_LP_RING( 6 ); 712 BEGIN_LP_RING(6);
721 OUT_RING( BR00_BITBLT_CLIENT | 713 OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
722 BR00_OP_COLOR_BLT | 0x3 ); 714 OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
723 OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch ); 715 OUT_RING((height << 16) | width);
724 OUT_RING( (height << 16) | width ); 716 OUT_RING(dev_priv->back_offset + start);
725 OUT_RING( dev_priv->back_offset + start ); 717 OUT_RING(clear_color);
726 OUT_RING( clear_color ); 718 OUT_RING(0);
727 OUT_RING( 0 );
728 ADVANCE_LP_RING(); 719 ADVANCE_LP_RING();
729 } 720 }
730 721
731 if ( flags & I810_DEPTH ) { 722 if (flags & I810_DEPTH) {
732 BEGIN_LP_RING( 6 ); 723 BEGIN_LP_RING(6);
733 OUT_RING( BR00_BITBLT_CLIENT | 724 OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
734 BR00_OP_COLOR_BLT | 0x3 ); 725 OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
735 OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch ); 726 OUT_RING((height << 16) | width);
736 OUT_RING( (height << 16) | width ); 727 OUT_RING(dev_priv->depth_offset + start);
737 OUT_RING( dev_priv->depth_offset + start ); 728 OUT_RING(clear_zval);
738 OUT_RING( clear_zval ); 729 OUT_RING(0);
739 OUT_RING( 0 );
740 ADVANCE_LP_RING(); 730 ADVANCE_LP_RING();
741 } 731 }
742 } 732 }
743} 733}
744 734
745static void i810_dma_dispatch_swap( drm_device_t *dev ) 735static void i810_dma_dispatch_swap(drm_device_t * dev)
746{ 736{
747 drm_i810_private_t *dev_priv = dev->dev_private; 737 drm_i810_private_t *dev_priv = dev->dev_private;
748 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; 738 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
749 int nbox = sarea_priv->nbox; 739 int nbox = sarea_priv->nbox;
750 drm_clip_rect_t *pbox = sarea_priv->boxes; 740 drm_clip_rect_t *pbox = sarea_priv->boxes;
751 int pitch = dev_priv->pitch; 741 int pitch = dev_priv->pitch;
@@ -755,75 +745,71 @@ static void i810_dma_dispatch_swap( drm_device_t *dev )
755 745
756 DRM_DEBUG("swapbuffers\n"); 746 DRM_DEBUG("swapbuffers\n");
757 747
758 i810_kernel_lost_context(dev); 748 i810_kernel_lost_context(dev);
759 749
760 if (nbox > I810_NR_SAREA_CLIPRECTS) 750 if (nbox > I810_NR_SAREA_CLIPRECTS)
761 nbox = I810_NR_SAREA_CLIPRECTS; 751 nbox = I810_NR_SAREA_CLIPRECTS;
762 752
763 for (i = 0 ; i < nbox; i++, pbox++) 753 for (i = 0; i < nbox; i++, pbox++) {
764 {
765 unsigned int w = pbox->x2 - pbox->x1; 754 unsigned int w = pbox->x2 - pbox->x1;
766 unsigned int h = pbox->y2 - pbox->y1; 755 unsigned int h = pbox->y2 - pbox->y1;
767 unsigned int dst = pbox->x1*cpp + pbox->y1*pitch; 756 unsigned int dst = pbox->x1 * cpp + pbox->y1 * pitch;
768 unsigned int start = dst; 757 unsigned int start = dst;
769 758
770 if (pbox->x1 > pbox->x2 || 759 if (pbox->x1 > pbox->x2 ||
771 pbox->y1 > pbox->y2 || 760 pbox->y1 > pbox->y2 ||
772 pbox->x2 > dev_priv->w || 761 pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
773 pbox->y2 > dev_priv->h)
774 continue; 762 continue;
775 763
776 BEGIN_LP_RING( 6 ); 764 BEGIN_LP_RING(6);
777 OUT_RING( BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4 ); 765 OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4);
778 OUT_RING( pitch | (0xCC << 16)); 766 OUT_RING(pitch | (0xCC << 16));
779 OUT_RING( (h << 16) | (w * cpp)); 767 OUT_RING((h << 16) | (w * cpp));
780 if (dev_priv->current_page == 0) 768 if (dev_priv->current_page == 0)
781 OUT_RING(dev_priv->front_offset + start); 769 OUT_RING(dev_priv->front_offset + start);
782 else 770 else
783 OUT_RING(dev_priv->back_offset + start); 771 OUT_RING(dev_priv->back_offset + start);
784 OUT_RING( pitch ); 772 OUT_RING(pitch);
785 if (dev_priv->current_page == 0) 773 if (dev_priv->current_page == 0)
786 OUT_RING(dev_priv->back_offset + start); 774 OUT_RING(dev_priv->back_offset + start);
787 else 775 else
788 OUT_RING(dev_priv->front_offset + start); 776 OUT_RING(dev_priv->front_offset + start);
789 ADVANCE_LP_RING(); 777 ADVANCE_LP_RING();
790 } 778 }
791} 779}
792 780
793 781static void i810_dma_dispatch_vertex(drm_device_t * dev,
794static void i810_dma_dispatch_vertex(drm_device_t *dev, 782 drm_buf_t * buf, int discard, int used)
795 drm_buf_t *buf,
796 int discard,
797 int used)
798{ 783{
799 drm_i810_private_t *dev_priv = dev->dev_private; 784 drm_i810_private_t *dev_priv = dev->dev_private;
800 drm_i810_buf_priv_t *buf_priv = buf->dev_private; 785 drm_i810_buf_priv_t *buf_priv = buf->dev_private;
801 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; 786 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
802 drm_clip_rect_t *box = sarea_priv->boxes; 787 drm_clip_rect_t *box = sarea_priv->boxes;
803 int nbox = sarea_priv->nbox; 788 int nbox = sarea_priv->nbox;
804 unsigned long address = (unsigned long)buf->bus_address; 789 unsigned long address = (unsigned long)buf->bus_address;
805 unsigned long start = address - dev->agp->base; 790 unsigned long start = address - dev->agp->base;
806 int i = 0; 791 int i = 0;
807 RING_LOCALS; 792 RING_LOCALS;
808 793
809 i810_kernel_lost_context(dev); 794 i810_kernel_lost_context(dev);
810 795
811 if (nbox > I810_NR_SAREA_CLIPRECTS) 796 if (nbox > I810_NR_SAREA_CLIPRECTS)
812 nbox = I810_NR_SAREA_CLIPRECTS; 797 nbox = I810_NR_SAREA_CLIPRECTS;
813 798
814 if (used > 4*1024) 799 if (used > 4 * 1024)
815 used = 0; 800 used = 0;
816 801
817 if (sarea_priv->dirty) 802 if (sarea_priv->dirty)
818 i810EmitState( dev ); 803 i810EmitState(dev);
819 804
820 if (buf_priv->currently_mapped == I810_BUF_MAPPED) { 805 if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
821 unsigned int prim = (sarea_priv->vertex_prim & PR_MASK); 806 unsigned int prim = (sarea_priv->vertex_prim & PR_MASK);
822 807
823 *(u32 *)buf_priv->kernel_virtual = ((GFX_OP_PRIMITIVE | prim | ((used/4)-2))); 808 *(u32 *) buf_priv->kernel_virtual =
809 ((GFX_OP_PRIMITIVE | prim | ((used / 4) - 2)));
824 810
825 if (used & 4) { 811 if (used & 4) {
826 *(u32 *)((u32)buf_priv->kernel_virtual + used) = 0; 812 *(u32 *) ((u32) buf_priv->kernel_virtual + used) = 0;
827 used += 4; 813 used += 4;
828 } 814 }
829 815
@@ -834,19 +820,20 @@ static void i810_dma_dispatch_vertex(drm_device_t *dev,
834 do { 820 do {
835 if (i < nbox) { 821 if (i < nbox) {
836 BEGIN_LP_RING(4); 822 BEGIN_LP_RING(4);
837 OUT_RING( GFX_OP_SCISSOR | SC_UPDATE_SCISSOR | 823 OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |
838 SC_ENABLE ); 824 SC_ENABLE);
839 OUT_RING( GFX_OP_SCISSOR_INFO ); 825 OUT_RING(GFX_OP_SCISSOR_INFO);
840 OUT_RING( box[i].x1 | (box[i].y1<<16) ); 826 OUT_RING(box[i].x1 | (box[i].y1 << 16));
841 OUT_RING( (box[i].x2-1) | ((box[i].y2-1)<<16) ); 827 OUT_RING((box[i].x2 -
828 1) | ((box[i].y2 - 1) << 16));
842 ADVANCE_LP_RING(); 829 ADVANCE_LP_RING();
843 } 830 }
844 831
845 BEGIN_LP_RING(4); 832 BEGIN_LP_RING(4);
846 OUT_RING( CMD_OP_BATCH_BUFFER ); 833 OUT_RING(CMD_OP_BATCH_BUFFER);
847 OUT_RING( start | BB1_PROTECTED ); 834 OUT_RING(start | BB1_PROTECTED);
848 OUT_RING( start + used - 4 ); 835 OUT_RING(start + used - 4);
849 OUT_RING( 0 ); 836 OUT_RING(0);
850 ADVANCE_LP_RING(); 837 ADVANCE_LP_RING();
851 838
852 } while (++i < nbox); 839 } while (++i < nbox);
@@ -855,59 +842,59 @@ static void i810_dma_dispatch_vertex(drm_device_t *dev,
855 if (discard) { 842 if (discard) {
856 dev_priv->counter++; 843 dev_priv->counter++;
857 844
858 (void) cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, 845 (void)cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
859 I810_BUF_HARDWARE); 846 I810_BUF_HARDWARE);
860 847
861 BEGIN_LP_RING(8); 848 BEGIN_LP_RING(8);
862 OUT_RING( CMD_STORE_DWORD_IDX ); 849 OUT_RING(CMD_STORE_DWORD_IDX);
863 OUT_RING( 20 ); 850 OUT_RING(20);
864 OUT_RING( dev_priv->counter ); 851 OUT_RING(dev_priv->counter);
865 OUT_RING( CMD_STORE_DWORD_IDX ); 852 OUT_RING(CMD_STORE_DWORD_IDX);
866 OUT_RING( buf_priv->my_use_idx ); 853 OUT_RING(buf_priv->my_use_idx);
867 OUT_RING( I810_BUF_FREE ); 854 OUT_RING(I810_BUF_FREE);
868 OUT_RING( CMD_REPORT_HEAD ); 855 OUT_RING(CMD_REPORT_HEAD);
869 OUT_RING( 0 ); 856 OUT_RING(0);
870 ADVANCE_LP_RING(); 857 ADVANCE_LP_RING();
871 } 858 }
872} 859}
873 860
874static void i810_dma_dispatch_flip( drm_device_t *dev ) 861static void i810_dma_dispatch_flip(drm_device_t * dev)
875{ 862{
876 drm_i810_private_t *dev_priv = dev->dev_private; 863 drm_i810_private_t *dev_priv = dev->dev_private;
877 int pitch = dev_priv->pitch; 864 int pitch = dev_priv->pitch;
878 RING_LOCALS; 865 RING_LOCALS;
879 866
880 DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n", 867 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
881 __FUNCTION__, 868 __FUNCTION__,
882 dev_priv->current_page, 869 dev_priv->current_page,
883 dev_priv->sarea_priv->pf_current_page); 870 dev_priv->sarea_priv->pf_current_page);
884 871
885 i810_kernel_lost_context(dev); 872 i810_kernel_lost_context(dev);
886 873
887 BEGIN_LP_RING( 2 ); 874 BEGIN_LP_RING(2);
888 OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE ); 875 OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
889 OUT_RING( 0 ); 876 OUT_RING(0);
890 ADVANCE_LP_RING(); 877 ADVANCE_LP_RING();
891 878
892 BEGIN_LP_RING( I810_DEST_SETUP_SIZE + 2 ); 879 BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
893 /* On i815 at least ASYNC is buggy */ 880 /* On i815 at least ASYNC is buggy */
894 /* pitch<<5 is from 11.2.8 p158, 881 /* pitch<<5 is from 11.2.8 p158,
895 its the pitch / 8 then left shifted 8, 882 its the pitch / 8 then left shifted 8,
896 so (pitch >> 3) << 8 */ 883 so (pitch >> 3) << 8 */
897 OUT_RING( CMD_OP_FRONTBUFFER_INFO | (pitch<<5) /*| ASYNC_FLIP */ ); 884 OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ );
898 if ( dev_priv->current_page == 0 ) { 885 if (dev_priv->current_page == 0) {
899 OUT_RING( dev_priv->back_offset ); 886 OUT_RING(dev_priv->back_offset);
900 dev_priv->current_page = 1; 887 dev_priv->current_page = 1;
901 } else { 888 } else {
902 OUT_RING( dev_priv->front_offset ); 889 OUT_RING(dev_priv->front_offset);
903 dev_priv->current_page = 0; 890 dev_priv->current_page = 0;
904 } 891 }
905 OUT_RING(0); 892 OUT_RING(0);
906 ADVANCE_LP_RING(); 893 ADVANCE_LP_RING();
907 894
908 BEGIN_LP_RING(2); 895 BEGIN_LP_RING(2);
909 OUT_RING( CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP ); 896 OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP);
910 OUT_RING( 0 ); 897 OUT_RING(0);
911 ADVANCE_LP_RING(); 898 ADVANCE_LP_RING();
912 899
913 /* Increment the frame counter. The client-side 3D driver must 900 /* Increment the frame counter. The client-side 3D driver must
@@ -918,46 +905,46 @@ static void i810_dma_dispatch_flip( drm_device_t *dev )
918 905
919} 906}
920 907
921static void i810_dma_quiescent(drm_device_t *dev) 908static void i810_dma_quiescent(drm_device_t * dev)
922{ 909{
923 drm_i810_private_t *dev_priv = dev->dev_private; 910 drm_i810_private_t *dev_priv = dev->dev_private;
924 RING_LOCALS; 911 RING_LOCALS;
925 912
926/* printk("%s\n", __FUNCTION__); */ 913/* printk("%s\n", __FUNCTION__); */
927 914
928 i810_kernel_lost_context(dev); 915 i810_kernel_lost_context(dev);
929 916
930 BEGIN_LP_RING(4); 917 BEGIN_LP_RING(4);
931 OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE ); 918 OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
932 OUT_RING( CMD_REPORT_HEAD ); 919 OUT_RING(CMD_REPORT_HEAD);
933 OUT_RING( 0 ); 920 OUT_RING(0);
934 OUT_RING( 0 ); 921 OUT_RING(0);
935 ADVANCE_LP_RING(); 922 ADVANCE_LP_RING();
936 923
937 i810_wait_ring( dev, dev_priv->ring.Size - 8 ); 924 i810_wait_ring(dev, dev_priv->ring.Size - 8);
938} 925}
939 926
940static int i810_flush_queue(drm_device_t *dev) 927static int i810_flush_queue(drm_device_t * dev)
941{ 928{
942 drm_i810_private_t *dev_priv = dev->dev_private; 929 drm_i810_private_t *dev_priv = dev->dev_private;
943 drm_device_dma_t *dma = dev->dma; 930 drm_device_dma_t *dma = dev->dma;
944 int i, ret = 0; 931 int i, ret = 0;
945 RING_LOCALS; 932 RING_LOCALS;
946 933
947/* printk("%s\n", __FUNCTION__); */ 934/* printk("%s\n", __FUNCTION__); */
948 935
949 i810_kernel_lost_context(dev); 936 i810_kernel_lost_context(dev);
950 937
951 BEGIN_LP_RING(2); 938 BEGIN_LP_RING(2);
952 OUT_RING( CMD_REPORT_HEAD ); 939 OUT_RING(CMD_REPORT_HEAD);
953 OUT_RING( 0 ); 940 OUT_RING(0);
954 ADVANCE_LP_RING(); 941 ADVANCE_LP_RING();
955 942
956 i810_wait_ring( dev, dev_priv->ring.Size - 8 ); 943 i810_wait_ring(dev, dev_priv->ring.Size - 8);
957 944
958 for (i = 0; i < dma->buf_count; i++) { 945 for (i = 0; i < dma->buf_count; i++) {
959 drm_buf_t *buf = dma->buflist[ i ]; 946 drm_buf_t *buf = dma->buflist[i];
960 drm_i810_buf_priv_t *buf_priv = buf->dev_private; 947 drm_i810_buf_priv_t *buf_priv = buf->dev_private;
961 948
962 int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE, 949 int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE,
963 I810_BUF_FREE); 950 I810_BUF_FREE);
@@ -968,24 +955,27 @@ static int i810_flush_queue(drm_device_t *dev)
968 DRM_DEBUG("still on client\n"); 955 DRM_DEBUG("still on client\n");
969 } 956 }
970 957
971 return ret; 958 return ret;
972} 959}
973 960
974/* Must be called with the lock held */ 961/* Must be called with the lock held */
975void i810_reclaim_buffers(drm_device_t *dev, struct file *filp) 962void i810_reclaim_buffers(drm_device_t * dev, struct file *filp)
976{ 963{
977 drm_device_dma_t *dma = dev->dma; 964 drm_device_dma_t *dma = dev->dma;
978 int i; 965 int i;
979 966
980 if (!dma) return; 967 if (!dma)
981 if (!dev->dev_private) return; 968 return;
982 if (!dma->buflist) return; 969 if (!dev->dev_private)
970 return;
971 if (!dma->buflist)
972 return;
983 973
984 i810_flush_queue(dev); 974 i810_flush_queue(dev);
985 975
986 for (i = 0; i < dma->buf_count; i++) { 976 for (i = 0; i < dma->buf_count; i++) {
987 drm_buf_t *buf = dma->buflist[ i ]; 977 drm_buf_t *buf = dma->buflist[i];
988 drm_i810_buf_priv_t *buf_priv = buf->dev_private; 978 drm_i810_buf_priv_t *buf_priv = buf->dev_private;
989 979
990 if (buf->filp == filp && buf_priv) { 980 if (buf->filp == filp && buf_priv) {
991 int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, 981 int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
@@ -994,7 +984,7 @@ void i810_reclaim_buffers(drm_device_t *dev, struct file *filp)
994 if (used == I810_BUF_CLIENT) 984 if (used == I810_BUF_CLIENT)
995 DRM_DEBUG("reclaimed from client\n"); 985 DRM_DEBUG("reclaimed from client\n");
996 if (buf_priv->currently_mapped == I810_BUF_MAPPED) 986 if (buf_priv->currently_mapped == I810_BUF_MAPPED)
997 buf_priv->currently_mapped = I810_BUF_UNMAPPED; 987 buf_priv->currently_mapped = I810_BUF_UNMAPPED;
998 } 988 }
999 } 989 }
1000} 990}
@@ -1002,29 +992,29 @@ void i810_reclaim_buffers(drm_device_t *dev, struct file *filp)
1002static int i810_flush_ioctl(struct inode *inode, struct file *filp, 992static int i810_flush_ioctl(struct inode *inode, struct file *filp,
1003 unsigned int cmd, unsigned long arg) 993 unsigned int cmd, unsigned long arg)
1004{ 994{
1005 drm_file_t *priv = filp->private_data; 995 drm_file_t *priv = filp->private_data;
1006 drm_device_t *dev = priv->head->dev; 996 drm_device_t *dev = priv->head->dev;
1007 997
1008 LOCK_TEST_WITH_RETURN(dev, filp); 998 LOCK_TEST_WITH_RETURN(dev, filp);
1009 999
1010 i810_flush_queue(dev); 1000 i810_flush_queue(dev);
1011 return 0; 1001 return 0;
1012} 1002}
1013 1003
1014
1015static int i810_dma_vertex(struct inode *inode, struct file *filp, 1004static int i810_dma_vertex(struct inode *inode, struct file *filp,
1016 unsigned int cmd, unsigned long arg) 1005 unsigned int cmd, unsigned long arg)
1017{ 1006{
1018 drm_file_t *priv = filp->private_data; 1007 drm_file_t *priv = filp->private_data;
1019 drm_device_t *dev = priv->head->dev; 1008 drm_device_t *dev = priv->head->dev;
1020 drm_device_dma_t *dma = dev->dma; 1009 drm_device_dma_t *dma = dev->dma;
1021 drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; 1010 drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
1022 u32 *hw_status = dev_priv->hw_status_page; 1011 u32 *hw_status = dev_priv->hw_status_page;
1023 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) 1012 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
1024 dev_priv->sarea_priv; 1013 dev_priv->sarea_priv;
1025 drm_i810_vertex_t vertex; 1014 drm_i810_vertex_t vertex;
1026 1015
1027 if (copy_from_user(&vertex, (drm_i810_vertex_t __user *)arg, sizeof(vertex))) 1016 if (copy_from_user
1017 (&vertex, (drm_i810_vertex_t __user *) arg, sizeof(vertex)))
1028 return -EFAULT; 1018 return -EFAULT;
1029 1019
1030 LOCK_TEST_WITH_RETURN(dev, filp); 1020 LOCK_TEST_WITH_RETURN(dev, filp);
@@ -1032,48 +1022,46 @@ static int i810_dma_vertex(struct inode *inode, struct file *filp,
1032 DRM_DEBUG("i810 dma vertex, idx %d used %d discard %d\n", 1022 DRM_DEBUG("i810 dma vertex, idx %d used %d discard %d\n",
1033 vertex.idx, vertex.used, vertex.discard); 1023 vertex.idx, vertex.used, vertex.discard);
1034 1024
1035 if (vertex.idx < 0 || vertex.idx > dma->buf_count) 1025 if (vertex.idx < 0 || vertex.idx > dma->buf_count)
1036 return -EINVAL; 1026 return -EINVAL;
1037 1027
1038 i810_dma_dispatch_vertex( dev, 1028 i810_dma_dispatch_vertex(dev,
1039 dma->buflist[ vertex.idx ], 1029 dma->buflist[vertex.idx],
1040 vertex.discard, vertex.used ); 1030 vertex.discard, vertex.used);
1041 1031
1042 atomic_add(vertex.used, &dev->counts[_DRM_STAT_SECONDARY]); 1032 atomic_add(vertex.used, &dev->counts[_DRM_STAT_SECONDARY]);
1043 atomic_inc(&dev->counts[_DRM_STAT_DMA]); 1033 atomic_inc(&dev->counts[_DRM_STAT_DMA]);
1044 sarea_priv->last_enqueue = dev_priv->counter-1; 1034 sarea_priv->last_enqueue = dev_priv->counter - 1;
1045 sarea_priv->last_dispatch = (int) hw_status[5]; 1035 sarea_priv->last_dispatch = (int)hw_status[5];
1046 1036
1047 return 0; 1037 return 0;
1048} 1038}
1049 1039
1050
1051
1052static int i810_clear_bufs(struct inode *inode, struct file *filp, 1040static int i810_clear_bufs(struct inode *inode, struct file *filp,
1053 unsigned int cmd, unsigned long arg) 1041 unsigned int cmd, unsigned long arg)
1054{ 1042{
1055 drm_file_t *priv = filp->private_data; 1043 drm_file_t *priv = filp->private_data;
1056 drm_device_t *dev = priv->head->dev; 1044 drm_device_t *dev = priv->head->dev;
1057 drm_i810_clear_t clear; 1045 drm_i810_clear_t clear;
1058 1046
1059 if (copy_from_user(&clear, (drm_i810_clear_t __user *)arg, sizeof(clear))) 1047 if (copy_from_user
1048 (&clear, (drm_i810_clear_t __user *) arg, sizeof(clear)))
1060 return -EFAULT; 1049 return -EFAULT;
1061 1050
1062 LOCK_TEST_WITH_RETURN(dev, filp); 1051 LOCK_TEST_WITH_RETURN(dev, filp);
1063 1052
1064 /* GH: Someone's doing nasty things... */ 1053 /* GH: Someone's doing nasty things... */
1065 if (!dev->dev_private) { 1054 if (!dev->dev_private) {
1066 return -EINVAL; 1055 return -EINVAL;
1067 } 1056 }
1068 1057
1069 i810_dma_dispatch_clear( dev, clear.flags, 1058 i810_dma_dispatch_clear(dev, clear.flags,
1070 clear.clear_color, 1059 clear.clear_color, clear.clear_depth);
1071 clear.clear_depth ); 1060 return 0;
1072 return 0;
1073} 1061}
1074 1062
1075static int i810_swap_bufs(struct inode *inode, struct file *filp, 1063static int i810_swap_bufs(struct inode *inode, struct file *filp,
1076 unsigned int cmd, unsigned long arg) 1064 unsigned int cmd, unsigned long arg)
1077{ 1065{
1078 drm_file_t *priv = filp->private_data; 1066 drm_file_t *priv = filp->private_data;
1079 drm_device_t *dev = priv->head->dev; 1067 drm_device_t *dev = priv->head->dev;
@@ -1082,37 +1070,37 @@ static int i810_swap_bufs(struct inode *inode, struct file *filp,
1082 1070
1083 LOCK_TEST_WITH_RETURN(dev, filp); 1071 LOCK_TEST_WITH_RETURN(dev, filp);
1084 1072
1085 i810_dma_dispatch_swap( dev ); 1073 i810_dma_dispatch_swap(dev);
1086 return 0; 1074 return 0;
1087} 1075}
1088 1076
1089static int i810_getage(struct inode *inode, struct file *filp, unsigned int cmd, 1077static int i810_getage(struct inode *inode, struct file *filp, unsigned int cmd,
1090 unsigned long arg) 1078 unsigned long arg)
1091{ 1079{
1092 drm_file_t *priv = filp->private_data; 1080 drm_file_t *priv = filp->private_data;
1093 drm_device_t *dev = priv->head->dev; 1081 drm_device_t *dev = priv->head->dev;
1094 drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; 1082 drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
1095 u32 *hw_status = dev_priv->hw_status_page; 1083 u32 *hw_status = dev_priv->hw_status_page;
1096 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) 1084 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
1097 dev_priv->sarea_priv; 1085 dev_priv->sarea_priv;
1098 1086
1099 sarea_priv->last_dispatch = (int) hw_status[5]; 1087 sarea_priv->last_dispatch = (int)hw_status[5];
1100 return 0; 1088 return 0;
1101} 1089}
1102 1090
1103static int i810_getbuf(struct inode *inode, struct file *filp, unsigned int cmd, 1091static int i810_getbuf(struct inode *inode, struct file *filp, unsigned int cmd,
1104 unsigned long arg) 1092 unsigned long arg)
1105{ 1093{
1106 drm_file_t *priv = filp->private_data; 1094 drm_file_t *priv = filp->private_data;
1107 drm_device_t *dev = priv->head->dev; 1095 drm_device_t *dev = priv->head->dev;
1108 int retcode = 0; 1096 int retcode = 0;
1109 drm_i810_dma_t d; 1097 drm_i810_dma_t d;
1110 drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; 1098 drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
1111 u32 *hw_status = dev_priv->hw_status_page; 1099 u32 *hw_status = dev_priv->hw_status_page;
1112 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) 1100 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
1113 dev_priv->sarea_priv; 1101 dev_priv->sarea_priv;
1114 1102
1115 if (copy_from_user(&d, (drm_i810_dma_t __user *)arg, sizeof(d))) 1103 if (copy_from_user(&d, (drm_i810_dma_t __user *) arg, sizeof(d)))
1116 return -EFAULT; 1104 return -EFAULT;
1117 1105
1118 LOCK_TEST_WITH_RETURN(dev, filp); 1106 LOCK_TEST_WITH_RETURN(dev, filp);
@@ -1124,29 +1112,29 @@ static int i810_getbuf(struct inode *inode, struct file *filp, unsigned int cmd,
1124 DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n", 1112 DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n",
1125 current->pid, retcode, d.granted); 1113 current->pid, retcode, d.granted);
1126 1114
1127 if (copy_to_user((drm_dma_t __user *)arg, &d, sizeof(d))) 1115 if (copy_to_user((drm_dma_t __user *) arg, &d, sizeof(d)))
1128 return -EFAULT; 1116 return -EFAULT;
1129 sarea_priv->last_dispatch = (int) hw_status[5]; 1117 sarea_priv->last_dispatch = (int)hw_status[5];
1130 1118
1131 return retcode; 1119 return retcode;
1132} 1120}
1133 1121
1134static int i810_copybuf(struct inode *inode, 1122static int i810_copybuf(struct inode *inode,
1135 struct file *filp, unsigned int cmd, unsigned long arg) 1123 struct file *filp, unsigned int cmd, unsigned long arg)
1136{ 1124{
1137 /* Never copy - 2.4.x doesn't need it */ 1125 /* Never copy - 2.4.x doesn't need it */
1138 return 0; 1126 return 0;
1139} 1127}
1140 1128
1141static int i810_docopy(struct inode *inode, struct file *filp, unsigned int cmd, 1129static int i810_docopy(struct inode *inode, struct file *filp, unsigned int cmd,
1142 unsigned long arg) 1130 unsigned long arg)
1143{ 1131{
1144 /* Never copy - 2.4.x doesn't need it */ 1132 /* Never copy - 2.4.x doesn't need it */
1145 return 0; 1133 return 0;
1146} 1134}
1147 1135
1148static void i810_dma_dispatch_mc(drm_device_t *dev, drm_buf_t *buf, int used, 1136static void i810_dma_dispatch_mc(drm_device_t * dev, drm_buf_t * buf, int used,
1149 unsigned int last_render) 1137 unsigned int last_render)
1150{ 1138{
1151 drm_i810_private_t *dev_priv = dev->dev_private; 1139 drm_i810_private_t *dev_priv = dev->dev_private;
1152 drm_i810_buf_priv_t *buf_priv = buf->dev_private; 1140 drm_i810_buf_priv_t *buf_priv = buf->dev_private;
@@ -1158,19 +1146,17 @@ static void i810_dma_dispatch_mc(drm_device_t *dev, drm_buf_t *buf, int used,
1158 1146
1159 i810_kernel_lost_context(dev); 1147 i810_kernel_lost_context(dev);
1160 1148
1161 u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, 1149 u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_HARDWARE);
1162 I810_BUF_HARDWARE);
1163 if (u != I810_BUF_CLIENT) { 1150 if (u != I810_BUF_CLIENT) {
1164 DRM_DEBUG("MC found buffer that isn't mine!\n"); 1151 DRM_DEBUG("MC found buffer that isn't mine!\n");
1165 } 1152 }
1166 1153
1167 if (used > 4*1024) 1154 if (used > 4 * 1024)
1168 used = 0; 1155 used = 0;
1169 1156
1170 sarea_priv->dirty = 0x7f; 1157 sarea_priv->dirty = 0x7f;
1171 1158
1172 DRM_DEBUG("dispatch mc addr 0x%lx, used 0x%x\n", 1159 DRM_DEBUG("dispatch mc addr 0x%lx, used 0x%x\n", address, used);
1173 address, used);
1174 1160
1175 dev_priv->counter++; 1161 dev_priv->counter++;
1176 DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter); 1162 DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
@@ -1181,46 +1167,45 @@ static void i810_dma_dispatch_mc(drm_device_t *dev, drm_buf_t *buf, int used,
1181 1167
1182 if (buf_priv->currently_mapped == I810_BUF_MAPPED) { 1168 if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
1183 if (used & 4) { 1169 if (used & 4) {
1184 *(u32 *)((u32)buf_priv->virtual + used) = 0; 1170 *(u32 *) ((u32) buf_priv->virtual + used) = 0;
1185 used += 4; 1171 used += 4;
1186 } 1172 }
1187 1173
1188 i810_unmap_buffer(buf); 1174 i810_unmap_buffer(buf);
1189 } 1175 }
1190 BEGIN_LP_RING(4); 1176 BEGIN_LP_RING(4);
1191 OUT_RING( CMD_OP_BATCH_BUFFER ); 1177 OUT_RING(CMD_OP_BATCH_BUFFER);
1192 OUT_RING( start | BB1_PROTECTED ); 1178 OUT_RING(start | BB1_PROTECTED);
1193 OUT_RING( start + used - 4 ); 1179 OUT_RING(start + used - 4);
1194 OUT_RING( 0 ); 1180 OUT_RING(0);
1195 ADVANCE_LP_RING(); 1181 ADVANCE_LP_RING();
1196 1182
1197
1198 BEGIN_LP_RING(8); 1183 BEGIN_LP_RING(8);
1199 OUT_RING( CMD_STORE_DWORD_IDX ); 1184 OUT_RING(CMD_STORE_DWORD_IDX);
1200 OUT_RING( buf_priv->my_use_idx ); 1185 OUT_RING(buf_priv->my_use_idx);
1201 OUT_RING( I810_BUF_FREE ); 1186 OUT_RING(I810_BUF_FREE);
1202 OUT_RING( 0 ); 1187 OUT_RING(0);
1203 1188
1204 OUT_RING( CMD_STORE_DWORD_IDX ); 1189 OUT_RING(CMD_STORE_DWORD_IDX);
1205 OUT_RING( 16 ); 1190 OUT_RING(16);
1206 OUT_RING( last_render ); 1191 OUT_RING(last_render);
1207 OUT_RING( 0 ); 1192 OUT_RING(0);
1208 ADVANCE_LP_RING(); 1193 ADVANCE_LP_RING();
1209} 1194}
1210 1195
1211static int i810_dma_mc(struct inode *inode, struct file *filp, 1196static int i810_dma_mc(struct inode *inode, struct file *filp,
1212 unsigned int cmd, unsigned long arg) 1197 unsigned int cmd, unsigned long arg)
1213{ 1198{
1214 drm_file_t *priv = filp->private_data; 1199 drm_file_t *priv = filp->private_data;
1215 drm_device_t *dev = priv->head->dev; 1200 drm_device_t *dev = priv->head->dev;
1216 drm_device_dma_t *dma = dev->dma; 1201 drm_device_dma_t *dma = dev->dma;
1217 drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; 1202 drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
1218 u32 *hw_status = dev_priv->hw_status_page; 1203 u32 *hw_status = dev_priv->hw_status_page;
1219 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) 1204 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
1220 dev_priv->sarea_priv; 1205 dev_priv->sarea_priv;
1221 drm_i810_mc_t mc; 1206 drm_i810_mc_t mc;
1222 1207
1223 if (copy_from_user(&mc, (drm_i810_mc_t __user *)arg, sizeof(mc))) 1208 if (copy_from_user(&mc, (drm_i810_mc_t __user *) arg, sizeof(mc)))
1224 return -EFAULT; 1209 return -EFAULT;
1225 1210
1226 LOCK_TEST_WITH_RETURN(dev, filp); 1211 LOCK_TEST_WITH_RETURN(dev, filp);
@@ -1229,12 +1214,12 @@ static int i810_dma_mc(struct inode *inode, struct file *filp,
1229 return -EINVAL; 1214 return -EINVAL;
1230 1215
1231 i810_dma_dispatch_mc(dev, dma->buflist[mc.idx], mc.used, 1216 i810_dma_dispatch_mc(dev, dma->buflist[mc.idx], mc.used,
1232 mc.last_render ); 1217 mc.last_render);
1233 1218
1234 atomic_add(mc.used, &dev->counts[_DRM_STAT_SECONDARY]); 1219 atomic_add(mc.used, &dev->counts[_DRM_STAT_SECONDARY]);
1235 atomic_inc(&dev->counts[_DRM_STAT_DMA]); 1220 atomic_inc(&dev->counts[_DRM_STAT_DMA]);
1236 sarea_priv->last_enqueue = dev_priv->counter-1; 1221 sarea_priv->last_enqueue = dev_priv->counter - 1;
1237 sarea_priv->last_dispatch = (int) hw_status[5]; 1222 sarea_priv->last_dispatch = (int)hw_status[5];
1238 1223
1239 return 0; 1224 return 0;
1240} 1225}
@@ -1244,22 +1229,23 @@ static int i810_rstatus(struct inode *inode, struct file *filp,
1244{ 1229{
1245 drm_file_t *priv = filp->private_data; 1230 drm_file_t *priv = filp->private_data;
1246 drm_device_t *dev = priv->head->dev; 1231 drm_device_t *dev = priv->head->dev;
1247 drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; 1232 drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
1248 1233
1249 return (int)(((u32 *)(dev_priv->hw_status_page))[4]); 1234 return (int)(((u32 *) (dev_priv->hw_status_page))[4]);
1250} 1235}
1251 1236
1252static int i810_ov0_info(struct inode *inode, struct file *filp, 1237static int i810_ov0_info(struct inode *inode, struct file *filp,
1253 unsigned int cmd, unsigned long arg) 1238 unsigned int cmd, unsigned long arg)
1254{ 1239{
1255 drm_file_t *priv = filp->private_data; 1240 drm_file_t *priv = filp->private_data;
1256 drm_device_t *dev = priv->head->dev; 1241 drm_device_t *dev = priv->head->dev;
1257 drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; 1242 drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
1258 drm_i810_overlay_t data; 1243 drm_i810_overlay_t data;
1259 1244
1260 data.offset = dev_priv->overlay_offset; 1245 data.offset = dev_priv->overlay_offset;
1261 data.physical = dev_priv->overlay_physical; 1246 data.physical = dev_priv->overlay_physical;
1262 if (copy_to_user((drm_i810_overlay_t __user *)arg,&data,sizeof(data))) 1247 if (copy_to_user
1248 ((drm_i810_overlay_t __user *) arg, &data, sizeof(data)))
1263 return -EFAULT; 1249 return -EFAULT;
1264 return 0; 1250 return 0;
1265} 1251}
@@ -1269,7 +1255,7 @@ static int i810_fstatus(struct inode *inode, struct file *filp,
1269{ 1255{
1270 drm_file_t *priv = filp->private_data; 1256 drm_file_t *priv = filp->private_data;
1271 drm_device_t *dev = priv->head->dev; 1257 drm_device_t *dev = priv->head->dev;
1272 drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; 1258 drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
1273 1259
1274 LOCK_TEST_WITH_RETURN(dev, filp); 1260 LOCK_TEST_WITH_RETURN(dev, filp);
1275 1261
@@ -1277,47 +1263,46 @@ static int i810_fstatus(struct inode *inode, struct file *filp,
1277} 1263}
1278 1264
1279static int i810_ov0_flip(struct inode *inode, struct file *filp, 1265static int i810_ov0_flip(struct inode *inode, struct file *filp,
1280 unsigned int cmd, unsigned long arg) 1266 unsigned int cmd, unsigned long arg)
1281{ 1267{
1282 drm_file_t *priv = filp->private_data; 1268 drm_file_t *priv = filp->private_data;
1283 drm_device_t *dev = priv->head->dev; 1269 drm_device_t *dev = priv->head->dev;
1284 drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; 1270 drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
1285 1271
1286 LOCK_TEST_WITH_RETURN(dev, filp); 1272 LOCK_TEST_WITH_RETURN(dev, filp);
1287 1273
1288 //Tell the overlay to update 1274 //Tell the overlay to update
1289 I810_WRITE(0x30000,dev_priv->overlay_physical | 0x80000000); 1275 I810_WRITE(0x30000, dev_priv->overlay_physical | 0x80000000);
1290 1276
1291 return 0; 1277 return 0;
1292} 1278}
1293 1279
1294
1295/* Not sure why this isn't set all the time: 1280/* Not sure why this isn't set all the time:
1296 */ 1281 */
1297static void i810_do_init_pageflip( drm_device_t *dev ) 1282static void i810_do_init_pageflip(drm_device_t * dev)
1298{ 1283{
1299 drm_i810_private_t *dev_priv = dev->dev_private; 1284 drm_i810_private_t *dev_priv = dev->dev_private;
1300 1285
1301 DRM_DEBUG("%s\n", __FUNCTION__); 1286 DRM_DEBUG("%s\n", __FUNCTION__);
1302 dev_priv->page_flipping = 1; 1287 dev_priv->page_flipping = 1;
1303 dev_priv->current_page = 0; 1288 dev_priv->current_page = 0;
1304 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; 1289 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
1305} 1290}
1306 1291
1307static int i810_do_cleanup_pageflip( drm_device_t *dev ) 1292static int i810_do_cleanup_pageflip(drm_device_t * dev)
1308{ 1293{
1309 drm_i810_private_t *dev_priv = dev->dev_private; 1294 drm_i810_private_t *dev_priv = dev->dev_private;
1310 1295
1311 DRM_DEBUG("%s\n", __FUNCTION__); 1296 DRM_DEBUG("%s\n", __FUNCTION__);
1312 if (dev_priv->current_page != 0) 1297 if (dev_priv->current_page != 0)
1313 i810_dma_dispatch_flip( dev ); 1298 i810_dma_dispatch_flip(dev);
1314 1299
1315 dev_priv->page_flipping = 0; 1300 dev_priv->page_flipping = 0;
1316 return 0; 1301 return 0;
1317} 1302}
1318 1303
1319static int i810_flip_bufs(struct inode *inode, struct file *filp, 1304static int i810_flip_bufs(struct inode *inode, struct file *filp,
1320 unsigned int cmd, unsigned long arg) 1305 unsigned int cmd, unsigned long arg)
1321{ 1306{
1322 drm_file_t *priv = filp->private_data; 1307 drm_file_t *priv = filp->private_data;
1323 drm_device_t *dev = priv->head->dev; 1308 drm_device_t *dev = priv->head->dev;
@@ -1327,19 +1312,19 @@ static int i810_flip_bufs(struct inode *inode, struct file *filp,
1327 1312
1328 LOCK_TEST_WITH_RETURN(dev, filp); 1313 LOCK_TEST_WITH_RETURN(dev, filp);
1329 1314
1330 if (!dev_priv->page_flipping) 1315 if (!dev_priv->page_flipping)
1331 i810_do_init_pageflip( dev ); 1316 i810_do_init_pageflip(dev);
1332 1317
1333 i810_dma_dispatch_flip( dev ); 1318 i810_dma_dispatch_flip(dev);
1334 return 0; 1319 return 0;
1335} 1320}
1336 1321
1337void i810_driver_pretakedown(drm_device_t *dev) 1322void i810_driver_pretakedown(drm_device_t * dev)
1338{ 1323{
1339 i810_dma_cleanup( dev ); 1324 i810_dma_cleanup(dev);
1340} 1325}
1341 1326
1342void i810_driver_prerelease(drm_device_t *dev, DRMFILE filp) 1327void i810_driver_prerelease(drm_device_t * dev, DRMFILE filp)
1343{ 1328{
1344 if (dev->dev_private) { 1329 if (dev->dev_private) {
1345 drm_i810_private_t *dev_priv = dev->dev_private; 1330 drm_i810_private_t *dev_priv = dev->dev_private;
@@ -1349,33 +1334,47 @@ void i810_driver_prerelease(drm_device_t *dev, DRMFILE filp)
1349 } 1334 }
1350} 1335}
1351 1336
1352void i810_driver_release(drm_device_t *dev, struct file *filp) 1337void i810_driver_release(drm_device_t * dev, struct file *filp)
1353{ 1338{
1354 i810_reclaim_buffers(dev, filp); 1339 i810_reclaim_buffers(dev, filp);
1355} 1340}
1356 1341
1357int i810_driver_dma_quiescent(drm_device_t *dev) 1342int i810_driver_dma_quiescent(drm_device_t * dev)
1358{ 1343{
1359 i810_dma_quiescent( dev ); 1344 i810_dma_quiescent(dev);
1360 return 0; 1345 return 0;
1361} 1346}
1362 1347
1363drm_ioctl_desc_t i810_ioctls[] = { 1348drm_ioctl_desc_t i810_ioctls[] = {
1364 [DRM_IOCTL_NR(DRM_I810_INIT)] = { i810_dma_init, 1, 1 }, 1349 [DRM_IOCTL_NR(DRM_I810_INIT)] = {i810_dma_init, 1, 1}
1365 [DRM_IOCTL_NR(DRM_I810_VERTEX)] = { i810_dma_vertex, 1, 0 }, 1350 ,
1366 [DRM_IOCTL_NR(DRM_I810_CLEAR)] = { i810_clear_bufs, 1, 0 }, 1351 [DRM_IOCTL_NR(DRM_I810_VERTEX)] = {i810_dma_vertex, 1, 0}
1367 [DRM_IOCTL_NR(DRM_I810_FLUSH)] = { i810_flush_ioctl, 1, 0 }, 1352 ,
1368 [DRM_IOCTL_NR(DRM_I810_GETAGE)] = { i810_getage, 1, 0 }, 1353 [DRM_IOCTL_NR(DRM_I810_CLEAR)] = {i810_clear_bufs, 1, 0}
1369 [DRM_IOCTL_NR(DRM_I810_GETBUF)] = { i810_getbuf, 1, 0 }, 1354 ,
1370 [DRM_IOCTL_NR(DRM_I810_SWAP)] = { i810_swap_bufs, 1, 0 }, 1355 [DRM_IOCTL_NR(DRM_I810_FLUSH)] = {i810_flush_ioctl, 1, 0}
1371 [DRM_IOCTL_NR(DRM_I810_COPY)] = { i810_copybuf, 1, 0 }, 1356 ,
1372 [DRM_IOCTL_NR(DRM_I810_DOCOPY)] = { i810_docopy, 1, 0 }, 1357 [DRM_IOCTL_NR(DRM_I810_GETAGE)] = {i810_getage, 1, 0}
1373 [DRM_IOCTL_NR(DRM_I810_OV0INFO)] = { i810_ov0_info, 1, 0 }, 1358 ,
1374 [DRM_IOCTL_NR(DRM_I810_FSTATUS)] = { i810_fstatus, 1, 0 }, 1359 [DRM_IOCTL_NR(DRM_I810_GETBUF)] = {i810_getbuf, 1, 0}
1375 [DRM_IOCTL_NR(DRM_I810_OV0FLIP)] = { i810_ov0_flip, 1, 0 }, 1360 ,
1376 [DRM_IOCTL_NR(DRM_I810_MC)] = { i810_dma_mc, 1, 1 }, 1361 [DRM_IOCTL_NR(DRM_I810_SWAP)] = {i810_swap_bufs, 1, 0}
1377 [DRM_IOCTL_NR(DRM_I810_RSTATUS)] = { i810_rstatus, 1, 0 }, 1362 ,
1378 [DRM_IOCTL_NR(DRM_I810_FLIP)] = { i810_flip_bufs, 1, 0 } 1363 [DRM_IOCTL_NR(DRM_I810_COPY)] = {i810_copybuf, 1, 0}
1364 ,
1365 [DRM_IOCTL_NR(DRM_I810_DOCOPY)] = {i810_docopy, 1, 0}
1366 ,
1367 [DRM_IOCTL_NR(DRM_I810_OV0INFO)] = {i810_ov0_info, 1, 0}
1368 ,
1369 [DRM_IOCTL_NR(DRM_I810_FSTATUS)] = {i810_fstatus, 1, 0}
1370 ,
1371 [DRM_IOCTL_NR(DRM_I810_OV0FLIP)] = {i810_ov0_flip, 1, 0}
1372 ,
1373 [DRM_IOCTL_NR(DRM_I810_MC)] = {i810_dma_mc, 1, 1}
1374 ,
1375 [DRM_IOCTL_NR(DRM_I810_RSTATUS)] = {i810_rstatus, 1, 0}
1376 ,
1377 [DRM_IOCTL_NR(DRM_I810_FLIP)] = {i810_flip_bufs, 1, 0}
1379}; 1378};
1380 1379
1381int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls); 1380int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls);
diff --git a/drivers/char/drm/i810_drm.h b/drivers/char/drm/i810_drm.h
index 73ac40563b1d..2deb925a94f3 100644
--- a/drivers/char/drm/i810_drm.h
+++ b/drivers/char/drm/i810_drm.h
@@ -19,21 +19,20 @@
19#define I810_LOG_MIN_TEX_REGION_SIZE 16 19#define I810_LOG_MIN_TEX_REGION_SIZE 16
20#endif 20#endif
21 21
22#define I810_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ 22#define I810_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */
23#define I810_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ 23#define I810_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */
24#define I810_UPLOAD_CTX 0x4 24#define I810_UPLOAD_CTX 0x4
25#define I810_UPLOAD_BUFFERS 0x8 25#define I810_UPLOAD_BUFFERS 0x8
26#define I810_UPLOAD_TEX0 0x10 26#define I810_UPLOAD_TEX0 0x10
27#define I810_UPLOAD_TEX1 0x20 27#define I810_UPLOAD_TEX1 0x20
28#define I810_UPLOAD_CLIPRECTS 0x40 28#define I810_UPLOAD_CLIPRECTS 0x40
29 29
30
31/* Indices into buf.Setup where various bits of state are mirrored per 30/* Indices into buf.Setup where various bits of state are mirrored per
32 * context and per buffer. These can be fired at the card as a unit, 31 * context and per buffer. These can be fired at the card as a unit,
33 * or in a piecewise fashion as required. 32 * or in a piecewise fashion as required.
34 */ 33 */
35 34
36/* Destbuffer state 35/* Destbuffer state
37 * - backbuffer linear offset and pitch -- invarient in the current dri 36 * - backbuffer linear offset and pitch -- invarient in the current dri
38 * - zbuffer linear offset and pitch -- also invarient 37 * - zbuffer linear offset and pitch -- also invarient
39 * - drawing origin in back and depth buffers. 38 * - drawing origin in back and depth buffers.
@@ -55,13 +54,13 @@
55/* Context state 54/* Context state
56 */ 55 */
57#define I810_CTXREG_CF0 0 /* GFX_OP_COLOR_FACTOR */ 56#define I810_CTXREG_CF0 0 /* GFX_OP_COLOR_FACTOR */
58#define I810_CTXREG_CF1 1 57#define I810_CTXREG_CF1 1
59#define I810_CTXREG_ST0 2 /* GFX_OP_STIPPLE */ 58#define I810_CTXREG_ST0 2 /* GFX_OP_STIPPLE */
60#define I810_CTXREG_ST1 3 59#define I810_CTXREG_ST1 3
61#define I810_CTXREG_VF 4 /* GFX_OP_VERTEX_FMT */ 60#define I810_CTXREG_VF 4 /* GFX_OP_VERTEX_FMT */
62#define I810_CTXREG_MT 5 /* GFX_OP_MAP_TEXELS */ 61#define I810_CTXREG_MT 5 /* GFX_OP_MAP_TEXELS */
63#define I810_CTXREG_MC0 6 /* GFX_OP_MAP_COLOR_STAGES - stage 0 */ 62#define I810_CTXREG_MC0 6 /* GFX_OP_MAP_COLOR_STAGES - stage 0 */
64#define I810_CTXREG_MC1 7 /* GFX_OP_MAP_COLOR_STAGES - stage 1 */ 63#define I810_CTXREG_MC1 7 /* GFX_OP_MAP_COLOR_STAGES - stage 1 */
65#define I810_CTXREG_MC2 8 /* GFX_OP_MAP_COLOR_STAGES - stage 2 */ 64#define I810_CTXREG_MC2 8 /* GFX_OP_MAP_COLOR_STAGES - stage 2 */
66#define I810_CTXREG_MA0 9 /* GFX_OP_MAP_ALPHA_STAGES - stage 0 */ 65#define I810_CTXREG_MA0 9 /* GFX_OP_MAP_ALPHA_STAGES - stage 0 */
67#define I810_CTXREG_MA1 10 /* GFX_OP_MAP_ALPHA_STAGES - stage 1 */ 66#define I810_CTXREG_MA1 10 /* GFX_OP_MAP_ALPHA_STAGES - stage 1 */
@@ -74,14 +73,14 @@
74#define I810_CTXREG_PV 17 /* GFX_OP_PV_RULE -- Invarient! */ 73#define I810_CTXREG_PV 17 /* GFX_OP_PV_RULE -- Invarient! */
75#define I810_CTXREG_ZA 18 /* GFX_OP_ZBIAS_ALPHAFUNC */ 74#define I810_CTXREG_ZA 18 /* GFX_OP_ZBIAS_ALPHAFUNC */
76#define I810_CTXREG_AA 19 /* GFX_OP_ANTIALIAS */ 75#define I810_CTXREG_AA 19 /* GFX_OP_ANTIALIAS */
77#define I810_CTX_SETUP_SIZE 20 76#define I810_CTX_SETUP_SIZE 20
78 77
79/* Texture state (per tex unit) 78/* Texture state (per tex unit)
80 */ 79 */
81#define I810_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (4 dwords) */ 80#define I810_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (4 dwords) */
82#define I810_TEXREG_MI1 1 81#define I810_TEXREG_MI1 1
83#define I810_TEXREG_MI2 2 82#define I810_TEXREG_MI2 2
84#define I810_TEXREG_MI3 3 83#define I810_TEXREG_MI3 3
85#define I810_TEXREG_MF 4 /* GFX_OP_MAP_FILTER */ 84#define I810_TEXREG_MF 4 /* GFX_OP_MAP_FILTER */
86#define I810_TEXREG_MLC 5 /* GFX_OP_MAP_LOD_CTL */ 85#define I810_TEXREG_MLC 5 /* GFX_OP_MAP_LOD_CTL */
87#define I810_TEXREG_MLL 6 /* GFX_OP_MAP_LOD_LIMITS */ 86#define I810_TEXREG_MLL 6 /* GFX_OP_MAP_LOD_LIMITS */
@@ -98,7 +97,7 @@ typedef enum _drm_i810_init_func {
98 I810_INIT_DMA = 0x01, 97 I810_INIT_DMA = 0x01,
99 I810_CLEANUP_DMA = 0x02, 98 I810_CLEANUP_DMA = 0x02,
100 I810_INIT_DMA_1_4 = 0x03 99 I810_INIT_DMA_1_4 = 0x03
101 } drm_i810_init_func_t; 100} drm_i810_init_func_t;
102 101
103/* This is the init structure after v1.2 */ 102/* This is the init structure after v1.2 */
104typedef struct _drm_i810_init { 103typedef struct _drm_i810_init {
@@ -122,7 +121,7 @@ typedef struct _drm_i810_init {
122 unsigned int w; 121 unsigned int w;
123 unsigned int h; 122 unsigned int h;
124 unsigned int pitch; 123 unsigned int pitch;
125 unsigned int pitch_bits; 124 unsigned int pitch_bits;
126} drm_i810_init_t; 125} drm_i810_init_t;
127 126
128/* This is the init structure prior to v1.2 */ 127/* This is the init structure prior to v1.2 */
@@ -140,23 +139,23 @@ typedef struct _drm_i810_pre12_init {
140 unsigned int w; 139 unsigned int w;
141 unsigned int h; 140 unsigned int h;
142 unsigned int pitch; 141 unsigned int pitch;
143 unsigned int pitch_bits; 142 unsigned int pitch_bits;
144} drm_i810_pre12_init_t; 143} drm_i810_pre12_init_t;
145 144
146/* Warning: If you change the SAREA structure you must change the Xserver 145/* Warning: If you change the SAREA structure you must change the Xserver
147 * structure as well */ 146 * structure as well */
148 147
149typedef struct _drm_i810_tex_region { 148typedef struct _drm_i810_tex_region {
150 unsigned char next, prev; /* indices to form a circular LRU */ 149 unsigned char next, prev; /* indices to form a circular LRU */
151 unsigned char in_use; /* owned by a client, or free? */ 150 unsigned char in_use; /* owned by a client, or free? */
152 int age; /* tracked by clients to update local LRU's */ 151 int age; /* tracked by clients to update local LRU's */
153} drm_i810_tex_region_t; 152} drm_i810_tex_region_t;
154 153
155typedef struct _drm_i810_sarea { 154typedef struct _drm_i810_sarea {
156 unsigned int ContextState[I810_CTX_SETUP_SIZE]; 155 unsigned int ContextState[I810_CTX_SETUP_SIZE];
157 unsigned int BufferState[I810_DEST_SETUP_SIZE]; 156 unsigned int BufferState[I810_DEST_SETUP_SIZE];
158 unsigned int TexState[2][I810_TEX_SETUP_SIZE]; 157 unsigned int TexState[2][I810_TEX_SETUP_SIZE];
159 unsigned int dirty; 158 unsigned int dirty;
160 159
161 unsigned int nbox; 160 unsigned int nbox;
162 drm_clip_rect_t boxes[I810_NR_SAREA_CLIPRECTS]; 161 drm_clip_rect_t boxes[I810_NR_SAREA_CLIPRECTS];
@@ -174,22 +173,22 @@ typedef struct _drm_i810_sarea {
174 * texture space, and can make informed decisions as to which 173 * texture space, and can make informed decisions as to which
175 * areas to kick out. There is no need to choose whether to 174 * areas to kick out. There is no need to choose whether to
176 * kick out your own texture or someone else's - simply eject 175 * kick out your own texture or someone else's - simply eject
177 * them all in LRU order. 176 * them all in LRU order.
178 */ 177 */
179 178
180 drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS+1]; 179 drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1];
181 /* Last elt is sentinal */ 180 /* Last elt is sentinal */
182 int texAge; /* last time texture was uploaded */ 181 int texAge; /* last time texture was uploaded */
183 int last_enqueue; /* last time a buffer was enqueued */ 182 int last_enqueue; /* last time a buffer was enqueued */
184 int last_dispatch; /* age of the most recently dispatched buffer */ 183 int last_dispatch; /* age of the most recently dispatched buffer */
185 int last_quiescent; /* */ 184 int last_quiescent; /* */
186 int ctxOwner; /* last context to upload state */ 185 int ctxOwner; /* last context to upload state */
187 186
188 int vertex_prim; 187 int vertex_prim;
189 188
190 int pf_enabled; /* is pageflipping allowed? */ 189 int pf_enabled; /* is pageflipping allowed? */
191 int pf_active; 190 int pf_active;
192 int pf_current_page; /* which buffer is being displayed? */ 191 int pf_current_page; /* which buffer is being displayed? */
193} drm_i810_sarea_t; 192} drm_i810_sarea_t;
194 193
195/* WARNING: If you change any of these defines, make sure to change the 194/* WARNING: If you change any of these defines, make sure to change the
@@ -243,13 +242,13 @@ typedef struct _drm_i810_clear {
243 * new set of cliprects. 242 * new set of cliprects.
244 */ 243 */
245typedef struct _drm_i810_vertex { 244typedef struct _drm_i810_vertex {
246 int idx; /* buffer index */ 245 int idx; /* buffer index */
247 int used; /* nr bytes in use */ 246 int used; /* nr bytes in use */
248 int discard; /* client is finished with the buffer? */ 247 int discard; /* client is finished with the buffer? */
249} drm_i810_vertex_t; 248} drm_i810_vertex_t;
250 249
251typedef struct _drm_i810_copy_t { 250typedef struct _drm_i810_copy_t {
252 int idx; /* buffer index */ 251 int idx; /* buffer index */
253 int used; /* nr bytes in use */ 252 int used; /* nr bytes in use */
254 void *address; /* Address to copy from */ 253 void *address; /* Address to copy from */
255} drm_i810_copy_t; 254} drm_i810_copy_t;
@@ -264,7 +263,6 @@ typedef struct _drm_i810_copy_t {
264#define PR_RECTS (0x7<<18) 263#define PR_RECTS (0x7<<18)
265#define PR_MASK (0x7<<18) 264#define PR_MASK (0x7<<18)
266 265
267
268typedef struct drm_i810_dma { 266typedef struct drm_i810_dma {
269 void *virtual; 267 void *virtual;
270 int request_idx; 268 int request_idx;
@@ -273,17 +271,16 @@ typedef struct drm_i810_dma {
273} drm_i810_dma_t; 271} drm_i810_dma_t;
274 272
275typedef struct _drm_i810_overlay_t { 273typedef struct _drm_i810_overlay_t {
276 unsigned int offset; /* Address of the Overlay Regs */ 274 unsigned int offset; /* Address of the Overlay Regs */
277 unsigned int physical; 275 unsigned int physical;
278} drm_i810_overlay_t; 276} drm_i810_overlay_t;
279 277
280typedef struct _drm_i810_mc { 278typedef struct _drm_i810_mc {
281 int idx; /* buffer index */ 279 int idx; /* buffer index */
282 int used; /* nr bytes in use */ 280 int used; /* nr bytes in use */
283 int num_blocks; /* number of GFXBlocks */ 281 int num_blocks; /* number of GFXBlocks */
284 int *length; /* List of lengths for GFXBlocks (FUTURE)*/ 282 int *length; /* List of lengths for GFXBlocks (FUTURE) */
285 unsigned int last_render; /* Last Render Request */ 283 unsigned int last_render; /* Last Render Request */
286} drm_i810_mc_t; 284} drm_i810_mc_t;
287 285
288 286#endif /* _I810_DRM_H_ */
289#endif /* _I810_DRM_H_ */
diff --git a/drivers/char/drm/i810_drv.c b/drivers/char/drm/i810_drv.c
index 00609329d578..327e2f1cc997 100644
--- a/drivers/char/drm/i810_drv.c
+++ b/drivers/char/drm/i810_drv.c
@@ -38,7 +38,7 @@
38 38
39#include "drm_pciids.h" 39#include "drm_pciids.h"
40 40
41static int postinit( struct drm_device *dev, unsigned long flags ) 41static int postinit(struct drm_device *dev, unsigned long flags)
42{ 42{
43 /* i810 has 4 more counters */ 43 /* i810 has 4 more counters */
44 dev->counters += 4; 44 dev->counters += 4;
@@ -46,29 +46,27 @@ static int postinit( struct drm_device *dev, unsigned long flags )
46 dev->types[7] = _DRM_STAT_PRIMARY; 46 dev->types[7] = _DRM_STAT_PRIMARY;
47 dev->types[8] = _DRM_STAT_SECONDARY; 47 dev->types[8] = _DRM_STAT_SECONDARY;
48 dev->types[9] = _DRM_STAT_DMA; 48 dev->types[9] = _DRM_STAT_DMA;
49 49
50 DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", 50 DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n",
51 DRIVER_NAME, 51 DRIVER_NAME,
52 DRIVER_MAJOR, 52 DRIVER_MAJOR,
53 DRIVER_MINOR, 53 DRIVER_MINOR,
54 DRIVER_PATCHLEVEL, 54 DRIVER_PATCHLEVEL,
55 DRIVER_DATE, 55 DRIVER_DATE, dev->primary.minor, pci_pretty_name(dev->pdev)
56 dev->primary.minor, 56 );
57 pci_pretty_name(dev->pdev)
58 );
59 return 0; 57 return 0;
60} 58}
61 59
62static int version( drm_version_t *version ) 60static int version(drm_version_t * version)
63{ 61{
64 int len; 62 int len;
65 63
66 version->version_major = DRIVER_MAJOR; 64 version->version_major = DRIVER_MAJOR;
67 version->version_minor = DRIVER_MINOR; 65 version->version_minor = DRIVER_MINOR;
68 version->version_patchlevel = DRIVER_PATCHLEVEL; 66 version->version_patchlevel = DRIVER_PATCHLEVEL;
69 DRM_COPY( version->name, DRIVER_NAME ); 67 DRM_COPY(version->name, DRIVER_NAME);
70 DRM_COPY( version->date, DRIVER_DATE ); 68 DRM_COPY(version->date, DRIVER_DATE);
71 DRM_COPY( version->desc, DRIVER_DESC ); 69 DRM_COPY(version->desc, DRIVER_DESC);
72 return 0; 70 return 0;
73} 71}
74 72
@@ -80,7 +78,9 @@ extern drm_ioctl_desc_t i810_ioctls[];
80extern int i810_max_ioctl; 78extern int i810_max_ioctl;
81 79
82static struct drm_driver driver = { 80static struct drm_driver driver = {
83 .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_DMA | DRIVER_DMA_QUEUE, 81 .driver_features =
82 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR |
83 DRIVER_HAVE_DMA | DRIVER_DMA_QUEUE,
84 .dev_priv_size = sizeof(drm_i810_buf_priv_t), 84 .dev_priv_size = sizeof(drm_i810_buf_priv_t),
85 .pretakedown = i810_driver_pretakedown, 85 .pretakedown = i810_driver_pretakedown,
86 .prerelease = i810_driver_prerelease, 86 .prerelease = i810_driver_prerelease,
@@ -94,18 +94,20 @@ static struct drm_driver driver = {
94 .version = version, 94 .version = version,
95 .ioctls = i810_ioctls, 95 .ioctls = i810_ioctls,
96 .fops = { 96 .fops = {
97 .owner = THIS_MODULE, 97 .owner = THIS_MODULE,
98 .open = drm_open, 98 .open = drm_open,
99 .release = drm_release, 99 .release = drm_release,
100 .ioctl = drm_ioctl, 100 .ioctl = drm_ioctl,
101 .mmap = drm_mmap, 101 .mmap = drm_mmap,
102 .poll = drm_poll, 102 .poll = drm_poll,
103 .fasync = drm_fasync, 103 .fasync = drm_fasync,
104 }, 104 }
105 ,
105 .pci_driver = { 106 .pci_driver = {
106 .name = DRIVER_NAME, 107 .name = DRIVER_NAME,
107 .id_table = pciidlist, 108 .id_table = pciidlist,
108 }, 109 }
110 ,
109}; 111};
110 112
111static int __init i810_init(void) 113static int __init i810_init(void)
@@ -122,6 +124,6 @@ static void __exit i810_exit(void)
122module_init(i810_init); 124module_init(i810_init);
123module_exit(i810_exit); 125module_exit(i810_exit);
124 126
125MODULE_AUTHOR( DRIVER_AUTHOR ); 127MODULE_AUTHOR(DRIVER_AUTHOR);
126MODULE_DESCRIPTION( DRIVER_DESC ); 128MODULE_DESCRIPTION(DRIVER_DESC);
127MODULE_LICENSE("GPL and additional rights"); 129MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/char/drm/i810_drv.h b/drivers/char/drm/i810_drv.h
index 62ee4f58c59a..2d6b594afa0d 100644
--- a/drivers/char/drm/i810_drv.h
+++ b/drivers/char/drm/i810_drv.h
@@ -56,14 +56,14 @@
56#define DRIVER_PATCHLEVEL 0 56#define DRIVER_PATCHLEVEL 0
57 57
58typedef struct drm_i810_buf_priv { 58typedef struct drm_i810_buf_priv {
59 u32 *in_use; 59 u32 *in_use;
60 int my_use_idx; 60 int my_use_idx;
61 int currently_mapped; 61 int currently_mapped;
62 void *virtual; 62 void *virtual;
63 void *kernel_virtual; 63 void *kernel_virtual;
64} drm_i810_buf_priv_t; 64} drm_i810_buf_priv_t;
65 65
66typedef struct _drm_i810_ring_buffer{ 66typedef struct _drm_i810_ring_buffer {
67 int tail_mask; 67 int tail_mask;
68 unsigned long Start; 68 unsigned long Start;
69 unsigned long End; 69 unsigned long End;
@@ -79,16 +79,15 @@ typedef struct drm_i810_private {
79 drm_map_t *mmio_map; 79 drm_map_t *mmio_map;
80 80
81 drm_i810_sarea_t *sarea_priv; 81 drm_i810_sarea_t *sarea_priv;
82 drm_i810_ring_buffer_t ring; 82 drm_i810_ring_buffer_t ring;
83 83
84 void *hw_status_page; 84 void *hw_status_page;
85 unsigned long counter; 85 unsigned long counter;
86 86
87 dma_addr_t dma_status_page; 87 dma_addr_t dma_status_page;
88 88
89 drm_buf_t *mmap_buffer; 89 drm_buf_t *mmap_buffer;
90 90
91
92 u32 front_di1, back_di1, zi1; 91 u32 front_di1, back_di1, zi1;
93 92
94 int back_offset; 93 int back_offset;
@@ -97,7 +96,7 @@ typedef struct drm_i810_private {
97 int overlay_physical; 96 int overlay_physical;
98 int w, h; 97 int w, h;
99 int pitch; 98 int pitch;
100 int back_pitch; 99 int back_pitch;
101 int depth_pitch; 100 int depth_pitch;
102 101
103 int do_boxes; 102 int do_boxes;
@@ -107,19 +106,19 @@ typedef struct drm_i810_private {
107 int page_flipping; 106 int page_flipping;
108 107
109 wait_queue_head_t irq_queue; 108 wait_queue_head_t irq_queue;
110 atomic_t irq_received; 109 atomic_t irq_received;
111 atomic_t irq_emitted; 110 atomic_t irq_emitted;
112 111
113 int front_offset; 112 int front_offset;
114} drm_i810_private_t; 113} drm_i810_private_t;
115 114
116 /* i810_dma.c */ 115 /* i810_dma.c */
117extern void i810_reclaim_buffers(drm_device_t *dev, struct file *filp); 116extern void i810_reclaim_buffers(drm_device_t * dev, struct file *filp);
118 117
119extern int i810_driver_dma_quiescent(drm_device_t *dev); 118extern int i810_driver_dma_quiescent(drm_device_t * dev);
120extern void i810_driver_release(drm_device_t *dev, struct file *filp); 119extern void i810_driver_release(drm_device_t * dev, struct file *filp);
121extern void i810_driver_pretakedown(drm_device_t *dev); 120extern void i810_driver_pretakedown(drm_device_t * dev);
122extern void i810_driver_prerelease(drm_device_t *dev, DRMFILE filp); 121extern void i810_driver_prerelease(drm_device_t * dev, DRMFILE filp);
123extern int i810_driver_device_is_agp(drm_device_t * dev); 122extern int i810_driver_device_is_agp(drm_device_t * dev);
124 123
125#define I810_BASE(reg) ((unsigned long) \ 124#define I810_BASE(reg) ((unsigned long) \
@@ -170,7 +169,6 @@ extern int i810_driver_device_is_agp(drm_device_t * dev);
170#define INST_OP_FLUSH 0x02000000 169#define INST_OP_FLUSH 0x02000000
171#define INST_FLUSH_MAP_CACHE 0x00000001 170#define INST_FLUSH_MAP_CACHE 0x00000001
172 171
173
174#define BB1_START_ADDR_MASK (~0x7) 172#define BB1_START_ADDR_MASK (~0x7)
175#define BB1_PROTECTED (1<<0) 173#define BB1_PROTECTED (1<<0)
176#define BB1_UNPROTECTED (0<<0) 174#define BB1_UNPROTECTED (0<<0)
@@ -229,8 +227,8 @@ extern int i810_driver_device_is_agp(drm_device_t * dev);
229#define BR00_OP_SRC_COPY_BLT 0x10C00000 227#define BR00_OP_SRC_COPY_BLT 0x10C00000
230#define BR13_SOLID_PATTERN 0x80000000 228#define BR13_SOLID_PATTERN 0x80000000
231 229
232#define WAIT_FOR_PLANE_A_SCANLINES (1<<1) 230#define WAIT_FOR_PLANE_A_SCANLINES (1<<1)
233#define WAIT_FOR_PLANE_A_FLIP (1<<2) 231#define WAIT_FOR_PLANE_A_FLIP (1<<2)
234#define WAIT_FOR_VBLANK (1<<3) 232#define WAIT_FOR_VBLANK (1<<3)
235 233
236#endif 234#endif
diff --git a/drivers/char/drm/i830_dma.c b/drivers/char/drm/i830_dma.c
index 6f89d5796ef3..e1107ecb16e3 100644
--- a/drivers/char/drm/i830_dma.c
+++ b/drivers/char/drm/i830_dma.c
@@ -11,11 +11,11 @@
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the 12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions: 13 * Software is furnished to do so, subject to the following conditions:
14 * 14 *
15 * The above copyright notice and this permission notice (including the next 15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the 16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software. 17 * Software.
18 * 18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -47,103 +47,104 @@
47#define I830_BUF_UNMAPPED 0 47#define I830_BUF_UNMAPPED 0
48#define I830_BUF_MAPPED 1 48#define I830_BUF_MAPPED 1
49 49
50static drm_buf_t *i830_freelist_get(drm_device_t *dev) 50static drm_buf_t *i830_freelist_get(drm_device_t * dev)
51{ 51{
52 drm_device_dma_t *dma = dev->dma; 52 drm_device_dma_t *dma = dev->dma;
53 int i; 53 int i;
54 int used; 54 int used;
55 55
56 /* Linear search might not be the best solution */ 56 /* Linear search might not be the best solution */
57 57
58 for (i = 0; i < dma->buf_count; i++) { 58 for (i = 0; i < dma->buf_count; i++) {
59 drm_buf_t *buf = dma->buflist[ i ]; 59 drm_buf_t *buf = dma->buflist[i];
60 drm_i830_buf_priv_t *buf_priv = buf->dev_private; 60 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
61 /* In use is already a pointer */ 61 /* In use is already a pointer */
62 used = cmpxchg(buf_priv->in_use, I830_BUF_FREE, 62 used = cmpxchg(buf_priv->in_use, I830_BUF_FREE,
63 I830_BUF_CLIENT); 63 I830_BUF_CLIENT);
64 if(used == I830_BUF_FREE) { 64 if (used == I830_BUF_FREE) {
65 return buf; 65 return buf;
66 } 66 }
67 } 67 }
68 return NULL; 68 return NULL;
69} 69}
70 70
71/* This should only be called if the buffer is not sent to the hardware 71/* This should only be called if the buffer is not sent to the hardware
72 * yet, the hardware updates in use for us once its on the ring buffer. 72 * yet, the hardware updates in use for us once its on the ring buffer.
73 */ 73 */
74 74
75static int i830_freelist_put(drm_device_t *dev, drm_buf_t *buf) 75static int i830_freelist_put(drm_device_t * dev, drm_buf_t * buf)
76{ 76{
77 drm_i830_buf_priv_t *buf_priv = buf->dev_private; 77 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
78 int used; 78 int used;
79 79
80 /* In use is already a pointer */ 80 /* In use is already a pointer */
81 used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, I830_BUF_FREE); 81 used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, I830_BUF_FREE);
82 if(used != I830_BUF_CLIENT) { 82 if (used != I830_BUF_CLIENT) {
83 DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx); 83 DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
84 return -EINVAL; 84 return -EINVAL;
85 } 85 }
86 86
87 return 0; 87 return 0;
88} 88}
89 89
90static int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma) 90static int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
91{ 91{
92 drm_file_t *priv = filp->private_data; 92 drm_file_t *priv = filp->private_data;
93 drm_device_t *dev; 93 drm_device_t *dev;
94 drm_i830_private_t *dev_priv; 94 drm_i830_private_t *dev_priv;
95 drm_buf_t *buf; 95 drm_buf_t *buf;
96 drm_i830_buf_priv_t *buf_priv; 96 drm_i830_buf_priv_t *buf_priv;
97 97
98 lock_kernel(); 98 lock_kernel();
99 dev = priv->head->dev; 99 dev = priv->head->dev;
100 dev_priv = dev->dev_private; 100 dev_priv = dev->dev_private;
101 buf = dev_priv->mmap_buffer; 101 buf = dev_priv->mmap_buffer;
102 buf_priv = buf->dev_private; 102 buf_priv = buf->dev_private;
103 103
104 vma->vm_flags |= (VM_IO | VM_DONTCOPY); 104 vma->vm_flags |= (VM_IO | VM_DONTCOPY);
105 vma->vm_file = filp; 105 vma->vm_file = filp;
106 106
107 buf_priv->currently_mapped = I830_BUF_MAPPED; 107 buf_priv->currently_mapped = I830_BUF_MAPPED;
108 unlock_kernel(); 108 unlock_kernel();
109 109
110 if (io_remap_pfn_range(vma, vma->vm_start, 110 if (io_remap_pfn_range(vma, vma->vm_start,
111 VM_OFFSET(vma) >> PAGE_SHIFT, 111 VM_OFFSET(vma) >> PAGE_SHIFT,
112 vma->vm_end - vma->vm_start, 112 vma->vm_end - vma->vm_start, vma->vm_page_prot))
113 vma->vm_page_prot)) return -EAGAIN; 113 return -EAGAIN;
114 return 0; 114 return 0;
115} 115}
116 116
117static struct file_operations i830_buffer_fops = { 117static struct file_operations i830_buffer_fops = {
118 .open = drm_open, 118 .open = drm_open,
119 .flush = drm_flush, 119 .flush = drm_flush,
120 .release = drm_release, 120 .release = drm_release,
121 .ioctl = drm_ioctl, 121 .ioctl = drm_ioctl,
122 .mmap = i830_mmap_buffers, 122 .mmap = i830_mmap_buffers,
123 .fasync = drm_fasync, 123 .fasync = drm_fasync,
124}; 124};
125 125
126static int i830_map_buffer(drm_buf_t *buf, struct file *filp) 126static int i830_map_buffer(drm_buf_t * buf, struct file *filp)
127{ 127{
128 drm_file_t *priv = filp->private_data; 128 drm_file_t *priv = filp->private_data;
129 drm_device_t *dev = priv->head->dev; 129 drm_device_t *dev = priv->head->dev;
130 drm_i830_buf_priv_t *buf_priv = buf->dev_private; 130 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
131 drm_i830_private_t *dev_priv = dev->dev_private; 131 drm_i830_private_t *dev_priv = dev->dev_private;
132 struct file_operations *old_fops; 132 struct file_operations *old_fops;
133 unsigned long virtual; 133 unsigned long virtual;
134 int retcode = 0; 134 int retcode = 0;
135 135
136 if(buf_priv->currently_mapped == I830_BUF_MAPPED) return -EINVAL; 136 if (buf_priv->currently_mapped == I830_BUF_MAPPED)
137 return -EINVAL;
137 138
138 down_write( &current->mm->mmap_sem ); 139 down_write(&current->mm->mmap_sem);
139 old_fops = filp->f_op; 140 old_fops = filp->f_op;
140 filp->f_op = &i830_buffer_fops; 141 filp->f_op = &i830_buffer_fops;
141 dev_priv->mmap_buffer = buf; 142 dev_priv->mmap_buffer = buf;
142 virtual = do_mmap(filp, 0, buf->total, PROT_READ|PROT_WRITE, 143 virtual = do_mmap(filp, 0, buf->total, PROT_READ | PROT_WRITE,
143 MAP_SHARED, buf->bus_address); 144 MAP_SHARED, buf->bus_address);
144 dev_priv->mmap_buffer = NULL; 145 dev_priv->mmap_buffer = NULL;
145 filp->f_op = old_fops; 146 filp->f_op = old_fops;
146 if (IS_ERR((void *)virtual)) { /* ugh */ 147 if (IS_ERR((void *)virtual)) { /* ugh */
147 /* Real error */ 148 /* Real error */
148 DRM_ERROR("mmap error\n"); 149 DRM_ERROR("mmap error\n");
149 retcode = virtual; 150 retcode = virtual;
@@ -151,17 +152,17 @@ static int i830_map_buffer(drm_buf_t *buf, struct file *filp)
151 } else { 152 } else {
152 buf_priv->virtual = (void __user *)virtual; 153 buf_priv->virtual = (void __user *)virtual;
153 } 154 }
154 up_write( &current->mm->mmap_sem ); 155 up_write(&current->mm->mmap_sem);
155 156
156 return retcode; 157 return retcode;
157} 158}
158 159
159static int i830_unmap_buffer(drm_buf_t *buf) 160static int i830_unmap_buffer(drm_buf_t * buf)
160{ 161{
161 drm_i830_buf_priv_t *buf_priv = buf->dev_private; 162 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
162 int retcode = 0; 163 int retcode = 0;
163 164
164 if(buf_priv->currently_mapped != I830_BUF_MAPPED) 165 if (buf_priv->currently_mapped != I830_BUF_MAPPED)
165 return -EINVAL; 166 return -EINVAL;
166 167
167 down_write(&current->mm->mmap_sem); 168 down_write(&current->mm->mmap_sem);
@@ -170,43 +171,43 @@ static int i830_unmap_buffer(drm_buf_t *buf)
170 (size_t) buf->total); 171 (size_t) buf->total);
171 up_write(&current->mm->mmap_sem); 172 up_write(&current->mm->mmap_sem);
172 173
173 buf_priv->currently_mapped = I830_BUF_UNMAPPED; 174 buf_priv->currently_mapped = I830_BUF_UNMAPPED;
174 buf_priv->virtual = NULL; 175 buf_priv->virtual = NULL;
175 176
176 return retcode; 177 return retcode;
177} 178}
178 179
179static int i830_dma_get_buffer(drm_device_t *dev, drm_i830_dma_t *d, 180static int i830_dma_get_buffer(drm_device_t * dev, drm_i830_dma_t * d,
180 struct file *filp) 181 struct file *filp)
181{ 182{
182 drm_buf_t *buf; 183 drm_buf_t *buf;
183 drm_i830_buf_priv_t *buf_priv; 184 drm_i830_buf_priv_t *buf_priv;
184 int retcode = 0; 185 int retcode = 0;
185 186
186 buf = i830_freelist_get(dev); 187 buf = i830_freelist_get(dev);
187 if (!buf) { 188 if (!buf) {
188 retcode = -ENOMEM; 189 retcode = -ENOMEM;
189 DRM_DEBUG("retcode=%d\n", retcode); 190 DRM_DEBUG("retcode=%d\n", retcode);
190 return retcode; 191 return retcode;
191 } 192 }
192 193
193 retcode = i830_map_buffer(buf, filp); 194 retcode = i830_map_buffer(buf, filp);
194 if(retcode) { 195 if (retcode) {
195 i830_freelist_put(dev, buf); 196 i830_freelist_put(dev, buf);
196 DRM_ERROR("mapbuf failed, retcode %d\n", retcode); 197 DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
197 return retcode; 198 return retcode;
198 } 199 }
199 buf->filp = filp; 200 buf->filp = filp;
200 buf_priv = buf->dev_private; 201 buf_priv = buf->dev_private;
201 d->granted = 1; 202 d->granted = 1;
202 d->request_idx = buf->idx; 203 d->request_idx = buf->idx;
203 d->request_size = buf->total; 204 d->request_size = buf->total;
204 d->virtual = buf_priv->virtual; 205 d->virtual = buf_priv->virtual;
205 206
206 return retcode; 207 return retcode;
207} 208}
208 209
209static int i830_dma_cleanup(drm_device_t *dev) 210static int i830_dma_cleanup(drm_device_t * dev)
210{ 211{
211 drm_device_dma_t *dma = dev->dma; 212 drm_device_dma_t *dma = dev->dma;
212 213
@@ -214,140 +215,144 @@ static int i830_dma_cleanup(drm_device_t *dev)
214 * may not have been called from userspace and after dev_private 215 * may not have been called from userspace and after dev_private
215 * is freed, it's too late. 216 * is freed, it's too late.
216 */ 217 */
217 if ( dev->irq_enabled ) drm_irq_uninstall(dev); 218 if (dev->irq_enabled)
219 drm_irq_uninstall(dev);
218 220
219 if (dev->dev_private) { 221 if (dev->dev_private) {
220 int i; 222 int i;
221 drm_i830_private_t *dev_priv = 223 drm_i830_private_t *dev_priv =
222 (drm_i830_private_t *) dev->dev_private; 224 (drm_i830_private_t *) dev->dev_private;
223 225
224 if (dev_priv->ring.virtual_start) { 226 if (dev_priv->ring.virtual_start) {
225 drm_ioremapfree((void *) dev_priv->ring.virtual_start, 227 drm_ioremapfree((void *)dev_priv->ring.virtual_start,
226 dev_priv->ring.Size, dev); 228 dev_priv->ring.Size, dev);
227 } 229 }
228 if (dev_priv->hw_status_page) { 230 if (dev_priv->hw_status_page) {
229 pci_free_consistent(dev->pdev, PAGE_SIZE, 231 pci_free_consistent(dev->pdev, PAGE_SIZE,
230 dev_priv->hw_status_page, 232 dev_priv->hw_status_page,
231 dev_priv->dma_status_page); 233 dev_priv->dma_status_page);
232 /* Need to rewrite hardware status page */ 234 /* Need to rewrite hardware status page */
233 I830_WRITE(0x02080, 0x1ffff000); 235 I830_WRITE(0x02080, 0x1ffff000);
234 } 236 }
235 237
236 drm_free(dev->dev_private, sizeof(drm_i830_private_t), 238 drm_free(dev->dev_private, sizeof(drm_i830_private_t),
237 DRM_MEM_DRIVER); 239 DRM_MEM_DRIVER);
238 dev->dev_private = NULL; 240 dev->dev_private = NULL;
239 241
240 for (i = 0; i < dma->buf_count; i++) { 242 for (i = 0; i < dma->buf_count; i++) {
241 drm_buf_t *buf = dma->buflist[ i ]; 243 drm_buf_t *buf = dma->buflist[i];
242 drm_i830_buf_priv_t *buf_priv = buf->dev_private; 244 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
243 if ( buf_priv->kernel_virtual && buf->total ) 245 if (buf_priv->kernel_virtual && buf->total)
244 drm_ioremapfree(buf_priv->kernel_virtual, buf->total, dev); 246 drm_ioremapfree(buf_priv->kernel_virtual,
247 buf->total, dev);
245 } 248 }
246 } 249 }
247 return 0; 250 return 0;
248} 251}
249 252
250int i830_wait_ring(drm_device_t *dev, int n, const char *caller) 253int i830_wait_ring(drm_device_t * dev, int n, const char *caller)
251{ 254{
252 drm_i830_private_t *dev_priv = dev->dev_private; 255 drm_i830_private_t *dev_priv = dev->dev_private;
253 drm_i830_ring_buffer_t *ring = &(dev_priv->ring); 256 drm_i830_ring_buffer_t *ring = &(dev_priv->ring);
254 int iters = 0; 257 int iters = 0;
255 unsigned long end; 258 unsigned long end;
256 unsigned int last_head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR; 259 unsigned int last_head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
257 260
258 end = jiffies + (HZ*3); 261 end = jiffies + (HZ * 3);
259 while (ring->space < n) { 262 while (ring->space < n) {
260 ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR; 263 ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
261 ring->space = ring->head - (ring->tail+8); 264 ring->space = ring->head - (ring->tail + 8);
262 if (ring->space < 0) ring->space += ring->Size; 265 if (ring->space < 0)
263 266 ring->space += ring->Size;
267
264 if (ring->head != last_head) { 268 if (ring->head != last_head) {
265 end = jiffies + (HZ*3); 269 end = jiffies + (HZ * 3);
266 last_head = ring->head; 270 last_head = ring->head;
267 } 271 }
268 272
269 iters++; 273 iters++;
270 if(time_before(end, jiffies)) { 274 if (time_before(end, jiffies)) {
271 DRM_ERROR("space: %d wanted %d\n", ring->space, n); 275 DRM_ERROR("space: %d wanted %d\n", ring->space, n);
272 DRM_ERROR("lockup\n"); 276 DRM_ERROR("lockup\n");
273 goto out_wait_ring; 277 goto out_wait_ring;
274 } 278 }
275 udelay(1); 279 udelay(1);
276 dev_priv->sarea_priv->perf_boxes |= I830_BOX_WAIT; 280 dev_priv->sarea_priv->perf_boxes |= I830_BOX_WAIT;
277 } 281 }
278 282
279out_wait_ring: 283 out_wait_ring:
280 return iters; 284 return iters;
281} 285}
282 286
283static void i830_kernel_lost_context(drm_device_t *dev) 287static void i830_kernel_lost_context(drm_device_t * dev)
284{ 288{
285 drm_i830_private_t *dev_priv = dev->dev_private; 289 drm_i830_private_t *dev_priv = dev->dev_private;
286 drm_i830_ring_buffer_t *ring = &(dev_priv->ring); 290 drm_i830_ring_buffer_t *ring = &(dev_priv->ring);
287 291
288 ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR; 292 ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
289 ring->tail = I830_READ(LP_RING + RING_TAIL) & TAIL_ADDR; 293 ring->tail = I830_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
290 ring->space = ring->head - (ring->tail+8); 294 ring->space = ring->head - (ring->tail + 8);
291 if (ring->space < 0) ring->space += ring->Size; 295 if (ring->space < 0)
296 ring->space += ring->Size;
292 297
293 if (ring->head == ring->tail) 298 if (ring->head == ring->tail)
294 dev_priv->sarea_priv->perf_boxes |= I830_BOX_RING_EMPTY; 299 dev_priv->sarea_priv->perf_boxes |= I830_BOX_RING_EMPTY;
295} 300}
296 301
297static int i830_freelist_init(drm_device_t *dev, drm_i830_private_t *dev_priv) 302static int i830_freelist_init(drm_device_t * dev, drm_i830_private_t * dev_priv)
298{ 303{
299 drm_device_dma_t *dma = dev->dma; 304 drm_device_dma_t *dma = dev->dma;
300 int my_idx = 36; 305 int my_idx = 36;
301 u32 *hw_status = (u32 *)(dev_priv->hw_status_page + my_idx); 306 u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx);
302 int i; 307 int i;
303 308
304 if(dma->buf_count > 1019) { 309 if (dma->buf_count > 1019) {
305 /* Not enough space in the status page for the freelist */ 310 /* Not enough space in the status page for the freelist */
306 return -EINVAL; 311 return -EINVAL;
307 } 312 }
308 313
309 for (i = 0; i < dma->buf_count; i++) { 314 for (i = 0; i < dma->buf_count; i++) {
310 drm_buf_t *buf = dma->buflist[ i ]; 315 drm_buf_t *buf = dma->buflist[i];
311 drm_i830_buf_priv_t *buf_priv = buf->dev_private; 316 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
312 317
313 buf_priv->in_use = hw_status++; 318 buf_priv->in_use = hw_status++;
314 buf_priv->my_use_idx = my_idx; 319 buf_priv->my_use_idx = my_idx;
315 my_idx += 4; 320 my_idx += 4;
316 321
317 *buf_priv->in_use = I830_BUF_FREE; 322 *buf_priv->in_use = I830_BUF_FREE;
318 323
319 buf_priv->kernel_virtual = drm_ioremap(buf->bus_address, 324 buf_priv->kernel_virtual = drm_ioremap(buf->bus_address,
320 buf->total, dev); 325 buf->total, dev);
321 } 326 }
322 return 0; 327 return 0;
323} 328}
324 329
325static int i830_dma_initialize(drm_device_t *dev, 330static int i830_dma_initialize(drm_device_t * dev,
326 drm_i830_private_t *dev_priv, 331 drm_i830_private_t * dev_priv,
327 drm_i830_init_t *init) 332 drm_i830_init_t * init)
328{ 333{
329 struct list_head *list; 334 struct list_head *list;
330 335
331 memset(dev_priv, 0, sizeof(drm_i830_private_t)); 336 memset(dev_priv, 0, sizeof(drm_i830_private_t));
332 337
333 list_for_each(list, &dev->maplist->head) { 338 list_for_each(list, &dev->maplist->head) {
334 drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head); 339 drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head);
335 if( r_list->map && 340 if (r_list->map &&
336 r_list->map->type == _DRM_SHM && 341 r_list->map->type == _DRM_SHM &&
337 r_list->map->flags & _DRM_CONTAINS_LOCK ) { 342 r_list->map->flags & _DRM_CONTAINS_LOCK) {
338 dev_priv->sarea_map = r_list->map; 343 dev_priv->sarea_map = r_list->map;
339 break; 344 break;
340 } 345 }
341 } 346 }
342 347
343 if(!dev_priv->sarea_map) { 348 if (!dev_priv->sarea_map) {
344 dev->dev_private = (void *)dev_priv; 349 dev->dev_private = (void *)dev_priv;
345 i830_dma_cleanup(dev); 350 i830_dma_cleanup(dev);
346 DRM_ERROR("can not find sarea!\n"); 351 DRM_ERROR("can not find sarea!\n");
347 return -EINVAL; 352 return -EINVAL;
348 } 353 }
349 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset); 354 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
350 if(!dev_priv->mmio_map) { 355 if (!dev_priv->mmio_map) {
351 dev->dev_private = (void *)dev_priv; 356 dev->dev_private = (void *)dev_priv;
352 i830_dma_cleanup(dev); 357 i830_dma_cleanup(dev);
353 DRM_ERROR("can not find mmio map!\n"); 358 DRM_ERROR("can not find mmio map!\n");
@@ -355,7 +360,7 @@ static int i830_dma_initialize(drm_device_t *dev,
355 } 360 }
356 dev->agp_buffer_token = init->buffers_offset; 361 dev->agp_buffer_token = init->buffers_offset;
357 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 362 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
358 if(!dev->agp_buffer_map) { 363 if (!dev->agp_buffer_map) {
359 dev->dev_private = (void *)dev_priv; 364 dev->dev_private = (void *)dev_priv;
360 i830_dma_cleanup(dev); 365 i830_dma_cleanup(dev);
361 DRM_ERROR("can not find dma buffer map!\n"); 366 DRM_ERROR("can not find dma buffer map!\n");
@@ -363,27 +368,26 @@ static int i830_dma_initialize(drm_device_t *dev,
363 } 368 }
364 369
365 dev_priv->sarea_priv = (drm_i830_sarea_t *) 370 dev_priv->sarea_priv = (drm_i830_sarea_t *)
366 ((u8 *)dev_priv->sarea_map->handle + 371 ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset);
367 init->sarea_priv_offset);
368 372
369 dev_priv->ring.Start = init->ring_start; 373 dev_priv->ring.Start = init->ring_start;
370 dev_priv->ring.End = init->ring_end; 374 dev_priv->ring.End = init->ring_end;
371 dev_priv->ring.Size = init->ring_size; 375 dev_priv->ring.Size = init->ring_size;
372 376
373 dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base + 377 dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base +
374 init->ring_start, 378 init->ring_start,
375 init->ring_size, dev); 379 init->ring_size, dev);
376 380
377 if (dev_priv->ring.virtual_start == NULL) { 381 if (dev_priv->ring.virtual_start == NULL) {
378 dev->dev_private = (void *) dev_priv; 382 dev->dev_private = (void *)dev_priv;
379 i830_dma_cleanup(dev); 383 i830_dma_cleanup(dev);
380 DRM_ERROR("can not ioremap virtual address for" 384 DRM_ERROR("can not ioremap virtual address for"
381 " ring buffer\n"); 385 " ring buffer\n");
382 return -ENOMEM; 386 return -ENOMEM;
383 } 387 }
384 388
385 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; 389 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
386 390
387 dev_priv->w = init->w; 391 dev_priv->w = init->w;
388 dev_priv->h = init->h; 392 dev_priv->h = init->h;
389 dev_priv->pitch = init->pitch; 393 dev_priv->pitch = init->pitch;
@@ -395,10 +399,10 @@ static int i830_dma_initialize(drm_device_t *dev,
395 dev_priv->back_di1 = init->back_offset | init->pitch_bits; 399 dev_priv->back_di1 = init->back_offset | init->pitch_bits;
396 dev_priv->zi1 = init->depth_offset | init->pitch_bits; 400 dev_priv->zi1 = init->depth_offset | init->pitch_bits;
397 401
398 DRM_DEBUG("front_di1 %x\n", dev_priv->front_di1); 402 DRM_DEBUG("front_di1 %x\n", dev_priv->front_di1);
399 DRM_DEBUG("back_offset %x\n", dev_priv->back_offset); 403 DRM_DEBUG("back_offset %x\n", dev_priv->back_offset);
400 DRM_DEBUG("back_di1 %x\n", dev_priv->back_di1); 404 DRM_DEBUG("back_di1 %x\n", dev_priv->back_di1);
401 DRM_DEBUG("pitch_bits %x\n", init->pitch_bits); 405 DRM_DEBUG("pitch_bits %x\n", init->pitch_bits);
402 406
403 dev_priv->cpp = init->cpp; 407 dev_priv->cpp = init->cpp;
404 /* We are using separate values as placeholders for mechanisms for 408 /* We are using separate values as placeholders for mechanisms for
@@ -410,63 +414,64 @@ static int i830_dma_initialize(drm_device_t *dev,
410 dev_priv->do_boxes = 0; 414 dev_priv->do_boxes = 0;
411 dev_priv->use_mi_batchbuffer_start = 0; 415 dev_priv->use_mi_batchbuffer_start = 0;
412 416
413 /* Program Hardware Status Page */ 417 /* Program Hardware Status Page */
414 dev_priv->hw_status_page = 418 dev_priv->hw_status_page =
415 pci_alloc_consistent(dev->pdev, PAGE_SIZE, 419 pci_alloc_consistent(dev->pdev, PAGE_SIZE,
416 &dev_priv->dma_status_page); 420 &dev_priv->dma_status_page);
417 if (!dev_priv->hw_status_page) { 421 if (!dev_priv->hw_status_page) {
418 dev->dev_private = (void *)dev_priv; 422 dev->dev_private = (void *)dev_priv;
419 i830_dma_cleanup(dev); 423 i830_dma_cleanup(dev);
420 DRM_ERROR("Can not allocate hardware status page\n"); 424 DRM_ERROR("Can not allocate hardware status page\n");
421 return -ENOMEM; 425 return -ENOMEM;
422 } 426 }
423 memset(dev_priv->hw_status_page, 0, PAGE_SIZE); 427 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
424 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); 428 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
425 429
426 I830_WRITE(0x02080, dev_priv->dma_status_page); 430 I830_WRITE(0x02080, dev_priv->dma_status_page);
427 DRM_DEBUG("Enabled hardware status page\n"); 431 DRM_DEBUG("Enabled hardware status page\n");
428 432
429 /* Now we need to init our freelist */ 433 /* Now we need to init our freelist */
430 if(i830_freelist_init(dev, dev_priv) != 0) { 434 if (i830_freelist_init(dev, dev_priv) != 0) {
431 dev->dev_private = (void *)dev_priv; 435 dev->dev_private = (void *)dev_priv;
432 i830_dma_cleanup(dev); 436 i830_dma_cleanup(dev);
433 DRM_ERROR("Not enough space in the status page for" 437 DRM_ERROR("Not enough space in the status page for"
434 " the freelist\n"); 438 " the freelist\n");
435 return -ENOMEM; 439 return -ENOMEM;
436 } 440 }
437 dev->dev_private = (void *)dev_priv; 441 dev->dev_private = (void *)dev_priv;
438 442
439 return 0; 443 return 0;
440} 444}
441 445
442static int i830_dma_init(struct inode *inode, struct file *filp, 446static int i830_dma_init(struct inode *inode, struct file *filp,
443 unsigned int cmd, unsigned long arg) 447 unsigned int cmd, unsigned long arg)
444{ 448{
445 drm_file_t *priv = filp->private_data; 449 drm_file_t *priv = filp->private_data;
446 drm_device_t *dev = priv->head->dev; 450 drm_device_t *dev = priv->head->dev;
447 drm_i830_private_t *dev_priv; 451 drm_i830_private_t *dev_priv;
448 drm_i830_init_t init; 452 drm_i830_init_t init;
449 int retcode = 0; 453 int retcode = 0;
450 454
451 if (copy_from_user(&init, (void * __user) arg, sizeof(init))) 455 if (copy_from_user(&init, (void *__user)arg, sizeof(init)))
452 return -EFAULT; 456 return -EFAULT;
453 457
454 switch(init.func) { 458 switch (init.func) {
455 case I830_INIT_DMA: 459 case I830_INIT_DMA:
456 dev_priv = drm_alloc(sizeof(drm_i830_private_t), 460 dev_priv = drm_alloc(sizeof(drm_i830_private_t),
457 DRM_MEM_DRIVER); 461 DRM_MEM_DRIVER);
458 if(dev_priv == NULL) return -ENOMEM; 462 if (dev_priv == NULL)
459 retcode = i830_dma_initialize(dev, dev_priv, &init); 463 return -ENOMEM;
460 break; 464 retcode = i830_dma_initialize(dev, dev_priv, &init);
461 case I830_CLEANUP_DMA: 465 break;
462 retcode = i830_dma_cleanup(dev); 466 case I830_CLEANUP_DMA:
463 break; 467 retcode = i830_dma_cleanup(dev);
464 default: 468 break;
465 retcode = -EINVAL; 469 default:
466 break; 470 retcode = -EINVAL;
471 break;
467 } 472 }
468 473
469 return retcode; 474 return retcode;
470} 475}
471 476
472#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 477#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
@@ -476,92 +481,89 @@ static int i830_dma_init(struct inode *inode, struct file *filp,
476/* Most efficient way to verify state for the i830 is as it is 481/* Most efficient way to verify state for the i830 is as it is
477 * emitted. Non-conformant state is silently dropped. 482 * emitted. Non-conformant state is silently dropped.
478 */ 483 */
479static void i830EmitContextVerified( drm_device_t *dev, 484static void i830EmitContextVerified(drm_device_t * dev, unsigned int *code)
480 unsigned int *code )
481{ 485{
482 drm_i830_private_t *dev_priv = dev->dev_private; 486 drm_i830_private_t *dev_priv = dev->dev_private;
483 int i, j = 0; 487 int i, j = 0;
484 unsigned int tmp; 488 unsigned int tmp;
485 RING_LOCALS; 489 RING_LOCALS;
486 490
487 BEGIN_LP_RING( I830_CTX_SETUP_SIZE + 4 ); 491 BEGIN_LP_RING(I830_CTX_SETUP_SIZE + 4);
488 492
489 for ( i = 0 ; i < I830_CTXREG_BLENDCOLR0 ; i++ ) { 493 for (i = 0; i < I830_CTXREG_BLENDCOLR0; i++) {
490 tmp = code[i]; 494 tmp = code[i];
491 if ((tmp & (7<<29)) == CMD_3D && 495 if ((tmp & (7 << 29)) == CMD_3D &&
492 (tmp & (0x1f<<24)) < (0x1d<<24)) { 496 (tmp & (0x1f << 24)) < (0x1d << 24)) {
493 OUT_RING( tmp ); 497 OUT_RING(tmp);
494 j++; 498 j++;
495 } else { 499 } else {
496 DRM_ERROR("Skipping %d\n", i); 500 DRM_ERROR("Skipping %d\n", i);
497 } 501 }
498 } 502 }
499 503
500 OUT_RING( STATE3D_CONST_BLEND_COLOR_CMD ); 504 OUT_RING(STATE3D_CONST_BLEND_COLOR_CMD);
501 OUT_RING( code[I830_CTXREG_BLENDCOLR] ); 505 OUT_RING(code[I830_CTXREG_BLENDCOLR]);
502 j += 2; 506 j += 2;
503 507
504 for ( i = I830_CTXREG_VF ; i < I830_CTXREG_MCSB0 ; i++ ) { 508 for (i = I830_CTXREG_VF; i < I830_CTXREG_MCSB0; i++) {
505 tmp = code[i]; 509 tmp = code[i];
506 if ((tmp & (7<<29)) == CMD_3D && 510 if ((tmp & (7 << 29)) == CMD_3D &&
507 (tmp & (0x1f<<24)) < (0x1d<<24)) { 511 (tmp & (0x1f << 24)) < (0x1d << 24)) {
508 OUT_RING( tmp ); 512 OUT_RING(tmp);
509 j++; 513 j++;
510 } else { 514 } else {
511 DRM_ERROR("Skipping %d\n", i); 515 DRM_ERROR("Skipping %d\n", i);
512 } 516 }
513 } 517 }
514 518
515 OUT_RING( STATE3D_MAP_COORD_SETBIND_CMD ); 519 OUT_RING(STATE3D_MAP_COORD_SETBIND_CMD);
516 OUT_RING( code[I830_CTXREG_MCSB1] ); 520 OUT_RING(code[I830_CTXREG_MCSB1]);
517 j += 2; 521 j += 2;
518 522
519 if (j & 1) 523 if (j & 1)
520 OUT_RING( 0 ); 524 OUT_RING(0);
521 525
522 ADVANCE_LP_RING(); 526 ADVANCE_LP_RING();
523} 527}
524 528
525static void i830EmitTexVerified( drm_device_t *dev, unsigned int *code ) 529static void i830EmitTexVerified(drm_device_t * dev, unsigned int *code)
526{ 530{
527 drm_i830_private_t *dev_priv = dev->dev_private; 531 drm_i830_private_t *dev_priv = dev->dev_private;
528 int i, j = 0; 532 int i, j = 0;
529 unsigned int tmp; 533 unsigned int tmp;
530 RING_LOCALS; 534 RING_LOCALS;
531 535
532 if (code[I830_TEXREG_MI0] == GFX_OP_MAP_INFO || 536 if (code[I830_TEXREG_MI0] == GFX_OP_MAP_INFO ||
533 (code[I830_TEXREG_MI0] & ~(0xf*LOAD_TEXTURE_MAP0)) == 537 (code[I830_TEXREG_MI0] & ~(0xf * LOAD_TEXTURE_MAP0)) ==
534 (STATE3D_LOAD_STATE_IMMEDIATE_2|4)) { 538 (STATE3D_LOAD_STATE_IMMEDIATE_2 | 4)) {
535 539
536 BEGIN_LP_RING( I830_TEX_SETUP_SIZE ); 540 BEGIN_LP_RING(I830_TEX_SETUP_SIZE);
537 541
538 OUT_RING( code[I830_TEXREG_MI0] ); /* TM0LI */ 542 OUT_RING(code[I830_TEXREG_MI0]); /* TM0LI */
539 OUT_RING( code[I830_TEXREG_MI1] ); /* TM0S0 */ 543 OUT_RING(code[I830_TEXREG_MI1]); /* TM0S0 */
540 OUT_RING( code[I830_TEXREG_MI2] ); /* TM0S1 */ 544 OUT_RING(code[I830_TEXREG_MI2]); /* TM0S1 */
541 OUT_RING( code[I830_TEXREG_MI3] ); /* TM0S2 */ 545 OUT_RING(code[I830_TEXREG_MI3]); /* TM0S2 */
542 OUT_RING( code[I830_TEXREG_MI4] ); /* TM0S3 */ 546 OUT_RING(code[I830_TEXREG_MI4]); /* TM0S3 */
543 OUT_RING( code[I830_TEXREG_MI5] ); /* TM0S4 */ 547 OUT_RING(code[I830_TEXREG_MI5]); /* TM0S4 */
544 548
545 for ( i = 6 ; i < I830_TEX_SETUP_SIZE ; i++ ) { 549 for (i = 6; i < I830_TEX_SETUP_SIZE; i++) {
546 tmp = code[i]; 550 tmp = code[i];
547 OUT_RING( tmp ); 551 OUT_RING(tmp);
548 j++; 552 j++;
549 } 553 }
550 554
551 if (j & 1) 555 if (j & 1)
552 OUT_RING( 0 ); 556 OUT_RING(0);
553 557
554 ADVANCE_LP_RING(); 558 ADVANCE_LP_RING();
555 } 559 } else
556 else
557 printk("rejected packet %x\n", code[0]); 560 printk("rejected packet %x\n", code[0]);
558} 561}
559 562
560static void i830EmitTexBlendVerified( drm_device_t *dev, 563static void i830EmitTexBlendVerified(drm_device_t * dev,
561 unsigned int *code, 564 unsigned int *code, unsigned int num)
562 unsigned int num)
563{ 565{
564 drm_i830_private_t *dev_priv = dev->dev_private; 566 drm_i830_private_t *dev_priv = dev->dev_private;
565 int i, j = 0; 567 int i, j = 0;
566 unsigned int tmp; 568 unsigned int tmp;
567 RING_LOCALS; 569 RING_LOCALS;
@@ -569,59 +571,54 @@ static void i830EmitTexBlendVerified( drm_device_t *dev,
569 if (!num) 571 if (!num)
570 return; 572 return;
571 573
572 BEGIN_LP_RING( num + 1 ); 574 BEGIN_LP_RING(num + 1);
573 575
574 for ( i = 0 ; i < num ; i++ ) { 576 for (i = 0; i < num; i++) {
575 tmp = code[i]; 577 tmp = code[i];
576 OUT_RING( tmp ); 578 OUT_RING(tmp);
577 j++; 579 j++;
578 } 580 }
579 581
580 if (j & 1) 582 if (j & 1)
581 OUT_RING( 0 ); 583 OUT_RING(0);
582 584
583 ADVANCE_LP_RING(); 585 ADVANCE_LP_RING();
584} 586}
585 587
586static void i830EmitTexPalette( drm_device_t *dev, 588static void i830EmitTexPalette(drm_device_t * dev,
587 unsigned int *palette, 589 unsigned int *palette, int number, int is_shared)
588 int number,
589 int is_shared )
590{ 590{
591 drm_i830_private_t *dev_priv = dev->dev_private; 591 drm_i830_private_t *dev_priv = dev->dev_private;
592 int i; 592 int i;
593 RING_LOCALS; 593 RING_LOCALS;
594 594
595 return; 595 return;
596 596
597 BEGIN_LP_RING( 258 ); 597 BEGIN_LP_RING(258);
598 598
599 if(is_shared == 1) { 599 if (is_shared == 1) {
600 OUT_RING(CMD_OP_MAP_PALETTE_LOAD | 600 OUT_RING(CMD_OP_MAP_PALETTE_LOAD |
601 MAP_PALETTE_NUM(0) | 601 MAP_PALETTE_NUM(0) | MAP_PALETTE_BOTH);
602 MAP_PALETTE_BOTH);
603 } else { 602 } else {
604 OUT_RING(CMD_OP_MAP_PALETTE_LOAD | MAP_PALETTE_NUM(number)); 603 OUT_RING(CMD_OP_MAP_PALETTE_LOAD | MAP_PALETTE_NUM(number));
605 } 604 }
606 for(i = 0; i < 256; i++) { 605 for (i = 0; i < 256; i++) {
607 OUT_RING(palette[i]); 606 OUT_RING(palette[i]);
608 } 607 }
609 OUT_RING(0); 608 OUT_RING(0);
610 /* KW: WHERE IS THE ADVANCE_LP_RING? This is effectively a noop! 609 /* KW: WHERE IS THE ADVANCE_LP_RING? This is effectively a noop!
611 */ 610 */
612} 611}
613 612
614/* Need to do some additional checking when setting the dest buffer. 613/* Need to do some additional checking when setting the dest buffer.
615 */ 614 */
616static void i830EmitDestVerified( drm_device_t *dev, 615static void i830EmitDestVerified(drm_device_t * dev, unsigned int *code)
617 unsigned int *code ) 616{
618{ 617 drm_i830_private_t *dev_priv = dev->dev_private;
619 drm_i830_private_t *dev_priv = dev->dev_private;
620 unsigned int tmp; 618 unsigned int tmp;
621 RING_LOCALS; 619 RING_LOCALS;
622 620
623 BEGIN_LP_RING( I830_DEST_SETUP_SIZE + 10 ); 621 BEGIN_LP_RING(I830_DEST_SETUP_SIZE + 10);
624
625 622
626 tmp = code[I830_DESTREG_CBUFADDR]; 623 tmp = code[I830_DESTREG_CBUFADDR];
627 if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) { 624 if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
@@ -630,18 +627,18 @@ static void i830EmitDestVerified( drm_device_t *dev,
630 OUT_RING(0); 627 OUT_RING(0);
631 } 628 }
632 629
633 OUT_RING( CMD_OP_DESTBUFFER_INFO ); 630 OUT_RING(CMD_OP_DESTBUFFER_INFO);
634 OUT_RING( BUF_3D_ID_COLOR_BACK | 631 OUT_RING(BUF_3D_ID_COLOR_BACK |
635 BUF_3D_PITCH(dev_priv->back_pitch * dev_priv->cpp) | 632 BUF_3D_PITCH(dev_priv->back_pitch * dev_priv->cpp) |
636 BUF_3D_USE_FENCE); 633 BUF_3D_USE_FENCE);
637 OUT_RING( tmp ); 634 OUT_RING(tmp);
638 OUT_RING( 0 ); 635 OUT_RING(0);
639 636
640 OUT_RING( CMD_OP_DESTBUFFER_INFO ); 637 OUT_RING(CMD_OP_DESTBUFFER_INFO);
641 OUT_RING( BUF_3D_ID_DEPTH | BUF_3D_USE_FENCE | 638 OUT_RING(BUF_3D_ID_DEPTH | BUF_3D_USE_FENCE |
642 BUF_3D_PITCH(dev_priv->depth_pitch * dev_priv->cpp)); 639 BUF_3D_PITCH(dev_priv->depth_pitch * dev_priv->cpp));
643 OUT_RING( dev_priv->zi1 ); 640 OUT_RING(dev_priv->zi1);
644 OUT_RING( 0 ); 641 OUT_RING(0);
645 } else { 642 } else {
646 DRM_ERROR("bad di1 %x (allow %x or %x)\n", 643 DRM_ERROR("bad di1 %x (allow %x or %x)\n",
647 tmp, dev_priv->front_di1, dev_priv->back_di1); 644 tmp, dev_priv->front_di1, dev_priv->back_di1);
@@ -650,83 +647,80 @@ static void i830EmitDestVerified( drm_device_t *dev,
650 /* invarient: 647 /* invarient:
651 */ 648 */
652 649
650 OUT_RING(GFX_OP_DESTBUFFER_VARS);
651 OUT_RING(code[I830_DESTREG_DV1]);
653 652
654 OUT_RING( GFX_OP_DESTBUFFER_VARS ); 653 OUT_RING(GFX_OP_DRAWRECT_INFO);
655 OUT_RING( code[I830_DESTREG_DV1] ); 654 OUT_RING(code[I830_DESTREG_DR1]);
656 655 OUT_RING(code[I830_DESTREG_DR2]);
657 OUT_RING( GFX_OP_DRAWRECT_INFO ); 656 OUT_RING(code[I830_DESTREG_DR3]);
658 OUT_RING( code[I830_DESTREG_DR1] ); 657 OUT_RING(code[I830_DESTREG_DR4]);
659 OUT_RING( code[I830_DESTREG_DR2] );
660 OUT_RING( code[I830_DESTREG_DR3] );
661 OUT_RING( code[I830_DESTREG_DR4] );
662 658
663 /* Need to verify this */ 659 /* Need to verify this */
664 tmp = code[I830_DESTREG_SENABLE]; 660 tmp = code[I830_DESTREG_SENABLE];
665 if((tmp & ~0x3) == GFX_OP_SCISSOR_ENABLE) { 661 if ((tmp & ~0x3) == GFX_OP_SCISSOR_ENABLE) {
666 OUT_RING( tmp ); 662 OUT_RING(tmp);
667 } else { 663 } else {
668 DRM_ERROR("bad scissor enable\n"); 664 DRM_ERROR("bad scissor enable\n");
669 OUT_RING( 0 ); 665 OUT_RING(0);
670 } 666 }
671 667
672 OUT_RING( GFX_OP_SCISSOR_RECT ); 668 OUT_RING(GFX_OP_SCISSOR_RECT);
673 OUT_RING( code[I830_DESTREG_SR1] ); 669 OUT_RING(code[I830_DESTREG_SR1]);
674 OUT_RING( code[I830_DESTREG_SR2] ); 670 OUT_RING(code[I830_DESTREG_SR2]);
675 OUT_RING( 0 ); 671 OUT_RING(0);
676 672
677 ADVANCE_LP_RING(); 673 ADVANCE_LP_RING();
678} 674}
679 675
680static void i830EmitStippleVerified( drm_device_t *dev, 676static void i830EmitStippleVerified(drm_device_t * dev, unsigned int *code)
681 unsigned int *code )
682{ 677{
683 drm_i830_private_t *dev_priv = dev->dev_private; 678 drm_i830_private_t *dev_priv = dev->dev_private;
684 RING_LOCALS; 679 RING_LOCALS;
685 680
686 BEGIN_LP_RING( 2 ); 681 BEGIN_LP_RING(2);
687 OUT_RING( GFX_OP_STIPPLE ); 682 OUT_RING(GFX_OP_STIPPLE);
688 OUT_RING( code[1] ); 683 OUT_RING(code[1]);
689 ADVANCE_LP_RING(); 684 ADVANCE_LP_RING();
690} 685}
691 686
692 687static void i830EmitState(drm_device_t * dev)
693static void i830EmitState( drm_device_t *dev )
694{ 688{
695 drm_i830_private_t *dev_priv = dev->dev_private; 689 drm_i830_private_t *dev_priv = dev->dev_private;
696 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; 690 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
697 unsigned int dirty = sarea_priv->dirty; 691 unsigned int dirty = sarea_priv->dirty;
698 692
699 DRM_DEBUG("%s %x\n", __FUNCTION__, dirty); 693 DRM_DEBUG("%s %x\n", __FUNCTION__, dirty);
700 694
701 if (dirty & I830_UPLOAD_BUFFERS) { 695 if (dirty & I830_UPLOAD_BUFFERS) {
702 i830EmitDestVerified( dev, sarea_priv->BufferState ); 696 i830EmitDestVerified(dev, sarea_priv->BufferState);
703 sarea_priv->dirty &= ~I830_UPLOAD_BUFFERS; 697 sarea_priv->dirty &= ~I830_UPLOAD_BUFFERS;
704 } 698 }
705 699
706 if (dirty & I830_UPLOAD_CTX) { 700 if (dirty & I830_UPLOAD_CTX) {
707 i830EmitContextVerified( dev, sarea_priv->ContextState ); 701 i830EmitContextVerified(dev, sarea_priv->ContextState);
708 sarea_priv->dirty &= ~I830_UPLOAD_CTX; 702 sarea_priv->dirty &= ~I830_UPLOAD_CTX;
709 } 703 }
710 704
711 if (dirty & I830_UPLOAD_TEX0) { 705 if (dirty & I830_UPLOAD_TEX0) {
712 i830EmitTexVerified( dev, sarea_priv->TexState[0] ); 706 i830EmitTexVerified(dev, sarea_priv->TexState[0]);
713 sarea_priv->dirty &= ~I830_UPLOAD_TEX0; 707 sarea_priv->dirty &= ~I830_UPLOAD_TEX0;
714 } 708 }
715 709
716 if (dirty & I830_UPLOAD_TEX1) { 710 if (dirty & I830_UPLOAD_TEX1) {
717 i830EmitTexVerified( dev, sarea_priv->TexState[1] ); 711 i830EmitTexVerified(dev, sarea_priv->TexState[1]);
718 sarea_priv->dirty &= ~I830_UPLOAD_TEX1; 712 sarea_priv->dirty &= ~I830_UPLOAD_TEX1;
719 } 713 }
720 714
721 if (dirty & I830_UPLOAD_TEXBLEND0) { 715 if (dirty & I830_UPLOAD_TEXBLEND0) {
722 i830EmitTexBlendVerified( dev, sarea_priv->TexBlendState[0], 716 i830EmitTexBlendVerified(dev, sarea_priv->TexBlendState[0],
723 sarea_priv->TexBlendStateWordsUsed[0]); 717 sarea_priv->TexBlendStateWordsUsed[0]);
724 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND0; 718 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND0;
725 } 719 }
726 720
727 if (dirty & I830_UPLOAD_TEXBLEND1) { 721 if (dirty & I830_UPLOAD_TEXBLEND1) {
728 i830EmitTexBlendVerified( dev, sarea_priv->TexBlendState[1], 722 i830EmitTexBlendVerified(dev, sarea_priv->TexBlendState[1],
729 sarea_priv->TexBlendStateWordsUsed[1]); 723 sarea_priv->TexBlendStateWordsUsed[1]);
730 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND1; 724 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND1;
731 } 725 }
732 726
@@ -759,36 +753,32 @@ static void i830EmitState( drm_device_t *dev )
759 /* 1.3: 753 /* 1.3:
760 */ 754 */
761 if (dirty & I830_UPLOAD_STIPPLE) { 755 if (dirty & I830_UPLOAD_STIPPLE) {
762 i830EmitStippleVerified( dev, 756 i830EmitStippleVerified(dev, sarea_priv->StippleState);
763 sarea_priv->StippleState);
764 sarea_priv->dirty &= ~I830_UPLOAD_STIPPLE; 757 sarea_priv->dirty &= ~I830_UPLOAD_STIPPLE;
765 } 758 }
766 759
767 if (dirty & I830_UPLOAD_TEX2) { 760 if (dirty & I830_UPLOAD_TEX2) {
768 i830EmitTexVerified( dev, sarea_priv->TexState2 ); 761 i830EmitTexVerified(dev, sarea_priv->TexState2);
769 sarea_priv->dirty &= ~I830_UPLOAD_TEX2; 762 sarea_priv->dirty &= ~I830_UPLOAD_TEX2;
770 } 763 }
771 764
772 if (dirty & I830_UPLOAD_TEX3) { 765 if (dirty & I830_UPLOAD_TEX3) {
773 i830EmitTexVerified( dev, sarea_priv->TexState3 ); 766 i830EmitTexVerified(dev, sarea_priv->TexState3);
774 sarea_priv->dirty &= ~I830_UPLOAD_TEX3; 767 sarea_priv->dirty &= ~I830_UPLOAD_TEX3;
775 } 768 }
776 769
777
778 if (dirty & I830_UPLOAD_TEXBLEND2) { 770 if (dirty & I830_UPLOAD_TEXBLEND2) {
779 i830EmitTexBlendVerified( 771 i830EmitTexBlendVerified(dev,
780 dev, 772 sarea_priv->TexBlendState2,
781 sarea_priv->TexBlendState2, 773 sarea_priv->TexBlendStateWordsUsed2);
782 sarea_priv->TexBlendStateWordsUsed2);
783 774
784 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND2; 775 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND2;
785 } 776 }
786 777
787 if (dirty & I830_UPLOAD_TEXBLEND3) { 778 if (dirty & I830_UPLOAD_TEXBLEND3) {
788 i830EmitTexBlendVerified( 779 i830EmitTexBlendVerified(dev,
789 dev, 780 sarea_priv->TexBlendState3,
790 sarea_priv->TexBlendState3, 781 sarea_priv->TexBlendStateWordsUsed3);
791 sarea_priv->TexBlendStateWordsUsed3);
792 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND3; 782 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND3;
793 } 783 }
794} 784}
@@ -797,97 +787,96 @@ static void i830EmitState( drm_device_t *dev )
797 * Performance monitoring functions 787 * Performance monitoring functions
798 */ 788 */
799 789
800static void i830_fill_box( drm_device_t *dev, 790static void i830_fill_box(drm_device_t * dev,
801 int x, int y, int w, int h, 791 int x, int y, int w, int h, int r, int g, int b)
802 int r, int g, int b )
803{ 792{
804 drm_i830_private_t *dev_priv = dev->dev_private; 793 drm_i830_private_t *dev_priv = dev->dev_private;
805 u32 color; 794 u32 color;
806 unsigned int BR13, CMD; 795 unsigned int BR13, CMD;
807 RING_LOCALS; 796 RING_LOCALS;
808 797
809 BR13 = (0xF0 << 16) | (dev_priv->pitch * dev_priv->cpp) | (1<<24); 798 BR13 = (0xF0 << 16) | (dev_priv->pitch * dev_priv->cpp) | (1 << 24);
810 CMD = XY_COLOR_BLT_CMD; 799 CMD = XY_COLOR_BLT_CMD;
811 x += dev_priv->sarea_priv->boxes[0].x1; 800 x += dev_priv->sarea_priv->boxes[0].x1;
812 y += dev_priv->sarea_priv->boxes[0].y1; 801 y += dev_priv->sarea_priv->boxes[0].y1;
813 802
814 if (dev_priv->cpp == 4) { 803 if (dev_priv->cpp == 4) {
815 BR13 |= (1<<25); 804 BR13 |= (1 << 25);
816 CMD |= (XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB); 805 CMD |= (XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB);
817 color = (((0xff) << 24) | (r << 16) | (g << 8) | b); 806 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
818 } else { 807 } else {
819 color = (((r & 0xf8) << 8) | 808 color = (((r & 0xf8) << 8) |
820 ((g & 0xfc) << 3) | 809 ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
821 ((b & 0xf8) >> 3));
822 } 810 }
823 811
824 BEGIN_LP_RING( 6 ); 812 BEGIN_LP_RING(6);
825 OUT_RING( CMD ); 813 OUT_RING(CMD);
826 OUT_RING( BR13 ); 814 OUT_RING(BR13);
827 OUT_RING( (y << 16) | x ); 815 OUT_RING((y << 16) | x);
828 OUT_RING( ((y+h) << 16) | (x+w) ); 816 OUT_RING(((y + h) << 16) | (x + w));
829 817
830 if ( dev_priv->current_page == 1 ) { 818 if (dev_priv->current_page == 1) {
831 OUT_RING( dev_priv->front_offset ); 819 OUT_RING(dev_priv->front_offset);
832 } else { 820 } else {
833 OUT_RING( dev_priv->back_offset ); 821 OUT_RING(dev_priv->back_offset);
834 } 822 }
835 823
836 OUT_RING( color ); 824 OUT_RING(color);
837 ADVANCE_LP_RING(); 825 ADVANCE_LP_RING();
838} 826}
839 827
840static void i830_cp_performance_boxes( drm_device_t *dev ) 828static void i830_cp_performance_boxes(drm_device_t * dev)
841{ 829{
842 drm_i830_private_t *dev_priv = dev->dev_private; 830 drm_i830_private_t *dev_priv = dev->dev_private;
843 831
844 /* Purple box for page flipping 832 /* Purple box for page flipping
845 */ 833 */
846 if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_FLIP ) 834 if (dev_priv->sarea_priv->perf_boxes & I830_BOX_FLIP)
847 i830_fill_box( dev, 4, 4, 8, 8, 255, 0, 255 ); 835 i830_fill_box(dev, 4, 4, 8, 8, 255, 0, 255);
848 836
849 /* Red box if we have to wait for idle at any point 837 /* Red box if we have to wait for idle at any point
850 */ 838 */
851 if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_WAIT ) 839 if (dev_priv->sarea_priv->perf_boxes & I830_BOX_WAIT)
852 i830_fill_box( dev, 16, 4, 8, 8, 255, 0, 0 ); 840 i830_fill_box(dev, 16, 4, 8, 8, 255, 0, 0);
853 841
854 /* Blue box: lost context? 842 /* Blue box: lost context?
855 */ 843 */
856 if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_LOST_CONTEXT ) 844 if (dev_priv->sarea_priv->perf_boxes & I830_BOX_LOST_CONTEXT)
857 i830_fill_box( dev, 28, 4, 8, 8, 0, 0, 255 ); 845 i830_fill_box(dev, 28, 4, 8, 8, 0, 0, 255);
858 846
859 /* Yellow box for texture swaps 847 /* Yellow box for texture swaps
860 */ 848 */
861 if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_TEXTURE_LOAD ) 849 if (dev_priv->sarea_priv->perf_boxes & I830_BOX_TEXTURE_LOAD)
862 i830_fill_box( dev, 40, 4, 8, 8, 255, 255, 0 ); 850 i830_fill_box(dev, 40, 4, 8, 8, 255, 255, 0);
863 851
864 /* Green box if hardware never idles (as far as we can tell) 852 /* Green box if hardware never idles (as far as we can tell)
865 */ 853 */
866 if ( !(dev_priv->sarea_priv->perf_boxes & I830_BOX_RING_EMPTY) ) 854 if (!(dev_priv->sarea_priv->perf_boxes & I830_BOX_RING_EMPTY))
867 i830_fill_box( dev, 64, 4, 8, 8, 0, 255, 0 ); 855 i830_fill_box(dev, 64, 4, 8, 8, 0, 255, 0);
868
869 856
870 /* Draw bars indicating number of buffers allocated 857 /* Draw bars indicating number of buffers allocated
871 * (not a great measure, easily confused) 858 * (not a great measure, easily confused)
872 */ 859 */
873 if (dev_priv->dma_used) { 860 if (dev_priv->dma_used) {
874 int bar = dev_priv->dma_used / 10240; 861 int bar = dev_priv->dma_used / 10240;
875 if (bar > 100) bar = 100; 862 if (bar > 100)
876 if (bar < 1) bar = 1; 863 bar = 100;
877 i830_fill_box( dev, 4, 16, bar, 4, 196, 128, 128 ); 864 if (bar < 1)
865 bar = 1;
866 i830_fill_box(dev, 4, 16, bar, 4, 196, 128, 128);
878 dev_priv->dma_used = 0; 867 dev_priv->dma_used = 0;
879 } 868 }
880 869
881 dev_priv->sarea_priv->perf_boxes = 0; 870 dev_priv->sarea_priv->perf_boxes = 0;
882} 871}
883 872
884static void i830_dma_dispatch_clear( drm_device_t *dev, int flags, 873static void i830_dma_dispatch_clear(drm_device_t * dev, int flags,
885 unsigned int clear_color, 874 unsigned int clear_color,
886 unsigned int clear_zval, 875 unsigned int clear_zval,
887 unsigned int clear_depthmask) 876 unsigned int clear_depthmask)
888{ 877{
889 drm_i830_private_t *dev_priv = dev->dev_private; 878 drm_i830_private_t *dev_priv = dev->dev_private;
890 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; 879 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
891 int nbox = sarea_priv->nbox; 880 int nbox = sarea_priv->nbox;
892 drm_clip_rect_t *pbox = sarea_priv->boxes; 881 drm_clip_rect_t *pbox = sarea_priv->boxes;
893 int pitch = dev_priv->pitch; 882 int pitch = dev_priv->pitch;
@@ -896,90 +885,90 @@ static void i830_dma_dispatch_clear( drm_device_t *dev, int flags,
896 unsigned int BR13, CMD, D_CMD; 885 unsigned int BR13, CMD, D_CMD;
897 RING_LOCALS; 886 RING_LOCALS;
898 887
899 888 if (dev_priv->current_page == 1) {
900 if ( dev_priv->current_page == 1 ) {
901 unsigned int tmp = flags; 889 unsigned int tmp = flags;
902 890
903 flags &= ~(I830_FRONT | I830_BACK); 891 flags &= ~(I830_FRONT | I830_BACK);
904 if ( tmp & I830_FRONT ) flags |= I830_BACK; 892 if (tmp & I830_FRONT)
905 if ( tmp & I830_BACK ) flags |= I830_FRONT; 893 flags |= I830_BACK;
894 if (tmp & I830_BACK)
895 flags |= I830_FRONT;
906 } 896 }
907 897
908 i830_kernel_lost_context(dev); 898 i830_kernel_lost_context(dev);
909 899
910 switch(cpp) { 900 switch (cpp) {
911 case 2: 901 case 2:
912 BR13 = (0xF0 << 16) | (pitch * cpp) | (1<<24); 902 BR13 = (0xF0 << 16) | (pitch * cpp) | (1 << 24);
913 D_CMD = CMD = XY_COLOR_BLT_CMD; 903 D_CMD = CMD = XY_COLOR_BLT_CMD;
914 break; 904 break;
915 case 4: 905 case 4:
916 BR13 = (0xF0 << 16) | (pitch * cpp) | (1<<24) | (1<<25); 906 BR13 = (0xF0 << 16) | (pitch * cpp) | (1 << 24) | (1 << 25);
917 CMD = (XY_COLOR_BLT_CMD | XY_COLOR_BLT_WRITE_ALPHA | 907 CMD = (XY_COLOR_BLT_CMD | XY_COLOR_BLT_WRITE_ALPHA |
918 XY_COLOR_BLT_WRITE_RGB); 908 XY_COLOR_BLT_WRITE_RGB);
919 D_CMD = XY_COLOR_BLT_CMD; 909 D_CMD = XY_COLOR_BLT_CMD;
920 if(clear_depthmask & 0x00ffffff) 910 if (clear_depthmask & 0x00ffffff)
921 D_CMD |= XY_COLOR_BLT_WRITE_RGB; 911 D_CMD |= XY_COLOR_BLT_WRITE_RGB;
922 if(clear_depthmask & 0xff000000) 912 if (clear_depthmask & 0xff000000)
923 D_CMD |= XY_COLOR_BLT_WRITE_ALPHA; 913 D_CMD |= XY_COLOR_BLT_WRITE_ALPHA;
924 break; 914 break;
925 default: 915 default:
926 BR13 = (0xF0 << 16) | (pitch * cpp) | (1<<24); 916 BR13 = (0xF0 << 16) | (pitch * cpp) | (1 << 24);
927 D_CMD = CMD = XY_COLOR_BLT_CMD; 917 D_CMD = CMD = XY_COLOR_BLT_CMD;
928 break; 918 break;
929 } 919 }
930 920
931 if (nbox > I830_NR_SAREA_CLIPRECTS) 921 if (nbox > I830_NR_SAREA_CLIPRECTS)
932 nbox = I830_NR_SAREA_CLIPRECTS; 922 nbox = I830_NR_SAREA_CLIPRECTS;
933 923
934 for (i = 0 ; i < nbox ; i++, pbox++) { 924 for (i = 0; i < nbox; i++, pbox++) {
935 if (pbox->x1 > pbox->x2 || 925 if (pbox->x1 > pbox->x2 ||
936 pbox->y1 > pbox->y2 || 926 pbox->y1 > pbox->y2 ||
937 pbox->x2 > dev_priv->w || 927 pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
938 pbox->y2 > dev_priv->h)
939 continue; 928 continue;
940 929
941 if ( flags & I830_FRONT ) { 930 if (flags & I830_FRONT) {
942 DRM_DEBUG("clear front\n"); 931 DRM_DEBUG("clear front\n");
943 BEGIN_LP_RING( 6 ); 932 BEGIN_LP_RING(6);
944 OUT_RING( CMD ); 933 OUT_RING(CMD);
945 OUT_RING( BR13 ); 934 OUT_RING(BR13);
946 OUT_RING( (pbox->y1 << 16) | pbox->x1 ); 935 OUT_RING((pbox->y1 << 16) | pbox->x1);
947 OUT_RING( (pbox->y2 << 16) | pbox->x2 ); 936 OUT_RING((pbox->y2 << 16) | pbox->x2);
948 OUT_RING( dev_priv->front_offset ); 937 OUT_RING(dev_priv->front_offset);
949 OUT_RING( clear_color ); 938 OUT_RING(clear_color);
950 ADVANCE_LP_RING(); 939 ADVANCE_LP_RING();
951 } 940 }
952 941
953 if ( flags & I830_BACK ) { 942 if (flags & I830_BACK) {
954 DRM_DEBUG("clear back\n"); 943 DRM_DEBUG("clear back\n");
955 BEGIN_LP_RING( 6 ); 944 BEGIN_LP_RING(6);
956 OUT_RING( CMD ); 945 OUT_RING(CMD);
957 OUT_RING( BR13 ); 946 OUT_RING(BR13);
958 OUT_RING( (pbox->y1 << 16) | pbox->x1 ); 947 OUT_RING((pbox->y1 << 16) | pbox->x1);
959 OUT_RING( (pbox->y2 << 16) | pbox->x2 ); 948 OUT_RING((pbox->y2 << 16) | pbox->x2);
960 OUT_RING( dev_priv->back_offset ); 949 OUT_RING(dev_priv->back_offset);
961 OUT_RING( clear_color ); 950 OUT_RING(clear_color);
962 ADVANCE_LP_RING(); 951 ADVANCE_LP_RING();
963 } 952 }
964 953
965 if ( flags & I830_DEPTH ) { 954 if (flags & I830_DEPTH) {
966 DRM_DEBUG("clear depth\n"); 955 DRM_DEBUG("clear depth\n");
967 BEGIN_LP_RING( 6 ); 956 BEGIN_LP_RING(6);
968 OUT_RING( D_CMD ); 957 OUT_RING(D_CMD);
969 OUT_RING( BR13 ); 958 OUT_RING(BR13);
970 OUT_RING( (pbox->y1 << 16) | pbox->x1 ); 959 OUT_RING((pbox->y1 << 16) | pbox->x1);
971 OUT_RING( (pbox->y2 << 16) | pbox->x2 ); 960 OUT_RING((pbox->y2 << 16) | pbox->x2);
972 OUT_RING( dev_priv->depth_offset ); 961 OUT_RING(dev_priv->depth_offset);
973 OUT_RING( clear_zval ); 962 OUT_RING(clear_zval);
974 ADVANCE_LP_RING(); 963 ADVANCE_LP_RING();
975 } 964 }
976 } 965 }
977} 966}
978 967
979static void i830_dma_dispatch_swap( drm_device_t *dev ) 968static void i830_dma_dispatch_swap(drm_device_t * dev)
980{ 969{
981 drm_i830_private_t *dev_priv = dev->dev_private; 970 drm_i830_private_t *dev_priv = dev->dev_private;
982 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; 971 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
983 int nbox = sarea_priv->nbox; 972 int nbox = sarea_priv->nbox;
984 drm_clip_rect_t *pbox = sarea_priv->boxes; 973 drm_clip_rect_t *pbox = sarea_priv->boxes;
985 int pitch = dev_priv->pitch; 974 int pitch = dev_priv->pitch;
@@ -990,202 +979,192 @@ static void i830_dma_dispatch_swap( drm_device_t *dev )
990 979
991 DRM_DEBUG("swapbuffers\n"); 980 DRM_DEBUG("swapbuffers\n");
992 981
993 i830_kernel_lost_context(dev); 982 i830_kernel_lost_context(dev);
994 983
995 if (dev_priv->do_boxes) 984 if (dev_priv->do_boxes)
996 i830_cp_performance_boxes( dev ); 985 i830_cp_performance_boxes(dev);
997 986
998 switch(cpp) { 987 switch (cpp) {
999 case 2: 988 case 2:
1000 BR13 = (pitch * cpp) | (0xCC << 16) | (1<<24); 989 BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24);
1001 CMD = XY_SRC_COPY_BLT_CMD; 990 CMD = XY_SRC_COPY_BLT_CMD;
1002 break; 991 break;
1003 case 4: 992 case 4:
1004 BR13 = (pitch * cpp) | (0xCC << 16) | (1<<24) | (1<<25); 993 BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24) | (1 << 25);
1005 CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA | 994 CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
1006 XY_SRC_COPY_BLT_WRITE_RGB); 995 XY_SRC_COPY_BLT_WRITE_RGB);
1007 break; 996 break;
1008 default: 997 default:
1009 BR13 = (pitch * cpp) | (0xCC << 16) | (1<<24); 998 BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24);
1010 CMD = XY_SRC_COPY_BLT_CMD; 999 CMD = XY_SRC_COPY_BLT_CMD;
1011 break; 1000 break;
1012 } 1001 }
1013 1002
1003 if (nbox > I830_NR_SAREA_CLIPRECTS)
1004 nbox = I830_NR_SAREA_CLIPRECTS;
1014 1005
1015 if (nbox > I830_NR_SAREA_CLIPRECTS) 1006 for (i = 0; i < nbox; i++, pbox++) {
1016 nbox = I830_NR_SAREA_CLIPRECTS;
1017
1018 for (i = 0 ; i < nbox; i++, pbox++)
1019 {
1020 if (pbox->x1 > pbox->x2 || 1007 if (pbox->x1 > pbox->x2 ||
1021 pbox->y1 > pbox->y2 || 1008 pbox->y1 > pbox->y2 ||
1022 pbox->x2 > dev_priv->w || 1009 pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
1023 pbox->y2 > dev_priv->h)
1024 continue; 1010 continue;
1025 1011
1026 DRM_DEBUG("dispatch swap %d,%d-%d,%d!\n", 1012 DRM_DEBUG("dispatch swap %d,%d-%d,%d!\n",
1027 pbox->x1, pbox->y1, 1013 pbox->x1, pbox->y1, pbox->x2, pbox->y2);
1028 pbox->x2, pbox->y2);
1029 1014
1030 BEGIN_LP_RING( 8 ); 1015 BEGIN_LP_RING(8);
1031 OUT_RING( CMD ); 1016 OUT_RING(CMD);
1032 OUT_RING( BR13 ); 1017 OUT_RING(BR13);
1033 OUT_RING( (pbox->y1 << 16) | pbox->x1 ); 1018 OUT_RING((pbox->y1 << 16) | pbox->x1);
1034 OUT_RING( (pbox->y2 << 16) | pbox->x2 ); 1019 OUT_RING((pbox->y2 << 16) | pbox->x2);
1035 1020
1036 if (dev_priv->current_page == 0) 1021 if (dev_priv->current_page == 0)
1037 OUT_RING( dev_priv->front_offset ); 1022 OUT_RING(dev_priv->front_offset);
1038 else 1023 else
1039 OUT_RING( dev_priv->back_offset ); 1024 OUT_RING(dev_priv->back_offset);
1040 1025
1041 OUT_RING( (pbox->y1 << 16) | pbox->x1 ); 1026 OUT_RING((pbox->y1 << 16) | pbox->x1);
1042 OUT_RING( BR13 & 0xffff ); 1027 OUT_RING(BR13 & 0xffff);
1043 1028
1044 if (dev_priv->current_page == 0) 1029 if (dev_priv->current_page == 0)
1045 OUT_RING( dev_priv->back_offset ); 1030 OUT_RING(dev_priv->back_offset);
1046 else 1031 else
1047 OUT_RING( dev_priv->front_offset ); 1032 OUT_RING(dev_priv->front_offset);
1048 1033
1049 ADVANCE_LP_RING(); 1034 ADVANCE_LP_RING();
1050 } 1035 }
1051} 1036}
1052 1037
1053static void i830_dma_dispatch_flip( drm_device_t *dev ) 1038static void i830_dma_dispatch_flip(drm_device_t * dev)
1054{ 1039{
1055 drm_i830_private_t *dev_priv = dev->dev_private; 1040 drm_i830_private_t *dev_priv = dev->dev_private;
1056 RING_LOCALS; 1041 RING_LOCALS;
1057 1042
1058 DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n", 1043 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
1059 __FUNCTION__, 1044 __FUNCTION__,
1060 dev_priv->current_page, 1045 dev_priv->current_page,
1061 dev_priv->sarea_priv->pf_current_page); 1046 dev_priv->sarea_priv->pf_current_page);
1062 1047
1063 i830_kernel_lost_context(dev); 1048 i830_kernel_lost_context(dev);
1064 1049
1065 if (dev_priv->do_boxes) { 1050 if (dev_priv->do_boxes) {
1066 dev_priv->sarea_priv->perf_boxes |= I830_BOX_FLIP; 1051 dev_priv->sarea_priv->perf_boxes |= I830_BOX_FLIP;
1067 i830_cp_performance_boxes( dev ); 1052 i830_cp_performance_boxes(dev);
1068 } 1053 }
1069 1054
1070 1055 BEGIN_LP_RING(2);
1071 BEGIN_LP_RING( 2 ); 1056 OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
1072 OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE ); 1057 OUT_RING(0);
1073 OUT_RING( 0 );
1074 ADVANCE_LP_RING(); 1058 ADVANCE_LP_RING();
1075 1059
1076 BEGIN_LP_RING( 6 ); 1060 BEGIN_LP_RING(6);
1077 OUT_RING( CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP ); 1061 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
1078 OUT_RING( 0 ); 1062 OUT_RING(0);
1079 if ( dev_priv->current_page == 0 ) { 1063 if (dev_priv->current_page == 0) {
1080 OUT_RING( dev_priv->back_offset ); 1064 OUT_RING(dev_priv->back_offset);
1081 dev_priv->current_page = 1; 1065 dev_priv->current_page = 1;
1082 } else { 1066 } else {
1083 OUT_RING( dev_priv->front_offset ); 1067 OUT_RING(dev_priv->front_offset);
1084 dev_priv->current_page = 0; 1068 dev_priv->current_page = 0;
1085 } 1069 }
1086 OUT_RING(0); 1070 OUT_RING(0);
1087 ADVANCE_LP_RING(); 1071 ADVANCE_LP_RING();
1088 1072
1089 1073 BEGIN_LP_RING(2);
1090 BEGIN_LP_RING( 2 ); 1074 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
1091 OUT_RING( MI_WAIT_FOR_EVENT | 1075 OUT_RING(0);
1092 MI_WAIT_FOR_PLANE_A_FLIP );
1093 OUT_RING( 0 );
1094 ADVANCE_LP_RING(); 1076 ADVANCE_LP_RING();
1095
1096 1077
1097 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; 1078 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
1098} 1079}
1099 1080
1100static void i830_dma_dispatch_vertex(drm_device_t *dev, 1081static void i830_dma_dispatch_vertex(drm_device_t * dev,
1101 drm_buf_t *buf, 1082 drm_buf_t * buf, int discard, int used)
1102 int discard,
1103 int used)
1104{ 1083{
1105 drm_i830_private_t *dev_priv = dev->dev_private; 1084 drm_i830_private_t *dev_priv = dev->dev_private;
1106 drm_i830_buf_priv_t *buf_priv = buf->dev_private; 1085 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
1107 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; 1086 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
1108 drm_clip_rect_t *box = sarea_priv->boxes; 1087 drm_clip_rect_t *box = sarea_priv->boxes;
1109 int nbox = sarea_priv->nbox; 1088 int nbox = sarea_priv->nbox;
1110 unsigned long address = (unsigned long)buf->bus_address; 1089 unsigned long address = (unsigned long)buf->bus_address;
1111 unsigned long start = address - dev->agp->base; 1090 unsigned long start = address - dev->agp->base;
1112 int i = 0, u; 1091 int i = 0, u;
1113 RING_LOCALS; 1092 RING_LOCALS;
1114 1093
1115 i830_kernel_lost_context(dev); 1094 i830_kernel_lost_context(dev);
1116 1095
1117 if (nbox > I830_NR_SAREA_CLIPRECTS) 1096 if (nbox > I830_NR_SAREA_CLIPRECTS)
1118 nbox = I830_NR_SAREA_CLIPRECTS; 1097 nbox = I830_NR_SAREA_CLIPRECTS;
1119 1098
1120 if (discard) { 1099 if (discard) {
1121 u = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, 1100 u = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT,
1122 I830_BUF_HARDWARE); 1101 I830_BUF_HARDWARE);
1123 if(u != I830_BUF_CLIENT) { 1102 if (u != I830_BUF_CLIENT) {
1124 DRM_DEBUG("xxxx 2\n"); 1103 DRM_DEBUG("xxxx 2\n");
1125 } 1104 }
1126 } 1105 }
1127 1106
1128 if (used > 4*1023) 1107 if (used > 4 * 1023)
1129 used = 0; 1108 used = 0;
1130 1109
1131 if (sarea_priv->dirty) 1110 if (sarea_priv->dirty)
1132 i830EmitState( dev ); 1111 i830EmitState(dev);
1133 1112
1134 DRM_DEBUG("dispatch vertex addr 0x%lx, used 0x%x nbox %d\n", 1113 DRM_DEBUG("dispatch vertex addr 0x%lx, used 0x%x nbox %d\n",
1135 address, used, nbox); 1114 address, used, nbox);
1136 1115
1137 dev_priv->counter++; 1116 dev_priv->counter++;
1138 DRM_DEBUG( "dispatch counter : %ld\n", dev_priv->counter); 1117 DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
1139 DRM_DEBUG( "i830_dma_dispatch\n"); 1118 DRM_DEBUG("i830_dma_dispatch\n");
1140 DRM_DEBUG( "start : %lx\n", start); 1119 DRM_DEBUG("start : %lx\n", start);
1141 DRM_DEBUG( "used : %d\n", used); 1120 DRM_DEBUG("used : %d\n", used);
1142 DRM_DEBUG( "start + used - 4 : %ld\n", start + used - 4); 1121 DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4);
1143 1122
1144 if (buf_priv->currently_mapped == I830_BUF_MAPPED) { 1123 if (buf_priv->currently_mapped == I830_BUF_MAPPED) {
1145 u32 *vp = buf_priv->kernel_virtual; 1124 u32 *vp = buf_priv->kernel_virtual;
1146 1125
1147 vp[0] = (GFX_OP_PRIMITIVE | 1126 vp[0] = (GFX_OP_PRIMITIVE |
1148 sarea_priv->vertex_prim | 1127 sarea_priv->vertex_prim | ((used / 4) - 2));
1149 ((used/4)-2));
1150 1128
1151 if (dev_priv->use_mi_batchbuffer_start) { 1129 if (dev_priv->use_mi_batchbuffer_start) {
1152 vp[used/4] = MI_BATCH_BUFFER_END; 1130 vp[used / 4] = MI_BATCH_BUFFER_END;
1153 used += 4; 1131 used += 4;
1154 } 1132 }
1155 1133
1156 if (used & 4) { 1134 if (used & 4) {
1157 vp[used/4] = 0; 1135 vp[used / 4] = 0;
1158 used += 4; 1136 used += 4;
1159 } 1137 }
1160 1138
1161 i830_unmap_buffer(buf); 1139 i830_unmap_buffer(buf);
1162 } 1140 }
1163 1141
1164 if (used) { 1142 if (used) {
1165 do { 1143 do {
1166 if (i < nbox) { 1144 if (i < nbox) {
1167 BEGIN_LP_RING(6); 1145 BEGIN_LP_RING(6);
1168 OUT_RING( GFX_OP_DRAWRECT_INFO ); 1146 OUT_RING(GFX_OP_DRAWRECT_INFO);
1169 OUT_RING( sarea_priv->BufferState[I830_DESTREG_DR1] ); 1147 OUT_RING(sarea_priv->
1170 OUT_RING( box[i].x1 | (box[i].y1<<16) ); 1148 BufferState[I830_DESTREG_DR1]);
1171 OUT_RING( box[i].x2 | (box[i].y2<<16) ); 1149 OUT_RING(box[i].x1 | (box[i].y1 << 16));
1172 OUT_RING( sarea_priv->BufferState[I830_DESTREG_DR4] ); 1150 OUT_RING(box[i].x2 | (box[i].y2 << 16));
1173 OUT_RING( 0 ); 1151 OUT_RING(sarea_priv->
1152 BufferState[I830_DESTREG_DR4]);
1153 OUT_RING(0);
1174 ADVANCE_LP_RING(); 1154 ADVANCE_LP_RING();
1175 } 1155 }
1176 1156
1177 if (dev_priv->use_mi_batchbuffer_start) { 1157 if (dev_priv->use_mi_batchbuffer_start) {
1178 BEGIN_LP_RING(2); 1158 BEGIN_LP_RING(2);
1179 OUT_RING( MI_BATCH_BUFFER_START | (2<<6) ); 1159 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
1180 OUT_RING( start | MI_BATCH_NON_SECURE ); 1160 OUT_RING(start | MI_BATCH_NON_SECURE);
1181 ADVANCE_LP_RING(); 1161 ADVANCE_LP_RING();
1182 } 1162 } else {
1183 else {
1184 BEGIN_LP_RING(4); 1163 BEGIN_LP_RING(4);
1185 OUT_RING( MI_BATCH_BUFFER ); 1164 OUT_RING(MI_BATCH_BUFFER);
1186 OUT_RING( start | MI_BATCH_NON_SECURE ); 1165 OUT_RING(start | MI_BATCH_NON_SECURE);
1187 OUT_RING( start + used - 4 ); 1166 OUT_RING(start + used - 4);
1188 OUT_RING( 0 ); 1167 OUT_RING(0);
1189 ADVANCE_LP_RING(); 1168 ADVANCE_LP_RING();
1190 } 1169 }
1191 1170
@@ -1195,61 +1174,60 @@ static void i830_dma_dispatch_vertex(drm_device_t *dev,
1195 if (discard) { 1174 if (discard) {
1196 dev_priv->counter++; 1175 dev_priv->counter++;
1197 1176
1198 (void) cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, 1177 (void)cmpxchg(buf_priv->in_use, I830_BUF_CLIENT,
1199 I830_BUF_HARDWARE); 1178 I830_BUF_HARDWARE);
1200 1179
1201 BEGIN_LP_RING(8); 1180 BEGIN_LP_RING(8);
1202 OUT_RING( CMD_STORE_DWORD_IDX ); 1181 OUT_RING(CMD_STORE_DWORD_IDX);
1203 OUT_RING( 20 ); 1182 OUT_RING(20);
1204 OUT_RING( dev_priv->counter ); 1183 OUT_RING(dev_priv->counter);
1205 OUT_RING( CMD_STORE_DWORD_IDX ); 1184 OUT_RING(CMD_STORE_DWORD_IDX);
1206 OUT_RING( buf_priv->my_use_idx ); 1185 OUT_RING(buf_priv->my_use_idx);
1207 OUT_RING( I830_BUF_FREE ); 1186 OUT_RING(I830_BUF_FREE);
1208 OUT_RING( CMD_REPORT_HEAD ); 1187 OUT_RING(CMD_REPORT_HEAD);
1209 OUT_RING( 0 ); 1188 OUT_RING(0);
1210 ADVANCE_LP_RING(); 1189 ADVANCE_LP_RING();
1211 } 1190 }
1212} 1191}
1213 1192
1214 1193static void i830_dma_quiescent(drm_device_t * dev)
1215static void i830_dma_quiescent(drm_device_t *dev)
1216{ 1194{
1217 drm_i830_private_t *dev_priv = dev->dev_private; 1195 drm_i830_private_t *dev_priv = dev->dev_private;
1218 RING_LOCALS; 1196 RING_LOCALS;
1219 1197
1220 i830_kernel_lost_context(dev); 1198 i830_kernel_lost_context(dev);
1221 1199
1222 BEGIN_LP_RING(4); 1200 BEGIN_LP_RING(4);
1223 OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE ); 1201 OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
1224 OUT_RING( CMD_REPORT_HEAD ); 1202 OUT_RING(CMD_REPORT_HEAD);
1225 OUT_RING( 0 ); 1203 OUT_RING(0);
1226 OUT_RING( 0 ); 1204 OUT_RING(0);
1227 ADVANCE_LP_RING(); 1205 ADVANCE_LP_RING();
1228 1206
1229 i830_wait_ring( dev, dev_priv->ring.Size - 8, __FUNCTION__ ); 1207 i830_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
1230} 1208}
1231 1209
1232static int i830_flush_queue(drm_device_t *dev) 1210static int i830_flush_queue(drm_device_t * dev)
1233{ 1211{
1234 drm_i830_private_t *dev_priv = dev->dev_private; 1212 drm_i830_private_t *dev_priv = dev->dev_private;
1235 drm_device_dma_t *dma = dev->dma; 1213 drm_device_dma_t *dma = dev->dma;
1236 int i, ret = 0; 1214 int i, ret = 0;
1237 RING_LOCALS; 1215 RING_LOCALS;
1238 1216
1239 i830_kernel_lost_context(dev); 1217 i830_kernel_lost_context(dev);
1240 1218
1241 BEGIN_LP_RING(2); 1219 BEGIN_LP_RING(2);
1242 OUT_RING( CMD_REPORT_HEAD ); 1220 OUT_RING(CMD_REPORT_HEAD);
1243 OUT_RING( 0 ); 1221 OUT_RING(0);
1244 ADVANCE_LP_RING(); 1222 ADVANCE_LP_RING();
1245 1223
1246 i830_wait_ring( dev, dev_priv->ring.Size - 8, __FUNCTION__ ); 1224 i830_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
1247 1225
1248 for (i = 0; i < dma->buf_count; i++) { 1226 for (i = 0; i < dma->buf_count; i++) {
1249 drm_buf_t *buf = dma->buflist[ i ]; 1227 drm_buf_t *buf = dma->buflist[i];
1250 drm_i830_buf_priv_t *buf_priv = buf->dev_private; 1228 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
1251 1229
1252 int used = cmpxchg(buf_priv->in_use, I830_BUF_HARDWARE, 1230 int used = cmpxchg(buf_priv->in_use, I830_BUF_HARDWARE,
1253 I830_BUF_FREE); 1231 I830_BUF_FREE);
1254 1232
1255 if (used == I830_BUF_HARDWARE) 1233 if (used == I830_BUF_HARDWARE)
@@ -1258,62 +1236,66 @@ static int i830_flush_queue(drm_device_t *dev)
1258 DRM_DEBUG("still on client\n"); 1236 DRM_DEBUG("still on client\n");
1259 } 1237 }
1260 1238
1261 return ret; 1239 return ret;
1262} 1240}
1263 1241
1264/* Must be called with the lock held */ 1242/* Must be called with the lock held */
1265void i830_reclaim_buffers(drm_device_t *dev, struct file *filp) 1243void i830_reclaim_buffers(drm_device_t * dev, struct file *filp)
1266{ 1244{
1267 drm_device_dma_t *dma = dev->dma; 1245 drm_device_dma_t *dma = dev->dma;
1268 int i; 1246 int i;
1269 1247
1270 if (!dma) return; 1248 if (!dma)
1271 if (!dev->dev_private) return; 1249 return;
1272 if (!dma->buflist) return; 1250 if (!dev->dev_private)
1251 return;
1252 if (!dma->buflist)
1253 return;
1273 1254
1274 i830_flush_queue(dev); 1255 i830_flush_queue(dev);
1275 1256
1276 for (i = 0; i < dma->buf_count; i++) { 1257 for (i = 0; i < dma->buf_count; i++) {
1277 drm_buf_t *buf = dma->buflist[ i ]; 1258 drm_buf_t *buf = dma->buflist[i];
1278 drm_i830_buf_priv_t *buf_priv = buf->dev_private; 1259 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
1279 1260
1280 if (buf->filp == filp && buf_priv) { 1261 if (buf->filp == filp && buf_priv) {
1281 int used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, 1262 int used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT,
1282 I830_BUF_FREE); 1263 I830_BUF_FREE);
1283 1264
1284 if (used == I830_BUF_CLIENT) 1265 if (used == I830_BUF_CLIENT)
1285 DRM_DEBUG("reclaimed from client\n"); 1266 DRM_DEBUG("reclaimed from client\n");
1286 if(buf_priv->currently_mapped == I830_BUF_MAPPED) 1267 if (buf_priv->currently_mapped == I830_BUF_MAPPED)
1287 buf_priv->currently_mapped = I830_BUF_UNMAPPED; 1268 buf_priv->currently_mapped = I830_BUF_UNMAPPED;
1288 } 1269 }
1289 } 1270 }
1290} 1271}
1291 1272
1292static int i830_flush_ioctl(struct inode *inode, struct file *filp, 1273static int i830_flush_ioctl(struct inode *inode, struct file *filp,
1293 unsigned int cmd, unsigned long arg) 1274 unsigned int cmd, unsigned long arg)
1294{ 1275{
1295 drm_file_t *priv = filp->private_data; 1276 drm_file_t *priv = filp->private_data;
1296 drm_device_t *dev = priv->head->dev; 1277 drm_device_t *dev = priv->head->dev;
1297 1278
1298 LOCK_TEST_WITH_RETURN(dev, filp); 1279 LOCK_TEST_WITH_RETURN(dev, filp);
1299 1280
1300 i830_flush_queue(dev); 1281 i830_flush_queue(dev);
1301 return 0; 1282 return 0;
1302} 1283}
1303 1284
1304static int i830_dma_vertex(struct inode *inode, struct file *filp, 1285static int i830_dma_vertex(struct inode *inode, struct file *filp,
1305 unsigned int cmd, unsigned long arg) 1286 unsigned int cmd, unsigned long arg)
1306{ 1287{
1307 drm_file_t *priv = filp->private_data; 1288 drm_file_t *priv = filp->private_data;
1308 drm_device_t *dev = priv->head->dev; 1289 drm_device_t *dev = priv->head->dev;
1309 drm_device_dma_t *dma = dev->dma; 1290 drm_device_dma_t *dma = dev->dma;
1310 drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private; 1291 drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
1311 u32 *hw_status = dev_priv->hw_status_page; 1292 u32 *hw_status = dev_priv->hw_status_page;
1312 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) 1293 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *)
1313 dev_priv->sarea_priv; 1294 dev_priv->sarea_priv;
1314 drm_i830_vertex_t vertex; 1295 drm_i830_vertex_t vertex;
1315 1296
1316 if (copy_from_user(&vertex, (drm_i830_vertex_t __user *)arg, sizeof(vertex))) 1297 if (copy_from_user
1298 (&vertex, (drm_i830_vertex_t __user *) arg, sizeof(vertex)))
1317 return -EFAULT; 1299 return -EFAULT;
1318 1300
1319 LOCK_TEST_WITH_RETURN(dev, filp); 1301 LOCK_TEST_WITH_RETURN(dev, filp);
@@ -1321,15 +1303,16 @@ static int i830_dma_vertex(struct inode *inode, struct file *filp,
1321 DRM_DEBUG("i830 dma vertex, idx %d used %d discard %d\n", 1303 DRM_DEBUG("i830 dma vertex, idx %d used %d discard %d\n",
1322 vertex.idx, vertex.used, vertex.discard); 1304 vertex.idx, vertex.used, vertex.discard);
1323 1305
1324 if(vertex.idx < 0 || vertex.idx > dma->buf_count) return -EINVAL; 1306 if (vertex.idx < 0 || vertex.idx > dma->buf_count)
1307 return -EINVAL;
1325 1308
1326 i830_dma_dispatch_vertex( dev, 1309 i830_dma_dispatch_vertex(dev,
1327 dma->buflist[ vertex.idx ], 1310 dma->buflist[vertex.idx],
1328 vertex.discard, vertex.used ); 1311 vertex.discard, vertex.used);
1312
1313 sarea_priv->last_enqueue = dev_priv->counter - 1;
1314 sarea_priv->last_dispatch = (int)hw_status[5];
1329 1315
1330 sarea_priv->last_enqueue = dev_priv->counter-1;
1331 sarea_priv->last_dispatch = (int) hw_status[5];
1332
1333 return 0; 1316 return 0;
1334} 1317}
1335 1318
@@ -1340,9 +1323,10 @@ static int i830_clear_bufs(struct inode *inode, struct file *filp,
1340 drm_device_t *dev = priv->head->dev; 1323 drm_device_t *dev = priv->head->dev;
1341 drm_i830_clear_t clear; 1324 drm_i830_clear_t clear;
1342 1325
1343 if (copy_from_user(&clear, (drm_i830_clear_t __user *)arg, sizeof(clear))) 1326 if (copy_from_user
1327 (&clear, (drm_i830_clear_t __user *) arg, sizeof(clear)))
1344 return -EFAULT; 1328 return -EFAULT;
1345 1329
1346 LOCK_TEST_WITH_RETURN(dev, filp); 1330 LOCK_TEST_WITH_RETURN(dev, filp);
1347 1331
1348 /* GH: Someone's doing nasty things... */ 1332 /* GH: Someone's doing nasty things... */
@@ -1350,11 +1334,10 @@ static int i830_clear_bufs(struct inode *inode, struct file *filp,
1350 return -EINVAL; 1334 return -EINVAL;
1351 } 1335 }
1352 1336
1353 i830_dma_dispatch_clear( dev, clear.flags, 1337 i830_dma_dispatch_clear(dev, clear.flags,
1354 clear.clear_color, 1338 clear.clear_color,
1355 clear.clear_depth, 1339 clear.clear_depth, clear.clear_depthmask);
1356 clear.clear_depthmask); 1340 return 0;
1357 return 0;
1358} 1341}
1359 1342
1360static int i830_swap_bufs(struct inode *inode, struct file *filp, 1343static int i830_swap_bufs(struct inode *inode, struct file *filp,
@@ -1362,20 +1345,18 @@ static int i830_swap_bufs(struct inode *inode, struct file *filp,
1362{ 1345{
1363 drm_file_t *priv = filp->private_data; 1346 drm_file_t *priv = filp->private_data;
1364 drm_device_t *dev = priv->head->dev; 1347 drm_device_t *dev = priv->head->dev;
1365 1348
1366 DRM_DEBUG("i830_swap_bufs\n"); 1349 DRM_DEBUG("i830_swap_bufs\n");
1367 1350
1368 LOCK_TEST_WITH_RETURN(dev, filp); 1351 LOCK_TEST_WITH_RETURN(dev, filp);
1369 1352
1370 i830_dma_dispatch_swap( dev ); 1353 i830_dma_dispatch_swap(dev);
1371 return 0; 1354 return 0;
1372} 1355}
1373 1356
1374
1375
1376/* Not sure why this isn't set all the time: 1357/* Not sure why this isn't set all the time:
1377 */ 1358 */
1378static void i830_do_init_pageflip( drm_device_t *dev ) 1359static void i830_do_init_pageflip(drm_device_t * dev)
1379{ 1360{
1380 drm_i830_private_t *dev_priv = dev->dev_private; 1361 drm_i830_private_t *dev_priv = dev->dev_private;
1381 1362
@@ -1385,20 +1366,20 @@ static void i830_do_init_pageflip( drm_device_t *dev )
1385 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; 1366 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
1386} 1367}
1387 1368
1388static int i830_do_cleanup_pageflip( drm_device_t *dev ) 1369static int i830_do_cleanup_pageflip(drm_device_t * dev)
1389{ 1370{
1390 drm_i830_private_t *dev_priv = dev->dev_private; 1371 drm_i830_private_t *dev_priv = dev->dev_private;
1391 1372
1392 DRM_DEBUG("%s\n", __FUNCTION__); 1373 DRM_DEBUG("%s\n", __FUNCTION__);
1393 if (dev_priv->current_page != 0) 1374 if (dev_priv->current_page != 0)
1394 i830_dma_dispatch_flip( dev ); 1375 i830_dma_dispatch_flip(dev);
1395 1376
1396 dev_priv->page_flipping = 0; 1377 dev_priv->page_flipping = 0;
1397 return 0; 1378 return 0;
1398} 1379}
1399 1380
1400static int i830_flip_bufs(struct inode *inode, struct file *filp, 1381static int i830_flip_bufs(struct inode *inode, struct file *filp,
1401 unsigned int cmd, unsigned long arg) 1382 unsigned int cmd, unsigned long arg)
1402{ 1383{
1403 drm_file_t *priv = filp->private_data; 1384 drm_file_t *priv = filp->private_data;
1404 drm_device_t *dev = priv->head->dev; 1385 drm_device_t *dev = priv->head->dev;
@@ -1408,45 +1389,45 @@ static int i830_flip_bufs(struct inode *inode, struct file *filp,
1408 1389
1409 LOCK_TEST_WITH_RETURN(dev, filp); 1390 LOCK_TEST_WITH_RETURN(dev, filp);
1410 1391
1411 if (!dev_priv->page_flipping) 1392 if (!dev_priv->page_flipping)
1412 i830_do_init_pageflip( dev ); 1393 i830_do_init_pageflip(dev);
1413 1394
1414 i830_dma_dispatch_flip( dev ); 1395 i830_dma_dispatch_flip(dev);
1415 return 0; 1396 return 0;
1416} 1397}
1417 1398
1418static int i830_getage(struct inode *inode, struct file *filp, unsigned int cmd, 1399static int i830_getage(struct inode *inode, struct file *filp, unsigned int cmd,
1419 unsigned long arg) 1400 unsigned long arg)
1420{ 1401{
1421 drm_file_t *priv = filp->private_data; 1402 drm_file_t *priv = filp->private_data;
1422 drm_device_t *dev = priv->head->dev; 1403 drm_device_t *dev = priv->head->dev;
1423 drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private; 1404 drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
1424 u32 *hw_status = dev_priv->hw_status_page; 1405 u32 *hw_status = dev_priv->hw_status_page;
1425 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) 1406 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *)
1426 dev_priv->sarea_priv; 1407 dev_priv->sarea_priv;
1427 1408
1428 sarea_priv->last_dispatch = (int) hw_status[5]; 1409 sarea_priv->last_dispatch = (int)hw_status[5];
1429 return 0; 1410 return 0;
1430} 1411}
1431 1412
1432static int i830_getbuf(struct inode *inode, struct file *filp, unsigned int cmd, 1413static int i830_getbuf(struct inode *inode, struct file *filp, unsigned int cmd,
1433 unsigned long arg) 1414 unsigned long arg)
1434{ 1415{
1435 drm_file_t *priv = filp->private_data; 1416 drm_file_t *priv = filp->private_data;
1436 drm_device_t *dev = priv->head->dev; 1417 drm_device_t *dev = priv->head->dev;
1437 int retcode = 0; 1418 int retcode = 0;
1438 drm_i830_dma_t d; 1419 drm_i830_dma_t d;
1439 drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private; 1420 drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
1440 u32 *hw_status = dev_priv->hw_status_page; 1421 u32 *hw_status = dev_priv->hw_status_page;
1441 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) 1422 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *)
1442 dev_priv->sarea_priv; 1423 dev_priv->sarea_priv;
1443 1424
1444 DRM_DEBUG("getbuf\n"); 1425 DRM_DEBUG("getbuf\n");
1445 if (copy_from_user(&d, (drm_i830_dma_t __user *)arg, sizeof(d))) 1426 if (copy_from_user(&d, (drm_i830_dma_t __user *) arg, sizeof(d)))
1446 return -EFAULT; 1427 return -EFAULT;
1447 1428
1448 LOCK_TEST_WITH_RETURN(dev, filp); 1429 LOCK_TEST_WITH_RETURN(dev, filp);
1449 1430
1450 d.granted = 0; 1431 d.granted = 0;
1451 1432
1452 retcode = i830_dma_get_buffer(dev, &d, filp); 1433 retcode = i830_dma_get_buffer(dev, &d, filp);
@@ -1454,46 +1435,45 @@ static int i830_getbuf(struct inode *inode, struct file *filp, unsigned int cmd,
1454 DRM_DEBUG("i830_dma: %d returning %d, granted = %d\n", 1435 DRM_DEBUG("i830_dma: %d returning %d, granted = %d\n",
1455 current->pid, retcode, d.granted); 1436 current->pid, retcode, d.granted);
1456 1437
1457 if (copy_to_user((drm_dma_t __user *)arg, &d, sizeof(d))) 1438 if (copy_to_user((drm_dma_t __user *) arg, &d, sizeof(d)))
1458 return -EFAULT; 1439 return -EFAULT;
1459 sarea_priv->last_dispatch = (int) hw_status[5]; 1440 sarea_priv->last_dispatch = (int)hw_status[5];
1460 1441
1461 return retcode; 1442 return retcode;
1462} 1443}
1463 1444
1464static int i830_copybuf(struct inode *inode, 1445static int i830_copybuf(struct inode *inode,
1465 struct file *filp, unsigned int cmd, unsigned long arg) 1446 struct file *filp, unsigned int cmd, unsigned long arg)
1466{ 1447{
1467 /* Never copy - 2.4.x doesn't need it */ 1448 /* Never copy - 2.4.x doesn't need it */
1468 return 0; 1449 return 0;
1469} 1450}
1470 1451
1471static int i830_docopy(struct inode *inode, struct file *filp, unsigned int cmd, 1452static int i830_docopy(struct inode *inode, struct file *filp, unsigned int cmd,
1472 unsigned long arg) 1453 unsigned long arg)
1473{ 1454{
1474 return 0; 1455 return 0;
1475} 1456}
1476 1457
1477 1458static int i830_getparam(struct inode *inode, struct file *filp,
1478 1459 unsigned int cmd, unsigned long arg)
1479static int i830_getparam( struct inode *inode, struct file *filp,
1480 unsigned int cmd, unsigned long arg )
1481{ 1460{
1482 drm_file_t *priv = filp->private_data; 1461 drm_file_t *priv = filp->private_data;
1483 drm_device_t *dev = priv->head->dev; 1462 drm_device_t *dev = priv->head->dev;
1484 drm_i830_private_t *dev_priv = dev->dev_private; 1463 drm_i830_private_t *dev_priv = dev->dev_private;
1485 drm_i830_getparam_t param; 1464 drm_i830_getparam_t param;
1486 int value; 1465 int value;
1487 1466
1488 if ( !dev_priv ) { 1467 if (!dev_priv) {
1489 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 1468 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1490 return -EINVAL; 1469 return -EINVAL;
1491 } 1470 }
1492 1471
1493 if (copy_from_user(&param, (drm_i830_getparam_t __user *)arg, sizeof(param) )) 1472 if (copy_from_user
1473 (&param, (drm_i830_getparam_t __user *) arg, sizeof(param)))
1494 return -EFAULT; 1474 return -EFAULT;
1495 1475
1496 switch( param.param ) { 1476 switch (param.param) {
1497 case I830_PARAM_IRQ_ACTIVE: 1477 case I830_PARAM_IRQ_ACTIVE:
1498 value = dev->irq_enabled; 1478 value = dev->irq_enabled;
1499 break; 1479 break;
@@ -1501,32 +1481,32 @@ static int i830_getparam( struct inode *inode, struct file *filp,
1501 return -EINVAL; 1481 return -EINVAL;
1502 } 1482 }
1503 1483
1504 if ( copy_to_user( param.value, &value, sizeof(int) ) ) { 1484 if (copy_to_user(param.value, &value, sizeof(int))) {
1505 DRM_ERROR( "copy_to_user\n" ); 1485 DRM_ERROR("copy_to_user\n");
1506 return -EFAULT; 1486 return -EFAULT;
1507 } 1487 }
1508 1488
1509 return 0; 1489 return 0;
1510} 1490}
1511 1491
1512 1492static int i830_setparam(struct inode *inode, struct file *filp,
1513static int i830_setparam( struct inode *inode, struct file *filp, 1493 unsigned int cmd, unsigned long arg)
1514 unsigned int cmd, unsigned long arg )
1515{ 1494{
1516 drm_file_t *priv = filp->private_data; 1495 drm_file_t *priv = filp->private_data;
1517 drm_device_t *dev = priv->head->dev; 1496 drm_device_t *dev = priv->head->dev;
1518 drm_i830_private_t *dev_priv = dev->dev_private; 1497 drm_i830_private_t *dev_priv = dev->dev_private;
1519 drm_i830_setparam_t param; 1498 drm_i830_setparam_t param;
1520 1499
1521 if ( !dev_priv ) { 1500 if (!dev_priv) {
1522 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 1501 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1523 return -EINVAL; 1502 return -EINVAL;
1524 } 1503 }
1525 1504
1526 if (copy_from_user(&param, (drm_i830_setparam_t __user *)arg, sizeof(param) )) 1505 if (copy_from_user
1506 (&param, (drm_i830_setparam_t __user *) arg, sizeof(param)))
1527 return -EFAULT; 1507 return -EFAULT;
1528 1508
1529 switch( param.param ) { 1509 switch (param.param) {
1530 case I830_SETPARAM_USE_MI_BATCHBUFFER_START: 1510 case I830_SETPARAM_USE_MI_BATCHBUFFER_START:
1531 dev_priv->use_mi_batchbuffer_start = param.value; 1511 dev_priv->use_mi_batchbuffer_start = param.value;
1532 break; 1512 break;
@@ -1537,13 +1517,12 @@ static int i830_setparam( struct inode *inode, struct file *filp,
1537 return 0; 1517 return 0;
1538} 1518}
1539 1519
1540 1520void i830_driver_pretakedown(drm_device_t * dev)
1541void i830_driver_pretakedown(drm_device_t *dev)
1542{ 1521{
1543 i830_dma_cleanup( dev ); 1522 i830_dma_cleanup(dev);
1544} 1523}
1545 1524
1546void i830_driver_prerelease(drm_device_t *dev, DRMFILE filp) 1525void i830_driver_prerelease(drm_device_t * dev, DRMFILE filp)
1547{ 1526{
1548 if (dev->dev_private) { 1527 if (dev->dev_private) {
1549 drm_i830_private_t *dev_priv = dev->dev_private; 1528 drm_i830_private_t *dev_priv = dev->dev_private;
@@ -1553,32 +1532,45 @@ void i830_driver_prerelease(drm_device_t *dev, DRMFILE filp)
1553 } 1532 }
1554} 1533}
1555 1534
1556void i830_driver_release(drm_device_t *dev, struct file *filp) 1535void i830_driver_release(drm_device_t * dev, struct file *filp)
1557{ 1536{
1558 i830_reclaim_buffers(dev, filp); 1537 i830_reclaim_buffers(dev, filp);
1559} 1538}
1560 1539
1561int i830_driver_dma_quiescent(drm_device_t *dev) 1540int i830_driver_dma_quiescent(drm_device_t * dev)
1562{ 1541{
1563 i830_dma_quiescent( dev ); 1542 i830_dma_quiescent(dev);
1564 return 0; 1543 return 0;
1565} 1544}
1566 1545
1567drm_ioctl_desc_t i830_ioctls[] = { 1546drm_ioctl_desc_t i830_ioctls[] = {
1568 [DRM_IOCTL_NR(DRM_I830_INIT)] = { i830_dma_init, 1, 1 }, 1547 [DRM_IOCTL_NR(DRM_I830_INIT)] = {i830_dma_init, 1, 1}
1569 [DRM_IOCTL_NR(DRM_I830_VERTEX)] = { i830_dma_vertex, 1, 0 }, 1548 ,
1570 [DRM_IOCTL_NR(DRM_I830_CLEAR)] = { i830_clear_bufs, 1, 0 }, 1549 [DRM_IOCTL_NR(DRM_I830_VERTEX)] = {i830_dma_vertex, 1, 0}
1571 [DRM_IOCTL_NR(DRM_I830_FLUSH)] = { i830_flush_ioctl, 1, 0 }, 1550 ,
1572 [DRM_IOCTL_NR(DRM_I830_GETAGE)] = { i830_getage, 1, 0 }, 1551 [DRM_IOCTL_NR(DRM_I830_CLEAR)] = {i830_clear_bufs, 1, 0}
1573 [DRM_IOCTL_NR(DRM_I830_GETBUF)] = { i830_getbuf, 1, 0 }, 1552 ,
1574 [DRM_IOCTL_NR(DRM_I830_SWAP)] = { i830_swap_bufs, 1, 0 }, 1553 [DRM_IOCTL_NR(DRM_I830_FLUSH)] = {i830_flush_ioctl, 1, 0}
1575 [DRM_IOCTL_NR(DRM_I830_COPY)] = { i830_copybuf, 1, 0 }, 1554 ,
1576 [DRM_IOCTL_NR(DRM_I830_DOCOPY)] = { i830_docopy, 1, 0 }, 1555 [DRM_IOCTL_NR(DRM_I830_GETAGE)] = {i830_getage, 1, 0}
1577 [DRM_IOCTL_NR(DRM_I830_FLIP)] = { i830_flip_bufs, 1, 0 }, 1556 ,
1578 [DRM_IOCTL_NR(DRM_I830_IRQ_EMIT)] = { i830_irq_emit, 1, 0 }, 1557 [DRM_IOCTL_NR(DRM_I830_GETBUF)] = {i830_getbuf, 1, 0}
1579 [DRM_IOCTL_NR(DRM_I830_IRQ_WAIT)] = { i830_irq_wait, 1, 0 }, 1558 ,
1580 [DRM_IOCTL_NR(DRM_I830_GETPARAM)] = { i830_getparam, 1, 0 }, 1559 [DRM_IOCTL_NR(DRM_I830_SWAP)] = {i830_swap_bufs, 1, 0}
1581 [DRM_IOCTL_NR(DRM_I830_SETPARAM)] = { i830_setparam, 1, 0 } 1560 ,
1561 [DRM_IOCTL_NR(DRM_I830_COPY)] = {i830_copybuf, 1, 0}
1562 ,
1563 [DRM_IOCTL_NR(DRM_I830_DOCOPY)] = {i830_docopy, 1, 0}
1564 ,
1565 [DRM_IOCTL_NR(DRM_I830_FLIP)] = {i830_flip_bufs, 1, 0}
1566 ,
1567 [DRM_IOCTL_NR(DRM_I830_IRQ_EMIT)] = {i830_irq_emit, 1, 0}
1568 ,
1569 [DRM_IOCTL_NR(DRM_I830_IRQ_WAIT)] = {i830_irq_wait, 1, 0}
1570 ,
1571 [DRM_IOCTL_NR(DRM_I830_GETPARAM)] = {i830_getparam, 1, 0}
1572 ,
1573 [DRM_IOCTL_NR(DRM_I830_SETPARAM)] = {i830_setparam, 1, 0}
1582}; 1574};
1583 1575
1584int i830_max_ioctl = DRM_ARRAY_SIZE(i830_ioctls); 1576int i830_max_ioctl = DRM_ARRAY_SIZE(i830_ioctls);
diff --git a/drivers/char/drm/i830_drm.h b/drivers/char/drm/i830_drm.h
index 03382c0beee3..66dd75027967 100644
--- a/drivers/char/drm/i830_drm.h
+++ b/drivers/char/drm/i830_drm.h
@@ -33,14 +33,14 @@
33#define I830_UPLOAD_CTX 0x1 33#define I830_UPLOAD_CTX 0x1
34#define I830_UPLOAD_BUFFERS 0x2 34#define I830_UPLOAD_BUFFERS 0x2
35#define I830_UPLOAD_CLIPRECTS 0x4 35#define I830_UPLOAD_CLIPRECTS 0x4
36#define I830_UPLOAD_TEX0_IMAGE 0x100 /* handled clientside */ 36#define I830_UPLOAD_TEX0_IMAGE 0x100 /* handled clientside */
37#define I830_UPLOAD_TEX0_CUBE 0x200 /* handled clientside */ 37#define I830_UPLOAD_TEX0_CUBE 0x200 /* handled clientside */
38#define I830_UPLOAD_TEX1_IMAGE 0x400 /* handled clientside */ 38#define I830_UPLOAD_TEX1_IMAGE 0x400 /* handled clientside */
39#define I830_UPLOAD_TEX1_CUBE 0x800 /* handled clientside */ 39#define I830_UPLOAD_TEX1_CUBE 0x800 /* handled clientside */
40#define I830_UPLOAD_TEX2_IMAGE 0x1000 /* handled clientside */ 40#define I830_UPLOAD_TEX2_IMAGE 0x1000 /* handled clientside */
41#define I830_UPLOAD_TEX2_CUBE 0x2000 /* handled clientside */ 41#define I830_UPLOAD_TEX2_CUBE 0x2000 /* handled clientside */
42#define I830_UPLOAD_TEX3_IMAGE 0x4000 /* handled clientside */ 42#define I830_UPLOAD_TEX3_IMAGE 0x4000 /* handled clientside */
43#define I830_UPLOAD_TEX3_CUBE 0x8000 /* handled clientside */ 43#define I830_UPLOAD_TEX3_CUBE 0x8000 /* handled clientside */
44#define I830_UPLOAD_TEX_N_IMAGE(n) (0x100 << (n * 2)) 44#define I830_UPLOAD_TEX_N_IMAGE(n) (0x100 << (n * 2))
45#define I830_UPLOAD_TEX_N_CUBE(n) (0x200 << (n * 2)) 45#define I830_UPLOAD_TEX_N_CUBE(n) (0x200 << (n * 2))
46#define I830_UPLOAD_TEXIMAGE_MASK 0xff00 46#define I830_UPLOAD_TEXIMAGE_MASK 0xff00
@@ -65,7 +65,7 @@
65 * or in a piecewise fashion as required. 65 * or in a piecewise fashion as required.
66 */ 66 */
67 67
68/* Destbuffer state 68/* Destbuffer state
69 * - backbuffer linear offset and pitch -- invarient in the current dri 69 * - backbuffer linear offset and pitch -- invarient in the current dri
70 * - zbuffer linear offset and pitch -- also invarient 70 * - zbuffer linear offset and pitch -- also invarient
71 * - drawing origin in back and depth buffers. 71 * - drawing origin in back and depth buffers.
@@ -103,7 +103,7 @@
103#define I830_CTXREG_AA 9 103#define I830_CTXREG_AA 9
104#define I830_CTXREG_FOGCOLOR 10 104#define I830_CTXREG_FOGCOLOR 10
105#define I830_CTXREG_BLENDCOLR0 11 105#define I830_CTXREG_BLENDCOLR0 11
106#define I830_CTXREG_BLENDCOLR 12 /* Dword 1 of 2 dword command */ 106#define I830_CTXREG_BLENDCOLR 12 /* Dword 1 of 2 dword command */
107#define I830_CTXREG_VF 13 107#define I830_CTXREG_VF 13
108#define I830_CTXREG_VF2 14 108#define I830_CTXREG_VF2 14
109#define I830_CTXREG_MCSB0 15 109#define I830_CTXREG_MCSB0 15
@@ -111,12 +111,11 @@
111#define I830_CTX_SETUP_SIZE 17 111#define I830_CTX_SETUP_SIZE 17
112 112
113/* 1.3: Stipple state 113/* 1.3: Stipple state
114 */ 114 */
115#define I830_STPREG_ST0 0 115#define I830_STPREG_ST0 0
116#define I830_STPREG_ST1 1 116#define I830_STPREG_ST1 1
117#define I830_STP_SETUP_SIZE 2 117#define I830_STP_SETUP_SIZE 2
118 118
119
120/* Texture state (per tex unit) 119/* Texture state (per tex unit)
121 */ 120 */
122 121
@@ -132,23 +131,23 @@
132#define I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS */ 131#define I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS */
133#define I830_TEX_SETUP_SIZE 10 132#define I830_TEX_SETUP_SIZE 10
134 133
135#define I830_TEXREG_TM0LI 0 /* load immediate 2 texture map n */ 134#define I830_TEXREG_TM0LI 0 /* load immediate 2 texture map n */
136#define I830_TEXREG_TM0S0 1 135#define I830_TEXREG_TM0S0 1
137#define I830_TEXREG_TM0S1 2 136#define I830_TEXREG_TM0S1 2
138#define I830_TEXREG_TM0S2 3 137#define I830_TEXREG_TM0S2 3
139#define I830_TEXREG_TM0S3 4 138#define I830_TEXREG_TM0S3 4
140#define I830_TEXREG_TM0S4 5 139#define I830_TEXREG_TM0S4 5
141#define I830_TEXREG_NOP0 6 /* noop */ 140#define I830_TEXREG_NOP0 6 /* noop */
142#define I830_TEXREG_NOP1 7 /* noop */ 141#define I830_TEXREG_NOP1 7 /* noop */
143#define I830_TEXREG_NOP2 8 /* noop */ 142#define I830_TEXREG_NOP2 8 /* noop */
144#define __I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS -- shared */ 143#define __I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS -- shared */
145#define __I830_TEX_SETUP_SIZE 10 144#define __I830_TEX_SETUP_SIZE 10
146 145
147#define I830_FRONT 0x1 146#define I830_FRONT 0x1
148#define I830_BACK 0x2 147#define I830_BACK 0x2
149#define I830_DEPTH 0x4 148#define I830_DEPTH 0x4
150 149
151#endif /* _I830_DEFINES_ */ 150#endif /* _I830_DEFINES_ */
152 151
153typedef struct _drm_i830_init { 152typedef struct _drm_i830_init {
154 enum { 153 enum {
@@ -177,19 +176,19 @@ typedef struct _drm_i830_init {
177 * structure as well */ 176 * structure as well */
178 177
179typedef struct _drm_i830_tex_region { 178typedef struct _drm_i830_tex_region {
180 unsigned char next, prev; /* indices to form a circular LRU */ 179 unsigned char next, prev; /* indices to form a circular LRU */
181 unsigned char in_use; /* owned by a client, or free? */ 180 unsigned char in_use; /* owned by a client, or free? */
182 int age; /* tracked by clients to update local LRU's */ 181 int age; /* tracked by clients to update local LRU's */
183} drm_i830_tex_region_t; 182} drm_i830_tex_region_t;
184 183
185typedef struct _drm_i830_sarea { 184typedef struct _drm_i830_sarea {
186 unsigned int ContextState[I830_CTX_SETUP_SIZE]; 185 unsigned int ContextState[I830_CTX_SETUP_SIZE];
187 unsigned int BufferState[I830_DEST_SETUP_SIZE]; 186 unsigned int BufferState[I830_DEST_SETUP_SIZE];
188 unsigned int TexState[I830_TEXTURE_COUNT][I830_TEX_SETUP_SIZE]; 187 unsigned int TexState[I830_TEXTURE_COUNT][I830_TEX_SETUP_SIZE];
189 unsigned int TexBlendState[I830_TEXBLEND_COUNT][I830_TEXBLEND_SIZE]; 188 unsigned int TexBlendState[I830_TEXBLEND_COUNT][I830_TEXBLEND_SIZE];
190 unsigned int TexBlendStateWordsUsed[I830_TEXBLEND_COUNT]; 189 unsigned int TexBlendStateWordsUsed[I830_TEXBLEND_COUNT];
191 unsigned int Palette[2][256]; 190 unsigned int Palette[2][256];
192 unsigned int dirty; 191 unsigned int dirty;
193 192
194 unsigned int nbox; 193 unsigned int nbox;
195 drm_clip_rect_t boxes[I830_NR_SAREA_CLIPRECTS]; 194 drm_clip_rect_t boxes[I830_NR_SAREA_CLIPRECTS];
@@ -207,26 +206,26 @@ typedef struct _drm_i830_sarea {
207 * texture space, and can make informed decisions as to which 206 * texture space, and can make informed decisions as to which
208 * areas to kick out. There is no need to choose whether to 207 * areas to kick out. There is no need to choose whether to
209 * kick out your own texture or someone else's - simply eject 208 * kick out your own texture or someone else's - simply eject
210 * them all in LRU order. 209 * them all in LRU order.
211 */ 210 */
212 211
213 drm_i830_tex_region_t texList[I830_NR_TEX_REGIONS+1]; 212 drm_i830_tex_region_t texList[I830_NR_TEX_REGIONS + 1];
214 /* Last elt is sentinal */ 213 /* Last elt is sentinal */
215 int texAge; /* last time texture was uploaded */ 214 int texAge; /* last time texture was uploaded */
216 int last_enqueue; /* last time a buffer was enqueued */ 215 int last_enqueue; /* last time a buffer was enqueued */
217 int last_dispatch; /* age of the most recently dispatched buffer */ 216 int last_dispatch; /* age of the most recently dispatched buffer */
218 int last_quiescent; /* */ 217 int last_quiescent; /* */
219 int ctxOwner; /* last context to upload state */ 218 int ctxOwner; /* last context to upload state */
220 219
221 int vertex_prim; 220 int vertex_prim;
222 221
223 int pf_enabled; /* is pageflipping allowed? */ 222 int pf_enabled; /* is pageflipping allowed? */
224 int pf_active; 223 int pf_active;
225 int pf_current_page; /* which buffer is being displayed? */ 224 int pf_current_page; /* which buffer is being displayed? */
225
226 int perf_boxes; /* performance boxes to be displayed */
226 227
227 int perf_boxes; /* performance boxes to be displayed */ 228 /* Here's the state for texunits 2,3:
228
229 /* Here's the state for texunits 2,3:
230 */ 229 */
231 unsigned int TexState2[I830_TEX_SETUP_SIZE]; 230 unsigned int TexState2[I830_TEX_SETUP_SIZE];
232 unsigned int TexBlendState2[I830_TEXBLEND_SIZE]; 231 unsigned int TexBlendState2[I830_TEXBLEND_SIZE];
@@ -241,12 +240,11 @@ typedef struct _drm_i830_sarea {
241 240
242/* Flags for perf_boxes 241/* Flags for perf_boxes
243 */ 242 */
244#define I830_BOX_RING_EMPTY 0x1 /* populated by kernel */ 243#define I830_BOX_RING_EMPTY 0x1 /* populated by kernel */
245#define I830_BOX_FLIP 0x2 /* populated by kernel */ 244#define I830_BOX_FLIP 0x2 /* populated by kernel */
246#define I830_BOX_WAIT 0x4 /* populated by kernel & client */ 245#define I830_BOX_WAIT 0x4 /* populated by kernel & client */
247#define I830_BOX_TEXTURE_LOAD 0x8 /* populated by kernel */ 246#define I830_BOX_TEXTURE_LOAD 0x8 /* populated by kernel */
248#define I830_BOX_LOST_CONTEXT 0x10 /* populated by client */ 247#define I830_BOX_LOST_CONTEXT 0x10 /* populated by client */
249
250 248
251/* I830 specific ioctls 249/* I830 specific ioctls
252 * The device specific ioctl range is 0x40 to 0x79. 250 * The device specific ioctl range is 0x40 to 0x79.
@@ -289,23 +287,21 @@ typedef struct _drm_i830_clear {
289 unsigned int clear_depthmask; 287 unsigned int clear_depthmask;
290} drm_i830_clear_t; 288} drm_i830_clear_t;
291 289
292
293
294/* These may be placeholders if we have more cliprects than 290/* These may be placeholders if we have more cliprects than
295 * I830_NR_SAREA_CLIPRECTS. In that case, the client sets discard to 291 * I830_NR_SAREA_CLIPRECTS. In that case, the client sets discard to
296 * false, indicating that the buffer will be dispatched again with a 292 * false, indicating that the buffer will be dispatched again with a
297 * new set of cliprects. 293 * new set of cliprects.
298 */ 294 */
299typedef struct _drm_i830_vertex { 295typedef struct _drm_i830_vertex {
300 int idx; /* buffer index */ 296 int idx; /* buffer index */
301 int used; /* nr bytes in use */ 297 int used; /* nr bytes in use */
302 int discard; /* client is finished with the buffer? */ 298 int discard; /* client is finished with the buffer? */
303} drm_i830_vertex_t; 299} drm_i830_vertex_t;
304 300
305typedef struct _drm_i830_copy_t { 301typedef struct _drm_i830_copy_t {
306 int idx; /* buffer index */ 302 int idx; /* buffer index */
307 int used; /* nr bytes in use */ 303 int used; /* nr bytes in use */
308 void __user *address; /* Address to copy from */ 304 void __user *address; /* Address to copy from */
309} drm_i830_copy_t; 305} drm_i830_copy_t;
310 306
311typedef struct drm_i830_dma { 307typedef struct drm_i830_dma {
@@ -315,7 +311,6 @@ typedef struct drm_i830_dma {
315 int granted; 311 int granted;
316} drm_i830_dma_t; 312} drm_i830_dma_t;
317 313
318
319/* 1.3: Userspace can request & wait on irq's: 314/* 1.3: Userspace can request & wait on irq's:
320 */ 315 */
321typedef struct drm_i830_irq_emit { 316typedef struct drm_i830_irq_emit {
@@ -326,7 +321,6 @@ typedef struct drm_i830_irq_wait {
326 int irq_seq; 321 int irq_seq;
327} drm_i830_irq_wait_t; 322} drm_i830_irq_wait_t;
328 323
329
330/* 1.3: New ioctl to query kernel params: 324/* 1.3: New ioctl to query kernel params:
331 */ 325 */
332#define I830_PARAM_IRQ_ACTIVE 1 326#define I830_PARAM_IRQ_ACTIVE 1
@@ -336,7 +330,6 @@ typedef struct drm_i830_getparam {
336 int __user *value; 330 int __user *value;
337} drm_i830_getparam_t; 331} drm_i830_getparam_t;
338 332
339
340/* 1.3: New ioctl to set kernel params: 333/* 1.3: New ioctl to set kernel params:
341 */ 334 */
342#define I830_SETPARAM_USE_MI_BATCHBUFFER_START 1 335#define I830_SETPARAM_USE_MI_BATCHBUFFER_START 1
@@ -346,5 +339,4 @@ typedef struct drm_i830_setparam {
346 int value; 339 int value;
347} drm_i830_setparam_t; 340} drm_i830_setparam_t;
348 341
349 342#endif /* _I830_DRM_H_ */
350#endif /* _I830_DRM_H_ */
diff --git a/drivers/char/drm/i830_drv.c b/drivers/char/drm/i830_drv.c
index 0da9cd19919e..6dad356450bc 100644
--- a/drivers/char/drm/i830_drv.c
+++ b/drivers/char/drm/i830_drv.c
@@ -40,36 +40,34 @@
40 40
41#include "drm_pciids.h" 41#include "drm_pciids.h"
42 42
43static int postinit( struct drm_device *dev, unsigned long flags ) 43static int postinit(struct drm_device *dev, unsigned long flags)
44{ 44{
45 dev->counters += 4; 45 dev->counters += 4;
46 dev->types[6] = _DRM_STAT_IRQ; 46 dev->types[6] = _DRM_STAT_IRQ;
47 dev->types[7] = _DRM_STAT_PRIMARY; 47 dev->types[7] = _DRM_STAT_PRIMARY;
48 dev->types[8] = _DRM_STAT_SECONDARY; 48 dev->types[8] = _DRM_STAT_SECONDARY;
49 dev->types[9] = _DRM_STAT_DMA; 49 dev->types[9] = _DRM_STAT_DMA;
50 50
51 DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", 51 DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n",
52 DRIVER_NAME, 52 DRIVER_NAME,
53 DRIVER_MAJOR, 53 DRIVER_MAJOR,
54 DRIVER_MINOR, 54 DRIVER_MINOR,
55 DRIVER_PATCHLEVEL, 55 DRIVER_PATCHLEVEL,
56 DRIVER_DATE, 56 DRIVER_DATE, dev->primary.minor, pci_pretty_name(dev->pdev)
57 dev->primary.minor, 57 );
58 pci_pretty_name(dev->pdev)
59 );
60 return 0; 58 return 0;
61} 59}
62 60
63static int version( drm_version_t *version ) 61static int version(drm_version_t * version)
64{ 62{
65 int len; 63 int len;
66 64
67 version->version_major = DRIVER_MAJOR; 65 version->version_major = DRIVER_MAJOR;
68 version->version_minor = DRIVER_MINOR; 66 version->version_minor = DRIVER_MINOR;
69 version->version_patchlevel = DRIVER_PATCHLEVEL; 67 version->version_patchlevel = DRIVER_PATCHLEVEL;
70 DRM_COPY( version->name, DRIVER_NAME ); 68 DRM_COPY(version->name, DRIVER_NAME);
71 DRM_COPY( version->date, DRIVER_DATE ); 69 DRM_COPY(version->date, DRIVER_DATE);
72 DRM_COPY( version->desc, DRIVER_DESC ); 70 DRM_COPY(version->desc, DRIVER_DESC);
73 return 0; 71 return 0;
74} 72}
75 73
@@ -81,7 +79,9 @@ extern drm_ioctl_desc_t i830_ioctls[];
81extern int i830_max_ioctl; 79extern int i830_max_ioctl;
82 80
83static struct drm_driver driver = { 81static struct drm_driver driver = {
84 .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_DMA | DRIVER_DMA_QUEUE, 82 .driver_features =
83 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR |
84 DRIVER_HAVE_DMA | DRIVER_DMA_QUEUE,
85#if USE_IRQS 85#if USE_IRQS
86 .driver_features |= DRIVER_HAVE_IRQ | DRIVER_SHARED_IRQ, 86 .driver_features |= DRIVER_HAVE_IRQ | DRIVER_SHARED_IRQ,
87#endif 87#endif
@@ -104,18 +104,19 @@ static struct drm_driver driver = {
104 .version = version, 104 .version = version,
105 .ioctls = i830_ioctls, 105 .ioctls = i830_ioctls,
106 .fops = { 106 .fops = {
107 .owner = THIS_MODULE, 107 .owner = THIS_MODULE,
108 .open = drm_open, 108 .open = drm_open,
109 .release = drm_release, 109 .release = drm_release,
110 .ioctl = drm_ioctl, 110 .ioctl = drm_ioctl,
111 .mmap = drm_mmap, 111 .mmap = drm_mmap,
112 .poll = drm_poll, 112 .poll = drm_poll,
113 .fasync = drm_fasync, 113 .fasync = drm_fasync,
114 }, 114 }
115 ,
115 .pci_driver = { 116 .pci_driver = {
116 .name = DRIVER_NAME, 117 .name = DRIVER_NAME,
117 .id_table = pciidlist, 118 .id_table = pciidlist,
118 } 119 }
119 120
120}; 121};
121 122
@@ -133,6 +134,6 @@ static void __exit i830_exit(void)
133module_init(i830_init); 134module_init(i830_init);
134module_exit(i830_exit); 135module_exit(i830_exit);
135 136
136MODULE_AUTHOR( DRIVER_AUTHOR ); 137MODULE_AUTHOR(DRIVER_AUTHOR);
137MODULE_DESCRIPTION( DRIVER_DESC ); 138MODULE_DESCRIPTION(DRIVER_DESC);
138MODULE_LICENSE("GPL and additional rights"); 139MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/char/drm/i830_drv.h b/drivers/char/drm/i830_drv.h
index 63f96a8b6a4a..99835465c44b 100644
--- a/drivers/char/drm/i830_drv.h
+++ b/drivers/char/drm/i830_drv.h
@@ -11,11 +11,11 @@
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the 12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions: 13 * Software is furnished to do so, subject to the following conditions:
14 * 14 *
15 * The above copyright notice and this permission notice (including the next 15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the 16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software. 17 * Software.
18 * 18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -63,14 +63,14 @@
63#define USE_IRQS 0 63#define USE_IRQS 0
64 64
65typedef struct drm_i830_buf_priv { 65typedef struct drm_i830_buf_priv {
66 u32 *in_use; 66 u32 *in_use;
67 int my_use_idx; 67 int my_use_idx;
68 int currently_mapped; 68 int currently_mapped;
69 void __user *virtual; 69 void __user *virtual;
70 void *kernel_virtual; 70 void *kernel_virtual;
71} drm_i830_buf_priv_t; 71} drm_i830_buf_priv_t;
72 72
73typedef struct _drm_i830_ring_buffer{ 73typedef struct _drm_i830_ring_buffer {
74 int tail_mask; 74 int tail_mask;
75 unsigned long Start; 75 unsigned long Start;
76 unsigned long End; 76 unsigned long End;
@@ -86,17 +86,17 @@ typedef struct drm_i830_private {
86 drm_map_t *mmio_map; 86 drm_map_t *mmio_map;
87 87
88 drm_i830_sarea_t *sarea_priv; 88 drm_i830_sarea_t *sarea_priv;
89 drm_i830_ring_buffer_t ring; 89 drm_i830_ring_buffer_t ring;
90 90
91 void * hw_status_page; 91 void *hw_status_page;
92 unsigned long counter; 92 unsigned long counter;
93 93
94 dma_addr_t dma_status_page; 94 dma_addr_t dma_status_page;
95 95
96 drm_buf_t *mmap_buffer; 96 drm_buf_t *mmap_buffer;
97 97
98 u32 front_di1, back_di1, zi1; 98 u32 front_di1, back_di1, zi1;
99 99
100 int back_offset; 100 int back_offset;
101 int depth_offset; 101 int depth_offset;
102 int front_offset; 102 int front_offset;
@@ -113,30 +113,30 @@ typedef struct drm_i830_private {
113 int page_flipping; 113 int page_flipping;
114 114
115 wait_queue_head_t irq_queue; 115 wait_queue_head_t irq_queue;
116 atomic_t irq_received; 116 atomic_t irq_received;
117 atomic_t irq_emitted; 117 atomic_t irq_emitted;
118 118
119 int use_mi_batchbuffer_start; 119 int use_mi_batchbuffer_start;
120 120
121} drm_i830_private_t; 121} drm_i830_private_t;
122 122
123/* i830_dma.c */ 123/* i830_dma.c */
124extern void i830_reclaim_buffers(drm_device_t *dev, struct file *filp); 124extern void i830_reclaim_buffers(drm_device_t * dev, struct file *filp);
125 125
126/* i830_irq.c */ 126/* i830_irq.c */
127extern int i830_irq_emit( struct inode *inode, struct file *filp, 127extern int i830_irq_emit(struct inode *inode, struct file *filp,
128 unsigned int cmd, unsigned long arg ); 128 unsigned int cmd, unsigned long arg);
129extern int i830_irq_wait( struct inode *inode, struct file *filp, 129extern int i830_irq_wait(struct inode *inode, struct file *filp,
130 unsigned int cmd, unsigned long arg ); 130 unsigned int cmd, unsigned long arg);
131 131
132extern irqreturn_t i830_driver_irq_handler( DRM_IRQ_ARGS ); 132extern irqreturn_t i830_driver_irq_handler(DRM_IRQ_ARGS);
133extern void i830_driver_irq_preinstall( drm_device_t *dev ); 133extern void i830_driver_irq_preinstall(drm_device_t * dev);
134extern void i830_driver_irq_postinstall( drm_device_t *dev ); 134extern void i830_driver_irq_postinstall(drm_device_t * dev);
135extern void i830_driver_irq_uninstall( drm_device_t *dev ); 135extern void i830_driver_irq_uninstall(drm_device_t * dev);
136extern void i830_driver_pretakedown(drm_device_t *dev); 136extern void i830_driver_pretakedown(drm_device_t * dev);
137extern void i830_driver_release(drm_device_t *dev, struct file *filp); 137extern void i830_driver_release(drm_device_t * dev, struct file *filp);
138extern int i830_driver_dma_quiescent(drm_device_t *dev); 138extern int i830_driver_dma_quiescent(drm_device_t * dev);
139extern void i830_driver_prerelease(drm_device_t *dev, DRMFILE filp); 139extern void i830_driver_prerelease(drm_device_t * dev, DRMFILE filp);
140extern int i830_driver_device_is_agp(drm_device_t * dev); 140extern int i830_driver_device_is_agp(drm_device_t * dev);
141 141
142#define I830_BASE(reg) ((unsigned long) \ 142#define I830_BASE(reg) ((unsigned long) \
@@ -149,8 +149,6 @@ extern int i830_driver_device_is_agp(drm_device_t * dev);
149#define I830_READ16(reg) I830_DEREF16(reg) 149#define I830_READ16(reg) I830_DEREF16(reg)
150#define I830_WRITE16(reg,val) do { I830_DEREF16(reg) = val; } while (0) 150#define I830_WRITE16(reg,val) do { I830_DEREF16(reg) = val; } while (0)
151 151
152
153
154#define I830_VERBOSE 0 152#define I830_VERBOSE 0
155 153
156#define RING_LOCALS unsigned int outring, ringmask, outcount; \ 154#define RING_LOCALS unsigned int outring, ringmask, outcount; \
@@ -168,7 +166,6 @@ extern int i830_driver_device_is_agp(drm_device_t * dev);
168 virt = dev_priv->ring.virtual_start; \ 166 virt = dev_priv->ring.virtual_start; \
169} while (0) 167} while (0)
170 168
171
172#define OUT_RING(n) do { \ 169#define OUT_RING(n) do { \
173 if (I830_VERBOSE) printk(" OUT_RING %x\n", (int)(n)); \ 170 if (I830_VERBOSE) printk(" OUT_RING %x\n", (int)(n)); \
174 *(volatile unsigned int *)(virt + outring) = n; \ 171 *(volatile unsigned int *)(virt + outring) = n; \
@@ -184,8 +181,7 @@ extern int i830_driver_device_is_agp(drm_device_t * dev);
184 I830_WRITE(LP_RING + RING_TAIL, outring); \ 181 I830_WRITE(LP_RING + RING_TAIL, outring); \
185} while(0) 182} while(0)
186 183
187extern int i830_wait_ring(drm_device_t *dev, int n, const char *caller); 184extern int i830_wait_ring(drm_device_t * dev, int n, const char *caller);
188
189 185
190#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) 186#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
191#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) 187#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
@@ -200,7 +196,6 @@ extern int i830_wait_ring(drm_device_t *dev, int n, const char *caller);
200#define INST_OP_FLUSH 0x02000000 196#define INST_OP_FLUSH 0x02000000
201#define INST_FLUSH_MAP_CACHE 0x00000001 197#define INST_FLUSH_MAP_CACHE 0x00000001
202 198
203
204#define BB1_START_ADDR_MASK (~0x7) 199#define BB1_START_ADDR_MASK (~0x7)
205#define BB1_PROTECTED (1<<0) 200#define BB1_PROTECTED (1<<0)
206#define BB1_UNPROTECTED (0<<0) 201#define BB1_UNPROTECTED (0<<0)
@@ -213,7 +208,6 @@ extern int i830_wait_ring(drm_device_t *dev, int n, const char *caller);
213 208
214#define I830_IRQ_RESERVED ((1<<13)|(3<<2)) 209#define I830_IRQ_RESERVED ((1<<13)|(3<<2))
215 210
216
217#define LP_RING 0x2030 211#define LP_RING 0x2030
218#define HP_RING 0x2040 212#define HP_RING 0x2040
219#define RING_TAIL 0x00 213#define RING_TAIL 0x00
@@ -225,7 +219,7 @@ extern int i830_wait_ring(drm_device_t *dev, int n, const char *caller);
225#define RING_START 0x08 219#define RING_START 0x08
226#define START_ADDR 0x0xFFFFF000 220#define START_ADDR 0x0xFFFFF000
227#define RING_LEN 0x0C 221#define RING_LEN 0x0C
228#define RING_NR_PAGES 0x001FF000 222#define RING_NR_PAGES 0x001FF000
229#define RING_REPORT_MASK 0x00000006 223#define RING_REPORT_MASK 0x00000006
230#define RING_REPORT_64K 0x00000002 224#define RING_REPORT_64K 0x00000002
231#define RING_REPORT_128K 0x00000004 225#define RING_REPORT_128K 0x00000004
@@ -291,10 +285,9 @@ extern int i830_wait_ring(drm_device_t *dev, int n, const char *caller);
291#define MI_BATCH_NON_SECURE (1) 285#define MI_BATCH_NON_SECURE (1)
292 286
293#define MI_WAIT_FOR_EVENT ((0x3<<23)) 287#define MI_WAIT_FOR_EVENT ((0x3<<23))
294#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 288#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
295#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 289#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
296 290
297#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23)) 291#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
298 292
299#endif 293#endif
300
diff --git a/drivers/char/drm/i830_irq.c b/drivers/char/drm/i830_irq.c
index a5923e5d0a77..5841f7674956 100644
--- a/drivers/char/drm/i830_irq.c
+++ b/drivers/char/drm/i830_irq.c
@@ -9,11 +9,11 @@
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the 10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions: 11 * Software is furnished to do so, subject to the following conditions:
12 * 12 *
13 * The above copyright notice and this permission notice (including the next 13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the 14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software. 15 * Software.
16 * 16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -33,28 +33,27 @@
33#include <linux/interrupt.h> /* For task queue support */ 33#include <linux/interrupt.h> /* For task queue support */
34#include <linux/delay.h> 34#include <linux/delay.h>
35 35
36 36irqreturn_t i830_driver_irq_handler(DRM_IRQ_ARGS)
37irqreturn_t i830_driver_irq_handler( DRM_IRQ_ARGS )
38{ 37{
39 drm_device_t *dev = (drm_device_t *)arg; 38 drm_device_t *dev = (drm_device_t *) arg;
40 drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private; 39 drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
41 u16 temp; 40 u16 temp;
42 41
43 temp = I830_READ16(I830REG_INT_IDENTITY_R); 42 temp = I830_READ16(I830REG_INT_IDENTITY_R);
44 DRM_DEBUG("%x\n", temp); 43 DRM_DEBUG("%x\n", temp);
45 44
46 if ( !( temp & 2 ) ) 45 if (!(temp & 2))
47 return IRQ_NONE; 46 return IRQ_NONE;
48 47
49 I830_WRITE16(I830REG_INT_IDENTITY_R, temp); 48 I830_WRITE16(I830REG_INT_IDENTITY_R, temp);
50 49
51 atomic_inc(&dev_priv->irq_received); 50 atomic_inc(&dev_priv->irq_received);
52 wake_up_interruptible(&dev_priv->irq_queue); 51 wake_up_interruptible(&dev_priv->irq_queue);
53 52
54 return IRQ_HANDLED; 53 return IRQ_HANDLED;
55} 54}
56 55
57static int i830_emit_irq(drm_device_t *dev) 56static int i830_emit_irq(drm_device_t * dev)
58{ 57{
59 drm_i830_private_t *dev_priv = dev->dev_private; 58 drm_i830_private_t *dev_priv = dev->dev_private;
60 RING_LOCALS; 59 RING_LOCALS;
@@ -63,27 +62,25 @@ static int i830_emit_irq(drm_device_t *dev)
63 62
64 atomic_inc(&dev_priv->irq_emitted); 63 atomic_inc(&dev_priv->irq_emitted);
65 64
66 BEGIN_LP_RING(2); 65 BEGIN_LP_RING(2);
67 OUT_RING( 0 ); 66 OUT_RING(0);
68 OUT_RING( GFX_OP_USER_INTERRUPT ); 67 OUT_RING(GFX_OP_USER_INTERRUPT);
69 ADVANCE_LP_RING(); 68 ADVANCE_LP_RING();
70 69
71 return atomic_read(&dev_priv->irq_emitted); 70 return atomic_read(&dev_priv->irq_emitted);
72} 71}
73 72
74 73static int i830_wait_irq(drm_device_t * dev, int irq_nr)
75static int i830_wait_irq(drm_device_t *dev, int irq_nr)
76{ 74{
77 drm_i830_private_t *dev_priv = 75 drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
78 (drm_i830_private_t *)dev->dev_private;
79 DECLARE_WAITQUEUE(entry, current); 76 DECLARE_WAITQUEUE(entry, current);
80 unsigned long end = jiffies + HZ*3; 77 unsigned long end = jiffies + HZ * 3;
81 int ret = 0; 78 int ret = 0;
82 79
83 DRM_DEBUG("%s\n", __FUNCTION__); 80 DRM_DEBUG("%s\n", __FUNCTION__);
84 81
85 if (atomic_read(&dev_priv->irq_received) >= irq_nr) 82 if (atomic_read(&dev_priv->irq_received) >= irq_nr)
86 return 0; 83 return 0;
87 84
88 dev_priv->sarea_priv->perf_boxes |= I830_BOX_WAIT; 85 dev_priv->sarea_priv->perf_boxes |= I830_BOX_WAIT;
89 86
@@ -91,21 +88,21 @@ static int i830_wait_irq(drm_device_t *dev, int irq_nr)
91 88
92 for (;;) { 89 for (;;) {
93 __set_current_state(TASK_INTERRUPTIBLE); 90 __set_current_state(TASK_INTERRUPTIBLE);
94 if (atomic_read(&dev_priv->irq_received) >= irq_nr) 91 if (atomic_read(&dev_priv->irq_received) >= irq_nr)
95 break; 92 break;
96 if((signed)(end - jiffies) <= 0) { 93 if ((signed)(end - jiffies) <= 0) {
97 DRM_ERROR("timeout iir %x imr %x ier %x hwstam %x\n", 94 DRM_ERROR("timeout iir %x imr %x ier %x hwstam %x\n",
98 I830_READ16( I830REG_INT_IDENTITY_R ), 95 I830_READ16(I830REG_INT_IDENTITY_R),
99 I830_READ16( I830REG_INT_MASK_R ), 96 I830_READ16(I830REG_INT_MASK_R),
100 I830_READ16( I830REG_INT_ENABLE_R ), 97 I830_READ16(I830REG_INT_ENABLE_R),
101 I830_READ16( I830REG_HWSTAM )); 98 I830_READ16(I830REG_HWSTAM));
102 99
103 ret = -EBUSY; /* Lockup? Missed irq? */ 100 ret = -EBUSY; /* Lockup? Missed irq? */
104 break; 101 break;
105 } 102 }
106 schedule_timeout(HZ*3); 103 schedule_timeout(HZ * 3);
107 if (signal_pending(current)) { 104 if (signal_pending(current)) {
108 ret = -EINTR; 105 ret = -EINTR;
109 break; 106 break;
110 } 107 }
111 } 108 }
@@ -115,89 +112,87 @@ static int i830_wait_irq(drm_device_t *dev, int irq_nr)
115 return ret; 112 return ret;
116} 113}
117 114
118
119/* Needs the lock as it touches the ring. 115/* Needs the lock as it touches the ring.
120 */ 116 */
121int i830_irq_emit( struct inode *inode, struct file *filp, unsigned int cmd, 117int i830_irq_emit(struct inode *inode, struct file *filp, unsigned int cmd,
122 unsigned long arg ) 118 unsigned long arg)
123{ 119{
124 drm_file_t *priv = filp->private_data; 120 drm_file_t *priv = filp->private_data;
125 drm_device_t *dev = priv->head->dev; 121 drm_device_t *dev = priv->head->dev;
126 drm_i830_private_t *dev_priv = dev->dev_private; 122 drm_i830_private_t *dev_priv = dev->dev_private;
127 drm_i830_irq_emit_t emit; 123 drm_i830_irq_emit_t emit;
128 int result; 124 int result;
129 125
130 LOCK_TEST_WITH_RETURN(dev, filp); 126 LOCK_TEST_WITH_RETURN(dev, filp);
131 127
132 if ( !dev_priv ) { 128 if (!dev_priv) {
133 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 129 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
134 return -EINVAL; 130 return -EINVAL;
135 } 131 }
136 132
137 if (copy_from_user( &emit, (drm_i830_irq_emit_t __user *)arg, sizeof(emit) )) 133 if (copy_from_user
134 (&emit, (drm_i830_irq_emit_t __user *) arg, sizeof(emit)))
138 return -EFAULT; 135 return -EFAULT;
139 136
140 result = i830_emit_irq( dev ); 137 result = i830_emit_irq(dev);
141 138
142 if ( copy_to_user( emit.irq_seq, &result, sizeof(int) ) ) { 139 if (copy_to_user(emit.irq_seq, &result, sizeof(int))) {
143 DRM_ERROR( "copy_to_user\n" ); 140 DRM_ERROR("copy_to_user\n");
144 return -EFAULT; 141 return -EFAULT;
145 } 142 }
146 143
147 return 0; 144 return 0;
148} 145}
149 146
150
151/* Doesn't need the hardware lock. 147/* Doesn't need the hardware lock.
152 */ 148 */
153int i830_irq_wait( struct inode *inode, struct file *filp, unsigned int cmd, 149int i830_irq_wait(struct inode *inode, struct file *filp, unsigned int cmd,
154 unsigned long arg ) 150 unsigned long arg)
155{ 151{
156 drm_file_t *priv = filp->private_data; 152 drm_file_t *priv = filp->private_data;
157 drm_device_t *dev = priv->head->dev; 153 drm_device_t *dev = priv->head->dev;
158 drm_i830_private_t *dev_priv = dev->dev_private; 154 drm_i830_private_t *dev_priv = dev->dev_private;
159 drm_i830_irq_wait_t irqwait; 155 drm_i830_irq_wait_t irqwait;
160 156
161 if ( !dev_priv ) { 157 if (!dev_priv) {
162 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 158 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
163 return -EINVAL; 159 return -EINVAL;
164 } 160 }
165 161
166 if (copy_from_user( &irqwait, (drm_i830_irq_wait_t __user *)arg, 162 if (copy_from_user(&irqwait, (drm_i830_irq_wait_t __user *) arg,
167 sizeof(irqwait) )) 163 sizeof(irqwait)))
168 return -EFAULT; 164 return -EFAULT;
169 165
170 return i830_wait_irq( dev, irqwait.irq_seq ); 166 return i830_wait_irq(dev, irqwait.irq_seq);
171} 167}
172 168
173
174/* drm_dma.h hooks 169/* drm_dma.h hooks
175*/ 170*/
176void i830_driver_irq_preinstall( drm_device_t *dev ) { 171void i830_driver_irq_preinstall(drm_device_t * dev)
177 drm_i830_private_t *dev_priv = 172{
178 (drm_i830_private_t *)dev->dev_private; 173 drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
179 174
180 I830_WRITE16( I830REG_HWSTAM, 0xffff ); 175 I830_WRITE16(I830REG_HWSTAM, 0xffff);
181 I830_WRITE16( I830REG_INT_MASK_R, 0x0 ); 176 I830_WRITE16(I830REG_INT_MASK_R, 0x0);
182 I830_WRITE16( I830REG_INT_ENABLE_R, 0x0 ); 177 I830_WRITE16(I830REG_INT_ENABLE_R, 0x0);
183 atomic_set(&dev_priv->irq_received, 0); 178 atomic_set(&dev_priv->irq_received, 0);
184 atomic_set(&dev_priv->irq_emitted, 0); 179 atomic_set(&dev_priv->irq_emitted, 0);
185 init_waitqueue_head(&dev_priv->irq_queue); 180 init_waitqueue_head(&dev_priv->irq_queue);
186} 181}
187 182
188void i830_driver_irq_postinstall( drm_device_t *dev ) { 183void i830_driver_irq_postinstall(drm_device_t * dev)
189 drm_i830_private_t *dev_priv = 184{
190 (drm_i830_private_t *)dev->dev_private; 185 drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
191 186
192 I830_WRITE16( I830REG_INT_ENABLE_R, 0x2 ); 187 I830_WRITE16(I830REG_INT_ENABLE_R, 0x2);
193} 188}
194 189
195void i830_driver_irq_uninstall( drm_device_t *dev ) { 190void i830_driver_irq_uninstall(drm_device_t * dev)
196 drm_i830_private_t *dev_priv = 191{
197 (drm_i830_private_t *)dev->dev_private; 192 drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
198 if (!dev_priv) 193 if (!dev_priv)
199 return; 194 return;
200 195
201 I830_WRITE16( I830REG_INT_MASK_R, 0xffff ); 196 I830_WRITE16(I830REG_INT_MASK_R, 0xffff);
202 I830_WRITE16( I830REG_INT_ENABLE_R, 0x0 ); 197 I830_WRITE16(I830REG_INT_ENABLE_R, 0x0);
203} 198}
diff --git a/drivers/char/drm/i915_dma.c b/drivers/char/drm/i915_dma.c
index 34f552f90c4a..f0bb0bdbb6e2 100644
--- a/drivers/char/drm/i915_dma.c
+++ b/drivers/char/drm/i915_dma.c
@@ -85,14 +85,14 @@ static int i915_dma_cleanup(drm_device_t * dev)
85 * is freed, it's too late. 85 * is freed, it's too late.
86 */ 86 */
87 if (dev->irq) 87 if (dev->irq)
88 drm_irq_uninstall (dev); 88 drm_irq_uninstall(dev);
89 89
90 if (dev->dev_private) { 90 if (dev->dev_private) {
91 drm_i915_private_t *dev_priv = 91 drm_i915_private_t *dev_priv =
92 (drm_i915_private_t *) dev->dev_private; 92 (drm_i915_private_t *) dev->dev_private;
93 93
94 if (dev_priv->ring.virtual_start) { 94 if (dev_priv->ring.virtual_start) {
95 drm_core_ioremapfree( &dev_priv->ring.map, dev); 95 drm_core_ioremapfree(&dev_priv->ring.map, dev);
96 } 96 }
97 97
98 if (dev_priv->status_page_dmah) { 98 if (dev_priv->status_page_dmah) {
@@ -101,8 +101,8 @@ static int i915_dma_cleanup(drm_device_t * dev)
101 I915_WRITE(0x02080, 0x1ffff000); 101 I915_WRITE(0x02080, 0x1ffff000);
102 } 102 }
103 103
104 drm_free (dev->dev_private, sizeof(drm_i915_private_t), 104 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
105 DRM_MEM_DRIVER); 105 DRM_MEM_DRIVER);
106 106
107 dev->dev_private = NULL; 107 dev->dev_private = NULL;
108 } 108 }
@@ -146,7 +146,7 @@ static int i915_initialize(drm_device_t * dev,
146 dev_priv->ring.map.flags = 0; 146 dev_priv->ring.map.flags = 0;
147 dev_priv->ring.map.mtrr = 0; 147 dev_priv->ring.map.mtrr = 0;
148 148
149 drm_core_ioremap( &dev_priv->ring.map, dev ); 149 drm_core_ioremap(&dev_priv->ring.map, dev);
150 150
151 if (dev_priv->ring.map.handle == NULL) { 151 if (dev_priv->ring.map.handle == NULL) {
152 dev->dev_private = (void *)dev_priv; 152 dev->dev_private = (void *)dev_priv;
@@ -243,8 +243,8 @@ static int i915_dma_init(DRM_IOCTL_ARGS)
243 243
244 switch (init.func) { 244 switch (init.func) {
245 case I915_INIT_DMA: 245 case I915_INIT_DMA:
246 dev_priv = drm_alloc (sizeof(drm_i915_private_t), 246 dev_priv = drm_alloc(sizeof(drm_i915_private_t),
247 DRM_MEM_DRIVER); 247 DRM_MEM_DRIVER);
248 if (dev_priv == NULL) 248 if (dev_priv == NULL)
249 return DRM_ERR(ENOMEM); 249 return DRM_ERR(ENOMEM);
250 retcode = i915_initialize(dev, dev_priv, &init); 250 retcode = i915_initialize(dev, dev_priv, &init);
@@ -297,7 +297,7 @@ static int do_validate_cmd(int cmd)
297 case 0x1c: 297 case 0x1c:
298 return 1; 298 return 1;
299 case 0x1d: 299 case 0x1d:
300 switch ((cmd>>16)&0xff) { 300 switch ((cmd >> 16) & 0xff) {
301 case 0x3: 301 case 0x3:
302 return (cmd & 0x1f) + 2; 302 return (cmd & 0x1f) + 2;
303 case 0x4: 303 case 0x4:
@@ -699,35 +699,46 @@ static int i915_setparam(DRM_IOCTL_ARGS)
699 return 0; 699 return 0;
700} 700}
701 701
702void i915_driver_pretakedown(drm_device_t *dev) 702void i915_driver_pretakedown(drm_device_t * dev)
703{ 703{
704 if ( dev->dev_private ) { 704 if (dev->dev_private) {
705 drm_i915_private_t *dev_priv = dev->dev_private; 705 drm_i915_private_t *dev_priv = dev->dev_private;
706 i915_mem_takedown( &(dev_priv->agp_heap) ); 706 i915_mem_takedown(&(dev_priv->agp_heap));
707 } 707 }
708 i915_dma_cleanup( dev ); 708 i915_dma_cleanup(dev);
709} 709}
710 710
711void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp) 711void i915_driver_prerelease(drm_device_t * dev, DRMFILE filp)
712{ 712{
713 if ( dev->dev_private ) { 713 if (dev->dev_private) {
714 drm_i915_private_t *dev_priv = dev->dev_private; 714 drm_i915_private_t *dev_priv = dev->dev_private;
715 i915_mem_release( dev, filp, dev_priv->agp_heap ); 715 i915_mem_release(dev, filp, dev_priv->agp_heap);
716 } 716 }
717} 717}
718 718
719drm_ioctl_desc_t i915_ioctls[] = { 719drm_ioctl_desc_t i915_ioctls[] = {
720 [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, 1, 1}, 720 [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, 1, 1}
721 [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, 1, 0}, 721 ,
722 [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, 1, 0}, 722 [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, 1, 0}
723 [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, 1, 0}, 723 ,
724 [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, 1, 0}, 724 [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, 1, 0}
725 [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, 1, 0}, 725 ,
726 [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, 1, 0}, 726 [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, 1, 0}
727 [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, 1, 1}, 727 ,
728 [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, 1, 0}, 728 [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, 1, 0}
729 [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, 1, 0}, 729 ,
730 [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, 1, 1}, 730 [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, 1, 0}
731 ,
732 [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, 1, 0}
733 ,
734 [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, 1, 1}
735 ,
736 [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, 1, 0}
737 ,
738 [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, 1, 0}
739 ,
740 [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, 1, 1}
741 ,
731 [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, 1, 0} 742 [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, 1, 0}
732}; 743};
733 744
diff --git a/drivers/char/drm/i915_drv.c b/drivers/char/drm/i915_drv.c
index 106b9ec02213..665da6ac11c6 100644
--- a/drivers/char/drm/i915_drv.c
+++ b/drivers/char/drm/i915_drv.c
@@ -34,36 +34,34 @@
34 34
35#include "drm_pciids.h" 35#include "drm_pciids.h"
36 36
37static int postinit( struct drm_device *dev, unsigned long flags ) 37static int postinit(struct drm_device *dev, unsigned long flags)
38{ 38{
39 dev->counters += 4; 39 dev->counters += 4;
40 dev->types[6] = _DRM_STAT_IRQ; 40 dev->types[6] = _DRM_STAT_IRQ;
41 dev->types[7] = _DRM_STAT_PRIMARY; 41 dev->types[7] = _DRM_STAT_PRIMARY;
42 dev->types[8] = _DRM_STAT_SECONDARY; 42 dev->types[8] = _DRM_STAT_SECONDARY;
43 dev->types[9] = _DRM_STAT_DMA; 43 dev->types[9] = _DRM_STAT_DMA;
44 44
45 DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", 45 DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n",
46 DRIVER_NAME, 46 DRIVER_NAME,
47 DRIVER_MAJOR, 47 DRIVER_MAJOR,
48 DRIVER_MINOR, 48 DRIVER_MINOR,
49 DRIVER_PATCHLEVEL, 49 DRIVER_PATCHLEVEL,
50 DRIVER_DATE, 50 DRIVER_DATE, dev->primary.minor, pci_pretty_name(dev->pdev)
51 dev->primary.minor, 51 );
52 pci_pretty_name(dev->pdev)
53 );
54 return 0; 52 return 0;
55} 53}
56 54
57static int version( drm_version_t *version ) 55static int version(drm_version_t * version)
58{ 56{
59 int len; 57 int len;
60 58
61 version->version_major = DRIVER_MAJOR; 59 version->version_major = DRIVER_MAJOR;
62 version->version_minor = DRIVER_MINOR; 60 version->version_minor = DRIVER_MINOR;
63 version->version_patchlevel = DRIVER_PATCHLEVEL; 61 version->version_patchlevel = DRIVER_PATCHLEVEL;
64 DRM_COPY( version->name, DRIVER_NAME ); 62 DRM_COPY(version->name, DRIVER_NAME);
65 DRM_COPY( version->date, DRIVER_DATE ); 63 DRM_COPY(version->date, DRIVER_DATE);
66 DRM_COPY( version->desc, DRIVER_DESC ); 64 DRM_COPY(version->desc, DRIVER_DESC);
67 return 0; 65 return 0;
68} 66}
69 67
@@ -75,8 +73,9 @@ extern drm_ioctl_desc_t i915_ioctls[];
75extern int i915_max_ioctl; 73extern int i915_max_ioctl;
76 74
77static struct drm_driver driver = { 75static struct drm_driver driver = {
78 .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | 76 .driver_features =
79 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED, 77 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR |
78 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED,
80 .pretakedown = i915_driver_pretakedown, 79 .pretakedown = i915_driver_pretakedown,
81 .prerelease = i915_driver_prerelease, 80 .prerelease = i915_driver_prerelease,
82 .device_is_agp = i915_driver_device_is_agp, 81 .device_is_agp = i915_driver_device_is_agp,
@@ -91,21 +90,21 @@ static struct drm_driver driver = {
91 .version = version, 90 .version = version,
92 .ioctls = i915_ioctls, 91 .ioctls = i915_ioctls,
93 .fops = { 92 .fops = {
94 .owner = THIS_MODULE, 93 .owner = THIS_MODULE,
95 .open = drm_open, 94 .open = drm_open,
96 .release = drm_release, 95 .release = drm_release,
97 .ioctl = drm_ioctl, 96 .ioctl = drm_ioctl,
98 .mmap = drm_mmap, 97 .mmap = drm_mmap,
99 .poll = drm_poll, 98 .poll = drm_poll,
100 .fasync = drm_fasync, 99 .fasync = drm_fasync,
101#ifdef CONFIG_COMPAT 100#ifdef CONFIG_COMPAT
102 .compat_ioctl = i915_compat_ioctl, 101 .compat_ioctl = i915_compat_ioctl,
103#endif 102#endif
104 }, 103 },
105 .pci_driver = { 104 .pci_driver = {
106 .name = DRIVER_NAME, 105 .name = DRIVER_NAME,
107 .id_table = pciidlist, 106 .id_table = pciidlist,
108 } 107 }
109}; 108};
110 109
111static int __init i915_init(void) 110static int __init i915_init(void)
@@ -122,6 +121,6 @@ static void __exit i915_exit(void)
122module_init(i915_init); 121module_init(i915_init);
123module_exit(i915_exit); 122module_exit(i915_exit);
124 123
125MODULE_AUTHOR( DRIVER_AUTHOR ); 124MODULE_AUTHOR(DRIVER_AUTHOR);
126MODULE_DESCRIPTION( DRIVER_DESC ); 125MODULE_DESCRIPTION(DRIVER_DESC);
127MODULE_LICENSE("GPL and additional rights"); 126MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/char/drm/i915_drv.h b/drivers/char/drm/i915_drv.h
index 70ed4e68eac8..511ef1d87637 100644
--- a/drivers/char/drm/i915_drv.h
+++ b/drivers/char/drm/i915_drv.h
@@ -101,18 +101,18 @@ typedef struct drm_i915_private {
101 101
102 /* i915_dma.c */ 102 /* i915_dma.c */
103extern void i915_kernel_lost_context(drm_device_t * dev); 103extern void i915_kernel_lost_context(drm_device_t * dev);
104extern void i915_driver_pretakedown(drm_device_t *dev); 104extern void i915_driver_pretakedown(drm_device_t * dev);
105extern void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp); 105extern void i915_driver_prerelease(drm_device_t * dev, DRMFILE filp);
106extern int i915_driver_device_is_agp(drm_device_t *dev); 106extern int i915_driver_device_is_agp(drm_device_t * dev);
107 107
108/* i915_irq.c */ 108/* i915_irq.c */
109extern int i915_irq_emit(DRM_IOCTL_ARGS); 109extern int i915_irq_emit(DRM_IOCTL_ARGS);
110extern int i915_irq_wait(DRM_IOCTL_ARGS); 110extern int i915_irq_wait(DRM_IOCTL_ARGS);
111 111
112extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 112extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
113extern void i915_driver_irq_preinstall(drm_device_t *dev); 113extern void i915_driver_irq_preinstall(drm_device_t * dev);
114extern void i915_driver_irq_postinstall(drm_device_t *dev); 114extern void i915_driver_irq_postinstall(drm_device_t * dev);
115extern void i915_driver_irq_uninstall(drm_device_t *dev); 115extern void i915_driver_irq_uninstall(drm_device_t * dev);
116 116
117/* i915_mem.c */ 117/* i915_mem.c */
118extern int i915_mem_alloc(DRM_IOCTL_ARGS); 118extern int i915_mem_alloc(DRM_IOCTL_ARGS);
@@ -125,7 +125,6 @@ extern void i915_mem_release(drm_device_t * dev,
125extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 125extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
126 unsigned long arg); 126 unsigned long arg);
127 127
128
129#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, reg) 128#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, reg)
130#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, reg, val) 129#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, reg, val)
131#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, reg) 130#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, reg)
diff --git a/drivers/char/drm/i915_ioc32.c b/drivers/char/drm/i915_ioc32.c
index fe009e1b3a3f..2218a946ec87 100644
--- a/drivers/char/drm/i915_ioc32.c
+++ b/drivers/char/drm/i915_ioc32.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * 32-bit ioctl compatibility routines for the i915 DRM. 4 * 32-bit ioctl compatibility routines for the i915 DRM.
5 * 5 *
6 * \author Alan Hourihane <alanh@fairlite.demon.co.uk> 6 * \author Alan Hourihane <alanh@fairlite.demon.co.uk>
7 * 7 *
8 * 8 *
9 * Copyright (C) Paul Mackerras 2005 9 * Copyright (C) Paul Mackerras 2005
@@ -42,51 +42,55 @@ typedef struct _drm_i915_batchbuffer32 {
42 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 42 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
43 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 43 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
44 int num_cliprects; /* mulitpass with multiple cliprects? */ 44 int num_cliprects; /* mulitpass with multiple cliprects? */
45 u32 cliprects; /* pointer to userspace cliprects */ 45 u32 cliprects; /* pointer to userspace cliprects */
46} drm_i915_batchbuffer32_t; 46} drm_i915_batchbuffer32_t;
47 47
48static int compat_i915_batchbuffer(struct file *file, unsigned int cmd, 48static int compat_i915_batchbuffer(struct file *file, unsigned int cmd,
49 unsigned long arg) 49 unsigned long arg)
50{ 50{
51 drm_i915_batchbuffer32_t batchbuffer32; 51 drm_i915_batchbuffer32_t batchbuffer32;
52 drm_i915_batchbuffer_t __user *batchbuffer; 52 drm_i915_batchbuffer_t __user *batchbuffer;
53 53
54 if (copy_from_user(&batchbuffer32, (void __user *)arg, sizeof(batchbuffer32))) 54 if (copy_from_user
55 (&batchbuffer32, (void __user *)arg, sizeof(batchbuffer32)))
55 return -EFAULT; 56 return -EFAULT;
56 57
57 batchbuffer = compat_alloc_user_space(sizeof(*batchbuffer)); 58 batchbuffer = compat_alloc_user_space(sizeof(*batchbuffer));
58 if (!access_ok(VERIFY_WRITE, batchbuffer, sizeof(*batchbuffer)) 59 if (!access_ok(VERIFY_WRITE, batchbuffer, sizeof(*batchbuffer))
59 || __put_user(batchbuffer32.start, &batchbuffer->start) 60 || __put_user(batchbuffer32.start, &batchbuffer->start)
60 || __put_user(batchbuffer32.used, &batchbuffer->used) 61 || __put_user(batchbuffer32.used, &batchbuffer->used)
61 || __put_user(batchbuffer32.DR1, &batchbuffer->DR1) 62 || __put_user(batchbuffer32.DR1, &batchbuffer->DR1)
62 || __put_user(batchbuffer32.DR4, &batchbuffer->DR4) 63 || __put_user(batchbuffer32.DR4, &batchbuffer->DR4)
63 || __put_user(batchbuffer32.num_cliprects, &batchbuffer->num_cliprects) 64 || __put_user(batchbuffer32.num_cliprects,
65 &batchbuffer->num_cliprects)
64 || __put_user((int __user *)(unsigned long)batchbuffer32.cliprects, 66 || __put_user((int __user *)(unsigned long)batchbuffer32.cliprects,
65 &batchbuffer->cliprects)) 67 &batchbuffer->cliprects))
66 return -EFAULT; 68 return -EFAULT;
67 69
68 return drm_ioctl(file->f_dentry->d_inode, file, 70 return drm_ioctl(file->f_dentry->d_inode, file,
69 DRM_IOCTL_I915_BATCHBUFFER, (unsigned long) batchbuffer); 71 DRM_IOCTL_I915_BATCHBUFFER,
72 (unsigned long)batchbuffer);
70} 73}
71 74
72typedef struct _drm_i915_cmdbuffer32 { 75typedef struct _drm_i915_cmdbuffer32 {
73 u32 buf; /* pointer to userspace command buffer */ 76 u32 buf; /* pointer to userspace command buffer */
74 int sz; /* nr bytes in buf */ 77 int sz; /* nr bytes in buf */
75 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 78 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
76 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 79 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
77 int num_cliprects; /* mulitpass with multiple cliprects? */ 80 int num_cliprects; /* mulitpass with multiple cliprects? */
78 u32 cliprects; /* pointer to userspace cliprects */ 81 u32 cliprects; /* pointer to userspace cliprects */
79} drm_i915_cmdbuffer32_t; 82} drm_i915_cmdbuffer32_t;
80 83
81static int compat_i915_cmdbuffer(struct file *file, unsigned int cmd, 84static int compat_i915_cmdbuffer(struct file *file, unsigned int cmd,
82 unsigned long arg) 85 unsigned long arg)
83{ 86{
84 drm_i915_cmdbuffer32_t cmdbuffer32; 87 drm_i915_cmdbuffer32_t cmdbuffer32;
85 drm_i915_cmdbuffer_t __user *cmdbuffer; 88 drm_i915_cmdbuffer_t __user *cmdbuffer;
86 89
87 if (copy_from_user(&cmdbuffer32, (void __user *)arg, sizeof(cmdbuffer32))) 90 if (copy_from_user
91 (&cmdbuffer32, (void __user *)arg, sizeof(cmdbuffer32)))
88 return -EFAULT; 92 return -EFAULT;
89 93
90 cmdbuffer = compat_alloc_user_space(sizeof(*cmdbuffer)); 94 cmdbuffer = compat_alloc_user_space(sizeof(*cmdbuffer));
91 if (!access_ok(VERIFY_WRITE, cmdbuffer, sizeof(*cmdbuffer)) 95 if (!access_ok(VERIFY_WRITE, cmdbuffer, sizeof(*cmdbuffer))
92 || __put_user((int __user *)(unsigned long)cmdbuffer32.buf, 96 || __put_user((int __user *)(unsigned long)cmdbuffer32.buf,
@@ -98,9 +102,9 @@ static int compat_i915_cmdbuffer(struct file *file, unsigned int cmd,
98 || __put_user((int __user *)(unsigned long)cmdbuffer32.cliprects, 102 || __put_user((int __user *)(unsigned long)cmdbuffer32.cliprects,
99 &cmdbuffer->cliprects)) 103 &cmdbuffer->cliprects))
100 return -EFAULT; 104 return -EFAULT;
101 105
102 return drm_ioctl(file->f_dentry->d_inode, file, 106 return drm_ioctl(file->f_dentry->d_inode, file,
103 DRM_IOCTL_I915_CMDBUFFER, (unsigned long) cmdbuffer); 107 DRM_IOCTL_I915_CMDBUFFER, (unsigned long)cmdbuffer);
104} 108}
105 109
106typedef struct drm_i915_irq_emit32 { 110typedef struct drm_i915_irq_emit32 {
@@ -108,12 +112,12 @@ typedef struct drm_i915_irq_emit32 {
108} drm_i915_irq_emit32_t; 112} drm_i915_irq_emit32_t;
109 113
110static int compat_i915_irq_emit(struct file *file, unsigned int cmd, 114static int compat_i915_irq_emit(struct file *file, unsigned int cmd,
111 unsigned long arg) 115 unsigned long arg)
112{ 116{
113 drm_i915_irq_emit32_t req32; 117 drm_i915_irq_emit32_t req32;
114 drm_i915_irq_emit_t __user *request; 118 drm_i915_irq_emit_t __user *request;
115 119
116 if (copy_from_user(&req32, (void __user *) arg, sizeof(req32))) 120 if (copy_from_user(&req32, (void __user *)arg, sizeof(req32)))
117 return -EFAULT; 121 return -EFAULT;
118 122
119 request = compat_alloc_user_space(sizeof(*request)); 123 request = compat_alloc_user_space(sizeof(*request));
@@ -123,7 +127,7 @@ static int compat_i915_irq_emit(struct file *file, unsigned int cmd,
123 return -EFAULT; 127 return -EFAULT;
124 128
125 return drm_ioctl(file->f_dentry->d_inode, file, 129 return drm_ioctl(file->f_dentry->d_inode, file,
126 DRM_IOCTL_I915_IRQ_EMIT, (unsigned long) request); 130 DRM_IOCTL_I915_IRQ_EMIT, (unsigned long)request);
127} 131}
128typedef struct drm_i915_getparam32 { 132typedef struct drm_i915_getparam32 {
129 int param; 133 int param;
@@ -131,12 +135,12 @@ typedef struct drm_i915_getparam32 {
131} drm_i915_getparam32_t; 135} drm_i915_getparam32_t;
132 136
133static int compat_i915_getparam(struct file *file, unsigned int cmd, 137static int compat_i915_getparam(struct file *file, unsigned int cmd,
134 unsigned long arg) 138 unsigned long arg)
135{ 139{
136 drm_i915_getparam32_t req32; 140 drm_i915_getparam32_t req32;
137 drm_i915_getparam_t __user *request; 141 drm_i915_getparam_t __user *request;
138 142
139 if (copy_from_user(&req32, (void __user *) arg, sizeof(req32))) 143 if (copy_from_user(&req32, (void __user *)arg, sizeof(req32)))
140 return -EFAULT; 144 return -EFAULT;
141 145
142 request = compat_alloc_user_space(sizeof(*request)); 146 request = compat_alloc_user_space(sizeof(*request));
@@ -147,7 +151,7 @@ static int compat_i915_getparam(struct file *file, unsigned int cmd,
147 return -EFAULT; 151 return -EFAULT;
148 152
149 return drm_ioctl(file->f_dentry->d_inode, file, 153 return drm_ioctl(file->f_dentry->d_inode, file,
150 DRM_IOCTL_I915_GETPARAM, (unsigned long) request); 154 DRM_IOCTL_I915_GETPARAM, (unsigned long)request);
151} 155}
152 156
153typedef struct drm_i915_mem_alloc32 { 157typedef struct drm_i915_mem_alloc32 {
@@ -158,12 +162,12 @@ typedef struct drm_i915_mem_alloc32 {
158} drm_i915_mem_alloc32_t; 162} drm_i915_mem_alloc32_t;
159 163
160static int compat_i915_alloc(struct file *file, unsigned int cmd, 164static int compat_i915_alloc(struct file *file, unsigned int cmd,
161 unsigned long arg) 165 unsigned long arg)
162{ 166{
163 drm_i915_mem_alloc32_t req32; 167 drm_i915_mem_alloc32_t req32;
164 drm_i915_mem_alloc_t __user *request; 168 drm_i915_mem_alloc_t __user *request;
165 169
166 if (copy_from_user(&req32, (void __user *) arg, sizeof(req32))) 170 if (copy_from_user(&req32, (void __user *)arg, sizeof(req32)))
167 return -EFAULT; 171 return -EFAULT;
168 172
169 request = compat_alloc_user_space(sizeof(*request)); 173 request = compat_alloc_user_space(sizeof(*request));
@@ -176,10 +180,9 @@ static int compat_i915_alloc(struct file *file, unsigned int cmd,
176 return -EFAULT; 180 return -EFAULT;
177 181
178 return drm_ioctl(file->f_dentry->d_inode, file, 182 return drm_ioctl(file->f_dentry->d_inode, file,
179 DRM_IOCTL_I915_ALLOC, (unsigned long) request); 183 DRM_IOCTL_I915_ALLOC, (unsigned long)request);
180} 184}
181 185
182
183drm_ioctl_compat_t *i915_compat_ioctls[] = { 186drm_ioctl_compat_t *i915_compat_ioctls[] = {
184 [DRM_I915_BATCHBUFFER] = compat_i915_batchbuffer, 187 [DRM_I915_BATCHBUFFER] = compat_i915_batchbuffer,
185 [DRM_I915_CMDBUFFER] = compat_i915_cmdbuffer, 188 [DRM_I915_CMDBUFFER] = compat_i915_cmdbuffer,
@@ -197,8 +200,7 @@ drm_ioctl_compat_t *i915_compat_ioctls[] = {
197 * \param arg user argument. 200 * \param arg user argument.
198 * \return zero on success or negative number on failure. 201 * \return zero on success or negative number on failure.
199 */ 202 */
200long i915_compat_ioctl(struct file *filp, unsigned int cmd, 203long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
201 unsigned long arg)
202{ 204{
203 unsigned int nr = DRM_IOCTL_NR(cmd); 205 unsigned int nr = DRM_IOCTL_NR(cmd);
204 drm_ioctl_compat_t *fn = NULL; 206 drm_ioctl_compat_t *fn = NULL;
@@ -206,13 +208,13 @@ long i915_compat_ioctl(struct file *filp, unsigned int cmd,
206 208
207 if (nr < DRM_COMMAND_BASE) 209 if (nr < DRM_COMMAND_BASE)
208 return drm_compat_ioctl(filp, cmd, arg); 210 return drm_compat_ioctl(filp, cmd, arg);
209 211
210 if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(i915_compat_ioctls)) 212 if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(i915_compat_ioctls))
211 fn = i915_compat_ioctls[nr - DRM_COMMAND_BASE]; 213 fn = i915_compat_ioctls[nr - DRM_COMMAND_BASE];
212 214
213 lock_kernel(); /* XXX for now */ 215 lock_kernel(); /* XXX for now */
214 if (fn != NULL) 216 if (fn != NULL)
215 ret = (*fn)(filp, cmd, arg); 217 ret = (*fn) (filp, cmd, arg);
216 else 218 else
217 ret = drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg); 219 ret = drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg);
218 unlock_kernel(); 220 unlock_kernel();
diff --git a/drivers/char/drm/i915_mem.c b/drivers/char/drm/i915_mem.c
index 9b1698f521be..13176d136a99 100644
--- a/drivers/char/drm/i915_mem.c
+++ b/drivers/char/drm/i915_mem.c
@@ -86,7 +86,7 @@ static void mark_block(drm_device_t * dev, struct mem_block *p, int in_use)
86} 86}
87 87
88/* Very simple allocator for agp memory, working on a static range 88/* Very simple allocator for agp memory, working on a static range
89 * already mapped into each client's address space. 89 * already mapped into each client's address space.
90 */ 90 */
91 91
92static struct mem_block *split_block(struct mem_block *p, int start, int size, 92static struct mem_block *split_block(struct mem_block *p, int start, int size,
@@ -94,7 +94,8 @@ static struct mem_block *split_block(struct mem_block *p, int start, int size,
94{ 94{
95 /* Maybe cut off the start of an existing block */ 95 /* Maybe cut off the start of an existing block */
96 if (start > p->start) { 96 if (start > p->start) {
97 struct mem_block *newblock = drm_alloc(sizeof(*newblock), DRM_MEM_BUFLISTS); 97 struct mem_block *newblock =
98 drm_alloc(sizeof(*newblock), DRM_MEM_BUFLISTS);
98 if (!newblock) 99 if (!newblock)
99 goto out; 100 goto out;
100 newblock->start = start; 101 newblock->start = start;
@@ -110,7 +111,8 @@ static struct mem_block *split_block(struct mem_block *p, int start, int size,
110 111
111 /* Maybe cut off the end of an existing block */ 112 /* Maybe cut off the end of an existing block */
112 if (size < p->size) { 113 if (size < p->size) {
113 struct mem_block *newblock = drm_alloc(sizeof(*newblock), DRM_MEM_BUFLISTS); 114 struct mem_block *newblock =
115 drm_alloc(sizeof(*newblock), DRM_MEM_BUFLISTS);
114 if (!newblock) 116 if (!newblock)
115 goto out; 117 goto out;
116 newblock->start = start + size; 118 newblock->start = start + size;
diff --git a/drivers/char/drm/mga_dma.c b/drivers/char/drm/mga_dma.c
index fc7d4a594bca..cfbe35d5d862 100644
--- a/drivers/char/drm/mga_dma.c
+++ b/drivers/char/drm/mga_dma.c
@@ -28,7 +28,7 @@
28/** 28/**
29 * \file mga_dma.c 29 * \file mga_dma.c
30 * DMA support for MGA G200 / G400. 30 * DMA support for MGA G200 / G400.
31 * 31 *
32 * \author Rickard E. (Rik) Faith <faith@valinux.com> 32 * \author Rickard E. (Rik) Faith <faith@valinux.com>
33 * \author Jeff Hartmann <jhartmann@valinux.com> 33 * \author Jeff Hartmann <jhartmann@valinux.com>
34 * \author Keith Whitwell <keith@tungstengraphics.com> 34 * \author Keith Whitwell <keith@tungstengraphics.com>
@@ -44,40 +44,40 @@
44#define MGA_DEFAULT_USEC_TIMEOUT 10000 44#define MGA_DEFAULT_USEC_TIMEOUT 10000
45#define MGA_FREELIST_DEBUG 0 45#define MGA_FREELIST_DEBUG 0
46 46
47static int mga_do_cleanup_dma( drm_device_t *dev ); 47static int mga_do_cleanup_dma(drm_device_t * dev);
48 48
49/* ================================================================ 49/* ================================================================
50 * Engine control 50 * Engine control
51 */ 51 */
52 52
53int mga_do_wait_for_idle( drm_mga_private_t *dev_priv ) 53int mga_do_wait_for_idle(drm_mga_private_t * dev_priv)
54{ 54{
55 u32 status = 0; 55 u32 status = 0;
56 int i; 56 int i;
57 DRM_DEBUG( "\n" ); 57 DRM_DEBUG("\n");
58 58
59 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 59 for (i = 0; i < dev_priv->usec_timeout; i++) {
60 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; 60 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
61 if ( status == MGA_ENDPRDMASTS ) { 61 if (status == MGA_ENDPRDMASTS) {
62 MGA_WRITE8( MGA_CRTC_INDEX, 0 ); 62 MGA_WRITE8(MGA_CRTC_INDEX, 0);
63 return 0; 63 return 0;
64 } 64 }
65 DRM_UDELAY( 1 ); 65 DRM_UDELAY(1);
66 } 66 }
67 67
68#if MGA_DMA_DEBUG 68#if MGA_DMA_DEBUG
69 DRM_ERROR( "failed!\n" ); 69 DRM_ERROR("failed!\n");
70 DRM_INFO( " status=0x%08x\n", status ); 70 DRM_INFO(" status=0x%08x\n", status);
71#endif 71#endif
72 return DRM_ERR(EBUSY); 72 return DRM_ERR(EBUSY);
73} 73}
74 74
75static int mga_do_dma_reset( drm_mga_private_t *dev_priv ) 75static int mga_do_dma_reset(drm_mga_private_t * dev_priv)
76{ 76{
77 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 77 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
78 drm_mga_primary_buffer_t *primary = &dev_priv->prim; 78 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
79 79
80 DRM_DEBUG( "\n" ); 80 DRM_DEBUG("\n");
81 81
82 /* The primary DMA stream should look like new right about now. 82 /* The primary DMA stream should look like new right about now.
83 */ 83 */
@@ -100,24 +100,25 @@ static int mga_do_dma_reset( drm_mga_private_t *dev_priv )
100 * Primary DMA stream 100 * Primary DMA stream
101 */ 101 */
102 102
103void mga_do_dma_flush( drm_mga_private_t *dev_priv ) 103void mga_do_dma_flush(drm_mga_private_t * dev_priv)
104{ 104{
105 drm_mga_primary_buffer_t *primary = &dev_priv->prim; 105 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
106 u32 head, tail; 106 u32 head, tail;
107 u32 status = 0; 107 u32 status = 0;
108 int i; 108 int i;
109 DMA_LOCALS; 109 DMA_LOCALS;
110 DRM_DEBUG( "\n" ); 110 DRM_DEBUG("\n");
111 111
112 /* We need to wait so that we can do an safe flush */ 112 /* We need to wait so that we can do an safe flush */
113 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 113 for (i = 0; i < dev_priv->usec_timeout; i++) {
114 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; 114 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
115 if ( status == MGA_ENDPRDMASTS ) break; 115 if (status == MGA_ENDPRDMASTS)
116 DRM_UDELAY( 1 ); 116 break;
117 DRM_UDELAY(1);
117 } 118 }
118 119
119 if ( primary->tail == primary->last_flush ) { 120 if (primary->tail == primary->last_flush) {
120 DRM_DEBUG( " bailing out...\n" ); 121 DRM_DEBUG(" bailing out...\n");
121 return; 122 return;
122 } 123 }
123 124
@@ -127,48 +128,46 @@ void mga_do_dma_flush( drm_mga_private_t *dev_priv )
127 * actually (partially?) reads the first of these commands. 128 * actually (partially?) reads the first of these commands.
128 * See page 4-16 in the G400 manual, middle of the page or so. 129 * See page 4-16 in the G400 manual, middle of the page or so.
129 */ 130 */
130 BEGIN_DMA( 1 ); 131 BEGIN_DMA(1);
131 132
132 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 133 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
133 MGA_DMAPAD, 0x00000000, 134 MGA_DMAPAD, 0x00000000,
134 MGA_DMAPAD, 0x00000000, 135 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
135 MGA_DMAPAD, 0x00000000 );
136 136
137 ADVANCE_DMA(); 137 ADVANCE_DMA();
138 138
139 primary->last_flush = primary->tail; 139 primary->last_flush = primary->tail;
140 140
141 head = MGA_READ( MGA_PRIMADDRESS ); 141 head = MGA_READ(MGA_PRIMADDRESS);
142 142
143 if ( head <= tail ) { 143 if (head <= tail) {
144 primary->space = primary->size - primary->tail; 144 primary->space = primary->size - primary->tail;
145 } else { 145 } else {
146 primary->space = head - tail; 146 primary->space = head - tail;
147 } 147 }
148 148
149 DRM_DEBUG( " head = 0x%06lx\n", head - dev_priv->primary->offset ); 149 DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset);
150 DRM_DEBUG( " tail = 0x%06lx\n", tail - dev_priv->primary->offset ); 150 DRM_DEBUG(" tail = 0x%06lx\n", tail - dev_priv->primary->offset);
151 DRM_DEBUG( " space = 0x%06x\n", primary->space ); 151 DRM_DEBUG(" space = 0x%06x\n", primary->space);
152 152
153 mga_flush_write_combine(); 153 mga_flush_write_combine();
154 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access); 154 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
155 155
156 DRM_DEBUG( "done.\n" ); 156 DRM_DEBUG("done.\n");
157} 157}
158 158
159void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv ) 159void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv)
160{ 160{
161 drm_mga_primary_buffer_t *primary = &dev_priv->prim; 161 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
162 u32 head, tail; 162 u32 head, tail;
163 DMA_LOCALS; 163 DMA_LOCALS;
164 DRM_DEBUG( "\n" ); 164 DRM_DEBUG("\n");
165 165
166 BEGIN_DMA_WRAP(); 166 BEGIN_DMA_WRAP();
167 167
168 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 168 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
169 MGA_DMAPAD, 0x00000000, 169 MGA_DMAPAD, 0x00000000,
170 MGA_DMAPAD, 0x00000000, 170 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
171 MGA_DMAPAD, 0x00000000 );
172 171
173 ADVANCE_DMA(); 172 ADVANCE_DMA();
174 173
@@ -178,45 +177,43 @@ void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv )
178 primary->last_flush = 0; 177 primary->last_flush = 0;
179 primary->last_wrap++; 178 primary->last_wrap++;
180 179
181 head = MGA_READ( MGA_PRIMADDRESS ); 180 head = MGA_READ(MGA_PRIMADDRESS);
182 181
183 if ( head == dev_priv->primary->offset ) { 182 if (head == dev_priv->primary->offset) {
184 primary->space = primary->size; 183 primary->space = primary->size;
185 } else { 184 } else {
186 primary->space = head - dev_priv->primary->offset; 185 primary->space = head - dev_priv->primary->offset;
187 } 186 }
188 187
189 DRM_DEBUG( " head = 0x%06lx\n", 188 DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset);
190 head - dev_priv->primary->offset ); 189 DRM_DEBUG(" tail = 0x%06x\n", primary->tail);
191 DRM_DEBUG( " tail = 0x%06x\n", primary->tail ); 190 DRM_DEBUG(" wrap = %d\n", primary->last_wrap);
192 DRM_DEBUG( " wrap = %d\n", primary->last_wrap ); 191 DRM_DEBUG(" space = 0x%06x\n", primary->space);
193 DRM_DEBUG( " space = 0x%06x\n", primary->space );
194 192
195 mga_flush_write_combine(); 193 mga_flush_write_combine();
196 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access); 194 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
197 195
198 set_bit( 0, &primary->wrapped ); 196 set_bit(0, &primary->wrapped);
199 DRM_DEBUG( "done.\n" ); 197 DRM_DEBUG("done.\n");
200} 198}
201 199
202void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv ) 200void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv)
203{ 201{
204 drm_mga_primary_buffer_t *primary = &dev_priv->prim; 202 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
205 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 203 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
206 u32 head = dev_priv->primary->offset; 204 u32 head = dev_priv->primary->offset;
207 DRM_DEBUG( "\n" ); 205 DRM_DEBUG("\n");
208 206
209 sarea_priv->last_wrap++; 207 sarea_priv->last_wrap++;
210 DRM_DEBUG( " wrap = %d\n", sarea_priv->last_wrap ); 208 DRM_DEBUG(" wrap = %d\n", sarea_priv->last_wrap);
211 209
212 mga_flush_write_combine(); 210 mga_flush_write_combine();
213 MGA_WRITE( MGA_PRIMADDRESS, head | MGA_DMA_GENERAL ); 211 MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL);
214 212
215 clear_bit( 0, &primary->wrapped ); 213 clear_bit(0, &primary->wrapped);
216 DRM_DEBUG( "done.\n" ); 214 DRM_DEBUG("done.\n");
217} 215}
218 216
219
220/* ================================================================ 217/* ================================================================
221 * Freelist management 218 * Freelist management
222 */ 219 */
@@ -225,63 +222,61 @@ void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv )
225#define MGA_BUFFER_FREE 0 222#define MGA_BUFFER_FREE 0
226 223
227#if MGA_FREELIST_DEBUG 224#if MGA_FREELIST_DEBUG
228static void mga_freelist_print( drm_device_t *dev ) 225static void mga_freelist_print(drm_device_t * dev)
229{ 226{
230 drm_mga_private_t *dev_priv = dev->dev_private; 227 drm_mga_private_t *dev_priv = dev->dev_private;
231 drm_mga_freelist_t *entry; 228 drm_mga_freelist_t *entry;
232 229
233 DRM_INFO( "\n" ); 230 DRM_INFO("\n");
234 DRM_INFO( "current dispatch: last=0x%x done=0x%x\n", 231 DRM_INFO("current dispatch: last=0x%x done=0x%x\n",
235 dev_priv->sarea_priv->last_dispatch, 232 dev_priv->sarea_priv->last_dispatch,
236 (unsigned int)(MGA_READ( MGA_PRIMADDRESS ) - 233 (unsigned int)(MGA_READ(MGA_PRIMADDRESS) -
237 dev_priv->primary->offset) ); 234 dev_priv->primary->offset));
238 DRM_INFO( "current freelist:\n" ); 235 DRM_INFO("current freelist:\n");
239 236
240 for ( entry = dev_priv->head->next ; entry ; entry = entry->next ) { 237 for (entry = dev_priv->head->next; entry; entry = entry->next) {
241 DRM_INFO( " %p idx=%2d age=0x%x 0x%06lx\n", 238 DRM_INFO(" %p idx=%2d age=0x%x 0x%06lx\n",
242 entry, entry->buf->idx, entry->age.head, 239 entry, entry->buf->idx, entry->age.head,
243 entry->age.head - dev_priv->primary->offset ); 240 entry->age.head - dev_priv->primary->offset);
244 } 241 }
245 DRM_INFO( "\n" ); 242 DRM_INFO("\n");
246} 243}
247#endif 244#endif
248 245
249static int mga_freelist_init( drm_device_t *dev, drm_mga_private_t *dev_priv ) 246static int mga_freelist_init(drm_device_t * dev, drm_mga_private_t * dev_priv)
250{ 247{
251 drm_device_dma_t *dma = dev->dma; 248 drm_device_dma_t *dma = dev->dma;
252 drm_buf_t *buf; 249 drm_buf_t *buf;
253 drm_mga_buf_priv_t *buf_priv; 250 drm_mga_buf_priv_t *buf_priv;
254 drm_mga_freelist_t *entry; 251 drm_mga_freelist_t *entry;
255 int i; 252 int i;
256 DRM_DEBUG( "count=%d\n", dma->buf_count ); 253 DRM_DEBUG("count=%d\n", dma->buf_count);
257 254
258 dev_priv->head = drm_alloc( sizeof(drm_mga_freelist_t), 255 dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
259 DRM_MEM_DRIVER ); 256 if (dev_priv->head == NULL)
260 if ( dev_priv->head == NULL )
261 return DRM_ERR(ENOMEM); 257 return DRM_ERR(ENOMEM);
262 258
263 memset( dev_priv->head, 0, sizeof(drm_mga_freelist_t) ); 259 memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t));
264 SET_AGE( &dev_priv->head->age, MGA_BUFFER_USED, 0 ); 260 SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0);
265 261
266 for ( i = 0 ; i < dma->buf_count ; i++ ) { 262 for (i = 0; i < dma->buf_count; i++) {
267 buf = dma->buflist[i]; 263 buf = dma->buflist[i];
268 buf_priv = buf->dev_private; 264 buf_priv = buf->dev_private;
269 265
270 entry = drm_alloc( sizeof(drm_mga_freelist_t), 266 entry = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
271 DRM_MEM_DRIVER ); 267 if (entry == NULL)
272 if ( entry == NULL )
273 return DRM_ERR(ENOMEM); 268 return DRM_ERR(ENOMEM);
274 269
275 memset( entry, 0, sizeof(drm_mga_freelist_t) ); 270 memset(entry, 0, sizeof(drm_mga_freelist_t));
276 271
277 entry->next = dev_priv->head->next; 272 entry->next = dev_priv->head->next;
278 entry->prev = dev_priv->head; 273 entry->prev = dev_priv->head;
279 SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 ); 274 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
280 entry->buf = buf; 275 entry->buf = buf;
281 276
282 if ( dev_priv->head->next != NULL ) 277 if (dev_priv->head->next != NULL)
283 dev_priv->head->next->prev = entry; 278 dev_priv->head->next->prev = entry;
284 if ( entry->next == NULL ) 279 if (entry->next == NULL)
285 dev_priv->tail = entry; 280 dev_priv->tail = entry;
286 281
287 buf_priv->list_entry = entry; 282 buf_priv->list_entry = entry;
@@ -294,17 +289,17 @@ static int mga_freelist_init( drm_device_t *dev, drm_mga_private_t *dev_priv )
294 return 0; 289 return 0;
295} 290}
296 291
297static void mga_freelist_cleanup( drm_device_t *dev ) 292static void mga_freelist_cleanup(drm_device_t * dev)
298{ 293{
299 drm_mga_private_t *dev_priv = dev->dev_private; 294 drm_mga_private_t *dev_priv = dev->dev_private;
300 drm_mga_freelist_t *entry; 295 drm_mga_freelist_t *entry;
301 drm_mga_freelist_t *next; 296 drm_mga_freelist_t *next;
302 DRM_DEBUG( "\n" ); 297 DRM_DEBUG("\n");
303 298
304 entry = dev_priv->head; 299 entry = dev_priv->head;
305 while ( entry ) { 300 while (entry) {
306 next = entry->next; 301 next = entry->next;
307 drm_free( entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER ); 302 drm_free(entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
308 entry = next; 303 entry = next;
309 } 304 }
310 305
@@ -314,71 +309,69 @@ static void mga_freelist_cleanup( drm_device_t *dev )
314#if 0 309#if 0
315/* FIXME: Still needed? 310/* FIXME: Still needed?
316 */ 311 */
317static void mga_freelist_reset( drm_device_t *dev ) 312static void mga_freelist_reset(drm_device_t * dev)
318{ 313{
319 drm_device_dma_t *dma = dev->dma; 314 drm_device_dma_t *dma = dev->dma;
320 drm_buf_t *buf; 315 drm_buf_t *buf;
321 drm_mga_buf_priv_t *buf_priv; 316 drm_mga_buf_priv_t *buf_priv;
322 int i; 317 int i;
323 318
324 for ( i = 0 ; i < dma->buf_count ; i++ ) { 319 for (i = 0; i < dma->buf_count; i++) {
325 buf = dma->buflist[i]; 320 buf = dma->buflist[i];
326 buf_priv = buf->dev_private; 321 buf_priv = buf->dev_private;
327 SET_AGE( &buf_priv->list_entry->age, 322 SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0);
328 MGA_BUFFER_FREE, 0 );
329 } 323 }
330} 324}
331#endif 325#endif
332 326
333static drm_buf_t *mga_freelist_get( drm_device_t *dev ) 327static drm_buf_t *mga_freelist_get(drm_device_t * dev)
334{ 328{
335 drm_mga_private_t *dev_priv = dev->dev_private; 329 drm_mga_private_t *dev_priv = dev->dev_private;
336 drm_mga_freelist_t *next; 330 drm_mga_freelist_t *next;
337 drm_mga_freelist_t *prev; 331 drm_mga_freelist_t *prev;
338 drm_mga_freelist_t *tail = dev_priv->tail; 332 drm_mga_freelist_t *tail = dev_priv->tail;
339 u32 head, wrap; 333 u32 head, wrap;
340 DRM_DEBUG( "\n" ); 334 DRM_DEBUG("\n");
341 335
342 head = MGA_READ( MGA_PRIMADDRESS ); 336 head = MGA_READ(MGA_PRIMADDRESS);
343 wrap = dev_priv->sarea_priv->last_wrap; 337 wrap = dev_priv->sarea_priv->last_wrap;
344 338
345 DRM_DEBUG( " tail=0x%06lx %d\n", 339 DRM_DEBUG(" tail=0x%06lx %d\n",
346 tail->age.head ? 340 tail->age.head ?
347 tail->age.head - dev_priv->primary->offset : 0, 341 tail->age.head - dev_priv->primary->offset : 0,
348 tail->age.wrap ); 342 tail->age.wrap);
349 DRM_DEBUG( " head=0x%06lx %d\n", 343 DRM_DEBUG(" head=0x%06lx %d\n",
350 head - dev_priv->primary->offset, wrap ); 344 head - dev_priv->primary->offset, wrap);
351 345
352 if ( TEST_AGE( &tail->age, head, wrap ) ) { 346 if (TEST_AGE(&tail->age, head, wrap)) {
353 prev = dev_priv->tail->prev; 347 prev = dev_priv->tail->prev;
354 next = dev_priv->tail; 348 next = dev_priv->tail;
355 prev->next = NULL; 349 prev->next = NULL;
356 next->prev = next->next = NULL; 350 next->prev = next->next = NULL;
357 dev_priv->tail = prev; 351 dev_priv->tail = prev;
358 SET_AGE( &next->age, MGA_BUFFER_USED, 0 ); 352 SET_AGE(&next->age, MGA_BUFFER_USED, 0);
359 return next->buf; 353 return next->buf;
360 } 354 }
361 355
362 DRM_DEBUG( "returning NULL!\n" ); 356 DRM_DEBUG("returning NULL!\n");
363 return NULL; 357 return NULL;
364} 358}
365 359
366int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf ) 360int mga_freelist_put(drm_device_t * dev, drm_buf_t * buf)
367{ 361{
368 drm_mga_private_t *dev_priv = dev->dev_private; 362 drm_mga_private_t *dev_priv = dev->dev_private;
369 drm_mga_buf_priv_t *buf_priv = buf->dev_private; 363 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
370 drm_mga_freelist_t *head, *entry, *prev; 364 drm_mga_freelist_t *head, *entry, *prev;
371 365
372 DRM_DEBUG( "age=0x%06lx wrap=%d\n", 366 DRM_DEBUG("age=0x%06lx wrap=%d\n",
373 buf_priv->list_entry->age.head - 367 buf_priv->list_entry->age.head -
374 dev_priv->primary->offset, 368 dev_priv->primary->offset, buf_priv->list_entry->age.wrap);
375 buf_priv->list_entry->age.wrap );
376 369
377 entry = buf_priv->list_entry; 370 entry = buf_priv->list_entry;
378 head = dev_priv->head; 371 head = dev_priv->head;
379 372
380 if ( buf_priv->list_entry->age.head == MGA_BUFFER_USED ) { 373 if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) {
381 SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 ); 374 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
382 prev = dev_priv->tail; 375 prev = dev_priv->tail;
383 prev->next = entry; 376 prev->next = entry;
384 entry->prev = prev; 377 entry->prev = prev;
@@ -394,15 +387,13 @@ int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf )
394 return 0; 387 return 0;
395} 388}
396 389
397
398/* ================================================================ 390/* ================================================================
399 * DMA initialization, cleanup 391 * DMA initialization, cleanup
400 */ 392 */
401 393
402 394int mga_driver_preinit(drm_device_t * dev, unsigned long flags)
403int mga_driver_preinit(drm_device_t *dev, unsigned long flags)
404{ 395{
405 drm_mga_private_t * dev_priv; 396 drm_mga_private_t *dev_priv;
406 397
407 dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER); 398 dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
408 if (!dev_priv) 399 if (!dev_priv)
@@ -420,7 +411,7 @@ int mga_driver_preinit(drm_device_t *dev, unsigned long flags)
420#if __OS_HAS_AGP 411#if __OS_HAS_AGP
421/** 412/**
422 * Bootstrap the driver for AGP DMA. 413 * Bootstrap the driver for AGP DMA.
423 * 414 *
424 * \todo 415 * \todo
425 * Investigate whether there is any benifit to storing the WARP microcode in 416 * Investigate whether there is any benifit to storing the WARP microcode in
426 * AGP memory. If not, the microcode may as well always be put in PCI 417 * AGP memory. If not, the microcode may as well always be put in PCI
@@ -436,18 +427,18 @@ int mga_driver_preinit(drm_device_t *dev, unsigned long flags)
436static int mga_do_agp_dma_bootstrap(drm_device_t * dev, 427static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
437 drm_mga_dma_bootstrap_t * dma_bs) 428 drm_mga_dma_bootstrap_t * dma_bs)
438{ 429{
439 drm_mga_private_t * const dev_priv = (drm_mga_private_t *) dev->dev_private; 430 drm_mga_private_t *const dev_priv =
431 (drm_mga_private_t *) dev->dev_private;
440 const unsigned int warp_size = mga_warp_microcode_size(dev_priv); 432 const unsigned int warp_size = mga_warp_microcode_size(dev_priv);
441 int err; 433 int err;
442 unsigned offset; 434 unsigned offset;
443 const unsigned secondary_size = dma_bs->secondary_bin_count 435 const unsigned secondary_size = dma_bs->secondary_bin_count
444 * dma_bs->secondary_bin_size; 436 * dma_bs->secondary_bin_size;
445 const unsigned agp_size = (dma_bs->agp_size << 20); 437 const unsigned agp_size = (dma_bs->agp_size << 20);
446 drm_buf_desc_t req; 438 drm_buf_desc_t req;
447 drm_agp_mode_t mode; 439 drm_agp_mode_t mode;
448 drm_agp_info_t info; 440 drm_agp_info_t info;
449 441
450
451 /* Acquire AGP. */ 442 /* Acquire AGP. */
452 err = drm_agp_acquire(dev); 443 err = drm_agp_acquire(dev);
453 if (err) { 444 if (err) {
@@ -468,7 +459,6 @@ static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
468 return err; 459 return err;
469 } 460 }
470 461
471
472 /* In addition to the usual AGP mode configuration, the G200 AGP cards 462 /* In addition to the usual AGP mode configuration, the G200 AGP cards
473 * need to have the AGP mode "manually" set. 463 * need to have the AGP mode "manually" set.
474 */ 464 */
@@ -476,68 +466,66 @@ static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
476 if (dev_priv->chipset == MGA_CARD_TYPE_G200) { 466 if (dev_priv->chipset == MGA_CARD_TYPE_G200) {
477 if (mode.mode & 0x02) { 467 if (mode.mode & 0x02) {
478 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE); 468 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE);
479 } 469 } else {
480 else {
481 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE); 470 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE);
482 } 471 }
483 } 472 }
484 473
485
486 /* Allocate and bind AGP memory. */ 474 /* Allocate and bind AGP memory. */
487 dev_priv->agp_pages = agp_size / PAGE_SIZE; 475 dev_priv->agp_pages = agp_size / PAGE_SIZE;
488 dev_priv->agp_mem = drm_alloc_agp( dev, dev_priv->agp_pages, 0 ); 476 dev_priv->agp_mem = drm_alloc_agp(dev, dev_priv->agp_pages, 0);
489 if (dev_priv->agp_mem == NULL) { 477 if (dev_priv->agp_mem == NULL) {
490 dev_priv->agp_pages = 0; 478 dev_priv->agp_pages = 0;
491 DRM_ERROR("Unable to allocate %uMB AGP memory\n", 479 DRM_ERROR("Unable to allocate %uMB AGP memory\n",
492 dma_bs->agp_size); 480 dma_bs->agp_size);
493 return DRM_ERR(ENOMEM); 481 return DRM_ERR(ENOMEM);
494 } 482 }
495 483
496 err = drm_bind_agp( dev_priv->agp_mem, 0 ); 484 err = drm_bind_agp(dev_priv->agp_mem, 0);
497 if (err) { 485 if (err) {
498 DRM_ERROR("Unable to bind AGP memory\n"); 486 DRM_ERROR("Unable to bind AGP memory\n");
499 return err; 487 return err;
500 } 488 }
501 489
502 offset = 0; 490 offset = 0;
503 err = drm_addmap( dev, offset, warp_size, 491 err = drm_addmap(dev, offset, warp_size,
504 _DRM_AGP, _DRM_READ_ONLY, & dev_priv->warp ); 492 _DRM_AGP, _DRM_READ_ONLY, &dev_priv->warp);
505 if (err) { 493 if (err) {
506 DRM_ERROR("Unable to map WARP microcode\n"); 494 DRM_ERROR("Unable to map WARP microcode\n");
507 return err; 495 return err;
508 } 496 }
509 497
510 offset += warp_size; 498 offset += warp_size;
511 err = drm_addmap( dev, offset, dma_bs->primary_size, 499 err = drm_addmap(dev, offset, dma_bs->primary_size,
512 _DRM_AGP, _DRM_READ_ONLY, & dev_priv->primary ); 500 _DRM_AGP, _DRM_READ_ONLY, &dev_priv->primary);
513 if (err) { 501 if (err) {
514 DRM_ERROR("Unable to map primary DMA region\n"); 502 DRM_ERROR("Unable to map primary DMA region\n");
515 return err; 503 return err;
516 } 504 }
517 505
518 offset += dma_bs->primary_size; 506 offset += dma_bs->primary_size;
519 err = drm_addmap( dev, offset, secondary_size, 507 err = drm_addmap(dev, offset, secondary_size,
520 _DRM_AGP, 0, & dev->agp_buffer_map ); 508 _DRM_AGP, 0, &dev->agp_buffer_map);
521 if (err) { 509 if (err) {
522 DRM_ERROR("Unable to map secondary DMA region\n"); 510 DRM_ERROR("Unable to map secondary DMA region\n");
523 return err; 511 return err;
524 } 512 }
525 513
526 (void) memset( &req, 0, sizeof(req) ); 514 (void)memset(&req, 0, sizeof(req));
527 req.count = dma_bs->secondary_bin_count; 515 req.count = dma_bs->secondary_bin_count;
528 req.size = dma_bs->secondary_bin_size; 516 req.size = dma_bs->secondary_bin_size;
529 req.flags = _DRM_AGP_BUFFER; 517 req.flags = _DRM_AGP_BUFFER;
530 req.agp_start = offset; 518 req.agp_start = offset;
531 519
532 err = drm_addbufs_agp( dev, & req ); 520 err = drm_addbufs_agp(dev, &req);
533 if (err) { 521 if (err) {
534 DRM_ERROR("Unable to add secondary DMA buffers\n"); 522 DRM_ERROR("Unable to add secondary DMA buffers\n");
535 return err; 523 return err;
536 } 524 }
537 525
538 offset += secondary_size; 526 offset += secondary_size;
539 err = drm_addmap( dev, offset, agp_size - offset, 527 err = drm_addmap(dev, offset, agp_size - offset,
540 _DRM_AGP, 0, & dev_priv->agp_textures ); 528 _DRM_AGP, 0, &dev_priv->agp_textures);
541 if (err) { 529 if (err) {
542 DRM_ERROR("Unable to map AGP texture region\n"); 530 DRM_ERROR("Unable to map AGP texture region\n");
543 return err; 531 return err;
@@ -571,7 +559,7 @@ static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
571 559
572/** 560/**
573 * Bootstrap the driver for PCI DMA. 561 * Bootstrap the driver for PCI DMA.
574 * 562 *
575 * \todo 563 * \todo
576 * The algorithm for decreasing the size of the primary DMA buffer could be 564 * The algorithm for decreasing the size of the primary DMA buffer could be
577 * better. The size should be rounded up to the nearest page size, then 565 * better. The size should be rounded up to the nearest page size, then
@@ -580,20 +568,20 @@ static int mga_do_agp_dma_bootstrap(drm_device_t * dev,
580 * \todo 568 * \todo
581 * Determine whether the maximum address passed to drm_pci_alloc is correct. 569 * Determine whether the maximum address passed to drm_pci_alloc is correct.
582 * The same goes for drm_addbufs_pci. 570 * The same goes for drm_addbufs_pci.
583 * 571 *
584 * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap 572 * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap
585 */ 573 */
586static int mga_do_pci_dma_bootstrap(drm_device_t * dev, 574static int mga_do_pci_dma_bootstrap(drm_device_t * dev,
587 drm_mga_dma_bootstrap_t * dma_bs) 575 drm_mga_dma_bootstrap_t * dma_bs)
588{ 576{
589 drm_mga_private_t * const dev_priv = (drm_mga_private_t *) dev->dev_private; 577 drm_mga_private_t *const dev_priv =
578 (drm_mga_private_t *) dev->dev_private;
590 const unsigned int warp_size = mga_warp_microcode_size(dev_priv); 579 const unsigned int warp_size = mga_warp_microcode_size(dev_priv);
591 unsigned int primary_size; 580 unsigned int primary_size;
592 unsigned int bin_count; 581 unsigned int bin_count;
593 int err; 582 int err;
594 drm_buf_desc_t req; 583 drm_buf_desc_t req;
595 584
596
597 if (dev->dma == NULL) { 585 if (dev->dma == NULL) {
598 DRM_ERROR("dev->dma is NULL\n"); 586 DRM_ERROR("dev->dma is NULL\n");
599 return DRM_ERR(EFAULT); 587 return DRM_ERR(EFAULT);
@@ -612,9 +600,8 @@ static int mga_do_pci_dma_bootstrap(drm_device_t * dev,
612 * alignment of the primary or secondary DMA buffers. 600 * alignment of the primary or secondary DMA buffers.
613 */ 601 */
614 602
615 for ( primary_size = dma_bs->primary_size 603 for (primary_size = dma_bs->primary_size; primary_size != 0;
616 ; primary_size != 0 604 primary_size >>= 1) {
617 ; primary_size >>= 1 ) {
618 /* The proper alignment for this mapping is 0x04 */ 605 /* The proper alignment for this mapping is 0x04 */
619 err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT, 606 err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT,
620 _DRM_READ_ONLY, &dev_priv->primary); 607 _DRM_READ_ONLY, &dev_priv->primary);
@@ -629,24 +616,23 @@ static int mga_do_pci_dma_bootstrap(drm_device_t * dev,
629 616
630 if (dev_priv->primary->size != dma_bs->primary_size) { 617 if (dev_priv->primary->size != dma_bs->primary_size) {
631 DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n", 618 DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n",
632 dma_bs->primary_size, 619 dma_bs->primary_size,
633 (unsigned) dev_priv->primary->size); 620 (unsigned)dev_priv->primary->size);
634 dma_bs->primary_size = dev_priv->primary->size; 621 dma_bs->primary_size = dev_priv->primary->size;
635 } 622 }
636 623
637 for ( bin_count = dma_bs->secondary_bin_count 624 for (bin_count = dma_bs->secondary_bin_count; bin_count > 0;
638 ; bin_count > 0 625 bin_count--) {
639 ; bin_count-- ) { 626 (void)memset(&req, 0, sizeof(req));
640 (void) memset( &req, 0, sizeof(req) );
641 req.count = bin_count; 627 req.count = bin_count;
642 req.size = dma_bs->secondary_bin_size; 628 req.size = dma_bs->secondary_bin_size;
643 629
644 err = drm_addbufs_pci( dev, & req ); 630 err = drm_addbufs_pci(dev, &req);
645 if (!err) { 631 if (!err) {
646 break; 632 break;
647 } 633 }
648 } 634 }
649 635
650 if (bin_count == 0) { 636 if (bin_count == 0) {
651 DRM_ERROR("Unable to add secondary DMA buffers\n"); 637 DRM_ERROR("Unable to add secondary DMA buffers\n");
652 return err; 638 return err;
@@ -668,38 +654,34 @@ static int mga_do_pci_dma_bootstrap(drm_device_t * dev,
668 return 0; 654 return 0;
669} 655}
670 656
671
672static int mga_do_dma_bootstrap(drm_device_t * dev, 657static int mga_do_dma_bootstrap(drm_device_t * dev,
673 drm_mga_dma_bootstrap_t * dma_bs) 658 drm_mga_dma_bootstrap_t * dma_bs)
674{ 659{
675 const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev); 660 const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev);
676 int err; 661 int err;
677 drm_mga_private_t * const dev_priv = 662 drm_mga_private_t *const dev_priv =
678 (drm_mga_private_t *) dev->dev_private; 663 (drm_mga_private_t *) dev->dev_private;
679
680 664
681 dev_priv->used_new_dma_init = 1; 665 dev_priv->used_new_dma_init = 1;
682 666
683 /* The first steps are the same for both PCI and AGP based DMA. Map 667 /* The first steps are the same for both PCI and AGP based DMA. Map
684 * the cards MMIO registers and map a status page. 668 * the cards MMIO registers and map a status page.
685 */ 669 */
686 err = drm_addmap( dev, dev_priv->mmio_base, dev_priv->mmio_size, 670 err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size,
687 _DRM_REGISTERS, _DRM_READ_ONLY, & dev_priv->mmio ); 671 _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio);
688 if (err) { 672 if (err) {
689 DRM_ERROR("Unable to map MMIO region\n"); 673 DRM_ERROR("Unable to map MMIO region\n");
690 return err; 674 return err;
691 } 675 }
692 676
693 677 err = drm_addmap(dev, 0, SAREA_MAX, _DRM_SHM,
694 err = drm_addmap( dev, 0, SAREA_MAX, _DRM_SHM, 678 _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL,
695 _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL, 679 &dev_priv->status);
696 & dev_priv->status );
697 if (err) { 680 if (err) {
698 DRM_ERROR("Unable to map status region\n"); 681 DRM_ERROR("Unable to map status region\n");
699 return err; 682 return err;
700 } 683 }
701 684
702
703 /* The DMA initialization procedure is slightly different for PCI and 685 /* The DMA initialization procedure is slightly different for PCI and
704 * AGP cards. AGP cards just allocate a large block of AGP memory and 686 * AGP cards. AGP cards just allocate a large block of AGP memory and
705 * carve off portions of it for internal uses. The remaining memory 687 * carve off portions of it for internal uses. The remaining memory
@@ -708,7 +690,7 @@ static int mga_do_dma_bootstrap(drm_device_t * dev,
708 if (is_agp) { 690 if (is_agp) {
709 err = mga_do_agp_dma_bootstrap(dev, dma_bs); 691 err = mga_do_agp_dma_bootstrap(dev, dma_bs);
710 } 692 }
711 693
712 /* If we attempted to initialize the card for AGP DMA but failed, 694 /* If we attempted to initialize the card for AGP DMA but failed,
713 * clean-up any mess that may have been created. 695 * clean-up any mess that may have been created.
714 */ 696 */
@@ -717,7 +699,6 @@ static int mga_do_dma_bootstrap(drm_device_t * dev,
717 mga_do_cleanup_dma(dev); 699 mga_do_cleanup_dma(dev);
718 } 700 }
719 701
720
721 /* Not only do we want to try and initialized PCI cards for PCI DMA, 702 /* Not only do we want to try and initialized PCI cards for PCI DMA,
722 * but we also try to initialized AGP cards that could not be 703 * but we also try to initialized AGP cards that could not be
723 * initialized for AGP DMA. This covers the case where we have an AGP 704 * initialized for AGP DMA. This covers the case where we have an AGP
@@ -730,7 +711,6 @@ static int mga_do_dma_bootstrap(drm_device_t * dev,
730 err = mga_do_pci_dma_bootstrap(dev, dma_bs); 711 err = mga_do_pci_dma_bootstrap(dev, dma_bs);
731 } 712 }
732 713
733
734 return err; 714 return err;
735} 715}
736 716
@@ -740,45 +720,42 @@ int mga_dma_bootstrap(DRM_IOCTL_ARGS)
740 drm_mga_dma_bootstrap_t bootstrap; 720 drm_mga_dma_bootstrap_t bootstrap;
741 int err; 721 int err;
742 722
743
744 DRM_COPY_FROM_USER_IOCTL(bootstrap, 723 DRM_COPY_FROM_USER_IOCTL(bootstrap,
745 (drm_mga_dma_bootstrap_t __user *) data, 724 (drm_mga_dma_bootstrap_t __user *) data,
746 sizeof(bootstrap)); 725 sizeof(bootstrap));
747 726
748 err = mga_do_dma_bootstrap(dev, & bootstrap); 727 err = mga_do_dma_bootstrap(dev, &bootstrap);
749 if (! err) { 728 if (!err) {
750 static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 }; 729 static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 };
751 const drm_mga_private_t * const dev_priv = 730 const drm_mga_private_t *const dev_priv =
752 (drm_mga_private_t *) dev->dev_private; 731 (drm_mga_private_t *) dev->dev_private;
753 732
754 if (dev_priv->agp_textures != NULL) { 733 if (dev_priv->agp_textures != NULL) {
755 bootstrap.texture_handle = dev_priv->agp_textures->offset; 734 bootstrap.texture_handle =
735 dev_priv->agp_textures->offset;
756 bootstrap.texture_size = dev_priv->agp_textures->size; 736 bootstrap.texture_size = dev_priv->agp_textures->size;
757 } 737 } else {
758 else {
759 bootstrap.texture_handle = 0; 738 bootstrap.texture_handle = 0;
760 bootstrap.texture_size = 0; 739 bootstrap.texture_size = 0;
761 } 740 }
762 741
763 bootstrap.agp_mode = modes[ bootstrap.agp_mode & 0x07 ]; 742 bootstrap.agp_mode = modes[bootstrap.agp_mode & 0x07];
764 if (DRM_COPY_TO_USER( (void __user *) data, & bootstrap, 743 if (DRM_COPY_TO_USER((void __user *)data, &bootstrap,
765 sizeof(bootstrap))) { 744 sizeof(bootstrap))) {
766 err = DRM_ERR(EFAULT); 745 err = DRM_ERR(EFAULT);
767 } 746 }
768 } 747 } else {
769 else {
770 mga_do_cleanup_dma(dev); 748 mga_do_cleanup_dma(dev);
771 } 749 }
772 750
773 return err; 751 return err;
774} 752}
775 753
776static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init ) 754static int mga_do_init_dma(drm_device_t * dev, drm_mga_init_t * init)
777{ 755{
778 drm_mga_private_t *dev_priv; 756 drm_mga_private_t *dev_priv;
779 int ret; 757 int ret;
780 DRM_DEBUG( "\n" ); 758 DRM_DEBUG("\n");
781
782 759
783 dev_priv = dev->dev_private; 760 dev_priv = dev->dev_private;
784 761
@@ -787,17 +764,17 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
787 } else { 764 } else {
788 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR; 765 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR;
789 } 766 }
790 dev_priv->maccess = init->maccess; 767 dev_priv->maccess = init->maccess;
791 768
792 dev_priv->fb_cpp = init->fb_cpp; 769 dev_priv->fb_cpp = init->fb_cpp;
793 dev_priv->front_offset = init->front_offset; 770 dev_priv->front_offset = init->front_offset;
794 dev_priv->front_pitch = init->front_pitch; 771 dev_priv->front_pitch = init->front_pitch;
795 dev_priv->back_offset = init->back_offset; 772 dev_priv->back_offset = init->back_offset;
796 dev_priv->back_pitch = init->back_pitch; 773 dev_priv->back_pitch = init->back_pitch;
797 774
798 dev_priv->depth_cpp = init->depth_cpp; 775 dev_priv->depth_cpp = init->depth_cpp;
799 dev_priv->depth_offset = init->depth_offset; 776 dev_priv->depth_offset = init->depth_offset;
800 dev_priv->depth_pitch = init->depth_pitch; 777 dev_priv->depth_pitch = init->depth_pitch;
801 778
802 /* FIXME: Need to support AGP textures... 779 /* FIXME: Need to support AGP textures...
803 */ 780 */
@@ -811,7 +788,7 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
811 return DRM_ERR(EINVAL); 788 return DRM_ERR(EINVAL);
812 } 789 }
813 790
814 if (! dev_priv->used_new_dma_init) { 791 if (!dev_priv->used_new_dma_init) {
815 dev_priv->status = drm_core_findmap(dev, init->status_offset); 792 dev_priv->status = drm_core_findmap(dev, init->status_offset);
816 if (!dev_priv->status) { 793 if (!dev_priv->status) {
817 DRM_ERROR("failed to find status page!\n"); 794 DRM_ERROR("failed to find status page!\n");
@@ -833,7 +810,8 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
833 return DRM_ERR(EINVAL); 810 return DRM_ERR(EINVAL);
834 } 811 }
835 dev->agp_buffer_token = init->buffers_offset; 812 dev->agp_buffer_token = init->buffers_offset;
836 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 813 dev->agp_buffer_map =
814 drm_core_findmap(dev, init->buffers_offset);
837 if (!dev->agp_buffer_map) { 815 if (!dev->agp_buffer_map) {
838 DRM_ERROR("failed to find dma buffer region!\n"); 816 DRM_ERROR("failed to find dma buffer region!\n");
839 return DRM_ERR(EINVAL); 817 return DRM_ERR(EINVAL);
@@ -845,8 +823,8 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
845 } 823 }
846 824
847 dev_priv->sarea_priv = 825 dev_priv->sarea_priv =
848 (drm_mga_sarea_t *)((u8 *)dev_priv->sarea->handle + 826 (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle +
849 init->sarea_priv_offset); 827 init->sarea_priv_offset);
850 828
851 if (!dev_priv->warp->handle || 829 if (!dev_priv->warp->handle ||
852 !dev_priv->primary->handle || 830 !dev_priv->primary->handle ||
@@ -869,23 +847,20 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
869 return ret; 847 return ret;
870 } 848 }
871 849
872 dev_priv->prim.status = (u32 *)dev_priv->status->handle; 850 dev_priv->prim.status = (u32 *) dev_priv->status->handle;
873 851
874 mga_do_wait_for_idle( dev_priv ); 852 mga_do_wait_for_idle(dev_priv);
875 853
876 /* Init the primary DMA registers. 854 /* Init the primary DMA registers.
877 */ 855 */
878 MGA_WRITE( MGA_PRIMADDRESS, 856 MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL);
879 dev_priv->primary->offset | MGA_DMA_GENERAL );
880#if 0 857#if 0
881 MGA_WRITE( MGA_PRIMPTR, 858 MGA_WRITE(MGA_PRIMPTR, virt_to_bus((void *)dev_priv->prim.status) | MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */
882 virt_to_bus((void *)dev_priv->prim.status) | 859 MGA_PRIMPTREN1); /* DWGSYNC */
883 MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */
884 MGA_PRIMPTREN1 ); /* DWGSYNC */
885#endif 860#endif
886 861
887 dev_priv->prim.start = (u8 *)dev_priv->primary->handle; 862 dev_priv->prim.start = (u8 *) dev_priv->primary->handle;
888 dev_priv->prim.end = ((u8 *)dev_priv->primary->handle 863 dev_priv->prim.end = ((u8 *) dev_priv->primary->handle
889 + dev_priv->primary->size); 864 + dev_priv->primary->size);
890 dev_priv->prim.size = dev_priv->primary->size; 865 dev_priv->prim.size = dev_priv->primary->size;
891 866
@@ -913,7 +888,7 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
913 return 0; 888 return 0;
914} 889}
915 890
916static int mga_do_cleanup_dma( drm_device_t *dev ) 891static int mga_do_cleanup_dma(drm_device_t * dev)
917{ 892{
918 int err = 0; 893 int err = 0;
919 DRM_DEBUG("\n"); 894 DRM_DEBUG("\n");
@@ -922,16 +897,17 @@ static int mga_do_cleanup_dma( drm_device_t *dev )
922 * may not have been called from userspace and after dev_private 897 * may not have been called from userspace and after dev_private
923 * is freed, it's too late. 898 * is freed, it's too late.
924 */ 899 */
925 if ( dev->irq_enabled ) drm_irq_uninstall(dev); 900 if (dev->irq_enabled)
901 drm_irq_uninstall(dev);
926 902
927 if ( dev->dev_private ) { 903 if (dev->dev_private) {
928 drm_mga_private_t *dev_priv = dev->dev_private; 904 drm_mga_private_t *dev_priv = dev->dev_private;
929 905
930 if ((dev_priv->warp != NULL) 906 if ((dev_priv->warp != NULL)
931 && (dev_priv->mmio->type != _DRM_CONSISTENT)) 907 && (dev_priv->mmio->type != _DRM_CONSISTENT))
932 drm_core_ioremapfree(dev_priv->warp, dev); 908 drm_core_ioremapfree(dev_priv->warp, dev);
933 909
934 if ((dev_priv->primary != NULL) 910 if ((dev_priv->primary != NULL)
935 && (dev_priv->primary->type != _DRM_CONSISTENT)) 911 && (dev_priv->primary->type != _DRM_CONSISTENT))
936 drm_core_ioremapfree(dev_priv->primary, dev); 912 drm_core_ioremapfree(dev_priv->primary, dev);
937 913
@@ -944,7 +920,8 @@ static int mga_do_cleanup_dma( drm_device_t *dev )
944 dev_priv->agp_textures = NULL; 920 dev_priv->agp_textures = NULL;
945 drm_unbind_agp(dev_priv->agp_mem); 921 drm_unbind_agp(dev_priv->agp_mem);
946 922
947 drm_free_agp(dev_priv->agp_mem, dev_priv->agp_pages); 923 drm_free_agp(dev_priv->agp_mem,
924 dev_priv->agp_pages);
948 dev_priv->agp_pages = 0; 925 dev_priv->agp_pages = 0;
949 dev_priv->agp_mem = NULL; 926 dev_priv->agp_mem = NULL;
950 } 927 }
@@ -966,7 +943,8 @@ static int mga_do_cleanup_dma( drm_device_t *dev )
966 943
967 memset(&dev_priv->prim, 0, sizeof(dev_priv->prim)); 944 memset(&dev_priv->prim, 0, sizeof(dev_priv->prim));
968 dev_priv->warp_pipe = 0; 945 dev_priv->warp_pipe = 0;
969 memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys)); 946 memset(dev_priv->warp_pipe_phys, 0,
947 sizeof(dev_priv->warp_pipe_phys));
970 948
971 if (dev_priv->head != NULL) { 949 if (dev_priv->head != NULL) {
972 mga_freelist_cleanup(dev); 950 mga_freelist_cleanup(dev);
@@ -976,103 +954,102 @@ static int mga_do_cleanup_dma( drm_device_t *dev )
976 return err; 954 return err;
977} 955}
978 956
979int mga_dma_init( DRM_IOCTL_ARGS ) 957int mga_dma_init(DRM_IOCTL_ARGS)
980{ 958{
981 DRM_DEVICE; 959 DRM_DEVICE;
982 drm_mga_init_t init; 960 drm_mga_init_t init;
983 int err; 961 int err;
984 962
985 LOCK_TEST_WITH_RETURN( dev, filp ); 963 LOCK_TEST_WITH_RETURN(dev, filp);
986 964
987 DRM_COPY_FROM_USER_IOCTL(init, (drm_mga_init_t __user *) data, 965 DRM_COPY_FROM_USER_IOCTL(init, (drm_mga_init_t __user *) data,
988 sizeof(init)); 966 sizeof(init));
989 967
990 switch ( init.func ) { 968 switch (init.func) {
991 case MGA_INIT_DMA: 969 case MGA_INIT_DMA:
992 err = mga_do_init_dma(dev, &init); 970 err = mga_do_init_dma(dev, &init);
993 if (err) { 971 if (err) {
994 (void) mga_do_cleanup_dma(dev); 972 (void)mga_do_cleanup_dma(dev);
995 } 973 }
996 return err; 974 return err;
997 case MGA_CLEANUP_DMA: 975 case MGA_CLEANUP_DMA:
998 return mga_do_cleanup_dma( dev ); 976 return mga_do_cleanup_dma(dev);
999 } 977 }
1000 978
1001 return DRM_ERR(EINVAL); 979 return DRM_ERR(EINVAL);
1002} 980}
1003 981
1004
1005/* ================================================================ 982/* ================================================================
1006 * Primary DMA stream management 983 * Primary DMA stream management
1007 */ 984 */
1008 985
1009int mga_dma_flush( DRM_IOCTL_ARGS ) 986int mga_dma_flush(DRM_IOCTL_ARGS)
1010{ 987{
1011 DRM_DEVICE; 988 DRM_DEVICE;
1012 drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; 989 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1013 drm_lock_t lock; 990 drm_lock_t lock;
1014 991
1015 LOCK_TEST_WITH_RETURN( dev, filp ); 992 LOCK_TEST_WITH_RETURN(dev, filp);
1016 993
1017 DRM_COPY_FROM_USER_IOCTL( lock, (drm_lock_t __user *)data, sizeof(lock) ); 994 DRM_COPY_FROM_USER_IOCTL(lock, (drm_lock_t __user *) data,
995 sizeof(lock));
1018 996
1019 DRM_DEBUG( "%s%s%s\n", 997 DRM_DEBUG("%s%s%s\n",
1020 (lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "", 998 (lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "",
1021 (lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "", 999 (lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "",
1022 (lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "" ); 1000 (lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "");
1023 1001
1024 WRAP_WAIT_WITH_RETURN( dev_priv ); 1002 WRAP_WAIT_WITH_RETURN(dev_priv);
1025 1003
1026 if ( lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL) ) { 1004 if (lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) {
1027 mga_do_dma_flush( dev_priv ); 1005 mga_do_dma_flush(dev_priv);
1028 } 1006 }
1029 1007
1030 if ( lock.flags & _DRM_LOCK_QUIESCENT ) { 1008 if (lock.flags & _DRM_LOCK_QUIESCENT) {
1031#if MGA_DMA_DEBUG 1009#if MGA_DMA_DEBUG
1032 int ret = mga_do_wait_for_idle( dev_priv ); 1010 int ret = mga_do_wait_for_idle(dev_priv);
1033 if ( ret < 0 ) 1011 if (ret < 0)
1034 DRM_INFO( "%s: -EBUSY\n", __FUNCTION__ ); 1012 DRM_INFO("%s: -EBUSY\n", __FUNCTION__);
1035 return ret; 1013 return ret;
1036#else 1014#else
1037 return mga_do_wait_for_idle( dev_priv ); 1015 return mga_do_wait_for_idle(dev_priv);
1038#endif 1016#endif
1039 } else { 1017 } else {
1040 return 0; 1018 return 0;
1041 } 1019 }
1042} 1020}
1043 1021
1044int mga_dma_reset( DRM_IOCTL_ARGS ) 1022int mga_dma_reset(DRM_IOCTL_ARGS)
1045{ 1023{
1046 DRM_DEVICE; 1024 DRM_DEVICE;
1047 drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; 1025 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1048 1026
1049 LOCK_TEST_WITH_RETURN( dev, filp ); 1027 LOCK_TEST_WITH_RETURN(dev, filp);
1050 1028
1051 return mga_do_dma_reset( dev_priv ); 1029 return mga_do_dma_reset(dev_priv);
1052} 1030}
1053 1031
1054
1055/* ================================================================ 1032/* ================================================================
1056 * DMA buffer management 1033 * DMA buffer management
1057 */ 1034 */
1058 1035
1059static int mga_dma_get_buffers( DRMFILE filp, 1036static int mga_dma_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d)
1060 drm_device_t *dev, drm_dma_t *d )
1061{ 1037{
1062 drm_buf_t *buf; 1038 drm_buf_t *buf;
1063 int i; 1039 int i;
1064 1040
1065 for ( i = d->granted_count ; i < d->request_count ; i++ ) { 1041 for (i = d->granted_count; i < d->request_count; i++) {
1066 buf = mga_freelist_get( dev ); 1042 buf = mga_freelist_get(dev);
1067 if ( !buf ) return DRM_ERR(EAGAIN); 1043 if (!buf)
1044 return DRM_ERR(EAGAIN);
1068 1045
1069 buf->filp = filp; 1046 buf->filp = filp;
1070 1047
1071 if ( DRM_COPY_TO_USER( &d->request_indices[i], 1048 if (DRM_COPY_TO_USER(&d->request_indices[i],
1072 &buf->idx, sizeof(buf->idx) ) ) 1049 &buf->idx, sizeof(buf->idx)))
1073 return DRM_ERR(EFAULT); 1050 return DRM_ERR(EFAULT);
1074 if ( DRM_COPY_TO_USER( &d->request_sizes[i], 1051 if (DRM_COPY_TO_USER(&d->request_sizes[i],
1075 &buf->total, sizeof(buf->total) ) ) 1052 &buf->total, sizeof(buf->total)))
1076 return DRM_ERR(EFAULT); 1053 return DRM_ERR(EFAULT);
1077 1054
1078 d->granted_count++; 1055 d->granted_count++;
@@ -1080,44 +1057,44 @@ static int mga_dma_get_buffers( DRMFILE filp,
1080 return 0; 1057 return 0;
1081} 1058}
1082 1059
1083int mga_dma_buffers( DRM_IOCTL_ARGS ) 1060int mga_dma_buffers(DRM_IOCTL_ARGS)
1084{ 1061{
1085 DRM_DEVICE; 1062 DRM_DEVICE;
1086 drm_device_dma_t *dma = dev->dma; 1063 drm_device_dma_t *dma = dev->dma;
1087 drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; 1064 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1088 drm_dma_t __user *argp = (void __user *)data; 1065 drm_dma_t __user *argp = (void __user *)data;
1089 drm_dma_t d; 1066 drm_dma_t d;
1090 int ret = 0; 1067 int ret = 0;
1091 1068
1092 LOCK_TEST_WITH_RETURN( dev, filp ); 1069 LOCK_TEST_WITH_RETURN(dev, filp);
1093 1070
1094 DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) ); 1071 DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
1095 1072
1096 /* Please don't send us buffers. 1073 /* Please don't send us buffers.
1097 */ 1074 */
1098 if ( d.send_count != 0 ) { 1075 if (d.send_count != 0) {
1099 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", 1076 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1100 DRM_CURRENTPID, d.send_count ); 1077 DRM_CURRENTPID, d.send_count);
1101 return DRM_ERR(EINVAL); 1078 return DRM_ERR(EINVAL);
1102 } 1079 }
1103 1080
1104 /* We'll send you buffers. 1081 /* We'll send you buffers.
1105 */ 1082 */
1106 if ( d.request_count < 0 || d.request_count > dma->buf_count ) { 1083 if (d.request_count < 0 || d.request_count > dma->buf_count) {
1107 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", 1084 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1108 DRM_CURRENTPID, d.request_count, dma->buf_count ); 1085 DRM_CURRENTPID, d.request_count, dma->buf_count);
1109 return DRM_ERR(EINVAL); 1086 return DRM_ERR(EINVAL);
1110 } 1087 }
1111 1088
1112 WRAP_TEST_WITH_RETURN( dev_priv ); 1089 WRAP_TEST_WITH_RETURN(dev_priv);
1113 1090
1114 d.granted_count = 0; 1091 d.granted_count = 0;
1115 1092
1116 if ( d.request_count ) { 1093 if (d.request_count) {
1117 ret = mga_dma_get_buffers( filp, dev, &d ); 1094 ret = mga_dma_get_buffers(filp, dev, &d);
1118 } 1095 }
1119 1096
1120 DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) ); 1097 DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
1121 1098
1122 return ret; 1099 return ret;
1123} 1100}
@@ -1138,11 +1115,11 @@ int mga_driver_postcleanup(drm_device_t * dev)
1138 */ 1115 */
1139void mga_driver_pretakedown(drm_device_t * dev) 1116void mga_driver_pretakedown(drm_device_t * dev)
1140{ 1117{
1141 mga_do_cleanup_dma( dev ); 1118 mga_do_cleanup_dma(dev);
1142} 1119}
1143 1120
1144int mga_driver_dma_quiescent(drm_device_t *dev) 1121int mga_driver_dma_quiescent(drm_device_t * dev)
1145{ 1122{
1146 drm_mga_private_t *dev_priv = dev->dev_private; 1123 drm_mga_private_t *dev_priv = dev->dev_private;
1147 return mga_do_wait_for_idle( dev_priv ); 1124 return mga_do_wait_for_idle(dev_priv);
1148} 1125}
diff --git a/drivers/char/drm/mga_drm.h b/drivers/char/drm/mga_drm.h
index d20aab3bd57b..44d1293e2947 100644
--- a/drivers/char/drm/mga_drm.h
+++ b/drivers/char/drm/mga_drm.h
@@ -44,10 +44,10 @@
44 44
45/* WARP pipe flags 45/* WARP pipe flags
46 */ 46 */
47#define MGA_F 0x1 /* fog */ 47#define MGA_F 0x1 /* fog */
48#define MGA_A 0x2 /* alpha */ 48#define MGA_A 0x2 /* alpha */
49#define MGA_S 0x4 /* specular */ 49#define MGA_S 0x4 /* specular */
50#define MGA_T2 0x8 /* multitexture */ 50#define MGA_T2 0x8 /* multitexture */
51 51
52#define MGA_WARP_TGZ 0 52#define MGA_WARP_TGZ 0
53#define MGA_WARP_TGZF (MGA_F) 53#define MGA_WARP_TGZF (MGA_F)
@@ -66,14 +66,14 @@
66#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A) 66#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A)
67#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A) 67#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A)
68 68
69#define MGA_MAX_G200_PIPES 8 /* no multitex */ 69#define MGA_MAX_G200_PIPES 8 /* no multitex */
70#define MGA_MAX_G400_PIPES 16 70#define MGA_MAX_G400_PIPES 16
71#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES 71#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES
72#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */ 72#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */
73 73
74#define MGA_CARD_TYPE_G200 1 74#define MGA_CARD_TYPE_G200 1
75#define MGA_CARD_TYPE_G400 2 75#define MGA_CARD_TYPE_G400 2
76#define MGA_CARD_TYPE_G450 3 /* not currently used */ 76#define MGA_CARD_TYPE_G450 3 /* not currently used */
77#define MGA_CARD_TYPE_G550 4 77#define MGA_CARD_TYPE_G550 4
78 78
79#define MGA_FRONT 0x1 79#define MGA_FRONT 0x1
@@ -86,14 +86,14 @@
86#define MGA_UPLOAD_TEX0 0x2 86#define MGA_UPLOAD_TEX0 0x2
87#define MGA_UPLOAD_TEX1 0x4 87#define MGA_UPLOAD_TEX1 0x4
88#define MGA_UPLOAD_PIPE 0x8 88#define MGA_UPLOAD_PIPE 0x8
89#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */ 89#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */
90#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */ 90#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */
91#define MGA_UPLOAD_2D 0x40 91#define MGA_UPLOAD_2D 0x40
92#define MGA_WAIT_AGE 0x80 /* handled client-side */ 92#define MGA_WAIT_AGE 0x80 /* handled client-side */
93#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ 93#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */
94#if 0 94#if 0
95#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock 95#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock
96 quiescent */ 96 quiescent */
97#endif 97#endif
98 98
99/* 32 buffers of 64k each, total 2 meg. 99/* 32 buffers of 64k each, total 2 meg.
@@ -120,8 +120,7 @@
120 120
121#define DRM_MGA_IDLE_RETRY 2048 121#define DRM_MGA_IDLE_RETRY 2048
122 122
123#endif /* __MGA_SAREA_DEFINES__ */ 123#endif /* __MGA_SAREA_DEFINES__ */
124
125 124
126/* Setup registers for 3D context 125/* Setup registers for 3D context
127 */ 126 */
@@ -165,25 +164,25 @@ typedef struct {
165/* General aging mechanism 164/* General aging mechanism
166 */ 165 */
167typedef struct { 166typedef struct {
168 unsigned int head; /* Position of head pointer */ 167 unsigned int head; /* Position of head pointer */
169 unsigned int wrap; /* Primary DMA wrap count */ 168 unsigned int wrap; /* Primary DMA wrap count */
170} drm_mga_age_t; 169} drm_mga_age_t;
171 170
172typedef struct _drm_mga_sarea { 171typedef struct _drm_mga_sarea {
173 /* The channel for communication of state information to the kernel 172 /* The channel for communication of state information to the kernel
174 * on firing a vertex dma buffer. 173 * on firing a vertex dma buffer.
175 */ 174 */
176 drm_mga_context_regs_t context_state; 175 drm_mga_context_regs_t context_state;
177 drm_mga_server_regs_t server_state; 176 drm_mga_server_regs_t server_state;
178 drm_mga_texture_regs_t tex_state[2]; 177 drm_mga_texture_regs_t tex_state[2];
179 unsigned int warp_pipe; 178 unsigned int warp_pipe;
180 unsigned int dirty; 179 unsigned int dirty;
181 unsigned int vertsize; 180 unsigned int vertsize;
182 181
183 /* The current cliprects, or a subset thereof. 182 /* The current cliprects, or a subset thereof.
184 */ 183 */
185 drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS]; 184 drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS];
186 unsigned int nbox; 185 unsigned int nbox;
187 186
188 /* Information about the most recently used 3d drawable. The 187 /* Information about the most recently used 3d drawable. The
189 * client fills in the req_* fields, the server fills in the 188 * client fills in the req_* fields, the server fills in the
@@ -192,18 +191,18 @@ typedef struct _drm_mga_sarea {
192 * The client clears the exported_drawable field before 191 * The client clears the exported_drawable field before
193 * clobbering the boxes data. 192 * clobbering the boxes data.
194 */ 193 */
195 unsigned int req_drawable; /* the X drawable id */ 194 unsigned int req_drawable; /* the X drawable id */
196 unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */ 195 unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */
197 196
198 unsigned int exported_drawable; 197 unsigned int exported_drawable;
199 unsigned int exported_index; 198 unsigned int exported_index;
200 unsigned int exported_stamp; 199 unsigned int exported_stamp;
201 unsigned int exported_buffers; 200 unsigned int exported_buffers;
202 unsigned int exported_nfront; 201 unsigned int exported_nfront;
203 unsigned int exported_nback; 202 unsigned int exported_nback;
204 int exported_back_x, exported_front_x, exported_w; 203 int exported_back_x, exported_front_x, exported_w;
205 int exported_back_y, exported_front_y, exported_h; 204 int exported_back_y, exported_front_y, exported_h;
206 drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS]; 205 drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS];
207 206
208 /* Counters for aging textures and for client-side throttling. 207 /* Counters for aging textures and for client-side throttling.
209 */ 208 */
@@ -211,21 +210,20 @@ typedef struct _drm_mga_sarea {
211 unsigned int last_wrap; 210 unsigned int last_wrap;
212 211
213 drm_mga_age_t last_frame; 212 drm_mga_age_t last_frame;
214 unsigned int last_enqueue; /* last time a buffer was enqueued */ 213 unsigned int last_enqueue; /* last time a buffer was enqueued */
215 unsigned int last_dispatch; /* age of the most recently dispatched buffer */ 214 unsigned int last_dispatch; /* age of the most recently dispatched buffer */
216 unsigned int last_quiescent; /* */ 215 unsigned int last_quiescent; /* */
217 216
218 /* LRU lists for texture memory in agp space and on the card. 217 /* LRU lists for texture memory in agp space and on the card.
219 */ 218 */
220 drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS+1]; 219 drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
221 unsigned int texAge[MGA_NR_TEX_HEAPS]; 220 unsigned int texAge[MGA_NR_TEX_HEAPS];
222 221
223 /* Mechanism to validate card state. 222 /* Mechanism to validate card state.
224 */ 223 */
225 int ctxOwner; 224 int ctxOwner;
226} drm_mga_sarea_t; 225} drm_mga_sarea_t;
227 226
228
229/* MGA specific ioctls 227/* MGA specific ioctls
230 * The device specific ioctl range is 0x40 to 0x79. 228 * The device specific ioctl range is 0x40 to 0x79.
231 */ 229 */
@@ -247,7 +245,6 @@ typedef struct _drm_mga_sarea {
247#define DRM_MGA_WAIT_FENCE 0x0b 245#define DRM_MGA_WAIT_FENCE 0x0b
248#define DRM_MGA_DMA_BOOTSTRAP 0x0c 246#define DRM_MGA_DMA_BOOTSTRAP 0x0c
249 247
250
251#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t) 248#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
252#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t) 249#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t)
253#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET) 250#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET)
@@ -263,33 +260,33 @@ typedef struct _drm_mga_sarea {
263#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t) 260#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
264 261
265typedef struct _drm_mga_warp_index { 262typedef struct _drm_mga_warp_index {
266 int installed; 263 int installed;
267 unsigned long phys_addr; 264 unsigned long phys_addr;
268 int size; 265 int size;
269} drm_mga_warp_index_t; 266} drm_mga_warp_index_t;
270 267
271typedef struct drm_mga_init { 268typedef struct drm_mga_init {
272 enum { 269 enum {
273 MGA_INIT_DMA = 0x01, 270 MGA_INIT_DMA = 0x01,
274 MGA_CLEANUP_DMA = 0x02 271 MGA_CLEANUP_DMA = 0x02
275 } func; 272 } func;
276 273
277 unsigned long sarea_priv_offset; 274 unsigned long sarea_priv_offset;
278 275
279 int chipset; 276 int chipset;
280 int sgram; 277 int sgram;
281 278
282 unsigned int maccess; 279 unsigned int maccess;
283 280
284 unsigned int fb_cpp; 281 unsigned int fb_cpp;
285 unsigned int front_offset, front_pitch; 282 unsigned int front_offset, front_pitch;
286 unsigned int back_offset, back_pitch; 283 unsigned int back_offset, back_pitch;
287 284
288 unsigned int depth_cpp; 285 unsigned int depth_cpp;
289 unsigned int depth_offset, depth_pitch; 286 unsigned int depth_offset, depth_pitch;
290 287
291 unsigned int texture_offset[MGA_NR_TEX_HEAPS]; 288 unsigned int texture_offset[MGA_NR_TEX_HEAPS];
292 unsigned int texture_size[MGA_NR_TEX_HEAPS]; 289 unsigned int texture_size[MGA_NR_TEX_HEAPS];
293 290
294 unsigned long fb_offset; 291 unsigned long fb_offset;
295 unsigned long mmio_offset; 292 unsigned long mmio_offset;
@@ -302,64 +299,59 @@ typedef struct drm_mga_init {
302typedef struct drm_mga_dma_bootstrap { 299typedef struct drm_mga_dma_bootstrap {
303 /** 300 /**
304 * \name AGP texture region 301 * \name AGP texture region
305 * 302 *
306 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will 303 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will
307 * be filled in with the actual AGP texture settings. 304 * be filled in with the actual AGP texture settings.
308 * 305 *
309 * \warning 306 * \warning
310 * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode 307 * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode
311 * is zero, it means that PCI memory (most likely through the use of 308 * is zero, it means that PCI memory (most likely through the use of
312 * an IOMMU) is being used for "AGP" textures. 309 * an IOMMU) is being used for "AGP" textures.
313 */ 310 */
314 /*@{*/ 311 /*@{ */
315 unsigned long texture_handle; /**< Handle used to map AGP textures. */ 312 unsigned long texture_handle; /**< Handle used to map AGP textures. */
316 uint32_t texture_size; /**< Size of the AGP texture region. */ 313 uint32_t texture_size; /**< Size of the AGP texture region. */
317 /*@}*/ 314 /*@} */
318
319 315
320 /** 316 /**
321 * Requested size of the primary DMA region. 317 * Requested size of the primary DMA region.
322 * 318 *
323 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be 319 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
324 * filled in with the actual AGP mode. If AGP was not available 320 * filled in with the actual AGP mode. If AGP was not available
325 */ 321 */
326 uint32_t primary_size; 322 uint32_t primary_size;
327 323
328
329 /** 324 /**
330 * Requested number of secondary DMA buffers. 325 * Requested number of secondary DMA buffers.
331 * 326 *
332 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be 327 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
333 * filled in with the actual number of secondary DMA buffers 328 * filled in with the actual number of secondary DMA buffers
334 * allocated. Particularly when PCI DMA is used, this may be 329 * allocated. Particularly when PCI DMA is used, this may be
335 * (subtantially) less than the number requested. 330 * (subtantially) less than the number requested.
336 */ 331 */
337 uint32_t secondary_bin_count; 332 uint32_t secondary_bin_count;
338 333
339
340 /** 334 /**
341 * Requested size of each secondary DMA buffer. 335 * Requested size of each secondary DMA buffer.
342 * 336 *
343 * While the kernel \b is free to reduce 337 * While the kernel \b is free to reduce
344 * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed 338 * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed
345 * to reduce dma_mga_dma_bootstrap::secondary_bin_size. 339 * to reduce dma_mga_dma_bootstrap::secondary_bin_size.
346 */ 340 */
347 uint32_t secondary_bin_size; 341 uint32_t secondary_bin_size;
348 342
349
350 /** 343 /**
351 * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X, 344 * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X,
352 * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is 345 * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is
353 * zero, it means that PCI DMA should be used, even if AGP is 346 * zero, it means that PCI DMA should be used, even if AGP is
354 * possible. 347 * possible.
355 * 348 *
356 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be 349 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
357 * filled in with the actual AGP mode. If AGP was not available 350 * filled in with the actual AGP mode. If AGP was not available
358 * (i.e., PCI DMA was used), this value will be zero. 351 * (i.e., PCI DMA was used), this value will be zero.
359 */ 352 */
360 uint32_t agp_mode; 353 uint32_t agp_mode;
361 354
362
363 /** 355 /**
364 * Desired AGP GART size, measured in megabytes. 356 * Desired AGP GART size, measured in megabytes.
365 */ 357 */
@@ -375,16 +367,16 @@ typedef struct drm_mga_clear {
375} drm_mga_clear_t; 367} drm_mga_clear_t;
376 368
377typedef struct drm_mga_vertex { 369typedef struct drm_mga_vertex {
378 int idx; /* buffer to queue */ 370 int idx; /* buffer to queue */
379 int used; /* bytes in use */ 371 int used; /* bytes in use */
380 int discard; /* client finished with buffer? */ 372 int discard; /* client finished with buffer? */
381} drm_mga_vertex_t; 373} drm_mga_vertex_t;
382 374
383typedef struct drm_mga_indices { 375typedef struct drm_mga_indices {
384 int idx; /* buffer to queue */ 376 int idx; /* buffer to queue */
385 unsigned int start; 377 unsigned int start;
386 unsigned int end; 378 unsigned int end;
387 int discard; /* client finished with buffer? */ 379 int discard; /* client finished with buffer? */
388} drm_mga_indices_t; 380} drm_mga_indices_t;
389 381
390typedef struct drm_mga_iload { 382typedef struct drm_mga_iload {
@@ -400,12 +392,12 @@ typedef struct _drm_mga_blit {
400 int src_pitch, dst_pitch; 392 int src_pitch, dst_pitch;
401 int delta_sx, delta_sy; 393 int delta_sx, delta_sy;
402 int delta_dx, delta_dy; 394 int delta_dx, delta_dy;
403 int height, ydir; /* flip image vertically */ 395 int height, ydir; /* flip image vertically */
404 int source_pitch, dest_pitch; 396 int source_pitch, dest_pitch;
405} drm_mga_blit_t; 397} drm_mga_blit_t;
406 398
407/* 3.1: An ioctl to get parameters that aren't available to the 3d 399/* 3.1: An ioctl to get parameters that aren't available to the 3d
408 * client any other way. 400 * client any other way.
409 */ 401 */
410#define MGA_PARAM_IRQ_NR 1 402#define MGA_PARAM_IRQ_NR 1
411 403
diff --git a/drivers/char/drm/mga_drv.c b/drivers/char/drm/mga_drv.c
index daabbba3b297..220037a91c09 100644
--- a/drivers/char/drm/mga_drv.c
+++ b/drivers/char/drm/mga_drv.c
@@ -35,14 +35,13 @@
35#include "mga_drm.h" 35#include "mga_drm.h"
36#include "mga_drv.h" 36#include "mga_drv.h"
37 37
38
39#include "drm_pciids.h" 38#include "drm_pciids.h"
40 39
41static int mga_driver_device_is_agp(drm_device_t * dev); 40static int mga_driver_device_is_agp(drm_device_t * dev);
42static int postinit( struct drm_device *dev, unsigned long flags ) 41static int postinit(struct drm_device *dev, unsigned long flags)
43{ 42{
44 drm_mga_private_t * const dev_priv = 43 drm_mga_private_t *const dev_priv =
45 (drm_mga_private_t *) dev->dev_private; 44 (drm_mga_private_t *) dev->dev_private;
46 45
47 dev_priv->mmio_base = pci_resource_start(dev->pdev, 1); 46 dev_priv->mmio_base = pci_resource_start(dev->pdev, 1);
48 dev_priv->mmio_size = pci_resource_len(dev->pdev, 1); 47 dev_priv->mmio_size = pci_resource_len(dev->pdev, 1);
@@ -52,28 +51,26 @@ static int postinit( struct drm_device *dev, unsigned long flags )
52 dev->types[7] = _DRM_STAT_PRIMARY; 51 dev->types[7] = _DRM_STAT_PRIMARY;
53 dev->types[8] = _DRM_STAT_SECONDARY; 52 dev->types[8] = _DRM_STAT_SECONDARY;
54 53
55 DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", 54 DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n",
56 DRIVER_NAME, 55 DRIVER_NAME,
57 DRIVER_MAJOR, 56 DRIVER_MAJOR,
58 DRIVER_MINOR, 57 DRIVER_MINOR,
59 DRIVER_PATCHLEVEL, 58 DRIVER_PATCHLEVEL,
60 DRIVER_DATE, 59 DRIVER_DATE, dev->primary.minor, pci_pretty_name(dev->pdev)
61 dev->primary.minor, 60 );
62 pci_pretty_name(dev->pdev)
63 );
64 return 0; 61 return 0;
65} 62}
66 63
67static int version( drm_version_t *version ) 64static int version(drm_version_t * version)
68{ 65{
69 int len; 66 int len;
70 67
71 version->version_major = DRIVER_MAJOR; 68 version->version_major = DRIVER_MAJOR;
72 version->version_minor = DRIVER_MINOR; 69 version->version_minor = DRIVER_MINOR;
73 version->version_patchlevel = DRIVER_PATCHLEVEL; 70 version->version_patchlevel = DRIVER_PATCHLEVEL;
74 DRM_COPY( version->name, DRIVER_NAME ); 71 DRM_COPY(version->name, DRIVER_NAME);
75 DRM_COPY( version->date, DRIVER_DATE ); 72 DRM_COPY(version->date, DRIVER_DATE);
76 DRM_COPY( version->desc, DRIVER_DESC ); 73 DRM_COPY(version->desc, DRIVER_DESC);
77 return 0; 74 return 0;
78} 75}
79 76
@@ -85,7 +82,10 @@ extern drm_ioctl_desc_t mga_ioctls[];
85extern int mga_max_ioctl; 82extern int mga_max_ioctl;
86 83
87static struct drm_driver driver = { 84static struct drm_driver driver = {
88 .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL, 85 .driver_features =
86 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR |
87 DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
88 DRIVER_IRQ_VBL,
89 .preinit = mga_driver_preinit, 89 .preinit = mga_driver_preinit,
90 .postcleanup = mga_driver_postcleanup, 90 .postcleanup = mga_driver_postcleanup,
91 .pretakedown = mga_driver_pretakedown, 91 .pretakedown = mga_driver_pretakedown,
@@ -104,21 +104,21 @@ static struct drm_driver driver = {
104 .ioctls = mga_ioctls, 104 .ioctls = mga_ioctls,
105 .dma_ioctl = mga_dma_buffers, 105 .dma_ioctl = mga_dma_buffers,
106 .fops = { 106 .fops = {
107 .owner = THIS_MODULE, 107 .owner = THIS_MODULE,
108 .open = drm_open, 108 .open = drm_open,
109 .release = drm_release, 109 .release = drm_release,
110 .ioctl = drm_ioctl, 110 .ioctl = drm_ioctl,
111 .mmap = drm_mmap, 111 .mmap = drm_mmap,
112 .poll = drm_poll, 112 .poll = drm_poll,
113 .fasync = drm_fasync, 113 .fasync = drm_fasync,
114#ifdef CONFIG_COMPAT 114#ifdef CONFIG_COMPAT
115 .compat_ioctl = mga_compat_ioctl, 115 .compat_ioctl = mga_compat_ioctl,
116#endif 116#endif
117 }, 117 },
118 .pci_driver = { 118 .pci_driver = {
119 .name = DRIVER_NAME, 119 .name = DRIVER_NAME,
120 .id_table = pciidlist, 120 .id_table = pciidlist,
121 } 121 }
122}; 122};
123 123
124static int __init mga_init(void) 124static int __init mga_init(void)
@@ -135,8 +135,8 @@ static void __exit mga_exit(void)
135module_init(mga_init); 135module_init(mga_init);
136module_exit(mga_exit); 136module_exit(mga_exit);
137 137
138MODULE_AUTHOR( DRIVER_AUTHOR ); 138MODULE_AUTHOR(DRIVER_AUTHOR);
139MODULE_DESCRIPTION( DRIVER_DESC ); 139MODULE_DESCRIPTION(DRIVER_DESC);
140MODULE_LICENSE("GPL and additional rights"); 140MODULE_LICENSE("GPL and additional rights");
141 141
142/** 142/**
@@ -153,8 +153,7 @@ MODULE_LICENSE("GPL and additional rights");
153 */ 153 */
154int mga_driver_device_is_agp(drm_device_t * dev) 154int mga_driver_device_is_agp(drm_device_t * dev)
155{ 155{
156 const struct pci_dev * const pdev = dev->pdev; 156 const struct pci_dev *const pdev = dev->pdev;
157
158 157
159 /* There are PCI versions of the G450. These cards have the 158 /* There are PCI versions of the G450. These cards have the
160 * same PCI ID as the AGP G450, but have an additional PCI-to-PCI 159 * same PCI ID as the AGP G450, but have an additional PCI-to-PCI
@@ -164,10 +163,10 @@ int mga_driver_device_is_agp(drm_device_t * dev)
164 * device is 0x0021 (HB6 Universal PCI-PCI bridge), we reject the 163 * device is 0x0021 (HB6 Universal PCI-PCI bridge), we reject the
165 * device. 164 * device.
166 */ 165 */
167 166
168 if ( (pdev->device == 0x0525) 167 if ((pdev->device == 0x0525)
169 && (pdev->bus->self->vendor == 0x3388) 168 && (pdev->bus->self->vendor == 0x3388)
170 && (pdev->bus->self->device == 0x0021) ) { 169 && (pdev->bus->self->device == 0x0021)) {
171 return 0; 170 return 0;
172 } 171 }
173 172
diff --git a/drivers/char/drm/mga_drv.h b/drivers/char/drm/mga_drv.h
index b22fdbd4f830..05f0f913dedd 100644
--- a/drivers/char/drm/mga_drv.h
+++ b/drivers/char/drm/mga_drv.h
@@ -62,14 +62,14 @@ typedef struct drm_mga_primary_buffer {
62} drm_mga_primary_buffer_t; 62} drm_mga_primary_buffer_t;
63 63
64typedef struct drm_mga_freelist { 64typedef struct drm_mga_freelist {
65 struct drm_mga_freelist *next; 65 struct drm_mga_freelist *next;
66 struct drm_mga_freelist *prev; 66 struct drm_mga_freelist *prev;
67 drm_mga_age_t age; 67 drm_mga_age_t age;
68 drm_buf_t *buf; 68 drm_buf_t *buf;
69} drm_mga_freelist_t; 69} drm_mga_freelist_t;
70 70
71typedef struct { 71typedef struct {
72 drm_mga_freelist_t *list_entry; 72 drm_mga_freelist_t *list_entry;
73 int discard; 73 int discard;
74 int dispatched; 74 int dispatched;
75} drm_mga_buf_priv_t; 75} drm_mga_buf_priv_t;
@@ -78,8 +78,8 @@ typedef struct drm_mga_private {
78 drm_mga_primary_buffer_t prim; 78 drm_mga_primary_buffer_t prim;
79 drm_mga_sarea_t *sarea_priv; 79 drm_mga_sarea_t *sarea_priv;
80 80
81 drm_mga_freelist_t *head; 81 drm_mga_freelist_t *head;
82 drm_mga_freelist_t *tail; 82 drm_mga_freelist_t *tail;
83 83
84 unsigned int warp_pipe; 84 unsigned int warp_pipe;
85 unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES]; 85 unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
@@ -109,13 +109,13 @@ typedef struct drm_mga_private {
109 109
110 /** 110 /**
111 * \name MMIO region parameters. 111 * \name MMIO region parameters.
112 * 112 *
113 * \sa drm_mga_private_t::mmio 113 * \sa drm_mga_private_t::mmio
114 */ 114 */
115 /*@{*/ 115 /*@{ */
116 u32 mmio_base; /**< Bus address of base of MMIO. */ 116 u32 mmio_base; /**< Bus address of base of MMIO. */
117 u32 mmio_size; /**< Size of the MMIO region. */ 117 u32 mmio_size; /**< Size of the MMIO region. */
118 /*@}*/ 118 /*@} */
119 119
120 u32 clear_cmd; 120 u32 clear_cmd;
121 u32 maccess; 121 u32 maccess;
@@ -143,7 +143,7 @@ typedef struct drm_mga_private {
143 drm_local_map_t *warp; 143 drm_local_map_t *warp;
144 drm_local_map_t *primary; 144 drm_local_map_t *primary;
145 drm_local_map_t *agp_textures; 145 drm_local_map_t *agp_textures;
146 146
147 DRM_AGP_MEM *agp_mem; 147 DRM_AGP_MEM *agp_mem;
148 unsigned int agp_pages; 148 unsigned int agp_pages;
149} drm_mga_private_t; 149} drm_mga_private_t;
@@ -165,7 +165,7 @@ extern void mga_do_dma_flush(drm_mga_private_t * dev_priv);
165extern void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv); 165extern void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv);
166extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv); 166extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv);
167 167
168extern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf ); 168extern int mga_freelist_put(drm_device_t * dev, drm_buf_t * buf);
169 169
170 /* mga_warp.c */ 170 /* mga_warp.c */
171extern unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv); 171extern unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv);
@@ -196,7 +196,7 @@ extern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
196#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0) 196#define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0)
197#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0) 197#define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0)
198 198
199static inline u32 _MGA_READ(u32 *addr) 199static inline u32 _MGA_READ(u32 * addr)
200{ 200{
201 DRM_MEMORYBARRIER(); 201 DRM_MEMORYBARRIER();
202 return *(volatile u32 *)addr; 202 return *(volatile u32 *)addr;
@@ -218,8 +218,6 @@ static inline u32 _MGA_READ(u32 *addr)
218#define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80) 218#define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80)
219#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r)) 219#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
220 220
221
222
223/* ================================================================ 221/* ================================================================
224 * Helper macross... 222 * Helper macross...
225 */ 223 */
@@ -261,7 +259,6 @@ do { \
261 } \ 259 } \
262} while (0) 260} while (0)
263 261
264
265/* ================================================================ 262/* ================================================================
266 * Primary DMA command stream 263 * Primary DMA command stream
267 */ 264 */
@@ -346,7 +343,6 @@ do { \
346 write += DMA_BLOCK_SIZE; \ 343 write += DMA_BLOCK_SIZE; \
347} while (0) 344} while (0)
348 345
349
350/* Buffer aging via primary DMA stream head pointer. 346/* Buffer aging via primary DMA stream head pointer.
351 */ 347 */
352 348
@@ -373,7 +369,6 @@ do { \
373 } \ 369 } \
374} while (0) 370} while (0)
375 371
376
377#define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \ 372#define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \
378 MGA_DWGENGSTS | \ 373 MGA_DWGENGSTS | \
379 MGA_ENDPRDMASTS) 374 MGA_ENDPRDMASTS)
@@ -382,8 +377,6 @@ do { \
382 377
383#define MGA_DMA_DEBUG 0 378#define MGA_DMA_DEBUG 0
384 379
385
386
387/* A reduced set of the mga registers. 380/* A reduced set of the mga registers.
388 */ 381 */
389#define MGA_CRTC_INDEX 0x1fd4 382#define MGA_CRTC_INDEX 0x1fd4
@@ -644,7 +637,6 @@ do { \
644# define MGA_G400_WR_MAGIC (1 << 6) 637# define MGA_G400_WR_MAGIC (1 << 6)
645# define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */ 638# define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */
646 639
647
648#define MGA_ILOAD_ALIGN 64 640#define MGA_ILOAD_ALIGN 64
649#define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1) 641#define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1)
650 642
@@ -679,10 +671,10 @@ do { \
679 671
680/* Simple idle test. 672/* Simple idle test.
681 */ 673 */
682static __inline__ int mga_is_idle( drm_mga_private_t *dev_priv ) 674static __inline__ int mga_is_idle(drm_mga_private_t * dev_priv)
683{ 675{
684 u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; 676 u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
685 return ( status == MGA_ENDPRDMASTS ); 677 return (status == MGA_ENDPRDMASTS);
686} 678}
687 679
688#endif 680#endif
diff --git a/drivers/char/drm/mga_ioc32.c b/drivers/char/drm/mga_ioc32.c
index 77d738e75a4d..24a9d4e86af0 100644
--- a/drivers/char/drm/mga_ioc32.c
+++ b/drivers/char/drm/mga_ioc32.c
@@ -39,17 +39,17 @@
39 39
40typedef struct drm32_mga_init { 40typedef struct drm32_mga_init {
41 int func; 41 int func;
42 u32 sarea_priv_offset; 42 u32 sarea_priv_offset;
43 int chipset; 43 int chipset;
44 int sgram; 44 int sgram;
45 unsigned int maccess; 45 unsigned int maccess;
46 unsigned int fb_cpp; 46 unsigned int fb_cpp;
47 unsigned int front_offset, front_pitch; 47 unsigned int front_offset, front_pitch;
48 unsigned int back_offset, back_pitch; 48 unsigned int back_offset, back_pitch;
49 unsigned int depth_cpp; 49 unsigned int depth_cpp;
50 unsigned int depth_offset, depth_pitch; 50 unsigned int depth_offset, depth_pitch;
51 unsigned int texture_offset[MGA_NR_TEX_HEAPS]; 51 unsigned int texture_offset[MGA_NR_TEX_HEAPS];
52 unsigned int texture_size[MGA_NR_TEX_HEAPS]; 52 unsigned int texture_size[MGA_NR_TEX_HEAPS];
53 u32 fb_offset; 53 u32 fb_offset;
54 u32 mmio_offset; 54 u32 mmio_offset;
55 u32 status_offset; 55 u32 status_offset;
@@ -64,10 +64,10 @@ static int compat_mga_init(struct file *file, unsigned int cmd,
64 drm_mga_init32_t init32; 64 drm_mga_init32_t init32;
65 drm_mga_init_t __user *init; 65 drm_mga_init_t __user *init;
66 int err = 0, i; 66 int err = 0, i;
67 67
68 if (copy_from_user(&init32, (void __user *)arg, sizeof(init32))) 68 if (copy_from_user(&init32, (void __user *)arg, sizeof(init32)))
69 return -EFAULT; 69 return -EFAULT;
70 70
71 init = compat_alloc_user_space(sizeof(*init)); 71 init = compat_alloc_user_space(sizeof(*init));
72 if (!access_ok(VERIFY_WRITE, init, sizeof(*init)) 72 if (!access_ok(VERIFY_WRITE, init, sizeof(*init))
73 || __put_user(init32.func, &init->func) 73 || __put_user(init32.func, &init->func)
@@ -90,42 +90,43 @@ static int compat_mga_init(struct file *file, unsigned int cmd,
90 || __put_user(init32.primary_offset, &init->primary_offset) 90 || __put_user(init32.primary_offset, &init->primary_offset)
91 || __put_user(init32.buffers_offset, &init->buffers_offset)) 91 || __put_user(init32.buffers_offset, &init->buffers_offset))
92 return -EFAULT; 92 return -EFAULT;
93 93
94 for (i=0; i<MGA_NR_TEX_HEAPS; i++) 94 for (i = 0; i < MGA_NR_TEX_HEAPS; i++) {
95 { 95 err |=
96 err |= __put_user(init32.texture_offset[i], &init->texture_offset[i]); 96 __put_user(init32.texture_offset[i],
97 err |= __put_user(init32.texture_size[i], &init->texture_size[i]); 97 &init->texture_offset[i]);
98 err |=
99 __put_user(init32.texture_size[i], &init->texture_size[i]);
98 } 100 }
99 if (err) 101 if (err)
100 return -EFAULT; 102 return -EFAULT;
101 103
102 return drm_ioctl(file->f_dentry->d_inode, file, 104 return drm_ioctl(file->f_dentry->d_inode, file,
103 DRM_IOCTL_MGA_INIT, (unsigned long) init); 105 DRM_IOCTL_MGA_INIT, (unsigned long)init);
104} 106}
105 107
106
107typedef struct drm_mga_getparam32 { 108typedef struct drm_mga_getparam32 {
108 int param; 109 int param;
109 u32 value; 110 u32 value;
110} drm_mga_getparam32_t; 111} drm_mga_getparam32_t;
111 112
112
113static int compat_mga_getparam(struct file *file, unsigned int cmd, 113static int compat_mga_getparam(struct file *file, unsigned int cmd,
114 unsigned long arg) 114 unsigned long arg)
115{ 115{
116 drm_mga_getparam32_t getparam32; 116 drm_mga_getparam32_t getparam32;
117 drm_mga_getparam_t __user *getparam; 117 drm_mga_getparam_t __user *getparam;
118 118
119 if (copy_from_user(&getparam32, (void __user *)arg, sizeof(getparam32))) 119 if (copy_from_user(&getparam32, (void __user *)arg, sizeof(getparam32)))
120 return -EFAULT; 120 return -EFAULT;
121 121
122 getparam = compat_alloc_user_space(sizeof(*getparam)); 122 getparam = compat_alloc_user_space(sizeof(*getparam));
123 if (!access_ok(VERIFY_WRITE, getparam, sizeof(*getparam)) 123 if (!access_ok(VERIFY_WRITE, getparam, sizeof(*getparam))
124 || __put_user(getparam32.param, &getparam->param) 124 || __put_user(getparam32.param, &getparam->param)
125 || __put_user((void __user *)(unsigned long)getparam32.value, &getparam->value)) 125 || __put_user((void __user *)(unsigned long)getparam32.value,
126 &getparam->value))
126 return -EFAULT; 127 return -EFAULT;
127 128
128 return drm_ioctl(file->f_dentry->d_inode, file, 129 return drm_ioctl(file->f_dentry->d_inode, file,
129 DRM_IOCTL_MGA_GETPARAM, (unsigned long)getparam); 130 DRM_IOCTL_MGA_GETPARAM, (unsigned long)getparam);
130} 131}
131 132
@@ -182,14 +183,12 @@ static int compat_mga_dma_bootstrap(struct file *file, unsigned int cmd,
182 &dma_bootstrap->secondary_bin_count) 183 &dma_bootstrap->secondary_bin_count)
183 || __get_user(dma_bootstrap32.secondary_bin_size, 184 || __get_user(dma_bootstrap32.secondary_bin_size,
184 &dma_bootstrap->secondary_bin_size) 185 &dma_bootstrap->secondary_bin_size)
185 || __get_user(dma_bootstrap32.agp_mode, 186 || __get_user(dma_bootstrap32.agp_mode, &dma_bootstrap->agp_mode)
186 &dma_bootstrap->agp_mode) 187 || __get_user(dma_bootstrap32.agp_size, &dma_bootstrap->agp_size))
187 || __get_user(dma_bootstrap32.agp_size,
188 &dma_bootstrap->agp_size))
189 return -EFAULT; 188 return -EFAULT;
190 189
191 if (copy_to_user((void __user *)arg, &dma_bootstrap32, 190 if (copy_to_user((void __user *)arg, &dma_bootstrap32,
192 sizeof(dma_bootstrap32))) 191 sizeof(dma_bootstrap32)))
193 return -EFAULT; 192 return -EFAULT;
194 193
195 return 0; 194 return 0;
@@ -210,8 +209,7 @@ drm_ioctl_compat_t *mga_compat_ioctls[] = {
210 * \param arg user argument. 209 * \param arg user argument.
211 * \return zero on success or negative number on failure. 210 * \return zero on success or negative number on failure.
212 */ 211 */
213long mga_compat_ioctl(struct file *filp, unsigned int cmd, 212long mga_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
214 unsigned long arg)
215{ 213{
216 unsigned int nr = DRM_IOCTL_NR(cmd); 214 unsigned int nr = DRM_IOCTL_NR(cmd);
217 drm_ioctl_compat_t *fn = NULL; 215 drm_ioctl_compat_t *fn = NULL;
@@ -219,13 +217,13 @@ long mga_compat_ioctl(struct file *filp, unsigned int cmd,
219 217
220 if (nr < DRM_COMMAND_BASE) 218 if (nr < DRM_COMMAND_BASE)
221 return drm_compat_ioctl(filp, cmd, arg); 219 return drm_compat_ioctl(filp, cmd, arg);
222 220
223 if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(mga_compat_ioctls)) 221 if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(mga_compat_ioctls))
224 fn = mga_compat_ioctls[nr - DRM_COMMAND_BASE]; 222 fn = mga_compat_ioctls[nr - DRM_COMMAND_BASE];
225 223
226 lock_kernel(); /* XXX for now */ 224 lock_kernel(); /* XXX for now */
227 if (fn != NULL) 225 if (fn != NULL)
228 ret = (*fn)(filp, cmd, arg); 226 ret = (*fn) (filp, cmd, arg);
229 else 227 else
230 ret = drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg); 228 ret = drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg);
231 unlock_kernel(); 229 unlock_kernel();
diff --git a/drivers/char/drm/mga_irq.c b/drivers/char/drm/mga_irq.c
index 52eaa4e788f9..eb9644024172 100644
--- a/drivers/char/drm/mga_irq.c
+++ b/drivers/char/drm/mga_irq.c
@@ -1,7 +1,7 @@
1/* mga_irq.c -- IRQ handling for radeon -*- linux-c -*- 1/* mga_irq.c -- IRQ handling for radeon -*- linux-c -*-
2 * 2 *
3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 * 4 *
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the 5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license. 6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved. 7 * This notice must be preserved.
@@ -35,19 +35,18 @@
35#include "mga_drm.h" 35#include "mga_drm.h"
36#include "mga_drv.h" 36#include "mga_drv.h"
37 37
38irqreturn_t mga_driver_irq_handler( DRM_IRQ_ARGS ) 38irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS)
39{ 39{
40 drm_device_t *dev = (drm_device_t *) arg; 40 drm_device_t *dev = (drm_device_t *) arg;
41 drm_mga_private_t *dev_priv = 41 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
42 (drm_mga_private_t *)dev->dev_private;
43 int status; 42 int status;
44 int handled = 0; 43 int handled = 0;
45 44
46 status = MGA_READ(MGA_STATUS); 45 status = MGA_READ(MGA_STATUS);
47 46
48 /* VBLANK interrupt */ 47 /* VBLANK interrupt */
49 if ( status & MGA_VLINEPEN ) { 48 if (status & MGA_VLINEPEN) {
50 MGA_WRITE( MGA_ICLEAR, MGA_VLINEICLR ); 49 MGA_WRITE(MGA_ICLEAR, MGA_VLINEICLR);
51 atomic_inc(&dev->vbl_received); 50 atomic_inc(&dev->vbl_received);
52 DRM_WAKEUP(&dev->vbl_queue); 51 DRM_WAKEUP(&dev->vbl_queue);
53 drm_vbl_send_signals(dev); 52 drm_vbl_send_signals(dev);
@@ -57,15 +56,14 @@ irqreturn_t mga_driver_irq_handler( DRM_IRQ_ARGS )
57 /* SOFTRAP interrupt */ 56 /* SOFTRAP interrupt */
58 if (status & MGA_SOFTRAPEN) { 57 if (status & MGA_SOFTRAPEN) {
59 const u32 prim_start = MGA_READ(MGA_PRIMADDRESS); 58 const u32 prim_start = MGA_READ(MGA_PRIMADDRESS);
60 const u32 prim_end = MGA_READ(MGA_PRIMEND); 59 const u32 prim_end = MGA_READ(MGA_PRIMEND);
61
62 60
63 MGA_WRITE(MGA_ICLEAR, MGA_SOFTRAPICLR); 61 MGA_WRITE(MGA_ICLEAR, MGA_SOFTRAPICLR);
64 62
65 /* In addition to clearing the interrupt-pending bit, we 63 /* In addition to clearing the interrupt-pending bit, we
66 * have to write to MGA_PRIMEND to re-start the DMA operation. 64 * have to write to MGA_PRIMEND to re-start the DMA operation.
67 */ 65 */
68 if ( (prim_start & ~0x03) != (prim_end & ~0x03) ) { 66 if ((prim_start & ~0x03) != (prim_end & ~0x03)) {
69 MGA_WRITE(MGA_PRIMEND, prim_end); 67 MGA_WRITE(MGA_PRIMEND, prim_end);
70 } 68 }
71 69
@@ -74,24 +72,24 @@ irqreturn_t mga_driver_irq_handler( DRM_IRQ_ARGS )
74 handled = 1; 72 handled = 1;
75 } 73 }
76 74
77 if ( handled ) { 75 if (handled) {
78 return IRQ_HANDLED; 76 return IRQ_HANDLED;
79 } 77 }
80 return IRQ_NONE; 78 return IRQ_NONE;
81} 79}
82 80
83int mga_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence) 81int mga_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence)
84{ 82{
85 unsigned int cur_vblank; 83 unsigned int cur_vblank;
86 int ret = 0; 84 int ret = 0;
87 85
88 /* Assume that the user has missed the current sequence number 86 /* Assume that the user has missed the current sequence number
89 * by about a day rather than she wants to wait for years 87 * by about a day rather than she wants to wait for years
90 * using vertical blanks... 88 * using vertical blanks...
91 */ 89 */
92 DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, 90 DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
93 ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) ) 91 (((cur_vblank = atomic_read(&dev->vbl_received))
94 - *sequence ) <= (1<<23) ) ); 92 - *sequence) <= (1 << 23)));
95 93
96 *sequence = cur_vblank; 94 *sequence = cur_vblank;
97 95
@@ -122,29 +120,29 @@ void mga_driver_irq_preinstall(drm_device_t * dev)
122 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; 120 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
123 121
124 /* Disable *all* interrupts */ 122 /* Disable *all* interrupts */
125 MGA_WRITE( MGA_IEN, 0 ); 123 MGA_WRITE(MGA_IEN, 0);
126 /* Clear bits if they're already high */ 124 /* Clear bits if they're already high */
127 MGA_WRITE( MGA_ICLEAR, ~0 ); 125 MGA_WRITE(MGA_ICLEAR, ~0);
128} 126}
129 127
130void mga_driver_irq_postinstall(drm_device_t * dev) 128void mga_driver_irq_postinstall(drm_device_t * dev)
131{ 129{
132 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; 130 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
133 131
134 DRM_INIT_WAITQUEUE( &dev_priv->fence_queue ); 132 DRM_INIT_WAITQUEUE(&dev_priv->fence_queue);
135 133
136 /* Turn on vertical blank interrupt and soft trap interrupt. */ 134 /* Turn on vertical blank interrupt and soft trap interrupt. */
137 MGA_WRITE(MGA_IEN, MGA_VLINEIEN | MGA_SOFTRAPEN); 135 MGA_WRITE(MGA_IEN, MGA_VLINEIEN | MGA_SOFTRAPEN);
138} 136}
139 137
140void mga_driver_irq_uninstall( drm_device_t *dev ) { 138void mga_driver_irq_uninstall(drm_device_t * dev)
141 drm_mga_private_t *dev_priv = 139{
142 (drm_mga_private_t *)dev->dev_private; 140 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
143 if (!dev_priv) 141 if (!dev_priv)
144 return; 142 return;
145 143
146 /* Disable *all* interrupts */ 144 /* Disable *all* interrupts */
147 MGA_WRITE(MGA_IEN, 0); 145 MGA_WRITE(MGA_IEN, 0);
148 146
149 dev->irq_enabled = 0; 147 dev->irq_enabled = 0;
150} 148}
diff --git a/drivers/char/drm/mga_state.c b/drivers/char/drm/mga_state.c
index 05bbb4719376..15114f8aa467 100644
--- a/drivers/char/drm/mga_state.c
+++ b/drivers/char/drm/mga_state.c
@@ -41,15 +41,15 @@
41 * DMA hardware state programming functions 41 * DMA hardware state programming functions
42 */ 42 */
43 43
44static void mga_emit_clip_rect( drm_mga_private_t *dev_priv, 44static void mga_emit_clip_rect(drm_mga_private_t * dev_priv,
45 drm_clip_rect_t *box ) 45 drm_clip_rect_t * box)
46{ 46{
47 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 47 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
48 drm_mga_context_regs_t *ctx = &sarea_priv->context_state; 48 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
49 unsigned int pitch = dev_priv->front_pitch; 49 unsigned int pitch = dev_priv->front_pitch;
50 DMA_LOCALS; 50 DMA_LOCALS;
51 51
52 BEGIN_DMA( 2 ); 52 BEGIN_DMA(2);
53 53
54 /* Force reset of DWGCTL on G400 (eliminates clip disable bit). 54 /* Force reset of DWGCTL on G400 (eliminates clip disable bit).
55 */ 55 */
@@ -61,101 +61,90 @@ static void mga_emit_clip_rect( drm_mga_private_t *dev_priv,
61 } 61 }
62 DMA_BLOCK(MGA_DMAPAD, 0x00000000, 62 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
63 MGA_CXBNDRY, ((box->x2 - 1) << 16) | box->x1, 63 MGA_CXBNDRY, ((box->x2 - 1) << 16) | box->x1,
64 MGA_YTOP, box->y1 * pitch, 64 MGA_YTOP, box->y1 * pitch, MGA_YBOT, (box->y2 - 1) * pitch);
65 MGA_YBOT, (box->y2 - 1) * pitch);
66 65
67 ADVANCE_DMA(); 66 ADVANCE_DMA();
68} 67}
69 68
70static __inline__ void mga_g200_emit_context( drm_mga_private_t *dev_priv ) 69static __inline__ void mga_g200_emit_context(drm_mga_private_t * dev_priv)
71{ 70{
72 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 71 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
73 drm_mga_context_regs_t *ctx = &sarea_priv->context_state; 72 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
74 DMA_LOCALS; 73 DMA_LOCALS;
75 74
76 BEGIN_DMA( 3 ); 75 BEGIN_DMA(3);
77 76
78 DMA_BLOCK( MGA_DSTORG, ctx->dstorg, 77 DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
79 MGA_MACCESS, ctx->maccess, 78 MGA_MACCESS, ctx->maccess,
80 MGA_PLNWT, ctx->plnwt, 79 MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl);
81 MGA_DWGCTL, ctx->dwgctl );
82 80
83 DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl, 81 DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
84 MGA_FOGCOL, ctx->fogcolor, 82 MGA_FOGCOL, ctx->fogcolor,
85 MGA_WFLAG, ctx->wflag, 83 MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset);
86 MGA_ZORG, dev_priv->depth_offset );
87 84
88 DMA_BLOCK( MGA_FCOL, ctx->fcol, 85 DMA_BLOCK(MGA_FCOL, ctx->fcol,
89 MGA_DMAPAD, 0x00000000, 86 MGA_DMAPAD, 0x00000000,
90 MGA_DMAPAD, 0x00000000, 87 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
91 MGA_DMAPAD, 0x00000000 );
92 88
93 ADVANCE_DMA(); 89 ADVANCE_DMA();
94} 90}
95 91
96static __inline__ void mga_g400_emit_context( drm_mga_private_t *dev_priv ) 92static __inline__ void mga_g400_emit_context(drm_mga_private_t * dev_priv)
97{ 93{
98 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 94 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
99 drm_mga_context_regs_t *ctx = &sarea_priv->context_state; 95 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
100 DMA_LOCALS; 96 DMA_LOCALS;
101 97
102 BEGIN_DMA( 4 ); 98 BEGIN_DMA(4);
103 99
104 DMA_BLOCK( MGA_DSTORG, ctx->dstorg, 100 DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
105 MGA_MACCESS, ctx->maccess, 101 MGA_MACCESS, ctx->maccess,
106 MGA_PLNWT, ctx->plnwt, 102 MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl);
107 MGA_DWGCTL, ctx->dwgctl );
108 103
109 DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl, 104 DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
110 MGA_FOGCOL, ctx->fogcolor, 105 MGA_FOGCOL, ctx->fogcolor,
111 MGA_WFLAG, ctx->wflag, 106 MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset);
112 MGA_ZORG, dev_priv->depth_offset );
113 107
114 DMA_BLOCK( MGA_WFLAG1, ctx->wflag, 108 DMA_BLOCK(MGA_WFLAG1, ctx->wflag,
115 MGA_TDUALSTAGE0, ctx->tdualstage0, 109 MGA_TDUALSTAGE0, ctx->tdualstage0,
116 MGA_TDUALSTAGE1, ctx->tdualstage1, 110 MGA_TDUALSTAGE1, ctx->tdualstage1, MGA_FCOL, ctx->fcol);
117 MGA_FCOL, ctx->fcol );
118 111
119 DMA_BLOCK( MGA_STENCIL, ctx->stencil, 112 DMA_BLOCK(MGA_STENCIL, ctx->stencil,
120 MGA_STENCILCTL, ctx->stencilctl, 113 MGA_STENCILCTL, ctx->stencilctl,
121 MGA_DMAPAD, 0x00000000, 114 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
122 MGA_DMAPAD, 0x00000000 );
123 115
124 ADVANCE_DMA(); 116 ADVANCE_DMA();
125} 117}
126 118
127static __inline__ void mga_g200_emit_tex0( drm_mga_private_t *dev_priv ) 119static __inline__ void mga_g200_emit_tex0(drm_mga_private_t * dev_priv)
128{ 120{
129 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 121 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
130 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0]; 122 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
131 DMA_LOCALS; 123 DMA_LOCALS;
132 124
133 BEGIN_DMA( 4 ); 125 BEGIN_DMA(4);
134 126
135 DMA_BLOCK( MGA_TEXCTL2, tex->texctl2, 127 DMA_BLOCK(MGA_TEXCTL2, tex->texctl2,
136 MGA_TEXCTL, tex->texctl, 128 MGA_TEXCTL, tex->texctl,
137 MGA_TEXFILTER, tex->texfilter, 129 MGA_TEXFILTER, tex->texfilter,
138 MGA_TEXBORDERCOL, tex->texbordercol ); 130 MGA_TEXBORDERCOL, tex->texbordercol);
139 131
140 DMA_BLOCK( MGA_TEXORG, tex->texorg, 132 DMA_BLOCK(MGA_TEXORG, tex->texorg,
141 MGA_TEXORG1, tex->texorg1, 133 MGA_TEXORG1, tex->texorg1,
142 MGA_TEXORG2, tex->texorg2, 134 MGA_TEXORG2, tex->texorg2, MGA_TEXORG3, tex->texorg3);
143 MGA_TEXORG3, tex->texorg3 );
144 135
145 DMA_BLOCK( MGA_TEXORG4, tex->texorg4, 136 DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
146 MGA_TEXWIDTH, tex->texwidth, 137 MGA_TEXWIDTH, tex->texwidth,
147 MGA_TEXHEIGHT, tex->texheight, 138 MGA_TEXHEIGHT, tex->texheight, MGA_WR24, tex->texwidth);
148 MGA_WR24, tex->texwidth );
149 139
150 DMA_BLOCK( MGA_WR34, tex->texheight, 140 DMA_BLOCK(MGA_WR34, tex->texheight,
151 MGA_TEXTRANS, 0x0000ffff, 141 MGA_TEXTRANS, 0x0000ffff,
152 MGA_TEXTRANSHIGH, 0x0000ffff, 142 MGA_TEXTRANSHIGH, 0x0000ffff, MGA_DMAPAD, 0x00000000);
153 MGA_DMAPAD, 0x00000000 );
154 143
155 ADVANCE_DMA(); 144 ADVANCE_DMA();
156} 145}
157 146
158static __inline__ void mga_g400_emit_tex0( drm_mga_private_t *dev_priv ) 147static __inline__ void mga_g400_emit_tex0(drm_mga_private_t * dev_priv)
159{ 148{
160 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 149 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
161 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0]; 150 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
@@ -164,42 +153,38 @@ static __inline__ void mga_g400_emit_tex0( drm_mga_private_t *dev_priv )
164/* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */ 153/* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
165/* tex->texctl, tex->texctl2); */ 154/* tex->texctl, tex->texctl2); */
166 155
167 BEGIN_DMA( 6 ); 156 BEGIN_DMA(6);
168 157
169 DMA_BLOCK( MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC, 158 DMA_BLOCK(MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC,
170 MGA_TEXCTL, tex->texctl, 159 MGA_TEXCTL, tex->texctl,
171 MGA_TEXFILTER, tex->texfilter, 160 MGA_TEXFILTER, tex->texfilter,
172 MGA_TEXBORDERCOL, tex->texbordercol ); 161 MGA_TEXBORDERCOL, tex->texbordercol);
173 162
174 DMA_BLOCK( MGA_TEXORG, tex->texorg, 163 DMA_BLOCK(MGA_TEXORG, tex->texorg,
175 MGA_TEXORG1, tex->texorg1, 164 MGA_TEXORG1, tex->texorg1,
176 MGA_TEXORG2, tex->texorg2, 165 MGA_TEXORG2, tex->texorg2, MGA_TEXORG3, tex->texorg3);
177 MGA_TEXORG3, tex->texorg3 );
178 166
179 DMA_BLOCK( MGA_TEXORG4, tex->texorg4, 167 DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
180 MGA_TEXWIDTH, tex->texwidth, 168 MGA_TEXWIDTH, tex->texwidth,
181 MGA_TEXHEIGHT, tex->texheight, 169 MGA_TEXHEIGHT, tex->texheight, MGA_WR49, 0x00000000);
182 MGA_WR49, 0x00000000 );
183 170
184 DMA_BLOCK( MGA_WR57, 0x00000000, 171 DMA_BLOCK(MGA_WR57, 0x00000000,
185 MGA_WR53, 0x00000000, 172 MGA_WR53, 0x00000000,
186 MGA_WR61, 0x00000000, 173 MGA_WR61, 0x00000000, MGA_WR52, MGA_G400_WR_MAGIC);
187 MGA_WR52, MGA_G400_WR_MAGIC );
188 174
189 DMA_BLOCK( MGA_WR60, MGA_G400_WR_MAGIC, 175 DMA_BLOCK(MGA_WR60, MGA_G400_WR_MAGIC,
190 MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC, 176 MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC,
191 MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC, 177 MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC,
192 MGA_DMAPAD, 0x00000000 ); 178 MGA_DMAPAD, 0x00000000);
193 179
194 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 180 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
195 MGA_DMAPAD, 0x00000000, 181 MGA_DMAPAD, 0x00000000,
196 MGA_TEXTRANS, 0x0000ffff, 182 MGA_TEXTRANS, 0x0000ffff, MGA_TEXTRANSHIGH, 0x0000ffff);
197 MGA_TEXTRANSHIGH, 0x0000ffff );
198 183
199 ADVANCE_DMA(); 184 ADVANCE_DMA();
200} 185}
201 186
202static __inline__ void mga_g400_emit_tex1( drm_mga_private_t *dev_priv ) 187static __inline__ void mga_g400_emit_tex1(drm_mga_private_t * dev_priv)
203{ 188{
204 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 189 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
205 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1]; 190 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
@@ -208,55 +193,51 @@ static __inline__ void mga_g400_emit_tex1( drm_mga_private_t *dev_priv )
208/* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */ 193/* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */
209/* tex->texctl, tex->texctl2); */ 194/* tex->texctl, tex->texctl2); */
210 195
211 BEGIN_DMA( 5 ); 196 BEGIN_DMA(5);
212 197
213 DMA_BLOCK( MGA_TEXCTL2, (tex->texctl2 | 198 DMA_BLOCK(MGA_TEXCTL2, (tex->texctl2 |
214 MGA_MAP1_ENABLE | 199 MGA_MAP1_ENABLE |
215 MGA_G400_TC2_MAGIC), 200 MGA_G400_TC2_MAGIC),
216 MGA_TEXCTL, tex->texctl, 201 MGA_TEXCTL, tex->texctl,
217 MGA_TEXFILTER, tex->texfilter, 202 MGA_TEXFILTER, tex->texfilter,
218 MGA_TEXBORDERCOL, tex->texbordercol ); 203 MGA_TEXBORDERCOL, tex->texbordercol);
219 204
220 DMA_BLOCK( MGA_TEXORG, tex->texorg, 205 DMA_BLOCK(MGA_TEXORG, tex->texorg,
221 MGA_TEXORG1, tex->texorg1, 206 MGA_TEXORG1, tex->texorg1,
222 MGA_TEXORG2, tex->texorg2, 207 MGA_TEXORG2, tex->texorg2, MGA_TEXORG3, tex->texorg3);
223 MGA_TEXORG3, tex->texorg3 );
224 208
225 DMA_BLOCK( MGA_TEXORG4, tex->texorg4, 209 DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
226 MGA_TEXWIDTH, tex->texwidth, 210 MGA_TEXWIDTH, tex->texwidth,
227 MGA_TEXHEIGHT, tex->texheight, 211 MGA_TEXHEIGHT, tex->texheight, MGA_WR49, 0x00000000);
228 MGA_WR49, 0x00000000 );
229 212
230 DMA_BLOCK( MGA_WR57, 0x00000000, 213 DMA_BLOCK(MGA_WR57, 0x00000000,
231 MGA_WR53, 0x00000000, 214 MGA_WR53, 0x00000000,
232 MGA_WR61, 0x00000000, 215 MGA_WR61, 0x00000000,
233 MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC ); 216 MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC);
234 217
235 DMA_BLOCK( MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC, 218 DMA_BLOCK(MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC,
236 MGA_TEXTRANS, 0x0000ffff, 219 MGA_TEXTRANS, 0x0000ffff,
237 MGA_TEXTRANSHIGH, 0x0000ffff, 220 MGA_TEXTRANSHIGH, 0x0000ffff,
238 MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC ); 221 MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC);
239 222
240 ADVANCE_DMA(); 223 ADVANCE_DMA();
241} 224}
242 225
243static __inline__ void mga_g200_emit_pipe( drm_mga_private_t *dev_priv ) 226static __inline__ void mga_g200_emit_pipe(drm_mga_private_t * dev_priv)
244{ 227{
245 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 228 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
246 unsigned int pipe = sarea_priv->warp_pipe; 229 unsigned int pipe = sarea_priv->warp_pipe;
247 DMA_LOCALS; 230 DMA_LOCALS;
248 231
249 BEGIN_DMA( 3 ); 232 BEGIN_DMA(3);
250 233
251 DMA_BLOCK( MGA_WIADDR, MGA_WMODE_SUSPEND, 234 DMA_BLOCK(MGA_WIADDR, MGA_WMODE_SUSPEND,
252 MGA_WVRTXSZ, 0x00000007, 235 MGA_WVRTXSZ, 0x00000007,
253 MGA_WFLAG, 0x00000000, 236 MGA_WFLAG, 0x00000000, MGA_WR24, 0x00000000);
254 MGA_WR24, 0x00000000 );
255 237
256 DMA_BLOCK( MGA_WR25, 0x00000100, 238 DMA_BLOCK(MGA_WR25, 0x00000100,
257 MGA_WR34, 0x00000000, 239 MGA_WR34, 0x00000000,
258 MGA_WR42, 0x0000ffff, 240 MGA_WR42, 0x0000ffff, MGA_WR60, 0x0000ffff);
259 MGA_WR60, 0x0000ffff );
260 241
261 /* Padding required to to hardware bug. 242 /* Padding required to to hardware bug.
262 */ 243 */
@@ -269,7 +250,7 @@ static __inline__ void mga_g200_emit_pipe( drm_mga_private_t *dev_priv )
269 ADVANCE_DMA(); 250 ADVANCE_DMA();
270} 251}
271 252
272static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv ) 253static __inline__ void mga_g400_emit_pipe(drm_mga_private_t * dev_priv)
273{ 254{
274 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 255 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
275 unsigned int pipe = sarea_priv->warp_pipe; 256 unsigned int pipe = sarea_priv->warp_pipe;
@@ -277,68 +258,64 @@ static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv )
277 258
278/* printk("mga_g400_emit_pipe %x\n", pipe); */ 259/* printk("mga_g400_emit_pipe %x\n", pipe); */
279 260
280 BEGIN_DMA( 10 ); 261 BEGIN_DMA(10);
281 262
282 DMA_BLOCK( MGA_WIADDR2, MGA_WMODE_SUSPEND, 263 DMA_BLOCK(MGA_WIADDR2, MGA_WMODE_SUSPEND,
283 MGA_DMAPAD, 0x00000000, 264 MGA_DMAPAD, 0x00000000,
284 MGA_DMAPAD, 0x00000000, 265 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
285 MGA_DMAPAD, 0x00000000 );
286 266
287 if ( pipe & MGA_T2 ) { 267 if (pipe & MGA_T2) {
288 DMA_BLOCK( MGA_WVRTXSZ, 0x00001e09, 268 DMA_BLOCK(MGA_WVRTXSZ, 0x00001e09,
289 MGA_DMAPAD, 0x00000000, 269 MGA_DMAPAD, 0x00000000,
290 MGA_DMAPAD, 0x00000000, 270 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
291 MGA_DMAPAD, 0x00000000 );
292 271
293 DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000, 272 DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000,
294 MGA_WACCEPTSEQ, 0x00000000, 273 MGA_WACCEPTSEQ, 0x00000000,
295 MGA_WACCEPTSEQ, 0x00000000, 274 MGA_WACCEPTSEQ, 0x00000000,
296 MGA_WACCEPTSEQ, 0x1e000000 ); 275 MGA_WACCEPTSEQ, 0x1e000000);
297 } else { 276 } else {
298 if ( dev_priv->warp_pipe & MGA_T2 ) { 277 if (dev_priv->warp_pipe & MGA_T2) {
299 /* Flush the WARP pipe */ 278 /* Flush the WARP pipe */
300 DMA_BLOCK( MGA_YDST, 0x00000000, 279 DMA_BLOCK(MGA_YDST, 0x00000000,
301 MGA_FXLEFT, 0x00000000, 280 MGA_FXLEFT, 0x00000000,
302 MGA_FXRIGHT, 0x00000001, 281 MGA_FXRIGHT, 0x00000001,
303 MGA_DWGCTL, MGA_DWGCTL_FLUSH ); 282 MGA_DWGCTL, MGA_DWGCTL_FLUSH);
304 283
305 DMA_BLOCK( MGA_LEN + MGA_EXEC, 0x00000001, 284 DMA_BLOCK(MGA_LEN + MGA_EXEC, 0x00000001,
306 MGA_DWGSYNC, 0x00007000, 285 MGA_DWGSYNC, 0x00007000,
307 MGA_TEXCTL2, MGA_G400_TC2_MAGIC, 286 MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
308 MGA_LEN + MGA_EXEC, 0x00000000 ); 287 MGA_LEN + MGA_EXEC, 0x00000000);
309 288
310 DMA_BLOCK( MGA_TEXCTL2, (MGA_DUALTEX | 289 DMA_BLOCK(MGA_TEXCTL2, (MGA_DUALTEX |
311 MGA_G400_TC2_MAGIC), 290 MGA_G400_TC2_MAGIC),
312 MGA_LEN + MGA_EXEC, 0x00000000, 291 MGA_LEN + MGA_EXEC, 0x00000000,
313 MGA_TEXCTL2, MGA_G400_TC2_MAGIC, 292 MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
314 MGA_DMAPAD, 0x00000000 ); 293 MGA_DMAPAD, 0x00000000);
315 } 294 }
316 295
317 DMA_BLOCK( MGA_WVRTXSZ, 0x00001807, 296 DMA_BLOCK(MGA_WVRTXSZ, 0x00001807,
318 MGA_DMAPAD, 0x00000000, 297 MGA_DMAPAD, 0x00000000,
319 MGA_DMAPAD, 0x00000000, 298 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
320 MGA_DMAPAD, 0x00000000 );
321 299
322 DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000, 300 DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000,
323 MGA_WACCEPTSEQ, 0x00000000, 301 MGA_WACCEPTSEQ, 0x00000000,
324 MGA_WACCEPTSEQ, 0x00000000, 302 MGA_WACCEPTSEQ, 0x00000000,
325 MGA_WACCEPTSEQ, 0x18000000 ); 303 MGA_WACCEPTSEQ, 0x18000000);
326 } 304 }
327 305
328 DMA_BLOCK( MGA_WFLAG, 0x00000000, 306 DMA_BLOCK(MGA_WFLAG, 0x00000000,
329 MGA_WFLAG1, 0x00000000, 307 MGA_WFLAG1, 0x00000000,
330 MGA_WR56, MGA_G400_WR56_MAGIC, 308 MGA_WR56, MGA_G400_WR56_MAGIC, MGA_DMAPAD, 0x00000000);
331 MGA_DMAPAD, 0x00000000 );
332 309
333 DMA_BLOCK( MGA_WR49, 0x00000000, /* tex0 */ 310 DMA_BLOCK(MGA_WR49, 0x00000000, /* tex0 */
334 MGA_WR57, 0x00000000, /* tex0 */ 311 MGA_WR57, 0x00000000, /* tex0 */
335 MGA_WR53, 0x00000000, /* tex1 */ 312 MGA_WR53, 0x00000000, /* tex1 */
336 MGA_WR61, 0x00000000 ); /* tex1 */ 313 MGA_WR61, 0x00000000); /* tex1 */
337 314
338 DMA_BLOCK( MGA_WR54, MGA_G400_WR_MAGIC, /* tex0 width */ 315 DMA_BLOCK(MGA_WR54, MGA_G400_WR_MAGIC, /* tex0 width */
339 MGA_WR62, MGA_G400_WR_MAGIC, /* tex0 height */ 316 MGA_WR62, MGA_G400_WR_MAGIC, /* tex0 height */
340 MGA_WR52, MGA_G400_WR_MAGIC, /* tex1 width */ 317 MGA_WR52, MGA_G400_WR_MAGIC, /* tex1 width */
341 MGA_WR60, MGA_G400_WR_MAGIC ); /* tex1 height */ 318 MGA_WR60, MGA_G400_WR_MAGIC); /* tex1 height */
342 319
343 /* Padding required to to hardware bug */ 320 /* Padding required to to hardware bug */
344 DMA_BLOCK(MGA_DMAPAD, 0xffffffff, 321 DMA_BLOCK(MGA_DMAPAD, 0xffffffff,
@@ -350,71 +327,70 @@ static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv )
350 ADVANCE_DMA(); 327 ADVANCE_DMA();
351} 328}
352 329
353static void mga_g200_emit_state( drm_mga_private_t *dev_priv ) 330static void mga_g200_emit_state(drm_mga_private_t * dev_priv)
354{ 331{
355 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 332 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
356 unsigned int dirty = sarea_priv->dirty; 333 unsigned int dirty = sarea_priv->dirty;
357 334
358 if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) { 335 if (sarea_priv->warp_pipe != dev_priv->warp_pipe) {
359 mga_g200_emit_pipe( dev_priv ); 336 mga_g200_emit_pipe(dev_priv);
360 dev_priv->warp_pipe = sarea_priv->warp_pipe; 337 dev_priv->warp_pipe = sarea_priv->warp_pipe;
361 } 338 }
362 339
363 if ( dirty & MGA_UPLOAD_CONTEXT ) { 340 if (dirty & MGA_UPLOAD_CONTEXT) {
364 mga_g200_emit_context( dev_priv ); 341 mga_g200_emit_context(dev_priv);
365 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT; 342 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
366 } 343 }
367 344
368 if ( dirty & MGA_UPLOAD_TEX0 ) { 345 if (dirty & MGA_UPLOAD_TEX0) {
369 mga_g200_emit_tex0( dev_priv ); 346 mga_g200_emit_tex0(dev_priv);
370 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; 347 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
371 } 348 }
372} 349}
373 350
374static void mga_g400_emit_state( drm_mga_private_t *dev_priv ) 351static void mga_g400_emit_state(drm_mga_private_t * dev_priv)
375{ 352{
376 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 353 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
377 unsigned int dirty = sarea_priv->dirty; 354 unsigned int dirty = sarea_priv->dirty;
378 int multitex = sarea_priv->warp_pipe & MGA_T2; 355 int multitex = sarea_priv->warp_pipe & MGA_T2;
379 356
380 if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) { 357 if (sarea_priv->warp_pipe != dev_priv->warp_pipe) {
381 mga_g400_emit_pipe( dev_priv ); 358 mga_g400_emit_pipe(dev_priv);
382 dev_priv->warp_pipe = sarea_priv->warp_pipe; 359 dev_priv->warp_pipe = sarea_priv->warp_pipe;
383 } 360 }
384 361
385 if ( dirty & MGA_UPLOAD_CONTEXT ) { 362 if (dirty & MGA_UPLOAD_CONTEXT) {
386 mga_g400_emit_context( dev_priv ); 363 mga_g400_emit_context(dev_priv);
387 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT; 364 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
388 } 365 }
389 366
390 if ( dirty & MGA_UPLOAD_TEX0 ) { 367 if (dirty & MGA_UPLOAD_TEX0) {
391 mga_g400_emit_tex0( dev_priv ); 368 mga_g400_emit_tex0(dev_priv);
392 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; 369 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
393 } 370 }
394 371
395 if ( (dirty & MGA_UPLOAD_TEX1) && multitex ) { 372 if ((dirty & MGA_UPLOAD_TEX1) && multitex) {
396 mga_g400_emit_tex1( dev_priv ); 373 mga_g400_emit_tex1(dev_priv);
397 sarea_priv->dirty &= ~MGA_UPLOAD_TEX1; 374 sarea_priv->dirty &= ~MGA_UPLOAD_TEX1;
398 } 375 }
399} 376}
400 377
401
402/* ================================================================ 378/* ================================================================
403 * SAREA state verification 379 * SAREA state verification
404 */ 380 */
405 381
406/* Disallow all write destinations except the front and backbuffer. 382/* Disallow all write destinations except the front and backbuffer.
407 */ 383 */
408static int mga_verify_context( drm_mga_private_t *dev_priv ) 384static int mga_verify_context(drm_mga_private_t * dev_priv)
409{ 385{
410 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 386 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
411 drm_mga_context_regs_t *ctx = &sarea_priv->context_state; 387 drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
412 388
413 if ( ctx->dstorg != dev_priv->front_offset && 389 if (ctx->dstorg != dev_priv->front_offset &&
414 ctx->dstorg != dev_priv->back_offset ) { 390 ctx->dstorg != dev_priv->back_offset) {
415 DRM_ERROR( "*** bad DSTORG: %x (front %x, back %x)\n\n", 391 DRM_ERROR("*** bad DSTORG: %x (front %x, back %x)\n\n",
416 ctx->dstorg, dev_priv->front_offset, 392 ctx->dstorg, dev_priv->front_offset,
417 dev_priv->back_offset ); 393 dev_priv->back_offset);
418 ctx->dstorg = 0; 394 ctx->dstorg = 0;
419 return DRM_ERR(EINVAL); 395 return DRM_ERR(EINVAL);
420 } 396 }
@@ -424,7 +400,7 @@ static int mga_verify_context( drm_mga_private_t *dev_priv )
424 400
425/* Disallow texture reads from PCI space. 401/* Disallow texture reads from PCI space.
426 */ 402 */
427static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit ) 403static int mga_verify_tex(drm_mga_private_t * dev_priv, int unit)
428{ 404{
429 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 405 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
430 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit]; 406 drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit];
@@ -432,9 +408,8 @@ static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit )
432 408
433 org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK); 409 org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK);
434 410
435 if ( org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI) ) { 411 if (org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI)) {
436 DRM_ERROR( "*** bad TEXORG: 0x%x, unit %d\n", 412 DRM_ERROR("*** bad TEXORG: 0x%x, unit %d\n", tex->texorg, unit);
437 tex->texorg, unit );
438 tex->texorg = 0; 413 tex->texorg = 0;
439 return DRM_ERR(EINVAL); 414 return DRM_ERR(EINVAL);
440 } 415 }
@@ -442,73 +417,70 @@ static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit )
442 return 0; 417 return 0;
443} 418}
444 419
445static int mga_verify_state( drm_mga_private_t *dev_priv ) 420static int mga_verify_state(drm_mga_private_t * dev_priv)
446{ 421{
447 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 422 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
448 unsigned int dirty = sarea_priv->dirty; 423 unsigned int dirty = sarea_priv->dirty;
449 int ret = 0; 424 int ret = 0;
450 425
451 if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) 426 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
452 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; 427 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
453 428
454 if ( dirty & MGA_UPLOAD_CONTEXT ) 429 if (dirty & MGA_UPLOAD_CONTEXT)
455 ret |= mga_verify_context( dev_priv ); 430 ret |= mga_verify_context(dev_priv);
456 431
457 if ( dirty & MGA_UPLOAD_TEX0 ) 432 if (dirty & MGA_UPLOAD_TEX0)
458 ret |= mga_verify_tex( dev_priv, 0 ); 433 ret |= mga_verify_tex(dev_priv, 0);
459 434
460 if (dev_priv->chipset >= MGA_CARD_TYPE_G400) { 435 if (dev_priv->chipset >= MGA_CARD_TYPE_G400) {
461 if (dirty & MGA_UPLOAD_TEX1) 436 if (dirty & MGA_UPLOAD_TEX1)
462 ret |= mga_verify_tex(dev_priv, 1); 437 ret |= mga_verify_tex(dev_priv, 1);
463 438
464 if ( dirty & MGA_UPLOAD_PIPE ) 439 if (dirty & MGA_UPLOAD_PIPE)
465 ret |= ( sarea_priv->warp_pipe > MGA_MAX_G400_PIPES ); 440 ret |= (sarea_priv->warp_pipe > MGA_MAX_G400_PIPES);
466 } else { 441 } else {
467 if ( dirty & MGA_UPLOAD_PIPE ) 442 if (dirty & MGA_UPLOAD_PIPE)
468 ret |= ( sarea_priv->warp_pipe > MGA_MAX_G200_PIPES ); 443 ret |= (sarea_priv->warp_pipe > MGA_MAX_G200_PIPES);
469 } 444 }
470 445
471 return ( ret == 0 ); 446 return (ret == 0);
472} 447}
473 448
474static int mga_verify_iload( drm_mga_private_t *dev_priv, 449static int mga_verify_iload(drm_mga_private_t * dev_priv,
475 unsigned int dstorg, unsigned int length ) 450 unsigned int dstorg, unsigned int length)
476{ 451{
477 if ( dstorg < dev_priv->texture_offset || 452 if (dstorg < dev_priv->texture_offset ||
478 dstorg + length > (dev_priv->texture_offset + 453 dstorg + length > (dev_priv->texture_offset +
479 dev_priv->texture_size) ) { 454 dev_priv->texture_size)) {
480 DRM_ERROR( "*** bad iload DSTORG: 0x%x\n", dstorg ); 455 DRM_ERROR("*** bad iload DSTORG: 0x%x\n", dstorg);
481 return DRM_ERR(EINVAL); 456 return DRM_ERR(EINVAL);
482 } 457 }
483 458
484 if ( length & MGA_ILOAD_MASK ) { 459 if (length & MGA_ILOAD_MASK) {
485 DRM_ERROR( "*** bad iload length: 0x%x\n", 460 DRM_ERROR("*** bad iload length: 0x%x\n",
486 length & MGA_ILOAD_MASK ); 461 length & MGA_ILOAD_MASK);
487 return DRM_ERR(EINVAL); 462 return DRM_ERR(EINVAL);
488 } 463 }
489 464
490 return 0; 465 return 0;
491} 466}
492 467
493static int mga_verify_blit( drm_mga_private_t *dev_priv, 468static int mga_verify_blit(drm_mga_private_t * dev_priv,
494 unsigned int srcorg, unsigned int dstorg ) 469 unsigned int srcorg, unsigned int dstorg)
495{ 470{
496 if ( (srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) || 471 if ((srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ||
497 (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ) { 472 (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM)) {
498 DRM_ERROR( "*** bad blit: src=0x%x dst=0x%x\n", 473 DRM_ERROR("*** bad blit: src=0x%x dst=0x%x\n", srcorg, dstorg);
499 srcorg, dstorg );
500 return DRM_ERR(EINVAL); 474 return DRM_ERR(EINVAL);
501 } 475 }
502 return 0; 476 return 0;
503} 477}
504 478
505
506/* ================================================================ 479/* ================================================================
507 * 480 *
508 */ 481 */
509 482
510static void mga_dma_dispatch_clear( drm_device_t *dev, 483static void mga_dma_dispatch_clear(drm_device_t * dev, drm_mga_clear_t * clear)
511 drm_mga_clear_t *clear )
512{ 484{
513 drm_mga_private_t *dev_priv = dev->dev_private; 485 drm_mga_private_t *dev_priv = dev->dev_private;
514 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 486 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -517,92 +489,86 @@ static void mga_dma_dispatch_clear( drm_device_t *dev,
517 int nbox = sarea_priv->nbox; 489 int nbox = sarea_priv->nbox;
518 int i; 490 int i;
519 DMA_LOCALS; 491 DMA_LOCALS;
520 DRM_DEBUG( "\n" ); 492 DRM_DEBUG("\n");
521 493
522 BEGIN_DMA( 1 ); 494 BEGIN_DMA(1);
523 495
524 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 496 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
525 MGA_DMAPAD, 0x00000000, 497 MGA_DMAPAD, 0x00000000,
526 MGA_DWGSYNC, 0x00007100, 498 MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000);
527 MGA_DWGSYNC, 0x00007000 );
528 499
529 ADVANCE_DMA(); 500 ADVANCE_DMA();
530 501
531 for ( i = 0 ; i < nbox ; i++ ) { 502 for (i = 0; i < nbox; i++) {
532 drm_clip_rect_t *box = &pbox[i]; 503 drm_clip_rect_t *box = &pbox[i];
533 u32 height = box->y2 - box->y1; 504 u32 height = box->y2 - box->y1;
534 505
535 DRM_DEBUG( " from=%d,%d to=%d,%d\n", 506 DRM_DEBUG(" from=%d,%d to=%d,%d\n",
536 box->x1, box->y1, box->x2, box->y2 ); 507 box->x1, box->y1, box->x2, box->y2);
537 508
538 if ( clear->flags & MGA_FRONT ) { 509 if (clear->flags & MGA_FRONT) {
539 BEGIN_DMA( 2 ); 510 BEGIN_DMA(2);
540 511
541 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 512 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
542 MGA_PLNWT, clear->color_mask, 513 MGA_PLNWT, clear->color_mask,
543 MGA_YDSTLEN, (box->y1 << 16) | height, 514 MGA_YDSTLEN, (box->y1 << 16) | height,
544 MGA_FXBNDRY, (box->x2 << 16) | box->x1 ); 515 MGA_FXBNDRY, (box->x2 << 16) | box->x1);
545 516
546 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 517 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
547 MGA_FCOL, clear->clear_color, 518 MGA_FCOL, clear->clear_color,
548 MGA_DSTORG, dev_priv->front_offset, 519 MGA_DSTORG, dev_priv->front_offset,
549 MGA_DWGCTL + MGA_EXEC, 520 MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
550 dev_priv->clear_cmd );
551 521
552 ADVANCE_DMA(); 522 ADVANCE_DMA();
553 } 523 }
554 524
525 if (clear->flags & MGA_BACK) {
526 BEGIN_DMA(2);
555 527
556 if ( clear->flags & MGA_BACK ) { 528 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
557 BEGIN_DMA( 2 ); 529 MGA_PLNWT, clear->color_mask,
558 530 MGA_YDSTLEN, (box->y1 << 16) | height,
559 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 531 MGA_FXBNDRY, (box->x2 << 16) | box->x1);
560 MGA_PLNWT, clear->color_mask,
561 MGA_YDSTLEN, (box->y1 << 16) | height,
562 MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
563 532
564 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 533 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
565 MGA_FCOL, clear->clear_color, 534 MGA_FCOL, clear->clear_color,
566 MGA_DSTORG, dev_priv->back_offset, 535 MGA_DSTORG, dev_priv->back_offset,
567 MGA_DWGCTL + MGA_EXEC, 536 MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
568 dev_priv->clear_cmd );
569 537
570 ADVANCE_DMA(); 538 ADVANCE_DMA();
571 } 539 }
572 540
573 if ( clear->flags & MGA_DEPTH ) { 541 if (clear->flags & MGA_DEPTH) {
574 BEGIN_DMA( 2 ); 542 BEGIN_DMA(2);
575 543
576 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 544 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
577 MGA_PLNWT, clear->depth_mask, 545 MGA_PLNWT, clear->depth_mask,
578 MGA_YDSTLEN, (box->y1 << 16) | height, 546 MGA_YDSTLEN, (box->y1 << 16) | height,
579 MGA_FXBNDRY, (box->x2 << 16) | box->x1 ); 547 MGA_FXBNDRY, (box->x2 << 16) | box->x1);
580 548
581 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 549 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
582 MGA_FCOL, clear->clear_depth, 550 MGA_FCOL, clear->clear_depth,
583 MGA_DSTORG, dev_priv->depth_offset, 551 MGA_DSTORG, dev_priv->depth_offset,
584 MGA_DWGCTL + MGA_EXEC, 552 MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
585 dev_priv->clear_cmd );
586 553
587 ADVANCE_DMA(); 554 ADVANCE_DMA();
588 } 555 }
589 556
590 } 557 }
591 558
592 BEGIN_DMA( 1 ); 559 BEGIN_DMA(1);
593 560
594 /* Force reset of DWGCTL */ 561 /* Force reset of DWGCTL */
595 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 562 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
596 MGA_DMAPAD, 0x00000000, 563 MGA_DMAPAD, 0x00000000,
597 MGA_PLNWT, ctx->plnwt, 564 MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl);
598 MGA_DWGCTL, ctx->dwgctl );
599 565
600 ADVANCE_DMA(); 566 ADVANCE_DMA();
601 567
602 FLUSH_DMA(); 568 FLUSH_DMA();
603} 569}
604 570
605static void mga_dma_dispatch_swap( drm_device_t *dev ) 571static void mga_dma_dispatch_swap(drm_device_t * dev)
606{ 572{
607 drm_mga_private_t *dev_priv = dev->dev_private; 573 drm_mga_private_t *dev_priv = dev->dev_private;
608 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 574 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -611,56 +577,52 @@ static void mga_dma_dispatch_swap( drm_device_t *dev )
611 int nbox = sarea_priv->nbox; 577 int nbox = sarea_priv->nbox;
612 int i; 578 int i;
613 DMA_LOCALS; 579 DMA_LOCALS;
614 DRM_DEBUG( "\n" ); 580 DRM_DEBUG("\n");
615 581
616 sarea_priv->last_frame.head = dev_priv->prim.tail; 582 sarea_priv->last_frame.head = dev_priv->prim.tail;
617 sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap; 583 sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap;
618 584
619 BEGIN_DMA( 4 + nbox ); 585 BEGIN_DMA(4 + nbox);
620 586
621 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 587 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
622 MGA_DMAPAD, 0x00000000, 588 MGA_DMAPAD, 0x00000000,
623 MGA_DWGSYNC, 0x00007100, 589 MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000);
624 MGA_DWGSYNC, 0x00007000 );
625 590
626 DMA_BLOCK( MGA_DSTORG, dev_priv->front_offset, 591 DMA_BLOCK(MGA_DSTORG, dev_priv->front_offset,
627 MGA_MACCESS, dev_priv->maccess, 592 MGA_MACCESS, dev_priv->maccess,
628 MGA_SRCORG, dev_priv->back_offset, 593 MGA_SRCORG, dev_priv->back_offset,
629 MGA_AR5, dev_priv->front_pitch ); 594 MGA_AR5, dev_priv->front_pitch);
630 595
631 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 596 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
632 MGA_DMAPAD, 0x00000000, 597 MGA_DMAPAD, 0x00000000,
633 MGA_PLNWT, 0xffffffff, 598 MGA_PLNWT, 0xffffffff, MGA_DWGCTL, MGA_DWGCTL_COPY);
634 MGA_DWGCTL, MGA_DWGCTL_COPY );
635 599
636 for ( i = 0 ; i < nbox ; i++ ) { 600 for (i = 0; i < nbox; i++) {
637 drm_clip_rect_t *box = &pbox[i]; 601 drm_clip_rect_t *box = &pbox[i];
638 u32 height = box->y2 - box->y1; 602 u32 height = box->y2 - box->y1;
639 u32 start = box->y1 * dev_priv->front_pitch; 603 u32 start = box->y1 * dev_priv->front_pitch;
640 604
641 DRM_DEBUG( " from=%d,%d to=%d,%d\n", 605 DRM_DEBUG(" from=%d,%d to=%d,%d\n",
642 box->x1, box->y1, box->x2, box->y2 ); 606 box->x1, box->y1, box->x2, box->y2);
643 607
644 DMA_BLOCK( MGA_AR0, start + box->x2 - 1, 608 DMA_BLOCK(MGA_AR0, start + box->x2 - 1,
645 MGA_AR3, start + box->x1, 609 MGA_AR3, start + box->x1,
646 MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1, 610 MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1,
647 MGA_YDSTLEN + MGA_EXEC, 611 MGA_YDSTLEN + MGA_EXEC, (box->y1 << 16) | height);
648 (box->y1 << 16) | height );
649 } 612 }
650 613
651 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 614 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
652 MGA_PLNWT, ctx->plnwt, 615 MGA_PLNWT, ctx->plnwt,
653 MGA_SRCORG, dev_priv->front_offset, 616 MGA_SRCORG, dev_priv->front_offset, MGA_DWGCTL, ctx->dwgctl);
654 MGA_DWGCTL, ctx->dwgctl );
655 617
656 ADVANCE_DMA(); 618 ADVANCE_DMA();
657 619
658 FLUSH_DMA(); 620 FLUSH_DMA();
659 621
660 DRM_DEBUG( "%s... done.\n", __FUNCTION__ ); 622 DRM_DEBUG("%s... done.\n", __FUNCTION__);
661} 623}
662 624
663static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf ) 625static void mga_dma_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf)
664{ 626{
665 drm_mga_private_t *dev_priv = dev->dev_private; 627 drm_mga_private_t *dev_priv = dev->dev_private;
666 drm_mga_buf_priv_t *buf_priv = buf->dev_private; 628 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
@@ -669,20 +631,20 @@ static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf )
669 u32 length = (u32) buf->used; 631 u32 length = (u32) buf->used;
670 int i = 0; 632 int i = 0;
671 DMA_LOCALS; 633 DMA_LOCALS;
672 DRM_DEBUG( "vertex: buf=%d used=%d\n", buf->idx, buf->used ); 634 DRM_DEBUG("vertex: buf=%d used=%d\n", buf->idx, buf->used);
673 635
674 if ( buf->used ) { 636 if (buf->used) {
675 buf_priv->dispatched = 1; 637 buf_priv->dispatched = 1;
676 638
677 MGA_EMIT_STATE( dev_priv, sarea_priv->dirty ); 639 MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
678 640
679 do { 641 do {
680 if ( i < sarea_priv->nbox ) { 642 if (i < sarea_priv->nbox) {
681 mga_emit_clip_rect( dev_priv, 643 mga_emit_clip_rect(dev_priv,
682 &sarea_priv->boxes[i] ); 644 &sarea_priv->boxes[i]);
683 } 645 }
684 646
685 BEGIN_DMA( 1 ); 647 BEGIN_DMA(1);
686 648
687 DMA_BLOCK(MGA_DMAPAD, 0x00000000, 649 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
688 MGA_DMAPAD, 0x00000000, 650 MGA_DMAPAD, 0x00000000,
@@ -692,23 +654,23 @@ static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf )
692 dev_priv->dma_access)); 654 dev_priv->dma_access));
693 655
694 ADVANCE_DMA(); 656 ADVANCE_DMA();
695 } while ( ++i < sarea_priv->nbox ); 657 } while (++i < sarea_priv->nbox);
696 } 658 }
697 659
698 if ( buf_priv->discard ) { 660 if (buf_priv->discard) {
699 AGE_BUFFER( buf_priv ); 661 AGE_BUFFER(buf_priv);
700 buf->pending = 0; 662 buf->pending = 0;
701 buf->used = 0; 663 buf->used = 0;
702 buf_priv->dispatched = 0; 664 buf_priv->dispatched = 0;
703 665
704 mga_freelist_put( dev, buf ); 666 mga_freelist_put(dev, buf);
705 } 667 }
706 668
707 FLUSH_DMA(); 669 FLUSH_DMA();
708} 670}
709 671
710static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf, 672static void mga_dma_dispatch_indices(drm_device_t * dev, drm_buf_t * buf,
711 unsigned int start, unsigned int end ) 673 unsigned int start, unsigned int end)
712{ 674{
713 drm_mga_private_t *dev_priv = dev->dev_private; 675 drm_mga_private_t *dev_priv = dev->dev_private;
714 drm_mga_buf_priv_t *buf_priv = buf->dev_private; 676 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
@@ -716,20 +678,20 @@ static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf,
716 u32 address = (u32) buf->bus_address; 678 u32 address = (u32) buf->bus_address;
717 int i = 0; 679 int i = 0;
718 DMA_LOCALS; 680 DMA_LOCALS;
719 DRM_DEBUG( "indices: buf=%d start=%d end=%d\n", buf->idx, start, end ); 681 DRM_DEBUG("indices: buf=%d start=%d end=%d\n", buf->idx, start, end);
720 682
721 if ( start != end ) { 683 if (start != end) {
722 buf_priv->dispatched = 1; 684 buf_priv->dispatched = 1;
723 685
724 MGA_EMIT_STATE( dev_priv, sarea_priv->dirty ); 686 MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
725 687
726 do { 688 do {
727 if ( i < sarea_priv->nbox ) { 689 if (i < sarea_priv->nbox) {
728 mga_emit_clip_rect( dev_priv, 690 mga_emit_clip_rect(dev_priv,
729 &sarea_priv->boxes[i] ); 691 &sarea_priv->boxes[i]);
730 } 692 }
731 693
732 BEGIN_DMA( 1 ); 694 BEGIN_DMA(1);
733 695
734 DMA_BLOCK(MGA_DMAPAD, 0x00000000, 696 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
735 MGA_DMAPAD, 0x00000000, 697 MGA_DMAPAD, 0x00000000,
@@ -738,16 +700,16 @@ static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf,
738 dev_priv->dma_access)); 700 dev_priv->dma_access));
739 701
740 ADVANCE_DMA(); 702 ADVANCE_DMA();
741 } while ( ++i < sarea_priv->nbox ); 703 } while (++i < sarea_priv->nbox);
742 } 704 }
743 705
744 if ( buf_priv->discard ) { 706 if (buf_priv->discard) {
745 AGE_BUFFER( buf_priv ); 707 AGE_BUFFER(buf_priv);
746 buf->pending = 0; 708 buf->pending = 0;
747 buf->used = 0; 709 buf->used = 0;
748 buf_priv->dispatched = 0; 710 buf_priv->dispatched = 0;
749 711
750 mga_freelist_put( dev, buf ); 712 mga_freelist_put(dev, buf);
751 } 713 }
752 714
753 FLUSH_DMA(); 715 FLUSH_DMA();
@@ -756,61 +718,55 @@ static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf,
756/* This copies a 64 byte aligned agp region to the frambuffer with a 718/* This copies a 64 byte aligned agp region to the frambuffer with a
757 * standard blit, the ioctl needs to do checking. 719 * standard blit, the ioctl needs to do checking.
758 */ 720 */
759static void mga_dma_dispatch_iload( drm_device_t *dev, drm_buf_t *buf, 721static void mga_dma_dispatch_iload(drm_device_t * dev, drm_buf_t * buf,
760 unsigned int dstorg, unsigned int length ) 722 unsigned int dstorg, unsigned int length)
761{ 723{
762 drm_mga_private_t *dev_priv = dev->dev_private; 724 drm_mga_private_t *dev_priv = dev->dev_private;
763 drm_mga_buf_priv_t *buf_priv = buf->dev_private; 725 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
764 drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state; 726 drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state;
765 u32 srcorg = buf->bus_address | dev_priv->dma_access | MGA_SRCMAP_SYSMEM; 727 u32 srcorg =
728 buf->bus_address | dev_priv->dma_access | MGA_SRCMAP_SYSMEM;
766 u32 y2; 729 u32 y2;
767 DMA_LOCALS; 730 DMA_LOCALS;
768 DRM_DEBUG( "buf=%d used=%d\n", buf->idx, buf->used ); 731 DRM_DEBUG("buf=%d used=%d\n", buf->idx, buf->used);
769 732
770 y2 = length / 64; 733 y2 = length / 64;
771 734
772 BEGIN_DMA( 5 ); 735 BEGIN_DMA(5);
773 736
774 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 737 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
775 MGA_DMAPAD, 0x00000000, 738 MGA_DMAPAD, 0x00000000,
776 MGA_DWGSYNC, 0x00007100, 739 MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000);
777 MGA_DWGSYNC, 0x00007000 );
778 740
779 DMA_BLOCK( MGA_DSTORG, dstorg, 741 DMA_BLOCK(MGA_DSTORG, dstorg,
780 MGA_MACCESS, 0x00000000, 742 MGA_MACCESS, 0x00000000, MGA_SRCORG, srcorg, MGA_AR5, 64);
781 MGA_SRCORG, srcorg,
782 MGA_AR5, 64 );
783 743
784 DMA_BLOCK( MGA_PITCH, 64, 744 DMA_BLOCK(MGA_PITCH, 64,
785 MGA_PLNWT, 0xffffffff, 745 MGA_PLNWT, 0xffffffff,
786 MGA_DMAPAD, 0x00000000, 746 MGA_DMAPAD, 0x00000000, MGA_DWGCTL, MGA_DWGCTL_COPY);
787 MGA_DWGCTL, MGA_DWGCTL_COPY );
788 747
789 DMA_BLOCK( MGA_AR0, 63, 748 DMA_BLOCK(MGA_AR0, 63,
790 MGA_AR3, 0, 749 MGA_AR3, 0,
791 MGA_FXBNDRY, (63 << 16) | 0, 750 MGA_FXBNDRY, (63 << 16) | 0, MGA_YDSTLEN + MGA_EXEC, y2);
792 MGA_YDSTLEN + MGA_EXEC, y2 );
793 751
794 DMA_BLOCK( MGA_PLNWT, ctx->plnwt, 752 DMA_BLOCK(MGA_PLNWT, ctx->plnwt,
795 MGA_SRCORG, dev_priv->front_offset, 753 MGA_SRCORG, dev_priv->front_offset,
796 MGA_PITCH, dev_priv->front_pitch, 754 MGA_PITCH, dev_priv->front_pitch, MGA_DWGSYNC, 0x00007000);
797 MGA_DWGSYNC, 0x00007000 );
798 755
799 ADVANCE_DMA(); 756 ADVANCE_DMA();
800 757
801 AGE_BUFFER( buf_priv ); 758 AGE_BUFFER(buf_priv);
802 759
803 buf->pending = 0; 760 buf->pending = 0;
804 buf->used = 0; 761 buf->used = 0;
805 buf_priv->dispatched = 0; 762 buf_priv->dispatched = 0;
806 763
807 mga_freelist_put( dev, buf ); 764 mga_freelist_put(dev, buf);
808 765
809 FLUSH_DMA(); 766 FLUSH_DMA();
810} 767}
811 768
812static void mga_dma_dispatch_blit( drm_device_t *dev, 769static void mga_dma_dispatch_blit(drm_device_t * dev, drm_mga_blit_t * blit)
813 drm_mga_blit_t *blit )
814{ 770{
815 drm_mga_private_t *dev_priv = dev->dev_private; 771 drm_mga_private_t *dev_priv = dev->dev_private;
816 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 772 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -819,26 +775,24 @@ static void mga_dma_dispatch_blit( drm_device_t *dev,
819 int nbox = sarea_priv->nbox; 775 int nbox = sarea_priv->nbox;
820 u32 scandir = 0, i; 776 u32 scandir = 0, i;
821 DMA_LOCALS; 777 DMA_LOCALS;
822 DRM_DEBUG( "\n" ); 778 DRM_DEBUG("\n");
823 779
824 BEGIN_DMA( 4 + nbox ); 780 BEGIN_DMA(4 + nbox);
825 781
826 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 782 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
827 MGA_DMAPAD, 0x00000000, 783 MGA_DMAPAD, 0x00000000,
828 MGA_DWGSYNC, 0x00007100, 784 MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000);
829 MGA_DWGSYNC, 0x00007000 );
830 785
831 DMA_BLOCK( MGA_DWGCTL, MGA_DWGCTL_COPY, 786 DMA_BLOCK(MGA_DWGCTL, MGA_DWGCTL_COPY,
832 MGA_PLNWT, blit->planemask, 787 MGA_PLNWT, blit->planemask,
833 MGA_SRCORG, blit->srcorg, 788 MGA_SRCORG, blit->srcorg, MGA_DSTORG, blit->dstorg);
834 MGA_DSTORG, blit->dstorg );
835 789
836 DMA_BLOCK( MGA_SGN, scandir, 790 DMA_BLOCK(MGA_SGN, scandir,
837 MGA_MACCESS, dev_priv->maccess, 791 MGA_MACCESS, dev_priv->maccess,
838 MGA_AR5, blit->ydir * blit->src_pitch, 792 MGA_AR5, blit->ydir * blit->src_pitch,
839 MGA_PITCH, blit->dst_pitch ); 793 MGA_PITCH, blit->dst_pitch);
840 794
841 for ( i = 0 ; i < nbox ; i++ ) { 795 for (i = 0; i < nbox; i++) {
842 int srcx = pbox[i].x1 + blit->delta_sx; 796 int srcx = pbox[i].x1 + blit->delta_sx;
843 int srcy = pbox[i].y1 + blit->delta_sy; 797 int srcy = pbox[i].y1 + blit->delta_sy;
844 int dstx = pbox[i].x1 + blit->delta_dx; 798 int dstx = pbox[i].x1 + blit->delta_dx;
@@ -847,52 +801,51 @@ static void mga_dma_dispatch_blit( drm_device_t *dev,
847 int w = pbox[i].x2 - pbox[i].x1 - 1; 801 int w = pbox[i].x2 - pbox[i].x1 - 1;
848 int start; 802 int start;
849 803
850 if ( blit->ydir == -1 ) { 804 if (blit->ydir == -1) {
851 srcy = blit->height - srcy - 1; 805 srcy = blit->height - srcy - 1;
852 } 806 }
853 807
854 start = srcy * blit->src_pitch + srcx; 808 start = srcy * blit->src_pitch + srcx;
855 809
856 DMA_BLOCK( MGA_AR0, start + w, 810 DMA_BLOCK(MGA_AR0, start + w,
857 MGA_AR3, start, 811 MGA_AR3, start,
858 MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff), 812 MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff),
859 MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h ); 813 MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h);
860 } 814 }
861 815
862 /* Do something to flush AGP? 816 /* Do something to flush AGP?
863 */ 817 */
864 818
865 /* Force reset of DWGCTL */ 819 /* Force reset of DWGCTL */
866 DMA_BLOCK( MGA_DMAPAD, 0x00000000, 820 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
867 MGA_PLNWT, ctx->plnwt, 821 MGA_PLNWT, ctx->plnwt,
868 MGA_PITCH, dev_priv->front_pitch, 822 MGA_PITCH, dev_priv->front_pitch, MGA_DWGCTL, ctx->dwgctl);
869 MGA_DWGCTL, ctx->dwgctl );
870 823
871 ADVANCE_DMA(); 824 ADVANCE_DMA();
872} 825}
873 826
874
875/* ================================================================ 827/* ================================================================
876 * 828 *
877 */ 829 */
878 830
879static int mga_dma_clear( DRM_IOCTL_ARGS ) 831static int mga_dma_clear(DRM_IOCTL_ARGS)
880{ 832{
881 DRM_DEVICE; 833 DRM_DEVICE;
882 drm_mga_private_t *dev_priv = dev->dev_private; 834 drm_mga_private_t *dev_priv = dev->dev_private;
883 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 835 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
884 drm_mga_clear_t clear; 836 drm_mga_clear_t clear;
885 837
886 LOCK_TEST_WITH_RETURN( dev, filp ); 838 LOCK_TEST_WITH_RETURN(dev, filp);
887 839
888 DRM_COPY_FROM_USER_IOCTL( clear, (drm_mga_clear_t __user *)data, sizeof(clear) ); 840 DRM_COPY_FROM_USER_IOCTL(clear, (drm_mga_clear_t __user *) data,
841 sizeof(clear));
889 842
890 if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) 843 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
891 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; 844 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
892 845
893 WRAP_TEST_WITH_RETURN( dev_priv ); 846 WRAP_TEST_WITH_RETURN(dev_priv);
894 847
895 mga_dma_dispatch_clear( dev, &clear ); 848 mga_dma_dispatch_clear(dev, &clear);
896 849
897 /* Make sure we restore the 3D state next time. 850 /* Make sure we restore the 3D state next time.
898 */ 851 */
@@ -901,20 +854,20 @@ static int mga_dma_clear( DRM_IOCTL_ARGS )
901 return 0; 854 return 0;
902} 855}
903 856
904static int mga_dma_swap( DRM_IOCTL_ARGS ) 857static int mga_dma_swap(DRM_IOCTL_ARGS)
905{ 858{
906 DRM_DEVICE; 859 DRM_DEVICE;
907 drm_mga_private_t *dev_priv = dev->dev_private; 860 drm_mga_private_t *dev_priv = dev->dev_private;
908 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 861 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
909 862
910 LOCK_TEST_WITH_RETURN( dev, filp ); 863 LOCK_TEST_WITH_RETURN(dev, filp);
911 864
912 if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) 865 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
913 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; 866 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
914 867
915 WRAP_TEST_WITH_RETURN( dev_priv ); 868 WRAP_TEST_WITH_RETURN(dev_priv);
916 869
917 mga_dma_dispatch_swap( dev ); 870 mga_dma_dispatch_swap(dev);
918 871
919 /* Make sure we restore the 3D state next time. 872 /* Make sure we restore the 3D state next time.
920 */ 873 */
@@ -923,7 +876,7 @@ static int mga_dma_swap( DRM_IOCTL_ARGS )
923 return 0; 876 return 0;
924} 877}
925 878
926static int mga_dma_vertex( DRM_IOCTL_ARGS ) 879static int mga_dma_vertex(DRM_IOCTL_ARGS)
927{ 880{
928 DRM_DEVICE; 881 DRM_DEVICE;
929 drm_mga_private_t *dev_priv = dev->dev_private; 882 drm_mga_private_t *dev_priv = dev->dev_private;
@@ -932,37 +885,38 @@ static int mga_dma_vertex( DRM_IOCTL_ARGS )
932 drm_mga_buf_priv_t *buf_priv; 885 drm_mga_buf_priv_t *buf_priv;
933 drm_mga_vertex_t vertex; 886 drm_mga_vertex_t vertex;
934 887
935 LOCK_TEST_WITH_RETURN( dev, filp ); 888 LOCK_TEST_WITH_RETURN(dev, filp);
936 889
937 DRM_COPY_FROM_USER_IOCTL( vertex, 890 DRM_COPY_FROM_USER_IOCTL(vertex,
938 (drm_mga_vertex_t __user *)data, 891 (drm_mga_vertex_t __user *) data,
939 sizeof(vertex) ); 892 sizeof(vertex));
940 893
941 if(vertex.idx < 0 || vertex.idx > dma->buf_count) return DRM_ERR(EINVAL); 894 if (vertex.idx < 0 || vertex.idx > dma->buf_count)
895 return DRM_ERR(EINVAL);
942 buf = dma->buflist[vertex.idx]; 896 buf = dma->buflist[vertex.idx];
943 buf_priv = buf->dev_private; 897 buf_priv = buf->dev_private;
944 898
945 buf->used = vertex.used; 899 buf->used = vertex.used;
946 buf_priv->discard = vertex.discard; 900 buf_priv->discard = vertex.discard;
947 901
948 if ( !mga_verify_state( dev_priv ) ) { 902 if (!mga_verify_state(dev_priv)) {
949 if ( vertex.discard ) { 903 if (vertex.discard) {
950 if ( buf_priv->dispatched == 1 ) 904 if (buf_priv->dispatched == 1)
951 AGE_BUFFER( buf_priv ); 905 AGE_BUFFER(buf_priv);
952 buf_priv->dispatched = 0; 906 buf_priv->dispatched = 0;
953 mga_freelist_put( dev, buf ); 907 mga_freelist_put(dev, buf);
954 } 908 }
955 return DRM_ERR(EINVAL); 909 return DRM_ERR(EINVAL);
956 } 910 }
957 911
958 WRAP_TEST_WITH_RETURN( dev_priv ); 912 WRAP_TEST_WITH_RETURN(dev_priv);
959 913
960 mga_dma_dispatch_vertex( dev, buf ); 914 mga_dma_dispatch_vertex(dev, buf);
961 915
962 return 0; 916 return 0;
963} 917}
964 918
965static int mga_dma_indices( DRM_IOCTL_ARGS ) 919static int mga_dma_indices(DRM_IOCTL_ARGS)
966{ 920{
967 DRM_DEVICE; 921 DRM_DEVICE;
968 drm_mga_private_t *dev_priv = dev->dev_private; 922 drm_mga_private_t *dev_priv = dev->dev_private;
@@ -971,37 +925,38 @@ static int mga_dma_indices( DRM_IOCTL_ARGS )
971 drm_mga_buf_priv_t *buf_priv; 925 drm_mga_buf_priv_t *buf_priv;
972 drm_mga_indices_t indices; 926 drm_mga_indices_t indices;
973 927
974 LOCK_TEST_WITH_RETURN( dev, filp ); 928 LOCK_TEST_WITH_RETURN(dev, filp);
975 929
976 DRM_COPY_FROM_USER_IOCTL( indices, 930 DRM_COPY_FROM_USER_IOCTL(indices,
977 (drm_mga_indices_t __user *)data, 931 (drm_mga_indices_t __user *) data,
978 sizeof(indices) ); 932 sizeof(indices));
979 933
980 if(indices.idx < 0 || indices.idx > dma->buf_count) return DRM_ERR(EINVAL); 934 if (indices.idx < 0 || indices.idx > dma->buf_count)
935 return DRM_ERR(EINVAL);
981 936
982 buf = dma->buflist[indices.idx]; 937 buf = dma->buflist[indices.idx];
983 buf_priv = buf->dev_private; 938 buf_priv = buf->dev_private;
984 939
985 buf_priv->discard = indices.discard; 940 buf_priv->discard = indices.discard;
986 941
987 if ( !mga_verify_state( dev_priv ) ) { 942 if (!mga_verify_state(dev_priv)) {
988 if ( indices.discard ) { 943 if (indices.discard) {
989 if ( buf_priv->dispatched == 1 ) 944 if (buf_priv->dispatched == 1)
990 AGE_BUFFER( buf_priv ); 945 AGE_BUFFER(buf_priv);
991 buf_priv->dispatched = 0; 946 buf_priv->dispatched = 0;
992 mga_freelist_put( dev, buf ); 947 mga_freelist_put(dev, buf);
993 } 948 }
994 return DRM_ERR(EINVAL); 949 return DRM_ERR(EINVAL);
995 } 950 }
996 951
997 WRAP_TEST_WITH_RETURN( dev_priv ); 952 WRAP_TEST_WITH_RETURN(dev_priv);
998 953
999 mga_dma_dispatch_indices( dev, buf, indices.start, indices.end ); 954 mga_dma_dispatch_indices(dev, buf, indices.start, indices.end);
1000 955
1001 return 0; 956 return 0;
1002} 957}
1003 958
1004static int mga_dma_iload( DRM_IOCTL_ARGS ) 959static int mga_dma_iload(DRM_IOCTL_ARGS)
1005{ 960{
1006 DRM_DEVICE; 961 DRM_DEVICE;
1007 drm_device_dma_t *dma = dev->dma; 962 drm_device_dma_t *dma = dev->dma;
@@ -1009,32 +964,34 @@ static int mga_dma_iload( DRM_IOCTL_ARGS )
1009 drm_buf_t *buf; 964 drm_buf_t *buf;
1010 drm_mga_buf_priv_t *buf_priv; 965 drm_mga_buf_priv_t *buf_priv;
1011 drm_mga_iload_t iload; 966 drm_mga_iload_t iload;
1012 DRM_DEBUG( "\n" ); 967 DRM_DEBUG("\n");
1013 968
1014 LOCK_TEST_WITH_RETURN( dev, filp ); 969 LOCK_TEST_WITH_RETURN(dev, filp);
1015 970
1016 DRM_COPY_FROM_USER_IOCTL( iload, (drm_mga_iload_t __user *)data, sizeof(iload) ); 971 DRM_COPY_FROM_USER_IOCTL(iload, (drm_mga_iload_t __user *) data,
972 sizeof(iload));
1017 973
1018#if 0 974#if 0
1019 if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { 975 if (mga_do_wait_for_idle(dev_priv) < 0) {
1020 if ( MGA_DMA_DEBUG ) 976 if (MGA_DMA_DEBUG)
1021 DRM_INFO( "%s: -EBUSY\n", __FUNCTION__ ); 977 DRM_INFO("%s: -EBUSY\n", __FUNCTION__);
1022 return DRM_ERR(EBUSY); 978 return DRM_ERR(EBUSY);
1023 } 979 }
1024#endif 980#endif
1025 if(iload.idx < 0 || iload.idx > dma->buf_count) return DRM_ERR(EINVAL); 981 if (iload.idx < 0 || iload.idx > dma->buf_count)
982 return DRM_ERR(EINVAL);
1026 983
1027 buf = dma->buflist[iload.idx]; 984 buf = dma->buflist[iload.idx];
1028 buf_priv = buf->dev_private; 985 buf_priv = buf->dev_private;
1029 986
1030 if ( mga_verify_iload( dev_priv, iload.dstorg, iload.length ) ) { 987 if (mga_verify_iload(dev_priv, iload.dstorg, iload.length)) {
1031 mga_freelist_put( dev, buf ); 988 mga_freelist_put(dev, buf);
1032 return DRM_ERR(EINVAL); 989 return DRM_ERR(EINVAL);
1033 } 990 }
1034 991
1035 WRAP_TEST_WITH_RETURN( dev_priv ); 992 WRAP_TEST_WITH_RETURN(dev_priv);
1036 993
1037 mga_dma_dispatch_iload( dev, buf, iload.dstorg, iload.length ); 994 mga_dma_dispatch_iload(dev, buf, iload.dstorg, iload.length);
1038 995
1039 /* Make sure we restore the 3D state next time. 996 /* Make sure we restore the 3D state next time.
1040 */ 997 */
@@ -1043,27 +1000,28 @@ static int mga_dma_iload( DRM_IOCTL_ARGS )
1043 return 0; 1000 return 0;
1044} 1001}
1045 1002
1046static int mga_dma_blit( DRM_IOCTL_ARGS ) 1003static int mga_dma_blit(DRM_IOCTL_ARGS)
1047{ 1004{
1048 DRM_DEVICE; 1005 DRM_DEVICE;
1049 drm_mga_private_t *dev_priv = dev->dev_private; 1006 drm_mga_private_t *dev_priv = dev->dev_private;
1050 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 1007 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
1051 drm_mga_blit_t blit; 1008 drm_mga_blit_t blit;
1052 DRM_DEBUG( "\n" ); 1009 DRM_DEBUG("\n");
1053 1010
1054 LOCK_TEST_WITH_RETURN( dev, filp ); 1011 LOCK_TEST_WITH_RETURN(dev, filp);
1055 1012
1056 DRM_COPY_FROM_USER_IOCTL( blit, (drm_mga_blit_t __user *)data, sizeof(blit) ); 1013 DRM_COPY_FROM_USER_IOCTL(blit, (drm_mga_blit_t __user *) data,
1014 sizeof(blit));
1057 1015
1058 if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) 1016 if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
1059 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; 1017 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
1060 1018
1061 if ( mga_verify_blit( dev_priv, blit.srcorg, blit.dstorg ) ) 1019 if (mga_verify_blit(dev_priv, blit.srcorg, blit.dstorg))
1062 return DRM_ERR(EINVAL); 1020 return DRM_ERR(EINVAL);
1063 1021
1064 WRAP_TEST_WITH_RETURN( dev_priv ); 1022 WRAP_TEST_WITH_RETURN(dev_priv);
1065 1023
1066 mga_dma_dispatch_blit( dev, &blit ); 1024 mga_dma_dispatch_blit(dev, &blit);
1067 1025
1068 /* Make sure we restore the 3D state next time. 1026 /* Make sure we restore the 3D state next time.
1069 */ 1027 */
@@ -1072,24 +1030,24 @@ static int mga_dma_blit( DRM_IOCTL_ARGS )
1072 return 0; 1030 return 0;
1073} 1031}
1074 1032
1075static int mga_getparam( DRM_IOCTL_ARGS ) 1033static int mga_getparam(DRM_IOCTL_ARGS)
1076{ 1034{
1077 DRM_DEVICE; 1035 DRM_DEVICE;
1078 drm_mga_private_t *dev_priv = dev->dev_private; 1036 drm_mga_private_t *dev_priv = dev->dev_private;
1079 drm_mga_getparam_t param; 1037 drm_mga_getparam_t param;
1080 int value; 1038 int value;
1081 1039
1082 if ( !dev_priv ) { 1040 if (!dev_priv) {
1083 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 1041 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1084 return DRM_ERR(EINVAL); 1042 return DRM_ERR(EINVAL);
1085 } 1043 }
1086 1044
1087 DRM_COPY_FROM_USER_IOCTL( param, (drm_mga_getparam_t __user *)data, 1045 DRM_COPY_FROM_USER_IOCTL(param, (drm_mga_getparam_t __user *) data,
1088 sizeof(param) ); 1046 sizeof(param));
1089 1047
1090 DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); 1048 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1091 1049
1092 switch( param.param ) { 1050 switch (param.param) {
1093 case MGA_PARAM_IRQ_NR: 1051 case MGA_PARAM_IRQ_NR:
1094 value = dev->irq; 1052 value = dev->irq;
1095 break; 1053 break;
@@ -1100,11 +1058,11 @@ static int mga_getparam( DRM_IOCTL_ARGS )
1100 return DRM_ERR(EINVAL); 1058 return DRM_ERR(EINVAL);
1101 } 1059 }
1102 1060
1103 if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { 1061 if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
1104 DRM_ERROR( "copy_to_user\n" ); 1062 DRM_ERROR("copy_to_user\n");
1105 return DRM_ERR(EFAULT); 1063 return DRM_ERR(EFAULT);
1106 } 1064 }
1107 1065
1108 return 0; 1066 return 0;
1109} 1067}
1110 1068
@@ -1132,11 +1090,10 @@ static int mga_set_fence(DRM_IOCTL_ARGS)
1132 BEGIN_DMA(1); 1090 BEGIN_DMA(1);
1133 DMA_BLOCK(MGA_DMAPAD, 0x00000000, 1091 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
1134 MGA_DMAPAD, 0x00000000, 1092 MGA_DMAPAD, 0x00000000,
1135 MGA_DMAPAD, 0x00000000, 1093 MGA_DMAPAD, 0x00000000, MGA_SOFTRAP, 0x00000000);
1136 MGA_SOFTRAP, 0x00000000);
1137 ADVANCE_DMA(); 1094 ADVANCE_DMA();
1138 1095
1139 if (DRM_COPY_TO_USER( (u32 __user *) data, & temp, sizeof(u32))) { 1096 if (DRM_COPY_TO_USER((u32 __user *) data, &temp, sizeof(u32))) {
1140 DRM_ERROR("copy_to_user\n"); 1097 DRM_ERROR("copy_to_user\n");
1141 return DRM_ERR(EFAULT); 1098 return DRM_ERR(EFAULT);
1142 } 1099 }
@@ -1159,9 +1116,9 @@ static int mga_wait_fence(DRM_IOCTL_ARGS)
1159 1116
1160 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); 1117 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1161 1118
1162 mga_driver_fence_wait(dev, & fence); 1119 mga_driver_fence_wait(dev, &fence);
1163 1120
1164 if (DRM_COPY_TO_USER( (u32 __user *) data, & fence, sizeof(u32))) { 1121 if (DRM_COPY_TO_USER((u32 __user *) data, &fence, sizeof(u32))) {
1165 DRM_ERROR("copy_to_user\n"); 1122 DRM_ERROR("copy_to_user\n");
1166 return DRM_ERR(EFAULT); 1123 return DRM_ERR(EFAULT);
1167 } 1124 }
@@ -1170,19 +1127,32 @@ static int mga_wait_fence(DRM_IOCTL_ARGS)
1170} 1127}
1171 1128
1172drm_ioctl_desc_t mga_ioctls[] = { 1129drm_ioctl_desc_t mga_ioctls[] = {
1173 [DRM_IOCTL_NR(DRM_MGA_INIT)] = {mga_dma_init, 1, 1}, 1130 [DRM_IOCTL_NR(DRM_MGA_INIT)] = {mga_dma_init, 1, 1}
1174 [DRM_IOCTL_NR(DRM_MGA_FLUSH)] = {mga_dma_flush, 1, 0}, 1131 ,
1175 [DRM_IOCTL_NR(DRM_MGA_RESET)] = {mga_dma_reset, 1, 0}, 1132 [DRM_IOCTL_NR(DRM_MGA_FLUSH)] = {mga_dma_flush, 1, 0}
1176 [DRM_IOCTL_NR(DRM_MGA_SWAP)] = {mga_dma_swap, 1, 0}, 1133 ,
1177 [DRM_IOCTL_NR(DRM_MGA_CLEAR)] = {mga_dma_clear, 1, 0}, 1134 [DRM_IOCTL_NR(DRM_MGA_RESET)] = {mga_dma_reset, 1, 0}
1178 [DRM_IOCTL_NR(DRM_MGA_VERTEX)] = {mga_dma_vertex, 1, 0}, 1135 ,
1179 [DRM_IOCTL_NR(DRM_MGA_INDICES)] = {mga_dma_indices, 1, 0}, 1136 [DRM_IOCTL_NR(DRM_MGA_SWAP)] = {mga_dma_swap, 1, 0}
1180 [DRM_IOCTL_NR(DRM_MGA_ILOAD)] = {mga_dma_iload, 1, 0}, 1137 ,
1181 [DRM_IOCTL_NR(DRM_MGA_BLIT)] = {mga_dma_blit, 1, 0}, 1138 [DRM_IOCTL_NR(DRM_MGA_CLEAR)] = {mga_dma_clear, 1, 0}
1182 [DRM_IOCTL_NR(DRM_MGA_GETPARAM)] = {mga_getparam, 1, 0}, 1139 ,
1183 [DRM_IOCTL_NR(DRM_MGA_SET_FENCE)] = {mga_set_fence, 1, 0}, 1140 [DRM_IOCTL_NR(DRM_MGA_VERTEX)] = {mga_dma_vertex, 1, 0}
1184 [DRM_IOCTL_NR(DRM_MGA_WAIT_FENCE)] = {mga_wait_fence, 1, 0}, 1141 ,
1185 [DRM_IOCTL_NR(DRM_MGA_DMA_BOOTSTRAP)] = {mga_dma_bootstrap, 1, 1}, 1142 [DRM_IOCTL_NR(DRM_MGA_INDICES)] = {mga_dma_indices, 1, 0}
1143 ,
1144 [DRM_IOCTL_NR(DRM_MGA_ILOAD)] = {mga_dma_iload, 1, 0}
1145 ,
1146 [DRM_IOCTL_NR(DRM_MGA_BLIT)] = {mga_dma_blit, 1, 0}
1147 ,
1148 [DRM_IOCTL_NR(DRM_MGA_GETPARAM)] = {mga_getparam, 1, 0}
1149 ,
1150 [DRM_IOCTL_NR(DRM_MGA_SET_FENCE)] = {mga_set_fence, 1, 0}
1151 ,
1152 [DRM_IOCTL_NR(DRM_MGA_WAIT_FENCE)] = {mga_wait_fence, 1, 0}
1153 ,
1154 [DRM_IOCTL_NR(DRM_MGA_DMA_BOOTSTRAP)] = {mga_dma_bootstrap, 1, 1}
1155 ,
1186 1156
1187}; 1157};
1188 1158
diff --git a/drivers/char/drm/mga_ucode.h b/drivers/char/drm/mga_ucode.h
index fa0f82ec9fa0..b611e27470e1 100644
--- a/drivers/char/drm/mga_ucode.h
+++ b/drivers/char/drm/mga_ucode.h
@@ -40,11606 +40,11606 @@
40 40
41static unsigned char warp_g200_tgz[] = { 41static unsigned char warp_g200_tgz[] = {
42 42
430x00, 0x80, 0x00, 0xE8, 43 0x00, 0x80, 0x00, 0xE8,
440x00, 0x80, 0x00, 0xE8, 44 0x00, 0x80, 0x00, 0xE8,
45 45
460x00, 0x80, 0x00, 0xE8, 46 0x00, 0x80, 0x00, 0xE8,
470x00, 0x80, 0x00, 0xE8, 47 0x00, 0x80, 0x00, 0xE8,
48 48
490x00, 0x80, 0x00, 0xE8, 49 0x00, 0x80, 0x00, 0xE8,
500x00, 0x80, 0x00, 0xE8, 50 0x00, 0x80, 0x00, 0xE8,
51 51
520x00, 0x80, 0x00, 0xE8, 52 0x00, 0x80, 0x00, 0xE8,
530x00, 0x80, 0x00, 0xE8, 53 0x00, 0x80, 0x00, 0xE8,
54 54
550x00, 0x80, 0x00, 0xE8, 55 0x00, 0x80, 0x00, 0xE8,
560x00, 0x80, 0x00, 0xE8, 56 0x00, 0x80, 0x00, 0xE8,
57 57
580x00, 0x98, 0xA0, 0xE9, 58 0x00, 0x98, 0xA0, 0xE9,
590x40, 0x40, 0xD8, 0xEC, 59 0x40, 0x40, 0xD8, 0xEC,
60 60
610xFF, 0x80, 0xC0, 0xE9, 61 0xFF, 0x80, 0xC0, 0xE9,
620x00, 0x80, 0x00, 0xE8, 62 0x00, 0x80, 0x00, 0xE8,
63 63
640x1F, 0xD7, 0x18, 0xBD, 64 0x1F, 0xD7, 0x18, 0xBD,
650x3F, 0xD7, 0x22, 0xBD, 65 0x3F, 0xD7, 0x22, 0xBD,
66 66
670x81, 0x04, 67 0x81, 0x04,
680x89, 0x04, 68 0x89, 0x04,
690x01, 0x04, 69 0x01, 0x04,
700x09, 0x04, 70 0x09, 0x04,
71 71
720xC9, 0x41, 0xC0, 0xEC, 72 0xC9, 0x41, 0xC0, 0xEC,
730x11, 0x04, 73 0x11, 0x04,
740x00, 0xE0, 74 0x00, 0xE0,
75 75
760x41, 0xCC, 0x41, 0xCD, 76 0x41, 0xCC, 0x41, 0xCD,
770x49, 0xCC, 0x49, 0xCD, 77 0x49, 0xCC, 0x49, 0xCD,
78 78
790xD1, 0x41, 0xC0, 0xEC, 79 0xD1, 0x41, 0xC0, 0xEC,
800x51, 0xCC, 0x51, 0xCD, 80 0x51, 0xCC, 0x51, 0xCD,
81 81
820x80, 0x04, 82 0x80, 0x04,
830x10, 0x04, 83 0x10, 0x04,
840x08, 0x04, 84 0x08, 0x04,
850x00, 0xE0, 85 0x00, 0xE0,
86 86
870x00, 0xCC, 0xC0, 0xCD, 87 0x00, 0xCC, 0xC0, 0xCD,
880xD1, 0x49, 0xC0, 0xEC, 88 0xD1, 0x49, 0xC0, 0xEC,
89 89
900x8A, 0x1F, 0x20, 0xE9, 90 0x8A, 0x1F, 0x20, 0xE9,
910x8B, 0x3F, 0x20, 0xE9, 91 0x8B, 0x3F, 0x20, 0xE9,
92 92
930x41, 0x3C, 0x41, 0xAD, 93 0x41, 0x3C, 0x41, 0xAD,
940x49, 0x3C, 0x49, 0xAD, 94 0x49, 0x3C, 0x49, 0xAD,
95 95
960x10, 0xCC, 0x10, 0xCD, 96 0x10, 0xCC, 0x10, 0xCD,
970x08, 0xCC, 0x08, 0xCD, 97 0x08, 0xCC, 0x08, 0xCD,
98 98
990xB9, 0x41, 0x49, 0xBB, 99 0xB9, 0x41, 0x49, 0xBB,
1000x1F, 0xF0, 0x41, 0xCD, 100 0x1F, 0xF0, 0x41, 0xCD,
101 101
1020x51, 0x3C, 0x51, 0xAD, 102 0x51, 0x3C, 0x51, 0xAD,
1030x00, 0x98, 0x80, 0xE9, 103 0x00, 0x98, 0x80, 0xE9,
104 104
1050x72, 0x80, 0x07, 0xEA, 105 0x72, 0x80, 0x07, 0xEA,
1060x24, 0x1F, 0x20, 0xE9, 106 0x24, 0x1F, 0x20, 0xE9,
107 107
1080x15, 0x41, 0x49, 0xBD, 108 0x15, 0x41, 0x49, 0xBD,
1090x1D, 0x41, 0x51, 0xBD, 109 0x1D, 0x41, 0x51, 0xBD,
110 110
1110x2E, 0x41, 0x2A, 0xB8, 111 0x2E, 0x41, 0x2A, 0xB8,
1120x34, 0x53, 0xA0, 0xE8, 112 0x34, 0x53, 0xA0, 0xE8,
113 113
1140x15, 0x30, 114 0x15, 0x30,
1150x1D, 0x30, 115 0x1D, 0x30,
1160x58, 0xE3, 116 0x58, 0xE3,
1170x00, 0xE0, 117 0x00, 0xE0,
118 118
1190xB5, 0x40, 0x48, 0xBD, 119 0xB5, 0x40, 0x48, 0xBD,
1200x3D, 0x40, 0x50, 0xBD, 120 0x3D, 0x40, 0x50, 0xBD,
121 121
1220x24, 0x43, 0xA0, 0xE8, 122 0x24, 0x43, 0xA0, 0xE8,
1230x2C, 0x4B, 0xA0, 0xE8, 123 0x2C, 0x4B, 0xA0, 0xE8,
124 124
1250x15, 0x72, 125 0x15, 0x72,
1260x09, 0xE3, 126 0x09, 0xE3,
1270x00, 0xE0, 127 0x00, 0xE0,
1280x1D, 0x72, 128 0x1D, 0x72,
129 129
1300x35, 0x30, 130 0x35, 0x30,
1310xB5, 0x30, 131 0xB5, 0x30,
1320xBD, 0x30, 132 0xBD, 0x30,
1330x3D, 0x30, 133 0x3D, 0x30,
134 134
1350x9C, 0x97, 0x57, 0x9F, 135 0x9C, 0x97, 0x57, 0x9F,
1360x00, 0x80, 0x00, 0xE8, 136 0x00, 0x80, 0x00, 0xE8,
137 137
1380x6C, 0x64, 0xC8, 0xEC, 138 0x6C, 0x64, 0xC8, 0xEC,
1390x98, 0xE1, 139 0x98, 0xE1,
1400xB5, 0x05, 140 0xB5, 0x05,
141 141
1420xBD, 0x05, 142 0xBD, 0x05,
1430x2E, 0x30, 143 0x2E, 0x30,
1440x32, 0xC0, 0xA0, 0xE8, 144 0x32, 0xC0, 0xA0, 0xE8,
145 145
1460x33, 0xC0, 0xA0, 0xE8, 146 0x33, 0xC0, 0xA0, 0xE8,
1470x74, 0x64, 0xC8, 0xEC, 147 0x74, 0x64, 0xC8, 0xEC,
148 148
1490x40, 0x3C, 0x40, 0xAD, 149 0x40, 0x3C, 0x40, 0xAD,
1500x32, 0x6A, 150 0x32, 0x6A,
1510x2A, 0x30, 151 0x2A, 0x30,
152 152
1530x20, 0x73, 153 0x20, 0x73,
1540x33, 0x6A, 154 0x33, 0x6A,
1550x00, 0xE0, 155 0x00, 0xE0,
1560x28, 0x73, 156 0x28, 0x73,
157 157
1580x1C, 0x72, 158 0x1C, 0x72,
1590x83, 0xE2, 159 0x83, 0xE2,
1600x60, 0x80, 0x15, 0xEA, 160 0x60, 0x80, 0x15, 0xEA,
161 161
1620xB8, 0x3D, 0x28, 0xDF, 162 0xB8, 0x3D, 0x28, 0xDF,
1630x30, 0x35, 0x20, 0xDF, 163 0x30, 0x35, 0x20, 0xDF,
164 164
1650x40, 0x30, 165 0x40, 0x30,
1660x00, 0xE0, 166 0x00, 0xE0,
1670xCC, 0xE2, 167 0xCC, 0xE2,
1680x64, 0x72, 168 0x64, 0x72,
169 169
1700x25, 0x42, 0x52, 0xBF, 170 0x25, 0x42, 0x52, 0xBF,
1710x2D, 0x42, 0x4A, 0xBF, 171 0x2D, 0x42, 0x4A, 0xBF,
172 172
1730x30, 0x2E, 0x30, 0xDF, 173 0x30, 0x2E, 0x30, 0xDF,
1740x38, 0x2E, 0x38, 0xDF, 174 0x38, 0x2E, 0x38, 0xDF,
175 175
1760x18, 0x1D, 0x45, 0xE9, 176 0x18, 0x1D, 0x45, 0xE9,
1770x1E, 0x15, 0x45, 0xE9, 177 0x1E, 0x15, 0x45, 0xE9,
178 178
1790x2B, 0x49, 0x51, 0xBD, 179 0x2B, 0x49, 0x51, 0xBD,
1800x00, 0xE0, 180 0x00, 0xE0,
1810x1F, 0x73, 181 0x1F, 0x73,
182 182
1830x38, 0x38, 0x40, 0xAF, 183 0x38, 0x38, 0x40, 0xAF,
1840x30, 0x30, 0x40, 0xAF, 184 0x30, 0x30, 0x40, 0xAF,
185 185
1860x24, 0x1F, 0x24, 0xDF, 186 0x24, 0x1F, 0x24, 0xDF,
1870x1D, 0x32, 0x20, 0xE9, 187 0x1D, 0x32, 0x20, 0xE9,
188 188
1890x2C, 0x1F, 0x2C, 0xDF, 189 0x2C, 0x1F, 0x2C, 0xDF,
1900x1A, 0x33, 0x20, 0xE9, 190 0x1A, 0x33, 0x20, 0xE9,
191 191
1920xB0, 0x10, 192 0xB0, 0x10,
1930x08, 0xE3, 193 0x08, 0xE3,
1940x40, 0x10, 194 0x40, 0x10,
1950xB8, 0x10, 195 0xB8, 0x10,
196 196
1970x26, 0xF0, 0x30, 0xCD, 197 0x26, 0xF0, 0x30, 0xCD,
1980x2F, 0xF0, 0x38, 0xCD, 198 0x2F, 0xF0, 0x38, 0xCD,
199 199
2000x2B, 0x80, 0x20, 0xE9, 200 0x2B, 0x80, 0x20, 0xE9,
2010x2A, 0x80, 0x20, 0xE9, 201 0x2A, 0x80, 0x20, 0xE9,
202 202
2030xA6, 0x20, 203 0xA6, 0x20,
2040x88, 0xE2, 204 0x88, 0xE2,
2050x00, 0xE0, 205 0x00, 0xE0,
2060xAF, 0x20, 206 0xAF, 0x20,
207 207
2080x28, 0x2A, 0x26, 0xAF, 208 0x28, 0x2A, 0x26, 0xAF,
2090x20, 0x2A, 0xC0, 0xAF, 209 0x20, 0x2A, 0xC0, 0xAF,
210 210
2110x34, 0x1F, 0x34, 0xDF, 211 0x34, 0x1F, 0x34, 0xDF,
2120x46, 0x24, 0x46, 0xDF, 212 0x46, 0x24, 0x46, 0xDF,
213 213
2140x28, 0x30, 0x80, 0xBF, 214 0x28, 0x30, 0x80, 0xBF,
2150x20, 0x38, 0x80, 0xBF, 215 0x20, 0x38, 0x80, 0xBF,
216 216
2170x47, 0x24, 0x47, 0xDF, 217 0x47, 0x24, 0x47, 0xDF,
2180x4E, 0x2C, 0x4E, 0xDF, 218 0x4E, 0x2C, 0x4E, 0xDF,
219 219
2200x4F, 0x2C, 0x4F, 0xDF, 220 0x4F, 0x2C, 0x4F, 0xDF,
2210x56, 0x34, 0x56, 0xDF, 221 0x56, 0x34, 0x56, 0xDF,
222 222
2230x28, 0x15, 0x28, 0xDF, 223 0x28, 0x15, 0x28, 0xDF,
2240x20, 0x1D, 0x20, 0xDF, 224 0x20, 0x1D, 0x20, 0xDF,
225 225
2260x57, 0x34, 0x57, 0xDF, 226 0x57, 0x34, 0x57, 0xDF,
2270x00, 0xE0, 227 0x00, 0xE0,
2280x1D, 0x05, 228 0x1D, 0x05,
229 229
2300x04, 0x80, 0x10, 0xEA, 230 0x04, 0x80, 0x10, 0xEA,
2310x89, 0xE2, 231 0x89, 0xE2,
2320x2B, 0x30, 232 0x2B, 0x30,
233 233
2340x3F, 0xC1, 0x1D, 0xBD, 234 0x3F, 0xC1, 0x1D, 0xBD,
2350x00, 0x80, 0x00, 0xE8, 235 0x00, 0x80, 0x00, 0xE8,
236 236
2370x00, 0x80, 0x00, 0xE8, 237 0x00, 0x80, 0x00, 0xE8,
2380x00, 0x80, 0x00, 0xE8, 238 0x00, 0x80, 0x00, 0xE8,
239 239
2400xA0, 0x68, 240 0xA0, 0x68,
2410xBF, 0x25, 241 0xBF, 0x25,
2420x00, 0x80, 0x00, 0xE8, 242 0x00, 0x80, 0x00, 0xE8,
243 243
2440x20, 0xC0, 0x20, 0xAF, 244 0x20, 0xC0, 0x20, 0xAF,
2450x28, 0x05, 245 0x28, 0x05,
2460x97, 0x74, 246 0x97, 0x74,
247 247
2480x00, 0xE0, 248 0x00, 0xE0,
2490x2A, 0x10, 249 0x2A, 0x10,
2500x16, 0xC0, 0x20, 0xE9, 250 0x16, 0xC0, 0x20, 0xE9,
251 251
2520x04, 0x80, 0x10, 0xEA, 252 0x04, 0x80, 0x10, 0xEA,
2530x8C, 0xE2, 253 0x8C, 0xE2,
2540x95, 0x05, 254 0x95, 0x05,
255 255
2560x28, 0xC1, 0x28, 0xAD, 256 0x28, 0xC1, 0x28, 0xAD,
2570x1F, 0xC1, 0x15, 0xBD, 257 0x1F, 0xC1, 0x15, 0xBD,
258 258
2590x00, 0x80, 0x00, 0xE8, 259 0x00, 0x80, 0x00, 0xE8,
2600x00, 0x80, 0x00, 0xE8, 260 0x00, 0x80, 0x00, 0xE8,
261 261
2620xA8, 0x67, 262 0xA8, 0x67,
2630x9F, 0x6B, 263 0x9F, 0x6B,
2640x00, 0x80, 0x00, 0xE8, 264 0x00, 0x80, 0x00, 0xE8,
265 265
2660x28, 0xC0, 0x28, 0xAD, 266 0x28, 0xC0, 0x28, 0xAD,
2670x1D, 0x25, 267 0x1D, 0x25,
2680x20, 0x05, 268 0x20, 0x05,
269 269
2700x28, 0x32, 0x80, 0xAD, 270 0x28, 0x32, 0x80, 0xAD,
2710x40, 0x2A, 0x40, 0xBD, 271 0x40, 0x2A, 0x40, 0xBD,
272 272
2730x1C, 0x80, 0x20, 0xE9, 273 0x1C, 0x80, 0x20, 0xE9,
2740x20, 0x33, 0x20, 0xAD, 274 0x20, 0x33, 0x20, 0xAD,
275 275
2760x20, 0x73, 276 0x20, 0x73,
2770x00, 0xE0, 277 0x00, 0xE0,
2780xB6, 0x49, 0x51, 0xBB, 278 0xB6, 0x49, 0x51, 0xBB,
279 279
2800x26, 0x2F, 0xB0, 0xE8, 280 0x26, 0x2F, 0xB0, 0xE8,
2810x19, 0x20, 0x20, 0xE9, 281 0x19, 0x20, 0x20, 0xE9,
282 282
2830x35, 0x20, 0x35, 0xDF, 283 0x35, 0x20, 0x35, 0xDF,
2840x3D, 0x20, 0x3D, 0xDF, 284 0x3D, 0x20, 0x3D, 0xDF,
285 285
2860x15, 0x20, 0x15, 0xDF, 286 0x15, 0x20, 0x15, 0xDF,
2870x1D, 0x20, 0x1D, 0xDF, 287 0x1D, 0x20, 0x1D, 0xDF,
288 288
2890x26, 0xD0, 0x26, 0xCD, 289 0x26, 0xD0, 0x26, 0xCD,
2900x29, 0x49, 0x2A, 0xB8, 290 0x29, 0x49, 0x2A, 0xB8,
291 291
2920x26, 0x40, 0x80, 0xBD, 292 0x26, 0x40, 0x80, 0xBD,
2930x3B, 0x48, 0x50, 0xBD, 293 0x3B, 0x48, 0x50, 0xBD,
294 294
2950x3E, 0x54, 0x57, 0x9F, 295 0x3E, 0x54, 0x57, 0x9F,
2960x00, 0xE0, 296 0x00, 0xE0,
2970x82, 0xE1, 297 0x82, 0xE1,
298 298
2990x1E, 0xAF, 0x59, 0x9F, 299 0x1E, 0xAF, 0x59, 0x9F,
3000x00, 0x80, 0x00, 0xE8, 300 0x00, 0x80, 0x00, 0xE8,
301 301
3020x26, 0x30, 302 0x26, 0x30,
3030x29, 0x30, 303 0x29, 0x30,
3040x48, 0x3C, 0x48, 0xAD, 304 0x48, 0x3C, 0x48, 0xAD,
305 305
3060x2B, 0x72, 306 0x2B, 0x72,
3070xC2, 0xE1, 307 0xC2, 0xE1,
3080x2C, 0xC0, 0x44, 0xC2, 308 0x2C, 0xC0, 0x44, 0xC2,
309 309
3100x05, 0x24, 0x34, 0xBF, 310 0x05, 0x24, 0x34, 0xBF,
3110x0D, 0x24, 0x2C, 0xBF, 311 0x0D, 0x24, 0x2C, 0xBF,
312 312
3130x2D, 0x46, 0x4E, 0xBF, 313 0x2D, 0x46, 0x4E, 0xBF,
3140x25, 0x46, 0x56, 0xBF, 314 0x25, 0x46, 0x56, 0xBF,
315 315
3160x20, 0x1D, 0x6F, 0x8F, 316 0x20, 0x1D, 0x6F, 0x8F,
3170x32, 0x3E, 0x5F, 0xE9, 317 0x32, 0x3E, 0x5F, 0xE9,
318 318
3190x3E, 0x50, 0x56, 0x9F, 319 0x3E, 0x50, 0x56, 0x9F,
3200x00, 0xE0, 320 0x00, 0xE0,
3210x3B, 0x30, 321 0x3B, 0x30,
322 322
3230x1E, 0x8F, 0x51, 0x9F, 323 0x1E, 0x8F, 0x51, 0x9F,
3240x33, 0x1E, 0x5F, 0xE9, 324 0x33, 0x1E, 0x5F, 0xE9,
325 325
3260x05, 0x44, 0x54, 0xB2, 326 0x05, 0x44, 0x54, 0xB2,
3270x0D, 0x44, 0x4C, 0xB2, 327 0x0D, 0x44, 0x4C, 0xB2,
328 328
3290x19, 0xC0, 0xB0, 0xE8, 329 0x19, 0xC0, 0xB0, 0xE8,
3300x34, 0xC0, 0x44, 0xC4, 330 0x34, 0xC0, 0x44, 0xC4,
331 331
3320x33, 0x73, 332 0x33, 0x73,
3330x00, 0xE0, 333 0x00, 0xE0,
3340x3E, 0x62, 0x57, 0x9F, 334 0x3E, 0x62, 0x57, 0x9F,
335 335
3360x1E, 0xAF, 0x59, 0x9F, 336 0x1E, 0xAF, 0x59, 0x9F,
3370x00, 0xE0, 337 0x00, 0xE0,
3380x0D, 0x20, 338 0x0D, 0x20,
339 339
3400x84, 0x3E, 0x58, 0xE9, 340 0x84, 0x3E, 0x58, 0xE9,
3410x28, 0x1D, 0x6F, 0x8F, 341 0x28, 0x1D, 0x6F, 0x8F,
342 342
3430x05, 0x20, 343 0x05, 0x20,
3440x00, 0xE0, 344 0x00, 0xE0,
3450x85, 0x1E, 0x58, 0xE9, 345 0x85, 0x1E, 0x58, 0xE9,
346 346
3470x9B, 0x3B, 0x33, 0xDF, 347 0x9B, 0x3B, 0x33, 0xDF,
3480x20, 0x20, 0x42, 0xAF, 348 0x20, 0x20, 0x42, 0xAF,
349 349
3500x30, 0x42, 0x56, 0x9F, 350 0x30, 0x42, 0x56, 0x9F,
3510x80, 0x3E, 0x57, 0xE9, 351 0x80, 0x3E, 0x57, 0xE9,
352 352
3530x3F, 0x8F, 0x51, 0x9F, 353 0x3F, 0x8F, 0x51, 0x9F,
3540x30, 0x80, 0x5F, 0xE9, 354 0x30, 0x80, 0x5F, 0xE9,
355 355
3560x28, 0x28, 0x24, 0xAF, 356 0x28, 0x28, 0x24, 0xAF,
3570x81, 0x1E, 0x57, 0xE9, 357 0x81, 0x1E, 0x57, 0xE9,
358 358
3590x05, 0x47, 0x57, 0xBF, 359 0x05, 0x47, 0x57, 0xBF,
3600x0D, 0x47, 0x4F, 0xBF, 360 0x0D, 0x47, 0x4F, 0xBF,
361 361
3620x88, 0x80, 0x58, 0xE9, 362 0x88, 0x80, 0x58, 0xE9,
3630x1B, 0x29, 0x1B, 0xDF, 363 0x1B, 0x29, 0x1B, 0xDF,
364 364
3650x30, 0x1D, 0x6F, 0x8F, 365 0x30, 0x1D, 0x6F, 0x8F,
3660x3A, 0x30, 0x4F, 0xE9, 366 0x3A, 0x30, 0x4F, 0xE9,
367 367
3680x1C, 0x30, 0x26, 0xDF, 368 0x1C, 0x30, 0x26, 0xDF,
3690x09, 0xE3, 369 0x09, 0xE3,
3700x3B, 0x05, 370 0x3B, 0x05,
371 371
3720x3E, 0x50, 0x56, 0x9F, 372 0x3E, 0x50, 0x56, 0x9F,
3730x3B, 0x3F, 0x4F, 0xE9, 373 0x3B, 0x3F, 0x4F, 0xE9,
374 374
3750x1E, 0x8F, 0x51, 0x9F, 375 0x1E, 0x8F, 0x51, 0x9F,
3760x00, 0xE0, 376 0x00, 0xE0,
3770xAC, 0x20, 377 0xAC, 0x20,
378 378
3790x2D, 0x44, 0x4C, 0xB4, 379 0x2D, 0x44, 0x4C, 0xB4,
3800x2C, 0x1C, 0xC0, 0xAF, 380 0x2C, 0x1C, 0xC0, 0xAF,
381 381
3820x25, 0x44, 0x54, 0xB4, 382 0x25, 0x44, 0x54, 0xB4,
3830x00, 0xE0, 383 0x00, 0xE0,
3840xC8, 0x30, 384 0xC8, 0x30,
385 385
3860x30, 0x46, 0x30, 0xAF, 386 0x30, 0x46, 0x30, 0xAF,
3870x1B, 0x1B, 0x48, 0xAF, 387 0x1B, 0x1B, 0x48, 0xAF,
388 388
3890x00, 0xE0, 389 0x00, 0xE0,
3900x25, 0x20, 390 0x25, 0x20,
3910x38, 0x2C, 0x4F, 0xE9, 391 0x38, 0x2C, 0x4F, 0xE9,
392 392
3930x86, 0x80, 0x57, 0xE9, 393 0x86, 0x80, 0x57, 0xE9,
3940x38, 0x1D, 0x6F, 0x8F, 394 0x38, 0x1D, 0x6F, 0x8F,
395 395
3960x28, 0x74, 396 0x28, 0x74,
3970x00, 0xE0, 397 0x00, 0xE0,
3980x0D, 0x44, 0x4C, 0xB0, 398 0x0D, 0x44, 0x4C, 0xB0,
399 399
4000x05, 0x44, 0x54, 0xB0, 400 0x05, 0x44, 0x54, 0xB0,
4010x2D, 0x20, 401 0x2D, 0x20,
4020x9B, 0x10, 402 0x9B, 0x10,
403 403
4040x82, 0x3E, 0x57, 0xE9, 404 0x82, 0x3E, 0x57, 0xE9,
4050x32, 0xF0, 0x1B, 0xCD, 405 0x32, 0xF0, 0x1B, 0xCD,
406 406
4070x1E, 0xBD, 0x59, 0x9F, 407 0x1E, 0xBD, 0x59, 0x9F,
4080x83, 0x1E, 0x57, 0xE9, 408 0x83, 0x1E, 0x57, 0xE9,
409 409
4100x38, 0x47, 0x38, 0xAF, 410 0x38, 0x47, 0x38, 0xAF,
4110x34, 0x20, 411 0x34, 0x20,
4120x2A, 0x30, 412 0x2A, 0x30,
413 413
4140x00, 0xE0, 414 0x00, 0xE0,
4150x0D, 0x20, 415 0x0D, 0x20,
4160x32, 0x20, 416 0x32, 0x20,
4170x05, 0x20, 417 0x05, 0x20,
418 418
4190x87, 0x80, 0x57, 0xE9, 419 0x87, 0x80, 0x57, 0xE9,
4200x1F, 0x54, 0x57, 0x9F, 420 0x1F, 0x54, 0x57, 0x9F,
421 421
4220x17, 0x42, 0x56, 0x9F, 422 0x17, 0x42, 0x56, 0x9F,
4230x00, 0xE0, 423 0x00, 0xE0,
4240x3B, 0x6A, 424 0x3B, 0x6A,
425 425
4260x3F, 0x8F, 0x51, 0x9F, 426 0x3F, 0x8F, 0x51, 0x9F,
4270x37, 0x1E, 0x4F, 0xE9, 427 0x37, 0x1E, 0x4F, 0xE9,
428 428
4290x37, 0x32, 0x2A, 0xAF, 429 0x37, 0x32, 0x2A, 0xAF,
4300x00, 0xE0, 430 0x00, 0xE0,
4310x32, 0x00, 431 0x32, 0x00,
432 432
4330x00, 0x80, 0x00, 0xE8, 433 0x00, 0x80, 0x00, 0xE8,
4340x27, 0xC0, 0x44, 0xC0, 434 0x27, 0xC0, 0x44, 0xC0,
435 435
4360x36, 0x1F, 0x4F, 0xE9, 436 0x36, 0x1F, 0x4F, 0xE9,
4370x1F, 0x1F, 0x26, 0xDF, 437 0x1F, 0x1F, 0x26, 0xDF,
438 438
4390x37, 0x1B, 0x37, 0xBF, 439 0x37, 0x1B, 0x37, 0xBF,
4400x17, 0x26, 0x17, 0xDF, 440 0x17, 0x26, 0x17, 0xDF,
441 441
4420x3E, 0x17, 0x4F, 0xE9, 442 0x3E, 0x17, 0x4F, 0xE9,
4430x3F, 0x3F, 0x4F, 0xE9, 443 0x3F, 0x3F, 0x4F, 0xE9,
444 444
4450x34, 0x1F, 0x34, 0xAF, 445 0x34, 0x1F, 0x34, 0xAF,
4460x2B, 0x05, 446 0x2B, 0x05,
4470xA7, 0x20, 447 0xA7, 0x20,
448 448
4490x33, 0x2B, 0x37, 0xDF, 449 0x33, 0x2B, 0x37, 0xDF,
4500x27, 0x17, 0xC0, 0xAF, 450 0x27, 0x17, 0xC0, 0xAF,
451 451
4520x34, 0x80, 0x4F, 0xE9, 452 0x34, 0x80, 0x4F, 0xE9,
4530x00, 0x80, 0x00, 0xE8, 453 0x00, 0x80, 0x00, 0xE8,
454 454
4550x03, 0x80, 0x0A, 0xEA, 455 0x03, 0x80, 0x0A, 0xEA,
4560x17, 0xC1, 0x2B, 0xBD, 456 0x17, 0xC1, 0x2B, 0xBD,
457 457
4580x00, 0x80, 0x00, 0xE8, 458 0x00, 0x80, 0x00, 0xE8,
4590x00, 0x80, 0x00, 0xE8, 459 0x00, 0x80, 0x00, 0xE8,
460 460
4610xB3, 0x68, 461 0xB3, 0x68,
4620x97, 0x25, 462 0x97, 0x25,
4630x00, 0x80, 0x00, 0xE8, 463 0x00, 0x80, 0x00, 0xE8,
464 464
4650x33, 0xC0, 0x33, 0xAF, 465 0x33, 0xC0, 0x33, 0xAF,
4660x3C, 0x27, 0x4F, 0xE9, 466 0x3C, 0x27, 0x4F, 0xE9,
467 467
4680x57, 0x39, 0x20, 0xE9, 468 0x57, 0x39, 0x20, 0xE9,
4690x28, 0x19, 0x60, 0xEC, 469 0x28, 0x19, 0x60, 0xEC,
470 470
4710x2B, 0x32, 0x20, 0xE9, 471 0x2B, 0x32, 0x20, 0xE9,
4720x1D, 0x3B, 0x20, 0xE9, 472 0x1D, 0x3B, 0x20, 0xE9,
473 473
4740xB3, 0x05, 474 0xB3, 0x05,
4750x00, 0xE0, 475 0x00, 0xE0,
4760x16, 0x28, 0x20, 0xE9, 476 0x16, 0x28, 0x20, 0xE9,
477 477
4780x23, 0x3B, 0x33, 0xAD, 478 0x23, 0x3B, 0x33, 0xAD,
4790x1E, 0x2B, 0x20, 0xE9, 479 0x1E, 0x2B, 0x20, 0xE9,
480 480
4810x1C, 0x80, 0x20, 0xE9, 481 0x1C, 0x80, 0x20, 0xE9,
4820x57, 0x36, 0x20, 0xE9, 482 0x57, 0x36, 0x20, 0xE9,
483 483
4840x00, 0x80, 0xA0, 0xE9, 484 0x00, 0x80, 0xA0, 0xE9,
4850x40, 0x40, 0xD8, 0xEC, 485 0x40, 0x40, 0xD8, 0xEC,
486 486
4870xFF, 0x80, 0xC0, 0xE9, 487 0xFF, 0x80, 0xC0, 0xE9,
4880x90, 0xE2, 488 0x90, 0xE2,
4890x00, 0xE0, 489 0x00, 0xE0,
490 490
4910x85, 0xFF, 0x20, 0xEA, 491 0x85, 0xFF, 0x20, 0xEA,
4920x19, 0xC8, 0xC1, 0xCD, 492 0x19, 0xC8, 0xC1, 0xCD,
493 493
4940x1F, 0xD7, 0x18, 0xBD, 494 0x1F, 0xD7, 0x18, 0xBD,
4950x3F, 0xD7, 0x22, 0xBD, 495 0x3F, 0xD7, 0x22, 0xBD,
496 496
4970x9F, 0x41, 0x49, 0xBD, 497 0x9F, 0x41, 0x49, 0xBD,
4980x00, 0x80, 0x00, 0xE8, 498 0x00, 0x80, 0x00, 0xE8,
499 499
5000x25, 0x41, 0x49, 0xBD, 500 0x25, 0x41, 0x49, 0xBD,
5010x2D, 0x41, 0x51, 0xBD, 501 0x2D, 0x41, 0x51, 0xBD,
502 502
5030x0D, 0x80, 0x07, 0xEA, 503 0x0D, 0x80, 0x07, 0xEA,
5040x00, 0x80, 0x00, 0xE8, 504 0x00, 0x80, 0x00, 0xE8,
505 505
5060x35, 0x40, 0x48, 0xBD, 506 0x35, 0x40, 0x48, 0xBD,
5070x3D, 0x40, 0x50, 0xBD, 507 0x3D, 0x40, 0x50, 0xBD,
508 508
5090x00, 0x80, 0x00, 0xE8, 509 0x00, 0x80, 0x00, 0xE8,
5100x25, 0x30, 510 0x25, 0x30,
5110x2D, 0x30, 511 0x2D, 0x30,
512 512
5130x35, 0x30, 513 0x35, 0x30,
5140xB5, 0x30, 514 0xB5, 0x30,
5150xBD, 0x30, 515 0xBD, 0x30,
5160x3D, 0x30, 516 0x3D, 0x30,
517 517
5180x9C, 0xA7, 0x5B, 0x9F, 518 0x9C, 0xA7, 0x5B, 0x9F,
5190x00, 0x80, 0x00, 0xE8, 519 0x00, 0x80, 0x00, 0xE8,
520 520
5210x00, 0x80, 0x00, 0xE8, 521 0x00, 0x80, 0x00, 0xE8,
5220x00, 0x80, 0x00, 0xE8, 522 0x00, 0x80, 0x00, 0xE8,
523 523
5240x00, 0x80, 0x00, 0xE8, 524 0x00, 0x80, 0x00, 0xE8,
5250x00, 0x80, 0x00, 0xE8, 525 0x00, 0x80, 0x00, 0xE8,
526 526
5270x00, 0x80, 0x00, 0xE8, 527 0x00, 0x80, 0x00, 0xE8,
5280x00, 0x80, 0x00, 0xE8, 528 0x00, 0x80, 0x00, 0xE8,
529 529
5300x00, 0x80, 0x00, 0xE8, 530 0x00, 0x80, 0x00, 0xE8,
5310x00, 0x80, 0x00, 0xE8, 531 0x00, 0x80, 0x00, 0xE8,
532 532
5330x84, 0xFF, 0x0A, 0xEA, 533 0x84, 0xFF, 0x0A, 0xEA,
5340x00, 0x80, 0x00, 0xE8, 534 0x00, 0x80, 0x00, 0xE8,
535 535
5360xC9, 0x41, 0xC8, 0xEC, 536 0xC9, 0x41, 0xC8, 0xEC,
5370x42, 0xE1, 537 0x42, 0xE1,
5380x00, 0xE0, 538 0x00, 0xE0,
539 539
5400x82, 0xFF, 0x20, 0xEA, 540 0x82, 0xFF, 0x20, 0xEA,
5410x00, 0x80, 0x00, 0xE8, 541 0x00, 0x80, 0x00, 0xE8,
542 542
5430x00, 0x80, 0x00, 0xE8, 543 0x00, 0x80, 0x00, 0xE8,
5440x00, 0x80, 0x00, 0xE8, 544 0x00, 0x80, 0x00, 0xE8,
545 545
5460xC8, 0x40, 0xC0, 0xEC, 546 0xC8, 0x40, 0xC0, 0xEC,
5470x00, 0x80, 0x00, 0xE8, 547 0x00, 0x80, 0x00, 0xE8,
548 548
5490x7F, 0xFF, 0x20, 0xEA, 549 0x7F, 0xFF, 0x20, 0xEA,
5500x00, 0x80, 0x00, 0xE8, 550 0x00, 0x80, 0x00, 0xE8,
551 551
5520x00, 0x80, 0x00, 0xE8, 552 0x00, 0x80, 0x00, 0xE8,
5530x00, 0x80, 0x00, 0xE8, 553 0x00, 0x80, 0x00, 0xE8,
554 554
555}; 555};
556 556
557static unsigned char warp_g200_tgza[] = { 557static unsigned char warp_g200_tgza[] = {
558 558
5590x00, 0x98, 0xA0, 0xE9, 559 0x00, 0x98, 0xA0, 0xE9,
5600x40, 0x40, 0xD8, 0xEC, 560 0x40, 0x40, 0xD8, 0xEC,
561 561
5620xFF, 0x80, 0xC0, 0xE9, 562 0xFF, 0x80, 0xC0, 0xE9,
5630x00, 0x80, 0x00, 0xE8, 563 0x00, 0x80, 0x00, 0xE8,
564 564
5650x1F, 0xD7, 0x18, 0xBD, 565 0x1F, 0xD7, 0x18, 0xBD,
5660x3F, 0xD7, 0x22, 0xBD, 566 0x3F, 0xD7, 0x22, 0xBD,
567 567
5680x81, 0x04, 568 0x81, 0x04,
5690x89, 0x04, 569 0x89, 0x04,
5700x01, 0x04, 570 0x01, 0x04,
5710x09, 0x04, 571 0x09, 0x04,
572 572
5730xC9, 0x41, 0xC0, 0xEC, 573 0xC9, 0x41, 0xC0, 0xEC,
5740x11, 0x04, 574 0x11, 0x04,
5750x00, 0xE0, 575 0x00, 0xE0,
576 576
5770x41, 0xCC, 0x41, 0xCD, 577 0x41, 0xCC, 0x41, 0xCD,
5780x49, 0xCC, 0x49, 0xCD, 578 0x49, 0xCC, 0x49, 0xCD,
579 579
5800xD1, 0x41, 0xC0, 0xEC, 580 0xD1, 0x41, 0xC0, 0xEC,
5810x51, 0xCC, 0x51, 0xCD, 581 0x51, 0xCC, 0x51, 0xCD,
582 582
5830x80, 0x04, 583 0x80, 0x04,
5840x10, 0x04, 584 0x10, 0x04,
5850x08, 0x04, 585 0x08, 0x04,
5860x00, 0xE0, 586 0x00, 0xE0,
587 587
5880x00, 0xCC, 0xC0, 0xCD, 588 0x00, 0xCC, 0xC0, 0xCD,
5890xD1, 0x49, 0xC0, 0xEC, 589 0xD1, 0x49, 0xC0, 0xEC,
590 590
5910x8A, 0x1F, 0x20, 0xE9, 591 0x8A, 0x1F, 0x20, 0xE9,
5920x8B, 0x3F, 0x20, 0xE9, 592 0x8B, 0x3F, 0x20, 0xE9,
593 593
5940x41, 0x3C, 0x41, 0xAD, 594 0x41, 0x3C, 0x41, 0xAD,
5950x49, 0x3C, 0x49, 0xAD, 595 0x49, 0x3C, 0x49, 0xAD,
596 596
5970x10, 0xCC, 0x10, 0xCD, 597 0x10, 0xCC, 0x10, 0xCD,
5980x08, 0xCC, 0x08, 0xCD, 598 0x08, 0xCC, 0x08, 0xCD,
599 599
6000xB9, 0x41, 0x49, 0xBB, 600 0xB9, 0x41, 0x49, 0xBB,
6010x1F, 0xF0, 0x41, 0xCD, 601 0x1F, 0xF0, 0x41, 0xCD,
602 602
6030x51, 0x3C, 0x51, 0xAD, 603 0x51, 0x3C, 0x51, 0xAD,
6040x00, 0x98, 0x80, 0xE9, 604 0x00, 0x98, 0x80, 0xE9,
605 605
6060x7D, 0x80, 0x07, 0xEA, 606 0x7D, 0x80, 0x07, 0xEA,
6070x24, 0x1F, 0x20, 0xE9, 607 0x24, 0x1F, 0x20, 0xE9,
608 608
6090x15, 0x41, 0x49, 0xBD, 609 0x15, 0x41, 0x49, 0xBD,
6100x1D, 0x41, 0x51, 0xBD, 610 0x1D, 0x41, 0x51, 0xBD,
611 611
6120x2E, 0x41, 0x2A, 0xB8, 612 0x2E, 0x41, 0x2A, 0xB8,
6130x34, 0x53, 0xA0, 0xE8, 613 0x34, 0x53, 0xA0, 0xE8,
614 614
6150x15, 0x30, 615 0x15, 0x30,
6160x1D, 0x30, 616 0x1D, 0x30,
6170x58, 0xE3, 617 0x58, 0xE3,
6180x00, 0xE0, 618 0x00, 0xE0,
619 619
6200xB5, 0x40, 0x48, 0xBD, 620 0xB5, 0x40, 0x48, 0xBD,
6210x3D, 0x40, 0x50, 0xBD, 621 0x3D, 0x40, 0x50, 0xBD,
622 622
6230x24, 0x43, 0xA0, 0xE8, 623 0x24, 0x43, 0xA0, 0xE8,
6240x2C, 0x4B, 0xA0, 0xE8, 624 0x2C, 0x4B, 0xA0, 0xE8,
625 625
6260x15, 0x72, 626 0x15, 0x72,
6270x09, 0xE3, 627 0x09, 0xE3,
6280x00, 0xE0, 628 0x00, 0xE0,
6290x1D, 0x72, 629 0x1D, 0x72,
630 630
6310x35, 0x30, 631 0x35, 0x30,
6320xB5, 0x30, 632 0xB5, 0x30,
6330xBD, 0x30, 633 0xBD, 0x30,
6340x3D, 0x30, 634 0x3D, 0x30,
635 635
6360x9C, 0x97, 0x57, 0x9F, 636 0x9C, 0x97, 0x57, 0x9F,
6370x00, 0x80, 0x00, 0xE8, 637 0x00, 0x80, 0x00, 0xE8,
638 638
6390x6C, 0x64, 0xC8, 0xEC, 639 0x6C, 0x64, 0xC8, 0xEC,
6400x98, 0xE1, 640 0x98, 0xE1,
6410xB5, 0x05, 641 0xB5, 0x05,
642 642
6430xBD, 0x05, 643 0xBD, 0x05,
6440x2E, 0x30, 644 0x2E, 0x30,
6450x32, 0xC0, 0xA0, 0xE8, 645 0x32, 0xC0, 0xA0, 0xE8,
646 646
6470x33, 0xC0, 0xA0, 0xE8, 647 0x33, 0xC0, 0xA0, 0xE8,
6480x74, 0x64, 0xC8, 0xEC, 648 0x74, 0x64, 0xC8, 0xEC,
649 649
6500x40, 0x3C, 0x40, 0xAD, 650 0x40, 0x3C, 0x40, 0xAD,
6510x32, 0x6A, 651 0x32, 0x6A,
6520x2A, 0x30, 652 0x2A, 0x30,
653 653
6540x20, 0x73, 654 0x20, 0x73,
6550x33, 0x6A, 655 0x33, 0x6A,
6560x00, 0xE0, 656 0x00, 0xE0,
6570x28, 0x73, 657 0x28, 0x73,
658 658
6590x1C, 0x72, 659 0x1C, 0x72,
6600x83, 0xE2, 660 0x83, 0xE2,
6610x6B, 0x80, 0x15, 0xEA, 661 0x6B, 0x80, 0x15, 0xEA,
662 662
6630xB8, 0x3D, 0x28, 0xDF, 663 0xB8, 0x3D, 0x28, 0xDF,
6640x30, 0x35, 0x20, 0xDF, 664 0x30, 0x35, 0x20, 0xDF,
665 665
6660x40, 0x30, 666 0x40, 0x30,
6670x00, 0xE0, 667 0x00, 0xE0,
6680xCC, 0xE2, 668 0xCC, 0xE2,
6690x64, 0x72, 669 0x64, 0x72,
670 670
6710x25, 0x42, 0x52, 0xBF, 671 0x25, 0x42, 0x52, 0xBF,
6720x2D, 0x42, 0x4A, 0xBF, 672 0x2D, 0x42, 0x4A, 0xBF,
673 673
6740x30, 0x2E, 0x30, 0xDF, 674 0x30, 0x2E, 0x30, 0xDF,
6750x38, 0x2E, 0x38, 0xDF, 675 0x38, 0x2E, 0x38, 0xDF,
676 676
6770x18, 0x1D, 0x45, 0xE9, 677 0x18, 0x1D, 0x45, 0xE9,
6780x1E, 0x15, 0x45, 0xE9, 678 0x1E, 0x15, 0x45, 0xE9,
679 679
6800x2B, 0x49, 0x51, 0xBD, 680 0x2B, 0x49, 0x51, 0xBD,
6810x00, 0xE0, 681 0x00, 0xE0,
6820x1F, 0x73, 682 0x1F, 0x73,
683 683
6840x38, 0x38, 0x40, 0xAF, 684 0x38, 0x38, 0x40, 0xAF,
6850x30, 0x30, 0x40, 0xAF, 685 0x30, 0x30, 0x40, 0xAF,
686 686
6870x24, 0x1F, 0x24, 0xDF, 687 0x24, 0x1F, 0x24, 0xDF,
6880x1D, 0x32, 0x20, 0xE9, 688 0x1D, 0x32, 0x20, 0xE9,
689 689
6900x2C, 0x1F, 0x2C, 0xDF, 690 0x2C, 0x1F, 0x2C, 0xDF,
6910x1A, 0x33, 0x20, 0xE9, 691 0x1A, 0x33, 0x20, 0xE9,
692 692
6930xB0, 0x10, 693 0xB0, 0x10,
6940x08, 0xE3, 694 0x08, 0xE3,
6950x40, 0x10, 695 0x40, 0x10,
6960xB8, 0x10, 696 0xB8, 0x10,
697 697
6980x26, 0xF0, 0x30, 0xCD, 698 0x26, 0xF0, 0x30, 0xCD,
6990x2F, 0xF0, 0x38, 0xCD, 699 0x2F, 0xF0, 0x38, 0xCD,
700 700
7010x2B, 0x80, 0x20, 0xE9, 701 0x2B, 0x80, 0x20, 0xE9,
7020x2A, 0x80, 0x20, 0xE9, 702 0x2A, 0x80, 0x20, 0xE9,
703 703
7040xA6, 0x20, 704 0xA6, 0x20,
7050x88, 0xE2, 705 0x88, 0xE2,
7060x00, 0xE0, 706 0x00, 0xE0,
7070xAF, 0x20, 707 0xAF, 0x20,
708 708
7090x28, 0x2A, 0x26, 0xAF, 709 0x28, 0x2A, 0x26, 0xAF,
7100x20, 0x2A, 0xC0, 0xAF, 710 0x20, 0x2A, 0xC0, 0xAF,
711 711
7120x34, 0x1F, 0x34, 0xDF, 712 0x34, 0x1F, 0x34, 0xDF,
7130x46, 0x24, 0x46, 0xDF, 713 0x46, 0x24, 0x46, 0xDF,
714 714
7150x28, 0x30, 0x80, 0xBF, 715 0x28, 0x30, 0x80, 0xBF,
7160x20, 0x38, 0x80, 0xBF, 716 0x20, 0x38, 0x80, 0xBF,
717 717
7180x47, 0x24, 0x47, 0xDF, 718 0x47, 0x24, 0x47, 0xDF,
7190x4E, 0x2C, 0x4E, 0xDF, 719 0x4E, 0x2C, 0x4E, 0xDF,
720 720
7210x4F, 0x2C, 0x4F, 0xDF, 721 0x4F, 0x2C, 0x4F, 0xDF,
7220x56, 0x34, 0x56, 0xDF, 722 0x56, 0x34, 0x56, 0xDF,
723 723
7240x28, 0x15, 0x28, 0xDF, 724 0x28, 0x15, 0x28, 0xDF,
7250x20, 0x1D, 0x20, 0xDF, 725 0x20, 0x1D, 0x20, 0xDF,
726 726
7270x57, 0x34, 0x57, 0xDF, 727 0x57, 0x34, 0x57, 0xDF,
7280x00, 0xE0, 728 0x00, 0xE0,
7290x1D, 0x05, 729 0x1D, 0x05,
730 730
7310x04, 0x80, 0x10, 0xEA, 731 0x04, 0x80, 0x10, 0xEA,
7320x89, 0xE2, 732 0x89, 0xE2,
7330x2B, 0x30, 733 0x2B, 0x30,
734 734
7350x3F, 0xC1, 0x1D, 0xBD, 735 0x3F, 0xC1, 0x1D, 0xBD,
7360x00, 0x80, 0x00, 0xE8, 736 0x00, 0x80, 0x00, 0xE8,
737 737
7380x00, 0x80, 0x00, 0xE8, 738 0x00, 0x80, 0x00, 0xE8,
7390x00, 0x80, 0x00, 0xE8, 739 0x00, 0x80, 0x00, 0xE8,
740 740
7410xA0, 0x68, 741 0xA0, 0x68,
7420xBF, 0x25, 742 0xBF, 0x25,
7430x00, 0x80, 0x00, 0xE8, 743 0x00, 0x80, 0x00, 0xE8,
744 744
7450x20, 0xC0, 0x20, 0xAF, 745 0x20, 0xC0, 0x20, 0xAF,
7460x28, 0x05, 746 0x28, 0x05,
7470x97, 0x74, 747 0x97, 0x74,
748 748
7490x00, 0xE0, 749 0x00, 0xE0,
7500x2A, 0x10, 750 0x2A, 0x10,
7510x16, 0xC0, 0x20, 0xE9, 751 0x16, 0xC0, 0x20, 0xE9,
752 752
7530x04, 0x80, 0x10, 0xEA, 753 0x04, 0x80, 0x10, 0xEA,
7540x8C, 0xE2, 754 0x8C, 0xE2,
7550x95, 0x05, 755 0x95, 0x05,
756 756
7570x28, 0xC1, 0x28, 0xAD, 757 0x28, 0xC1, 0x28, 0xAD,
7580x1F, 0xC1, 0x15, 0xBD, 758 0x1F, 0xC1, 0x15, 0xBD,
759 759
7600x00, 0x80, 0x00, 0xE8, 760 0x00, 0x80, 0x00, 0xE8,
7610x00, 0x80, 0x00, 0xE8, 761 0x00, 0x80, 0x00, 0xE8,
762 762
7630xA8, 0x67, 763 0xA8, 0x67,
7640x9F, 0x6B, 764 0x9F, 0x6B,
7650x00, 0x80, 0x00, 0xE8, 765 0x00, 0x80, 0x00, 0xE8,
766 766
7670x28, 0xC0, 0x28, 0xAD, 767 0x28, 0xC0, 0x28, 0xAD,
7680x1D, 0x25, 768 0x1D, 0x25,
7690x20, 0x05, 769 0x20, 0x05,
770 770
7710x28, 0x32, 0x80, 0xAD, 771 0x28, 0x32, 0x80, 0xAD,
7720x40, 0x2A, 0x40, 0xBD, 772 0x40, 0x2A, 0x40, 0xBD,
773 773
7740x1C, 0x80, 0x20, 0xE9, 774 0x1C, 0x80, 0x20, 0xE9,
7750x20, 0x33, 0x20, 0xAD, 775 0x20, 0x33, 0x20, 0xAD,
776 776
7770x20, 0x73, 777 0x20, 0x73,
7780x00, 0xE0, 778 0x00, 0xE0,
7790xB6, 0x49, 0x51, 0xBB, 779 0xB6, 0x49, 0x51, 0xBB,
780 780
7810x26, 0x2F, 0xB0, 0xE8, 781 0x26, 0x2F, 0xB0, 0xE8,
7820x19, 0x20, 0x20, 0xE9, 782 0x19, 0x20, 0x20, 0xE9,
783 783
7840x35, 0x20, 0x35, 0xDF, 784 0x35, 0x20, 0x35, 0xDF,
7850x3D, 0x20, 0x3D, 0xDF, 785 0x3D, 0x20, 0x3D, 0xDF,
786 786
7870x15, 0x20, 0x15, 0xDF, 787 0x15, 0x20, 0x15, 0xDF,
7880x1D, 0x20, 0x1D, 0xDF, 788 0x1D, 0x20, 0x1D, 0xDF,
789 789
7900x26, 0xD0, 0x26, 0xCD, 790 0x26, 0xD0, 0x26, 0xCD,
7910x29, 0x49, 0x2A, 0xB8, 791 0x29, 0x49, 0x2A, 0xB8,
792 792
7930x26, 0x40, 0x80, 0xBD, 793 0x26, 0x40, 0x80, 0xBD,
7940x3B, 0x48, 0x50, 0xBD, 794 0x3B, 0x48, 0x50, 0xBD,
795 795
7960x3E, 0x54, 0x57, 0x9F, 796 0x3E, 0x54, 0x57, 0x9F,
7970x00, 0xE0, 797 0x00, 0xE0,
7980x82, 0xE1, 798 0x82, 0xE1,
799 799
8000x1E, 0xAF, 0x59, 0x9F, 800 0x1E, 0xAF, 0x59, 0x9F,
8010x00, 0x80, 0x00, 0xE8, 801 0x00, 0x80, 0x00, 0xE8,
802 802
8030x26, 0x30, 803 0x26, 0x30,
8040x29, 0x30, 804 0x29, 0x30,
8050x48, 0x3C, 0x48, 0xAD, 805 0x48, 0x3C, 0x48, 0xAD,
806 806
8070x2B, 0x72, 807 0x2B, 0x72,
8080xC2, 0xE1, 808 0xC2, 0xE1,
8090x2C, 0xC0, 0x44, 0xC2, 809 0x2C, 0xC0, 0x44, 0xC2,
810 810
8110x05, 0x24, 0x34, 0xBF, 811 0x05, 0x24, 0x34, 0xBF,
8120x0D, 0x24, 0x2C, 0xBF, 812 0x0D, 0x24, 0x2C, 0xBF,
813 813
8140x2D, 0x46, 0x4E, 0xBF, 814 0x2D, 0x46, 0x4E, 0xBF,
8150x25, 0x46, 0x56, 0xBF, 815 0x25, 0x46, 0x56, 0xBF,
816 816
8170x20, 0x1D, 0x6F, 0x8F, 817 0x20, 0x1D, 0x6F, 0x8F,
8180x32, 0x3E, 0x5F, 0xE9, 818 0x32, 0x3E, 0x5F, 0xE9,
819 819
8200x3E, 0x50, 0x56, 0x9F, 820 0x3E, 0x50, 0x56, 0x9F,
8210x00, 0xE0, 821 0x00, 0xE0,
8220x3B, 0x30, 822 0x3B, 0x30,
823 823
8240x1E, 0x8F, 0x51, 0x9F, 824 0x1E, 0x8F, 0x51, 0x9F,
8250x33, 0x1E, 0x5F, 0xE9, 825 0x33, 0x1E, 0x5F, 0xE9,
826 826
8270x05, 0x44, 0x54, 0xB2, 827 0x05, 0x44, 0x54, 0xB2,
8280x0D, 0x44, 0x4C, 0xB2, 828 0x0D, 0x44, 0x4C, 0xB2,
829 829
8300x19, 0xC0, 0xB0, 0xE8, 830 0x19, 0xC0, 0xB0, 0xE8,
8310x34, 0xC0, 0x44, 0xC4, 831 0x34, 0xC0, 0x44, 0xC4,
832 832
8330x33, 0x73, 833 0x33, 0x73,
8340x00, 0xE0, 834 0x00, 0xE0,
8350x3E, 0x62, 0x57, 0x9F, 835 0x3E, 0x62, 0x57, 0x9F,
836 836
8370x1E, 0xAF, 0x59, 0x9F, 837 0x1E, 0xAF, 0x59, 0x9F,
8380x00, 0xE0, 838 0x00, 0xE0,
8390x0D, 0x20, 839 0x0D, 0x20,
840 840
8410x84, 0x3E, 0x58, 0xE9, 841 0x84, 0x3E, 0x58, 0xE9,
8420x28, 0x1D, 0x6F, 0x8F, 842 0x28, 0x1D, 0x6F, 0x8F,
843 843
8440x05, 0x20, 844 0x05, 0x20,
8450x00, 0xE0, 845 0x00, 0xE0,
8460x85, 0x1E, 0x58, 0xE9, 846 0x85, 0x1E, 0x58, 0xE9,
847 847
8480x9B, 0x3B, 0x33, 0xDF, 848 0x9B, 0x3B, 0x33, 0xDF,
8490x20, 0x20, 0x42, 0xAF, 849 0x20, 0x20, 0x42, 0xAF,
850 850
8510x30, 0x42, 0x56, 0x9F, 851 0x30, 0x42, 0x56, 0x9F,
8520x80, 0x3E, 0x57, 0xE9, 852 0x80, 0x3E, 0x57, 0xE9,
853 853
8540x3F, 0x8F, 0x51, 0x9F, 854 0x3F, 0x8F, 0x51, 0x9F,
8550x30, 0x80, 0x5F, 0xE9, 855 0x30, 0x80, 0x5F, 0xE9,
856 856
8570x28, 0x28, 0x24, 0xAF, 857 0x28, 0x28, 0x24, 0xAF,
8580x81, 0x1E, 0x57, 0xE9, 858 0x81, 0x1E, 0x57, 0xE9,
859 859
8600x05, 0x47, 0x57, 0xBF, 860 0x05, 0x47, 0x57, 0xBF,
8610x0D, 0x47, 0x4F, 0xBF, 861 0x0D, 0x47, 0x4F, 0xBF,
862 862
8630x88, 0x80, 0x58, 0xE9, 863 0x88, 0x80, 0x58, 0xE9,
8640x1B, 0x29, 0x1B, 0xDF, 864 0x1B, 0x29, 0x1B, 0xDF,
865 865
8660x30, 0x1D, 0x6F, 0x8F, 866 0x30, 0x1D, 0x6F, 0x8F,
8670x3A, 0x30, 0x4F, 0xE9, 867 0x3A, 0x30, 0x4F, 0xE9,
868 868
8690x1C, 0x30, 0x26, 0xDF, 869 0x1C, 0x30, 0x26, 0xDF,
8700x09, 0xE3, 870 0x09, 0xE3,
8710x3B, 0x05, 871 0x3B, 0x05,
872 872
8730x3E, 0x50, 0x56, 0x9F, 873 0x3E, 0x50, 0x56, 0x9F,
8740x3B, 0x3F, 0x4F, 0xE9, 874 0x3B, 0x3F, 0x4F, 0xE9,
875 875
8760x1E, 0x8F, 0x51, 0x9F, 876 0x1E, 0x8F, 0x51, 0x9F,
8770x00, 0xE0, 877 0x00, 0xE0,
8780xAC, 0x20, 878 0xAC, 0x20,
879 879
8800x2D, 0x44, 0x4C, 0xB4, 880 0x2D, 0x44, 0x4C, 0xB4,
8810x2C, 0x1C, 0xC0, 0xAF, 881 0x2C, 0x1C, 0xC0, 0xAF,
882 882
8830x25, 0x44, 0x54, 0xB4, 883 0x25, 0x44, 0x54, 0xB4,
8840x00, 0xE0, 884 0x00, 0xE0,
8850xC8, 0x30, 885 0xC8, 0x30,
886 886
8870x30, 0x46, 0x30, 0xAF, 887 0x30, 0x46, 0x30, 0xAF,
8880x1B, 0x1B, 0x48, 0xAF, 888 0x1B, 0x1B, 0x48, 0xAF,
889 889
8900x00, 0xE0, 890 0x00, 0xE0,
8910x25, 0x20, 891 0x25, 0x20,
8920x38, 0x2C, 0x4F, 0xE9, 892 0x38, 0x2C, 0x4F, 0xE9,
893 893
8940x86, 0x80, 0x57, 0xE9, 894 0x86, 0x80, 0x57, 0xE9,
8950x38, 0x1D, 0x6F, 0x8F, 895 0x38, 0x1D, 0x6F, 0x8F,
896 896
8970x28, 0x74, 897 0x28, 0x74,
8980x00, 0xE0, 898 0x00, 0xE0,
8990x0D, 0x44, 0x4C, 0xB0, 899 0x0D, 0x44, 0x4C, 0xB0,
900 900
9010x05, 0x44, 0x54, 0xB0, 901 0x05, 0x44, 0x54, 0xB0,
9020x2D, 0x20, 902 0x2D, 0x20,
9030x9B, 0x10, 903 0x9B, 0x10,
904 904
9050x82, 0x3E, 0x57, 0xE9, 905 0x82, 0x3E, 0x57, 0xE9,
9060x32, 0xF0, 0x1B, 0xCD, 906 0x32, 0xF0, 0x1B, 0xCD,
907 907
9080x1E, 0xBD, 0x59, 0x9F, 908 0x1E, 0xBD, 0x59, 0x9F,
9090x83, 0x1E, 0x57, 0xE9, 909 0x83, 0x1E, 0x57, 0xE9,
910 910
9110x38, 0x47, 0x38, 0xAF, 911 0x38, 0x47, 0x38, 0xAF,
9120x34, 0x20, 912 0x34, 0x20,
9130x2A, 0x30, 913 0x2A, 0x30,
914 914
9150x00, 0xE0, 915 0x00, 0xE0,
9160x0D, 0x20, 916 0x0D, 0x20,
9170x32, 0x20, 917 0x32, 0x20,
9180x05, 0x20, 918 0x05, 0x20,
919 919
9200x87, 0x80, 0x57, 0xE9, 920 0x87, 0x80, 0x57, 0xE9,
9210x1F, 0x54, 0x57, 0x9F, 921 0x1F, 0x54, 0x57, 0x9F,
922 922
9230x17, 0x42, 0x56, 0x9F, 923 0x17, 0x42, 0x56, 0x9F,
9240x00, 0xE0, 924 0x00, 0xE0,
9250x3B, 0x6A, 925 0x3B, 0x6A,
926 926
9270x3F, 0x8F, 0x51, 0x9F, 927 0x3F, 0x8F, 0x51, 0x9F,
9280x37, 0x1E, 0x4F, 0xE9, 928 0x37, 0x1E, 0x4F, 0xE9,
929 929
9300x37, 0x32, 0x2A, 0xAF, 930 0x37, 0x32, 0x2A, 0xAF,
9310x00, 0xE0, 931 0x00, 0xE0,
9320x32, 0x00, 932 0x32, 0x00,
933 933
9340x00, 0x80, 0x00, 0xE8, 934 0x00, 0x80, 0x00, 0xE8,
9350x27, 0xC0, 0x44, 0xC0, 935 0x27, 0xC0, 0x44, 0xC0,
936 936
9370x36, 0x1F, 0x4F, 0xE9, 937 0x36, 0x1F, 0x4F, 0xE9,
9380x1F, 0x1F, 0x26, 0xDF, 938 0x1F, 0x1F, 0x26, 0xDF,
939 939
9400x37, 0x1B, 0x37, 0xBF, 940 0x37, 0x1B, 0x37, 0xBF,
9410x17, 0x26, 0x17, 0xDF, 941 0x17, 0x26, 0x17, 0xDF,
942 942
9430x3E, 0x17, 0x4F, 0xE9, 943 0x3E, 0x17, 0x4F, 0xE9,
9440x3F, 0x3F, 0x4F, 0xE9, 944 0x3F, 0x3F, 0x4F, 0xE9,
945 945
9460x34, 0x1F, 0x34, 0xAF, 946 0x34, 0x1F, 0x34, 0xAF,
9470x2B, 0x05, 947 0x2B, 0x05,
9480xA7, 0x20, 948 0xA7, 0x20,
949 949
9500x33, 0x2B, 0x37, 0xDF, 950 0x33, 0x2B, 0x37, 0xDF,
9510x27, 0x17, 0xC0, 0xAF, 951 0x27, 0x17, 0xC0, 0xAF,
952 952
9530x34, 0x80, 0x4F, 0xE9, 953 0x34, 0x80, 0x4F, 0xE9,
9540x00, 0x80, 0x00, 0xE8, 954 0x00, 0x80, 0x00, 0xE8,
955 955
9560x2D, 0x44, 0x4C, 0xB6, 956 0x2D, 0x44, 0x4C, 0xB6,
9570x25, 0x44, 0x54, 0xB6, 957 0x25, 0x44, 0x54, 0xB6,
958 958
9590x03, 0x80, 0x2A, 0xEA, 959 0x03, 0x80, 0x2A, 0xEA,
9600x17, 0xC1, 0x2B, 0xBD, 960 0x17, 0xC1, 0x2B, 0xBD,
961 961
9620x2D, 0x20, 962 0x2D, 0x20,
9630x25, 0x20, 963 0x25, 0x20,
9640x07, 0xC0, 0x44, 0xC6, 964 0x07, 0xC0, 0x44, 0xC6,
965 965
9660xB3, 0x68, 966 0xB3, 0x68,
9670x97, 0x25, 967 0x97, 0x25,
9680x00, 0x80, 0x00, 0xE8, 968 0x00, 0x80, 0x00, 0xE8,
969 969
9700x33, 0xC0, 0x33, 0xAF, 970 0x33, 0xC0, 0x33, 0xAF,
9710x3C, 0x27, 0x4F, 0xE9, 971 0x3C, 0x27, 0x4F, 0xE9,
972 972
9730x1F, 0x62, 0x57, 0x9F, 973 0x1F, 0x62, 0x57, 0x9F,
9740x00, 0x80, 0x00, 0xE8, 974 0x00, 0x80, 0x00, 0xE8,
975 975
9760x3F, 0x3D, 0x5D, 0x9F, 976 0x3F, 0x3D, 0x5D, 0x9F,
9770x00, 0xE0, 977 0x00, 0xE0,
9780x07, 0x20, 978 0x07, 0x20,
979 979
9800x00, 0x80, 0x00, 0xE8, 980 0x00, 0x80, 0x00, 0xE8,
9810x28, 0x19, 0x60, 0xEC, 981 0x28, 0x19, 0x60, 0xEC,
982 982
9830xB3, 0x05, 983 0xB3, 0x05,
9840x00, 0xE0, 984 0x00, 0xE0,
9850x00, 0x80, 0x00, 0xE8, 985 0x00, 0x80, 0x00, 0xE8,
986 986
9870x23, 0x3B, 0x33, 0xAD, 987 0x23, 0x3B, 0x33, 0xAD,
9880x00, 0x80, 0x00, 0xE8, 988 0x00, 0x80, 0x00, 0xE8,
989 989
9900x1F, 0x26, 0x1F, 0xDF, 990 0x1F, 0x26, 0x1F, 0xDF,
9910x9D, 0x1F, 0x4F, 0xE9, 991 0x9D, 0x1F, 0x4F, 0xE9,
992 992
9930x00, 0x80, 0x00, 0xE8, 993 0x00, 0x80, 0x00, 0xE8,
9940x00, 0x80, 0x00, 0xE8, 994 0x00, 0x80, 0x00, 0xE8,
995 995
9960x00, 0x80, 0x00, 0xE8, 996 0x00, 0x80, 0x00, 0xE8,
9970x9E, 0x3F, 0x4F, 0xE9, 997 0x9E, 0x3F, 0x4F, 0xE9,
998 998
9990x07, 0x07, 0x1F, 0xAF, 999 0x07, 0x07, 0x1F, 0xAF,
10000x00, 0x80, 0x00, 0xE8, 1000 0x00, 0x80, 0x00, 0xE8,
1001 1001
10020x00, 0x80, 0x00, 0xE8, 1002 0x00, 0x80, 0x00, 0xE8,
10030x00, 0x80, 0x00, 0xE8, 1003 0x00, 0x80, 0x00, 0xE8,
1004 1004
10050x9C, 0x80, 0x4F, 0xE9, 1005 0x9C, 0x80, 0x4F, 0xE9,
10060x00, 0x80, 0x00, 0xE8, 1006 0x00, 0x80, 0x00, 0xE8,
1007 1007
10080x00, 0x80, 0x00, 0xE8, 1008 0x00, 0x80, 0x00, 0xE8,
10090x57, 0x39, 0x20, 0xE9, 1009 0x57, 0x39, 0x20, 0xE9,
1010 1010
10110x16, 0x28, 0x20, 0xE9, 1011 0x16, 0x28, 0x20, 0xE9,
10120x1D, 0x3B, 0x20, 0xE9, 1012 0x1D, 0x3B, 0x20, 0xE9,
1013 1013
10140x1E, 0x2B, 0x20, 0xE9, 1014 0x1E, 0x2B, 0x20, 0xE9,
10150x2B, 0x32, 0x20, 0xE9, 1015 0x2B, 0x32, 0x20, 0xE9,
1016 1016
10170x1C, 0x23, 0x20, 0xE9, 1017 0x1C, 0x23, 0x20, 0xE9,
10180x57, 0x36, 0x20, 0xE9, 1018 0x57, 0x36, 0x20, 0xE9,
1019 1019
10200x00, 0x80, 0xA0, 0xE9, 1020 0x00, 0x80, 0xA0, 0xE9,
10210x40, 0x40, 0xD8, 0xEC, 1021 0x40, 0x40, 0xD8, 0xEC,
1022 1022
10230xFF, 0x80, 0xC0, 0xE9, 1023 0xFF, 0x80, 0xC0, 0xE9,
10240x90, 0xE2, 1024 0x90, 0xE2,
10250x00, 0xE0, 1025 0x00, 0xE0,
1026 1026
10270x7A, 0xFF, 0x20, 0xEA, 1027 0x7A, 0xFF, 0x20, 0xEA,
10280x19, 0xC8, 0xC1, 0xCD, 1028 0x19, 0xC8, 0xC1, 0xCD,
1029 1029
10300x1F, 0xD7, 0x18, 0xBD, 1030 0x1F, 0xD7, 0x18, 0xBD,
10310x3F, 0xD7, 0x22, 0xBD, 1031 0x3F, 0xD7, 0x22, 0xBD,
1032 1032
10330x9F, 0x41, 0x49, 0xBD, 1033 0x9F, 0x41, 0x49, 0xBD,
10340x00, 0x80, 0x00, 0xE8, 1034 0x00, 0x80, 0x00, 0xE8,
1035 1035
10360x25, 0x41, 0x49, 0xBD, 1036 0x25, 0x41, 0x49, 0xBD,
10370x2D, 0x41, 0x51, 0xBD, 1037 0x2D, 0x41, 0x51, 0xBD,
1038 1038
10390x0D, 0x80, 0x07, 0xEA, 1039 0x0D, 0x80, 0x07, 0xEA,
10400x00, 0x80, 0x00, 0xE8, 1040 0x00, 0x80, 0x00, 0xE8,
1041 1041
10420x35, 0x40, 0x48, 0xBD, 1042 0x35, 0x40, 0x48, 0xBD,
10430x3D, 0x40, 0x50, 0xBD, 1043 0x3D, 0x40, 0x50, 0xBD,
1044 1044
10450x00, 0x80, 0x00, 0xE8, 1045 0x00, 0x80, 0x00, 0xE8,
10460x25, 0x30, 1046 0x25, 0x30,
10470x2D, 0x30, 1047 0x2D, 0x30,
1048 1048
10490x35, 0x30, 1049 0x35, 0x30,
10500xB5, 0x30, 1050 0xB5, 0x30,
10510xBD, 0x30, 1051 0xBD, 0x30,
10520x3D, 0x30, 1052 0x3D, 0x30,
1053 1053
10540x9C, 0xA7, 0x5B, 0x9F, 1054 0x9C, 0xA7, 0x5B, 0x9F,
10550x00, 0x80, 0x00, 0xE8, 1055 0x00, 0x80, 0x00, 0xE8,
1056 1056
10570x00, 0x80, 0x00, 0xE8, 1057 0x00, 0x80, 0x00, 0xE8,
10580x00, 0x80, 0x00, 0xE8, 1058 0x00, 0x80, 0x00, 0xE8,
1059 1059
10600x00, 0x80, 0x00, 0xE8, 1060 0x00, 0x80, 0x00, 0xE8,
10610x00, 0x80, 0x00, 0xE8, 1061 0x00, 0x80, 0x00, 0xE8,
1062 1062
10630x00, 0x80, 0x00, 0xE8, 1063 0x00, 0x80, 0x00, 0xE8,
10640x00, 0x80, 0x00, 0xE8, 1064 0x00, 0x80, 0x00, 0xE8,
1065 1065
10660x00, 0x80, 0x00, 0xE8, 1066 0x00, 0x80, 0x00, 0xE8,
10670x00, 0x80, 0x00, 0xE8, 1067 0x00, 0x80, 0x00, 0xE8,
1068 1068
10690x79, 0xFF, 0x0A, 0xEA, 1069 0x79, 0xFF, 0x0A, 0xEA,
10700x00, 0x80, 0x00, 0xE8, 1070 0x00, 0x80, 0x00, 0xE8,
1071 1071
10720xC9, 0x41, 0xC8, 0xEC, 1072 0xC9, 0x41, 0xC8, 0xEC,
10730x42, 0xE1, 1073 0x42, 0xE1,
10740x00, 0xE0, 1074 0x00, 0xE0,
1075 1075
10760x77, 0xFF, 0x20, 0xEA, 1076 0x77, 0xFF, 0x20, 0xEA,
10770x00, 0x80, 0x00, 0xE8, 1077 0x00, 0x80, 0x00, 0xE8,
1078 1078
10790x00, 0x80, 0x00, 0xE8, 1079 0x00, 0x80, 0x00, 0xE8,
10800x00, 0x80, 0x00, 0xE8, 1080 0x00, 0x80, 0x00, 0xE8,
1081 1081
10820xC8, 0x40, 0xC0, 0xEC, 1082 0xC8, 0x40, 0xC0, 0xEC,
10830x00, 0x80, 0x00, 0xE8, 1083 0x00, 0x80, 0x00, 0xE8,
1084 1084
10850x74, 0xFF, 0x20, 0xEA, 1085 0x74, 0xFF, 0x20, 0xEA,
10860x00, 0x80, 0x00, 0xE8, 1086 0x00, 0x80, 0x00, 0xE8,
1087 1087
10880x00, 0x80, 0x00, 0xE8, 1088 0x00, 0x80, 0x00, 0xE8,
10890x00, 0x80, 0x00, 0xE8, 1089 0x00, 0x80, 0x00, 0xE8,
1090 1090
1091}; 1091};
1092 1092
1093static unsigned char warp_g200_tgzaf[] = { 1093static unsigned char warp_g200_tgzaf[] = {
1094 1094
10950x00, 0x80, 0x00, 0xE8, 1095 0x00, 0x80, 0x00, 0xE8,
10960x00, 0x80, 0x00, 0xE8, 1096 0x00, 0x80, 0x00, 0xE8,
1097 1097
10980x00, 0x80, 0x00, 0xE8, 1098 0x00, 0x80, 0x00, 0xE8,
10990x00, 0x80, 0x00, 0xE8, 1099 0x00, 0x80, 0x00, 0xE8,
1100 1100
11010x00, 0x80, 0x00, 0xE8, 1101 0x00, 0x80, 0x00, 0xE8,
11020x00, 0x80, 0x00, 0xE8, 1102 0x00, 0x80, 0x00, 0xE8,
1103 1103
11040x00, 0x80, 0x00, 0xE8, 1104 0x00, 0x80, 0x00, 0xE8,
11050x00, 0x80, 0x00, 0xE8, 1105 0x00, 0x80, 0x00, 0xE8,
1106 1106
11070x00, 0x80, 0x00, 0xE8, 1107 0x00, 0x80, 0x00, 0xE8,
11080x00, 0x80, 0x00, 0xE8, 1108 0x00, 0x80, 0x00, 0xE8,
1109 1109
11100x00, 0x80, 0x00, 0xE8, 1110 0x00, 0x80, 0x00, 0xE8,
11110x00, 0x80, 0x00, 0xE8, 1111 0x00, 0x80, 0x00, 0xE8,
1112 1112
11130x00, 0x80, 0x00, 0xE8, 1113 0x00, 0x80, 0x00, 0xE8,
11140x00, 0x80, 0x00, 0xE8, 1114 0x00, 0x80, 0x00, 0xE8,
1115 1115
11160x00, 0x80, 0x00, 0xE8, 1116 0x00, 0x80, 0x00, 0xE8,
11170x00, 0x80, 0x00, 0xE8, 1117 0x00, 0x80, 0x00, 0xE8,
1118 1118
11190x00, 0x80, 0x00, 0xE8, 1119 0x00, 0x80, 0x00, 0xE8,
11200x00, 0x80, 0x00, 0xE8, 1120 0x00, 0x80, 0x00, 0xE8,
1121 1121
11220x00, 0x80, 0x00, 0xE8, 1122 0x00, 0x80, 0x00, 0xE8,
11230x00, 0x80, 0x00, 0xE8, 1123 0x00, 0x80, 0x00, 0xE8,
1124 1124
11250x00, 0x98, 0xA0, 0xE9, 1125 0x00, 0x98, 0xA0, 0xE9,
11260x40, 0x40, 0xD8, 0xEC, 1126 0x40, 0x40, 0xD8, 0xEC,
1127 1127
11280xFF, 0x80, 0xC0, 0xE9, 1128 0xFF, 0x80, 0xC0, 0xE9,
11290x00, 0x80, 0x00, 0xE8, 1129 0x00, 0x80, 0x00, 0xE8,
1130 1130
11310x1F, 0xD7, 0x18, 0xBD, 1131 0x1F, 0xD7, 0x18, 0xBD,
11320x3F, 0xD7, 0x22, 0xBD, 1132 0x3F, 0xD7, 0x22, 0xBD,
1133 1133
11340x81, 0x04, 1134 0x81, 0x04,
11350x89, 0x04, 1135 0x89, 0x04,
11360x01, 0x04, 1136 0x01, 0x04,
11370x09, 0x04, 1137 0x09, 0x04,
1138 1138
11390xC9, 0x41, 0xC0, 0xEC, 1139 0xC9, 0x41, 0xC0, 0xEC,
11400x11, 0x04, 1140 0x11, 0x04,
11410x00, 0xE0, 1141 0x00, 0xE0,
1142 1142
11430x41, 0xCC, 0x41, 0xCD, 1143 0x41, 0xCC, 0x41, 0xCD,
11440x49, 0xCC, 0x49, 0xCD, 1144 0x49, 0xCC, 0x49, 0xCD,
1145 1145
11460xD1, 0x41, 0xC0, 0xEC, 1146 0xD1, 0x41, 0xC0, 0xEC,
11470x51, 0xCC, 0x51, 0xCD, 1147 0x51, 0xCC, 0x51, 0xCD,
1148 1148
11490x80, 0x04, 1149 0x80, 0x04,
11500x10, 0x04, 1150 0x10, 0x04,
11510x08, 0x04, 1151 0x08, 0x04,
11520x00, 0xE0, 1152 0x00, 0xE0,
1153 1153
11540x00, 0xCC, 0xC0, 0xCD, 1154 0x00, 0xCC, 0xC0, 0xCD,
11550xD1, 0x49, 0xC0, 0xEC, 1155 0xD1, 0x49, 0xC0, 0xEC,
1156 1156
11570x8A, 0x1F, 0x20, 0xE9, 1157 0x8A, 0x1F, 0x20, 0xE9,
11580x8B, 0x3F, 0x20, 0xE9, 1158 0x8B, 0x3F, 0x20, 0xE9,
1159 1159
11600x41, 0x3C, 0x41, 0xAD, 1160 0x41, 0x3C, 0x41, 0xAD,
11610x49, 0x3C, 0x49, 0xAD, 1161 0x49, 0x3C, 0x49, 0xAD,
1162 1162
11630x10, 0xCC, 0x10, 0xCD, 1163 0x10, 0xCC, 0x10, 0xCD,
11640x08, 0xCC, 0x08, 0xCD, 1164 0x08, 0xCC, 0x08, 0xCD,
1165 1165
11660xB9, 0x41, 0x49, 0xBB, 1166 0xB9, 0x41, 0x49, 0xBB,
11670x1F, 0xF0, 0x41, 0xCD, 1167 0x1F, 0xF0, 0x41, 0xCD,
1168 1168
11690x51, 0x3C, 0x51, 0xAD, 1169 0x51, 0x3C, 0x51, 0xAD,
11700x00, 0x98, 0x80, 0xE9, 1170 0x00, 0x98, 0x80, 0xE9,
1171 1171
11720x83, 0x80, 0x07, 0xEA, 1172 0x83, 0x80, 0x07, 0xEA,
11730x24, 0x1F, 0x20, 0xE9, 1173 0x24, 0x1F, 0x20, 0xE9,
1174 1174
11750x21, 0x45, 0x80, 0xE8, 1175 0x21, 0x45, 0x80, 0xE8,
11760x1A, 0x4D, 0x80, 0xE8, 1176 0x1A, 0x4D, 0x80, 0xE8,
1177 1177
11780x31, 0x55, 0x80, 0xE8, 1178 0x31, 0x55, 0x80, 0xE8,
11790x00, 0x80, 0x00, 0xE8, 1179 0x00, 0x80, 0x00, 0xE8,
1180 1180
11810x15, 0x41, 0x49, 0xBD, 1181 0x15, 0x41, 0x49, 0xBD,
11820x1D, 0x41, 0x51, 0xBD, 1182 0x1D, 0x41, 0x51, 0xBD,
1183 1183
11840x2E, 0x41, 0x2A, 0xB8, 1184 0x2E, 0x41, 0x2A, 0xB8,
11850x34, 0x53, 0xA0, 0xE8, 1185 0x34, 0x53, 0xA0, 0xE8,
1186 1186
11870x15, 0x30, 1187 0x15, 0x30,
11880x1D, 0x30, 1188 0x1D, 0x30,
11890x58, 0xE3, 1189 0x58, 0xE3,
11900x00, 0xE0, 1190 0x00, 0xE0,
1191 1191
11920xB5, 0x40, 0x48, 0xBD, 1192 0xB5, 0x40, 0x48, 0xBD,
11930x3D, 0x40, 0x50, 0xBD, 1193 0x3D, 0x40, 0x50, 0xBD,
1194 1194
11950x24, 0x43, 0xA0, 0xE8, 1195 0x24, 0x43, 0xA0, 0xE8,
11960x2C, 0x4B, 0xA0, 0xE8, 1196 0x2C, 0x4B, 0xA0, 0xE8,
1197 1197
11980x15, 0x72, 1198 0x15, 0x72,
11990x09, 0xE3, 1199 0x09, 0xE3,
12000x00, 0xE0, 1200 0x00, 0xE0,
12010x1D, 0x72, 1201 0x1D, 0x72,
1202 1202
12030x35, 0x30, 1203 0x35, 0x30,
12040xB5, 0x30, 1204 0xB5, 0x30,
12050xBD, 0x30, 1205 0xBD, 0x30,
12060x3D, 0x30, 1206 0x3D, 0x30,
1207 1207
12080x9C, 0x97, 0x57, 0x9F, 1208 0x9C, 0x97, 0x57, 0x9F,
12090x00, 0x80, 0x00, 0xE8, 1209 0x00, 0x80, 0x00, 0xE8,
1210 1210
12110x6C, 0x64, 0xC8, 0xEC, 1211 0x6C, 0x64, 0xC8, 0xEC,
12120x98, 0xE1, 1212 0x98, 0xE1,
12130xB5, 0x05, 1213 0xB5, 0x05,
1214 1214
12150xBD, 0x05, 1215 0xBD, 0x05,
12160x2E, 0x30, 1216 0x2E, 0x30,
12170x32, 0xC0, 0xA0, 0xE8, 1217 0x32, 0xC0, 0xA0, 0xE8,
1218 1218
12190x33, 0xC0, 0xA0, 0xE8, 1219 0x33, 0xC0, 0xA0, 0xE8,
12200x74, 0x64, 0xC8, 0xEC, 1220 0x74, 0x64, 0xC8, 0xEC,
1221 1221
12220x40, 0x3C, 0x40, 0xAD, 1222 0x40, 0x3C, 0x40, 0xAD,
12230x32, 0x6A, 1223 0x32, 0x6A,
12240x2A, 0x30, 1224 0x2A, 0x30,
1225 1225
12260x20, 0x73, 1226 0x20, 0x73,
12270x33, 0x6A, 1227 0x33, 0x6A,
12280x00, 0xE0, 1228 0x00, 0xE0,
12290x28, 0x73, 1229 0x28, 0x73,
1230 1230
12310x1C, 0x72, 1231 0x1C, 0x72,
12320x83, 0xE2, 1232 0x83, 0xE2,
12330x6F, 0x80, 0x15, 0xEA, 1233 0x6F, 0x80, 0x15, 0xEA,
1234 1234
12350xB8, 0x3D, 0x28, 0xDF, 1235 0xB8, 0x3D, 0x28, 0xDF,
12360x30, 0x35, 0x20, 0xDF, 1236 0x30, 0x35, 0x20, 0xDF,
1237 1237
12380x40, 0x30, 1238 0x40, 0x30,
12390x00, 0xE0, 1239 0x00, 0xE0,
12400xCC, 0xE2, 1240 0xCC, 0xE2,
12410x64, 0x72, 1241 0x64, 0x72,
1242 1242
12430x25, 0x42, 0x52, 0xBF, 1243 0x25, 0x42, 0x52, 0xBF,
12440x2D, 0x42, 0x4A, 0xBF, 1244 0x2D, 0x42, 0x4A, 0xBF,
1245 1245
12460x30, 0x2E, 0x30, 0xDF, 1246 0x30, 0x2E, 0x30, 0xDF,
12470x38, 0x2E, 0x38, 0xDF, 1247 0x38, 0x2E, 0x38, 0xDF,
1248 1248
12490x18, 0x1D, 0x45, 0xE9, 1249 0x18, 0x1D, 0x45, 0xE9,
12500x1E, 0x15, 0x45, 0xE9, 1250 0x1E, 0x15, 0x45, 0xE9,
1251 1251
12520x2B, 0x49, 0x51, 0xBD, 1252 0x2B, 0x49, 0x51, 0xBD,
12530x00, 0xE0, 1253 0x00, 0xE0,
12540x1F, 0x73, 1254 0x1F, 0x73,
1255 1255
12560x38, 0x38, 0x40, 0xAF, 1256 0x38, 0x38, 0x40, 0xAF,
12570x30, 0x30, 0x40, 0xAF, 1257 0x30, 0x30, 0x40, 0xAF,
1258 1258
12590x24, 0x1F, 0x24, 0xDF, 1259 0x24, 0x1F, 0x24, 0xDF,
12600x1D, 0x32, 0x20, 0xE9, 1260 0x1D, 0x32, 0x20, 0xE9,
1261 1261
12620x2C, 0x1F, 0x2C, 0xDF, 1262 0x2C, 0x1F, 0x2C, 0xDF,
12630x1A, 0x33, 0x20, 0xE9, 1263 0x1A, 0x33, 0x20, 0xE9,
1264 1264
12650xB0, 0x10, 1265 0xB0, 0x10,
12660x08, 0xE3, 1266 0x08, 0xE3,
12670x40, 0x10, 1267 0x40, 0x10,
12680xB8, 0x10, 1268 0xB8, 0x10,
1269 1269
12700x26, 0xF0, 0x30, 0xCD, 1270 0x26, 0xF0, 0x30, 0xCD,
12710x2F, 0xF0, 0x38, 0xCD, 1271 0x2F, 0xF0, 0x38, 0xCD,
1272 1272
12730x2B, 0x80, 0x20, 0xE9, 1273 0x2B, 0x80, 0x20, 0xE9,
12740x2A, 0x80, 0x20, 0xE9, 1274 0x2A, 0x80, 0x20, 0xE9,
1275 1275
12760xA6, 0x20, 1276 0xA6, 0x20,
12770x88, 0xE2, 1277 0x88, 0xE2,
12780x00, 0xE0, 1278 0x00, 0xE0,
12790xAF, 0x20, 1279 0xAF, 0x20,
1280 1280
12810x28, 0x2A, 0x26, 0xAF, 1281 0x28, 0x2A, 0x26, 0xAF,
12820x20, 0x2A, 0xC0, 0xAF, 1282 0x20, 0x2A, 0xC0, 0xAF,
1283 1283
12840x34, 0x1F, 0x34, 0xDF, 1284 0x34, 0x1F, 0x34, 0xDF,
12850x46, 0x24, 0x46, 0xDF, 1285 0x46, 0x24, 0x46, 0xDF,
1286 1286
12870x28, 0x30, 0x80, 0xBF, 1287 0x28, 0x30, 0x80, 0xBF,
12880x20, 0x38, 0x80, 0xBF, 1288 0x20, 0x38, 0x80, 0xBF,
1289 1289
12900x47, 0x24, 0x47, 0xDF, 1290 0x47, 0x24, 0x47, 0xDF,
12910x4E, 0x2C, 0x4E, 0xDF, 1291 0x4E, 0x2C, 0x4E, 0xDF,
1292 1292
12930x4F, 0x2C, 0x4F, 0xDF, 1293 0x4F, 0x2C, 0x4F, 0xDF,
12940x56, 0x34, 0x56, 0xDF, 1294 0x56, 0x34, 0x56, 0xDF,
1295 1295
12960x28, 0x15, 0x28, 0xDF, 1296 0x28, 0x15, 0x28, 0xDF,
12970x20, 0x1D, 0x20, 0xDF, 1297 0x20, 0x1D, 0x20, 0xDF,
1298 1298
12990x57, 0x34, 0x57, 0xDF, 1299 0x57, 0x34, 0x57, 0xDF,
13000x00, 0xE0, 1300 0x00, 0xE0,
13010x1D, 0x05, 1301 0x1D, 0x05,
1302 1302
13030x04, 0x80, 0x10, 0xEA, 1303 0x04, 0x80, 0x10, 0xEA,
13040x89, 0xE2, 1304 0x89, 0xE2,
13050x2B, 0x30, 1305 0x2B, 0x30,
1306 1306
13070x3F, 0xC1, 0x1D, 0xBD, 1307 0x3F, 0xC1, 0x1D, 0xBD,
13080x00, 0x80, 0x00, 0xE8, 1308 0x00, 0x80, 0x00, 0xE8,
1309 1309
13100x00, 0x80, 0x00, 0xE8, 1310 0x00, 0x80, 0x00, 0xE8,
13110x00, 0x80, 0x00, 0xE8, 1311 0x00, 0x80, 0x00, 0xE8,
1312 1312
13130xA0, 0x68, 1313 0xA0, 0x68,
13140xBF, 0x25, 1314 0xBF, 0x25,
13150x00, 0x80, 0x00, 0xE8, 1315 0x00, 0x80, 0x00, 0xE8,
1316 1316
13170x20, 0xC0, 0x20, 0xAF, 1317 0x20, 0xC0, 0x20, 0xAF,
13180x28, 0x05, 1318 0x28, 0x05,
13190x97, 0x74, 1319 0x97, 0x74,
1320 1320
13210x00, 0xE0, 1321 0x00, 0xE0,
13220x2A, 0x10, 1322 0x2A, 0x10,
13230x16, 0xC0, 0x20, 0xE9, 1323 0x16, 0xC0, 0x20, 0xE9,
1324 1324
13250x04, 0x80, 0x10, 0xEA, 1325 0x04, 0x80, 0x10, 0xEA,
13260x8C, 0xE2, 1326 0x8C, 0xE2,
13270x95, 0x05, 1327 0x95, 0x05,
1328 1328
13290x28, 0xC1, 0x28, 0xAD, 1329 0x28, 0xC1, 0x28, 0xAD,
13300x1F, 0xC1, 0x15, 0xBD, 1330 0x1F, 0xC1, 0x15, 0xBD,
1331 1331
13320x00, 0x80, 0x00, 0xE8, 1332 0x00, 0x80, 0x00, 0xE8,
13330x00, 0x80, 0x00, 0xE8, 1333 0x00, 0x80, 0x00, 0xE8,
1334 1334
13350xA8, 0x67, 1335 0xA8, 0x67,
13360x9F, 0x6B, 1336 0x9F, 0x6B,
13370x00, 0x80, 0x00, 0xE8, 1337 0x00, 0x80, 0x00, 0xE8,
1338 1338
13390x28, 0xC0, 0x28, 0xAD, 1339 0x28, 0xC0, 0x28, 0xAD,
13400x1D, 0x25, 1340 0x1D, 0x25,
13410x20, 0x05, 1341 0x20, 0x05,
1342 1342
13430x28, 0x32, 0x80, 0xAD, 1343 0x28, 0x32, 0x80, 0xAD,
13440x40, 0x2A, 0x40, 0xBD, 1344 0x40, 0x2A, 0x40, 0xBD,
1345 1345
13460x1C, 0x80, 0x20, 0xE9, 1346 0x1C, 0x80, 0x20, 0xE9,
13470x20, 0x33, 0x20, 0xAD, 1347 0x20, 0x33, 0x20, 0xAD,
1348 1348
13490x20, 0x73, 1349 0x20, 0x73,
13500x00, 0xE0, 1350 0x00, 0xE0,
13510xB6, 0x49, 0x51, 0xBB, 1351 0xB6, 0x49, 0x51, 0xBB,
1352 1352
13530x26, 0x2F, 0xB0, 0xE8, 1353 0x26, 0x2F, 0xB0, 0xE8,
13540x19, 0x20, 0x20, 0xE9, 1354 0x19, 0x20, 0x20, 0xE9,
1355 1355
13560x35, 0x20, 0x35, 0xDF, 1356 0x35, 0x20, 0x35, 0xDF,
13570x3D, 0x20, 0x3D, 0xDF, 1357 0x3D, 0x20, 0x3D, 0xDF,
1358 1358
13590x15, 0x20, 0x15, 0xDF, 1359 0x15, 0x20, 0x15, 0xDF,
13600x1D, 0x20, 0x1D, 0xDF, 1360 0x1D, 0x20, 0x1D, 0xDF,
1361 1361
13620x26, 0xD0, 0x26, 0xCD, 1362 0x26, 0xD0, 0x26, 0xCD,
13630x29, 0x49, 0x2A, 0xB8, 1363 0x29, 0x49, 0x2A, 0xB8,
1364 1364
13650x26, 0x40, 0x80, 0xBD, 1365 0x26, 0x40, 0x80, 0xBD,
13660x3B, 0x48, 0x50, 0xBD, 1366 0x3B, 0x48, 0x50, 0xBD,
1367 1367
13680x3E, 0x54, 0x57, 0x9F, 1368 0x3E, 0x54, 0x57, 0x9F,
13690x00, 0xE0, 1369 0x00, 0xE0,
13700x82, 0xE1, 1370 0x82, 0xE1,
1371 1371
13720x1E, 0xAF, 0x59, 0x9F, 1372 0x1E, 0xAF, 0x59, 0x9F,
13730x00, 0x80, 0x00, 0xE8, 1373 0x00, 0x80, 0x00, 0xE8,
1374 1374
13750x26, 0x30, 1375 0x26, 0x30,
13760x29, 0x30, 1376 0x29, 0x30,
13770x48, 0x3C, 0x48, 0xAD, 1377 0x48, 0x3C, 0x48, 0xAD,
1378 1378
13790x2B, 0x72, 1379 0x2B, 0x72,
13800xC2, 0xE1, 1380 0xC2, 0xE1,
13810x2C, 0xC0, 0x44, 0xC2, 1381 0x2C, 0xC0, 0x44, 0xC2,
1382 1382
13830x05, 0x24, 0x34, 0xBF, 1383 0x05, 0x24, 0x34, 0xBF,
13840x0D, 0x24, 0x2C, 0xBF, 1384 0x0D, 0x24, 0x2C, 0xBF,
1385 1385
13860x2D, 0x46, 0x4E, 0xBF, 1386 0x2D, 0x46, 0x4E, 0xBF,
13870x25, 0x46, 0x56, 0xBF, 1387 0x25, 0x46, 0x56, 0xBF,
1388 1388
13890x20, 0x1D, 0x6F, 0x8F, 1389 0x20, 0x1D, 0x6F, 0x8F,
13900x32, 0x3E, 0x5F, 0xE9, 1390 0x32, 0x3E, 0x5F, 0xE9,
1391 1391
13920x3E, 0x50, 0x56, 0x9F, 1392 0x3E, 0x50, 0x56, 0x9F,
13930x00, 0xE0, 1393 0x00, 0xE0,
13940x3B, 0x30, 1394 0x3B, 0x30,
1395 1395
13960x1E, 0x8F, 0x51, 0x9F, 1396 0x1E, 0x8F, 0x51, 0x9F,
13970x33, 0x1E, 0x5F, 0xE9, 1397 0x33, 0x1E, 0x5F, 0xE9,
1398 1398
13990x05, 0x44, 0x54, 0xB2, 1399 0x05, 0x44, 0x54, 0xB2,
14000x0D, 0x44, 0x4C, 0xB2, 1400 0x0D, 0x44, 0x4C, 0xB2,
1401 1401
14020x19, 0xC0, 0xB0, 0xE8, 1402 0x19, 0xC0, 0xB0, 0xE8,
14030x34, 0xC0, 0x44, 0xC4, 1403 0x34, 0xC0, 0x44, 0xC4,
1404 1404
14050x33, 0x73, 1405 0x33, 0x73,
14060x00, 0xE0, 1406 0x00, 0xE0,
14070x3E, 0x62, 0x57, 0x9F, 1407 0x3E, 0x62, 0x57, 0x9F,
1408 1408
14090x1E, 0xAF, 0x59, 0x9F, 1409 0x1E, 0xAF, 0x59, 0x9F,
14100x00, 0xE0, 1410 0x00, 0xE0,
14110x0D, 0x20, 1411 0x0D, 0x20,
1412 1412
14130x84, 0x3E, 0x58, 0xE9, 1413 0x84, 0x3E, 0x58, 0xE9,
14140x28, 0x1D, 0x6F, 0x8F, 1414 0x28, 0x1D, 0x6F, 0x8F,
1415 1415
14160x05, 0x20, 1416 0x05, 0x20,
14170x00, 0xE0, 1417 0x00, 0xE0,
14180x85, 0x1E, 0x58, 0xE9, 1418 0x85, 0x1E, 0x58, 0xE9,
1419 1419
14200x9B, 0x3B, 0x33, 0xDF, 1420 0x9B, 0x3B, 0x33, 0xDF,
14210x20, 0x20, 0x42, 0xAF, 1421 0x20, 0x20, 0x42, 0xAF,
1422 1422
14230x30, 0x42, 0x56, 0x9F, 1423 0x30, 0x42, 0x56, 0x9F,
14240x80, 0x3E, 0x57, 0xE9, 1424 0x80, 0x3E, 0x57, 0xE9,
1425 1425
14260x3F, 0x8F, 0x51, 0x9F, 1426 0x3F, 0x8F, 0x51, 0x9F,
14270x30, 0x80, 0x5F, 0xE9, 1427 0x30, 0x80, 0x5F, 0xE9,
1428 1428
14290x28, 0x28, 0x24, 0xAF, 1429 0x28, 0x28, 0x24, 0xAF,
14300x81, 0x1E, 0x57, 0xE9, 1430 0x81, 0x1E, 0x57, 0xE9,
1431 1431
14320x05, 0x47, 0x57, 0xBF, 1432 0x05, 0x47, 0x57, 0xBF,
14330x0D, 0x47, 0x4F, 0xBF, 1433 0x0D, 0x47, 0x4F, 0xBF,
1434 1434
14350x88, 0x80, 0x58, 0xE9, 1435 0x88, 0x80, 0x58, 0xE9,
14360x1B, 0x29, 0x1B, 0xDF, 1436 0x1B, 0x29, 0x1B, 0xDF,
1437 1437
14380x30, 0x1D, 0x6F, 0x8F, 1438 0x30, 0x1D, 0x6F, 0x8F,
14390x3A, 0x30, 0x4F, 0xE9, 1439 0x3A, 0x30, 0x4F, 0xE9,
1440 1440
14410x1C, 0x30, 0x26, 0xDF, 1441 0x1C, 0x30, 0x26, 0xDF,
14420x09, 0xE3, 1442 0x09, 0xE3,
14430x3B, 0x05, 1443 0x3B, 0x05,
1444 1444
14450x3E, 0x50, 0x56, 0x9F, 1445 0x3E, 0x50, 0x56, 0x9F,
14460x3B, 0x3F, 0x4F, 0xE9, 1446 0x3B, 0x3F, 0x4F, 0xE9,
1447 1447
14480x1E, 0x8F, 0x51, 0x9F, 1448 0x1E, 0x8F, 0x51, 0x9F,
14490x00, 0xE0, 1449 0x00, 0xE0,
14500xAC, 0x20, 1450 0xAC, 0x20,
1451 1451
14520x2D, 0x44, 0x4C, 0xB4, 1452 0x2D, 0x44, 0x4C, 0xB4,
14530x2C, 0x1C, 0xC0, 0xAF, 1453 0x2C, 0x1C, 0xC0, 0xAF,
1454 1454
14550x25, 0x44, 0x54, 0xB4, 1455 0x25, 0x44, 0x54, 0xB4,
14560x00, 0xE0, 1456 0x00, 0xE0,
14570xC8, 0x30, 1457 0xC8, 0x30,
1458 1458
14590x30, 0x46, 0x30, 0xAF, 1459 0x30, 0x46, 0x30, 0xAF,
14600x1B, 0x1B, 0x48, 0xAF, 1460 0x1B, 0x1B, 0x48, 0xAF,
1461 1461
14620x00, 0xE0, 1462 0x00, 0xE0,
14630x25, 0x20, 1463 0x25, 0x20,
14640x38, 0x2C, 0x4F, 0xE9, 1464 0x38, 0x2C, 0x4F, 0xE9,
1465 1465
14660x86, 0x80, 0x57, 0xE9, 1466 0x86, 0x80, 0x57, 0xE9,
14670x38, 0x1D, 0x6F, 0x8F, 1467 0x38, 0x1D, 0x6F, 0x8F,
1468 1468
14690x28, 0x74, 1469 0x28, 0x74,
14700x00, 0xE0, 1470 0x00, 0xE0,
14710x0D, 0x44, 0x4C, 0xB0, 1471 0x0D, 0x44, 0x4C, 0xB0,
1472 1472
14730x05, 0x44, 0x54, 0xB0, 1473 0x05, 0x44, 0x54, 0xB0,
14740x2D, 0x20, 1474 0x2D, 0x20,
14750x9B, 0x10, 1475 0x9B, 0x10,
1476 1476
14770x82, 0x3E, 0x57, 0xE9, 1477 0x82, 0x3E, 0x57, 0xE9,
14780x32, 0xF0, 0x1B, 0xCD, 1478 0x32, 0xF0, 0x1B, 0xCD,
1479 1479
14800x1E, 0xBD, 0x59, 0x9F, 1480 0x1E, 0xBD, 0x59, 0x9F,
14810x83, 0x1E, 0x57, 0xE9, 1481 0x83, 0x1E, 0x57, 0xE9,
1482 1482
14830x38, 0x47, 0x38, 0xAF, 1483 0x38, 0x47, 0x38, 0xAF,
14840x34, 0x20, 1484 0x34, 0x20,
14850x2A, 0x30, 1485 0x2A, 0x30,
1486 1486
14870x00, 0xE0, 1487 0x00, 0xE0,
14880x0D, 0x20, 1488 0x0D, 0x20,
14890x32, 0x20, 1489 0x32, 0x20,
14900x05, 0x20, 1490 0x05, 0x20,
1491 1491
14920x87, 0x80, 0x57, 0xE9, 1492 0x87, 0x80, 0x57, 0xE9,
14930x1F, 0x54, 0x57, 0x9F, 1493 0x1F, 0x54, 0x57, 0x9F,
1494 1494
14950x17, 0x42, 0x56, 0x9F, 1495 0x17, 0x42, 0x56, 0x9F,
14960x00, 0xE0, 1496 0x00, 0xE0,
14970x3B, 0x6A, 1497 0x3B, 0x6A,
1498 1498
14990x3F, 0x8F, 0x51, 0x9F, 1499 0x3F, 0x8F, 0x51, 0x9F,
15000x37, 0x1E, 0x4F, 0xE9, 1500 0x37, 0x1E, 0x4F, 0xE9,
1501 1501
15020x37, 0x32, 0x2A, 0xAF, 1502 0x37, 0x32, 0x2A, 0xAF,
15030x00, 0xE0, 1503 0x00, 0xE0,
15040x32, 0x00, 1504 0x32, 0x00,
1505 1505
15060x00, 0x80, 0x00, 0xE8, 1506 0x00, 0x80, 0x00, 0xE8,
15070x27, 0xC0, 0x44, 0xC0, 1507 0x27, 0xC0, 0x44, 0xC0,
1508 1508
15090x36, 0x1F, 0x4F, 0xE9, 1509 0x36, 0x1F, 0x4F, 0xE9,
15100x1F, 0x1F, 0x26, 0xDF, 1510 0x1F, 0x1F, 0x26, 0xDF,
1511 1511
15120x37, 0x1B, 0x37, 0xBF, 1512 0x37, 0x1B, 0x37, 0xBF,
15130x17, 0x26, 0x17, 0xDF, 1513 0x17, 0x26, 0x17, 0xDF,
1514 1514
15150x3E, 0x17, 0x4F, 0xE9, 1515 0x3E, 0x17, 0x4F, 0xE9,
15160x3F, 0x3F, 0x4F, 0xE9, 1516 0x3F, 0x3F, 0x4F, 0xE9,
1517 1517
15180x34, 0x1F, 0x34, 0xAF, 1518 0x34, 0x1F, 0x34, 0xAF,
15190x2B, 0x05, 1519 0x2B, 0x05,
15200xA7, 0x20, 1520 0xA7, 0x20,
1521 1521
15220x33, 0x2B, 0x37, 0xDF, 1522 0x33, 0x2B, 0x37, 0xDF,
15230x27, 0x17, 0xC0, 0xAF, 1523 0x27, 0x17, 0xC0, 0xAF,
1524 1524
15250x34, 0x80, 0x4F, 0xE9, 1525 0x34, 0x80, 0x4F, 0xE9,
15260x00, 0x80, 0x00, 0xE8, 1526 0x00, 0x80, 0x00, 0xE8,
1527 1527
15280x0D, 0x21, 0x1A, 0xB6, 1528 0x0D, 0x21, 0x1A, 0xB6,
15290x05, 0x21, 0x31, 0xB6, 1529 0x05, 0x21, 0x31, 0xB6,
1530 1530
15310x2D, 0x44, 0x4C, 0xB6, 1531 0x2D, 0x44, 0x4C, 0xB6,
15320x25, 0x44, 0x54, 0xB6, 1532 0x25, 0x44, 0x54, 0xB6,
1533 1533
15340x03, 0x80, 0x2A, 0xEA, 1534 0x03, 0x80, 0x2A, 0xEA,
15350x17, 0xC1, 0x2B, 0xBD, 1535 0x17, 0xC1, 0x2B, 0xBD,
1536 1536
15370x0D, 0x20, 1537 0x0D, 0x20,
15380x05, 0x20, 1538 0x05, 0x20,
15390x2F, 0xC0, 0x21, 0xC6, 1539 0x2F, 0xC0, 0x21, 0xC6,
1540 1540
15410xB3, 0x68, 1541 0xB3, 0x68,
15420x97, 0x25, 1542 0x97, 0x25,
15430x00, 0x80, 0x00, 0xE8, 1543 0x00, 0x80, 0x00, 0xE8,
1544 1544
15450x33, 0xC0, 0x33, 0xAF, 1545 0x33, 0xC0, 0x33, 0xAF,
15460x3C, 0x27, 0x4F, 0xE9, 1546 0x3C, 0x27, 0x4F, 0xE9,
1547 1547
15480x00, 0xE0, 1548 0x00, 0xE0,
15490x25, 0x20, 1549 0x25, 0x20,
15500x07, 0xC0, 0x44, 0xC6, 1550 0x07, 0xC0, 0x44, 0xC6,
1551 1551
15520x17, 0x50, 0x56, 0x9F, 1552 0x17, 0x50, 0x56, 0x9F,
15530x00, 0xE0, 1553 0x00, 0xE0,
15540x2D, 0x20, 1554 0x2D, 0x20,
1555 1555
15560x37, 0x0F, 0x5C, 0x9F, 1556 0x37, 0x0F, 0x5C, 0x9F,
15570x00, 0xE0, 1557 0x00, 0xE0,
15580x2F, 0x20, 1558 0x2F, 0x20,
1559 1559
15600x1F, 0x62, 0x57, 0x9F, 1560 0x1F, 0x62, 0x57, 0x9F,
15610x00, 0xE0, 1561 0x00, 0xE0,
15620x07, 0x20, 1562 0x07, 0x20,
1563 1563
15640x3F, 0x3D, 0x5D, 0x9F, 1564 0x3F, 0x3D, 0x5D, 0x9F,
15650x00, 0x80, 0x00, 0xE8, 1565 0x00, 0x80, 0x00, 0xE8,
1566 1566
15670x00, 0x80, 0x00, 0xE8, 1567 0x00, 0x80, 0x00, 0xE8,
15680x28, 0x19, 0x60, 0xEC, 1568 0x28, 0x19, 0x60, 0xEC,
1569 1569
15700xB3, 0x05, 1570 0xB3, 0x05,
15710x00, 0xE0, 1571 0x00, 0xE0,
15720x17, 0x26, 0x17, 0xDF, 1572 0x17, 0x26, 0x17, 0xDF,
1573 1573
15740x23, 0x3B, 0x33, 0xAD, 1574 0x23, 0x3B, 0x33, 0xAD,
15750x35, 0x17, 0x4F, 0xE9, 1575 0x35, 0x17, 0x4F, 0xE9,
1576 1576
15770x1F, 0x26, 0x1F, 0xDF, 1577 0x1F, 0x26, 0x1F, 0xDF,
15780x9D, 0x1F, 0x4F, 0xE9, 1578 0x9D, 0x1F, 0x4F, 0xE9,
1579 1579
15800x9E, 0x3F, 0x4F, 0xE9, 1580 0x9E, 0x3F, 0x4F, 0xE9,
15810x39, 0x37, 0x4F, 0xE9, 1581 0x39, 0x37, 0x4F, 0xE9,
1582 1582
15830x2F, 0x2F, 0x17, 0xAF, 1583 0x2F, 0x2F, 0x17, 0xAF,
15840x00, 0x80, 0x00, 0xE8, 1584 0x00, 0x80, 0x00, 0xE8,
1585 1585
15860x07, 0x07, 0x1F, 0xAF, 1586 0x07, 0x07, 0x1F, 0xAF,
15870x00, 0x80, 0x00, 0xE8, 1587 0x00, 0x80, 0x00, 0xE8,
1588 1588
15890x31, 0x80, 0x4F, 0xE9, 1589 0x31, 0x80, 0x4F, 0xE9,
15900x00, 0x80, 0x00, 0xE8, 1590 0x00, 0x80, 0x00, 0xE8,
1591 1591
15920x9C, 0x80, 0x4F, 0xE9, 1592 0x9C, 0x80, 0x4F, 0xE9,
15930x00, 0x80, 0x00, 0xE8, 1593 0x00, 0x80, 0x00, 0xE8,
1594 1594
15950x00, 0x80, 0x00, 0xE8, 1595 0x00, 0x80, 0x00, 0xE8,
15960x57, 0x39, 0x20, 0xE9, 1596 0x57, 0x39, 0x20, 0xE9,
1597 1597
15980x16, 0x28, 0x20, 0xE9, 1598 0x16, 0x28, 0x20, 0xE9,
15990x1D, 0x3B, 0x20, 0xE9, 1599 0x1D, 0x3B, 0x20, 0xE9,
1600 1600
16010x1E, 0x2B, 0x20, 0xE9, 1601 0x1E, 0x2B, 0x20, 0xE9,
16020x2B, 0x32, 0x20, 0xE9, 1602 0x2B, 0x32, 0x20, 0xE9,
1603 1603
16040x1C, 0x23, 0x20, 0xE9, 1604 0x1C, 0x23, 0x20, 0xE9,
16050x57, 0x36, 0x20, 0xE9, 1605 0x57, 0x36, 0x20, 0xE9,
1606 1606
16070x00, 0x80, 0xA0, 0xE9, 1607 0x00, 0x80, 0xA0, 0xE9,
16080x40, 0x40, 0xD8, 0xEC, 1608 0x40, 0x40, 0xD8, 0xEC,
1609 1609
16100xFF, 0x80, 0xC0, 0xE9, 1610 0xFF, 0x80, 0xC0, 0xE9,
16110x90, 0xE2, 1611 0x90, 0xE2,
16120x00, 0xE0, 1612 0x00, 0xE0,
1613 1613
16140x74, 0xFF, 0x20, 0xEA, 1614 0x74, 0xFF, 0x20, 0xEA,
16150x19, 0xC8, 0xC1, 0xCD, 1615 0x19, 0xC8, 0xC1, 0xCD,
1616 1616
16170x1F, 0xD7, 0x18, 0xBD, 1617 0x1F, 0xD7, 0x18, 0xBD,
16180x3F, 0xD7, 0x22, 0xBD, 1618 0x3F, 0xD7, 0x22, 0xBD,
1619 1619
16200x9F, 0x41, 0x49, 0xBD, 1620 0x9F, 0x41, 0x49, 0xBD,
16210x00, 0x80, 0x00, 0xE8, 1621 0x00, 0x80, 0x00, 0xE8,
1622 1622
16230x25, 0x41, 0x49, 0xBD, 1623 0x25, 0x41, 0x49, 0xBD,
16240x2D, 0x41, 0x51, 0xBD, 1624 0x2D, 0x41, 0x51, 0xBD,
1625 1625
16260x0D, 0x80, 0x07, 0xEA, 1626 0x0D, 0x80, 0x07, 0xEA,
16270x00, 0x80, 0x00, 0xE8, 1627 0x00, 0x80, 0x00, 0xE8,
1628 1628
16290x35, 0x40, 0x48, 0xBD, 1629 0x35, 0x40, 0x48, 0xBD,
16300x3D, 0x40, 0x50, 0xBD, 1630 0x3D, 0x40, 0x50, 0xBD,
1631 1631
16320x00, 0x80, 0x00, 0xE8, 1632 0x00, 0x80, 0x00, 0xE8,
16330x25, 0x30, 1633 0x25, 0x30,
16340x2D, 0x30, 1634 0x2D, 0x30,
1635 1635
16360x35, 0x30, 1636 0x35, 0x30,
16370xB5, 0x30, 1637 0xB5, 0x30,
16380xBD, 0x30, 1638 0xBD, 0x30,
16390x3D, 0x30, 1639 0x3D, 0x30,
1640 1640
16410x9C, 0xA7, 0x5B, 0x9F, 1641 0x9C, 0xA7, 0x5B, 0x9F,
16420x00, 0x80, 0x00, 0xE8, 1642 0x00, 0x80, 0x00, 0xE8,
1643 1643
16440x00, 0x80, 0x00, 0xE8, 1644 0x00, 0x80, 0x00, 0xE8,
16450x00, 0x80, 0x00, 0xE8, 1645 0x00, 0x80, 0x00, 0xE8,
1646 1646
16470x00, 0x80, 0x00, 0xE8, 1647 0x00, 0x80, 0x00, 0xE8,
16480x00, 0x80, 0x00, 0xE8, 1648 0x00, 0x80, 0x00, 0xE8,
1649 1649
16500x00, 0x80, 0x00, 0xE8, 1650 0x00, 0x80, 0x00, 0xE8,
16510x00, 0x80, 0x00, 0xE8, 1651 0x00, 0x80, 0x00, 0xE8,
1652 1652
16530x00, 0x80, 0x00, 0xE8, 1653 0x00, 0x80, 0x00, 0xE8,
16540x00, 0x80, 0x00, 0xE8, 1654 0x00, 0x80, 0x00, 0xE8,
1655 1655
16560x73, 0xFF, 0x0A, 0xEA, 1656 0x73, 0xFF, 0x0A, 0xEA,
16570x00, 0x80, 0x00, 0xE8, 1657 0x00, 0x80, 0x00, 0xE8,
1658 1658
16590xC9, 0x41, 0xC8, 0xEC, 1659 0xC9, 0x41, 0xC8, 0xEC,
16600x42, 0xE1, 1660 0x42, 0xE1,
16610x00, 0xE0, 1661 0x00, 0xE0,
1662 1662
16630x71, 0xFF, 0x20, 0xEA, 1663 0x71, 0xFF, 0x20, 0xEA,
16640x00, 0x80, 0x00, 0xE8, 1664 0x00, 0x80, 0x00, 0xE8,
1665 1665
16660x00, 0x80, 0x00, 0xE8, 1666 0x00, 0x80, 0x00, 0xE8,
16670x00, 0x80, 0x00, 0xE8, 1667 0x00, 0x80, 0x00, 0xE8,
1668 1668
16690xC8, 0x40, 0xC0, 0xEC, 1669 0xC8, 0x40, 0xC0, 0xEC,
16700x00, 0x80, 0x00, 0xE8, 1670 0x00, 0x80, 0x00, 0xE8,
1671 1671
16720x6E, 0xFF, 0x20, 0xEA, 1672 0x6E, 0xFF, 0x20, 0xEA,
16730x00, 0x80, 0x00, 0xE8, 1673 0x00, 0x80, 0x00, 0xE8,
1674 1674
16750x00, 0x80, 0x00, 0xE8, 1675 0x00, 0x80, 0x00, 0xE8,
16760x00, 0x80, 0x00, 0xE8, 1676 0x00, 0x80, 0x00, 0xE8,
1677 1677
1678}; 1678};
1679 1679
1680static unsigned char warp_g200_tgzf[] = { 1680static unsigned char warp_g200_tgzf[] = {
1681 1681
16820x00, 0x80, 0x00, 0xE8, 1682 0x00, 0x80, 0x00, 0xE8,
16830x00, 0x80, 0x00, 0xE8, 1683 0x00, 0x80, 0x00, 0xE8,
1684 1684
16850x00, 0x80, 0x00, 0xE8, 1685 0x00, 0x80, 0x00, 0xE8,
16860x00, 0x80, 0x00, 0xE8, 1686 0x00, 0x80, 0x00, 0xE8,
1687 1687
16880x00, 0x80, 0x00, 0xE8, 1688 0x00, 0x80, 0x00, 0xE8,
16890x00, 0x80, 0x00, 0xE8, 1689 0x00, 0x80, 0x00, 0xE8,
1690 1690
16910x00, 0x80, 0x00, 0xE8, 1691 0x00, 0x80, 0x00, 0xE8,
16920x00, 0x80, 0x00, 0xE8, 1692 0x00, 0x80, 0x00, 0xE8,
1693 1693
16940x00, 0x80, 0x00, 0xE8, 1694 0x00, 0x80, 0x00, 0xE8,
16950x00, 0x80, 0x00, 0xE8, 1695 0x00, 0x80, 0x00, 0xE8,
1696 1696
16970x00, 0x80, 0x00, 0xE8, 1697 0x00, 0x80, 0x00, 0xE8,
16980x00, 0x80, 0x00, 0xE8, 1698 0x00, 0x80, 0x00, 0xE8,
1699 1699
17000x00, 0x80, 0x00, 0xE8, 1700 0x00, 0x80, 0x00, 0xE8,
17010x00, 0x80, 0x00, 0xE8, 1701 0x00, 0x80, 0x00, 0xE8,
1702 1702
17030x00, 0x80, 0x00, 0xE8, 1703 0x00, 0x80, 0x00, 0xE8,
17040x00, 0x80, 0x00, 0xE8, 1704 0x00, 0x80, 0x00, 0xE8,
1705 1705
17060x00, 0x80, 0x00, 0xE8, 1706 0x00, 0x80, 0x00, 0xE8,
17070x00, 0x80, 0x00, 0xE8, 1707 0x00, 0x80, 0x00, 0xE8,
1708 1708
17090x00, 0x80, 0x00, 0xE8, 1709 0x00, 0x80, 0x00, 0xE8,
17100x00, 0x80, 0x00, 0xE8, 1710 0x00, 0x80, 0x00, 0xE8,
1711 1711
17120x00, 0x98, 0xA0, 0xE9, 1712 0x00, 0x98, 0xA0, 0xE9,
17130x40, 0x40, 0xD8, 0xEC, 1713 0x40, 0x40, 0xD8, 0xEC,
1714 1714
17150xFF, 0x80, 0xC0, 0xE9, 1715 0xFF, 0x80, 0xC0, 0xE9,
17160x00, 0x80, 0x00, 0xE8, 1716 0x00, 0x80, 0x00, 0xE8,
1717 1717
17180x1F, 0xD7, 0x18, 0xBD, 1718 0x1F, 0xD7, 0x18, 0xBD,
17190x3F, 0xD7, 0x22, 0xBD, 1719 0x3F, 0xD7, 0x22, 0xBD,
1720 1720
17210x81, 0x04, 1721 0x81, 0x04,
17220x89, 0x04, 1722 0x89, 0x04,
17230x01, 0x04, 1723 0x01, 0x04,
17240x09, 0x04, 1724 0x09, 0x04,
1725 1725
17260xC9, 0x41, 0xC0, 0xEC, 1726 0xC9, 0x41, 0xC0, 0xEC,
17270x11, 0x04, 1727 0x11, 0x04,
17280x00, 0xE0, 1728 0x00, 0xE0,
1729 1729
17300x41, 0xCC, 0x41, 0xCD, 1730 0x41, 0xCC, 0x41, 0xCD,
17310x49, 0xCC, 0x49, 0xCD, 1731 0x49, 0xCC, 0x49, 0xCD,
1732 1732
17330xD1, 0x41, 0xC0, 0xEC, 1733 0xD1, 0x41, 0xC0, 0xEC,
17340x51, 0xCC, 0x51, 0xCD, 1734 0x51, 0xCC, 0x51, 0xCD,
1735 1735
17360x80, 0x04, 1736 0x80, 0x04,
17370x10, 0x04, 1737 0x10, 0x04,
17380x08, 0x04, 1738 0x08, 0x04,
17390x00, 0xE0, 1739 0x00, 0xE0,
1740 1740
17410x00, 0xCC, 0xC0, 0xCD, 1741 0x00, 0xCC, 0xC0, 0xCD,
17420xD1, 0x49, 0xC0, 0xEC, 1742 0xD1, 0x49, 0xC0, 0xEC,
1743 1743
17440x8A, 0x1F, 0x20, 0xE9, 1744 0x8A, 0x1F, 0x20, 0xE9,
17450x8B, 0x3F, 0x20, 0xE9, 1745 0x8B, 0x3F, 0x20, 0xE9,
1746 1746
17470x41, 0x3C, 0x41, 0xAD, 1747 0x41, 0x3C, 0x41, 0xAD,
17480x49, 0x3C, 0x49, 0xAD, 1748 0x49, 0x3C, 0x49, 0xAD,
1749 1749
17500x10, 0xCC, 0x10, 0xCD, 1750 0x10, 0xCC, 0x10, 0xCD,
17510x08, 0xCC, 0x08, 0xCD, 1751 0x08, 0xCC, 0x08, 0xCD,
1752 1752
17530xB9, 0x41, 0x49, 0xBB, 1753 0xB9, 0x41, 0x49, 0xBB,
17540x1F, 0xF0, 0x41, 0xCD, 1754 0x1F, 0xF0, 0x41, 0xCD,
1755 1755
17560x51, 0x3C, 0x51, 0xAD, 1756 0x51, 0x3C, 0x51, 0xAD,
17570x00, 0x98, 0x80, 0xE9, 1757 0x00, 0x98, 0x80, 0xE9,
1758 1758
17590x7F, 0x80, 0x07, 0xEA, 1759 0x7F, 0x80, 0x07, 0xEA,
17600x24, 0x1F, 0x20, 0xE9, 1760 0x24, 0x1F, 0x20, 0xE9,
1761 1761
17620x21, 0x45, 0x80, 0xE8, 1762 0x21, 0x45, 0x80, 0xE8,
17630x1A, 0x4D, 0x80, 0xE8, 1763 0x1A, 0x4D, 0x80, 0xE8,
1764 1764
17650x31, 0x55, 0x80, 0xE8, 1765 0x31, 0x55, 0x80, 0xE8,
17660x00, 0x80, 0x00, 0xE8, 1766 0x00, 0x80, 0x00, 0xE8,
1767 1767
17680x15, 0x41, 0x49, 0xBD, 1768 0x15, 0x41, 0x49, 0xBD,
17690x1D, 0x41, 0x51, 0xBD, 1769 0x1D, 0x41, 0x51, 0xBD,
1770 1770
17710x2E, 0x41, 0x2A, 0xB8, 1771 0x2E, 0x41, 0x2A, 0xB8,
17720x34, 0x53, 0xA0, 0xE8, 1772 0x34, 0x53, 0xA0, 0xE8,
1773 1773
17740x15, 0x30, 1774 0x15, 0x30,
17750x1D, 0x30, 1775 0x1D, 0x30,
17760x58, 0xE3, 1776 0x58, 0xE3,
17770x00, 0xE0, 1777 0x00, 0xE0,
1778 1778
17790xB5, 0x40, 0x48, 0xBD, 1779 0xB5, 0x40, 0x48, 0xBD,
17800x3D, 0x40, 0x50, 0xBD, 1780 0x3D, 0x40, 0x50, 0xBD,
1781 1781
17820x24, 0x43, 0xA0, 0xE8, 1782 0x24, 0x43, 0xA0, 0xE8,
17830x2C, 0x4B, 0xA0, 0xE8, 1783 0x2C, 0x4B, 0xA0, 0xE8,
1784 1784
17850x15, 0x72, 1785 0x15, 0x72,
17860x09, 0xE3, 1786 0x09, 0xE3,
17870x00, 0xE0, 1787 0x00, 0xE0,
17880x1D, 0x72, 1788 0x1D, 0x72,
1789 1789
17900x35, 0x30, 1790 0x35, 0x30,
17910xB5, 0x30, 1791 0xB5, 0x30,
17920xBD, 0x30, 1792 0xBD, 0x30,
17930x3D, 0x30, 1793 0x3D, 0x30,
1794 1794
17950x9C, 0x97, 0x57, 0x9F, 1795 0x9C, 0x97, 0x57, 0x9F,
17960x00, 0x80, 0x00, 0xE8, 1796 0x00, 0x80, 0x00, 0xE8,
1797 1797
17980x6C, 0x64, 0xC8, 0xEC, 1798 0x6C, 0x64, 0xC8, 0xEC,
17990x98, 0xE1, 1799 0x98, 0xE1,
18000xB5, 0x05, 1800 0xB5, 0x05,
1801 1801
18020xBD, 0x05, 1802 0xBD, 0x05,
18030x2E, 0x30, 1803 0x2E, 0x30,
18040x32, 0xC0, 0xA0, 0xE8, 1804 0x32, 0xC0, 0xA0, 0xE8,
1805 1805
18060x33, 0xC0, 0xA0, 0xE8, 1806 0x33, 0xC0, 0xA0, 0xE8,
18070x74, 0x64, 0xC8, 0xEC, 1807 0x74, 0x64, 0xC8, 0xEC,
1808 1808
18090x40, 0x3C, 0x40, 0xAD, 1809 0x40, 0x3C, 0x40, 0xAD,
18100x32, 0x6A, 1810 0x32, 0x6A,
18110x2A, 0x30, 1811 0x2A, 0x30,
1812 1812
18130x20, 0x73, 1813 0x20, 0x73,
18140x33, 0x6A, 1814 0x33, 0x6A,
18150x00, 0xE0, 1815 0x00, 0xE0,
18160x28, 0x73, 1816 0x28, 0x73,
1817 1817
18180x1C, 0x72, 1818 0x1C, 0x72,
18190x83, 0xE2, 1819 0x83, 0xE2,
18200x6B, 0x80, 0x15, 0xEA, 1820 0x6B, 0x80, 0x15, 0xEA,
1821 1821
18220xB8, 0x3D, 0x28, 0xDF, 1822 0xB8, 0x3D, 0x28, 0xDF,
18230x30, 0x35, 0x20, 0xDF, 1823 0x30, 0x35, 0x20, 0xDF,
1824 1824
18250x40, 0x30, 1825 0x40, 0x30,
18260x00, 0xE0, 1826 0x00, 0xE0,
18270xCC, 0xE2, 1827 0xCC, 0xE2,
18280x64, 0x72, 1828 0x64, 0x72,
1829 1829
18300x25, 0x42, 0x52, 0xBF, 1830 0x25, 0x42, 0x52, 0xBF,
18310x2D, 0x42, 0x4A, 0xBF, 1831 0x2D, 0x42, 0x4A, 0xBF,
1832 1832
18330x30, 0x2E, 0x30, 0xDF, 1833 0x30, 0x2E, 0x30, 0xDF,
18340x38, 0x2E, 0x38, 0xDF, 1834 0x38, 0x2E, 0x38, 0xDF,
1835 1835
18360x18, 0x1D, 0x45, 0xE9, 1836 0x18, 0x1D, 0x45, 0xE9,
18370x1E, 0x15, 0x45, 0xE9, 1837 0x1E, 0x15, 0x45, 0xE9,
1838 1838
18390x2B, 0x49, 0x51, 0xBD, 1839 0x2B, 0x49, 0x51, 0xBD,
18400x00, 0xE0, 1840 0x00, 0xE0,
18410x1F, 0x73, 1841 0x1F, 0x73,
1842 1842
18430x38, 0x38, 0x40, 0xAF, 1843 0x38, 0x38, 0x40, 0xAF,
18440x30, 0x30, 0x40, 0xAF, 1844 0x30, 0x30, 0x40, 0xAF,
1845 1845
18460x24, 0x1F, 0x24, 0xDF, 1846 0x24, 0x1F, 0x24, 0xDF,
18470x1D, 0x32, 0x20, 0xE9, 1847 0x1D, 0x32, 0x20, 0xE9,
1848 1848
18490x2C, 0x1F, 0x2C, 0xDF, 1849 0x2C, 0x1F, 0x2C, 0xDF,
18500x1A, 0x33, 0x20, 0xE9, 1850 0x1A, 0x33, 0x20, 0xE9,
1851 1851
18520xB0, 0x10, 1852 0xB0, 0x10,
18530x08, 0xE3, 1853 0x08, 0xE3,
18540x40, 0x10, 1854 0x40, 0x10,
18550xB8, 0x10, 1855 0xB8, 0x10,
1856 1856
18570x26, 0xF0, 0x30, 0xCD, 1857 0x26, 0xF0, 0x30, 0xCD,
18580x2F, 0xF0, 0x38, 0xCD, 1858 0x2F, 0xF0, 0x38, 0xCD,
1859 1859
18600x2B, 0x80, 0x20, 0xE9, 1860 0x2B, 0x80, 0x20, 0xE9,
18610x2A, 0x80, 0x20, 0xE9, 1861 0x2A, 0x80, 0x20, 0xE9,
1862 1862
18630xA6, 0x20, 1863 0xA6, 0x20,
18640x88, 0xE2, 1864 0x88, 0xE2,
18650x00, 0xE0, 1865 0x00, 0xE0,
18660xAF, 0x20, 1866 0xAF, 0x20,
1867 1867
18680x28, 0x2A, 0x26, 0xAF, 1868 0x28, 0x2A, 0x26, 0xAF,
18690x20, 0x2A, 0xC0, 0xAF, 1869 0x20, 0x2A, 0xC0, 0xAF,
1870 1870
18710x34, 0x1F, 0x34, 0xDF, 1871 0x34, 0x1F, 0x34, 0xDF,
18720x46, 0x24, 0x46, 0xDF, 1872 0x46, 0x24, 0x46, 0xDF,
1873 1873
18740x28, 0x30, 0x80, 0xBF, 1874 0x28, 0x30, 0x80, 0xBF,
18750x20, 0x38, 0x80, 0xBF, 1875 0x20, 0x38, 0x80, 0xBF,
1876 1876
18770x47, 0x24, 0x47, 0xDF, 1877 0x47, 0x24, 0x47, 0xDF,
18780x4E, 0x2C, 0x4E, 0xDF, 1878 0x4E, 0x2C, 0x4E, 0xDF,
1879 1879
18800x4F, 0x2C, 0x4F, 0xDF, 1880 0x4F, 0x2C, 0x4F, 0xDF,
18810x56, 0x34, 0x56, 0xDF, 1881 0x56, 0x34, 0x56, 0xDF,
1882 1882
18830x28, 0x15, 0x28, 0xDF, 1883 0x28, 0x15, 0x28, 0xDF,
18840x20, 0x1D, 0x20, 0xDF, 1884 0x20, 0x1D, 0x20, 0xDF,
1885 1885
18860x57, 0x34, 0x57, 0xDF, 1886 0x57, 0x34, 0x57, 0xDF,
18870x00, 0xE0, 1887 0x00, 0xE0,
18880x1D, 0x05, 1888 0x1D, 0x05,
1889 1889
18900x04, 0x80, 0x10, 0xEA, 1890 0x04, 0x80, 0x10, 0xEA,
18910x89, 0xE2, 1891 0x89, 0xE2,
18920x2B, 0x30, 1892 0x2B, 0x30,
1893 1893
18940x3F, 0xC1, 0x1D, 0xBD, 1894 0x3F, 0xC1, 0x1D, 0xBD,
18950x00, 0x80, 0x00, 0xE8, 1895 0x00, 0x80, 0x00, 0xE8,
1896 1896
18970x00, 0x80, 0x00, 0xE8, 1897 0x00, 0x80, 0x00, 0xE8,
18980x00, 0x80, 0x00, 0xE8, 1898 0x00, 0x80, 0x00, 0xE8,
1899 1899
19000xA0, 0x68, 1900 0xA0, 0x68,
19010xBF, 0x25, 1901 0xBF, 0x25,
19020x00, 0x80, 0x00, 0xE8, 1902 0x00, 0x80, 0x00, 0xE8,
1903 1903
19040x20, 0xC0, 0x20, 0xAF, 1904 0x20, 0xC0, 0x20, 0xAF,
19050x28, 0x05, 1905 0x28, 0x05,
19060x97, 0x74, 1906 0x97, 0x74,
1907 1907
19080x00, 0xE0, 1908 0x00, 0xE0,
19090x2A, 0x10, 1909 0x2A, 0x10,
19100x16, 0xC0, 0x20, 0xE9, 1910 0x16, 0xC0, 0x20, 0xE9,
1911 1911
19120x04, 0x80, 0x10, 0xEA, 1912 0x04, 0x80, 0x10, 0xEA,
19130x8C, 0xE2, 1913 0x8C, 0xE2,
19140x95, 0x05, 1914 0x95, 0x05,
1915 1915
19160x28, 0xC1, 0x28, 0xAD, 1916 0x28, 0xC1, 0x28, 0xAD,
19170x1F, 0xC1, 0x15, 0xBD, 1917 0x1F, 0xC1, 0x15, 0xBD,
1918 1918
19190x00, 0x80, 0x00, 0xE8, 1919 0x00, 0x80, 0x00, 0xE8,
19200x00, 0x80, 0x00, 0xE8, 1920 0x00, 0x80, 0x00, 0xE8,
1921 1921
19220xA8, 0x67, 1922 0xA8, 0x67,
19230x9F, 0x6B, 1923 0x9F, 0x6B,
19240x00, 0x80, 0x00, 0xE8, 1924 0x00, 0x80, 0x00, 0xE8,
1925 1925
19260x28, 0xC0, 0x28, 0xAD, 1926 0x28, 0xC0, 0x28, 0xAD,
19270x1D, 0x25, 1927 0x1D, 0x25,
19280x20, 0x05, 1928 0x20, 0x05,
1929 1929
19300x28, 0x32, 0x80, 0xAD, 1930 0x28, 0x32, 0x80, 0xAD,
19310x40, 0x2A, 0x40, 0xBD, 1931 0x40, 0x2A, 0x40, 0xBD,
1932 1932
19330x1C, 0x80, 0x20, 0xE9, 1933 0x1C, 0x80, 0x20, 0xE9,
19340x20, 0x33, 0x20, 0xAD, 1934 0x20, 0x33, 0x20, 0xAD,
1935 1935
19360x20, 0x73, 1936 0x20, 0x73,
19370x00, 0xE0, 1937 0x00, 0xE0,
19380xB6, 0x49, 0x51, 0xBB, 1938 0xB6, 0x49, 0x51, 0xBB,
1939 1939
19400x26, 0x2F, 0xB0, 0xE8, 1940 0x26, 0x2F, 0xB0, 0xE8,
19410x19, 0x20, 0x20, 0xE9, 1941 0x19, 0x20, 0x20, 0xE9,
1942 1942
19430x35, 0x20, 0x35, 0xDF, 1943 0x35, 0x20, 0x35, 0xDF,
19440x3D, 0x20, 0x3D, 0xDF, 1944 0x3D, 0x20, 0x3D, 0xDF,
1945 1945
19460x15, 0x20, 0x15, 0xDF, 1946 0x15, 0x20, 0x15, 0xDF,
19470x1D, 0x20, 0x1D, 0xDF, 1947 0x1D, 0x20, 0x1D, 0xDF,
1948 1948
19490x26, 0xD0, 0x26, 0xCD, 1949 0x26, 0xD0, 0x26, 0xCD,
19500x29, 0x49, 0x2A, 0xB8, 1950 0x29, 0x49, 0x2A, 0xB8,
1951 1951
19520x26, 0x40, 0x80, 0xBD, 1952 0x26, 0x40, 0x80, 0xBD,
19530x3B, 0x48, 0x50, 0xBD, 1953 0x3B, 0x48, 0x50, 0xBD,
1954 1954
19550x3E, 0x54, 0x57, 0x9F, 1955 0x3E, 0x54, 0x57, 0x9F,
19560x00, 0xE0, 1956 0x00, 0xE0,
19570x82, 0xE1, 1957 0x82, 0xE1,
1958 1958
19590x1E, 0xAF, 0x59, 0x9F, 1959 0x1E, 0xAF, 0x59, 0x9F,
19600x00, 0x80, 0x00, 0xE8, 1960 0x00, 0x80, 0x00, 0xE8,
1961 1961
19620x26, 0x30, 1962 0x26, 0x30,
19630x29, 0x30, 1963 0x29, 0x30,
19640x48, 0x3C, 0x48, 0xAD, 1964 0x48, 0x3C, 0x48, 0xAD,
1965 1965
19660x2B, 0x72, 1966 0x2B, 0x72,
19670xC2, 0xE1, 1967 0xC2, 0xE1,
19680x2C, 0xC0, 0x44, 0xC2, 1968 0x2C, 0xC0, 0x44, 0xC2,
1969 1969
19700x05, 0x24, 0x34, 0xBF, 1970 0x05, 0x24, 0x34, 0xBF,
19710x0D, 0x24, 0x2C, 0xBF, 1971 0x0D, 0x24, 0x2C, 0xBF,
1972 1972
19730x2D, 0x46, 0x4E, 0xBF, 1973 0x2D, 0x46, 0x4E, 0xBF,
19740x25, 0x46, 0x56, 0xBF, 1974 0x25, 0x46, 0x56, 0xBF,
1975 1975
19760x20, 0x1D, 0x6F, 0x8F, 1976 0x20, 0x1D, 0x6F, 0x8F,
19770x32, 0x3E, 0x5F, 0xE9, 1977 0x32, 0x3E, 0x5F, 0xE9,
1978 1978
19790x3E, 0x50, 0x56, 0x9F, 1979 0x3E, 0x50, 0x56, 0x9F,
19800x00, 0xE0, 1980 0x00, 0xE0,
19810x3B, 0x30, 1981 0x3B, 0x30,
1982 1982
19830x1E, 0x8F, 0x51, 0x9F, 1983 0x1E, 0x8F, 0x51, 0x9F,
19840x33, 0x1E, 0x5F, 0xE9, 1984 0x33, 0x1E, 0x5F, 0xE9,
1985 1985
19860x05, 0x44, 0x54, 0xB2, 1986 0x05, 0x44, 0x54, 0xB2,
19870x0D, 0x44, 0x4C, 0xB2, 1987 0x0D, 0x44, 0x4C, 0xB2,
1988 1988
19890x19, 0xC0, 0xB0, 0xE8, 1989 0x19, 0xC0, 0xB0, 0xE8,
19900x34, 0xC0, 0x44, 0xC4, 1990 0x34, 0xC0, 0x44, 0xC4,
1991 1991
19920x33, 0x73, 1992 0x33, 0x73,
19930x00, 0xE0, 1993 0x00, 0xE0,
19940x3E, 0x62, 0x57, 0x9F, 1994 0x3E, 0x62, 0x57, 0x9F,
1995 1995
19960x1E, 0xAF, 0x59, 0x9F, 1996 0x1E, 0xAF, 0x59, 0x9F,
19970x00, 0xE0, 1997 0x00, 0xE0,
19980x0D, 0x20, 1998 0x0D, 0x20,
1999 1999
20000x84, 0x3E, 0x58, 0xE9, 2000 0x84, 0x3E, 0x58, 0xE9,
20010x28, 0x1D, 0x6F, 0x8F, 2001 0x28, 0x1D, 0x6F, 0x8F,
2002 2002
20030x05, 0x20, 2003 0x05, 0x20,
20040x00, 0xE0, 2004 0x00, 0xE0,
20050x85, 0x1E, 0x58, 0xE9, 2005 0x85, 0x1E, 0x58, 0xE9,
2006 2006
20070x9B, 0x3B, 0x33, 0xDF, 2007 0x9B, 0x3B, 0x33, 0xDF,
20080x20, 0x20, 0x42, 0xAF, 2008 0x20, 0x20, 0x42, 0xAF,
2009 2009
20100x30, 0x42, 0x56, 0x9F, 2010 0x30, 0x42, 0x56, 0x9F,
20110x80, 0x3E, 0x57, 0xE9, 2011 0x80, 0x3E, 0x57, 0xE9,
2012 2012
20130x3F, 0x8F, 0x51, 0x9F, 2013 0x3F, 0x8F, 0x51, 0x9F,
20140x30, 0x80, 0x5F, 0xE9, 2014 0x30, 0x80, 0x5F, 0xE9,
2015 2015
20160x28, 0x28, 0x24, 0xAF, 2016 0x28, 0x28, 0x24, 0xAF,
20170x81, 0x1E, 0x57, 0xE9, 2017 0x81, 0x1E, 0x57, 0xE9,
2018 2018
20190x05, 0x47, 0x57, 0xBF, 2019 0x05, 0x47, 0x57, 0xBF,
20200x0D, 0x47, 0x4F, 0xBF, 2020 0x0D, 0x47, 0x4F, 0xBF,
2021 2021
20220x88, 0x80, 0x58, 0xE9, 2022 0x88, 0x80, 0x58, 0xE9,
20230x1B, 0x29, 0x1B, 0xDF, 2023 0x1B, 0x29, 0x1B, 0xDF,
2024 2024
20250x30, 0x1D, 0x6F, 0x8F, 2025 0x30, 0x1D, 0x6F, 0x8F,
20260x3A, 0x30, 0x4F, 0xE9, 2026 0x3A, 0x30, 0x4F, 0xE9,
2027 2027
20280x1C, 0x30, 0x26, 0xDF, 2028 0x1C, 0x30, 0x26, 0xDF,
20290x09, 0xE3, 2029 0x09, 0xE3,
20300x3B, 0x05, 2030 0x3B, 0x05,
2031 2031
20320x3E, 0x50, 0x56, 0x9F, 2032 0x3E, 0x50, 0x56, 0x9F,
20330x3B, 0x3F, 0x4F, 0xE9, 2033 0x3B, 0x3F, 0x4F, 0xE9,
2034 2034
20350x1E, 0x8F, 0x51, 0x9F, 2035 0x1E, 0x8F, 0x51, 0x9F,
20360x00, 0xE0, 2036 0x00, 0xE0,
20370xAC, 0x20, 2037 0xAC, 0x20,
2038 2038
20390x2D, 0x44, 0x4C, 0xB4, 2039 0x2D, 0x44, 0x4C, 0xB4,
20400x2C, 0x1C, 0xC0, 0xAF, 2040 0x2C, 0x1C, 0xC0, 0xAF,
2041 2041
20420x25, 0x44, 0x54, 0xB4, 2042 0x25, 0x44, 0x54, 0xB4,
20430x00, 0xE0, 2043 0x00, 0xE0,
20440xC8, 0x30, 2044 0xC8, 0x30,
2045 2045
20460x30, 0x46, 0x30, 0xAF, 2046 0x30, 0x46, 0x30, 0xAF,
20470x1B, 0x1B, 0x48, 0xAF, 2047 0x1B, 0x1B, 0x48, 0xAF,
2048 2048
20490x00, 0xE0, 2049 0x00, 0xE0,
20500x25, 0x20, 2050 0x25, 0x20,
20510x38, 0x2C, 0x4F, 0xE9, 2051 0x38, 0x2C, 0x4F, 0xE9,
2052 2052
20530x86, 0x80, 0x57, 0xE9, 2053 0x86, 0x80, 0x57, 0xE9,
20540x38, 0x1D, 0x6F, 0x8F, 2054 0x38, 0x1D, 0x6F, 0x8F,
2055 2055
20560x28, 0x74, 2056 0x28, 0x74,
20570x00, 0xE0, 2057 0x00, 0xE0,
20580x0D, 0x44, 0x4C, 0xB0, 2058 0x0D, 0x44, 0x4C, 0xB0,
2059 2059
20600x05, 0x44, 0x54, 0xB0, 2060 0x05, 0x44, 0x54, 0xB0,
20610x2D, 0x20, 2061 0x2D, 0x20,
20620x9B, 0x10, 2062 0x9B, 0x10,
2063 2063
20640x82, 0x3E, 0x57, 0xE9, 2064 0x82, 0x3E, 0x57, 0xE9,
20650x32, 0xF0, 0x1B, 0xCD, 2065 0x32, 0xF0, 0x1B, 0xCD,
2066 2066
20670x1E, 0xBD, 0x59, 0x9F, 2067 0x1E, 0xBD, 0x59, 0x9F,
20680x83, 0x1E, 0x57, 0xE9, 2068 0x83, 0x1E, 0x57, 0xE9,
2069 2069
20700x38, 0x47, 0x38, 0xAF, 2070 0x38, 0x47, 0x38, 0xAF,
20710x34, 0x20, 2071 0x34, 0x20,
20720x2A, 0x30, 2072 0x2A, 0x30,
2073 2073
20740x00, 0xE0, 2074 0x00, 0xE0,
20750x0D, 0x20, 2075 0x0D, 0x20,
20760x32, 0x20, 2076 0x32, 0x20,
20770x05, 0x20, 2077 0x05, 0x20,
2078 2078
20790x87, 0x80, 0x57, 0xE9, 2079 0x87, 0x80, 0x57, 0xE9,
20800x1F, 0x54, 0x57, 0x9F, 2080 0x1F, 0x54, 0x57, 0x9F,
2081 2081
20820x17, 0x42, 0x56, 0x9F, 2082 0x17, 0x42, 0x56, 0x9F,
20830x00, 0xE0, 2083 0x00, 0xE0,
20840x3B, 0x6A, 2084 0x3B, 0x6A,
2085 2085
20860x3F, 0x8F, 0x51, 0x9F, 2086 0x3F, 0x8F, 0x51, 0x9F,
20870x37, 0x1E, 0x4F, 0xE9, 2087 0x37, 0x1E, 0x4F, 0xE9,
2088 2088
20890x37, 0x32, 0x2A, 0xAF, 2089 0x37, 0x32, 0x2A, 0xAF,
20900x00, 0xE0, 2090 0x00, 0xE0,
20910x32, 0x00, 2091 0x32, 0x00,
2092 2092
20930x00, 0x80, 0x00, 0xE8, 2093 0x00, 0x80, 0x00, 0xE8,
20940x27, 0xC0, 0x44, 0xC0, 2094 0x27, 0xC0, 0x44, 0xC0,
2095 2095
20960x36, 0x1F, 0x4F, 0xE9, 2096 0x36, 0x1F, 0x4F, 0xE9,
20970x1F, 0x1F, 0x26, 0xDF, 2097 0x1F, 0x1F, 0x26, 0xDF,
2098 2098
20990x37, 0x1B, 0x37, 0xBF, 2099 0x37, 0x1B, 0x37, 0xBF,
21000x17, 0x26, 0x17, 0xDF, 2100 0x17, 0x26, 0x17, 0xDF,
2101 2101
21020x3E, 0x17, 0x4F, 0xE9, 2102 0x3E, 0x17, 0x4F, 0xE9,
21030x3F, 0x3F, 0x4F, 0xE9, 2103 0x3F, 0x3F, 0x4F, 0xE9,
2104 2104
21050x34, 0x1F, 0x34, 0xAF, 2105 0x34, 0x1F, 0x34, 0xAF,
21060x2B, 0x05, 2106 0x2B, 0x05,
21070xA7, 0x20, 2107 0xA7, 0x20,
2108 2108
21090x33, 0x2B, 0x37, 0xDF, 2109 0x33, 0x2B, 0x37, 0xDF,
21100x27, 0x17, 0xC0, 0xAF, 2110 0x27, 0x17, 0xC0, 0xAF,
2111 2111
21120x34, 0x80, 0x4F, 0xE9, 2112 0x34, 0x80, 0x4F, 0xE9,
21130x00, 0x80, 0x00, 0xE8, 2113 0x00, 0x80, 0x00, 0xE8,
2114 2114
21150x0D, 0x21, 0x1A, 0xB6, 2115 0x0D, 0x21, 0x1A, 0xB6,
21160x05, 0x21, 0x31, 0xB6, 2116 0x05, 0x21, 0x31, 0xB6,
2117 2117
21180x03, 0x80, 0x2A, 0xEA, 2118 0x03, 0x80, 0x2A, 0xEA,
21190x17, 0xC1, 0x2B, 0xBD, 2119 0x17, 0xC1, 0x2B, 0xBD,
2120 2120
21210x0D, 0x20, 2121 0x0D, 0x20,
21220x05, 0x20, 2122 0x05, 0x20,
21230x2F, 0xC0, 0x21, 0xC6, 2123 0x2F, 0xC0, 0x21, 0xC6,
2124 2124
21250xB3, 0x68, 2125 0xB3, 0x68,
21260x97, 0x25, 2126 0x97, 0x25,
21270x00, 0x80, 0x00, 0xE8, 2127 0x00, 0x80, 0x00, 0xE8,
2128 2128
21290x33, 0xC0, 0x33, 0xAF, 2129 0x33, 0xC0, 0x33, 0xAF,
21300x3C, 0x27, 0x4F, 0xE9, 2130 0x3C, 0x27, 0x4F, 0xE9,
2131 2131
21320x17, 0x50, 0x56, 0x9F, 2132 0x17, 0x50, 0x56, 0x9F,
21330x00, 0x80, 0x00, 0xE8, 2133 0x00, 0x80, 0x00, 0xE8,
2134 2134
21350x37, 0x0F, 0x5C, 0x9F, 2135 0x37, 0x0F, 0x5C, 0x9F,
21360x00, 0xE0, 2136 0x00, 0xE0,
21370x2F, 0x20, 2137 0x2F, 0x20,
2138 2138
21390x00, 0x80, 0x00, 0xE8, 2139 0x00, 0x80, 0x00, 0xE8,
21400x28, 0x19, 0x60, 0xEC, 2140 0x28, 0x19, 0x60, 0xEC,
2141 2141
21420xB3, 0x05, 2142 0xB3, 0x05,
21430x00, 0xE0, 2143 0x00, 0xE0,
21440x00, 0x80, 0x00, 0xE8, 2144 0x00, 0x80, 0x00, 0xE8,
2145 2145
21460x23, 0x3B, 0x33, 0xAD, 2146 0x23, 0x3B, 0x33, 0xAD,
21470x00, 0x80, 0x00, 0xE8, 2147 0x00, 0x80, 0x00, 0xE8,
2148 2148
21490x17, 0x26, 0x17, 0xDF, 2149 0x17, 0x26, 0x17, 0xDF,
21500x35, 0x17, 0x4F, 0xE9, 2150 0x35, 0x17, 0x4F, 0xE9,
2151 2151
21520x00, 0x80, 0x00, 0xE8, 2152 0x00, 0x80, 0x00, 0xE8,
21530x00, 0x80, 0x00, 0xE8, 2153 0x00, 0x80, 0x00, 0xE8,
2154 2154
21550x00, 0x80, 0x00, 0xE8, 2155 0x00, 0x80, 0x00, 0xE8,
21560x39, 0x37, 0x4F, 0xE9, 2156 0x39, 0x37, 0x4F, 0xE9,
2157 2157
21580x2F, 0x2F, 0x17, 0xAF, 2158 0x2F, 0x2F, 0x17, 0xAF,
21590x00, 0x80, 0x00, 0xE8, 2159 0x00, 0x80, 0x00, 0xE8,
2160 2160
21610x00, 0x80, 0x00, 0xE8, 2161 0x00, 0x80, 0x00, 0xE8,
21620x00, 0x80, 0x00, 0xE8, 2162 0x00, 0x80, 0x00, 0xE8,
2163 2163
21640x31, 0x80, 0x4F, 0xE9, 2164 0x31, 0x80, 0x4F, 0xE9,
21650x00, 0x80, 0x00, 0xE8, 2165 0x00, 0x80, 0x00, 0xE8,
2166 2166
21670x00, 0x80, 0x00, 0xE8, 2167 0x00, 0x80, 0x00, 0xE8,
21680x57, 0x39, 0x20, 0xE9, 2168 0x57, 0x39, 0x20, 0xE9,
2169 2169
21700x16, 0x28, 0x20, 0xE9, 2170 0x16, 0x28, 0x20, 0xE9,
21710x1D, 0x3B, 0x20, 0xE9, 2171 0x1D, 0x3B, 0x20, 0xE9,
2172 2172
21730x1E, 0x2B, 0x20, 0xE9, 2173 0x1E, 0x2B, 0x20, 0xE9,
21740x2B, 0x32, 0x20, 0xE9, 2174 0x2B, 0x32, 0x20, 0xE9,
2175 2175
21760x1C, 0x23, 0x20, 0xE9, 2176 0x1C, 0x23, 0x20, 0xE9,
21770x57, 0x36, 0x20, 0xE9, 2177 0x57, 0x36, 0x20, 0xE9,
2178 2178
21790x00, 0x80, 0xA0, 0xE9, 2179 0x00, 0x80, 0xA0, 0xE9,
21800x40, 0x40, 0xD8, 0xEC, 2180 0x40, 0x40, 0xD8, 0xEC,
2181 2181
21820xFF, 0x80, 0xC0, 0xE9, 2182 0xFF, 0x80, 0xC0, 0xE9,
21830x90, 0xE2, 2183 0x90, 0xE2,
21840x00, 0xE0, 2184 0x00, 0xE0,
2185 2185
21860x78, 0xFF, 0x20, 0xEA, 2186 0x78, 0xFF, 0x20, 0xEA,
21870x19, 0xC8, 0xC1, 0xCD, 2187 0x19, 0xC8, 0xC1, 0xCD,
2188 2188
21890x1F, 0xD7, 0x18, 0xBD, 2189 0x1F, 0xD7, 0x18, 0xBD,
21900x3F, 0xD7, 0x22, 0xBD, 2190 0x3F, 0xD7, 0x22, 0xBD,
2191 2191
21920x9F, 0x41, 0x49, 0xBD, 2192 0x9F, 0x41, 0x49, 0xBD,
21930x00, 0x80, 0x00, 0xE8, 2193 0x00, 0x80, 0x00, 0xE8,
2194 2194
21950x25, 0x41, 0x49, 0xBD, 2195 0x25, 0x41, 0x49, 0xBD,
21960x2D, 0x41, 0x51, 0xBD, 2196 0x2D, 0x41, 0x51, 0xBD,
2197 2197
21980x0D, 0x80, 0x07, 0xEA, 2198 0x0D, 0x80, 0x07, 0xEA,
21990x00, 0x80, 0x00, 0xE8, 2199 0x00, 0x80, 0x00, 0xE8,
2200 2200
22010x35, 0x40, 0x48, 0xBD, 2201 0x35, 0x40, 0x48, 0xBD,
22020x3D, 0x40, 0x50, 0xBD, 2202 0x3D, 0x40, 0x50, 0xBD,
2203 2203
22040x00, 0x80, 0x00, 0xE8, 2204 0x00, 0x80, 0x00, 0xE8,
22050x25, 0x30, 2205 0x25, 0x30,
22060x2D, 0x30, 2206 0x2D, 0x30,
2207 2207
22080x35, 0x30, 2208 0x35, 0x30,
22090xB5, 0x30, 2209 0xB5, 0x30,
22100xBD, 0x30, 2210 0xBD, 0x30,
22110x3D, 0x30, 2211 0x3D, 0x30,
2212 2212
22130x9C, 0xA7, 0x5B, 0x9F, 2213 0x9C, 0xA7, 0x5B, 0x9F,
22140x00, 0x80, 0x00, 0xE8, 2214 0x00, 0x80, 0x00, 0xE8,
2215 2215
22160x00, 0x80, 0x00, 0xE8, 2216 0x00, 0x80, 0x00, 0xE8,
22170x00, 0x80, 0x00, 0xE8, 2217 0x00, 0x80, 0x00, 0xE8,
2218 2218
22190x00, 0x80, 0x00, 0xE8, 2219 0x00, 0x80, 0x00, 0xE8,
22200x00, 0x80, 0x00, 0xE8, 2220 0x00, 0x80, 0x00, 0xE8,
2221 2221
22220x00, 0x80, 0x00, 0xE8, 2222 0x00, 0x80, 0x00, 0xE8,
22230x00, 0x80, 0x00, 0xE8, 2223 0x00, 0x80, 0x00, 0xE8,
2224 2224
22250x00, 0x80, 0x00, 0xE8, 2225 0x00, 0x80, 0x00, 0xE8,
22260x00, 0x80, 0x00, 0xE8, 2226 0x00, 0x80, 0x00, 0xE8,
2227 2227
22280x77, 0xFF, 0x0A, 0xEA, 2228 0x77, 0xFF, 0x0A, 0xEA,
22290x00, 0x80, 0x00, 0xE8, 2229 0x00, 0x80, 0x00, 0xE8,
2230 2230
22310xC9, 0x41, 0xC8, 0xEC, 2231 0xC9, 0x41, 0xC8, 0xEC,
22320x42, 0xE1, 2232 0x42, 0xE1,
22330x00, 0xE0, 2233 0x00, 0xE0,
2234 2234
22350x75, 0xFF, 0x20, 0xEA, 2235 0x75, 0xFF, 0x20, 0xEA,
22360x00, 0x80, 0x00, 0xE8, 2236 0x00, 0x80, 0x00, 0xE8,
2237 2237
22380x00, 0x80, 0x00, 0xE8, 2238 0x00, 0x80, 0x00, 0xE8,
22390x00, 0x80, 0x00, 0xE8, 2239 0x00, 0x80, 0x00, 0xE8,
2240 2240
22410xC8, 0x40, 0xC0, 0xEC, 2241 0xC8, 0x40, 0xC0, 0xEC,
22420x00, 0x80, 0x00, 0xE8, 2242 0x00, 0x80, 0x00, 0xE8,
2243 2243
22440x72, 0xFF, 0x20, 0xEA, 2244 0x72, 0xFF, 0x20, 0xEA,
22450x00, 0x80, 0x00, 0xE8, 2245 0x00, 0x80, 0x00, 0xE8,
2246 2246
22470x00, 0x80, 0x00, 0xE8, 2247 0x00, 0x80, 0x00, 0xE8,
22480x00, 0x80, 0x00, 0xE8, 2248 0x00, 0x80, 0x00, 0xE8,
2249 2249
2250}; 2250};
2251 2251
2252static unsigned char warp_g200_tgzs[] = { 2252static unsigned char warp_g200_tgzs[] = {
2253 2253
22540x00, 0x80, 0x00, 0xE8, 2254 0x00, 0x80, 0x00, 0xE8,
22550x00, 0x80, 0x00, 0xE8, 2255 0x00, 0x80, 0x00, 0xE8,
2256 2256
22570x00, 0x80, 0x00, 0xE8, 2257 0x00, 0x80, 0x00, 0xE8,
22580x00, 0x80, 0x00, 0xE8, 2258 0x00, 0x80, 0x00, 0xE8,
2259 2259
22600x00, 0x80, 0x00, 0xE8, 2260 0x00, 0x80, 0x00, 0xE8,
22610x00, 0x80, 0x00, 0xE8, 2261 0x00, 0x80, 0x00, 0xE8,
2262 2262
22630x00, 0x80, 0x00, 0xE8, 2263 0x00, 0x80, 0x00, 0xE8,
22640x00, 0x80, 0x00, 0xE8, 2264 0x00, 0x80, 0x00, 0xE8,
2265 2265
22660x00, 0x80, 0x00, 0xE8, 2266 0x00, 0x80, 0x00, 0xE8,
22670x00, 0x80, 0x00, 0xE8, 2267 0x00, 0x80, 0x00, 0xE8,
2268 2268
22690x00, 0x80, 0x00, 0xE8, 2269 0x00, 0x80, 0x00, 0xE8,
22700x00, 0x80, 0x00, 0xE8, 2270 0x00, 0x80, 0x00, 0xE8,
2271 2271
22720x00, 0x80, 0x00, 0xE8, 2272 0x00, 0x80, 0x00, 0xE8,
22730x00, 0x80, 0x00, 0xE8, 2273 0x00, 0x80, 0x00, 0xE8,
2274 2274
22750x00, 0x80, 0x00, 0xE8, 2275 0x00, 0x80, 0x00, 0xE8,
22760x00, 0x80, 0x00, 0xE8, 2276 0x00, 0x80, 0x00, 0xE8,
2277 2277
22780x00, 0x80, 0x00, 0xE8, 2278 0x00, 0x80, 0x00, 0xE8,
22790x00, 0x80, 0x00, 0xE8, 2279 0x00, 0x80, 0x00, 0xE8,
2280 2280
22810x00, 0x80, 0x00, 0xE8, 2281 0x00, 0x80, 0x00, 0xE8,
22820x00, 0x80, 0x00, 0xE8, 2282 0x00, 0x80, 0x00, 0xE8,
2283 2283
22840x00, 0x80, 0x00, 0xE8, 2284 0x00, 0x80, 0x00, 0xE8,
22850x00, 0x80, 0x00, 0xE8, 2285 0x00, 0x80, 0x00, 0xE8,
2286 2286
22870x00, 0x80, 0x00, 0xE8, 2287 0x00, 0x80, 0x00, 0xE8,
22880x00, 0x80, 0x00, 0xE8, 2288 0x00, 0x80, 0x00, 0xE8,
2289 2289
22900x00, 0x80, 0x00, 0xE8, 2290 0x00, 0x80, 0x00, 0xE8,
22910x00, 0x80, 0x00, 0xE8, 2291 0x00, 0x80, 0x00, 0xE8,
2292 2292
22930x00, 0x98, 0xA0, 0xE9, 2293 0x00, 0x98, 0xA0, 0xE9,
22940x40, 0x40, 0xD8, 0xEC, 2294 0x40, 0x40, 0xD8, 0xEC,
2295 2295
22960xFF, 0x80, 0xC0, 0xE9, 2296 0xFF, 0x80, 0xC0, 0xE9,
22970x00, 0x80, 0x00, 0xE8, 2297 0x00, 0x80, 0x00, 0xE8,
2298 2298
22990x1F, 0xD7, 0x18, 0xBD, 2299 0x1F, 0xD7, 0x18, 0xBD,
23000x3F, 0xD7, 0x22, 0xBD, 2300 0x3F, 0xD7, 0x22, 0xBD,
2301 2301
23020x81, 0x04, 2302 0x81, 0x04,
23030x89, 0x04, 2303 0x89, 0x04,
23040x01, 0x04, 2304 0x01, 0x04,
23050x09, 0x04, 2305 0x09, 0x04,
2306 2306
23070xC9, 0x41, 0xC0, 0xEC, 2307 0xC9, 0x41, 0xC0, 0xEC,
23080x11, 0x04, 2308 0x11, 0x04,
23090x00, 0xE0, 2309 0x00, 0xE0,
2310 2310
23110x41, 0xCC, 0x41, 0xCD, 2311 0x41, 0xCC, 0x41, 0xCD,
23120x49, 0xCC, 0x49, 0xCD, 2312 0x49, 0xCC, 0x49, 0xCD,
2313 2313
23140xD1, 0x41, 0xC0, 0xEC, 2314 0xD1, 0x41, 0xC0, 0xEC,
23150x51, 0xCC, 0x51, 0xCD, 2315 0x51, 0xCC, 0x51, 0xCD,
2316 2316
23170x80, 0x04, 2317 0x80, 0x04,
23180x10, 0x04, 2318 0x10, 0x04,
23190x08, 0x04, 2319 0x08, 0x04,
23200x00, 0xE0, 2320 0x00, 0xE0,
2321 2321
23220x00, 0xCC, 0xC0, 0xCD, 2322 0x00, 0xCC, 0xC0, 0xCD,
23230xD1, 0x49, 0xC0, 0xEC, 2323 0xD1, 0x49, 0xC0, 0xEC,
2324 2324
23250x8A, 0x1F, 0x20, 0xE9, 2325 0x8A, 0x1F, 0x20, 0xE9,
23260x8B, 0x3F, 0x20, 0xE9, 2326 0x8B, 0x3F, 0x20, 0xE9,
2327 2327
23280x41, 0x3C, 0x41, 0xAD, 2328 0x41, 0x3C, 0x41, 0xAD,
23290x49, 0x3C, 0x49, 0xAD, 2329 0x49, 0x3C, 0x49, 0xAD,
2330 2330
23310x10, 0xCC, 0x10, 0xCD, 2331 0x10, 0xCC, 0x10, 0xCD,
23320x08, 0xCC, 0x08, 0xCD, 2332 0x08, 0xCC, 0x08, 0xCD,
2333 2333
23340xB9, 0x41, 0x49, 0xBB, 2334 0xB9, 0x41, 0x49, 0xBB,
23350x1F, 0xF0, 0x41, 0xCD, 2335 0x1F, 0xF0, 0x41, 0xCD,
2336 2336
23370x51, 0x3C, 0x51, 0xAD, 2337 0x51, 0x3C, 0x51, 0xAD,
23380x00, 0x98, 0x80, 0xE9, 2338 0x00, 0x98, 0x80, 0xE9,
2339 2339
23400x8B, 0x80, 0x07, 0xEA, 2340 0x8B, 0x80, 0x07, 0xEA,
23410x24, 0x1F, 0x20, 0xE9, 2341 0x24, 0x1F, 0x20, 0xE9,
2342 2342
23430x21, 0x45, 0x80, 0xE8, 2343 0x21, 0x45, 0x80, 0xE8,
23440x1A, 0x4D, 0x80, 0xE8, 2344 0x1A, 0x4D, 0x80, 0xE8,
2345 2345
23460x31, 0x55, 0x80, 0xE8, 2346 0x31, 0x55, 0x80, 0xE8,
23470x00, 0x80, 0x00, 0xE8, 2347 0x00, 0x80, 0x00, 0xE8,
2348 2348
23490x15, 0x41, 0x49, 0xBD, 2349 0x15, 0x41, 0x49, 0xBD,
23500x1D, 0x41, 0x51, 0xBD, 2350 0x1D, 0x41, 0x51, 0xBD,
2351 2351
23520x2E, 0x41, 0x2A, 0xB8, 2352 0x2E, 0x41, 0x2A, 0xB8,
23530x34, 0x53, 0xA0, 0xE8, 2353 0x34, 0x53, 0xA0, 0xE8,
2354 2354
23550x15, 0x30, 2355 0x15, 0x30,
23560x1D, 0x30, 2356 0x1D, 0x30,
23570x58, 0xE3, 2357 0x58, 0xE3,
23580x00, 0xE0, 2358 0x00, 0xE0,
2359 2359
23600xB5, 0x40, 0x48, 0xBD, 2360 0xB5, 0x40, 0x48, 0xBD,
23610x3D, 0x40, 0x50, 0xBD, 2361 0x3D, 0x40, 0x50, 0xBD,
2362 2362
23630x24, 0x43, 0xA0, 0xE8, 2363 0x24, 0x43, 0xA0, 0xE8,
23640x2C, 0x4B, 0xA0, 0xE8, 2364 0x2C, 0x4B, 0xA0, 0xE8,
2365 2365
23660x15, 0x72, 2366 0x15, 0x72,
23670x09, 0xE3, 2367 0x09, 0xE3,
23680x00, 0xE0, 2368 0x00, 0xE0,
23690x1D, 0x72, 2369 0x1D, 0x72,
2370 2370
23710x35, 0x30, 2371 0x35, 0x30,
23720xB5, 0x30, 2372 0xB5, 0x30,
23730xBD, 0x30, 2373 0xBD, 0x30,
23740x3D, 0x30, 2374 0x3D, 0x30,
2375 2375
23760x9C, 0x97, 0x57, 0x9F, 2376 0x9C, 0x97, 0x57, 0x9F,
23770x00, 0x80, 0x00, 0xE8, 2377 0x00, 0x80, 0x00, 0xE8,
2378 2378
23790x6C, 0x64, 0xC8, 0xEC, 2379 0x6C, 0x64, 0xC8, 0xEC,
23800x98, 0xE1, 2380 0x98, 0xE1,
23810xB5, 0x05, 2381 0xB5, 0x05,
2382 2382
23830xBD, 0x05, 2383 0xBD, 0x05,
23840x2E, 0x30, 2384 0x2E, 0x30,
23850x32, 0xC0, 0xA0, 0xE8, 2385 0x32, 0xC0, 0xA0, 0xE8,
2386 2386
23870x33, 0xC0, 0xA0, 0xE8, 2387 0x33, 0xC0, 0xA0, 0xE8,
23880x74, 0x64, 0xC8, 0xEC, 2388 0x74, 0x64, 0xC8, 0xEC,
2389 2389
23900x40, 0x3C, 0x40, 0xAD, 2390 0x40, 0x3C, 0x40, 0xAD,
23910x32, 0x6A, 2391 0x32, 0x6A,
23920x2A, 0x30, 2392 0x2A, 0x30,
2393 2393
23940x20, 0x73, 2394 0x20, 0x73,
23950x33, 0x6A, 2395 0x33, 0x6A,
23960x00, 0xE0, 2396 0x00, 0xE0,
23970x28, 0x73, 2397 0x28, 0x73,
2398 2398
23990x1C, 0x72, 2399 0x1C, 0x72,
24000x83, 0xE2, 2400 0x83, 0xE2,
24010x77, 0x80, 0x15, 0xEA, 2401 0x77, 0x80, 0x15, 0xEA,
2402 2402
24030xB8, 0x3D, 0x28, 0xDF, 2403 0xB8, 0x3D, 0x28, 0xDF,
24040x30, 0x35, 0x20, 0xDF, 2404 0x30, 0x35, 0x20, 0xDF,
2405 2405
24060x40, 0x30, 2406 0x40, 0x30,
24070x00, 0xE0, 2407 0x00, 0xE0,
24080xCC, 0xE2, 2408 0xCC, 0xE2,
24090x64, 0x72, 2409 0x64, 0x72,
2410 2410
24110x25, 0x42, 0x52, 0xBF, 2411 0x25, 0x42, 0x52, 0xBF,
24120x2D, 0x42, 0x4A, 0xBF, 2412 0x2D, 0x42, 0x4A, 0xBF,
2413 2413
24140x30, 0x2E, 0x30, 0xDF, 2414 0x30, 0x2E, 0x30, 0xDF,
24150x38, 0x2E, 0x38, 0xDF, 2415 0x38, 0x2E, 0x38, 0xDF,
2416 2416
24170x18, 0x1D, 0x45, 0xE9, 2417 0x18, 0x1D, 0x45, 0xE9,
24180x1E, 0x15, 0x45, 0xE9, 2418 0x1E, 0x15, 0x45, 0xE9,
2419 2419
24200x2B, 0x49, 0x51, 0xBD, 2420 0x2B, 0x49, 0x51, 0xBD,
24210x00, 0xE0, 2421 0x00, 0xE0,
24220x1F, 0x73, 2422 0x1F, 0x73,
2423 2423
24240x38, 0x38, 0x40, 0xAF, 2424 0x38, 0x38, 0x40, 0xAF,
24250x30, 0x30, 0x40, 0xAF, 2425 0x30, 0x30, 0x40, 0xAF,
2426 2426
24270x24, 0x1F, 0x24, 0xDF, 2427 0x24, 0x1F, 0x24, 0xDF,
24280x1D, 0x32, 0x20, 0xE9, 2428 0x1D, 0x32, 0x20, 0xE9,
2429 2429
24300x2C, 0x1F, 0x2C, 0xDF, 2430 0x2C, 0x1F, 0x2C, 0xDF,
24310x1A, 0x33, 0x20, 0xE9, 2431 0x1A, 0x33, 0x20, 0xE9,
2432 2432
24330xB0, 0x10, 2433 0xB0, 0x10,
24340x08, 0xE3, 2434 0x08, 0xE3,
24350x40, 0x10, 2435 0x40, 0x10,
24360xB8, 0x10, 2436 0xB8, 0x10,
2437 2437
24380x26, 0xF0, 0x30, 0xCD, 2438 0x26, 0xF0, 0x30, 0xCD,
24390x2F, 0xF0, 0x38, 0xCD, 2439 0x2F, 0xF0, 0x38, 0xCD,
2440 2440
24410x2B, 0x80, 0x20, 0xE9, 2441 0x2B, 0x80, 0x20, 0xE9,
24420x2A, 0x80, 0x20, 0xE9, 2442 0x2A, 0x80, 0x20, 0xE9,
2443 2443
24440xA6, 0x20, 2444 0xA6, 0x20,
24450x88, 0xE2, 2445 0x88, 0xE2,
24460x00, 0xE0, 2446 0x00, 0xE0,
24470xAF, 0x20, 2447 0xAF, 0x20,
2448 2448
24490x28, 0x2A, 0x26, 0xAF, 2449 0x28, 0x2A, 0x26, 0xAF,
24500x20, 0x2A, 0xC0, 0xAF, 2450 0x20, 0x2A, 0xC0, 0xAF,
2451 2451
24520x34, 0x1F, 0x34, 0xDF, 2452 0x34, 0x1F, 0x34, 0xDF,
24530x46, 0x24, 0x46, 0xDF, 2453 0x46, 0x24, 0x46, 0xDF,
2454 2454
24550x28, 0x30, 0x80, 0xBF, 2455 0x28, 0x30, 0x80, 0xBF,
24560x20, 0x38, 0x80, 0xBF, 2456 0x20, 0x38, 0x80, 0xBF,
2457 2457
24580x47, 0x24, 0x47, 0xDF, 2458 0x47, 0x24, 0x47, 0xDF,
24590x4E, 0x2C, 0x4E, 0xDF, 2459 0x4E, 0x2C, 0x4E, 0xDF,
2460 2460
24610x4F, 0x2C, 0x4F, 0xDF, 2461 0x4F, 0x2C, 0x4F, 0xDF,
24620x56, 0x34, 0x56, 0xDF, 2462 0x56, 0x34, 0x56, 0xDF,
2463 2463
24640x28, 0x15, 0x28, 0xDF, 2464 0x28, 0x15, 0x28, 0xDF,
24650x20, 0x1D, 0x20, 0xDF, 2465 0x20, 0x1D, 0x20, 0xDF,
2466 2466
24670x57, 0x34, 0x57, 0xDF, 2467 0x57, 0x34, 0x57, 0xDF,
24680x00, 0xE0, 2468 0x00, 0xE0,
24690x1D, 0x05, 2469 0x1D, 0x05,
2470 2470
24710x04, 0x80, 0x10, 0xEA, 2471 0x04, 0x80, 0x10, 0xEA,
24720x89, 0xE2, 2472 0x89, 0xE2,
24730x2B, 0x30, 2473 0x2B, 0x30,
2474 2474
24750x3F, 0xC1, 0x1D, 0xBD, 2475 0x3F, 0xC1, 0x1D, 0xBD,
24760x00, 0x80, 0x00, 0xE8, 2476 0x00, 0x80, 0x00, 0xE8,
2477 2477
24780x00, 0x80, 0x00, 0xE8, 2478 0x00, 0x80, 0x00, 0xE8,
24790x00, 0x80, 0x00, 0xE8, 2479 0x00, 0x80, 0x00, 0xE8,
2480 2480
24810xA0, 0x68, 2481 0xA0, 0x68,
24820xBF, 0x25, 2482 0xBF, 0x25,
24830x00, 0x80, 0x00, 0xE8, 2483 0x00, 0x80, 0x00, 0xE8,
2484 2484
24850x20, 0xC0, 0x20, 0xAF, 2485 0x20, 0xC0, 0x20, 0xAF,
24860x28, 0x05, 2486 0x28, 0x05,
24870x97, 0x74, 2487 0x97, 0x74,
2488 2488
24890x00, 0xE0, 2489 0x00, 0xE0,
24900x2A, 0x10, 2490 0x2A, 0x10,
24910x16, 0xC0, 0x20, 0xE9, 2491 0x16, 0xC0, 0x20, 0xE9,
2492 2492
24930x04, 0x80, 0x10, 0xEA, 2493 0x04, 0x80, 0x10, 0xEA,
24940x8C, 0xE2, 2494 0x8C, 0xE2,
24950x95, 0x05, 2495 0x95, 0x05,
2496 2496
24970x28, 0xC1, 0x28, 0xAD, 2497 0x28, 0xC1, 0x28, 0xAD,
24980x1F, 0xC1, 0x15, 0xBD, 2498 0x1F, 0xC1, 0x15, 0xBD,
2499 2499
25000x00, 0x80, 0x00, 0xE8, 2500 0x00, 0x80, 0x00, 0xE8,
25010x00, 0x80, 0x00, 0xE8, 2501 0x00, 0x80, 0x00, 0xE8,
2502 2502
25030xA8, 0x67, 2503 0xA8, 0x67,
25040x9F, 0x6B, 2504 0x9F, 0x6B,
25050x00, 0x80, 0x00, 0xE8, 2505 0x00, 0x80, 0x00, 0xE8,
2506 2506
25070x28, 0xC0, 0x28, 0xAD, 2507 0x28, 0xC0, 0x28, 0xAD,
25080x1D, 0x25, 2508 0x1D, 0x25,
25090x20, 0x05, 2509 0x20, 0x05,
2510 2510
25110x28, 0x32, 0x80, 0xAD, 2511 0x28, 0x32, 0x80, 0xAD,
25120x40, 0x2A, 0x40, 0xBD, 2512 0x40, 0x2A, 0x40, 0xBD,
2513 2513
25140x1C, 0x80, 0x20, 0xE9, 2514 0x1C, 0x80, 0x20, 0xE9,
25150x20, 0x33, 0x20, 0xAD, 2515 0x20, 0x33, 0x20, 0xAD,
2516 2516
25170x20, 0x73, 2517 0x20, 0x73,
25180x00, 0xE0, 2518 0x00, 0xE0,
25190xB6, 0x49, 0x51, 0xBB, 2519 0xB6, 0x49, 0x51, 0xBB,
2520 2520
25210x26, 0x2F, 0xB0, 0xE8, 2521 0x26, 0x2F, 0xB0, 0xE8,
25220x19, 0x20, 0x20, 0xE9, 2522 0x19, 0x20, 0x20, 0xE9,
2523 2523
25240x35, 0x20, 0x35, 0xDF, 2524 0x35, 0x20, 0x35, 0xDF,
25250x3D, 0x20, 0x3D, 0xDF, 2525 0x3D, 0x20, 0x3D, 0xDF,
2526 2526
25270x15, 0x20, 0x15, 0xDF, 2527 0x15, 0x20, 0x15, 0xDF,
25280x1D, 0x20, 0x1D, 0xDF, 2528 0x1D, 0x20, 0x1D, 0xDF,
2529 2529
25300x26, 0xD0, 0x26, 0xCD, 2530 0x26, 0xD0, 0x26, 0xCD,
25310x29, 0x49, 0x2A, 0xB8, 2531 0x29, 0x49, 0x2A, 0xB8,
2532 2532
25330x26, 0x40, 0x80, 0xBD, 2533 0x26, 0x40, 0x80, 0xBD,
25340x3B, 0x48, 0x50, 0xBD, 2534 0x3B, 0x48, 0x50, 0xBD,
2535 2535
25360x3E, 0x54, 0x57, 0x9F, 2536 0x3E, 0x54, 0x57, 0x9F,
25370x00, 0xE0, 2537 0x00, 0xE0,
25380x82, 0xE1, 2538 0x82, 0xE1,
2539 2539
25400x1E, 0xAF, 0x59, 0x9F, 2540 0x1E, 0xAF, 0x59, 0x9F,
25410x00, 0x80, 0x00, 0xE8, 2541 0x00, 0x80, 0x00, 0xE8,
2542 2542
25430x26, 0x30, 2543 0x26, 0x30,
25440x29, 0x30, 2544 0x29, 0x30,
25450x48, 0x3C, 0x48, 0xAD, 2545 0x48, 0x3C, 0x48, 0xAD,
2546 2546
25470x2B, 0x72, 2547 0x2B, 0x72,
25480xC2, 0xE1, 2548 0xC2, 0xE1,
25490x2C, 0xC0, 0x44, 0xC2, 2549 0x2C, 0xC0, 0x44, 0xC2,
2550 2550
25510x05, 0x24, 0x34, 0xBF, 2551 0x05, 0x24, 0x34, 0xBF,
25520x0D, 0x24, 0x2C, 0xBF, 2552 0x0D, 0x24, 0x2C, 0xBF,
2553 2553
25540x2D, 0x46, 0x4E, 0xBF, 2554 0x2D, 0x46, 0x4E, 0xBF,
25550x25, 0x46, 0x56, 0xBF, 2555 0x25, 0x46, 0x56, 0xBF,
2556 2556
25570x20, 0x1D, 0x6F, 0x8F, 2557 0x20, 0x1D, 0x6F, 0x8F,
25580x32, 0x3E, 0x5F, 0xE9, 2558 0x32, 0x3E, 0x5F, 0xE9,
2559 2559
25600x3E, 0x50, 0x56, 0x9F, 2560 0x3E, 0x50, 0x56, 0x9F,
25610x00, 0xE0, 2561 0x00, 0xE0,
25620x3B, 0x30, 2562 0x3B, 0x30,
2563 2563
25640x1E, 0x8F, 0x51, 0x9F, 2564 0x1E, 0x8F, 0x51, 0x9F,
25650x33, 0x1E, 0x5F, 0xE9, 2565 0x33, 0x1E, 0x5F, 0xE9,
2566 2566
25670x05, 0x44, 0x54, 0xB2, 2567 0x05, 0x44, 0x54, 0xB2,
25680x0D, 0x44, 0x4C, 0xB2, 2568 0x0D, 0x44, 0x4C, 0xB2,
2569 2569
25700x19, 0xC0, 0xB0, 0xE8, 2570 0x19, 0xC0, 0xB0, 0xE8,
25710x34, 0xC0, 0x44, 0xC4, 2571 0x34, 0xC0, 0x44, 0xC4,
2572 2572
25730x33, 0x73, 2573 0x33, 0x73,
25740x00, 0xE0, 2574 0x00, 0xE0,
25750x3E, 0x62, 0x57, 0x9F, 2575 0x3E, 0x62, 0x57, 0x9F,
2576 2576
25770x1E, 0xAF, 0x59, 0x9F, 2577 0x1E, 0xAF, 0x59, 0x9F,
25780x00, 0xE0, 2578 0x00, 0xE0,
25790x0D, 0x20, 2579 0x0D, 0x20,
2580 2580
25810x84, 0x3E, 0x58, 0xE9, 2581 0x84, 0x3E, 0x58, 0xE9,
25820x28, 0x1D, 0x6F, 0x8F, 2582 0x28, 0x1D, 0x6F, 0x8F,
2583 2583
25840x05, 0x20, 2584 0x05, 0x20,
25850x00, 0xE0, 2585 0x00, 0xE0,
25860x85, 0x1E, 0x58, 0xE9, 2586 0x85, 0x1E, 0x58, 0xE9,
2587 2587
25880x9B, 0x3B, 0x33, 0xDF, 2588 0x9B, 0x3B, 0x33, 0xDF,
25890x20, 0x20, 0x42, 0xAF, 2589 0x20, 0x20, 0x42, 0xAF,
2590 2590
25910x30, 0x42, 0x56, 0x9F, 2591 0x30, 0x42, 0x56, 0x9F,
25920x80, 0x3E, 0x57, 0xE9, 2592 0x80, 0x3E, 0x57, 0xE9,
2593 2593
25940x3F, 0x8F, 0x51, 0x9F, 2594 0x3F, 0x8F, 0x51, 0x9F,
25950x30, 0x80, 0x5F, 0xE9, 2595 0x30, 0x80, 0x5F, 0xE9,
2596 2596
25970x28, 0x28, 0x24, 0xAF, 2597 0x28, 0x28, 0x24, 0xAF,
25980x81, 0x1E, 0x57, 0xE9, 2598 0x81, 0x1E, 0x57, 0xE9,
2599 2599
26000x05, 0x47, 0x57, 0xBF, 2600 0x05, 0x47, 0x57, 0xBF,
26010x0D, 0x47, 0x4F, 0xBF, 2601 0x0D, 0x47, 0x4F, 0xBF,
2602 2602
26030x88, 0x80, 0x58, 0xE9, 2603 0x88, 0x80, 0x58, 0xE9,
26040x1B, 0x29, 0x1B, 0xDF, 2604 0x1B, 0x29, 0x1B, 0xDF,
2605 2605
26060x30, 0x1D, 0x6F, 0x8F, 2606 0x30, 0x1D, 0x6F, 0x8F,
26070x3A, 0x30, 0x4F, 0xE9, 2607 0x3A, 0x30, 0x4F, 0xE9,
2608 2608
26090x1C, 0x30, 0x26, 0xDF, 2609 0x1C, 0x30, 0x26, 0xDF,
26100x09, 0xE3, 2610 0x09, 0xE3,
26110x3B, 0x05, 2611 0x3B, 0x05,
2612 2612
26130x3E, 0x50, 0x56, 0x9F, 2613 0x3E, 0x50, 0x56, 0x9F,
26140x3B, 0x3F, 0x4F, 0xE9, 2614 0x3B, 0x3F, 0x4F, 0xE9,
2615 2615
26160x1E, 0x8F, 0x51, 0x9F, 2616 0x1E, 0x8F, 0x51, 0x9F,
26170x00, 0xE0, 2617 0x00, 0xE0,
26180xAC, 0x20, 2618 0xAC, 0x20,
2619 2619
26200x2D, 0x44, 0x4C, 0xB4, 2620 0x2D, 0x44, 0x4C, 0xB4,
26210x2C, 0x1C, 0xC0, 0xAF, 2621 0x2C, 0x1C, 0xC0, 0xAF,
2622 2622
26230x25, 0x44, 0x54, 0xB4, 2623 0x25, 0x44, 0x54, 0xB4,
26240x00, 0xE0, 2624 0x00, 0xE0,
26250xC8, 0x30, 2625 0xC8, 0x30,
2626 2626
26270x30, 0x46, 0x30, 0xAF, 2627 0x30, 0x46, 0x30, 0xAF,
26280x1B, 0x1B, 0x48, 0xAF, 2628 0x1B, 0x1B, 0x48, 0xAF,
2629 2629
26300x00, 0xE0, 2630 0x00, 0xE0,
26310x25, 0x20, 2631 0x25, 0x20,
26320x38, 0x2C, 0x4F, 0xE9, 2632 0x38, 0x2C, 0x4F, 0xE9,
2633 2633
26340x86, 0x80, 0x57, 0xE9, 2634 0x86, 0x80, 0x57, 0xE9,
26350x38, 0x1D, 0x6F, 0x8F, 2635 0x38, 0x1D, 0x6F, 0x8F,
2636 2636
26370x28, 0x74, 2637 0x28, 0x74,
26380x00, 0xE0, 2638 0x00, 0xE0,
26390x0D, 0x44, 0x4C, 0xB0, 2639 0x0D, 0x44, 0x4C, 0xB0,
2640 2640
26410x05, 0x44, 0x54, 0xB0, 2641 0x05, 0x44, 0x54, 0xB0,
26420x2D, 0x20, 2642 0x2D, 0x20,
26430x9B, 0x10, 2643 0x9B, 0x10,
2644 2644
26450x82, 0x3E, 0x57, 0xE9, 2645 0x82, 0x3E, 0x57, 0xE9,
26460x32, 0xF0, 0x1B, 0xCD, 2646 0x32, 0xF0, 0x1B, 0xCD,
2647 2647
26480x1E, 0xBD, 0x59, 0x9F, 2648 0x1E, 0xBD, 0x59, 0x9F,
26490x83, 0x1E, 0x57, 0xE9, 2649 0x83, 0x1E, 0x57, 0xE9,
2650 2650
26510x38, 0x47, 0x38, 0xAF, 2651 0x38, 0x47, 0x38, 0xAF,
26520x34, 0x20, 2652 0x34, 0x20,
26530x2A, 0x30, 2653 0x2A, 0x30,
2654 2654
26550x00, 0xE0, 2655 0x00, 0xE0,
26560x0D, 0x20, 2656 0x0D, 0x20,
26570x32, 0x20, 2657 0x32, 0x20,
26580x05, 0x20, 2658 0x05, 0x20,
2659 2659
26600x87, 0x80, 0x57, 0xE9, 2660 0x87, 0x80, 0x57, 0xE9,
26610x1F, 0x54, 0x57, 0x9F, 2661 0x1F, 0x54, 0x57, 0x9F,
2662 2662
26630x17, 0x42, 0x56, 0x9F, 2663 0x17, 0x42, 0x56, 0x9F,
26640x00, 0xE0, 2664 0x00, 0xE0,
26650x3B, 0x6A, 2665 0x3B, 0x6A,
2666 2666
26670x3F, 0x8F, 0x51, 0x9F, 2667 0x3F, 0x8F, 0x51, 0x9F,
26680x37, 0x1E, 0x4F, 0xE9, 2668 0x37, 0x1E, 0x4F, 0xE9,
2669 2669
26700x37, 0x32, 0x2A, 0xAF, 2670 0x37, 0x32, 0x2A, 0xAF,
26710x00, 0xE0, 2671 0x00, 0xE0,
26720x32, 0x00, 2672 0x32, 0x00,
2673 2673
26740x00, 0x80, 0x00, 0xE8, 2674 0x00, 0x80, 0x00, 0xE8,
26750x27, 0xC0, 0x44, 0xC0, 2675 0x27, 0xC0, 0x44, 0xC0,
2676 2676
26770x36, 0x1F, 0x4F, 0xE9, 2677 0x36, 0x1F, 0x4F, 0xE9,
26780x1F, 0x1F, 0x26, 0xDF, 2678 0x1F, 0x1F, 0x26, 0xDF,
2679 2679
26800x37, 0x1B, 0x37, 0xBF, 2680 0x37, 0x1B, 0x37, 0xBF,
26810x17, 0x26, 0x17, 0xDF, 2681 0x17, 0x26, 0x17, 0xDF,
2682 2682
26830x3E, 0x17, 0x4F, 0xE9, 2683 0x3E, 0x17, 0x4F, 0xE9,
26840x3F, 0x3F, 0x4F, 0xE9, 2684 0x3F, 0x3F, 0x4F, 0xE9,
2685 2685
26860x34, 0x1F, 0x34, 0xAF, 2686 0x34, 0x1F, 0x34, 0xAF,
26870x2B, 0x05, 2687 0x2B, 0x05,
26880xA7, 0x20, 2688 0xA7, 0x20,
2689 2689
26900x33, 0x2B, 0x37, 0xDF, 2690 0x33, 0x2B, 0x37, 0xDF,
26910x27, 0x17, 0xC0, 0xAF, 2691 0x27, 0x17, 0xC0, 0xAF,
2692 2692
26930x34, 0x80, 0x4F, 0xE9, 2693 0x34, 0x80, 0x4F, 0xE9,
26940x00, 0x80, 0x00, 0xE8, 2694 0x00, 0x80, 0x00, 0xE8,
2695 2695
26960x2D, 0x21, 0x1A, 0xB0, 2696 0x2D, 0x21, 0x1A, 0xB0,
26970x25, 0x21, 0x31, 0xB0, 2697 0x25, 0x21, 0x31, 0xB0,
2698 2698
26990x0D, 0x21, 0x1A, 0xB2, 2699 0x0D, 0x21, 0x1A, 0xB2,
27000x05, 0x21, 0x31, 0xB2, 2700 0x05, 0x21, 0x31, 0xB2,
2701 2701
27020x03, 0x80, 0x2A, 0xEA, 2702 0x03, 0x80, 0x2A, 0xEA,
27030x17, 0xC1, 0x2B, 0xBD, 2703 0x17, 0xC1, 0x2B, 0xBD,
2704 2704
27050x2D, 0x20, 2705 0x2D, 0x20,
27060x25, 0x20, 2706 0x25, 0x20,
27070x05, 0x20, 2707 0x05, 0x20,
27080x0D, 0x20, 2708 0x0D, 0x20,
2709 2709
27100xB3, 0x68, 2710 0xB3, 0x68,
27110x97, 0x25, 2711 0x97, 0x25,
27120x00, 0x80, 0x00, 0xE8, 2712 0x00, 0x80, 0x00, 0xE8,
2713 2713
27140x33, 0xC0, 0x33, 0xAF, 2714 0x33, 0xC0, 0x33, 0xAF,
27150x2F, 0xC0, 0x21, 0xC0, 2715 0x2F, 0xC0, 0x21, 0xC0,
2716 2716
27170x16, 0x42, 0x56, 0x9F, 2717 0x16, 0x42, 0x56, 0x9F,
27180x3C, 0x27, 0x4F, 0xE9, 2718 0x3C, 0x27, 0x4F, 0xE9,
2719 2719
27200x1E, 0x62, 0x57, 0x9F, 2720 0x1E, 0x62, 0x57, 0x9F,
27210x00, 0x80, 0x00, 0xE8, 2721 0x00, 0x80, 0x00, 0xE8,
2722 2722
27230x25, 0x21, 0x31, 0xB4, 2723 0x25, 0x21, 0x31, 0xB4,
27240x2D, 0x21, 0x1A, 0xB4, 2724 0x2D, 0x21, 0x1A, 0xB4,
2725 2725
27260x3F, 0x2F, 0x5D, 0x9F, 2726 0x3F, 0x2F, 0x5D, 0x9F,
27270x00, 0x80, 0x00, 0xE8, 2727 0x00, 0x80, 0x00, 0xE8,
2728 2728
27290x33, 0x05, 2729 0x33, 0x05,
27300x00, 0xE0, 2730 0x00, 0xE0,
27310x28, 0x19, 0x60, 0xEC, 2731 0x28, 0x19, 0x60, 0xEC,
2732 2732
27330x37, 0x0F, 0x5C, 0x9F, 2733 0x37, 0x0F, 0x5C, 0x9F,
27340x00, 0xE0, 2734 0x00, 0xE0,
27350x2F, 0x20, 2735 0x2F, 0x20,
2736 2736
27370x23, 0x3B, 0x33, 0xAD, 2737 0x23, 0x3B, 0x33, 0xAD,
27380x1E, 0x26, 0x1E, 0xDF, 2738 0x1E, 0x26, 0x1E, 0xDF,
2739 2739
27400xA7, 0x1E, 0x4F, 0xE9, 2740 0xA7, 0x1E, 0x4F, 0xE9,
27410x17, 0x26, 0x16, 0xDF, 2741 0x17, 0x26, 0x16, 0xDF,
2742 2742
27430x2D, 0x20, 2743 0x2D, 0x20,
27440x00, 0xE0, 2744 0x00, 0xE0,
27450xA8, 0x3F, 0x4F, 0xE9, 2745 0xA8, 0x3F, 0x4F, 0xE9,
2746 2746
27470x2F, 0x2F, 0x1E, 0xAF, 2747 0x2F, 0x2F, 0x1E, 0xAF,
27480x25, 0x20, 2748 0x25, 0x20,
27490x00, 0xE0, 2749 0x00, 0xE0,
2750 2750
27510xA4, 0x16, 0x4F, 0xE9, 2751 0xA4, 0x16, 0x4F, 0xE9,
27520x0F, 0xC0, 0x21, 0xC2, 2752 0x0F, 0xC0, 0x21, 0xC2,
2753 2753
27540xA6, 0x80, 0x4F, 0xE9, 2754 0xA6, 0x80, 0x4F, 0xE9,
27550x1F, 0x62, 0x57, 0x9F, 2755 0x1F, 0x62, 0x57, 0x9F,
2756 2756
27570x3F, 0x2F, 0x5D, 0x9F, 2757 0x3F, 0x2F, 0x5D, 0x9F,
27580x00, 0xE0, 2758 0x00, 0xE0,
27590x8F, 0x20, 2759 0x8F, 0x20,
2760 2760
27610xA5, 0x37, 0x4F, 0xE9, 2761 0xA5, 0x37, 0x4F, 0xE9,
27620x0F, 0x17, 0x0F, 0xAF, 2762 0x0F, 0x17, 0x0F, 0xAF,
2763 2763
27640x06, 0xC0, 0x21, 0xC4, 2764 0x06, 0xC0, 0x21, 0xC4,
27650x00, 0x80, 0x00, 0xE8, 2765 0x00, 0x80, 0x00, 0xE8,
2766 2766
27670x00, 0x80, 0x00, 0xE8, 2767 0x00, 0x80, 0x00, 0xE8,
27680xA3, 0x80, 0x4F, 0xE9, 2768 0xA3, 0x80, 0x4F, 0xE9,
2769 2769
27700x06, 0x20, 2770 0x06, 0x20,
27710x00, 0xE0, 2771 0x00, 0xE0,
27720x1F, 0x26, 0x1F, 0xDF, 2772 0x1F, 0x26, 0x1F, 0xDF,
2773 2773
27740xA1, 0x1F, 0x4F, 0xE9, 2774 0xA1, 0x1F, 0x4F, 0xE9,
27750xA2, 0x3F, 0x4F, 0xE9, 2775 0xA2, 0x3F, 0x4F, 0xE9,
2776 2776
27770x00, 0x80, 0x00, 0xE8, 2777 0x00, 0x80, 0x00, 0xE8,
27780x00, 0x80, 0x00, 0xE8, 2778 0x00, 0x80, 0x00, 0xE8,
2779 2779
27800x06, 0x06, 0x1F, 0xAF, 2780 0x06, 0x06, 0x1F, 0xAF,
27810x00, 0x80, 0x00, 0xE8, 2781 0x00, 0x80, 0x00, 0xE8,
2782 2782
27830x00, 0x80, 0x00, 0xE8, 2783 0x00, 0x80, 0x00, 0xE8,
27840x00, 0x80, 0x00, 0xE8, 2784 0x00, 0x80, 0x00, 0xE8,
2785 2785
27860xA0, 0x80, 0x4F, 0xE9, 2786 0xA0, 0x80, 0x4F, 0xE9,
27870x00, 0x80, 0x00, 0xE8, 2787 0x00, 0x80, 0x00, 0xE8,
2788 2788
27890x00, 0x80, 0x00, 0xE8, 2789 0x00, 0x80, 0x00, 0xE8,
27900x57, 0x39, 0x20, 0xE9, 2790 0x57, 0x39, 0x20, 0xE9,
2791 2791
27920x16, 0x28, 0x20, 0xE9, 2792 0x16, 0x28, 0x20, 0xE9,
27930x1D, 0x3B, 0x20, 0xE9, 2793 0x1D, 0x3B, 0x20, 0xE9,
2794 2794
27950x1E, 0x2B, 0x20, 0xE9, 2795 0x1E, 0x2B, 0x20, 0xE9,
27960x2B, 0x32, 0x20, 0xE9, 2796 0x2B, 0x32, 0x20, 0xE9,
2797 2797
27980x1C, 0x23, 0x20, 0xE9, 2798 0x1C, 0x23, 0x20, 0xE9,
27990x57, 0x36, 0x20, 0xE9, 2799 0x57, 0x36, 0x20, 0xE9,
2800 2800
28010x00, 0x80, 0xA0, 0xE9, 2801 0x00, 0x80, 0xA0, 0xE9,
28020x40, 0x40, 0xD8, 0xEC, 2802 0x40, 0x40, 0xD8, 0xEC,
2803 2803
28040xFF, 0x80, 0xC0, 0xE9, 2804 0xFF, 0x80, 0xC0, 0xE9,
28050x90, 0xE2, 2805 0x90, 0xE2,
28060x00, 0xE0, 2806 0x00, 0xE0,
2807 2807
28080x6C, 0xFF, 0x20, 0xEA, 2808 0x6C, 0xFF, 0x20, 0xEA,
28090x19, 0xC8, 0xC1, 0xCD, 2809 0x19, 0xC8, 0xC1, 0xCD,
2810 2810
28110x1F, 0xD7, 0x18, 0xBD, 2811 0x1F, 0xD7, 0x18, 0xBD,
28120x3F, 0xD7, 0x22, 0xBD, 2812 0x3F, 0xD7, 0x22, 0xBD,
2813 2813
28140x9F, 0x41, 0x49, 0xBD, 2814 0x9F, 0x41, 0x49, 0xBD,
28150x00, 0x80, 0x00, 0xE8, 2815 0x00, 0x80, 0x00, 0xE8,
2816 2816
28170x25, 0x41, 0x49, 0xBD, 2817 0x25, 0x41, 0x49, 0xBD,
28180x2D, 0x41, 0x51, 0xBD, 2818 0x2D, 0x41, 0x51, 0xBD,
2819 2819
28200x0D, 0x80, 0x07, 0xEA, 2820 0x0D, 0x80, 0x07, 0xEA,
28210x00, 0x80, 0x00, 0xE8, 2821 0x00, 0x80, 0x00, 0xE8,
2822 2822
28230x35, 0x40, 0x48, 0xBD, 2823 0x35, 0x40, 0x48, 0xBD,
28240x3D, 0x40, 0x50, 0xBD, 2824 0x3D, 0x40, 0x50, 0xBD,
2825 2825
28260x00, 0x80, 0x00, 0xE8, 2826 0x00, 0x80, 0x00, 0xE8,
28270x25, 0x30, 2827 0x25, 0x30,
28280x2D, 0x30, 2828 0x2D, 0x30,
2829 2829
28300x35, 0x30, 2830 0x35, 0x30,
28310xB5, 0x30, 2831 0xB5, 0x30,
28320xBD, 0x30, 2832 0xBD, 0x30,
28330x3D, 0x30, 2833 0x3D, 0x30,
2834 2834
28350x9C, 0xA7, 0x5B, 0x9F, 2835 0x9C, 0xA7, 0x5B, 0x9F,
28360x00, 0x80, 0x00, 0xE8, 2836 0x00, 0x80, 0x00, 0xE8,
2837 2837
28380x00, 0x80, 0x00, 0xE8, 2838 0x00, 0x80, 0x00, 0xE8,
28390x00, 0x80, 0x00, 0xE8, 2839 0x00, 0x80, 0x00, 0xE8,
2840 2840
28410x00, 0x80, 0x00, 0xE8, 2841 0x00, 0x80, 0x00, 0xE8,
28420x00, 0x80, 0x00, 0xE8, 2842 0x00, 0x80, 0x00, 0xE8,
2843 2843
28440x00, 0x80, 0x00, 0xE8, 2844 0x00, 0x80, 0x00, 0xE8,
28450x00, 0x80, 0x00, 0xE8, 2845 0x00, 0x80, 0x00, 0xE8,
2846 2846
28470x00, 0x80, 0x00, 0xE8, 2847 0x00, 0x80, 0x00, 0xE8,
28480x00, 0x80, 0x00, 0xE8, 2848 0x00, 0x80, 0x00, 0xE8,
2849 2849
28500x6B, 0xFF, 0x0A, 0xEA, 2850 0x6B, 0xFF, 0x0A, 0xEA,
28510x00, 0x80, 0x00, 0xE8, 2851 0x00, 0x80, 0x00, 0xE8,
2852 2852
28530xC9, 0x41, 0xC8, 0xEC, 2853 0xC9, 0x41, 0xC8, 0xEC,
28540x42, 0xE1, 2854 0x42, 0xE1,
28550x00, 0xE0, 2855 0x00, 0xE0,
2856 2856
28570x69, 0xFF, 0x20, 0xEA, 2857 0x69, 0xFF, 0x20, 0xEA,
28580x00, 0x80, 0x00, 0xE8, 2858 0x00, 0x80, 0x00, 0xE8,
2859 2859
28600x00, 0x80, 0x00, 0xE8, 2860 0x00, 0x80, 0x00, 0xE8,
28610x00, 0x80, 0x00, 0xE8, 2861 0x00, 0x80, 0x00, 0xE8,
2862 2862
28630xC8, 0x40, 0xC0, 0xEC, 2863 0xC8, 0x40, 0xC0, 0xEC,
28640x00, 0x80, 0x00, 0xE8, 2864 0x00, 0x80, 0x00, 0xE8,
2865 2865
28660x66, 0xFF, 0x20, 0xEA, 2866 0x66, 0xFF, 0x20, 0xEA,
28670x00, 0x80, 0x00, 0xE8, 2867 0x00, 0x80, 0x00, 0xE8,
2868 2868
28690x00, 0x80, 0x00, 0xE8, 2869 0x00, 0x80, 0x00, 0xE8,
28700x00, 0x80, 0x00, 0xE8, 2870 0x00, 0x80, 0x00, 0xE8,
2871 2871
2872}; 2872};
2873 2873
2874static unsigned char warp_g200_tgzsa[] = { 2874static unsigned char warp_g200_tgzsa[] = {
2875 2875
28760x00, 0x80, 0x00, 0xE8, 2876 0x00, 0x80, 0x00, 0xE8,
28770x00, 0x80, 0x00, 0xE8, 2877 0x00, 0x80, 0x00, 0xE8,
2878 2878
28790x00, 0x80, 0x00, 0xE8, 2879 0x00, 0x80, 0x00, 0xE8,
28800x00, 0x80, 0x00, 0xE8, 2880 0x00, 0x80, 0x00, 0xE8,
2881 2881
28820x00, 0x80, 0x00, 0xE8, 2882 0x00, 0x80, 0x00, 0xE8,
28830x00, 0x80, 0x00, 0xE8, 2883 0x00, 0x80, 0x00, 0xE8,
2884 2884
28850x00, 0x80, 0x00, 0xE8, 2885 0x00, 0x80, 0x00, 0xE8,
28860x00, 0x80, 0x00, 0xE8, 2886 0x00, 0x80, 0x00, 0xE8,
2887 2887
28880x00, 0x80, 0x00, 0xE8, 2888 0x00, 0x80, 0x00, 0xE8,
28890x00, 0x80, 0x00, 0xE8, 2889 0x00, 0x80, 0x00, 0xE8,
2890 2890
28910x00, 0x80, 0x00, 0xE8, 2891 0x00, 0x80, 0x00, 0xE8,
28920x00, 0x80, 0x00, 0xE8, 2892 0x00, 0x80, 0x00, 0xE8,
2893 2893
28940x00, 0x80, 0x00, 0xE8, 2894 0x00, 0x80, 0x00, 0xE8,
28950x00, 0x80, 0x00, 0xE8, 2895 0x00, 0x80, 0x00, 0xE8,
2896 2896
28970x00, 0x80, 0x00, 0xE8, 2897 0x00, 0x80, 0x00, 0xE8,
28980x00, 0x80, 0x00, 0xE8, 2898 0x00, 0x80, 0x00, 0xE8,
2899 2899
29000x00, 0x80, 0x00, 0xE8, 2900 0x00, 0x80, 0x00, 0xE8,
29010x00, 0x80, 0x00, 0xE8, 2901 0x00, 0x80, 0x00, 0xE8,
2902 2902
29030x00, 0x80, 0x00, 0xE8, 2903 0x00, 0x80, 0x00, 0xE8,
29040x00, 0x80, 0x00, 0xE8, 2904 0x00, 0x80, 0x00, 0xE8,
2905 2905
29060x00, 0x80, 0x00, 0xE8, 2906 0x00, 0x80, 0x00, 0xE8,
29070x00, 0x80, 0x00, 0xE8, 2907 0x00, 0x80, 0x00, 0xE8,
2908 2908
29090x00, 0x80, 0x00, 0xE8, 2909 0x00, 0x80, 0x00, 0xE8,
29100x00, 0x80, 0x00, 0xE8, 2910 0x00, 0x80, 0x00, 0xE8,
2911 2911
29120x00, 0x80, 0x00, 0xE8, 2912 0x00, 0x80, 0x00, 0xE8,
29130x00, 0x80, 0x00, 0xE8, 2913 0x00, 0x80, 0x00, 0xE8,
2914 2914
29150x00, 0x98, 0xA0, 0xE9, 2915 0x00, 0x98, 0xA0, 0xE9,
29160x40, 0x40, 0xD8, 0xEC, 2916 0x40, 0x40, 0xD8, 0xEC,
2917 2917
29180xFF, 0x80, 0xC0, 0xE9, 2918 0xFF, 0x80, 0xC0, 0xE9,
29190x00, 0x80, 0x00, 0xE8, 2919 0x00, 0x80, 0x00, 0xE8,
2920 2920
29210x1F, 0xD7, 0x18, 0xBD, 2921 0x1F, 0xD7, 0x18, 0xBD,
29220x3F, 0xD7, 0x22, 0xBD, 2922 0x3F, 0xD7, 0x22, 0xBD,
2923 2923
29240x81, 0x04, 2924 0x81, 0x04,
29250x89, 0x04, 2925 0x89, 0x04,
29260x01, 0x04, 2926 0x01, 0x04,
29270x09, 0x04, 2927 0x09, 0x04,
2928 2928
29290xC9, 0x41, 0xC0, 0xEC, 2929 0xC9, 0x41, 0xC0, 0xEC,
29300x11, 0x04, 2930 0x11, 0x04,
29310x00, 0xE0, 2931 0x00, 0xE0,
2932 2932
29330x41, 0xCC, 0x41, 0xCD, 2933 0x41, 0xCC, 0x41, 0xCD,
29340x49, 0xCC, 0x49, 0xCD, 2934 0x49, 0xCC, 0x49, 0xCD,
2935 2935
29360xD1, 0x41, 0xC0, 0xEC, 2936 0xD1, 0x41, 0xC0, 0xEC,
29370x51, 0xCC, 0x51, 0xCD, 2937 0x51, 0xCC, 0x51, 0xCD,
2938 2938
29390x80, 0x04, 2939 0x80, 0x04,
29400x10, 0x04, 2940 0x10, 0x04,
29410x08, 0x04, 2941 0x08, 0x04,
29420x00, 0xE0, 2942 0x00, 0xE0,
2943 2943
29440x00, 0xCC, 0xC0, 0xCD, 2944 0x00, 0xCC, 0xC0, 0xCD,
29450xD1, 0x49, 0xC0, 0xEC, 2945 0xD1, 0x49, 0xC0, 0xEC,
2946 2946
29470x8A, 0x1F, 0x20, 0xE9, 2947 0x8A, 0x1F, 0x20, 0xE9,
29480x8B, 0x3F, 0x20, 0xE9, 2948 0x8B, 0x3F, 0x20, 0xE9,
2949 2949
29500x41, 0x3C, 0x41, 0xAD, 2950 0x41, 0x3C, 0x41, 0xAD,
29510x49, 0x3C, 0x49, 0xAD, 2951 0x49, 0x3C, 0x49, 0xAD,
2952 2952
29530x10, 0xCC, 0x10, 0xCD, 2953 0x10, 0xCC, 0x10, 0xCD,
29540x08, 0xCC, 0x08, 0xCD, 2954 0x08, 0xCC, 0x08, 0xCD,
2955 2955
29560xB9, 0x41, 0x49, 0xBB, 2956 0xB9, 0x41, 0x49, 0xBB,
29570x1F, 0xF0, 0x41, 0xCD, 2957 0x1F, 0xF0, 0x41, 0xCD,
2958 2958
29590x51, 0x3C, 0x51, 0xAD, 2959 0x51, 0x3C, 0x51, 0xAD,
29600x00, 0x98, 0x80, 0xE9, 2960 0x00, 0x98, 0x80, 0xE9,
2961 2961
29620x8F, 0x80, 0x07, 0xEA, 2962 0x8F, 0x80, 0x07, 0xEA,
29630x24, 0x1F, 0x20, 0xE9, 2963 0x24, 0x1F, 0x20, 0xE9,
2964 2964
29650x21, 0x45, 0x80, 0xE8, 2965 0x21, 0x45, 0x80, 0xE8,
29660x1A, 0x4D, 0x80, 0xE8, 2966 0x1A, 0x4D, 0x80, 0xE8,
2967 2967
29680x31, 0x55, 0x80, 0xE8, 2968 0x31, 0x55, 0x80, 0xE8,
29690x00, 0x80, 0x00, 0xE8, 2969 0x00, 0x80, 0x00, 0xE8,
2970 2970
29710x15, 0x41, 0x49, 0xBD, 2971 0x15, 0x41, 0x49, 0xBD,
29720x1D, 0x41, 0x51, 0xBD, 2972 0x1D, 0x41, 0x51, 0xBD,
2973 2973
29740x2E, 0x41, 0x2A, 0xB8, 2974 0x2E, 0x41, 0x2A, 0xB8,
29750x34, 0x53, 0xA0, 0xE8, 2975 0x34, 0x53, 0xA0, 0xE8,
2976 2976
29770x15, 0x30, 2977 0x15, 0x30,
29780x1D, 0x30, 2978 0x1D, 0x30,
29790x58, 0xE3, 2979 0x58, 0xE3,
29800x00, 0xE0, 2980 0x00, 0xE0,
2981 2981
29820xB5, 0x40, 0x48, 0xBD, 2982 0xB5, 0x40, 0x48, 0xBD,
29830x3D, 0x40, 0x50, 0xBD, 2983 0x3D, 0x40, 0x50, 0xBD,
2984 2984
29850x24, 0x43, 0xA0, 0xE8, 2985 0x24, 0x43, 0xA0, 0xE8,
29860x2C, 0x4B, 0xA0, 0xE8, 2986 0x2C, 0x4B, 0xA0, 0xE8,
2987 2987
29880x15, 0x72, 2988 0x15, 0x72,
29890x09, 0xE3, 2989 0x09, 0xE3,
29900x00, 0xE0, 2990 0x00, 0xE0,
29910x1D, 0x72, 2991 0x1D, 0x72,
2992 2992
29930x35, 0x30, 2993 0x35, 0x30,
29940xB5, 0x30, 2994 0xB5, 0x30,
29950xBD, 0x30, 2995 0xBD, 0x30,
29960x3D, 0x30, 2996 0x3D, 0x30,
2997 2997
29980x9C, 0x97, 0x57, 0x9F, 2998 0x9C, 0x97, 0x57, 0x9F,
29990x00, 0x80, 0x00, 0xE8, 2999 0x00, 0x80, 0x00, 0xE8,
3000 3000
30010x6C, 0x64, 0xC8, 0xEC, 3001 0x6C, 0x64, 0xC8, 0xEC,
30020x98, 0xE1, 3002 0x98, 0xE1,
30030xB5, 0x05, 3003 0xB5, 0x05,
3004 3004
30050xBD, 0x05, 3005 0xBD, 0x05,
30060x2E, 0x30, 3006 0x2E, 0x30,
30070x32, 0xC0, 0xA0, 0xE8, 3007 0x32, 0xC0, 0xA0, 0xE8,
3008 3008
30090x33, 0xC0, 0xA0, 0xE8, 3009 0x33, 0xC0, 0xA0, 0xE8,
30100x74, 0x64, 0xC8, 0xEC, 3010 0x74, 0x64, 0xC8, 0xEC,
3011 3011
30120x40, 0x3C, 0x40, 0xAD, 3012 0x40, 0x3C, 0x40, 0xAD,
30130x32, 0x6A, 3013 0x32, 0x6A,
30140x2A, 0x30, 3014 0x2A, 0x30,
3015 3015
30160x20, 0x73, 3016 0x20, 0x73,
30170x33, 0x6A, 3017 0x33, 0x6A,
30180x00, 0xE0, 3018 0x00, 0xE0,
30190x28, 0x73, 3019 0x28, 0x73,
3020 3020
30210x1C, 0x72, 3021 0x1C, 0x72,
30220x83, 0xE2, 3022 0x83, 0xE2,
30230x7B, 0x80, 0x15, 0xEA, 3023 0x7B, 0x80, 0x15, 0xEA,
3024 3024
30250xB8, 0x3D, 0x28, 0xDF, 3025 0xB8, 0x3D, 0x28, 0xDF,
30260x30, 0x35, 0x20, 0xDF, 3026 0x30, 0x35, 0x20, 0xDF,
3027 3027
30280x40, 0x30, 3028 0x40, 0x30,
30290x00, 0xE0, 3029 0x00, 0xE0,
30300xCC, 0xE2, 3030 0xCC, 0xE2,
30310x64, 0x72, 3031 0x64, 0x72,
3032 3032
30330x25, 0x42, 0x52, 0xBF, 3033 0x25, 0x42, 0x52, 0xBF,
30340x2D, 0x42, 0x4A, 0xBF, 3034 0x2D, 0x42, 0x4A, 0xBF,
3035 3035
30360x30, 0x2E, 0x30, 0xDF, 3036 0x30, 0x2E, 0x30, 0xDF,
30370x38, 0x2E, 0x38, 0xDF, 3037 0x38, 0x2E, 0x38, 0xDF,
3038 3038
30390x18, 0x1D, 0x45, 0xE9, 3039 0x18, 0x1D, 0x45, 0xE9,
30400x1E, 0x15, 0x45, 0xE9, 3040 0x1E, 0x15, 0x45, 0xE9,
3041 3041
30420x2B, 0x49, 0x51, 0xBD, 3042 0x2B, 0x49, 0x51, 0xBD,
30430x00, 0xE0, 3043 0x00, 0xE0,
30440x1F, 0x73, 3044 0x1F, 0x73,
3045 3045
30460x38, 0x38, 0x40, 0xAF, 3046 0x38, 0x38, 0x40, 0xAF,
30470x30, 0x30, 0x40, 0xAF, 3047 0x30, 0x30, 0x40, 0xAF,
3048 3048
30490x24, 0x1F, 0x24, 0xDF, 3049 0x24, 0x1F, 0x24, 0xDF,
30500x1D, 0x32, 0x20, 0xE9, 3050 0x1D, 0x32, 0x20, 0xE9,
3051 3051
30520x2C, 0x1F, 0x2C, 0xDF, 3052 0x2C, 0x1F, 0x2C, 0xDF,
30530x1A, 0x33, 0x20, 0xE9, 3053 0x1A, 0x33, 0x20, 0xE9,
3054 3054
30550xB0, 0x10, 3055 0xB0, 0x10,
30560x08, 0xE3, 3056 0x08, 0xE3,
30570x40, 0x10, 3057 0x40, 0x10,
30580xB8, 0x10, 3058 0xB8, 0x10,
3059 3059
30600x26, 0xF0, 0x30, 0xCD, 3060 0x26, 0xF0, 0x30, 0xCD,
30610x2F, 0xF0, 0x38, 0xCD, 3061 0x2F, 0xF0, 0x38, 0xCD,
3062 3062
30630x2B, 0x80, 0x20, 0xE9, 3063 0x2B, 0x80, 0x20, 0xE9,
30640x2A, 0x80, 0x20, 0xE9, 3064 0x2A, 0x80, 0x20, 0xE9,
3065 3065
30660xA6, 0x20, 3066 0xA6, 0x20,
30670x88, 0xE2, 3067 0x88, 0xE2,
30680x00, 0xE0, 3068 0x00, 0xE0,
30690xAF, 0x20, 3069 0xAF, 0x20,
3070 3070
30710x28, 0x2A, 0x26, 0xAF, 3071 0x28, 0x2A, 0x26, 0xAF,
30720x20, 0x2A, 0xC0, 0xAF, 3072 0x20, 0x2A, 0xC0, 0xAF,
3073 3073
30740x34, 0x1F, 0x34, 0xDF, 3074 0x34, 0x1F, 0x34, 0xDF,
30750x46, 0x24, 0x46, 0xDF, 3075 0x46, 0x24, 0x46, 0xDF,
3076 3076
30770x28, 0x30, 0x80, 0xBF, 3077 0x28, 0x30, 0x80, 0xBF,
30780x20, 0x38, 0x80, 0xBF, 3078 0x20, 0x38, 0x80, 0xBF,
3079 3079
30800x47, 0x24, 0x47, 0xDF, 3080 0x47, 0x24, 0x47, 0xDF,
30810x4E, 0x2C, 0x4E, 0xDF, 3081 0x4E, 0x2C, 0x4E, 0xDF,
3082 3082
30830x4F, 0x2C, 0x4F, 0xDF, 3083 0x4F, 0x2C, 0x4F, 0xDF,
30840x56, 0x34, 0x56, 0xDF, 3084 0x56, 0x34, 0x56, 0xDF,
3085 3085
30860x28, 0x15, 0x28, 0xDF, 3086 0x28, 0x15, 0x28, 0xDF,
30870x20, 0x1D, 0x20, 0xDF, 3087 0x20, 0x1D, 0x20, 0xDF,
3088 3088
30890x57, 0x34, 0x57, 0xDF, 3089 0x57, 0x34, 0x57, 0xDF,
30900x00, 0xE0, 3090 0x00, 0xE0,
30910x1D, 0x05, 3091 0x1D, 0x05,
3092 3092
30930x04, 0x80, 0x10, 0xEA, 3093 0x04, 0x80, 0x10, 0xEA,
30940x89, 0xE2, 3094 0x89, 0xE2,
30950x2B, 0x30, 3095 0x2B, 0x30,
3096 3096
30970x3F, 0xC1, 0x1D, 0xBD, 3097 0x3F, 0xC1, 0x1D, 0xBD,
30980x00, 0x80, 0x00, 0xE8, 3098 0x00, 0x80, 0x00, 0xE8,
3099 3099
31000x00, 0x80, 0x00, 0xE8, 3100 0x00, 0x80, 0x00, 0xE8,
31010x00, 0x80, 0x00, 0xE8, 3101 0x00, 0x80, 0x00, 0xE8,
3102 3102
31030xA0, 0x68, 3103 0xA0, 0x68,
31040xBF, 0x25, 3104 0xBF, 0x25,
31050x00, 0x80, 0x00, 0xE8, 3105 0x00, 0x80, 0x00, 0xE8,
3106 3106
31070x20, 0xC0, 0x20, 0xAF, 3107 0x20, 0xC0, 0x20, 0xAF,
31080x28, 0x05, 3108 0x28, 0x05,
31090x97, 0x74, 3109 0x97, 0x74,
3110 3110
31110x00, 0xE0, 3111 0x00, 0xE0,
31120x2A, 0x10, 3112 0x2A, 0x10,
31130x16, 0xC0, 0x20, 0xE9, 3113 0x16, 0xC0, 0x20, 0xE9,
3114 3114
31150x04, 0x80, 0x10, 0xEA, 3115 0x04, 0x80, 0x10, 0xEA,
31160x8C, 0xE2, 3116 0x8C, 0xE2,
31170x95, 0x05, 3117 0x95, 0x05,
3118 3118
31190x28, 0xC1, 0x28, 0xAD, 3119 0x28, 0xC1, 0x28, 0xAD,
31200x1F, 0xC1, 0x15, 0xBD, 3120 0x1F, 0xC1, 0x15, 0xBD,
3121 3121
31220x00, 0x80, 0x00, 0xE8, 3122 0x00, 0x80, 0x00, 0xE8,
31230x00, 0x80, 0x00, 0xE8, 3123 0x00, 0x80, 0x00, 0xE8,
3124 3124
31250xA8, 0x67, 3125 0xA8, 0x67,
31260x9F, 0x6B, 3126 0x9F, 0x6B,
31270x00, 0x80, 0x00, 0xE8, 3127 0x00, 0x80, 0x00, 0xE8,
3128 3128
31290x28, 0xC0, 0x28, 0xAD, 3129 0x28, 0xC0, 0x28, 0xAD,
31300x1D, 0x25, 3130 0x1D, 0x25,
31310x20, 0x05, 3131 0x20, 0x05,
3132 3132
31330x28, 0x32, 0x80, 0xAD, 3133 0x28, 0x32, 0x80, 0xAD,
31340x40, 0x2A, 0x40, 0xBD, 3134 0x40, 0x2A, 0x40, 0xBD,
3135 3135
31360x1C, 0x80, 0x20, 0xE9, 3136 0x1C, 0x80, 0x20, 0xE9,
31370x20, 0x33, 0x20, 0xAD, 3137 0x20, 0x33, 0x20, 0xAD,
3138 3138
31390x20, 0x73, 3139 0x20, 0x73,
31400x00, 0xE0, 3140 0x00, 0xE0,
31410xB6, 0x49, 0x51, 0xBB, 3141 0xB6, 0x49, 0x51, 0xBB,
3142 3142
31430x26, 0x2F, 0xB0, 0xE8, 3143 0x26, 0x2F, 0xB0, 0xE8,
31440x19, 0x20, 0x20, 0xE9, 3144 0x19, 0x20, 0x20, 0xE9,
3145 3145
31460x35, 0x20, 0x35, 0xDF, 3146 0x35, 0x20, 0x35, 0xDF,
31470x3D, 0x20, 0x3D, 0xDF, 3147 0x3D, 0x20, 0x3D, 0xDF,
3148 3148
31490x15, 0x20, 0x15, 0xDF, 3149 0x15, 0x20, 0x15, 0xDF,
31500x1D, 0x20, 0x1D, 0xDF, 3150 0x1D, 0x20, 0x1D, 0xDF,
3151 3151
31520x26, 0xD0, 0x26, 0xCD, 3152 0x26, 0xD0, 0x26, 0xCD,
31530x29, 0x49, 0x2A, 0xB8, 3153 0x29, 0x49, 0x2A, 0xB8,
3154 3154
31550x26, 0x40, 0x80, 0xBD, 3155 0x26, 0x40, 0x80, 0xBD,
31560x3B, 0x48, 0x50, 0xBD, 3156 0x3B, 0x48, 0x50, 0xBD,
3157 3157
31580x3E, 0x54, 0x57, 0x9F, 3158 0x3E, 0x54, 0x57, 0x9F,
31590x00, 0xE0, 3159 0x00, 0xE0,
31600x82, 0xE1, 3160 0x82, 0xE1,
3161 3161
31620x1E, 0xAF, 0x59, 0x9F, 3162 0x1E, 0xAF, 0x59, 0x9F,
31630x00, 0x80, 0x00, 0xE8, 3163 0x00, 0x80, 0x00, 0xE8,
3164 3164
31650x26, 0x30, 3165 0x26, 0x30,
31660x29, 0x30, 3166 0x29, 0x30,
31670x48, 0x3C, 0x48, 0xAD, 3167 0x48, 0x3C, 0x48, 0xAD,
3168 3168
31690x2B, 0x72, 3169 0x2B, 0x72,
31700xC2, 0xE1, 3170 0xC2, 0xE1,
31710x2C, 0xC0, 0x44, 0xC2, 3171 0x2C, 0xC0, 0x44, 0xC2,
3172 3172
31730x05, 0x24, 0x34, 0xBF, 3173 0x05, 0x24, 0x34, 0xBF,
31740x0D, 0x24, 0x2C, 0xBF, 3174 0x0D, 0x24, 0x2C, 0xBF,
3175 3175
31760x2D, 0x46, 0x4E, 0xBF, 3176 0x2D, 0x46, 0x4E, 0xBF,
31770x25, 0x46, 0x56, 0xBF, 3177 0x25, 0x46, 0x56, 0xBF,
3178 3178
31790x20, 0x1D, 0x6F, 0x8F, 3179 0x20, 0x1D, 0x6F, 0x8F,
31800x32, 0x3E, 0x5F, 0xE9, 3180 0x32, 0x3E, 0x5F, 0xE9,
3181 3181
31820x3E, 0x50, 0x56, 0x9F, 3182 0x3E, 0x50, 0x56, 0x9F,
31830x00, 0xE0, 3183 0x00, 0xE0,
31840x3B, 0x30, 3184 0x3B, 0x30,
3185 3185
31860x1E, 0x8F, 0x51, 0x9F, 3186 0x1E, 0x8F, 0x51, 0x9F,
31870x33, 0x1E, 0x5F, 0xE9, 3187 0x33, 0x1E, 0x5F, 0xE9,
3188 3188
31890x05, 0x44, 0x54, 0xB2, 3189 0x05, 0x44, 0x54, 0xB2,
31900x0D, 0x44, 0x4C, 0xB2, 3190 0x0D, 0x44, 0x4C, 0xB2,
3191 3191
31920x19, 0xC0, 0xB0, 0xE8, 3192 0x19, 0xC0, 0xB0, 0xE8,
31930x34, 0xC0, 0x44, 0xC4, 3193 0x34, 0xC0, 0x44, 0xC4,
3194 3194
31950x33, 0x73, 3195 0x33, 0x73,
31960x00, 0xE0, 3196 0x00, 0xE0,
31970x3E, 0x62, 0x57, 0x9F, 3197 0x3E, 0x62, 0x57, 0x9F,
3198 3198
31990x1E, 0xAF, 0x59, 0x9F, 3199 0x1E, 0xAF, 0x59, 0x9F,
32000x00, 0xE0, 3200 0x00, 0xE0,
32010x0D, 0x20, 3201 0x0D, 0x20,
3202 3202
32030x84, 0x3E, 0x58, 0xE9, 3203 0x84, 0x3E, 0x58, 0xE9,
32040x28, 0x1D, 0x6F, 0x8F, 3204 0x28, 0x1D, 0x6F, 0x8F,
3205 3205
32060x05, 0x20, 3206 0x05, 0x20,
32070x00, 0xE0, 3207 0x00, 0xE0,
32080x85, 0x1E, 0x58, 0xE9, 3208 0x85, 0x1E, 0x58, 0xE9,
3209 3209
32100x9B, 0x3B, 0x33, 0xDF, 3210 0x9B, 0x3B, 0x33, 0xDF,
32110x20, 0x20, 0x42, 0xAF, 3211 0x20, 0x20, 0x42, 0xAF,
3212 3212
32130x30, 0x42, 0x56, 0x9F, 3213 0x30, 0x42, 0x56, 0x9F,
32140x80, 0x3E, 0x57, 0xE9, 3214 0x80, 0x3E, 0x57, 0xE9,
3215 3215
32160x3F, 0x8F, 0x51, 0x9F, 3216 0x3F, 0x8F, 0x51, 0x9F,
32170x30, 0x80, 0x5F, 0xE9, 3217 0x30, 0x80, 0x5F, 0xE9,
3218 3218
32190x28, 0x28, 0x24, 0xAF, 3219 0x28, 0x28, 0x24, 0xAF,
32200x81, 0x1E, 0x57, 0xE9, 3220 0x81, 0x1E, 0x57, 0xE9,
3221 3221
32220x05, 0x47, 0x57, 0xBF, 3222 0x05, 0x47, 0x57, 0xBF,
32230x0D, 0x47, 0x4F, 0xBF, 3223 0x0D, 0x47, 0x4F, 0xBF,
3224 3224
32250x88, 0x80, 0x58, 0xE9, 3225 0x88, 0x80, 0x58, 0xE9,
32260x1B, 0x29, 0x1B, 0xDF, 3226 0x1B, 0x29, 0x1B, 0xDF,
3227 3227
32280x30, 0x1D, 0x6F, 0x8F, 3228 0x30, 0x1D, 0x6F, 0x8F,
32290x3A, 0x30, 0x4F, 0xE9, 3229 0x3A, 0x30, 0x4F, 0xE9,
3230 3230
32310x1C, 0x30, 0x26, 0xDF, 3231 0x1C, 0x30, 0x26, 0xDF,
32320x09, 0xE3, 3232 0x09, 0xE3,
32330x3B, 0x05, 3233 0x3B, 0x05,
3234 3234
32350x3E, 0x50, 0x56, 0x9F, 3235 0x3E, 0x50, 0x56, 0x9F,
32360x3B, 0x3F, 0x4F, 0xE9, 3236 0x3B, 0x3F, 0x4F, 0xE9,
3237 3237
32380x1E, 0x8F, 0x51, 0x9F, 3238 0x1E, 0x8F, 0x51, 0x9F,
32390x00, 0xE0, 3239 0x00, 0xE0,
32400xAC, 0x20, 3240 0xAC, 0x20,
3241 3241
32420x2D, 0x44, 0x4C, 0xB4, 3242 0x2D, 0x44, 0x4C, 0xB4,
32430x2C, 0x1C, 0xC0, 0xAF, 3243 0x2C, 0x1C, 0xC0, 0xAF,
3244 3244
32450x25, 0x44, 0x54, 0xB4, 3245 0x25, 0x44, 0x54, 0xB4,
32460x00, 0xE0, 3246 0x00, 0xE0,
32470xC8, 0x30, 3247 0xC8, 0x30,
3248 3248
32490x30, 0x46, 0x30, 0xAF, 3249 0x30, 0x46, 0x30, 0xAF,
32500x1B, 0x1B, 0x48, 0xAF, 3250 0x1B, 0x1B, 0x48, 0xAF,
3251 3251
32520x00, 0xE0, 3252 0x00, 0xE0,
32530x25, 0x20, 3253 0x25, 0x20,
32540x38, 0x2C, 0x4F, 0xE9, 3254 0x38, 0x2C, 0x4F, 0xE9,
3255 3255
32560x86, 0x80, 0x57, 0xE9, 3256 0x86, 0x80, 0x57, 0xE9,
32570x38, 0x1D, 0x6F, 0x8F, 3257 0x38, 0x1D, 0x6F, 0x8F,
3258 3258
32590x28, 0x74, 3259 0x28, 0x74,
32600x00, 0xE0, 3260 0x00, 0xE0,
32610x0D, 0x44, 0x4C, 0xB0, 3261 0x0D, 0x44, 0x4C, 0xB0,
3262 3262
32630x05, 0x44, 0x54, 0xB0, 3263 0x05, 0x44, 0x54, 0xB0,
32640x2D, 0x20, 3264 0x2D, 0x20,
32650x9B, 0x10, 3265 0x9B, 0x10,
3266 3266
32670x82, 0x3E, 0x57, 0xE9, 3267 0x82, 0x3E, 0x57, 0xE9,
32680x32, 0xF0, 0x1B, 0xCD, 3268 0x32, 0xF0, 0x1B, 0xCD,
3269 3269
32700x1E, 0xBD, 0x59, 0x9F, 3270 0x1E, 0xBD, 0x59, 0x9F,
32710x83, 0x1E, 0x57, 0xE9, 3271 0x83, 0x1E, 0x57, 0xE9,
3272 3272
32730x38, 0x47, 0x38, 0xAF, 3273 0x38, 0x47, 0x38, 0xAF,
32740x34, 0x20, 3274 0x34, 0x20,
32750x2A, 0x30, 3275 0x2A, 0x30,
3276 3276
32770x00, 0xE0, 3277 0x00, 0xE0,
32780x0D, 0x20, 3278 0x0D, 0x20,
32790x32, 0x20, 3279 0x32, 0x20,
32800x05, 0x20, 3280 0x05, 0x20,
3281 3281
32820x87, 0x80, 0x57, 0xE9, 3282 0x87, 0x80, 0x57, 0xE9,
32830x1F, 0x54, 0x57, 0x9F, 3283 0x1F, 0x54, 0x57, 0x9F,
3284 3284
32850x17, 0x42, 0x56, 0x9F, 3285 0x17, 0x42, 0x56, 0x9F,
32860x00, 0xE0, 3286 0x00, 0xE0,
32870x3B, 0x6A, 3287 0x3B, 0x6A,
3288 3288
32890x3F, 0x8F, 0x51, 0x9F, 3289 0x3F, 0x8F, 0x51, 0x9F,
32900x37, 0x1E, 0x4F, 0xE9, 3290 0x37, 0x1E, 0x4F, 0xE9,
3291 3291
32920x37, 0x32, 0x2A, 0xAF, 3292 0x37, 0x32, 0x2A, 0xAF,
32930x00, 0xE0, 3293 0x00, 0xE0,
32940x32, 0x00, 3294 0x32, 0x00,
3295 3295
32960x00, 0x80, 0x00, 0xE8, 3296 0x00, 0x80, 0x00, 0xE8,
32970x27, 0xC0, 0x44, 0xC0, 3297 0x27, 0xC0, 0x44, 0xC0,
3298 3298
32990x36, 0x1F, 0x4F, 0xE9, 3299 0x36, 0x1F, 0x4F, 0xE9,
33000x1F, 0x1F, 0x26, 0xDF, 3300 0x1F, 0x1F, 0x26, 0xDF,
3301 3301
33020x37, 0x1B, 0x37, 0xBF, 3302 0x37, 0x1B, 0x37, 0xBF,
33030x17, 0x26, 0x17, 0xDF, 3303 0x17, 0x26, 0x17, 0xDF,
3304 3304
33050x3E, 0x17, 0x4F, 0xE9, 3305 0x3E, 0x17, 0x4F, 0xE9,
33060x3F, 0x3F, 0x4F, 0xE9, 3306 0x3F, 0x3F, 0x4F, 0xE9,
3307 3307
33080x34, 0x1F, 0x34, 0xAF, 3308 0x34, 0x1F, 0x34, 0xAF,
33090x2B, 0x05, 3309 0x2B, 0x05,
33100xA7, 0x20, 3310 0xA7, 0x20,
3311 3311
33120x33, 0x2B, 0x37, 0xDF, 3312 0x33, 0x2B, 0x37, 0xDF,
33130x27, 0x17, 0xC0, 0xAF, 3313 0x27, 0x17, 0xC0, 0xAF,
3314 3314
33150x34, 0x80, 0x4F, 0xE9, 3315 0x34, 0x80, 0x4F, 0xE9,
33160x00, 0x80, 0x00, 0xE8, 3316 0x00, 0x80, 0x00, 0xE8,
3317 3317
33180x2D, 0x21, 0x1A, 0xB0, 3318 0x2D, 0x21, 0x1A, 0xB0,
33190x25, 0x21, 0x31, 0xB0, 3319 0x25, 0x21, 0x31, 0xB0,
3320 3320
33210x0D, 0x21, 0x1A, 0xB2, 3321 0x0D, 0x21, 0x1A, 0xB2,
33220x05, 0x21, 0x31, 0xB2, 3322 0x05, 0x21, 0x31, 0xB2,
3323 3323
33240x03, 0x80, 0x2A, 0xEA, 3324 0x03, 0x80, 0x2A, 0xEA,
33250x17, 0xC1, 0x2B, 0xBD, 3325 0x17, 0xC1, 0x2B, 0xBD,
3326 3326
33270x2D, 0x20, 3327 0x2D, 0x20,
33280x25, 0x20, 3328 0x25, 0x20,
33290x05, 0x20, 3329 0x05, 0x20,
33300x0D, 0x20, 3330 0x0D, 0x20,
3331 3331
33320xB3, 0x68, 3332 0xB3, 0x68,
33330x97, 0x25, 3333 0x97, 0x25,
33340x00, 0x80, 0x00, 0xE8, 3334 0x00, 0x80, 0x00, 0xE8,
3335 3335
33360x33, 0xC0, 0x33, 0xAF, 3336 0x33, 0xC0, 0x33, 0xAF,
33370x2F, 0xC0, 0x21, 0xC0, 3337 0x2F, 0xC0, 0x21, 0xC0,
3338 3338
33390x16, 0x42, 0x56, 0x9F, 3339 0x16, 0x42, 0x56, 0x9F,
33400x3C, 0x27, 0x4F, 0xE9, 3340 0x3C, 0x27, 0x4F, 0xE9,
3341 3341
33420x1E, 0x62, 0x57, 0x9F, 3342 0x1E, 0x62, 0x57, 0x9F,
33430x00, 0x80, 0x00, 0xE8, 3343 0x00, 0x80, 0x00, 0xE8,
3344 3344
33450x25, 0x21, 0x31, 0xB4, 3345 0x25, 0x21, 0x31, 0xB4,
33460x2D, 0x21, 0x1A, 0xB4, 3346 0x2D, 0x21, 0x1A, 0xB4,
3347 3347
33480x3F, 0x2F, 0x5D, 0x9F, 3348 0x3F, 0x2F, 0x5D, 0x9F,
33490x00, 0x80, 0x00, 0xE8, 3349 0x00, 0x80, 0x00, 0xE8,
3350 3350
33510x33, 0x05, 3351 0x33, 0x05,
33520x00, 0xE0, 3352 0x00, 0xE0,
33530x28, 0x19, 0x60, 0xEC, 3353 0x28, 0x19, 0x60, 0xEC,
3354 3354
33550x0D, 0x44, 0x4C, 0xB6, 3355 0x0D, 0x44, 0x4C, 0xB6,
33560x05, 0x44, 0x54, 0xB6, 3356 0x05, 0x44, 0x54, 0xB6,
3357 3357
33580x37, 0x0F, 0x5C, 0x9F, 3358 0x37, 0x0F, 0x5C, 0x9F,
33590x00, 0xE0, 3359 0x00, 0xE0,
33600x2F, 0x20, 3360 0x2F, 0x20,
3361 3361
33620x23, 0x3B, 0x33, 0xAD, 3362 0x23, 0x3B, 0x33, 0xAD,
33630x1E, 0x26, 0x1E, 0xDF, 3363 0x1E, 0x26, 0x1E, 0xDF,
3364 3364
33650xA7, 0x1E, 0x4F, 0xE9, 3365 0xA7, 0x1E, 0x4F, 0xE9,
33660x17, 0x26, 0x16, 0xDF, 3366 0x17, 0x26, 0x16, 0xDF,
3367 3367
33680x2D, 0x20, 3368 0x2D, 0x20,
33690x00, 0xE0, 3369 0x00, 0xE0,
33700xA8, 0x3F, 0x4F, 0xE9, 3370 0xA8, 0x3F, 0x4F, 0xE9,
3371 3371
33720x2F, 0x2F, 0x1E, 0xAF, 3372 0x2F, 0x2F, 0x1E, 0xAF,
33730x25, 0x20, 3373 0x25, 0x20,
33740x00, 0xE0, 3374 0x00, 0xE0,
3375 3375
33760xA4, 0x16, 0x4F, 0xE9, 3376 0xA4, 0x16, 0x4F, 0xE9,
33770x0F, 0xC0, 0x21, 0xC2, 3377 0x0F, 0xC0, 0x21, 0xC2,
3378 3378
33790xA6, 0x80, 0x4F, 0xE9, 3379 0xA6, 0x80, 0x4F, 0xE9,
33800x1F, 0x62, 0x57, 0x9F, 3380 0x1F, 0x62, 0x57, 0x9F,
3381 3381
33820x0D, 0x20, 3382 0x0D, 0x20,
33830x05, 0x20, 3383 0x05, 0x20,
33840x00, 0x80, 0x00, 0xE8, 3384 0x00, 0x80, 0x00, 0xE8,
3385 3385
33860x3F, 0x2F, 0x5D, 0x9F, 3386 0x3F, 0x2F, 0x5D, 0x9F,
33870x00, 0xE0, 3387 0x00, 0xE0,
33880x0F, 0x20, 3388 0x0F, 0x20,
3389 3389
33900x17, 0x50, 0x56, 0x9F, 3390 0x17, 0x50, 0x56, 0x9F,
33910xA5, 0x37, 0x4F, 0xE9, 3391 0xA5, 0x37, 0x4F, 0xE9,
3392 3392
33930x06, 0xC0, 0x21, 0xC4, 3393 0x06, 0xC0, 0x21, 0xC4,
33940x0F, 0x17, 0x0F, 0xAF, 3394 0x0F, 0x17, 0x0F, 0xAF,
3395 3395
33960x37, 0x0F, 0x5C, 0x9F, 3396 0x37, 0x0F, 0x5C, 0x9F,
33970x00, 0x80, 0x00, 0xE8, 3397 0x00, 0x80, 0x00, 0xE8,
3398 3398
33990x2F, 0xC0, 0x44, 0xC6, 3399 0x2F, 0xC0, 0x44, 0xC6,
34000xA3, 0x80, 0x4F, 0xE9, 3400 0xA3, 0x80, 0x4F, 0xE9,
3401 3401
34020x06, 0x20, 3402 0x06, 0x20,
34030x00, 0xE0, 3403 0x00, 0xE0,
34040x1F, 0x26, 0x1F, 0xDF, 3404 0x1F, 0x26, 0x1F, 0xDF,
3405 3405
34060x17, 0x26, 0x17, 0xDF, 3406 0x17, 0x26, 0x17, 0xDF,
34070x9D, 0x17, 0x4F, 0xE9, 3407 0x9D, 0x17, 0x4F, 0xE9,
3408 3408
34090xA1, 0x1F, 0x4F, 0xE9, 3409 0xA1, 0x1F, 0x4F, 0xE9,
34100xA2, 0x3F, 0x4F, 0xE9, 3410 0xA2, 0x3F, 0x4F, 0xE9,
3411 3411
34120x06, 0x06, 0x1F, 0xAF, 3412 0x06, 0x06, 0x1F, 0xAF,
34130x00, 0xE0, 3413 0x00, 0xE0,
34140xAF, 0x20, 3414 0xAF, 0x20,
3415 3415
34160x9E, 0x37, 0x4F, 0xE9, 3416 0x9E, 0x37, 0x4F, 0xE9,
34170x2F, 0x17, 0x2F, 0xAF, 3417 0x2F, 0x17, 0x2F, 0xAF,
3418 3418
34190xA0, 0x80, 0x4F, 0xE9, 3419 0xA0, 0x80, 0x4F, 0xE9,
34200x00, 0x80, 0x00, 0xE8, 3420 0x00, 0x80, 0x00, 0xE8,
3421 3421
34220x00, 0x80, 0x00, 0xE8, 3422 0x00, 0x80, 0x00, 0xE8,
34230x9C, 0x80, 0x4F, 0xE9, 3423 0x9C, 0x80, 0x4F, 0xE9,
3424 3424
34250x00, 0x80, 0x00, 0xE8, 3425 0x00, 0x80, 0x00, 0xE8,
34260x57, 0x39, 0x20, 0xE9, 3426 0x57, 0x39, 0x20, 0xE9,
3427 3427
34280x16, 0x28, 0x20, 0xE9, 3428 0x16, 0x28, 0x20, 0xE9,
34290x1D, 0x3B, 0x20, 0xE9, 3429 0x1D, 0x3B, 0x20, 0xE9,
3430 3430
34310x1E, 0x2B, 0x20, 0xE9, 3431 0x1E, 0x2B, 0x20, 0xE9,
34320x2B, 0x32, 0x20, 0xE9, 3432 0x2B, 0x32, 0x20, 0xE9,
3433 3433
34340x1C, 0x23, 0x20, 0xE9, 3434 0x1C, 0x23, 0x20, 0xE9,
34350x57, 0x36, 0x20, 0xE9, 3435 0x57, 0x36, 0x20, 0xE9,
3436 3436
34370x00, 0x80, 0xA0, 0xE9, 3437 0x00, 0x80, 0xA0, 0xE9,
34380x40, 0x40, 0xD8, 0xEC, 3438 0x40, 0x40, 0xD8, 0xEC,
3439 3439
34400xFF, 0x80, 0xC0, 0xE9, 3440 0xFF, 0x80, 0xC0, 0xE9,
34410x90, 0xE2, 3441 0x90, 0xE2,
34420x00, 0xE0, 3442 0x00, 0xE0,
3443 3443
34440x68, 0xFF, 0x20, 0xEA, 3444 0x68, 0xFF, 0x20, 0xEA,
34450x19, 0xC8, 0xC1, 0xCD, 3445 0x19, 0xC8, 0xC1, 0xCD,
3446 3446
34470x1F, 0xD7, 0x18, 0xBD, 3447 0x1F, 0xD7, 0x18, 0xBD,
34480x3F, 0xD7, 0x22, 0xBD, 3448 0x3F, 0xD7, 0x22, 0xBD,
3449 3449
34500x9F, 0x41, 0x49, 0xBD, 3450 0x9F, 0x41, 0x49, 0xBD,
34510x00, 0x80, 0x00, 0xE8, 3451 0x00, 0x80, 0x00, 0xE8,
3452 3452
34530x25, 0x41, 0x49, 0xBD, 3453 0x25, 0x41, 0x49, 0xBD,
34540x2D, 0x41, 0x51, 0xBD, 3454 0x2D, 0x41, 0x51, 0xBD,
3455 3455
34560x0D, 0x80, 0x07, 0xEA, 3456 0x0D, 0x80, 0x07, 0xEA,
34570x00, 0x80, 0x00, 0xE8, 3457 0x00, 0x80, 0x00, 0xE8,
3458 3458
34590x35, 0x40, 0x48, 0xBD, 3459 0x35, 0x40, 0x48, 0xBD,
34600x3D, 0x40, 0x50, 0xBD, 3460 0x3D, 0x40, 0x50, 0xBD,
3461 3461
34620x00, 0x80, 0x00, 0xE8, 3462 0x00, 0x80, 0x00, 0xE8,
34630x25, 0x30, 3463 0x25, 0x30,
34640x2D, 0x30, 3464 0x2D, 0x30,
3465 3465
34660x35, 0x30, 3466 0x35, 0x30,
34670xB5, 0x30, 3467 0xB5, 0x30,
34680xBD, 0x30, 3468 0xBD, 0x30,
34690x3D, 0x30, 3469 0x3D, 0x30,
3470 3470
34710x9C, 0xA7, 0x5B, 0x9F, 3471 0x9C, 0xA7, 0x5B, 0x9F,
34720x00, 0x80, 0x00, 0xE8, 3472 0x00, 0x80, 0x00, 0xE8,
3473 3473
34740x00, 0x80, 0x00, 0xE8, 3474 0x00, 0x80, 0x00, 0xE8,
34750x00, 0x80, 0x00, 0xE8, 3475 0x00, 0x80, 0x00, 0xE8,
3476 3476
34770x00, 0x80, 0x00, 0xE8, 3477 0x00, 0x80, 0x00, 0xE8,
34780x00, 0x80, 0x00, 0xE8, 3478 0x00, 0x80, 0x00, 0xE8,
3479 3479
34800x00, 0x80, 0x00, 0xE8, 3480 0x00, 0x80, 0x00, 0xE8,
34810x00, 0x80, 0x00, 0xE8, 3481 0x00, 0x80, 0x00, 0xE8,
3482 3482
34830x00, 0x80, 0x00, 0xE8, 3483 0x00, 0x80, 0x00, 0xE8,
34840x00, 0x80, 0x00, 0xE8, 3484 0x00, 0x80, 0x00, 0xE8,
3485 3485
34860x67, 0xFF, 0x0A, 0xEA, 3486 0x67, 0xFF, 0x0A, 0xEA,
34870x00, 0x80, 0x00, 0xE8, 3487 0x00, 0x80, 0x00, 0xE8,
3488 3488
34890xC9, 0x41, 0xC8, 0xEC, 3489 0xC9, 0x41, 0xC8, 0xEC,
34900x42, 0xE1, 3490 0x42, 0xE1,
34910x00, 0xE0, 3491 0x00, 0xE0,
3492 3492
34930x65, 0xFF, 0x20, 0xEA, 3493 0x65, 0xFF, 0x20, 0xEA,
34940x00, 0x80, 0x00, 0xE8, 3494 0x00, 0x80, 0x00, 0xE8,
3495 3495
34960x00, 0x80, 0x00, 0xE8, 3496 0x00, 0x80, 0x00, 0xE8,
34970x00, 0x80, 0x00, 0xE8, 3497 0x00, 0x80, 0x00, 0xE8,
3498 3498
34990xC8, 0x40, 0xC0, 0xEC, 3499 0xC8, 0x40, 0xC0, 0xEC,
35000x00, 0x80, 0x00, 0xE8, 3500 0x00, 0x80, 0x00, 0xE8,
3501 3501
35020x62, 0xFF, 0x20, 0xEA, 3502 0x62, 0xFF, 0x20, 0xEA,
35030x00, 0x80, 0x00, 0xE8, 3503 0x00, 0x80, 0x00, 0xE8,
3504 3504
35050x00, 0x80, 0x00, 0xE8, 3505 0x00, 0x80, 0x00, 0xE8,
35060x00, 0x80, 0x00, 0xE8, 3506 0x00, 0x80, 0x00, 0xE8,
3507 3507
3508}; 3508};
3509 3509
3510static unsigned char warp_g200_tgzsaf[] = { 3510static unsigned char warp_g200_tgzsaf[] = {
3511 3511
35120x00, 0x80, 0x00, 0xE8, 3512 0x00, 0x80, 0x00, 0xE8,
35130x00, 0x80, 0x00, 0xE8, 3513 0x00, 0x80, 0x00, 0xE8,
3514 3514
35150x00, 0x80, 0x00, 0xE8, 3515 0x00, 0x80, 0x00, 0xE8,
35160x00, 0x80, 0x00, 0xE8, 3516 0x00, 0x80, 0x00, 0xE8,
3517 3517
35180x00, 0x80, 0x00, 0xE8, 3518 0x00, 0x80, 0x00, 0xE8,
35190x00, 0x80, 0x00, 0xE8, 3519 0x00, 0x80, 0x00, 0xE8,
3520 3520
35210x00, 0x98, 0xA0, 0xE9, 3521 0x00, 0x98, 0xA0, 0xE9,
35220x40, 0x40, 0xD8, 0xEC, 3522 0x40, 0x40, 0xD8, 0xEC,
3523 3523
35240xFF, 0x80, 0xC0, 0xE9, 3524 0xFF, 0x80, 0xC0, 0xE9,
35250x00, 0x80, 0x00, 0xE8, 3525 0x00, 0x80, 0x00, 0xE8,
3526 3526
35270x1F, 0xD7, 0x18, 0xBD, 3527 0x1F, 0xD7, 0x18, 0xBD,
35280x3F, 0xD7, 0x22, 0xBD, 3528 0x3F, 0xD7, 0x22, 0xBD,
3529 3529
35300x81, 0x04, 3530 0x81, 0x04,
35310x89, 0x04, 3531 0x89, 0x04,
35320x01, 0x04, 3532 0x01, 0x04,
35330x09, 0x04, 3533 0x09, 0x04,
3534 3534
35350xC9, 0x41, 0xC0, 0xEC, 3535 0xC9, 0x41, 0xC0, 0xEC,
35360x11, 0x04, 3536 0x11, 0x04,
35370x00, 0xE0, 3537 0x00, 0xE0,
3538 3538
35390x41, 0xCC, 0x41, 0xCD, 3539 0x41, 0xCC, 0x41, 0xCD,
35400x49, 0xCC, 0x49, 0xCD, 3540 0x49, 0xCC, 0x49, 0xCD,
3541 3541
35420xD1, 0x41, 0xC0, 0xEC, 3542 0xD1, 0x41, 0xC0, 0xEC,
35430x51, 0xCC, 0x51, 0xCD, 3543 0x51, 0xCC, 0x51, 0xCD,
3544 3544
35450x80, 0x04, 3545 0x80, 0x04,
35460x10, 0x04, 3546 0x10, 0x04,
35470x08, 0x04, 3547 0x08, 0x04,
35480x00, 0xE0, 3548 0x00, 0xE0,
3549 3549
35500x00, 0xCC, 0xC0, 0xCD, 3550 0x00, 0xCC, 0xC0, 0xCD,
35510xD1, 0x49, 0xC0, 0xEC, 3551 0xD1, 0x49, 0xC0, 0xEC,
3552 3552
35530x8A, 0x1F, 0x20, 0xE9, 3553 0x8A, 0x1F, 0x20, 0xE9,
35540x8B, 0x3F, 0x20, 0xE9, 3554 0x8B, 0x3F, 0x20, 0xE9,
3555 3555
35560x41, 0x3C, 0x41, 0xAD, 3556 0x41, 0x3C, 0x41, 0xAD,
35570x49, 0x3C, 0x49, 0xAD, 3557 0x49, 0x3C, 0x49, 0xAD,
3558 3558
35590x10, 0xCC, 0x10, 0xCD, 3559 0x10, 0xCC, 0x10, 0xCD,
35600x08, 0xCC, 0x08, 0xCD, 3560 0x08, 0xCC, 0x08, 0xCD,
3561 3561
35620xB9, 0x41, 0x49, 0xBB, 3562 0xB9, 0x41, 0x49, 0xBB,
35630x1F, 0xF0, 0x41, 0xCD, 3563 0x1F, 0xF0, 0x41, 0xCD,
3564 3564
35650x51, 0x3C, 0x51, 0xAD, 3565 0x51, 0x3C, 0x51, 0xAD,
35660x00, 0x98, 0x80, 0xE9, 3566 0x00, 0x98, 0x80, 0xE9,
3567 3567
35680x94, 0x80, 0x07, 0xEA, 3568 0x94, 0x80, 0x07, 0xEA,
35690x24, 0x1F, 0x20, 0xE9, 3569 0x24, 0x1F, 0x20, 0xE9,
3570 3570
35710x21, 0x45, 0x80, 0xE8, 3571 0x21, 0x45, 0x80, 0xE8,
35720x1A, 0x4D, 0x80, 0xE8, 3572 0x1A, 0x4D, 0x80, 0xE8,
3573 3573
35740x31, 0x55, 0x80, 0xE8, 3574 0x31, 0x55, 0x80, 0xE8,
35750x00, 0x80, 0x00, 0xE8, 3575 0x00, 0x80, 0x00, 0xE8,
3576 3576
35770x15, 0x41, 0x49, 0xBD, 3577 0x15, 0x41, 0x49, 0xBD,
35780x1D, 0x41, 0x51, 0xBD, 3578 0x1D, 0x41, 0x51, 0xBD,
3579 3579
35800x2E, 0x41, 0x2A, 0xB8, 3580 0x2E, 0x41, 0x2A, 0xB8,
35810x34, 0x53, 0xA0, 0xE8, 3581 0x34, 0x53, 0xA0, 0xE8,
3582 3582
35830x15, 0x30, 3583 0x15, 0x30,
35840x1D, 0x30, 3584 0x1D, 0x30,
35850x58, 0xE3, 3585 0x58, 0xE3,
35860x00, 0xE0, 3586 0x00, 0xE0,
3587 3587
35880xB5, 0x40, 0x48, 0xBD, 3588 0xB5, 0x40, 0x48, 0xBD,
35890x3D, 0x40, 0x50, 0xBD, 3589 0x3D, 0x40, 0x50, 0xBD,
3590 3590
35910x24, 0x43, 0xA0, 0xE8, 3591 0x24, 0x43, 0xA0, 0xE8,
35920x2C, 0x4B, 0xA0, 0xE8, 3592 0x2C, 0x4B, 0xA0, 0xE8,
3593 3593
35940x15, 0x72, 3594 0x15, 0x72,
35950x09, 0xE3, 3595 0x09, 0xE3,
35960x00, 0xE0, 3596 0x00, 0xE0,
35970x1D, 0x72, 3597 0x1D, 0x72,
3598 3598
35990x35, 0x30, 3599 0x35, 0x30,
36000xB5, 0x30, 3600 0xB5, 0x30,
36010xBD, 0x30, 3601 0xBD, 0x30,
36020x3D, 0x30, 3602 0x3D, 0x30,
3603 3603
36040x9C, 0x97, 0x57, 0x9F, 3604 0x9C, 0x97, 0x57, 0x9F,
36050x00, 0x80, 0x00, 0xE8, 3605 0x00, 0x80, 0x00, 0xE8,
3606 3606
36070x6C, 0x64, 0xC8, 0xEC, 3607 0x6C, 0x64, 0xC8, 0xEC,
36080x98, 0xE1, 3608 0x98, 0xE1,
36090xB5, 0x05, 3609 0xB5, 0x05,
3610 3610
36110xBD, 0x05, 3611 0xBD, 0x05,
36120x2E, 0x30, 3612 0x2E, 0x30,
36130x32, 0xC0, 0xA0, 0xE8, 3613 0x32, 0xC0, 0xA0, 0xE8,
3614 3614
36150x33, 0xC0, 0xA0, 0xE8, 3615 0x33, 0xC0, 0xA0, 0xE8,
36160x74, 0x64, 0xC8, 0xEC, 3616 0x74, 0x64, 0xC8, 0xEC,
3617 3617
36180x40, 0x3C, 0x40, 0xAD, 3618 0x40, 0x3C, 0x40, 0xAD,
36190x32, 0x6A, 3619 0x32, 0x6A,
36200x2A, 0x30, 3620 0x2A, 0x30,
3621 3621
36220x20, 0x73, 3622 0x20, 0x73,
36230x33, 0x6A, 3623 0x33, 0x6A,
36240x00, 0xE0, 3624 0x00, 0xE0,
36250x28, 0x73, 3625 0x28, 0x73,
3626 3626
36270x1C, 0x72, 3627 0x1C, 0x72,
36280x83, 0xE2, 3628 0x83, 0xE2,
36290x80, 0x80, 0x15, 0xEA, 3629 0x80, 0x80, 0x15, 0xEA,
3630 3630
36310xB8, 0x3D, 0x28, 0xDF, 3631 0xB8, 0x3D, 0x28, 0xDF,
36320x30, 0x35, 0x20, 0xDF, 3632 0x30, 0x35, 0x20, 0xDF,
3633 3633
36340x40, 0x30, 3634 0x40, 0x30,
36350x00, 0xE0, 3635 0x00, 0xE0,
36360xCC, 0xE2, 3636 0xCC, 0xE2,
36370x64, 0x72, 3637 0x64, 0x72,
3638 3638
36390x25, 0x42, 0x52, 0xBF, 3639 0x25, 0x42, 0x52, 0xBF,
36400x2D, 0x42, 0x4A, 0xBF, 3640 0x2D, 0x42, 0x4A, 0xBF,
3641 3641
36420x30, 0x2E, 0x30, 0xDF, 3642 0x30, 0x2E, 0x30, 0xDF,
36430x38, 0x2E, 0x38, 0xDF, 3643 0x38, 0x2E, 0x38, 0xDF,
3644 3644
36450x18, 0x1D, 0x45, 0xE9, 3645 0x18, 0x1D, 0x45, 0xE9,
36460x1E, 0x15, 0x45, 0xE9, 3646 0x1E, 0x15, 0x45, 0xE9,
3647 3647
36480x2B, 0x49, 0x51, 0xBD, 3648 0x2B, 0x49, 0x51, 0xBD,
36490x00, 0xE0, 3649 0x00, 0xE0,
36500x1F, 0x73, 3650 0x1F, 0x73,
3651 3651
36520x38, 0x38, 0x40, 0xAF, 3652 0x38, 0x38, 0x40, 0xAF,
36530x30, 0x30, 0x40, 0xAF, 3653 0x30, 0x30, 0x40, 0xAF,
3654 3654
36550x24, 0x1F, 0x24, 0xDF, 3655 0x24, 0x1F, 0x24, 0xDF,
36560x1D, 0x32, 0x20, 0xE9, 3656 0x1D, 0x32, 0x20, 0xE9,
3657 3657
36580x2C, 0x1F, 0x2C, 0xDF, 3658 0x2C, 0x1F, 0x2C, 0xDF,
36590x1A, 0x33, 0x20, 0xE9, 3659 0x1A, 0x33, 0x20, 0xE9,
3660 3660
36610xB0, 0x10, 3661 0xB0, 0x10,
36620x08, 0xE3, 3662 0x08, 0xE3,
36630x40, 0x10, 3663 0x40, 0x10,
36640xB8, 0x10, 3664 0xB8, 0x10,
3665 3665
36660x26, 0xF0, 0x30, 0xCD, 3666 0x26, 0xF0, 0x30, 0xCD,
36670x2F, 0xF0, 0x38, 0xCD, 3667 0x2F, 0xF0, 0x38, 0xCD,
3668 3668
36690x2B, 0x80, 0x20, 0xE9, 3669 0x2B, 0x80, 0x20, 0xE9,
36700x2A, 0x80, 0x20, 0xE9, 3670 0x2A, 0x80, 0x20, 0xE9,
3671 3671
36720xA6, 0x20, 3672 0xA6, 0x20,
36730x88, 0xE2, 3673 0x88, 0xE2,
36740x00, 0xE0, 3674 0x00, 0xE0,
36750xAF, 0x20, 3675 0xAF, 0x20,
3676 3676
36770x28, 0x2A, 0x26, 0xAF, 3677 0x28, 0x2A, 0x26, 0xAF,
36780x20, 0x2A, 0xC0, 0xAF, 3678 0x20, 0x2A, 0xC0, 0xAF,
3679 3679
36800x34, 0x1F, 0x34, 0xDF, 3680 0x34, 0x1F, 0x34, 0xDF,
36810x46, 0x24, 0x46, 0xDF, 3681 0x46, 0x24, 0x46, 0xDF,
3682 3682
36830x28, 0x30, 0x80, 0xBF, 3683 0x28, 0x30, 0x80, 0xBF,
36840x20, 0x38, 0x80, 0xBF, 3684 0x20, 0x38, 0x80, 0xBF,
3685 3685
36860x47, 0x24, 0x47, 0xDF, 3686 0x47, 0x24, 0x47, 0xDF,
36870x4E, 0x2C, 0x4E, 0xDF, 3687 0x4E, 0x2C, 0x4E, 0xDF,
3688 3688
36890x4F, 0x2C, 0x4F, 0xDF, 3689 0x4F, 0x2C, 0x4F, 0xDF,
36900x56, 0x34, 0x56, 0xDF, 3690 0x56, 0x34, 0x56, 0xDF,
3691 3691
36920x28, 0x15, 0x28, 0xDF, 3692 0x28, 0x15, 0x28, 0xDF,
36930x20, 0x1D, 0x20, 0xDF, 3693 0x20, 0x1D, 0x20, 0xDF,
3694 3694
36950x57, 0x34, 0x57, 0xDF, 3695 0x57, 0x34, 0x57, 0xDF,
36960x00, 0xE0, 3696 0x00, 0xE0,
36970x1D, 0x05, 3697 0x1D, 0x05,
3698 3698
36990x04, 0x80, 0x10, 0xEA, 3699 0x04, 0x80, 0x10, 0xEA,
37000x89, 0xE2, 3700 0x89, 0xE2,
37010x2B, 0x30, 3701 0x2B, 0x30,
3702 3702
37030x3F, 0xC1, 0x1D, 0xBD, 3703 0x3F, 0xC1, 0x1D, 0xBD,
37040x00, 0x80, 0x00, 0xE8, 3704 0x00, 0x80, 0x00, 0xE8,
3705 3705
37060x00, 0x80, 0x00, 0xE8, 3706 0x00, 0x80, 0x00, 0xE8,
37070x00, 0x80, 0x00, 0xE8, 3707 0x00, 0x80, 0x00, 0xE8,
3708 3708
37090xA0, 0x68, 3709 0xA0, 0x68,
37100xBF, 0x25, 3710 0xBF, 0x25,
37110x00, 0x80, 0x00, 0xE8, 3711 0x00, 0x80, 0x00, 0xE8,
3712 3712
37130x20, 0xC0, 0x20, 0xAF, 3713 0x20, 0xC0, 0x20, 0xAF,
37140x28, 0x05, 3714 0x28, 0x05,
37150x97, 0x74, 3715 0x97, 0x74,
3716 3716
37170x00, 0xE0, 3717 0x00, 0xE0,
37180x2A, 0x10, 3718 0x2A, 0x10,
37190x16, 0xC0, 0x20, 0xE9, 3719 0x16, 0xC0, 0x20, 0xE9,
3720 3720
37210x04, 0x80, 0x10, 0xEA, 3721 0x04, 0x80, 0x10, 0xEA,
37220x8C, 0xE2, 3722 0x8C, 0xE2,
37230x95, 0x05, 3723 0x95, 0x05,
3724 3724
37250x28, 0xC1, 0x28, 0xAD, 3725 0x28, 0xC1, 0x28, 0xAD,
37260x1F, 0xC1, 0x15, 0xBD, 3726 0x1F, 0xC1, 0x15, 0xBD,
3727 3727
37280x00, 0x80, 0x00, 0xE8, 3728 0x00, 0x80, 0x00, 0xE8,
37290x00, 0x80, 0x00, 0xE8, 3729 0x00, 0x80, 0x00, 0xE8,
3730 3730
37310xA8, 0x67, 3731 0xA8, 0x67,
37320x9F, 0x6B, 3732 0x9F, 0x6B,
37330x00, 0x80, 0x00, 0xE8, 3733 0x00, 0x80, 0x00, 0xE8,
3734 3734
37350x28, 0xC0, 0x28, 0xAD, 3735 0x28, 0xC0, 0x28, 0xAD,
37360x1D, 0x25, 3736 0x1D, 0x25,
37370x20, 0x05, 3737 0x20, 0x05,
3738 3738
37390x28, 0x32, 0x80, 0xAD, 3739 0x28, 0x32, 0x80, 0xAD,
37400x40, 0x2A, 0x40, 0xBD, 3740 0x40, 0x2A, 0x40, 0xBD,
3741 3741
37420x1C, 0x80, 0x20, 0xE9, 3742 0x1C, 0x80, 0x20, 0xE9,
37430x20, 0x33, 0x20, 0xAD, 3743 0x20, 0x33, 0x20, 0xAD,
3744 3744
37450x20, 0x73, 3745 0x20, 0x73,
37460x00, 0xE0, 3746 0x00, 0xE0,
37470xB6, 0x49, 0x51, 0xBB, 3747 0xB6, 0x49, 0x51, 0xBB,
3748 3748
37490x26, 0x2F, 0xB0, 0xE8, 3749 0x26, 0x2F, 0xB0, 0xE8,
37500x19, 0x20, 0x20, 0xE9, 3750 0x19, 0x20, 0x20, 0xE9,
3751 3751
37520x35, 0x20, 0x35, 0xDF, 3752 0x35, 0x20, 0x35, 0xDF,
37530x3D, 0x20, 0x3D, 0xDF, 3753 0x3D, 0x20, 0x3D, 0xDF,
3754 3754
37550x15, 0x20, 0x15, 0xDF, 3755 0x15, 0x20, 0x15, 0xDF,
37560x1D, 0x20, 0x1D, 0xDF, 3756 0x1D, 0x20, 0x1D, 0xDF,
3757 3757
37580x26, 0xD0, 0x26, 0xCD, 3758 0x26, 0xD0, 0x26, 0xCD,
37590x29, 0x49, 0x2A, 0xB8, 3759 0x29, 0x49, 0x2A, 0xB8,
3760 3760
37610x26, 0x40, 0x80, 0xBD, 3761 0x26, 0x40, 0x80, 0xBD,
37620x3B, 0x48, 0x50, 0xBD, 3762 0x3B, 0x48, 0x50, 0xBD,
3763 3763
37640x3E, 0x54, 0x57, 0x9F, 3764 0x3E, 0x54, 0x57, 0x9F,
37650x00, 0xE0, 3765 0x00, 0xE0,
37660x82, 0xE1, 3766 0x82, 0xE1,
3767 3767
37680x1E, 0xAF, 0x59, 0x9F, 3768 0x1E, 0xAF, 0x59, 0x9F,
37690x00, 0x80, 0x00, 0xE8, 3769 0x00, 0x80, 0x00, 0xE8,
3770 3770
37710x26, 0x30, 3771 0x26, 0x30,
37720x29, 0x30, 3772 0x29, 0x30,
37730x48, 0x3C, 0x48, 0xAD, 3773 0x48, 0x3C, 0x48, 0xAD,
3774 3774
37750x2B, 0x72, 3775 0x2B, 0x72,
37760xC2, 0xE1, 3776 0xC2, 0xE1,
37770x2C, 0xC0, 0x44, 0xC2, 3777 0x2C, 0xC0, 0x44, 0xC2,
3778 3778
37790x05, 0x24, 0x34, 0xBF, 3779 0x05, 0x24, 0x34, 0xBF,
37800x0D, 0x24, 0x2C, 0xBF, 3780 0x0D, 0x24, 0x2C, 0xBF,
3781 3781
37820x2D, 0x46, 0x4E, 0xBF, 3782 0x2D, 0x46, 0x4E, 0xBF,
37830x25, 0x46, 0x56, 0xBF, 3783 0x25, 0x46, 0x56, 0xBF,
3784 3784
37850x20, 0x1D, 0x6F, 0x8F, 3785 0x20, 0x1D, 0x6F, 0x8F,
37860x32, 0x3E, 0x5F, 0xE9, 3786 0x32, 0x3E, 0x5F, 0xE9,
3787 3787
37880x3E, 0x50, 0x56, 0x9F, 3788 0x3E, 0x50, 0x56, 0x9F,
37890x00, 0xE0, 3789 0x00, 0xE0,
37900x3B, 0x30, 3790 0x3B, 0x30,
3791 3791
37920x1E, 0x8F, 0x51, 0x9F, 3792 0x1E, 0x8F, 0x51, 0x9F,
37930x33, 0x1E, 0x5F, 0xE9, 3793 0x33, 0x1E, 0x5F, 0xE9,
3794 3794
37950x05, 0x44, 0x54, 0xB2, 3795 0x05, 0x44, 0x54, 0xB2,
37960x0D, 0x44, 0x4C, 0xB2, 3796 0x0D, 0x44, 0x4C, 0xB2,
3797 3797
37980x19, 0xC0, 0xB0, 0xE8, 3798 0x19, 0xC0, 0xB0, 0xE8,
37990x34, 0xC0, 0x44, 0xC4, 3799 0x34, 0xC0, 0x44, 0xC4,
3800 3800
38010x33, 0x73, 3801 0x33, 0x73,
38020x00, 0xE0, 3802 0x00, 0xE0,
38030x3E, 0x62, 0x57, 0x9F, 3803 0x3E, 0x62, 0x57, 0x9F,
3804 3804
38050x1E, 0xAF, 0x59, 0x9F, 3805 0x1E, 0xAF, 0x59, 0x9F,
38060x00, 0xE0, 3806 0x00, 0xE0,
38070x0D, 0x20, 3807 0x0D, 0x20,
3808 3808
38090x84, 0x3E, 0x58, 0xE9, 3809 0x84, 0x3E, 0x58, 0xE9,
38100x28, 0x1D, 0x6F, 0x8F, 3810 0x28, 0x1D, 0x6F, 0x8F,
3811 3811
38120x05, 0x20, 3812 0x05, 0x20,
38130x00, 0xE0, 3813 0x00, 0xE0,
38140x85, 0x1E, 0x58, 0xE9, 3814 0x85, 0x1E, 0x58, 0xE9,
3815 3815
38160x9B, 0x3B, 0x33, 0xDF, 3816 0x9B, 0x3B, 0x33, 0xDF,
38170x20, 0x20, 0x42, 0xAF, 3817 0x20, 0x20, 0x42, 0xAF,
3818 3818
38190x30, 0x42, 0x56, 0x9F, 3819 0x30, 0x42, 0x56, 0x9F,
38200x80, 0x3E, 0x57, 0xE9, 3820 0x80, 0x3E, 0x57, 0xE9,
3821 3821
38220x3F, 0x8F, 0x51, 0x9F, 3822 0x3F, 0x8F, 0x51, 0x9F,
38230x30, 0x80, 0x5F, 0xE9, 3823 0x30, 0x80, 0x5F, 0xE9,
3824 3824
38250x28, 0x28, 0x24, 0xAF, 3825 0x28, 0x28, 0x24, 0xAF,
38260x81, 0x1E, 0x57, 0xE9, 3826 0x81, 0x1E, 0x57, 0xE9,
3827 3827
38280x05, 0x47, 0x57, 0xBF, 3828 0x05, 0x47, 0x57, 0xBF,
38290x0D, 0x47, 0x4F, 0xBF, 3829 0x0D, 0x47, 0x4F, 0xBF,
3830 3830
38310x88, 0x80, 0x58, 0xE9, 3831 0x88, 0x80, 0x58, 0xE9,
38320x1B, 0x29, 0x1B, 0xDF, 3832 0x1B, 0x29, 0x1B, 0xDF,
3833 3833
38340x30, 0x1D, 0x6F, 0x8F, 3834 0x30, 0x1D, 0x6F, 0x8F,
38350x3A, 0x30, 0x4F, 0xE9, 3835 0x3A, 0x30, 0x4F, 0xE9,
3836 3836
38370x1C, 0x30, 0x26, 0xDF, 3837 0x1C, 0x30, 0x26, 0xDF,
38380x09, 0xE3, 3838 0x09, 0xE3,
38390x3B, 0x05, 3839 0x3B, 0x05,
3840 3840
38410x3E, 0x50, 0x56, 0x9F, 3841 0x3E, 0x50, 0x56, 0x9F,
38420x3B, 0x3F, 0x4F, 0xE9, 3842 0x3B, 0x3F, 0x4F, 0xE9,
3843 3843
38440x1E, 0x8F, 0x51, 0x9F, 3844 0x1E, 0x8F, 0x51, 0x9F,
38450x00, 0xE0, 3845 0x00, 0xE0,
38460xAC, 0x20, 3846 0xAC, 0x20,
3847 3847
38480x2D, 0x44, 0x4C, 0xB4, 3848 0x2D, 0x44, 0x4C, 0xB4,
38490x2C, 0x1C, 0xC0, 0xAF, 3849 0x2C, 0x1C, 0xC0, 0xAF,
3850 3850
38510x25, 0x44, 0x54, 0xB4, 3851 0x25, 0x44, 0x54, 0xB4,
38520x00, 0xE0, 3852 0x00, 0xE0,
38530xC8, 0x30, 3853 0xC8, 0x30,
3854 3854
38550x30, 0x46, 0x30, 0xAF, 3855 0x30, 0x46, 0x30, 0xAF,
38560x1B, 0x1B, 0x48, 0xAF, 3856 0x1B, 0x1B, 0x48, 0xAF,
3857 3857
38580x00, 0xE0, 3858 0x00, 0xE0,
38590x25, 0x20, 3859 0x25, 0x20,
38600x38, 0x2C, 0x4F, 0xE9, 3860 0x38, 0x2C, 0x4F, 0xE9,
3861 3861
38620x86, 0x80, 0x57, 0xE9, 3862 0x86, 0x80, 0x57, 0xE9,
38630x38, 0x1D, 0x6F, 0x8F, 3863 0x38, 0x1D, 0x6F, 0x8F,
3864 3864
38650x28, 0x74, 3865 0x28, 0x74,
38660x00, 0xE0, 3866 0x00, 0xE0,
38670x0D, 0x44, 0x4C, 0xB0, 3867 0x0D, 0x44, 0x4C, 0xB0,
3868 3868
38690x05, 0x44, 0x54, 0xB0, 3869 0x05, 0x44, 0x54, 0xB0,
38700x2D, 0x20, 3870 0x2D, 0x20,
38710x9B, 0x10, 3871 0x9B, 0x10,
3872 3872
38730x82, 0x3E, 0x57, 0xE9, 3873 0x82, 0x3E, 0x57, 0xE9,
38740x32, 0xF0, 0x1B, 0xCD, 3874 0x32, 0xF0, 0x1B, 0xCD,
3875 3875
38760x1E, 0xBD, 0x59, 0x9F, 3876 0x1E, 0xBD, 0x59, 0x9F,
38770x83, 0x1E, 0x57, 0xE9, 3877 0x83, 0x1E, 0x57, 0xE9,
3878 3878
38790x38, 0x47, 0x38, 0xAF, 3879 0x38, 0x47, 0x38, 0xAF,
38800x34, 0x20, 3880 0x34, 0x20,
38810x2A, 0x30, 3881 0x2A, 0x30,
3882 3882
38830x00, 0xE0, 3883 0x00, 0xE0,
38840x0D, 0x20, 3884 0x0D, 0x20,
38850x32, 0x20, 3885 0x32, 0x20,
38860x05, 0x20, 3886 0x05, 0x20,
3887 3887
38880x87, 0x80, 0x57, 0xE9, 3888 0x87, 0x80, 0x57, 0xE9,
38890x1F, 0x54, 0x57, 0x9F, 3889 0x1F, 0x54, 0x57, 0x9F,
3890 3890
38910x17, 0x42, 0x56, 0x9F, 3891 0x17, 0x42, 0x56, 0x9F,
38920x00, 0xE0, 3892 0x00, 0xE0,
38930x3B, 0x6A, 3893 0x3B, 0x6A,
3894 3894
38950x3F, 0x8F, 0x51, 0x9F, 3895 0x3F, 0x8F, 0x51, 0x9F,
38960x37, 0x1E, 0x4F, 0xE9, 3896 0x37, 0x1E, 0x4F, 0xE9,
3897 3897
38980x37, 0x32, 0x2A, 0xAF, 3898 0x37, 0x32, 0x2A, 0xAF,
38990x00, 0xE0, 3899 0x00, 0xE0,
39000x32, 0x00, 3900 0x32, 0x00,
3901 3901
39020x00, 0x80, 0x00, 0xE8, 3902 0x00, 0x80, 0x00, 0xE8,
39030x27, 0xC0, 0x44, 0xC0, 3903 0x27, 0xC0, 0x44, 0xC0,
3904 3904
39050x36, 0x1F, 0x4F, 0xE9, 3905 0x36, 0x1F, 0x4F, 0xE9,
39060x1F, 0x1F, 0x26, 0xDF, 3906 0x1F, 0x1F, 0x26, 0xDF,
3907 3907
39080x37, 0x1B, 0x37, 0xBF, 3908 0x37, 0x1B, 0x37, 0xBF,
39090x17, 0x26, 0x17, 0xDF, 3909 0x17, 0x26, 0x17, 0xDF,
3910 3910
39110x3E, 0x17, 0x4F, 0xE9, 3911 0x3E, 0x17, 0x4F, 0xE9,
39120x3F, 0x3F, 0x4F, 0xE9, 3912 0x3F, 0x3F, 0x4F, 0xE9,
3913 3913
39140x34, 0x1F, 0x34, 0xAF, 3914 0x34, 0x1F, 0x34, 0xAF,
39150x2B, 0x05, 3915 0x2B, 0x05,
39160xA7, 0x20, 3916 0xA7, 0x20,
3917 3917
39180x33, 0x2B, 0x37, 0xDF, 3918 0x33, 0x2B, 0x37, 0xDF,
39190x27, 0x17, 0xC0, 0xAF, 3919 0x27, 0x17, 0xC0, 0xAF,
3920 3920
39210x34, 0x80, 0x4F, 0xE9, 3921 0x34, 0x80, 0x4F, 0xE9,
39220x00, 0x80, 0x00, 0xE8, 3922 0x00, 0x80, 0x00, 0xE8,
3923 3923
39240x2D, 0x21, 0x1A, 0xB0, 3924 0x2D, 0x21, 0x1A, 0xB0,
39250x25, 0x21, 0x31, 0xB0, 3925 0x25, 0x21, 0x31, 0xB0,
3926 3926
39270x0D, 0x21, 0x1A, 0xB2, 3927 0x0D, 0x21, 0x1A, 0xB2,
39280x05, 0x21, 0x31, 0xB2, 3928 0x05, 0x21, 0x31, 0xB2,
3929 3929
39300x03, 0x80, 0x2A, 0xEA, 3930 0x03, 0x80, 0x2A, 0xEA,
39310x17, 0xC1, 0x2B, 0xBD, 3931 0x17, 0xC1, 0x2B, 0xBD,
3932 3932
39330x2D, 0x20, 3933 0x2D, 0x20,
39340x25, 0x20, 3934 0x25, 0x20,
39350x05, 0x20, 3935 0x05, 0x20,
39360x0D, 0x20, 3936 0x0D, 0x20,
3937 3937
39380xB3, 0x68, 3938 0xB3, 0x68,
39390x97, 0x25, 3939 0x97, 0x25,
39400x00, 0x80, 0x00, 0xE8, 3940 0x00, 0x80, 0x00, 0xE8,
3941 3941
39420x33, 0xC0, 0x33, 0xAF, 3942 0x33, 0xC0, 0x33, 0xAF,
39430x2F, 0xC0, 0x21, 0xC0, 3943 0x2F, 0xC0, 0x21, 0xC0,
3944 3944
39450x16, 0x42, 0x56, 0x9F, 3945 0x16, 0x42, 0x56, 0x9F,
39460x3C, 0x27, 0x4F, 0xE9, 3946 0x3C, 0x27, 0x4F, 0xE9,
3947 3947
39480x1E, 0x62, 0x57, 0x9F, 3948 0x1E, 0x62, 0x57, 0x9F,
39490x00, 0x80, 0x00, 0xE8, 3949 0x00, 0x80, 0x00, 0xE8,
3950 3950
39510x25, 0x21, 0x31, 0xB4, 3951 0x25, 0x21, 0x31, 0xB4,
39520x2D, 0x21, 0x1A, 0xB4, 3952 0x2D, 0x21, 0x1A, 0xB4,
3953 3953
39540x3F, 0x2F, 0x5D, 0x9F, 3954 0x3F, 0x2F, 0x5D, 0x9F,
39550x00, 0x80, 0x00, 0xE8, 3955 0x00, 0x80, 0x00, 0xE8,
3956 3956
39570x33, 0x05, 3957 0x33, 0x05,
39580x00, 0xE0, 3958 0x00, 0xE0,
39590x28, 0x19, 0x60, 0xEC, 3959 0x28, 0x19, 0x60, 0xEC,
3960 3960
39610x0D, 0x21, 0x1A, 0xB6, 3961 0x0D, 0x21, 0x1A, 0xB6,
39620x05, 0x21, 0x31, 0xB6, 3962 0x05, 0x21, 0x31, 0xB6,
3963 3963
39640x37, 0x0F, 0x5C, 0x9F, 3964 0x37, 0x0F, 0x5C, 0x9F,
39650x00, 0xE0, 3965 0x00, 0xE0,
39660x2F, 0x20, 3966 0x2F, 0x20,
3967 3967
39680x23, 0x3B, 0x33, 0xAD, 3968 0x23, 0x3B, 0x33, 0xAD,
39690x1E, 0x26, 0x1E, 0xDF, 3969 0x1E, 0x26, 0x1E, 0xDF,
3970 3970
39710xA7, 0x1E, 0x4F, 0xE9, 3971 0xA7, 0x1E, 0x4F, 0xE9,
39720x17, 0x26, 0x16, 0xDF, 3972 0x17, 0x26, 0x16, 0xDF,
3973 3973
39740x2D, 0x20, 3974 0x2D, 0x20,
39750x00, 0xE0, 3975 0x00, 0xE0,
39760xA8, 0x3F, 0x4F, 0xE9, 3976 0xA8, 0x3F, 0x4F, 0xE9,
3977 3977
39780x2F, 0x2F, 0x1E, 0xAF, 3978 0x2F, 0x2F, 0x1E, 0xAF,
39790x25, 0x20, 3979 0x25, 0x20,
39800x00, 0xE0, 3980 0x00, 0xE0,
3981 3981
39820xA4, 0x16, 0x4F, 0xE9, 3982 0xA4, 0x16, 0x4F, 0xE9,
39830x0F, 0xC0, 0x21, 0xC2, 3983 0x0F, 0xC0, 0x21, 0xC2,
3984 3984
39850xA6, 0x80, 0x4F, 0xE9, 3985 0xA6, 0x80, 0x4F, 0xE9,
39860x1F, 0x62, 0x57, 0x9F, 3986 0x1F, 0x62, 0x57, 0x9F,
3987 3987
39880x0D, 0x20, 3988 0x0D, 0x20,
39890x05, 0x20, 3989 0x05, 0x20,
39900x2F, 0xC0, 0x21, 0xC6, 3990 0x2F, 0xC0, 0x21, 0xC6,
3991 3991
39920x2D, 0x44, 0x4C, 0xB6, 3992 0x2D, 0x44, 0x4C, 0xB6,
39930x25, 0x44, 0x54, 0xB6, 3993 0x25, 0x44, 0x54, 0xB6,
3994 3994
39950x3F, 0x2F, 0x5D, 0x9F, 3995 0x3F, 0x2F, 0x5D, 0x9F,
39960x00, 0xE0, 3996 0x00, 0xE0,
39970x0F, 0x20, 3997 0x0F, 0x20,
3998 3998
39990x2D, 0x20, 3999 0x2D, 0x20,
40000x25, 0x20, 4000 0x25, 0x20,
40010x07, 0xC0, 0x44, 0xC6, 4001 0x07, 0xC0, 0x44, 0xC6,
4002 4002
40030x17, 0x50, 0x56, 0x9F, 4003 0x17, 0x50, 0x56, 0x9F,
40040xA5, 0x37, 0x4F, 0xE9, 4004 0xA5, 0x37, 0x4F, 0xE9,
4005 4005
40060x06, 0xC0, 0x21, 0xC4, 4006 0x06, 0xC0, 0x21, 0xC4,
40070x0F, 0x17, 0x0F, 0xAF, 4007 0x0F, 0x17, 0x0F, 0xAF,
4008 4008
40090x37, 0x0F, 0x5C, 0x9F, 4009 0x37, 0x0F, 0x5C, 0x9F,
40100x00, 0x80, 0x00, 0xE8, 4010 0x00, 0x80, 0x00, 0xE8,
4011 4011
40120x1E, 0x62, 0x57, 0x9F, 4012 0x1E, 0x62, 0x57, 0x9F,
40130x00, 0x80, 0x00, 0xE8, 4013 0x00, 0x80, 0x00, 0xE8,
4014 4014
40150x3E, 0x3D, 0x5D, 0x9F, 4015 0x3E, 0x3D, 0x5D, 0x9F,
40160x00, 0xE0, 4016 0x00, 0xE0,
40170x07, 0x20, 4017 0x07, 0x20,
4018 4018
40190x2F, 0x20, 4019 0x2F, 0x20,
40200x00, 0xE0, 4020 0x00, 0xE0,
40210xA3, 0x0F, 0x4F, 0xE9, 4021 0xA3, 0x0F, 0x4F, 0xE9,
4022 4022
40230x06, 0x20, 4023 0x06, 0x20,
40240x00, 0xE0, 4024 0x00, 0xE0,
40250x1F, 0x26, 0x1F, 0xDF, 4025 0x1F, 0x26, 0x1F, 0xDF,
4026 4026
40270x17, 0x26, 0x17, 0xDF, 4027 0x17, 0x26, 0x17, 0xDF,
40280xA1, 0x1F, 0x4F, 0xE9, 4028 0xA1, 0x1F, 0x4F, 0xE9,
4029 4029
40300x1E, 0x26, 0x1E, 0xDF, 4030 0x1E, 0x26, 0x1E, 0xDF,
40310x9D, 0x1E, 0x4F, 0xE9, 4031 0x9D, 0x1E, 0x4F, 0xE9,
4032 4032
40330x35, 0x17, 0x4F, 0xE9, 4033 0x35, 0x17, 0x4F, 0xE9,
40340xA2, 0x3F, 0x4F, 0xE9, 4034 0xA2, 0x3F, 0x4F, 0xE9,
4035 4035
40360x06, 0x06, 0x1F, 0xAF, 4036 0x06, 0x06, 0x1F, 0xAF,
40370x39, 0x37, 0x4F, 0xE9, 4037 0x39, 0x37, 0x4F, 0xE9,
4038 4038
40390x2F, 0x2F, 0x17, 0xAF, 4039 0x2F, 0x2F, 0x17, 0xAF,
40400x07, 0x07, 0x1E, 0xAF, 4040 0x07, 0x07, 0x1E, 0xAF,
4041 4041
40420xA0, 0x80, 0x4F, 0xE9, 4042 0xA0, 0x80, 0x4F, 0xE9,
40430x9E, 0x3E, 0x4F, 0xE9, 4043 0x9E, 0x3E, 0x4F, 0xE9,
4044 4044
40450x31, 0x80, 0x4F, 0xE9, 4045 0x31, 0x80, 0x4F, 0xE9,
40460x9C, 0x80, 0x4F, 0xE9, 4046 0x9C, 0x80, 0x4F, 0xE9,
4047 4047
40480x00, 0x80, 0x00, 0xE8, 4048 0x00, 0x80, 0x00, 0xE8,
40490x57, 0x39, 0x20, 0xE9, 4049 0x57, 0x39, 0x20, 0xE9,
4050 4050
40510x16, 0x28, 0x20, 0xE9, 4051 0x16, 0x28, 0x20, 0xE9,
40520x1D, 0x3B, 0x20, 0xE9, 4052 0x1D, 0x3B, 0x20, 0xE9,
4053 4053
40540x1E, 0x2B, 0x20, 0xE9, 4054 0x1E, 0x2B, 0x20, 0xE9,
40550x2B, 0x32, 0x20, 0xE9, 4055 0x2B, 0x32, 0x20, 0xE9,
4056 4056
40570x1C, 0x23, 0x20, 0xE9, 4057 0x1C, 0x23, 0x20, 0xE9,
40580x57, 0x36, 0x20, 0xE9, 4058 0x57, 0x36, 0x20, 0xE9,
4059 4059
40600x00, 0x80, 0xA0, 0xE9, 4060 0x00, 0x80, 0xA0, 0xE9,
40610x40, 0x40, 0xD8, 0xEC, 4061 0x40, 0x40, 0xD8, 0xEC,
4062 4062
40630xFF, 0x80, 0xC0, 0xE9, 4063 0xFF, 0x80, 0xC0, 0xE9,
40640x90, 0xE2, 4064 0x90, 0xE2,
40650x00, 0xE0, 4065 0x00, 0xE0,
4066 4066
40670x63, 0xFF, 0x20, 0xEA, 4067 0x63, 0xFF, 0x20, 0xEA,
40680x19, 0xC8, 0xC1, 0xCD, 4068 0x19, 0xC8, 0xC1, 0xCD,
4069 4069
40700x1F, 0xD7, 0x18, 0xBD, 4070 0x1F, 0xD7, 0x18, 0xBD,
40710x3F, 0xD7, 0x22, 0xBD, 4071 0x3F, 0xD7, 0x22, 0xBD,
4072 4072
40730x9F, 0x41, 0x49, 0xBD, 4073 0x9F, 0x41, 0x49, 0xBD,
40740x00, 0x80, 0x00, 0xE8, 4074 0x00, 0x80, 0x00, 0xE8,
4075 4075
40760x25, 0x41, 0x49, 0xBD, 4076 0x25, 0x41, 0x49, 0xBD,
40770x2D, 0x41, 0x51, 0xBD, 4077 0x2D, 0x41, 0x51, 0xBD,
4078 4078
40790x0D, 0x80, 0x07, 0xEA, 4079 0x0D, 0x80, 0x07, 0xEA,
40800x00, 0x80, 0x00, 0xE8, 4080 0x00, 0x80, 0x00, 0xE8,
4081 4081
40820x35, 0x40, 0x48, 0xBD, 4082 0x35, 0x40, 0x48, 0xBD,
40830x3D, 0x40, 0x50, 0xBD, 4083 0x3D, 0x40, 0x50, 0xBD,
4084 4084
40850x00, 0x80, 0x00, 0xE8, 4085 0x00, 0x80, 0x00, 0xE8,
40860x25, 0x30, 4086 0x25, 0x30,
40870x2D, 0x30, 4087 0x2D, 0x30,
4088 4088
40890x35, 0x30, 4089 0x35, 0x30,
40900xB5, 0x30, 4090 0xB5, 0x30,
40910xBD, 0x30, 4091 0xBD, 0x30,
40920x3D, 0x30, 4092 0x3D, 0x30,
4093 4093
40940x9C, 0xA7, 0x5B, 0x9F, 4094 0x9C, 0xA7, 0x5B, 0x9F,
40950x00, 0x80, 0x00, 0xE8, 4095 0x00, 0x80, 0x00, 0xE8,
4096 4096
40970x00, 0x80, 0x00, 0xE8, 4097 0x00, 0x80, 0x00, 0xE8,
40980x00, 0x80, 0x00, 0xE8, 4098 0x00, 0x80, 0x00, 0xE8,
4099 4099
41000x00, 0x80, 0x00, 0xE8, 4100 0x00, 0x80, 0x00, 0xE8,
41010x00, 0x80, 0x00, 0xE8, 4101 0x00, 0x80, 0x00, 0xE8,
4102 4102
41030x00, 0x80, 0x00, 0xE8, 4103 0x00, 0x80, 0x00, 0xE8,
41040x00, 0x80, 0x00, 0xE8, 4104 0x00, 0x80, 0x00, 0xE8,
4105 4105
41060x00, 0x80, 0x00, 0xE8, 4106 0x00, 0x80, 0x00, 0xE8,
41070x00, 0x80, 0x00, 0xE8, 4107 0x00, 0x80, 0x00, 0xE8,
4108 4108
41090x62, 0xFF, 0x0A, 0xEA, 4109 0x62, 0xFF, 0x0A, 0xEA,
41100x00, 0x80, 0x00, 0xE8, 4110 0x00, 0x80, 0x00, 0xE8,
4111 4111
41120xC9, 0x41, 0xC8, 0xEC, 4112 0xC9, 0x41, 0xC8, 0xEC,
41130x42, 0xE1, 4113 0x42, 0xE1,
41140x00, 0xE0, 4114 0x00, 0xE0,
4115 4115
41160x60, 0xFF, 0x20, 0xEA, 4116 0x60, 0xFF, 0x20, 0xEA,
41170x00, 0x80, 0x00, 0xE8, 4117 0x00, 0x80, 0x00, 0xE8,
4118 4118
41190x00, 0x80, 0x00, 0xE8, 4119 0x00, 0x80, 0x00, 0xE8,
41200x00, 0x80, 0x00, 0xE8, 4120 0x00, 0x80, 0x00, 0xE8,
4121 4121
41220xC8, 0x40, 0xC0, 0xEC, 4122 0xC8, 0x40, 0xC0, 0xEC,
41230x00, 0x80, 0x00, 0xE8, 4123 0x00, 0x80, 0x00, 0xE8,
4124 4124
41250x5D, 0xFF, 0x20, 0xEA, 4125 0x5D, 0xFF, 0x20, 0xEA,
41260x00, 0x80, 0x00, 0xE8, 4126 0x00, 0x80, 0x00, 0xE8,
4127 4127
41280x00, 0x80, 0x00, 0xE8, 4128 0x00, 0x80, 0x00, 0xE8,
41290x00, 0x80, 0x00, 0xE8, 4129 0x00, 0x80, 0x00, 0xE8,
4130 4130
4131}; 4131};
4132 4132
4133static unsigned char warp_g200_tgzsf[] = { 4133static unsigned char warp_g200_tgzsf[] = {
4134 4134
41350x00, 0x80, 0x00, 0xE8, 4135 0x00, 0x80, 0x00, 0xE8,
41360x00, 0x80, 0x00, 0xE8, 4136 0x00, 0x80, 0x00, 0xE8,
4137 4137
41380x00, 0x80, 0x00, 0xE8, 4138 0x00, 0x80, 0x00, 0xE8,
41390x00, 0x80, 0x00, 0xE8, 4139 0x00, 0x80, 0x00, 0xE8,
4140 4140
41410x00, 0x80, 0x00, 0xE8, 4141 0x00, 0x80, 0x00, 0xE8,
41420x00, 0x80, 0x00, 0xE8, 4142 0x00, 0x80, 0x00, 0xE8,
4143 4143
41440x00, 0x80, 0x00, 0xE8, 4144 0x00, 0x80, 0x00, 0xE8,
41450x00, 0x80, 0x00, 0xE8, 4145 0x00, 0x80, 0x00, 0xE8,
4146 4146
41470x00, 0x80, 0x00, 0xE8, 4147 0x00, 0x80, 0x00, 0xE8,
41480x00, 0x80, 0x00, 0xE8, 4148 0x00, 0x80, 0x00, 0xE8,
4149 4149
41500x00, 0x80, 0x00, 0xE8, 4150 0x00, 0x80, 0x00, 0xE8,
41510x00, 0x80, 0x00, 0xE8, 4151 0x00, 0x80, 0x00, 0xE8,
4152 4152
41530x00, 0x80, 0x00, 0xE8, 4153 0x00, 0x80, 0x00, 0xE8,
41540x00, 0x80, 0x00, 0xE8, 4154 0x00, 0x80, 0x00, 0xE8,
4155 4155
41560x00, 0x80, 0x00, 0xE8, 4156 0x00, 0x80, 0x00, 0xE8,
41570x00, 0x80, 0x00, 0xE8, 4157 0x00, 0x80, 0x00, 0xE8,
4158 4158
41590x00, 0x80, 0x00, 0xE8, 4159 0x00, 0x80, 0x00, 0xE8,
41600x00, 0x80, 0x00, 0xE8, 4160 0x00, 0x80, 0x00, 0xE8,
4161 4161
41620x00, 0x80, 0x00, 0xE8, 4162 0x00, 0x80, 0x00, 0xE8,
41630x00, 0x80, 0x00, 0xE8, 4163 0x00, 0x80, 0x00, 0xE8,
4164 4164
41650x00, 0x80, 0x00, 0xE8, 4165 0x00, 0x80, 0x00, 0xE8,
41660x00, 0x80, 0x00, 0xE8, 4166 0x00, 0x80, 0x00, 0xE8,
4167 4167
41680x00, 0x80, 0x00, 0xE8, 4168 0x00, 0x80, 0x00, 0xE8,
41690x00, 0x80, 0x00, 0xE8, 4169 0x00, 0x80, 0x00, 0xE8,
4170 4170
41710x00, 0x80, 0x00, 0xE8, 4171 0x00, 0x80, 0x00, 0xE8,
41720x00, 0x80, 0x00, 0xE8, 4172 0x00, 0x80, 0x00, 0xE8,
4173 4173
41740x00, 0x98, 0xA0, 0xE9, 4174 0x00, 0x98, 0xA0, 0xE9,
41750x40, 0x40, 0xD8, 0xEC, 4175 0x40, 0x40, 0xD8, 0xEC,
4176 4176
41770xFF, 0x80, 0xC0, 0xE9, 4177 0xFF, 0x80, 0xC0, 0xE9,
41780x00, 0x80, 0x00, 0xE8, 4178 0x00, 0x80, 0x00, 0xE8,
4179 4179
41800x1F, 0xD7, 0x18, 0xBD, 4180 0x1F, 0xD7, 0x18, 0xBD,
41810x3F, 0xD7, 0x22, 0xBD, 4181 0x3F, 0xD7, 0x22, 0xBD,
4182 4182
41830x81, 0x04, 4183 0x81, 0x04,
41840x89, 0x04, 4184 0x89, 0x04,
41850x01, 0x04, 4185 0x01, 0x04,
41860x09, 0x04, 4186 0x09, 0x04,
4187 4187
41880xC9, 0x41, 0xC0, 0xEC, 4188 0xC9, 0x41, 0xC0, 0xEC,
41890x11, 0x04, 4189 0x11, 0x04,
41900x00, 0xE0, 4190 0x00, 0xE0,
4191 4191
41920x41, 0xCC, 0x41, 0xCD, 4192 0x41, 0xCC, 0x41, 0xCD,
41930x49, 0xCC, 0x49, 0xCD, 4193 0x49, 0xCC, 0x49, 0xCD,
4194 4194
41950xD1, 0x41, 0xC0, 0xEC, 4195 0xD1, 0x41, 0xC0, 0xEC,
41960x51, 0xCC, 0x51, 0xCD, 4196 0x51, 0xCC, 0x51, 0xCD,
4197 4197
41980x80, 0x04, 4198 0x80, 0x04,
41990x10, 0x04, 4199 0x10, 0x04,
42000x08, 0x04, 4200 0x08, 0x04,
42010x00, 0xE0, 4201 0x00, 0xE0,
4202 4202
42030x00, 0xCC, 0xC0, 0xCD, 4203 0x00, 0xCC, 0xC0, 0xCD,
42040xD1, 0x49, 0xC0, 0xEC, 4204 0xD1, 0x49, 0xC0, 0xEC,
4205 4205
42060x8A, 0x1F, 0x20, 0xE9, 4206 0x8A, 0x1F, 0x20, 0xE9,
42070x8B, 0x3F, 0x20, 0xE9, 4207 0x8B, 0x3F, 0x20, 0xE9,
4208 4208
42090x41, 0x3C, 0x41, 0xAD, 4209 0x41, 0x3C, 0x41, 0xAD,
42100x49, 0x3C, 0x49, 0xAD, 4210 0x49, 0x3C, 0x49, 0xAD,
4211 4211
42120x10, 0xCC, 0x10, 0xCD, 4212 0x10, 0xCC, 0x10, 0xCD,
42130x08, 0xCC, 0x08, 0xCD, 4213 0x08, 0xCC, 0x08, 0xCD,
4214 4214
42150xB9, 0x41, 0x49, 0xBB, 4215 0xB9, 0x41, 0x49, 0xBB,
42160x1F, 0xF0, 0x41, 0xCD, 4216 0x1F, 0xF0, 0x41, 0xCD,
4217 4217
42180x51, 0x3C, 0x51, 0xAD, 4218 0x51, 0x3C, 0x51, 0xAD,
42190x00, 0x98, 0x80, 0xE9, 4219 0x00, 0x98, 0x80, 0xE9,
4220 4220
42210x8F, 0x80, 0x07, 0xEA, 4221 0x8F, 0x80, 0x07, 0xEA,
42220x24, 0x1F, 0x20, 0xE9, 4222 0x24, 0x1F, 0x20, 0xE9,
4223 4223
42240x21, 0x45, 0x80, 0xE8, 4224 0x21, 0x45, 0x80, 0xE8,
42250x1A, 0x4D, 0x80, 0xE8, 4225 0x1A, 0x4D, 0x80, 0xE8,
4226 4226
42270x31, 0x55, 0x80, 0xE8, 4227 0x31, 0x55, 0x80, 0xE8,
42280x00, 0x80, 0x00, 0xE8, 4228 0x00, 0x80, 0x00, 0xE8,
4229 4229
42300x15, 0x41, 0x49, 0xBD, 4230 0x15, 0x41, 0x49, 0xBD,
42310x1D, 0x41, 0x51, 0xBD, 4231 0x1D, 0x41, 0x51, 0xBD,
4232 4232
42330x2E, 0x41, 0x2A, 0xB8, 4233 0x2E, 0x41, 0x2A, 0xB8,
42340x34, 0x53, 0xA0, 0xE8, 4234 0x34, 0x53, 0xA0, 0xE8,
4235 4235
42360x15, 0x30, 4236 0x15, 0x30,
42370x1D, 0x30, 4237 0x1D, 0x30,
42380x58, 0xE3, 4238 0x58, 0xE3,
42390x00, 0xE0, 4239 0x00, 0xE0,
4240 4240
42410xB5, 0x40, 0x48, 0xBD, 4241 0xB5, 0x40, 0x48, 0xBD,
42420x3D, 0x40, 0x50, 0xBD, 4242 0x3D, 0x40, 0x50, 0xBD,
4243 4243
42440x24, 0x43, 0xA0, 0xE8, 4244 0x24, 0x43, 0xA0, 0xE8,
42450x2C, 0x4B, 0xA0, 0xE8, 4245 0x2C, 0x4B, 0xA0, 0xE8,
4246 4246
42470x15, 0x72, 4247 0x15, 0x72,
42480x09, 0xE3, 4248 0x09, 0xE3,
42490x00, 0xE0, 4249 0x00, 0xE0,
42500x1D, 0x72, 4250 0x1D, 0x72,
4251 4251
42520x35, 0x30, 4252 0x35, 0x30,
42530xB5, 0x30, 4253 0xB5, 0x30,
42540xBD, 0x30, 4254 0xBD, 0x30,
42550x3D, 0x30, 4255 0x3D, 0x30,
4256 4256
42570x9C, 0x97, 0x57, 0x9F, 4257 0x9C, 0x97, 0x57, 0x9F,
42580x00, 0x80, 0x00, 0xE8, 4258 0x00, 0x80, 0x00, 0xE8,
4259 4259
42600x6C, 0x64, 0xC8, 0xEC, 4260 0x6C, 0x64, 0xC8, 0xEC,
42610x98, 0xE1, 4261 0x98, 0xE1,
42620xB5, 0x05, 4262 0xB5, 0x05,
4263 4263
42640xBD, 0x05, 4264 0xBD, 0x05,
42650x2E, 0x30, 4265 0x2E, 0x30,
42660x32, 0xC0, 0xA0, 0xE8, 4266 0x32, 0xC0, 0xA0, 0xE8,
4267 4267
42680x33, 0xC0, 0xA0, 0xE8, 4268 0x33, 0xC0, 0xA0, 0xE8,
42690x74, 0x64, 0xC8, 0xEC, 4269 0x74, 0x64, 0xC8, 0xEC,
4270 4270
42710x40, 0x3C, 0x40, 0xAD, 4271 0x40, 0x3C, 0x40, 0xAD,
42720x32, 0x6A, 4272 0x32, 0x6A,
42730x2A, 0x30, 4273 0x2A, 0x30,
4274 4274
42750x20, 0x73, 4275 0x20, 0x73,
42760x33, 0x6A, 4276 0x33, 0x6A,
42770x00, 0xE0, 4277 0x00, 0xE0,
42780x28, 0x73, 4278 0x28, 0x73,
4279 4279
42800x1C, 0x72, 4280 0x1C, 0x72,
42810x83, 0xE2, 4281 0x83, 0xE2,
42820x7B, 0x80, 0x15, 0xEA, 4282 0x7B, 0x80, 0x15, 0xEA,
4283 4283
42840xB8, 0x3D, 0x28, 0xDF, 4284 0xB8, 0x3D, 0x28, 0xDF,
42850x30, 0x35, 0x20, 0xDF, 4285 0x30, 0x35, 0x20, 0xDF,
4286 4286
42870x40, 0x30, 4287 0x40, 0x30,
42880x00, 0xE0, 4288 0x00, 0xE0,
42890xCC, 0xE2, 4289 0xCC, 0xE2,
42900x64, 0x72, 4290 0x64, 0x72,
4291 4291
42920x25, 0x42, 0x52, 0xBF, 4292 0x25, 0x42, 0x52, 0xBF,
42930x2D, 0x42, 0x4A, 0xBF, 4293 0x2D, 0x42, 0x4A, 0xBF,
4294 4294
42950x30, 0x2E, 0x30, 0xDF, 4295 0x30, 0x2E, 0x30, 0xDF,
42960x38, 0x2E, 0x38, 0xDF, 4296 0x38, 0x2E, 0x38, 0xDF,
4297 4297
42980x18, 0x1D, 0x45, 0xE9, 4298 0x18, 0x1D, 0x45, 0xE9,
42990x1E, 0x15, 0x45, 0xE9, 4299 0x1E, 0x15, 0x45, 0xE9,
4300 4300
43010x2B, 0x49, 0x51, 0xBD, 4301 0x2B, 0x49, 0x51, 0xBD,
43020x00, 0xE0, 4302 0x00, 0xE0,
43030x1F, 0x73, 4303 0x1F, 0x73,
4304 4304
43050x38, 0x38, 0x40, 0xAF, 4305 0x38, 0x38, 0x40, 0xAF,
43060x30, 0x30, 0x40, 0xAF, 4306 0x30, 0x30, 0x40, 0xAF,
4307 4307
43080x24, 0x1F, 0x24, 0xDF, 4308 0x24, 0x1F, 0x24, 0xDF,
43090x1D, 0x32, 0x20, 0xE9, 4309 0x1D, 0x32, 0x20, 0xE9,
4310 4310
43110x2C, 0x1F, 0x2C, 0xDF, 4311 0x2C, 0x1F, 0x2C, 0xDF,
43120x1A, 0x33, 0x20, 0xE9, 4312 0x1A, 0x33, 0x20, 0xE9,
4313 4313
43140xB0, 0x10, 4314 0xB0, 0x10,
43150x08, 0xE3, 4315 0x08, 0xE3,
43160x40, 0x10, 4316 0x40, 0x10,
43170xB8, 0x10, 4317 0xB8, 0x10,
4318 4318
43190x26, 0xF0, 0x30, 0xCD, 4319 0x26, 0xF0, 0x30, 0xCD,
43200x2F, 0xF0, 0x38, 0xCD, 4320 0x2F, 0xF0, 0x38, 0xCD,
4321 4321
43220x2B, 0x80, 0x20, 0xE9, 4322 0x2B, 0x80, 0x20, 0xE9,
43230x2A, 0x80, 0x20, 0xE9, 4323 0x2A, 0x80, 0x20, 0xE9,
4324 4324
43250xA6, 0x20, 4325 0xA6, 0x20,
43260x88, 0xE2, 4326 0x88, 0xE2,
43270x00, 0xE0, 4327 0x00, 0xE0,
43280xAF, 0x20, 4328 0xAF, 0x20,
4329 4329
43300x28, 0x2A, 0x26, 0xAF, 4330 0x28, 0x2A, 0x26, 0xAF,
43310x20, 0x2A, 0xC0, 0xAF, 4331 0x20, 0x2A, 0xC0, 0xAF,
4332 4332
43330x34, 0x1F, 0x34, 0xDF, 4333 0x34, 0x1F, 0x34, 0xDF,
43340x46, 0x24, 0x46, 0xDF, 4334 0x46, 0x24, 0x46, 0xDF,
4335 4335
43360x28, 0x30, 0x80, 0xBF, 4336 0x28, 0x30, 0x80, 0xBF,
43370x20, 0x38, 0x80, 0xBF, 4337 0x20, 0x38, 0x80, 0xBF,
4338 4338
43390x47, 0x24, 0x47, 0xDF, 4339 0x47, 0x24, 0x47, 0xDF,
43400x4E, 0x2C, 0x4E, 0xDF, 4340 0x4E, 0x2C, 0x4E, 0xDF,
4341 4341
43420x4F, 0x2C, 0x4F, 0xDF, 4342 0x4F, 0x2C, 0x4F, 0xDF,
43430x56, 0x34, 0x56, 0xDF, 4343 0x56, 0x34, 0x56, 0xDF,
4344 4344
43450x28, 0x15, 0x28, 0xDF, 4345 0x28, 0x15, 0x28, 0xDF,
43460x20, 0x1D, 0x20, 0xDF, 4346 0x20, 0x1D, 0x20, 0xDF,
4347 4347
43480x57, 0x34, 0x57, 0xDF, 4348 0x57, 0x34, 0x57, 0xDF,
43490x00, 0xE0, 4349 0x00, 0xE0,
43500x1D, 0x05, 4350 0x1D, 0x05,
4351 4351
43520x04, 0x80, 0x10, 0xEA, 4352 0x04, 0x80, 0x10, 0xEA,
43530x89, 0xE2, 4353 0x89, 0xE2,
43540x2B, 0x30, 4354 0x2B, 0x30,
4355 4355
43560x3F, 0xC1, 0x1D, 0xBD, 4356 0x3F, 0xC1, 0x1D, 0xBD,
43570x00, 0x80, 0x00, 0xE8, 4357 0x00, 0x80, 0x00, 0xE8,
4358 4358
43590x00, 0x80, 0x00, 0xE8, 4359 0x00, 0x80, 0x00, 0xE8,
43600x00, 0x80, 0x00, 0xE8, 4360 0x00, 0x80, 0x00, 0xE8,
4361 4361
43620xA0, 0x68, 4362 0xA0, 0x68,
43630xBF, 0x25, 4363 0xBF, 0x25,
43640x00, 0x80, 0x00, 0xE8, 4364 0x00, 0x80, 0x00, 0xE8,
4365 4365
43660x20, 0xC0, 0x20, 0xAF, 4366 0x20, 0xC0, 0x20, 0xAF,
43670x28, 0x05, 4367 0x28, 0x05,
43680x97, 0x74, 4368 0x97, 0x74,
4369 4369
43700x00, 0xE0, 4370 0x00, 0xE0,
43710x2A, 0x10, 4371 0x2A, 0x10,
43720x16, 0xC0, 0x20, 0xE9, 4372 0x16, 0xC0, 0x20, 0xE9,
4373 4373
43740x04, 0x80, 0x10, 0xEA, 4374 0x04, 0x80, 0x10, 0xEA,
43750x8C, 0xE2, 4375 0x8C, 0xE2,
43760x95, 0x05, 4376 0x95, 0x05,
4377 4377
43780x28, 0xC1, 0x28, 0xAD, 4378 0x28, 0xC1, 0x28, 0xAD,
43790x1F, 0xC1, 0x15, 0xBD, 4379 0x1F, 0xC1, 0x15, 0xBD,
4380 4380
43810x00, 0x80, 0x00, 0xE8, 4381 0x00, 0x80, 0x00, 0xE8,
43820x00, 0x80, 0x00, 0xE8, 4382 0x00, 0x80, 0x00, 0xE8,
4383 4383
43840xA8, 0x67, 4384 0xA8, 0x67,
43850x9F, 0x6B, 4385 0x9F, 0x6B,
43860x00, 0x80, 0x00, 0xE8, 4386 0x00, 0x80, 0x00, 0xE8,
4387 4387
43880x28, 0xC0, 0x28, 0xAD, 4388 0x28, 0xC0, 0x28, 0xAD,
43890x1D, 0x25, 4389 0x1D, 0x25,
43900x20, 0x05, 4390 0x20, 0x05,
4391 4391
43920x28, 0x32, 0x80, 0xAD, 4392 0x28, 0x32, 0x80, 0xAD,
43930x40, 0x2A, 0x40, 0xBD, 4393 0x40, 0x2A, 0x40, 0xBD,
4394 4394
43950x1C, 0x80, 0x20, 0xE9, 4395 0x1C, 0x80, 0x20, 0xE9,
43960x20, 0x33, 0x20, 0xAD, 4396 0x20, 0x33, 0x20, 0xAD,
4397 4397
43980x20, 0x73, 4398 0x20, 0x73,
43990x00, 0xE0, 4399 0x00, 0xE0,
44000xB6, 0x49, 0x51, 0xBB, 4400 0xB6, 0x49, 0x51, 0xBB,
4401 4401
44020x26, 0x2F, 0xB0, 0xE8, 4402 0x26, 0x2F, 0xB0, 0xE8,
44030x19, 0x20, 0x20, 0xE9, 4403 0x19, 0x20, 0x20, 0xE9,
4404 4404
44050x35, 0x20, 0x35, 0xDF, 4405 0x35, 0x20, 0x35, 0xDF,
44060x3D, 0x20, 0x3D, 0xDF, 4406 0x3D, 0x20, 0x3D, 0xDF,
4407 4407
44080x15, 0x20, 0x15, 0xDF, 4408 0x15, 0x20, 0x15, 0xDF,
44090x1D, 0x20, 0x1D, 0xDF, 4409 0x1D, 0x20, 0x1D, 0xDF,
4410 4410
44110x26, 0xD0, 0x26, 0xCD, 4411 0x26, 0xD0, 0x26, 0xCD,
44120x29, 0x49, 0x2A, 0xB8, 4412 0x29, 0x49, 0x2A, 0xB8,
4413 4413
44140x26, 0x40, 0x80, 0xBD, 4414 0x26, 0x40, 0x80, 0xBD,
44150x3B, 0x48, 0x50, 0xBD, 4415 0x3B, 0x48, 0x50, 0xBD,
4416 4416
44170x3E, 0x54, 0x57, 0x9F, 4417 0x3E, 0x54, 0x57, 0x9F,
44180x00, 0xE0, 4418 0x00, 0xE0,
44190x82, 0xE1, 4419 0x82, 0xE1,
4420 4420
44210x1E, 0xAF, 0x59, 0x9F, 4421 0x1E, 0xAF, 0x59, 0x9F,
44220x00, 0x80, 0x00, 0xE8, 4422 0x00, 0x80, 0x00, 0xE8,
4423 4423
44240x26, 0x30, 4424 0x26, 0x30,
44250x29, 0x30, 4425 0x29, 0x30,
44260x48, 0x3C, 0x48, 0xAD, 4426 0x48, 0x3C, 0x48, 0xAD,
4427 4427
44280x2B, 0x72, 4428 0x2B, 0x72,
44290xC2, 0xE1, 4429 0xC2, 0xE1,
44300x2C, 0xC0, 0x44, 0xC2, 4430 0x2C, 0xC0, 0x44, 0xC2,
4431 4431
44320x05, 0x24, 0x34, 0xBF, 4432 0x05, 0x24, 0x34, 0xBF,
44330x0D, 0x24, 0x2C, 0xBF, 4433 0x0D, 0x24, 0x2C, 0xBF,
4434 4434
44350x2D, 0x46, 0x4E, 0xBF, 4435 0x2D, 0x46, 0x4E, 0xBF,
44360x25, 0x46, 0x56, 0xBF, 4436 0x25, 0x46, 0x56, 0xBF,
4437 4437
44380x20, 0x1D, 0x6F, 0x8F, 4438 0x20, 0x1D, 0x6F, 0x8F,
44390x32, 0x3E, 0x5F, 0xE9, 4439 0x32, 0x3E, 0x5F, 0xE9,
4440 4440
44410x3E, 0x50, 0x56, 0x9F, 4441 0x3E, 0x50, 0x56, 0x9F,
44420x00, 0xE0, 4442 0x00, 0xE0,
44430x3B, 0x30, 4443 0x3B, 0x30,
4444 4444
44450x1E, 0x8F, 0x51, 0x9F, 4445 0x1E, 0x8F, 0x51, 0x9F,
44460x33, 0x1E, 0x5F, 0xE9, 4446 0x33, 0x1E, 0x5F, 0xE9,
4447 4447
44480x05, 0x44, 0x54, 0xB2, 4448 0x05, 0x44, 0x54, 0xB2,
44490x0D, 0x44, 0x4C, 0xB2, 4449 0x0D, 0x44, 0x4C, 0xB2,
4450 4450
44510x19, 0xC0, 0xB0, 0xE8, 4451 0x19, 0xC0, 0xB0, 0xE8,
44520x34, 0xC0, 0x44, 0xC4, 4452 0x34, 0xC0, 0x44, 0xC4,
4453 4453
44540x33, 0x73, 4454 0x33, 0x73,
44550x00, 0xE0, 4455 0x00, 0xE0,
44560x3E, 0x62, 0x57, 0x9F, 4456 0x3E, 0x62, 0x57, 0x9F,
4457 4457
44580x1E, 0xAF, 0x59, 0x9F, 4458 0x1E, 0xAF, 0x59, 0x9F,
44590x00, 0xE0, 4459 0x00, 0xE0,
44600x0D, 0x20, 4460 0x0D, 0x20,
4461 4461
44620x84, 0x3E, 0x58, 0xE9, 4462 0x84, 0x3E, 0x58, 0xE9,
44630x28, 0x1D, 0x6F, 0x8F, 4463 0x28, 0x1D, 0x6F, 0x8F,
4464 4464
44650x05, 0x20, 4465 0x05, 0x20,
44660x00, 0xE0, 4466 0x00, 0xE0,
44670x85, 0x1E, 0x58, 0xE9, 4467 0x85, 0x1E, 0x58, 0xE9,
4468 4468
44690x9B, 0x3B, 0x33, 0xDF, 4469 0x9B, 0x3B, 0x33, 0xDF,
44700x20, 0x20, 0x42, 0xAF, 4470 0x20, 0x20, 0x42, 0xAF,
4471 4471
44720x30, 0x42, 0x56, 0x9F, 4472 0x30, 0x42, 0x56, 0x9F,
44730x80, 0x3E, 0x57, 0xE9, 4473 0x80, 0x3E, 0x57, 0xE9,
4474 4474
44750x3F, 0x8F, 0x51, 0x9F, 4475 0x3F, 0x8F, 0x51, 0x9F,
44760x30, 0x80, 0x5F, 0xE9, 4476 0x30, 0x80, 0x5F, 0xE9,
4477 4477
44780x28, 0x28, 0x24, 0xAF, 4478 0x28, 0x28, 0x24, 0xAF,
44790x81, 0x1E, 0x57, 0xE9, 4479 0x81, 0x1E, 0x57, 0xE9,
4480 4480
44810x05, 0x47, 0x57, 0xBF, 4481 0x05, 0x47, 0x57, 0xBF,
44820x0D, 0x47, 0x4F, 0xBF, 4482 0x0D, 0x47, 0x4F, 0xBF,
4483 4483
44840x88, 0x80, 0x58, 0xE9, 4484 0x88, 0x80, 0x58, 0xE9,
44850x1B, 0x29, 0x1B, 0xDF, 4485 0x1B, 0x29, 0x1B, 0xDF,
4486 4486
44870x30, 0x1D, 0x6F, 0x8F, 4487 0x30, 0x1D, 0x6F, 0x8F,
44880x3A, 0x30, 0x4F, 0xE9, 4488 0x3A, 0x30, 0x4F, 0xE9,
4489 4489
44900x1C, 0x30, 0x26, 0xDF, 4490 0x1C, 0x30, 0x26, 0xDF,
44910x09, 0xE3, 4491 0x09, 0xE3,
44920x3B, 0x05, 4492 0x3B, 0x05,
4493 4493
44940x3E, 0x50, 0x56, 0x9F, 4494 0x3E, 0x50, 0x56, 0x9F,
44950x3B, 0x3F, 0x4F, 0xE9, 4495 0x3B, 0x3F, 0x4F, 0xE9,
4496 4496
44970x1E, 0x8F, 0x51, 0x9F, 4497 0x1E, 0x8F, 0x51, 0x9F,
44980x00, 0xE0, 4498 0x00, 0xE0,
44990xAC, 0x20, 4499 0xAC, 0x20,
4500 4500
45010x2D, 0x44, 0x4C, 0xB4, 4501 0x2D, 0x44, 0x4C, 0xB4,
45020x2C, 0x1C, 0xC0, 0xAF, 4502 0x2C, 0x1C, 0xC0, 0xAF,
4503 4503
45040x25, 0x44, 0x54, 0xB4, 4504 0x25, 0x44, 0x54, 0xB4,
45050x00, 0xE0, 4505 0x00, 0xE0,
45060xC8, 0x30, 4506 0xC8, 0x30,
4507 4507
45080x30, 0x46, 0x30, 0xAF, 4508 0x30, 0x46, 0x30, 0xAF,
45090x1B, 0x1B, 0x48, 0xAF, 4509 0x1B, 0x1B, 0x48, 0xAF,
4510 4510
45110x00, 0xE0, 4511 0x00, 0xE0,
45120x25, 0x20, 4512 0x25, 0x20,
45130x38, 0x2C, 0x4F, 0xE9, 4513 0x38, 0x2C, 0x4F, 0xE9,
4514 4514
45150x86, 0x80, 0x57, 0xE9, 4515 0x86, 0x80, 0x57, 0xE9,
45160x38, 0x1D, 0x6F, 0x8F, 4516 0x38, 0x1D, 0x6F, 0x8F,
4517 4517
45180x28, 0x74, 4518 0x28, 0x74,
45190x00, 0xE0, 4519 0x00, 0xE0,
45200x0D, 0x44, 0x4C, 0xB0, 4520 0x0D, 0x44, 0x4C, 0xB0,
4521 4521
45220x05, 0x44, 0x54, 0xB0, 4522 0x05, 0x44, 0x54, 0xB0,
45230x2D, 0x20, 4523 0x2D, 0x20,
45240x9B, 0x10, 4524 0x9B, 0x10,
4525 4525
45260x82, 0x3E, 0x57, 0xE9, 4526 0x82, 0x3E, 0x57, 0xE9,
45270x32, 0xF0, 0x1B, 0xCD, 4527 0x32, 0xF0, 0x1B, 0xCD,
4528 4528
45290x1E, 0xBD, 0x59, 0x9F, 4529 0x1E, 0xBD, 0x59, 0x9F,
45300x83, 0x1E, 0x57, 0xE9, 4530 0x83, 0x1E, 0x57, 0xE9,
4531 4531
45320x38, 0x47, 0x38, 0xAF, 4532 0x38, 0x47, 0x38, 0xAF,
45330x34, 0x20, 4533 0x34, 0x20,
45340x2A, 0x30, 4534 0x2A, 0x30,
4535 4535
45360x00, 0xE0, 4536 0x00, 0xE0,
45370x0D, 0x20, 4537 0x0D, 0x20,
45380x32, 0x20, 4538 0x32, 0x20,
45390x05, 0x20, 4539 0x05, 0x20,
4540 4540
45410x87, 0x80, 0x57, 0xE9, 4541 0x87, 0x80, 0x57, 0xE9,
45420x1F, 0x54, 0x57, 0x9F, 4542 0x1F, 0x54, 0x57, 0x9F,
4543 4543
45440x17, 0x42, 0x56, 0x9F, 4544 0x17, 0x42, 0x56, 0x9F,
45450x00, 0xE0, 4545 0x00, 0xE0,
45460x3B, 0x6A, 4546 0x3B, 0x6A,
4547 4547
45480x3F, 0x8F, 0x51, 0x9F, 4548 0x3F, 0x8F, 0x51, 0x9F,
45490x37, 0x1E, 0x4F, 0xE9, 4549 0x37, 0x1E, 0x4F, 0xE9,
4550 4550
45510x37, 0x32, 0x2A, 0xAF, 4551 0x37, 0x32, 0x2A, 0xAF,
45520x00, 0xE0, 4552 0x00, 0xE0,
45530x32, 0x00, 4553 0x32, 0x00,
4554 4554
45550x00, 0x80, 0x00, 0xE8, 4555 0x00, 0x80, 0x00, 0xE8,
45560x27, 0xC0, 0x44, 0xC0, 4556 0x27, 0xC0, 0x44, 0xC0,
4557 4557
45580x36, 0x1F, 0x4F, 0xE9, 4558 0x36, 0x1F, 0x4F, 0xE9,
45590x1F, 0x1F, 0x26, 0xDF, 4559 0x1F, 0x1F, 0x26, 0xDF,
4560 4560
45610x37, 0x1B, 0x37, 0xBF, 4561 0x37, 0x1B, 0x37, 0xBF,
45620x17, 0x26, 0x17, 0xDF, 4562 0x17, 0x26, 0x17, 0xDF,
4563 4563
45640x3E, 0x17, 0x4F, 0xE9, 4564 0x3E, 0x17, 0x4F, 0xE9,
45650x3F, 0x3F, 0x4F, 0xE9, 4565 0x3F, 0x3F, 0x4F, 0xE9,
4566 4566
45670x34, 0x1F, 0x34, 0xAF, 4567 0x34, 0x1F, 0x34, 0xAF,
45680x2B, 0x05, 4568 0x2B, 0x05,
45690xA7, 0x20, 4569 0xA7, 0x20,
4570 4570
45710x33, 0x2B, 0x37, 0xDF, 4571 0x33, 0x2B, 0x37, 0xDF,
45720x27, 0x17, 0xC0, 0xAF, 4572 0x27, 0x17, 0xC0, 0xAF,
4573 4573
45740x34, 0x80, 0x4F, 0xE9, 4574 0x34, 0x80, 0x4F, 0xE9,
45750x00, 0x80, 0x00, 0xE8, 4575 0x00, 0x80, 0x00, 0xE8,
4576 4576
45770x2D, 0x21, 0x1A, 0xB0, 4577 0x2D, 0x21, 0x1A, 0xB0,
45780x25, 0x21, 0x31, 0xB0, 4578 0x25, 0x21, 0x31, 0xB0,
4579 4579
45800x0D, 0x21, 0x1A, 0xB2, 4580 0x0D, 0x21, 0x1A, 0xB2,
45810x05, 0x21, 0x31, 0xB2, 4581 0x05, 0x21, 0x31, 0xB2,
4582 4582
45830x03, 0x80, 0x2A, 0xEA, 4583 0x03, 0x80, 0x2A, 0xEA,
45840x17, 0xC1, 0x2B, 0xBD, 4584 0x17, 0xC1, 0x2B, 0xBD,
4585 4585
45860x2D, 0x20, 4586 0x2D, 0x20,
45870x25, 0x20, 4587 0x25, 0x20,
45880x05, 0x20, 4588 0x05, 0x20,
45890x0D, 0x20, 4589 0x0D, 0x20,
4590 4590
45910xB3, 0x68, 4591 0xB3, 0x68,
45920x97, 0x25, 4592 0x97, 0x25,
45930x00, 0x80, 0x00, 0xE8, 4593 0x00, 0x80, 0x00, 0xE8,
4594 4594
45950x33, 0xC0, 0x33, 0xAF, 4595 0x33, 0xC0, 0x33, 0xAF,
45960x2F, 0xC0, 0x21, 0xC0, 4596 0x2F, 0xC0, 0x21, 0xC0,
4597 4597
45980x16, 0x42, 0x56, 0x9F, 4598 0x16, 0x42, 0x56, 0x9F,
45990x3C, 0x27, 0x4F, 0xE9, 4599 0x3C, 0x27, 0x4F, 0xE9,
4600 4600
46010x1E, 0x62, 0x57, 0x9F, 4601 0x1E, 0x62, 0x57, 0x9F,
46020x00, 0x80, 0x00, 0xE8, 4602 0x00, 0x80, 0x00, 0xE8,
4603 4603
46040x25, 0x21, 0x31, 0xB4, 4604 0x25, 0x21, 0x31, 0xB4,
46050x2D, 0x21, 0x1A, 0xB4, 4605 0x2D, 0x21, 0x1A, 0xB4,
4606 4606
46070x3F, 0x2F, 0x5D, 0x9F, 4607 0x3F, 0x2F, 0x5D, 0x9F,
46080x00, 0x80, 0x00, 0xE8, 4608 0x00, 0x80, 0x00, 0xE8,
4609 4609
46100x33, 0x05, 4610 0x33, 0x05,
46110x00, 0xE0, 4611 0x00, 0xE0,
46120x28, 0x19, 0x60, 0xEC, 4612 0x28, 0x19, 0x60, 0xEC,
4613 4613
46140x0D, 0x21, 0x1A, 0xB6, 4614 0x0D, 0x21, 0x1A, 0xB6,
46150x05, 0x21, 0x31, 0xB6, 4615 0x05, 0x21, 0x31, 0xB6,
4616 4616
46170x37, 0x0F, 0x5C, 0x9F, 4617 0x37, 0x0F, 0x5C, 0x9F,
46180x00, 0xE0, 4618 0x00, 0xE0,
46190x2F, 0x20, 4619 0x2F, 0x20,
4620 4620
46210x23, 0x3B, 0x33, 0xAD, 4621 0x23, 0x3B, 0x33, 0xAD,
46220x1E, 0x26, 0x1E, 0xDF, 4622 0x1E, 0x26, 0x1E, 0xDF,
4623 4623
46240xA7, 0x1E, 0x4F, 0xE9, 4624 0xA7, 0x1E, 0x4F, 0xE9,
46250x17, 0x26, 0x16, 0xDF, 4625 0x17, 0x26, 0x16, 0xDF,
4626 4626
46270x2D, 0x20, 4627 0x2D, 0x20,
46280x00, 0xE0, 4628 0x00, 0xE0,
46290xA8, 0x3F, 0x4F, 0xE9, 4629 0xA8, 0x3F, 0x4F, 0xE9,
4630 4630
46310x2F, 0x2F, 0x1E, 0xAF, 4631 0x2F, 0x2F, 0x1E, 0xAF,
46320x25, 0x20, 4632 0x25, 0x20,
46330x00, 0xE0, 4633 0x00, 0xE0,
4634 4634
46350xA4, 0x16, 0x4F, 0xE9, 4635 0xA4, 0x16, 0x4F, 0xE9,
46360x0F, 0xC0, 0x21, 0xC2, 4636 0x0F, 0xC0, 0x21, 0xC2,
4637 4637
46380xA6, 0x80, 0x4F, 0xE9, 4638 0xA6, 0x80, 0x4F, 0xE9,
46390x1F, 0x62, 0x57, 0x9F, 4639 0x1F, 0x62, 0x57, 0x9F,
4640 4640
46410x0D, 0x20, 4641 0x0D, 0x20,
46420x05, 0x20, 4642 0x05, 0x20,
46430x2F, 0xC0, 0x21, 0xC6, 4643 0x2F, 0xC0, 0x21, 0xC6,
4644 4644
46450x3F, 0x2F, 0x5D, 0x9F, 4645 0x3F, 0x2F, 0x5D, 0x9F,
46460x00, 0xE0, 4646 0x00, 0xE0,
46470x0F, 0x20, 4647 0x0F, 0x20,
4648 4648
46490x17, 0x50, 0x56, 0x9F, 4649 0x17, 0x50, 0x56, 0x9F,
46500xA5, 0x37, 0x4F, 0xE9, 4650 0xA5, 0x37, 0x4F, 0xE9,
4651 4651
46520x06, 0xC0, 0x21, 0xC4, 4652 0x06, 0xC0, 0x21, 0xC4,
46530x0F, 0x17, 0x0F, 0xAF, 4653 0x0F, 0x17, 0x0F, 0xAF,
4654 4654
46550x37, 0x0F, 0x5C, 0x9F, 4655 0x37, 0x0F, 0x5C, 0x9F,
46560x00, 0x80, 0x00, 0xE8, 4656 0x00, 0x80, 0x00, 0xE8,
4657 4657
46580x2F, 0x20, 4658 0x2F, 0x20,
46590x00, 0xE0, 4659 0x00, 0xE0,
46600xA3, 0x80, 0x4F, 0xE9, 4660 0xA3, 0x80, 0x4F, 0xE9,
4661 4661
46620x06, 0x20, 4662 0x06, 0x20,
46630x00, 0xE0, 4663 0x00, 0xE0,
46640x1F, 0x26, 0x1F, 0xDF, 4664 0x1F, 0x26, 0x1F, 0xDF,
4665 4665
46660x17, 0x26, 0x17, 0xDF, 4666 0x17, 0x26, 0x17, 0xDF,
46670x35, 0x17, 0x4F, 0xE9, 4667 0x35, 0x17, 0x4F, 0xE9,
4668 4668
46690xA1, 0x1F, 0x4F, 0xE9, 4669 0xA1, 0x1F, 0x4F, 0xE9,
46700xA2, 0x3F, 0x4F, 0xE9, 4670 0xA2, 0x3F, 0x4F, 0xE9,
4671 4671
46720x06, 0x06, 0x1F, 0xAF, 4672 0x06, 0x06, 0x1F, 0xAF,
46730x39, 0x37, 0x4F, 0xE9, 4673 0x39, 0x37, 0x4F, 0xE9,
4674 4674
46750x2F, 0x2F, 0x17, 0xAF, 4675 0x2F, 0x2F, 0x17, 0xAF,
46760x00, 0x80, 0x00, 0xE8, 4676 0x00, 0x80, 0x00, 0xE8,
4677 4677
46780xA0, 0x80, 0x4F, 0xE9, 4678 0xA0, 0x80, 0x4F, 0xE9,
46790x00, 0x80, 0x00, 0xE8, 4679 0x00, 0x80, 0x00, 0xE8,
4680 4680
46810x31, 0x80, 0x4F, 0xE9, 4681 0x31, 0x80, 0x4F, 0xE9,
46820x00, 0x80, 0x00, 0xE8, 4682 0x00, 0x80, 0x00, 0xE8,
4683 4683
46840x00, 0x80, 0x00, 0xE8, 4684 0x00, 0x80, 0x00, 0xE8,
46850x57, 0x39, 0x20, 0xE9, 4685 0x57, 0x39, 0x20, 0xE9,
4686 4686
46870x16, 0x28, 0x20, 0xE9, 4687 0x16, 0x28, 0x20, 0xE9,
46880x1D, 0x3B, 0x20, 0xE9, 4688 0x1D, 0x3B, 0x20, 0xE9,
4689 4689
46900x1E, 0x2B, 0x20, 0xE9, 4690 0x1E, 0x2B, 0x20, 0xE9,
46910x2B, 0x32, 0x20, 0xE9, 4691 0x2B, 0x32, 0x20, 0xE9,
4692 4692
46930x1C, 0x23, 0x20, 0xE9, 4693 0x1C, 0x23, 0x20, 0xE9,
46940x57, 0x36, 0x20, 0xE9, 4694 0x57, 0x36, 0x20, 0xE9,
4695 4695
46960x00, 0x80, 0xA0, 0xE9, 4696 0x00, 0x80, 0xA0, 0xE9,
46970x40, 0x40, 0xD8, 0xEC, 4697 0x40, 0x40, 0xD8, 0xEC,
4698 4698
46990xFF, 0x80, 0xC0, 0xE9, 4699 0xFF, 0x80, 0xC0, 0xE9,
47000x90, 0xE2, 4700 0x90, 0xE2,
47010x00, 0xE0, 4701 0x00, 0xE0,
4702 4702
47030x68, 0xFF, 0x20, 0xEA, 4703 0x68, 0xFF, 0x20, 0xEA,
47040x19, 0xC8, 0xC1, 0xCD, 4704 0x19, 0xC8, 0xC1, 0xCD,
4705 4705
47060x1F, 0xD7, 0x18, 0xBD, 4706 0x1F, 0xD7, 0x18, 0xBD,
47070x3F, 0xD7, 0x22, 0xBD, 4707 0x3F, 0xD7, 0x22, 0xBD,
4708 4708
47090x9F, 0x41, 0x49, 0xBD, 4709 0x9F, 0x41, 0x49, 0xBD,
47100x00, 0x80, 0x00, 0xE8, 4710 0x00, 0x80, 0x00, 0xE8,
4711 4711
47120x25, 0x41, 0x49, 0xBD, 4712 0x25, 0x41, 0x49, 0xBD,
47130x2D, 0x41, 0x51, 0xBD, 4713 0x2D, 0x41, 0x51, 0xBD,
4714 4714
47150x0D, 0x80, 0x07, 0xEA, 4715 0x0D, 0x80, 0x07, 0xEA,
47160x00, 0x80, 0x00, 0xE8, 4716 0x00, 0x80, 0x00, 0xE8,
4717 4717
47180x35, 0x40, 0x48, 0xBD, 4718 0x35, 0x40, 0x48, 0xBD,
47190x3D, 0x40, 0x50, 0xBD, 4719 0x3D, 0x40, 0x50, 0xBD,
4720 4720
47210x00, 0x80, 0x00, 0xE8, 4721 0x00, 0x80, 0x00, 0xE8,
47220x25, 0x30, 4722 0x25, 0x30,
47230x2D, 0x30, 4723 0x2D, 0x30,
4724 4724
47250x35, 0x30, 4725 0x35, 0x30,
47260xB5, 0x30, 4726 0xB5, 0x30,
47270xBD, 0x30, 4727 0xBD, 0x30,
47280x3D, 0x30, 4728 0x3D, 0x30,
4729 4729
47300x9C, 0xA7, 0x5B, 0x9F, 4730 0x9C, 0xA7, 0x5B, 0x9F,
47310x00, 0x80, 0x00, 0xE8, 4731 0x00, 0x80, 0x00, 0xE8,
4732 4732
47330x00, 0x80, 0x00, 0xE8, 4733 0x00, 0x80, 0x00, 0xE8,
47340x00, 0x80, 0x00, 0xE8, 4734 0x00, 0x80, 0x00, 0xE8,
4735 4735
47360x00, 0x80, 0x00, 0xE8, 4736 0x00, 0x80, 0x00, 0xE8,
47370x00, 0x80, 0x00, 0xE8, 4737 0x00, 0x80, 0x00, 0xE8,
4738 4738
47390x00, 0x80, 0x00, 0xE8, 4739 0x00, 0x80, 0x00, 0xE8,
47400x00, 0x80, 0x00, 0xE8, 4740 0x00, 0x80, 0x00, 0xE8,
4741 4741
47420x00, 0x80, 0x00, 0xE8, 4742 0x00, 0x80, 0x00, 0xE8,
47430x00, 0x80, 0x00, 0xE8, 4743 0x00, 0x80, 0x00, 0xE8,
4744 4744
47450x67, 0xFF, 0x0A, 0xEA, 4745 0x67, 0xFF, 0x0A, 0xEA,
47460x00, 0x80, 0x00, 0xE8, 4746 0x00, 0x80, 0x00, 0xE8,
4747 4747
47480xC9, 0x41, 0xC8, 0xEC, 4748 0xC9, 0x41, 0xC8, 0xEC,
47490x42, 0xE1, 4749 0x42, 0xE1,
47500x00, 0xE0, 4750 0x00, 0xE0,
4751 4751
47520x65, 0xFF, 0x20, 0xEA, 4752 0x65, 0xFF, 0x20, 0xEA,
47530x00, 0x80, 0x00, 0xE8, 4753 0x00, 0x80, 0x00, 0xE8,
4754 4754
47550x00, 0x80, 0x00, 0xE8, 4755 0x00, 0x80, 0x00, 0xE8,
47560x00, 0x80, 0x00, 0xE8, 4756 0x00, 0x80, 0x00, 0xE8,
4757 4757
47580xC8, 0x40, 0xC0, 0xEC, 4758 0xC8, 0x40, 0xC0, 0xEC,
47590x00, 0x80, 0x00, 0xE8, 4759 0x00, 0x80, 0x00, 0xE8,
4760 4760
47610x62, 0xFF, 0x20, 0xEA, 4761 0x62, 0xFF, 0x20, 0xEA,
47620x00, 0x80, 0x00, 0xE8, 4762 0x00, 0x80, 0x00, 0xE8,
4763 4763
47640x00, 0x80, 0x00, 0xE8, 4764 0x00, 0x80, 0x00, 0xE8,
47650x00, 0x80, 0x00, 0xE8, 4765 0x00, 0x80, 0x00, 0xE8,
4766 4766
4767}; 4767};
4768 4768
4769static unsigned char warp_g400_t2gz[] = { 4769static unsigned char warp_g400_t2gz[] = {
4770 4770
47710x00, 0x8A, 0x98, 0xE9, 4771 0x00, 0x8A, 0x98, 0xE9,
47720x00, 0x80, 0x00, 0xE8, 4772 0x00, 0x80, 0x00, 0xE8,
4773 4773
47740x00, 0x80, 0xA0, 0xE9, 4774 0x00, 0x80, 0xA0, 0xE9,
47750x00, 0x00, 0xD8, 0xEC, 4775 0x00, 0x00, 0xD8, 0xEC,
4776 4776
47770xFF, 0x80, 0xC0, 0xE9, 4777 0xFF, 0x80, 0xC0, 0xE9,
47780x00, 0x80, 0x00, 0xE8, 4778 0x00, 0x80, 0x00, 0xE8,
4779 4779
47800x0A, 0x40, 0x50, 0xBF, 4780 0x0A, 0x40, 0x50, 0xBF,
47810x2A, 0x40, 0x60, 0xBF, 4781 0x2A, 0x40, 0x60, 0xBF,
4782 4782
47830x32, 0x41, 0x51, 0xBF, 4783 0x32, 0x41, 0x51, 0xBF,
47840x3A, 0x41, 0x61, 0xBF, 4784 0x3A, 0x41, 0x61, 0xBF,
4785 4785
47860xC3, 0x6B, 4786 0xC3, 0x6B,
47870xD3, 0x6B, 4787 0xD3, 0x6B,
47880x00, 0x8A, 0x98, 0xE9, 4788 0x00, 0x8A, 0x98, 0xE9,
4789 4789
47900x73, 0x7B, 0xC8, 0xEC, 4790 0x73, 0x7B, 0xC8, 0xEC,
47910x96, 0xE2, 4791 0x96, 0xE2,
47920x41, 0x04, 4792 0x41, 0x04,
4793 4793
47940x7B, 0x43, 0xA0, 0xE8, 4794 0x7B, 0x43, 0xA0, 0xE8,
47950x73, 0x53, 0xA0, 0xE8, 4795 0x73, 0x53, 0xA0, 0xE8,
4796 4796
47970xAD, 0xEE, 0x23, 0x9F, 4797 0xAD, 0xEE, 0x23, 0x9F,
47980x00, 0xE0, 4798 0x00, 0xE0,
47990x51, 0x04, 4799 0x51, 0x04,
4800 4800
48010x90, 0xE2, 4801 0x90, 0xE2,
48020x61, 0x04, 4802 0x61, 0x04,
48030x31, 0x46, 0xB1, 0xE8, 4803 0x31, 0x46, 0xB1, 0xE8,
4804 4804
48050x51, 0x41, 0xE0, 0xEC, 4805 0x51, 0x41, 0xE0, 0xEC,
48060x39, 0x67, 0xB1, 0xE8, 4806 0x39, 0x67, 0xB1, 0xE8,
4807 4807
48080x00, 0x04, 4808 0x00, 0x04,
48090x46, 0xE2, 4809 0x46, 0xE2,
48100x73, 0x63, 0xA0, 0xE8, 4810 0x73, 0x63, 0xA0, 0xE8,
4811 4811
48120x61, 0x41, 0xE0, 0xEC, 4812 0x61, 0x41, 0xE0, 0xEC,
48130x31, 0x00, 4813 0x31, 0x00,
48140x39, 0x00, 4814 0x39, 0x00,
4815 4815
48160x78, 0x80, 0x15, 0xEA, 4816 0x78, 0x80, 0x15, 0xEA,
48170x10, 0x04, 4817 0x10, 0x04,
48180x20, 0x04, 4818 0x20, 0x04,
4819 4819
48200x61, 0x51, 0xE0, 0xEC, 4820 0x61, 0x51, 0xE0, 0xEC,
48210x2F, 0x41, 0x60, 0xEA, 4821 0x2F, 0x41, 0x60, 0xEA,
4822 4822
48230x31, 0x20, 4823 0x31, 0x20,
48240x39, 0x20, 4824 0x39, 0x20,
48250x1F, 0x42, 0xA0, 0xE8, 4825 0x1F, 0x42, 0xA0, 0xE8,
4826 4826
48270x2A, 0x42, 0x52, 0xBF, 4827 0x2A, 0x42, 0x52, 0xBF,
48280x0F, 0x52, 0xA0, 0xE8, 4828 0x0F, 0x52, 0xA0, 0xE8,
4829 4829
48300x1A, 0x42, 0x62, 0xBF, 4830 0x1A, 0x42, 0x62, 0xBF,
48310x1E, 0x51, 0x60, 0xEA, 4831 0x1E, 0x51, 0x60, 0xEA,
4832 4832
48330x73, 0x7B, 0xC8, 0xEC, 4833 0x73, 0x7B, 0xC8, 0xEC,
48340x0E, 0x61, 0x60, 0xEA, 4834 0x0E, 0x61, 0x60, 0xEA,
4835 4835
48360x32, 0x40, 0x50, 0xBD, 4836 0x32, 0x40, 0x50, 0xBD,
48370x22, 0x40, 0x60, 0xBD, 4837 0x22, 0x40, 0x60, 0xBD,
4838 4838
48390x12, 0x41, 0x51, 0xBD, 4839 0x12, 0x41, 0x51, 0xBD,
48400x3A, 0x41, 0x61, 0xBD, 4840 0x3A, 0x41, 0x61, 0xBD,
4841 4841
48420xBF, 0x2F, 0x0E, 0xBD, 4842 0xBF, 0x2F, 0x0E, 0xBD,
48430x97, 0xE2, 4843 0x97, 0xE2,
48440x7B, 0x72, 4844 0x7B, 0x72,
4845 4845
48460x32, 0x20, 4846 0x32, 0x20,
48470x22, 0x20, 4847 0x22, 0x20,
48480x12, 0x20, 4848 0x12, 0x20,
48490x3A, 0x20, 4849 0x3A, 0x20,
4850 4850
48510x35, 0x48, 0xB1, 0xE8, 4851 0x35, 0x48, 0xB1, 0xE8,
48520x3D, 0x59, 0xB1, 0xE8, 4852 0x3D, 0x59, 0xB1, 0xE8,
4853 4853
48540x46, 0x31, 0x46, 0xBF, 4854 0x46, 0x31, 0x46, 0xBF,
48550x56, 0x31, 0x56, 0xBF, 4855 0x56, 0x31, 0x56, 0xBF,
4856 4856
48570xB3, 0xE2, 0x2D, 0x9F, 4857 0xB3, 0xE2, 0x2D, 0x9F,
48580x00, 0x80, 0x00, 0xE8, 4858 0x00, 0x80, 0x00, 0xE8,
4859 4859
48600x66, 0x31, 0x66, 0xBF, 4860 0x66, 0x31, 0x66, 0xBF,
48610x47, 0x39, 0x47, 0xBF, 4861 0x47, 0x39, 0x47, 0xBF,
4862 4862
48630x57, 0x39, 0x57, 0xBF, 4863 0x57, 0x39, 0x57, 0xBF,
48640x67, 0x39, 0x67, 0xBF, 4864 0x67, 0x39, 0x67, 0xBF,
4865 4865
48660x69, 0x80, 0x07, 0xEA, 4866 0x69, 0x80, 0x07, 0xEA,
48670x24, 0x41, 0x20, 0xE9, 4867 0x24, 0x41, 0x20, 0xE9,
4868 4868
48690x35, 0x00, 4869 0x35, 0x00,
48700x3D, 0x00, 4870 0x3D, 0x00,
48710x00, 0xE0, 4871 0x00, 0xE0,
48720x2D, 0x73, 4872 0x2D, 0x73,
4873 4873
48740x33, 0x72, 4874 0x33, 0x72,
48750x0C, 0xE3, 4875 0x0C, 0xE3,
48760x8D, 0x2F, 0x1E, 0xBD, 4876 0x8D, 0x2F, 0x1E, 0xBD,
4877 4877
48780x43, 0x75, 0xF8, 0xEC, 4878 0x43, 0x75, 0xF8, 0xEC,
48790x35, 0x20, 4879 0x35, 0x20,
48800x3D, 0x20, 4880 0x3D, 0x20,
4881 4881
48820x43, 0x43, 0x2D, 0xDF, 4882 0x43, 0x43, 0x2D, 0xDF,
48830x53, 0x53, 0x2D, 0xDF, 4883 0x53, 0x53, 0x2D, 0xDF,
4884 4884
48850xAE, 0x1E, 0x0E, 0xBD, 4885 0xAE, 0x1E, 0x0E, 0xBD,
48860x58, 0xE3, 4886 0x58, 0xE3,
48870x33, 0x66, 4887 0x33, 0x66,
4888 4888
48890x48, 0x35, 0x48, 0xBF, 4889 0x48, 0x35, 0x48, 0xBF,
48900x58, 0x35, 0x58, 0xBF, 4890 0x58, 0x35, 0x58, 0xBF,
4891 4891
48920x68, 0x35, 0x68, 0xBF, 4892 0x68, 0x35, 0x68, 0xBF,
48930x49, 0x3D, 0x49, 0xBF, 4893 0x49, 0x3D, 0x49, 0xBF,
4894 4894
48950x59, 0x3D, 0x59, 0xBF, 4895 0x59, 0x3D, 0x59, 0xBF,
48960x69, 0x3D, 0x69, 0xBF, 4896 0x69, 0x3D, 0x69, 0xBF,
4897 4897
48980x63, 0x63, 0x2D, 0xDF, 4898 0x63, 0x63, 0x2D, 0xDF,
48990x4D, 0x7D, 0xF8, 0xEC, 4899 0x4D, 0x7D, 0xF8, 0xEC,
4900 4900
49010x59, 0xE3, 4901 0x59, 0xE3,
49020x00, 0xE0, 4902 0x00, 0xE0,
49030xB8, 0x38, 0x33, 0xBF, 4903 0xB8, 0x38, 0x33, 0xBF,
4904 4904
49050x2D, 0x73, 4905 0x2D, 0x73,
49060x30, 0x76, 4906 0x30, 0x76,
49070x18, 0x3A, 0x41, 0xE9, 4907 0x18, 0x3A, 0x41, 0xE9,
4908 4908
49090x3F, 0x53, 0xA0, 0xE8, 4909 0x3F, 0x53, 0xA0, 0xE8,
49100x05, 0x80, 0x3D, 0xEA, 4910 0x05, 0x80, 0x3D, 0xEA,
4911 4911
49120x37, 0x43, 0xA0, 0xE8, 4912 0x37, 0x43, 0xA0, 0xE8,
49130x3D, 0x63, 0xA0, 0xE8, 4913 0x3D, 0x63, 0xA0, 0xE8,
4914 4914
49150x50, 0x70, 0xF8, 0xEC, 4915 0x50, 0x70, 0xF8, 0xEC,
49160x2B, 0x50, 0x3C, 0xE9, 4916 0x2B, 0x50, 0x3C, 0xE9,
4917 4917
49180x1F, 0x0F, 0xBC, 0xE8, 4918 0x1F, 0x0F, 0xBC, 0xE8,
49190x00, 0x80, 0x00, 0xE8, 4919 0x00, 0x80, 0x00, 0xE8,
4920 4920
49210x59, 0x78, 0xF8, 0xEC, 4921 0x59, 0x78, 0xF8, 0xEC,
49220x00, 0x80, 0x00, 0xE8, 4922 0x00, 0x80, 0x00, 0xE8,
4923 4923
49240x15, 0xC0, 0x20, 0xE9, 4924 0x15, 0xC0, 0x20, 0xE9,
49250x15, 0xC0, 0x20, 0xE9, 4925 0x15, 0xC0, 0x20, 0xE9,
4926 4926
49270x15, 0xC0, 0x20, 0xE9, 4927 0x15, 0xC0, 0x20, 0xE9,
49280x15, 0xC0, 0x20, 0xE9, 4928 0x15, 0xC0, 0x20, 0xE9,
4929 4929
49300x1E, 0x12, 0x41, 0xE9, 4930 0x1E, 0x12, 0x41, 0xE9,
49310x1A, 0x22, 0x41, 0xE9, 4931 0x1A, 0x22, 0x41, 0xE9,
4932 4932
49330x46, 0x37, 0x46, 0xDF, 4933 0x46, 0x37, 0x46, 0xDF,
49340x56, 0x3F, 0x56, 0xDF, 4934 0x56, 0x3F, 0x56, 0xDF,
4935 4935
49360x2B, 0x40, 0x3D, 0xE9, 4936 0x2B, 0x40, 0x3D, 0xE9,
49370x66, 0x3D, 0x66, 0xDF, 4937 0x66, 0x3D, 0x66, 0xDF,
4938 4938
49390x1D, 0x32, 0x41, 0xE9, 4939 0x1D, 0x32, 0x41, 0xE9,
49400x67, 0x3D, 0x67, 0xDF, 4940 0x67, 0x3D, 0x67, 0xDF,
4941 4941
49420x47, 0x37, 0x47, 0xDF, 4942 0x47, 0x37, 0x47, 0xDF,
49430x57, 0x3F, 0x57, 0xDF, 4943 0x57, 0x3F, 0x57, 0xDF,
4944 4944
49450x2A, 0x40, 0x20, 0xE9, 4945 0x2A, 0x40, 0x20, 0xE9,
49460x59, 0x3F, 0x59, 0xDF, 4946 0x59, 0x3F, 0x59, 0xDF,
4947 4947
49480x16, 0x30, 0x20, 0xE9, 4948 0x16, 0x30, 0x20, 0xE9,
49490x69, 0x3D, 0x69, 0xDF, 4949 0x69, 0x3D, 0x69, 0xDF,
4950 4950
49510x48, 0x37, 0x48, 0xDF, 4951 0x48, 0x37, 0x48, 0xDF,
49520x58, 0x3F, 0x58, 0xDF, 4952 0x58, 0x3F, 0x58, 0xDF,
4953 4953
49540x12, 0x12, 0x2D, 0xDF, 4954 0x12, 0x12, 0x2D, 0xDF,
49550x22, 0x22, 0x2D, 0xDF, 4955 0x22, 0x22, 0x2D, 0xDF,
4956 4956
49570x32, 0x32, 0x2D, 0xDF, 4957 0x32, 0x32, 0x2D, 0xDF,
49580x3A, 0x3A, 0x2D, 0xDF, 4958 0x3A, 0x3A, 0x2D, 0xDF,
4959 4959
49600x68, 0x3D, 0x68, 0xDF, 4960 0x68, 0x3D, 0x68, 0xDF,
49610x49, 0x37, 0x49, 0xDF, 4961 0x49, 0x37, 0x49, 0xDF,
4962 4962
49630x3D, 0xCF, 0x74, 0xC0, 4963 0x3D, 0xCF, 0x74, 0xC0,
49640x37, 0xCF, 0x74, 0xC4, 4964 0x37, 0xCF, 0x74, 0xC4,
4965 4965
49660x31, 0x53, 0x2F, 0x9F, 4966 0x31, 0x53, 0x2F, 0x9F,
49670x34, 0x80, 0x20, 0xE9, 4967 0x34, 0x80, 0x20, 0xE9,
4968 4968
49690x39, 0xE5, 0x2C, 0x9F, 4969 0x39, 0xE5, 0x2C, 0x9F,
49700x3C, 0x3D, 0x20, 0xE9, 4970 0x3C, 0x3D, 0x20, 0xE9,
4971 4971
49720x0A, 0x44, 0x54, 0xB0, 4972 0x0A, 0x44, 0x54, 0xB0,
49730x02, 0x44, 0x64, 0xB0, 4973 0x02, 0x44, 0x64, 0xB0,
4974 4974
49750x2A, 0x44, 0x54, 0xB2, 4975 0x2A, 0x44, 0x54, 0xB2,
49760x1A, 0x44, 0x64, 0xB2, 4976 0x1A, 0x44, 0x64, 0xB2,
4977 4977
49780x25, 0x80, 0x3A, 0xEA, 4978 0x25, 0x80, 0x3A, 0xEA,
49790x0A, 0x20, 4979 0x0A, 0x20,
49800x02, 0x20, 4980 0x02, 0x20,
4981 4981
49820x3D, 0xCF, 0x74, 0xC2, 4982 0x3D, 0xCF, 0x74, 0xC2,
49830x2A, 0x20, 4983 0x2A, 0x20,
49840x1A, 0x20, 4984 0x1A, 0x20,
4985 4985
49860x30, 0x50, 0x2E, 0x9F, 4986 0x30, 0x50, 0x2E, 0x9F,
49870x32, 0x31, 0x5F, 0xE9, 4987 0x32, 0x31, 0x5F, 0xE9,
4988 4988
49890x38, 0x21, 0x2C, 0x9F, 4989 0x38, 0x21, 0x2C, 0x9F,
49900x33, 0x39, 0x5F, 0xE9, 4990 0x33, 0x39, 0x5F, 0xE9,
4991 4991
49920x31, 0x53, 0x2F, 0x9F, 4992 0x31, 0x53, 0x2F, 0x9F,
49930x00, 0x80, 0x00, 0xE8, 4993 0x00, 0x80, 0x00, 0xE8,
4994 4994
49950x2A, 0x44, 0x54, 0xB4, 4995 0x2A, 0x44, 0x54, 0xB4,
49960x1A, 0x44, 0x64, 0xB4, 4996 0x1A, 0x44, 0x64, 0xB4,
4997 4997
49980x39, 0xE5, 0x2C, 0x9F, 4998 0x39, 0xE5, 0x2C, 0x9F,
49990x38, 0x3D, 0x20, 0xE9, 4999 0x38, 0x3D, 0x20, 0xE9,
5000 5000
50010x88, 0x73, 0x5E, 0xE9, 5001 0x88, 0x73, 0x5E, 0xE9,
50020x2A, 0x20, 5002 0x2A, 0x20,
50030x1A, 0x20, 5003 0x1A, 0x20,
5004 5004
50050x2A, 0x46, 0x56, 0xBF, 5005 0x2A, 0x46, 0x56, 0xBF,
50060x1A, 0x46, 0x66, 0xBF, 5006 0x1A, 0x46, 0x66, 0xBF,
5007 5007
50080x31, 0x53, 0x2F, 0x9F, 5008 0x31, 0x53, 0x2F, 0x9F,
50090x3E, 0x30, 0x4F, 0xE9, 5009 0x3E, 0x30, 0x4F, 0xE9,
5010 5010
50110x39, 0xE5, 0x2C, 0x9F, 5011 0x39, 0xE5, 0x2C, 0x9F,
50120x3F, 0x38, 0x4F, 0xE9, 5012 0x3F, 0x38, 0x4F, 0xE9,
5013 5013
50140x0A, 0x47, 0x57, 0xBF, 5014 0x0A, 0x47, 0x57, 0xBF,
50150x02, 0x47, 0x67, 0xBF, 5015 0x02, 0x47, 0x67, 0xBF,
5016 5016
50170x31, 0x53, 0x2F, 0x9F, 5017 0x31, 0x53, 0x2F, 0x9F,
50180x3A, 0x31, 0x4F, 0xE9, 5018 0x3A, 0x31, 0x4F, 0xE9,
5019 5019
50200x39, 0xE5, 0x2C, 0x9F, 5020 0x39, 0xE5, 0x2C, 0x9F,
50210x3B, 0x39, 0x4F, 0xE9, 5021 0x3B, 0x39, 0x4F, 0xE9,
5022 5022
50230x2A, 0x43, 0x53, 0xBF, 5023 0x2A, 0x43, 0x53, 0xBF,
50240x1A, 0x43, 0x63, 0xBF, 5024 0x1A, 0x43, 0x63, 0xBF,
5025 5025
50260x30, 0x50, 0x2E, 0x9F, 5026 0x30, 0x50, 0x2E, 0x9F,
50270x36, 0x31, 0x4F, 0xE9, 5027 0x36, 0x31, 0x4F, 0xE9,
5028 5028
50290x38, 0x21, 0x2C, 0x9F, 5029 0x38, 0x21, 0x2C, 0x9F,
50300x37, 0x39, 0x4F, 0xE9, 5030 0x37, 0x39, 0x4F, 0xE9,
5031 5031
50320x0A, 0x48, 0x58, 0xBF, 5032 0x0A, 0x48, 0x58, 0xBF,
50330x02, 0x48, 0x68, 0xBF, 5033 0x02, 0x48, 0x68, 0xBF,
5034 5034
50350x31, 0x53, 0x2F, 0x9F, 5035 0x31, 0x53, 0x2F, 0x9F,
50360x80, 0x31, 0x57, 0xE9, 5036 0x80, 0x31, 0x57, 0xE9,
5037 5037
50380x39, 0xE5, 0x2C, 0x9F, 5038 0x39, 0xE5, 0x2C, 0x9F,
50390x81, 0x39, 0x57, 0xE9, 5039 0x81, 0x39, 0x57, 0xE9,
5040 5040
50410x2A, 0x49, 0x59, 0xBF, 5041 0x2A, 0x49, 0x59, 0xBF,
50420x1A, 0x49, 0x69, 0xBF, 5042 0x1A, 0x49, 0x69, 0xBF,
5043 5043
50440x30, 0x50, 0x2E, 0x9F, 5044 0x30, 0x50, 0x2E, 0x9F,
50450x82, 0x30, 0x57, 0xE9, 5045 0x82, 0x30, 0x57, 0xE9,
5046 5046
50470x38, 0x21, 0x2C, 0x9F, 5047 0x38, 0x21, 0x2C, 0x9F,
50480x83, 0x38, 0x57, 0xE9, 5048 0x83, 0x38, 0x57, 0xE9,
5049 5049
50500x31, 0x53, 0x2F, 0x9F, 5050 0x31, 0x53, 0x2F, 0x9F,
50510x84, 0x31, 0x5E, 0xE9, 5051 0x84, 0x31, 0x5E, 0xE9,
5052 5052
50530x39, 0xE5, 0x2C, 0x9F, 5053 0x39, 0xE5, 0x2C, 0x9F,
50540x85, 0x39, 0x5E, 0xE9, 5054 0x85, 0x39, 0x5E, 0xE9,
5055 5055
50560x86, 0x76, 0x57, 0xE9, 5056 0x86, 0x76, 0x57, 0xE9,
50570x8A, 0x36, 0x20, 0xE9, 5057 0x8A, 0x36, 0x20, 0xE9,
5058 5058
50590x87, 0x77, 0x57, 0xE9, 5059 0x87, 0x77, 0x57, 0xE9,
50600x8B, 0x3E, 0xBF, 0xEA, 5060 0x8B, 0x3E, 0xBF, 0xEA,
5061 5061
50620x80, 0x30, 0x57, 0xE9, 5062 0x80, 0x30, 0x57, 0xE9,
50630x81, 0x38, 0x57, 0xE9, 5063 0x81, 0x38, 0x57, 0xE9,
5064 5064
50650x82, 0x31, 0x57, 0xE9, 5065 0x82, 0x31, 0x57, 0xE9,
50660x86, 0x78, 0x57, 0xE9, 5066 0x86, 0x78, 0x57, 0xE9,
5067 5067
50680x83, 0x39, 0x57, 0xE9, 5068 0x83, 0x39, 0x57, 0xE9,
50690x87, 0x79, 0x57, 0xE9, 5069 0x87, 0x79, 0x57, 0xE9,
5070 5070
50710x30, 0x1F, 0x5F, 0xE9, 5071 0x30, 0x1F, 0x5F, 0xE9,
50720x8A, 0x34, 0x20, 0xE9, 5072 0x8A, 0x34, 0x20, 0xE9,
5073 5073
50740x8B, 0x3C, 0x20, 0xE9, 5074 0x8B, 0x3C, 0x20, 0xE9,
50750x37, 0x50, 0x60, 0xBD, 5075 0x37, 0x50, 0x60, 0xBD,
5076 5076
50770x57, 0x0D, 0x20, 0xE9, 5077 0x57, 0x0D, 0x20, 0xE9,
50780x35, 0x51, 0x61, 0xBD, 5078 0x35, 0x51, 0x61, 0xBD,
5079 5079
50800x2B, 0x50, 0x20, 0xE9, 5080 0x2B, 0x50, 0x20, 0xE9,
50810x1D, 0x37, 0xE1, 0xEA, 5081 0x1D, 0x37, 0xE1, 0xEA,
5082 5082
50830x1E, 0x35, 0xE1, 0xEA, 5083 0x1E, 0x35, 0xE1, 0xEA,
50840x00, 0xE0, 5084 0x00, 0xE0,
50850x0E, 0x77, 5085 0x0E, 0x77,
5086 5086
50870x24, 0x51, 0x20, 0xE9, 5087 0x24, 0x51, 0x20, 0xE9,
50880x9F, 0xFF, 0x20, 0xEA, 5088 0x9F, 0xFF, 0x20, 0xEA,
5089 5089
50900x16, 0x0E, 0x20, 0xE9, 5090 0x16, 0x0E, 0x20, 0xE9,
50910x57, 0x2E, 0xBF, 0xEA, 5091 0x57, 0x2E, 0xBF, 0xEA,
5092 5092
50930x0B, 0x46, 0xA0, 0xE8, 5093 0x0B, 0x46, 0xA0, 0xE8,
50940x1B, 0x56, 0xA0, 0xE8, 5094 0x1B, 0x56, 0xA0, 0xE8,
5095 5095
50960x2B, 0x66, 0xA0, 0xE8, 5096 0x2B, 0x66, 0xA0, 0xE8,
50970x0C, 0x47, 0xA0, 0xE8, 5097 0x0C, 0x47, 0xA0, 0xE8,
5098 5098
50990x1C, 0x57, 0xA0, 0xE8, 5099 0x1C, 0x57, 0xA0, 0xE8,
51000x2C, 0x67, 0xA0, 0xE8, 5100 0x2C, 0x67, 0xA0, 0xE8,
5101 5101
51020x0B, 0x00, 5102 0x0B, 0x00,
51030x1B, 0x00, 5103 0x1B, 0x00,
51040x2B, 0x00, 5104 0x2B, 0x00,
51050x00, 0xE0, 5105 0x00, 0xE0,
5106 5106
51070x0C, 0x00, 5107 0x0C, 0x00,
51080x1C, 0x00, 5108 0x1C, 0x00,
51090x2C, 0x00, 5109 0x2C, 0x00,
51100x00, 0xE0, 5110 0x00, 0xE0,
5111 5111
51120x0B, 0x65, 5112 0x0B, 0x65,
51130x1B, 0x65, 5113 0x1B, 0x65,
51140x2B, 0x65, 5114 0x2B, 0x65,
51150x00, 0xE0, 5115 0x00, 0xE0,
5116 5116
51170x0C, 0x65, 5117 0x0C, 0x65,
51180x1C, 0x65, 5118 0x1C, 0x65,
51190x2C, 0x65, 5119 0x2C, 0x65,
51200x00, 0xE0, 5120 0x00, 0xE0,
5121 5121
51220x0B, 0x1B, 0x60, 0xEC, 5122 0x0B, 0x1B, 0x60, 0xEC,
51230x36, 0xD7, 0x36, 0xAD, 5123 0x36, 0xD7, 0x36, 0xAD,
5124 5124
51250x2B, 0x80, 0x60, 0xEC, 5125 0x2B, 0x80, 0x60, 0xEC,
51260x0C, 0x1C, 0x60, 0xEC, 5126 0x0C, 0x1C, 0x60, 0xEC,
5127 5127
51280x3E, 0xD7, 0x3E, 0xAD, 5128 0x3E, 0xD7, 0x3E, 0xAD,
51290x2C, 0x80, 0x60, 0xEC, 5129 0x2C, 0x80, 0x60, 0xEC,
5130 5130
51310x0B, 0x2B, 0xDE, 0xE8, 5131 0x0B, 0x2B, 0xDE, 0xE8,
51320x1B, 0x80, 0xDE, 0xE8, 5132 0x1B, 0x80, 0xDE, 0xE8,
5133 5133
51340x36, 0x80, 0x36, 0xBD, 5134 0x36, 0x80, 0x36, 0xBD,
51350x3E, 0x80, 0x3E, 0xBD, 5135 0x3E, 0x80, 0x3E, 0xBD,
5136 5136
51370x33, 0xD7, 0x0B, 0xBD, 5137 0x33, 0xD7, 0x0B, 0xBD,
51380x3B, 0xD7, 0x1B, 0xBD, 5138 0x3B, 0xD7, 0x1B, 0xBD,
5139 5139
51400x46, 0x80, 0x46, 0xCF, 5140 0x46, 0x80, 0x46, 0xCF,
51410x57, 0x80, 0x57, 0xCF, 5141 0x57, 0x80, 0x57, 0xCF,
5142 5142
51430x66, 0x33, 0x66, 0xCF, 5143 0x66, 0x33, 0x66, 0xCF,
51440x47, 0x3B, 0x47, 0xCF, 5144 0x47, 0x3B, 0x47, 0xCF,
5145 5145
51460x56, 0x33, 0x56, 0xCF, 5146 0x56, 0x33, 0x56, 0xCF,
51470x67, 0x3B, 0x67, 0xCF, 5147 0x67, 0x3B, 0x67, 0xCF,
5148 5148
51490x0B, 0x48, 0xA0, 0xE8, 5149 0x0B, 0x48, 0xA0, 0xE8,
51500x1B, 0x58, 0xA0, 0xE8, 5150 0x1B, 0x58, 0xA0, 0xE8,
5151 5151
51520x2B, 0x68, 0xA0, 0xE8, 5152 0x2B, 0x68, 0xA0, 0xE8,
51530x0C, 0x49, 0xA0, 0xE8, 5153 0x0C, 0x49, 0xA0, 0xE8,
5154 5154
51550x1C, 0x59, 0xA0, 0xE8, 5155 0x1C, 0x59, 0xA0, 0xE8,
51560x2C, 0x69, 0xA0, 0xE8, 5156 0x2C, 0x69, 0xA0, 0xE8,
5157 5157
51580x0B, 0x00, 5158 0x0B, 0x00,
51590x1B, 0x00, 5159 0x1B, 0x00,
51600x2B, 0x00, 5160 0x2B, 0x00,
51610x00, 0xE0, 5161 0x00, 0xE0,
5162 5162
51630x0C, 0x00, 5163 0x0C, 0x00,
51640x1C, 0x00, 5164 0x1C, 0x00,
51650x2C, 0x00, 5165 0x2C, 0x00,
51660x00, 0xE0, 5166 0x00, 0xE0,
5167 5167
51680x0B, 0x65, 5168 0x0B, 0x65,
51690x1B, 0x65, 5169 0x1B, 0x65,
51700x2B, 0x65, 5170 0x2B, 0x65,
51710x00, 0xE0, 5171 0x00, 0xE0,
5172 5172
51730x0C, 0x65, 5173 0x0C, 0x65,
51740x1C, 0x65, 5174 0x1C, 0x65,
51750x2C, 0x65, 5175 0x2C, 0x65,
51760x00, 0xE0, 5176 0x00, 0xE0,
5177 5177
51780x0B, 0x1B, 0x60, 0xEC, 5178 0x0B, 0x1B, 0x60, 0xEC,
51790x34, 0xD7, 0x34, 0xAD, 5179 0x34, 0xD7, 0x34, 0xAD,
5180 5180
51810x2B, 0x80, 0x60, 0xEC, 5181 0x2B, 0x80, 0x60, 0xEC,
51820x0C, 0x1C, 0x60, 0xEC, 5182 0x0C, 0x1C, 0x60, 0xEC,
5183 5183
51840x3C, 0xD7, 0x3C, 0xAD, 5184 0x3C, 0xD7, 0x3C, 0xAD,
51850x2C, 0x80, 0x60, 0xEC, 5185 0x2C, 0x80, 0x60, 0xEC,
5186 5186
51870x0B, 0x2B, 0xDE, 0xE8, 5187 0x0B, 0x2B, 0xDE, 0xE8,
51880x1B, 0x80, 0xDE, 0xE8, 5188 0x1B, 0x80, 0xDE, 0xE8,
5189 5189
51900x34, 0x80, 0x34, 0xBD, 5190 0x34, 0x80, 0x34, 0xBD,
51910x3C, 0x80, 0x3C, 0xBD, 5191 0x3C, 0x80, 0x3C, 0xBD,
5192 5192
51930x33, 0xD7, 0x0B, 0xBD, 5193 0x33, 0xD7, 0x0B, 0xBD,
51940x3B, 0xD7, 0x1B, 0xBD, 5194 0x3B, 0xD7, 0x1B, 0xBD,
5195 5195
51960x48, 0x80, 0x48, 0xCF, 5196 0x48, 0x80, 0x48, 0xCF,
51970x59, 0x80, 0x59, 0xCF, 5197 0x59, 0x80, 0x59, 0xCF,
5198 5198
51990x68, 0x33, 0x68, 0xCF, 5199 0x68, 0x33, 0x68, 0xCF,
52000x49, 0x3B, 0x49, 0xCF, 5200 0x49, 0x3B, 0x49, 0xCF,
5201 5201
52020xBE, 0xFF, 0x20, 0xEA, 5202 0xBE, 0xFF, 0x20, 0xEA,
52030x00, 0x80, 0x00, 0xE8, 5203 0x00, 0x80, 0x00, 0xE8,
5204 5204
52050x58, 0x33, 0x58, 0xCF, 5205 0x58, 0x33, 0x58, 0xCF,
52060x69, 0x3B, 0x69, 0xCF, 5206 0x69, 0x3B, 0x69, 0xCF,
5207 5207
52080x7D, 0xFF, 0x20, 0xEA, 5208 0x7D, 0xFF, 0x20, 0xEA,
52090x57, 0xC0, 0xBF, 0xEA, 5209 0x57, 0xC0, 0xBF, 0xEA,
5210 5210
52110x00, 0x80, 0xA0, 0xE9, 5211 0x00, 0x80, 0xA0, 0xE9,
52120x00, 0x00, 0xD8, 0xEC, 5212 0x00, 0x00, 0xD8, 0xEC,
5213 5213
5214}; 5214};
5215 5215
5216static unsigned char warp_g400_t2gza[] = { 5216static unsigned char warp_g400_t2gza[] = {
5217 5217
52180x00, 0x8A, 0x98, 0xE9, 5218 0x00, 0x8A, 0x98, 0xE9,
52190x00, 0x80, 0x00, 0xE8, 5219 0x00, 0x80, 0x00, 0xE8,
5220 5220
52210x00, 0x80, 0xA0, 0xE9, 5221 0x00, 0x80, 0xA0, 0xE9,
52220x00, 0x00, 0xD8, 0xEC, 5222 0x00, 0x00, 0xD8, 0xEC,
5223 5223
52240xFF, 0x80, 0xC0, 0xE9, 5224 0xFF, 0x80, 0xC0, 0xE9,
52250x00, 0x80, 0x00, 0xE8, 5225 0x00, 0x80, 0x00, 0xE8,
5226 5226
52270x0A, 0x40, 0x50, 0xBF, 5227 0x0A, 0x40, 0x50, 0xBF,
52280x2A, 0x40, 0x60, 0xBF, 5228 0x2A, 0x40, 0x60, 0xBF,
5229 5229
52300x32, 0x41, 0x51, 0xBF, 5230 0x32, 0x41, 0x51, 0xBF,
52310x3A, 0x41, 0x61, 0xBF, 5231 0x3A, 0x41, 0x61, 0xBF,
5232 5232
52330xC3, 0x6B, 5233 0xC3, 0x6B,
52340xD3, 0x6B, 5234 0xD3, 0x6B,
52350x00, 0x8A, 0x98, 0xE9, 5235 0x00, 0x8A, 0x98, 0xE9,
5236 5236
52370x73, 0x7B, 0xC8, 0xEC, 5237 0x73, 0x7B, 0xC8, 0xEC,
52380x96, 0xE2, 5238 0x96, 0xE2,
52390x41, 0x04, 5239 0x41, 0x04,
5240 5240
52410x7B, 0x43, 0xA0, 0xE8, 5241 0x7B, 0x43, 0xA0, 0xE8,
52420x73, 0x53, 0xA0, 0xE8, 5242 0x73, 0x53, 0xA0, 0xE8,
5243 5243
52440xAD, 0xEE, 0x23, 0x9F, 5244 0xAD, 0xEE, 0x23, 0x9F,
52450x00, 0xE0, 5245 0x00, 0xE0,
52460x51, 0x04, 5246 0x51, 0x04,
5247 5247
52480x90, 0xE2, 5248 0x90, 0xE2,
52490x61, 0x04, 5249 0x61, 0x04,
52500x31, 0x46, 0xB1, 0xE8, 5250 0x31, 0x46, 0xB1, 0xE8,
5251 5251
52520x51, 0x41, 0xE0, 0xEC, 5252 0x51, 0x41, 0xE0, 0xEC,
52530x39, 0x67, 0xB1, 0xE8, 5253 0x39, 0x67, 0xB1, 0xE8,
5254 5254
52550x00, 0x04, 5255 0x00, 0x04,
52560x46, 0xE2, 5256 0x46, 0xE2,
52570x73, 0x63, 0xA0, 0xE8, 5257 0x73, 0x63, 0xA0, 0xE8,
5258 5258
52590x61, 0x41, 0xE0, 0xEC, 5259 0x61, 0x41, 0xE0, 0xEC,
52600x31, 0x00, 5260 0x31, 0x00,
52610x39, 0x00, 5261 0x39, 0x00,
5262 5262
52630x7C, 0x80, 0x15, 0xEA, 5263 0x7C, 0x80, 0x15, 0xEA,
52640x10, 0x04, 5264 0x10, 0x04,
52650x20, 0x04, 5265 0x20, 0x04,
5266 5266
52670x61, 0x51, 0xE0, 0xEC, 5267 0x61, 0x51, 0xE0, 0xEC,
52680x2F, 0x41, 0x60, 0xEA, 5268 0x2F, 0x41, 0x60, 0xEA,
5269 5269
52700x31, 0x20, 5270 0x31, 0x20,
52710x39, 0x20, 5271 0x39, 0x20,
52720x1F, 0x42, 0xA0, 0xE8, 5272 0x1F, 0x42, 0xA0, 0xE8,
5273 5273
52740x2A, 0x42, 0x52, 0xBF, 5274 0x2A, 0x42, 0x52, 0xBF,
52750x0F, 0x52, 0xA0, 0xE8, 5275 0x0F, 0x52, 0xA0, 0xE8,
5276 5276
52770x1A, 0x42, 0x62, 0xBF, 5277 0x1A, 0x42, 0x62, 0xBF,
52780x1E, 0x51, 0x60, 0xEA, 5278 0x1E, 0x51, 0x60, 0xEA,
5279 5279
52800x73, 0x7B, 0xC8, 0xEC, 5280 0x73, 0x7B, 0xC8, 0xEC,
52810x0E, 0x61, 0x60, 0xEA, 5281 0x0E, 0x61, 0x60, 0xEA,
5282 5282
52830x32, 0x40, 0x50, 0xBD, 5283 0x32, 0x40, 0x50, 0xBD,
52840x22, 0x40, 0x60, 0xBD, 5284 0x22, 0x40, 0x60, 0xBD,
5285 5285
52860x12, 0x41, 0x51, 0xBD, 5286 0x12, 0x41, 0x51, 0xBD,
52870x3A, 0x41, 0x61, 0xBD, 5287 0x3A, 0x41, 0x61, 0xBD,
5288 5288
52890xBF, 0x2F, 0x0E, 0xBD, 5289 0xBF, 0x2F, 0x0E, 0xBD,
52900x97, 0xE2, 5290 0x97, 0xE2,
52910x7B, 0x72, 5291 0x7B, 0x72,
5292 5292
52930x32, 0x20, 5293 0x32, 0x20,
52940x22, 0x20, 5294 0x22, 0x20,
52950x12, 0x20, 5295 0x12, 0x20,
52960x3A, 0x20, 5296 0x3A, 0x20,
5297 5297
52980x35, 0x48, 0xB1, 0xE8, 5298 0x35, 0x48, 0xB1, 0xE8,
52990x3D, 0x59, 0xB1, 0xE8, 5299 0x3D, 0x59, 0xB1, 0xE8,
5300 5300
53010x46, 0x31, 0x46, 0xBF, 5301 0x46, 0x31, 0x46, 0xBF,
53020x56, 0x31, 0x56, 0xBF, 5302 0x56, 0x31, 0x56, 0xBF,
5303 5303
53040xB3, 0xE2, 0x2D, 0x9F, 5304 0xB3, 0xE2, 0x2D, 0x9F,
53050x00, 0x80, 0x00, 0xE8, 5305 0x00, 0x80, 0x00, 0xE8,
5306 5306
53070x66, 0x31, 0x66, 0xBF, 5307 0x66, 0x31, 0x66, 0xBF,
53080x47, 0x39, 0x47, 0xBF, 5308 0x47, 0x39, 0x47, 0xBF,
5309 5309
53100x57, 0x39, 0x57, 0xBF, 5310 0x57, 0x39, 0x57, 0xBF,
53110x67, 0x39, 0x67, 0xBF, 5311 0x67, 0x39, 0x67, 0xBF,
5312 5312
53130x6D, 0x80, 0x07, 0xEA, 5313 0x6D, 0x80, 0x07, 0xEA,
53140x24, 0x41, 0x20, 0xE9, 5314 0x24, 0x41, 0x20, 0xE9,
5315 5315
53160x35, 0x00, 5316 0x35, 0x00,
53170x3D, 0x00, 5317 0x3D, 0x00,
53180x00, 0xE0, 5318 0x00, 0xE0,
53190x2D, 0x73, 5319 0x2D, 0x73,
5320 5320
53210x33, 0x72, 5321 0x33, 0x72,
53220x0C, 0xE3, 5322 0x0C, 0xE3,
53230x8D, 0x2F, 0x1E, 0xBD, 5323 0x8D, 0x2F, 0x1E, 0xBD,
5324 5324
53250x43, 0x75, 0xF8, 0xEC, 5325 0x43, 0x75, 0xF8, 0xEC,
53260x35, 0x20, 5326 0x35, 0x20,
53270x3D, 0x20, 5327 0x3D, 0x20,
5328 5328
53290x43, 0x43, 0x2D, 0xDF, 5329 0x43, 0x43, 0x2D, 0xDF,
53300x53, 0x53, 0x2D, 0xDF, 5330 0x53, 0x53, 0x2D, 0xDF,
5331 5331
53320xAE, 0x1E, 0x0E, 0xBD, 5332 0xAE, 0x1E, 0x0E, 0xBD,
53330x58, 0xE3, 5333 0x58, 0xE3,
53340x33, 0x66, 5334 0x33, 0x66,
5335 5335
53360x48, 0x35, 0x48, 0xBF, 5336 0x48, 0x35, 0x48, 0xBF,
53370x58, 0x35, 0x58, 0xBF, 5337 0x58, 0x35, 0x58, 0xBF,
5338 5338
53390x68, 0x35, 0x68, 0xBF, 5339 0x68, 0x35, 0x68, 0xBF,
53400x49, 0x3D, 0x49, 0xBF, 5340 0x49, 0x3D, 0x49, 0xBF,
5341 5341
53420x59, 0x3D, 0x59, 0xBF, 5342 0x59, 0x3D, 0x59, 0xBF,
53430x69, 0x3D, 0x69, 0xBF, 5343 0x69, 0x3D, 0x69, 0xBF,
5344 5344
53450x63, 0x63, 0x2D, 0xDF, 5345 0x63, 0x63, 0x2D, 0xDF,
53460x4D, 0x7D, 0xF8, 0xEC, 5346 0x4D, 0x7D, 0xF8, 0xEC,
5347 5347
53480x59, 0xE3, 5348 0x59, 0xE3,
53490x00, 0xE0, 5349 0x00, 0xE0,
53500xB8, 0x38, 0x33, 0xBF, 5350 0xB8, 0x38, 0x33, 0xBF,
5351 5351
53520x2D, 0x73, 5352 0x2D, 0x73,
53530x30, 0x76, 5353 0x30, 0x76,
53540x18, 0x3A, 0x41, 0xE9, 5354 0x18, 0x3A, 0x41, 0xE9,
5355 5355
53560x3F, 0x53, 0xA0, 0xE8, 5356 0x3F, 0x53, 0xA0, 0xE8,
53570x05, 0x80, 0x3D, 0xEA, 5357 0x05, 0x80, 0x3D, 0xEA,
5358 5358
53590x37, 0x43, 0xA0, 0xE8, 5359 0x37, 0x43, 0xA0, 0xE8,
53600x3D, 0x63, 0xA0, 0xE8, 5360 0x3D, 0x63, 0xA0, 0xE8,
5361 5361
53620x50, 0x70, 0xF8, 0xEC, 5362 0x50, 0x70, 0xF8, 0xEC,
53630x2B, 0x50, 0x3C, 0xE9, 5363 0x2B, 0x50, 0x3C, 0xE9,
5364 5364
53650x1F, 0x0F, 0xBC, 0xE8, 5365 0x1F, 0x0F, 0xBC, 0xE8,
53660x00, 0x80, 0x00, 0xE8, 5366 0x00, 0x80, 0x00, 0xE8,
5367 5367
53680x59, 0x78, 0xF8, 0xEC, 5368 0x59, 0x78, 0xF8, 0xEC,
53690x00, 0x80, 0x00, 0xE8, 5369 0x00, 0x80, 0x00, 0xE8,
5370 5370
53710x15, 0xC0, 0x20, 0xE9, 5371 0x15, 0xC0, 0x20, 0xE9,
53720x15, 0xC0, 0x20, 0xE9, 5372 0x15, 0xC0, 0x20, 0xE9,
5373 5373
53740x15, 0xC0, 0x20, 0xE9, 5374 0x15, 0xC0, 0x20, 0xE9,
53750x15, 0xC0, 0x20, 0xE9, 5375 0x15, 0xC0, 0x20, 0xE9,
5376 5376
53770x1E, 0x12, 0x41, 0xE9, 5377 0x1E, 0x12, 0x41, 0xE9,
53780x1A, 0x22, 0x41, 0xE9, 5378 0x1A, 0x22, 0x41, 0xE9,
5379 5379
53800x46, 0x37, 0x46, 0xDF, 5380 0x46, 0x37, 0x46, 0xDF,
53810x56, 0x3F, 0x56, 0xDF, 5381 0x56, 0x3F, 0x56, 0xDF,
5382 5382
53830x2B, 0x40, 0x3D, 0xE9, 5383 0x2B, 0x40, 0x3D, 0xE9,
53840x66, 0x3D, 0x66, 0xDF, 5384 0x66, 0x3D, 0x66, 0xDF,
5385 5385
53860x1D, 0x32, 0x41, 0xE9, 5386 0x1D, 0x32, 0x41, 0xE9,
53870x67, 0x3D, 0x67, 0xDF, 5387 0x67, 0x3D, 0x67, 0xDF,
5388 5388
53890x47, 0x37, 0x47, 0xDF, 5389 0x47, 0x37, 0x47, 0xDF,
53900x57, 0x3F, 0x57, 0xDF, 5390 0x57, 0x3F, 0x57, 0xDF,
5391 5391
53920x2A, 0x40, 0x20, 0xE9, 5392 0x2A, 0x40, 0x20, 0xE9,
53930x59, 0x3F, 0x59, 0xDF, 5393 0x59, 0x3F, 0x59, 0xDF,
5394 5394
53950x16, 0x30, 0x20, 0xE9, 5395 0x16, 0x30, 0x20, 0xE9,
53960x69, 0x3D, 0x69, 0xDF, 5396 0x69, 0x3D, 0x69, 0xDF,
5397 5397
53980x48, 0x37, 0x48, 0xDF, 5398 0x48, 0x37, 0x48, 0xDF,
53990x58, 0x3F, 0x58, 0xDF, 5399 0x58, 0x3F, 0x58, 0xDF,
5400 5400
54010x12, 0x12, 0x2D, 0xDF, 5401 0x12, 0x12, 0x2D, 0xDF,
54020x22, 0x22, 0x2D, 0xDF, 5402 0x22, 0x22, 0x2D, 0xDF,
5403 5403
54040x32, 0x32, 0x2D, 0xDF, 5404 0x32, 0x32, 0x2D, 0xDF,
54050x3A, 0x3A, 0x2D, 0xDF, 5405 0x3A, 0x3A, 0x2D, 0xDF,
5406 5406
54070x68, 0x3D, 0x68, 0xDF, 5407 0x68, 0x3D, 0x68, 0xDF,
54080x49, 0x37, 0x49, 0xDF, 5408 0x49, 0x37, 0x49, 0xDF,
5409 5409
54100x3D, 0xCF, 0x74, 0xC0, 5410 0x3D, 0xCF, 0x74, 0xC0,
54110x37, 0xCF, 0x74, 0xC4, 5411 0x37, 0xCF, 0x74, 0xC4,
5412 5412
54130x31, 0x53, 0x2F, 0x9F, 5413 0x31, 0x53, 0x2F, 0x9F,
54140x34, 0x80, 0x20, 0xE9, 5414 0x34, 0x80, 0x20, 0xE9,
5415 5415
54160x39, 0xE5, 0x2C, 0x9F, 5416 0x39, 0xE5, 0x2C, 0x9F,
54170x3C, 0x3D, 0x20, 0xE9, 5417 0x3C, 0x3D, 0x20, 0xE9,
5418 5418
54190x0A, 0x44, 0x54, 0xB0, 5419 0x0A, 0x44, 0x54, 0xB0,
54200x02, 0x44, 0x64, 0xB0, 5420 0x02, 0x44, 0x64, 0xB0,
5421 5421
54220x2A, 0x44, 0x54, 0xB2, 5422 0x2A, 0x44, 0x54, 0xB2,
54230x1A, 0x44, 0x64, 0xB2, 5423 0x1A, 0x44, 0x64, 0xB2,
5424 5424
54250x29, 0x80, 0x3A, 0xEA, 5425 0x29, 0x80, 0x3A, 0xEA,
54260x0A, 0x20, 5426 0x0A, 0x20,
54270x02, 0x20, 5427 0x02, 0x20,
5428 5428
54290x0F, 0xCF, 0x74, 0xC6, 5429 0x0F, 0xCF, 0x74, 0xC6,
54300x3D, 0xCF, 0x74, 0xC2, 5430 0x3D, 0xCF, 0x74, 0xC2,
5431 5431
54320x88, 0x73, 0x5E, 0xE9, 5432 0x88, 0x73, 0x5E, 0xE9,
54330x2A, 0x20, 5433 0x2A, 0x20,
54340x1A, 0x20, 5434 0x1A, 0x20,
5435 5435
54360x30, 0x50, 0x2E, 0x9F, 5436 0x30, 0x50, 0x2E, 0x9F,
54370x32, 0x31, 0x5F, 0xE9, 5437 0x32, 0x31, 0x5F, 0xE9,
5438 5438
54390x38, 0x21, 0x2C, 0x9F, 5439 0x38, 0x21, 0x2C, 0x9F,
54400x33, 0x39, 0x5F, 0xE9, 5440 0x33, 0x39, 0x5F, 0xE9,
5441 5441
54420x31, 0x53, 0x2F, 0x9F, 5442 0x31, 0x53, 0x2F, 0x9F,
54430x9C, 0x0F, 0x20, 0xE9, 5443 0x9C, 0x0F, 0x20, 0xE9,
5444 5444
54450x0A, 0x44, 0x54, 0xB4, 5445 0x0A, 0x44, 0x54, 0xB4,
54460x02, 0x44, 0x64, 0xB4, 5446 0x02, 0x44, 0x64, 0xB4,
5447 5447
54480x2A, 0x44, 0x54, 0xB6, 5448 0x2A, 0x44, 0x54, 0xB6,
54490x1A, 0x44, 0x64, 0xB6, 5449 0x1A, 0x44, 0x64, 0xB6,
5450 5450
54510x39, 0xE5, 0x2C, 0x9F, 5451 0x39, 0xE5, 0x2C, 0x9F,
54520x38, 0x3D, 0x20, 0xE9, 5452 0x38, 0x3D, 0x20, 0xE9,
5453 5453
54540x0A, 0x20, 5454 0x0A, 0x20,
54550x02, 0x20, 5455 0x02, 0x20,
54560x2A, 0x20, 5456 0x2A, 0x20,
54570x1A, 0x20, 5457 0x1A, 0x20,
5458 5458
54590x0A, 0x47, 0x57, 0xBF, 5459 0x0A, 0x47, 0x57, 0xBF,
54600x02, 0x47, 0x67, 0xBF, 5460 0x02, 0x47, 0x67, 0xBF,
5461 5461
54620x30, 0x50, 0x2E, 0x9F, 5462 0x30, 0x50, 0x2E, 0x9F,
54630x3E, 0x30, 0x4F, 0xE9, 5463 0x3E, 0x30, 0x4F, 0xE9,
5464 5464
54650x38, 0x21, 0x2C, 0x9F, 5465 0x38, 0x21, 0x2C, 0x9F,
54660x3F, 0x38, 0x4F, 0xE9, 5466 0x3F, 0x38, 0x4F, 0xE9,
5467 5467
54680x2A, 0x46, 0x56, 0xBF, 5468 0x2A, 0x46, 0x56, 0xBF,
54690x1A, 0x46, 0x66, 0xBF, 5469 0x1A, 0x46, 0x66, 0xBF,
5470 5470
54710x31, 0x53, 0x2F, 0x9F, 5471 0x31, 0x53, 0x2F, 0x9F,
54720x3A, 0x31, 0x4F, 0xE9, 5472 0x3A, 0x31, 0x4F, 0xE9,
5473 5473
54740x39, 0xE5, 0x2C, 0x9F, 5474 0x39, 0xE5, 0x2C, 0x9F,
54750x3B, 0x39, 0x4F, 0xE9, 5475 0x3B, 0x39, 0x4F, 0xE9,
5476 5476
54770x31, 0x53, 0x2F, 0x9F, 5477 0x31, 0x53, 0x2F, 0x9F,
54780x36, 0x30, 0x4F, 0xE9, 5478 0x36, 0x30, 0x4F, 0xE9,
5479 5479
54800x39, 0xE5, 0x2C, 0x9F, 5480 0x39, 0xE5, 0x2C, 0x9F,
54810x37, 0x38, 0x4F, 0xE9, 5481 0x37, 0x38, 0x4F, 0xE9,
5482 5482
54830x2A, 0x43, 0x53, 0xBF, 5483 0x2A, 0x43, 0x53, 0xBF,
54840x1A, 0x43, 0x63, 0xBF, 5484 0x1A, 0x43, 0x63, 0xBF,
5485 5485
54860x30, 0x50, 0x2E, 0x9F, 5486 0x30, 0x50, 0x2E, 0x9F,
54870x9D, 0x31, 0x4F, 0xE9, 5487 0x9D, 0x31, 0x4F, 0xE9,
5488 5488
54890x38, 0x21, 0x2C, 0x9F, 5489 0x38, 0x21, 0x2C, 0x9F,
54900x9E, 0x39, 0x4F, 0xE9, 5490 0x9E, 0x39, 0x4F, 0xE9,
5491 5491
54920x0A, 0x48, 0x58, 0xBF, 5492 0x0A, 0x48, 0x58, 0xBF,
54930x02, 0x48, 0x68, 0xBF, 5493 0x02, 0x48, 0x68, 0xBF,
5494 5494
54950x31, 0x53, 0x2F, 0x9F, 5495 0x31, 0x53, 0x2F, 0x9F,
54960x80, 0x31, 0x57, 0xE9, 5496 0x80, 0x31, 0x57, 0xE9,
5497 5497
54980x39, 0xE5, 0x2C, 0x9F, 5498 0x39, 0xE5, 0x2C, 0x9F,
54990x81, 0x39, 0x57, 0xE9, 5499 0x81, 0x39, 0x57, 0xE9,
5500 5500
55010x2A, 0x49, 0x59, 0xBF, 5501 0x2A, 0x49, 0x59, 0xBF,
55020x1A, 0x49, 0x69, 0xBF, 5502 0x1A, 0x49, 0x69, 0xBF,
5503 5503
55040x30, 0x50, 0x2E, 0x9F, 5504 0x30, 0x50, 0x2E, 0x9F,
55050x82, 0x30, 0x57, 0xE9, 5505 0x82, 0x30, 0x57, 0xE9,
5506 5506
55070x38, 0x21, 0x2C, 0x9F, 5507 0x38, 0x21, 0x2C, 0x9F,
55080x83, 0x38, 0x57, 0xE9, 5508 0x83, 0x38, 0x57, 0xE9,
5509 5509
55100x31, 0x53, 0x2F, 0x9F, 5510 0x31, 0x53, 0x2F, 0x9F,
55110x84, 0x31, 0x5E, 0xE9, 5511 0x84, 0x31, 0x5E, 0xE9,
5512 5512
55130x39, 0xE5, 0x2C, 0x9F, 5513 0x39, 0xE5, 0x2C, 0x9F,
55140x85, 0x39, 0x5E, 0xE9, 5514 0x85, 0x39, 0x5E, 0xE9,
5515 5515
55160x86, 0x76, 0x57, 0xE9, 5516 0x86, 0x76, 0x57, 0xE9,
55170x8A, 0x36, 0x20, 0xE9, 5517 0x8A, 0x36, 0x20, 0xE9,
5518 5518
55190x87, 0x77, 0x57, 0xE9, 5519 0x87, 0x77, 0x57, 0xE9,
55200x8B, 0x3E, 0xBF, 0xEA, 5520 0x8B, 0x3E, 0xBF, 0xEA,
5521 5521
55220x80, 0x30, 0x57, 0xE9, 5522 0x80, 0x30, 0x57, 0xE9,
55230x81, 0x38, 0x57, 0xE9, 5523 0x81, 0x38, 0x57, 0xE9,
5524 5524
55250x82, 0x31, 0x57, 0xE9, 5525 0x82, 0x31, 0x57, 0xE9,
55260x86, 0x78, 0x57, 0xE9, 5526 0x86, 0x78, 0x57, 0xE9,
5527 5527
55280x83, 0x39, 0x57, 0xE9, 5528 0x83, 0x39, 0x57, 0xE9,
55290x87, 0x79, 0x57, 0xE9, 5529 0x87, 0x79, 0x57, 0xE9,
5530 5530
55310x30, 0x1F, 0x5F, 0xE9, 5531 0x30, 0x1F, 0x5F, 0xE9,
55320x8A, 0x34, 0x20, 0xE9, 5532 0x8A, 0x34, 0x20, 0xE9,
5533 5533
55340x8B, 0x3C, 0x20, 0xE9, 5534 0x8B, 0x3C, 0x20, 0xE9,
55350x37, 0x50, 0x60, 0xBD, 5535 0x37, 0x50, 0x60, 0xBD,
5536 5536
55370x57, 0x0D, 0x20, 0xE9, 5537 0x57, 0x0D, 0x20, 0xE9,
55380x35, 0x51, 0x61, 0xBD, 5538 0x35, 0x51, 0x61, 0xBD,
5539 5539
55400x2B, 0x50, 0x20, 0xE9, 5540 0x2B, 0x50, 0x20, 0xE9,
55410x1D, 0x37, 0xE1, 0xEA, 5541 0x1D, 0x37, 0xE1, 0xEA,
5542 5542
55430x1E, 0x35, 0xE1, 0xEA, 5543 0x1E, 0x35, 0xE1, 0xEA,
55440x00, 0xE0, 5544 0x00, 0xE0,
55450x0E, 0x77, 5545 0x0E, 0x77,
5546 5546
55470x24, 0x51, 0x20, 0xE9, 5547 0x24, 0x51, 0x20, 0xE9,
55480x9B, 0xFF, 0x20, 0xEA, 5548 0x9B, 0xFF, 0x20, 0xEA,
5549 5549
55500x16, 0x0E, 0x20, 0xE9, 5550 0x16, 0x0E, 0x20, 0xE9,
55510x57, 0x2E, 0xBF, 0xEA, 5551 0x57, 0x2E, 0xBF, 0xEA,
5552 5552
55530x0B, 0x46, 0xA0, 0xE8, 5553 0x0B, 0x46, 0xA0, 0xE8,
55540x1B, 0x56, 0xA0, 0xE8, 5554 0x1B, 0x56, 0xA0, 0xE8,
5555 5555
55560x2B, 0x66, 0xA0, 0xE8, 5556 0x2B, 0x66, 0xA0, 0xE8,
55570x0C, 0x47, 0xA0, 0xE8, 5557 0x0C, 0x47, 0xA0, 0xE8,
5558 5558
55590x1C, 0x57, 0xA0, 0xE8, 5559 0x1C, 0x57, 0xA0, 0xE8,
55600x2C, 0x67, 0xA0, 0xE8, 5560 0x2C, 0x67, 0xA0, 0xE8,
5561 5561
55620x0B, 0x00, 5562 0x0B, 0x00,
55630x1B, 0x00, 5563 0x1B, 0x00,
55640x2B, 0x00, 5564 0x2B, 0x00,
55650x00, 0xE0, 5565 0x00, 0xE0,
5566 5566
55670x0C, 0x00, 5567 0x0C, 0x00,
55680x1C, 0x00, 5568 0x1C, 0x00,
55690x2C, 0x00, 5569 0x2C, 0x00,
55700x00, 0xE0, 5570 0x00, 0xE0,
5571 5571
55720x0B, 0x65, 5572 0x0B, 0x65,
55730x1B, 0x65, 5573 0x1B, 0x65,
55740x2B, 0x65, 5574 0x2B, 0x65,
55750x00, 0xE0, 5575 0x00, 0xE0,
5576 5576
55770x0C, 0x65, 5577 0x0C, 0x65,
55780x1C, 0x65, 5578 0x1C, 0x65,
55790x2C, 0x65, 5579 0x2C, 0x65,
55800x00, 0xE0, 5580 0x00, 0xE0,
5581 5581
55820x0B, 0x1B, 0x60, 0xEC, 5582 0x0B, 0x1B, 0x60, 0xEC,
55830x36, 0xD7, 0x36, 0xAD, 5583 0x36, 0xD7, 0x36, 0xAD,
5584 5584
55850x2B, 0x80, 0x60, 0xEC, 5585 0x2B, 0x80, 0x60, 0xEC,
55860x0C, 0x1C, 0x60, 0xEC, 5586 0x0C, 0x1C, 0x60, 0xEC,
5587 5587
55880x3E, 0xD7, 0x3E, 0xAD, 5588 0x3E, 0xD7, 0x3E, 0xAD,
55890x2C, 0x80, 0x60, 0xEC, 5589 0x2C, 0x80, 0x60, 0xEC,
5590 5590
55910x0B, 0x2B, 0xDE, 0xE8, 5591 0x0B, 0x2B, 0xDE, 0xE8,
55920x1B, 0x80, 0xDE, 0xE8, 5592 0x1B, 0x80, 0xDE, 0xE8,
5593 5593
55940x36, 0x80, 0x36, 0xBD, 5594 0x36, 0x80, 0x36, 0xBD,
55950x3E, 0x80, 0x3E, 0xBD, 5595 0x3E, 0x80, 0x3E, 0xBD,
5596 5596
55970x33, 0xD7, 0x0B, 0xBD, 5597 0x33, 0xD7, 0x0B, 0xBD,
55980x3B, 0xD7, 0x1B, 0xBD, 5598 0x3B, 0xD7, 0x1B, 0xBD,
5599 5599
56000x46, 0x80, 0x46, 0xCF, 5600 0x46, 0x80, 0x46, 0xCF,
56010x57, 0x80, 0x57, 0xCF, 5601 0x57, 0x80, 0x57, 0xCF,
5602 5602
56030x66, 0x33, 0x66, 0xCF, 5603 0x66, 0x33, 0x66, 0xCF,
56040x47, 0x3B, 0x47, 0xCF, 5604 0x47, 0x3B, 0x47, 0xCF,
5605 5605
56060x56, 0x33, 0x56, 0xCF, 5606 0x56, 0x33, 0x56, 0xCF,
56070x67, 0x3B, 0x67, 0xCF, 5607 0x67, 0x3B, 0x67, 0xCF,
5608 5608
56090x0B, 0x48, 0xA0, 0xE8, 5609 0x0B, 0x48, 0xA0, 0xE8,
56100x1B, 0x58, 0xA0, 0xE8, 5610 0x1B, 0x58, 0xA0, 0xE8,
5611 5611
56120x2B, 0x68, 0xA0, 0xE8, 5612 0x2B, 0x68, 0xA0, 0xE8,
56130x0C, 0x49, 0xA0, 0xE8, 5613 0x0C, 0x49, 0xA0, 0xE8,
5614 5614
56150x1C, 0x59, 0xA0, 0xE8, 5615 0x1C, 0x59, 0xA0, 0xE8,
56160x2C, 0x69, 0xA0, 0xE8, 5616 0x2C, 0x69, 0xA0, 0xE8,
5617 5617
56180x0B, 0x00, 5618 0x0B, 0x00,
56190x1B, 0x00, 5619 0x1B, 0x00,
56200x2B, 0x00, 5620 0x2B, 0x00,
56210x00, 0xE0, 5621 0x00, 0xE0,
5622 5622
56230x0C, 0x00, 5623 0x0C, 0x00,
56240x1C, 0x00, 5624 0x1C, 0x00,
56250x2C, 0x00, 5625 0x2C, 0x00,
56260x00, 0xE0, 5626 0x00, 0xE0,
5627 5627
56280x0B, 0x65, 5628 0x0B, 0x65,
56290x1B, 0x65, 5629 0x1B, 0x65,
56300x2B, 0x65, 5630 0x2B, 0x65,
56310x00, 0xE0, 5631 0x00, 0xE0,
5632 5632
56330x0C, 0x65, 5633 0x0C, 0x65,
56340x1C, 0x65, 5634 0x1C, 0x65,
56350x2C, 0x65, 5635 0x2C, 0x65,
56360x00, 0xE0, 5636 0x00, 0xE0,
5637 5637
56380x0B, 0x1B, 0x60, 0xEC, 5638 0x0B, 0x1B, 0x60, 0xEC,
56390x34, 0xD7, 0x34, 0xAD, 5639 0x34, 0xD7, 0x34, 0xAD,
5640 5640
56410x2B, 0x80, 0x60, 0xEC, 5641 0x2B, 0x80, 0x60, 0xEC,
56420x0C, 0x1C, 0x60, 0xEC, 5642 0x0C, 0x1C, 0x60, 0xEC,
5643 5643
56440x3C, 0xD7, 0x3C, 0xAD, 5644 0x3C, 0xD7, 0x3C, 0xAD,
56450x2C, 0x80, 0x60, 0xEC, 5645 0x2C, 0x80, 0x60, 0xEC,
5646 5646
56470x0B, 0x2B, 0xDE, 0xE8, 5647 0x0B, 0x2B, 0xDE, 0xE8,
56480x1B, 0x80, 0xDE, 0xE8, 5648 0x1B, 0x80, 0xDE, 0xE8,
5649 5649
56500x34, 0x80, 0x34, 0xBD, 5650 0x34, 0x80, 0x34, 0xBD,
56510x3C, 0x80, 0x3C, 0xBD, 5651 0x3C, 0x80, 0x3C, 0xBD,
5652 5652
56530x33, 0xD7, 0x0B, 0xBD, 5653 0x33, 0xD7, 0x0B, 0xBD,
56540x3B, 0xD7, 0x1B, 0xBD, 5654 0x3B, 0xD7, 0x1B, 0xBD,
5655 5655
56560x48, 0x80, 0x48, 0xCF, 5656 0x48, 0x80, 0x48, 0xCF,
56570x59, 0x80, 0x59, 0xCF, 5657 0x59, 0x80, 0x59, 0xCF,
5658 5658
56590x68, 0x33, 0x68, 0xCF, 5659 0x68, 0x33, 0x68, 0xCF,
56600x49, 0x3B, 0x49, 0xCF, 5660 0x49, 0x3B, 0x49, 0xCF,
5661 5661
56620xBA, 0xFF, 0x20, 0xEA, 5662 0xBA, 0xFF, 0x20, 0xEA,
56630x00, 0x80, 0x00, 0xE8, 5663 0x00, 0x80, 0x00, 0xE8,
5664 5664
56650x58, 0x33, 0x58, 0xCF, 5665 0x58, 0x33, 0x58, 0xCF,
56660x69, 0x3B, 0x69, 0xCF, 5666 0x69, 0x3B, 0x69, 0xCF,
5667 5667
56680x79, 0xFF, 0x20, 0xEA, 5668 0x79, 0xFF, 0x20, 0xEA,
56690x57, 0xC0, 0xBF, 0xEA, 5669 0x57, 0xC0, 0xBF, 0xEA,
5670 5670
56710x00, 0x80, 0xA0, 0xE9, 5671 0x00, 0x80, 0xA0, 0xE9,
56720x00, 0x00, 0xD8, 0xEC, 5672 0x00, 0x00, 0xD8, 0xEC,
5673 5673
5674}; 5674};
5675 5675
5676static unsigned char warp_g400_t2gzaf[] = { 5676static unsigned char warp_g400_t2gzaf[] = {
5677 5677
56780x00, 0x8A, 0x98, 0xE9, 5678 0x00, 0x8A, 0x98, 0xE9,
56790x00, 0x80, 0x00, 0xE8, 5679 0x00, 0x80, 0x00, 0xE8,
5680 5680
56810x00, 0x80, 0xA0, 0xE9, 5681 0x00, 0x80, 0xA0, 0xE9,
56820x00, 0x00, 0xD8, 0xEC, 5682 0x00, 0x00, 0xD8, 0xEC,
5683 5683
56840xFF, 0x80, 0xC0, 0xE9, 5684 0xFF, 0x80, 0xC0, 0xE9,
56850x00, 0x80, 0x00, 0xE8, 5685 0x00, 0x80, 0x00, 0xE8,
5686 5686
56870x0A, 0x40, 0x50, 0xBF, 5687 0x0A, 0x40, 0x50, 0xBF,
56880x2A, 0x40, 0x60, 0xBF, 5688 0x2A, 0x40, 0x60, 0xBF,
5689 5689
56900x32, 0x41, 0x51, 0xBF, 5690 0x32, 0x41, 0x51, 0xBF,
56910x3A, 0x41, 0x61, 0xBF, 5691 0x3A, 0x41, 0x61, 0xBF,
5692 5692
56930xC3, 0x6B, 5693 0xC3, 0x6B,
56940xD3, 0x6B, 5694 0xD3, 0x6B,
56950x00, 0x8A, 0x98, 0xE9, 5695 0x00, 0x8A, 0x98, 0xE9,
5696 5696
56970x73, 0x7B, 0xC8, 0xEC, 5697 0x73, 0x7B, 0xC8, 0xEC,
56980x96, 0xE2, 5698 0x96, 0xE2,
56990x41, 0x04, 5699 0x41, 0x04,
5700 5700
57010x7B, 0x43, 0xA0, 0xE8, 5701 0x7B, 0x43, 0xA0, 0xE8,
57020x73, 0x53, 0xA0, 0xE8, 5702 0x73, 0x53, 0xA0, 0xE8,
5703 5703
57040xAD, 0xEE, 0x23, 0x9F, 5704 0xAD, 0xEE, 0x23, 0x9F,
57050x00, 0xE0, 5705 0x00, 0xE0,
57060x51, 0x04, 5706 0x51, 0x04,
5707 5707
57080x90, 0xE2, 5708 0x90, 0xE2,
57090x61, 0x04, 5709 0x61, 0x04,
57100x31, 0x46, 0xB1, 0xE8, 5710 0x31, 0x46, 0xB1, 0xE8,
5711 5711
57120x51, 0x41, 0xE0, 0xEC, 5712 0x51, 0x41, 0xE0, 0xEC,
57130x39, 0x67, 0xB1, 0xE8, 5713 0x39, 0x67, 0xB1, 0xE8,
5714 5714
57150x00, 0x04, 5715 0x00, 0x04,
57160x46, 0xE2, 5716 0x46, 0xE2,
57170x73, 0x63, 0xA0, 0xE8, 5717 0x73, 0x63, 0xA0, 0xE8,
5718 5718
57190x61, 0x41, 0xE0, 0xEC, 5719 0x61, 0x41, 0xE0, 0xEC,
57200x31, 0x00, 5720 0x31, 0x00,
57210x39, 0x00, 5721 0x39, 0x00,
5722 5722
57230x81, 0x80, 0x15, 0xEA, 5723 0x81, 0x80, 0x15, 0xEA,
57240x10, 0x04, 5724 0x10, 0x04,
57250x20, 0x04, 5725 0x20, 0x04,
5726 5726
57270x61, 0x51, 0xE0, 0xEC, 5727 0x61, 0x51, 0xE0, 0xEC,
57280x2F, 0x41, 0x60, 0xEA, 5728 0x2F, 0x41, 0x60, 0xEA,
5729 5729
57300x31, 0x20, 5730 0x31, 0x20,
57310x39, 0x20, 5731 0x39, 0x20,
57320x1F, 0x42, 0xA0, 0xE8, 5732 0x1F, 0x42, 0xA0, 0xE8,
5733 5733
57340x2A, 0x42, 0x52, 0xBF, 5734 0x2A, 0x42, 0x52, 0xBF,
57350x0F, 0x52, 0xA0, 0xE8, 5735 0x0F, 0x52, 0xA0, 0xE8,
5736 5736
57370x1A, 0x42, 0x62, 0xBF, 5737 0x1A, 0x42, 0x62, 0xBF,
57380x1E, 0x51, 0x60, 0xEA, 5738 0x1E, 0x51, 0x60, 0xEA,
5739 5739
57400x73, 0x7B, 0xC8, 0xEC, 5740 0x73, 0x7B, 0xC8, 0xEC,
57410x0E, 0x61, 0x60, 0xEA, 5741 0x0E, 0x61, 0x60, 0xEA,
5742 5742
57430x32, 0x40, 0x50, 0xBD, 5743 0x32, 0x40, 0x50, 0xBD,
57440x22, 0x40, 0x60, 0xBD, 5744 0x22, 0x40, 0x60, 0xBD,
5745 5745
57460x12, 0x41, 0x51, 0xBD, 5746 0x12, 0x41, 0x51, 0xBD,
57470x3A, 0x41, 0x61, 0xBD, 5747 0x3A, 0x41, 0x61, 0xBD,
5748 5748
57490xBF, 0x2F, 0x0E, 0xBD, 5749 0xBF, 0x2F, 0x0E, 0xBD,
57500x97, 0xE2, 5750 0x97, 0xE2,
57510x7B, 0x72, 5751 0x7B, 0x72,
5752 5752
57530x32, 0x20, 5753 0x32, 0x20,
57540x22, 0x20, 5754 0x22, 0x20,
57550x12, 0x20, 5755 0x12, 0x20,
57560x3A, 0x20, 5756 0x3A, 0x20,
5757 5757
57580x35, 0x48, 0xB1, 0xE8, 5758 0x35, 0x48, 0xB1, 0xE8,
57590x3D, 0x59, 0xB1, 0xE8, 5759 0x3D, 0x59, 0xB1, 0xE8,
5760 5760
57610x46, 0x31, 0x46, 0xBF, 5761 0x46, 0x31, 0x46, 0xBF,
57620x56, 0x31, 0x56, 0xBF, 5762 0x56, 0x31, 0x56, 0xBF,
5763 5763
57640xB3, 0xE2, 0x2D, 0x9F, 5764 0xB3, 0xE2, 0x2D, 0x9F,
57650x00, 0x80, 0x00, 0xE8, 5765 0x00, 0x80, 0x00, 0xE8,
5766 5766
57670x66, 0x31, 0x66, 0xBF, 5767 0x66, 0x31, 0x66, 0xBF,
57680x47, 0x39, 0x47, 0xBF, 5768 0x47, 0x39, 0x47, 0xBF,
5769 5769
57700x57, 0x39, 0x57, 0xBF, 5770 0x57, 0x39, 0x57, 0xBF,
57710x67, 0x39, 0x67, 0xBF, 5771 0x67, 0x39, 0x67, 0xBF,
5772 5772
57730x72, 0x80, 0x07, 0xEA, 5773 0x72, 0x80, 0x07, 0xEA,
57740x24, 0x41, 0x20, 0xE9, 5774 0x24, 0x41, 0x20, 0xE9,
5775 5775
57760x35, 0x00, 5776 0x35, 0x00,
57770x3D, 0x00, 5777 0x3D, 0x00,
57780x00, 0xE0, 5778 0x00, 0xE0,
57790x2D, 0x73, 5779 0x2D, 0x73,
5780 5780
57810x33, 0x72, 5781 0x33, 0x72,
57820x0C, 0xE3, 5782 0x0C, 0xE3,
57830x8D, 0x2F, 0x1E, 0xBD, 5783 0x8D, 0x2F, 0x1E, 0xBD,
5784 5784
57850x43, 0x75, 0xF8, 0xEC, 5785 0x43, 0x75, 0xF8, 0xEC,
57860x35, 0x20, 5786 0x35, 0x20,
57870x3D, 0x20, 5787 0x3D, 0x20,
5788 5788
57890x43, 0x43, 0x2D, 0xDF, 5789 0x43, 0x43, 0x2D, 0xDF,
57900x53, 0x53, 0x2D, 0xDF, 5790 0x53, 0x53, 0x2D, 0xDF,
5791 5791
57920xAE, 0x1E, 0x0E, 0xBD, 5792 0xAE, 0x1E, 0x0E, 0xBD,
57930x58, 0xE3, 5793 0x58, 0xE3,
57940x33, 0x66, 5794 0x33, 0x66,
5795 5795
57960x48, 0x35, 0x48, 0xBF, 5796 0x48, 0x35, 0x48, 0xBF,
57970x58, 0x35, 0x58, 0xBF, 5797 0x58, 0x35, 0x58, 0xBF,
5798 5798
57990x68, 0x35, 0x68, 0xBF, 5799 0x68, 0x35, 0x68, 0xBF,
58000x49, 0x3D, 0x49, 0xBF, 5800 0x49, 0x3D, 0x49, 0xBF,
5801 5801
58020x59, 0x3D, 0x59, 0xBF, 5802 0x59, 0x3D, 0x59, 0xBF,
58030x69, 0x3D, 0x69, 0xBF, 5803 0x69, 0x3D, 0x69, 0xBF,
5804 5804
58050x63, 0x63, 0x2D, 0xDF, 5805 0x63, 0x63, 0x2D, 0xDF,
58060x4D, 0x7D, 0xF8, 0xEC, 5806 0x4D, 0x7D, 0xF8, 0xEC,
5807 5807
58080x59, 0xE3, 5808 0x59, 0xE3,
58090x00, 0xE0, 5809 0x00, 0xE0,
58100xB8, 0x38, 0x33, 0xBF, 5810 0xB8, 0x38, 0x33, 0xBF,
5811 5811
58120x2D, 0x73, 5812 0x2D, 0x73,
58130x30, 0x76, 5813 0x30, 0x76,
58140x18, 0x3A, 0x41, 0xE9, 5814 0x18, 0x3A, 0x41, 0xE9,
5815 5815
58160x3F, 0x53, 0xA0, 0xE8, 5816 0x3F, 0x53, 0xA0, 0xE8,
58170x05, 0x80, 0x3D, 0xEA, 5817 0x05, 0x80, 0x3D, 0xEA,
5818 5818
58190x37, 0x43, 0xA0, 0xE8, 5819 0x37, 0x43, 0xA0, 0xE8,
58200x3D, 0x63, 0xA0, 0xE8, 5820 0x3D, 0x63, 0xA0, 0xE8,
5821 5821
58220x50, 0x70, 0xF8, 0xEC, 5822 0x50, 0x70, 0xF8, 0xEC,
58230x2B, 0x50, 0x3C, 0xE9, 5823 0x2B, 0x50, 0x3C, 0xE9,
5824 5824
58250x1F, 0x0F, 0xBC, 0xE8, 5825 0x1F, 0x0F, 0xBC, 0xE8,
58260x00, 0x80, 0x00, 0xE8, 5826 0x00, 0x80, 0x00, 0xE8,
5827 5827
58280x59, 0x78, 0xF8, 0xEC, 5828 0x59, 0x78, 0xF8, 0xEC,
58290x00, 0x80, 0x00, 0xE8, 5829 0x00, 0x80, 0x00, 0xE8,
5830 5830
58310x15, 0xC0, 0x20, 0xE9, 5831 0x15, 0xC0, 0x20, 0xE9,
58320x15, 0xC0, 0x20, 0xE9, 5832 0x15, 0xC0, 0x20, 0xE9,
5833 5833
58340x15, 0xC0, 0x20, 0xE9, 5834 0x15, 0xC0, 0x20, 0xE9,
58350x15, 0xC0, 0x20, 0xE9, 5835 0x15, 0xC0, 0x20, 0xE9,
5836 5836
58370x1E, 0x12, 0x41, 0xE9, 5837 0x1E, 0x12, 0x41, 0xE9,
58380x1A, 0x22, 0x41, 0xE9, 5838 0x1A, 0x22, 0x41, 0xE9,
5839 5839
58400x46, 0x37, 0x46, 0xDF, 5840 0x46, 0x37, 0x46, 0xDF,
58410x56, 0x3F, 0x56, 0xDF, 5841 0x56, 0x3F, 0x56, 0xDF,
5842 5842
58430x2B, 0x40, 0x3D, 0xE9, 5843 0x2B, 0x40, 0x3D, 0xE9,
58440x66, 0x3D, 0x66, 0xDF, 5844 0x66, 0x3D, 0x66, 0xDF,
5845 5845
58460x1D, 0x32, 0x41, 0xE9, 5846 0x1D, 0x32, 0x41, 0xE9,
58470x67, 0x3D, 0x67, 0xDF, 5847 0x67, 0x3D, 0x67, 0xDF,
5848 5848
58490x47, 0x37, 0x47, 0xDF, 5849 0x47, 0x37, 0x47, 0xDF,
58500x57, 0x3F, 0x57, 0xDF, 5850 0x57, 0x3F, 0x57, 0xDF,
5851 5851
58520x2A, 0x40, 0x20, 0xE9, 5852 0x2A, 0x40, 0x20, 0xE9,
58530x59, 0x3F, 0x59, 0xDF, 5853 0x59, 0x3F, 0x59, 0xDF,
5854 5854
58550x16, 0x30, 0x20, 0xE9, 5855 0x16, 0x30, 0x20, 0xE9,
58560x69, 0x3D, 0x69, 0xDF, 5856 0x69, 0x3D, 0x69, 0xDF,
5857 5857
58580x48, 0x37, 0x48, 0xDF, 5858 0x48, 0x37, 0x48, 0xDF,
58590x58, 0x3F, 0x58, 0xDF, 5859 0x58, 0x3F, 0x58, 0xDF,
5860 5860
58610x12, 0x12, 0x2D, 0xDF, 5861 0x12, 0x12, 0x2D, 0xDF,
58620x22, 0x22, 0x2D, 0xDF, 5862 0x22, 0x22, 0x2D, 0xDF,
5863 5863
58640x32, 0x32, 0x2D, 0xDF, 5864 0x32, 0x32, 0x2D, 0xDF,
58650x3A, 0x3A, 0x2D, 0xDF, 5865 0x3A, 0x3A, 0x2D, 0xDF,
5866 5866
58670x68, 0x3D, 0x68, 0xDF, 5867 0x68, 0x3D, 0x68, 0xDF,
58680x49, 0x37, 0x49, 0xDF, 5868 0x49, 0x37, 0x49, 0xDF,
5869 5869
58700x3D, 0xCF, 0x74, 0xC0, 5870 0x3D, 0xCF, 0x74, 0xC0,
58710x37, 0xCF, 0x74, 0xC4, 5871 0x37, 0xCF, 0x74, 0xC4,
5872 5872
58730x0A, 0x44, 0x54, 0xB0, 5873 0x0A, 0x44, 0x54, 0xB0,
58740x02, 0x44, 0x64, 0xB0, 5874 0x02, 0x44, 0x64, 0xB0,
5875 5875
58760x31, 0x53, 0x2F, 0x9F, 5876 0x31, 0x53, 0x2F, 0x9F,
58770x34, 0x37, 0x20, 0xE9, 5877 0x34, 0x37, 0x20, 0xE9,
5878 5878
58790x39, 0xE5, 0x2C, 0x9F, 5879 0x39, 0xE5, 0x2C, 0x9F,
58800x3C, 0x3D, 0x20, 0xE9, 5880 0x3C, 0x3D, 0x20, 0xE9,
5881 5881
58820x2A, 0x44, 0x54, 0xB2, 5882 0x2A, 0x44, 0x54, 0xB2,
58830x1A, 0x44, 0x64, 0xB2, 5883 0x1A, 0x44, 0x64, 0xB2,
5884 5884
58850x2E, 0x80, 0x3A, 0xEA, 5885 0x2E, 0x80, 0x3A, 0xEA,
58860x0A, 0x20, 5886 0x0A, 0x20,
58870x02, 0x20, 5887 0x02, 0x20,
5888 5888
58890x88, 0x73, 0x5E, 0xE9, 5889 0x88, 0x73, 0x5E, 0xE9,
58900x2A, 0x20, 5890 0x2A, 0x20,
58910x1A, 0x20, 5891 0x1A, 0x20,
5892 5892
58930x3D, 0xCF, 0x74, 0xC2, 5893 0x3D, 0xCF, 0x74, 0xC2,
58940x0F, 0xCF, 0x74, 0xC6, 5894 0x0F, 0xCF, 0x74, 0xC6,
5895 5895
58960x30, 0x50, 0x2E, 0x9F, 5896 0x30, 0x50, 0x2E, 0x9F,
58970x32, 0x31, 0x5F, 0xE9, 5897 0x32, 0x31, 0x5F, 0xE9,
5898 5898
58990x38, 0x21, 0x2C, 0x9F, 5899 0x38, 0x21, 0x2C, 0x9F,
59000x33, 0x39, 0x5F, 0xE9, 5900 0x33, 0x39, 0x5F, 0xE9,
5901 5901
59020x31, 0x53, 0x2F, 0x9F, 5902 0x31, 0x53, 0x2F, 0x9F,
59030x9C, 0x0F, 0x20, 0xE9, 5903 0x9C, 0x0F, 0x20, 0xE9,
5904 5904
59050x0A, 0x44, 0x54, 0xB4, 5905 0x0A, 0x44, 0x54, 0xB4,
59060x02, 0x44, 0x64, 0xB4, 5906 0x02, 0x44, 0x64, 0xB4,
5907 5907
59080x2A, 0x44, 0x54, 0xB6, 5908 0x2A, 0x44, 0x54, 0xB6,
59090x1A, 0x44, 0x64, 0xB6, 5909 0x1A, 0x44, 0x64, 0xB6,
5910 5910
59110x39, 0xE5, 0x2C, 0x9F, 5911 0x39, 0xE5, 0x2C, 0x9F,
59120x38, 0x3D, 0x20, 0xE9, 5912 0x38, 0x3D, 0x20, 0xE9,
5913 5913
59140x0A, 0x20, 5914 0x0A, 0x20,
59150x02, 0x20, 5915 0x02, 0x20,
59160x2A, 0x20, 5916 0x2A, 0x20,
59170x1A, 0x20, 5917 0x1A, 0x20,
5918 5918
59190x3D, 0xCF, 0x75, 0xC6, 5919 0x3D, 0xCF, 0x75, 0xC6,
59200x00, 0x80, 0x00, 0xE8, 5920 0x00, 0x80, 0x00, 0xE8,
5921 5921
59220x30, 0x50, 0x2E, 0x9F, 5922 0x30, 0x50, 0x2E, 0x9F,
59230x3E, 0x30, 0x4F, 0xE9, 5923 0x3E, 0x30, 0x4F, 0xE9,
5924 5924
59250x38, 0x21, 0x2C, 0x9F, 5925 0x38, 0x21, 0x2C, 0x9F,
59260x3F, 0x38, 0x4F, 0xE9, 5926 0x3F, 0x38, 0x4F, 0xE9,
5927 5927
59280x0A, 0x45, 0x55, 0xB6, 5928 0x0A, 0x45, 0x55, 0xB6,
59290x02, 0x45, 0x65, 0xB6, 5929 0x02, 0x45, 0x65, 0xB6,
5930 5930
59310x31, 0x53, 0x2F, 0x9F, 5931 0x31, 0x53, 0x2F, 0x9F,
59320x3A, 0x31, 0x4F, 0xE9, 5932 0x3A, 0x31, 0x4F, 0xE9,
5933 5933
59340x39, 0xE5, 0x2C, 0x9F, 5934 0x39, 0xE5, 0x2C, 0x9F,
59350x3B, 0x39, 0x4F, 0xE9, 5935 0x3B, 0x39, 0x4F, 0xE9,
5936 5936
59370x31, 0x3D, 0x20, 0xE9, 5937 0x31, 0x3D, 0x20, 0xE9,
59380x0A, 0x20, 5938 0x0A, 0x20,
59390x02, 0x20, 5939 0x02, 0x20,
5940 5940
59410x2A, 0x46, 0x56, 0xBF, 5941 0x2A, 0x46, 0x56, 0xBF,
59420x1A, 0x46, 0x66, 0xBF, 5942 0x1A, 0x46, 0x66, 0xBF,
5943 5943
59440x0A, 0x47, 0x57, 0xBF, 5944 0x0A, 0x47, 0x57, 0xBF,
59450x02, 0x47, 0x67, 0xBF, 5945 0x02, 0x47, 0x67, 0xBF,
5946 5946
59470x30, 0x50, 0x2E, 0x9F, 5947 0x30, 0x50, 0x2E, 0x9F,
59480x36, 0x30, 0x4F, 0xE9, 5948 0x36, 0x30, 0x4F, 0xE9,
5949 5949
59500x38, 0x21, 0x2C, 0x9F, 5950 0x38, 0x21, 0x2C, 0x9F,
59510x37, 0x38, 0x4F, 0xE9, 5951 0x37, 0x38, 0x4F, 0xE9,
5952 5952
59530x31, 0x53, 0x2F, 0x9F, 5953 0x31, 0x53, 0x2F, 0x9F,
59540x9D, 0x31, 0x4F, 0xE9, 5954 0x9D, 0x31, 0x4F, 0xE9,
5955 5955
59560x39, 0xE5, 0x2C, 0x9F, 5956 0x39, 0xE5, 0x2C, 0x9F,
59570x9E, 0x39, 0x4F, 0xE9, 5957 0x9E, 0x39, 0x4F, 0xE9,
5958 5958
59590x2A, 0x43, 0x53, 0xBF, 5959 0x2A, 0x43, 0x53, 0xBF,
59600x1A, 0x43, 0x63, 0xBF, 5960 0x1A, 0x43, 0x63, 0xBF,
5961 5961
59620x30, 0x50, 0x2E, 0x9F, 5962 0x30, 0x50, 0x2E, 0x9F,
59630x35, 0x30, 0x4F, 0xE9, 5963 0x35, 0x30, 0x4F, 0xE9,
5964 5964
59650x38, 0x21, 0x2C, 0x9F, 5965 0x38, 0x21, 0x2C, 0x9F,
59660x39, 0x38, 0x4F, 0xE9, 5966 0x39, 0x38, 0x4F, 0xE9,
5967 5967
59680x0A, 0x48, 0x58, 0xBF, 5968 0x0A, 0x48, 0x58, 0xBF,
59690x02, 0x48, 0x68, 0xBF, 5969 0x02, 0x48, 0x68, 0xBF,
5970 5970
59710x31, 0x53, 0x2F, 0x9F, 5971 0x31, 0x53, 0x2F, 0x9F,
59720x80, 0x31, 0x57, 0xE9, 5972 0x80, 0x31, 0x57, 0xE9,
5973 5973
59740x39, 0xE5, 0x2C, 0x9F, 5974 0x39, 0xE5, 0x2C, 0x9F,
59750x81, 0x39, 0x57, 0xE9, 5975 0x81, 0x39, 0x57, 0xE9,
5976 5976
59770x2A, 0x49, 0x59, 0xBF, 5977 0x2A, 0x49, 0x59, 0xBF,
59780x1A, 0x49, 0x69, 0xBF, 5978 0x1A, 0x49, 0x69, 0xBF,
5979 5979
59800x30, 0x50, 0x2E, 0x9F, 5980 0x30, 0x50, 0x2E, 0x9F,
59810x82, 0x30, 0x57, 0xE9, 5981 0x82, 0x30, 0x57, 0xE9,
5982 5982
59830x38, 0x21, 0x2C, 0x9F, 5983 0x38, 0x21, 0x2C, 0x9F,
59840x83, 0x38, 0x57, 0xE9, 5984 0x83, 0x38, 0x57, 0xE9,
5985 5985
59860x31, 0x53, 0x2F, 0x9F, 5986 0x31, 0x53, 0x2F, 0x9F,
59870x84, 0x31, 0x5E, 0xE9, 5987 0x84, 0x31, 0x5E, 0xE9,
5988 5988
59890x39, 0xE5, 0x2C, 0x9F, 5989 0x39, 0xE5, 0x2C, 0x9F,
59900x85, 0x39, 0x5E, 0xE9, 5990 0x85, 0x39, 0x5E, 0xE9,
5991 5991
59920x86, 0x76, 0x57, 0xE9, 5992 0x86, 0x76, 0x57, 0xE9,
59930x8A, 0x36, 0x20, 0xE9, 5993 0x8A, 0x36, 0x20, 0xE9,
5994 5994
59950x87, 0x77, 0x57, 0xE9, 5995 0x87, 0x77, 0x57, 0xE9,
59960x8B, 0x3E, 0xBF, 0xEA, 5996 0x8B, 0x3E, 0xBF, 0xEA,
5997 5997
59980x80, 0x30, 0x57, 0xE9, 5998 0x80, 0x30, 0x57, 0xE9,
59990x81, 0x38, 0x57, 0xE9, 5999 0x81, 0x38, 0x57, 0xE9,
6000 6000
60010x82, 0x31, 0x57, 0xE9, 6001 0x82, 0x31, 0x57, 0xE9,
60020x86, 0x78, 0x57, 0xE9, 6002 0x86, 0x78, 0x57, 0xE9,
6003 6003
60040x83, 0x39, 0x57, 0xE9, 6004 0x83, 0x39, 0x57, 0xE9,
60050x87, 0x79, 0x57, 0xE9, 6005 0x87, 0x79, 0x57, 0xE9,
6006 6006
60070x30, 0x1F, 0x5F, 0xE9, 6007 0x30, 0x1F, 0x5F, 0xE9,
60080x8A, 0x34, 0x20, 0xE9, 6008 0x8A, 0x34, 0x20, 0xE9,
6009 6009
60100x8B, 0x3C, 0x20, 0xE9, 6010 0x8B, 0x3C, 0x20, 0xE9,
60110x37, 0x50, 0x60, 0xBD, 6011 0x37, 0x50, 0x60, 0xBD,
6012 6012
60130x57, 0x0D, 0x20, 0xE9, 6013 0x57, 0x0D, 0x20, 0xE9,
60140x35, 0x51, 0x61, 0xBD, 6014 0x35, 0x51, 0x61, 0xBD,
6015 6015
60160x2B, 0x50, 0x20, 0xE9, 6016 0x2B, 0x50, 0x20, 0xE9,
60170x1D, 0x37, 0xE1, 0xEA, 6017 0x1D, 0x37, 0xE1, 0xEA,
6018 6018
60190x1E, 0x35, 0xE1, 0xEA, 6019 0x1E, 0x35, 0xE1, 0xEA,
60200x00, 0xE0, 6020 0x00, 0xE0,
60210x0E, 0x77, 6021 0x0E, 0x77,
6022 6022
60230x24, 0x51, 0x20, 0xE9, 6023 0x24, 0x51, 0x20, 0xE9,
60240x96, 0xFF, 0x20, 0xEA, 6024 0x96, 0xFF, 0x20, 0xEA,
6025 6025
60260x16, 0x0E, 0x20, 0xE9, 6026 0x16, 0x0E, 0x20, 0xE9,
60270x57, 0x2E, 0xBF, 0xEA, 6027 0x57, 0x2E, 0xBF, 0xEA,
6028 6028
60290x0B, 0x46, 0xA0, 0xE8, 6029 0x0B, 0x46, 0xA0, 0xE8,
60300x1B, 0x56, 0xA0, 0xE8, 6030 0x1B, 0x56, 0xA0, 0xE8,
6031 6031
60320x2B, 0x66, 0xA0, 0xE8, 6032 0x2B, 0x66, 0xA0, 0xE8,
60330x0C, 0x47, 0xA0, 0xE8, 6033 0x0C, 0x47, 0xA0, 0xE8,
6034 6034
60350x1C, 0x57, 0xA0, 0xE8, 6035 0x1C, 0x57, 0xA0, 0xE8,
60360x2C, 0x67, 0xA0, 0xE8, 6036 0x2C, 0x67, 0xA0, 0xE8,
6037 6037
60380x0B, 0x00, 6038 0x0B, 0x00,
60390x1B, 0x00, 6039 0x1B, 0x00,
60400x2B, 0x00, 6040 0x2B, 0x00,
60410x00, 0xE0, 6041 0x00, 0xE0,
6042 6042
60430x0C, 0x00, 6043 0x0C, 0x00,
60440x1C, 0x00, 6044 0x1C, 0x00,
60450x2C, 0x00, 6045 0x2C, 0x00,
60460x00, 0xE0, 6046 0x00, 0xE0,
6047 6047
60480x0B, 0x65, 6048 0x0B, 0x65,
60490x1B, 0x65, 6049 0x1B, 0x65,
60500x2B, 0x65, 6050 0x2B, 0x65,
60510x00, 0xE0, 6051 0x00, 0xE0,
6052 6052
60530x0C, 0x65, 6053 0x0C, 0x65,
60540x1C, 0x65, 6054 0x1C, 0x65,
60550x2C, 0x65, 6055 0x2C, 0x65,
60560x00, 0xE0, 6056 0x00, 0xE0,
6057 6057
60580x0B, 0x1B, 0x60, 0xEC, 6058 0x0B, 0x1B, 0x60, 0xEC,
60590x36, 0xD7, 0x36, 0xAD, 6059 0x36, 0xD7, 0x36, 0xAD,
6060 6060
60610x2B, 0x80, 0x60, 0xEC, 6061 0x2B, 0x80, 0x60, 0xEC,
60620x0C, 0x1C, 0x60, 0xEC, 6062 0x0C, 0x1C, 0x60, 0xEC,
6063 6063
60640x3E, 0xD7, 0x3E, 0xAD, 6064 0x3E, 0xD7, 0x3E, 0xAD,
60650x2C, 0x80, 0x60, 0xEC, 6065 0x2C, 0x80, 0x60, 0xEC,
6066 6066
60670x0B, 0x2B, 0xDE, 0xE8, 6067 0x0B, 0x2B, 0xDE, 0xE8,
60680x1B, 0x80, 0xDE, 0xE8, 6068 0x1B, 0x80, 0xDE, 0xE8,
6069 6069
60700x36, 0x80, 0x36, 0xBD, 6070 0x36, 0x80, 0x36, 0xBD,
60710x3E, 0x80, 0x3E, 0xBD, 6071 0x3E, 0x80, 0x3E, 0xBD,
6072 6072
60730x33, 0xD7, 0x0B, 0xBD, 6073 0x33, 0xD7, 0x0B, 0xBD,
60740x3B, 0xD7, 0x1B, 0xBD, 6074 0x3B, 0xD7, 0x1B, 0xBD,
6075 6075
60760x46, 0x80, 0x46, 0xCF, 6076 0x46, 0x80, 0x46, 0xCF,
60770x57, 0x80, 0x57, 0xCF, 6077 0x57, 0x80, 0x57, 0xCF,
6078 6078
60790x66, 0x33, 0x66, 0xCF, 6079 0x66, 0x33, 0x66, 0xCF,
60800x47, 0x3B, 0x47, 0xCF, 6080 0x47, 0x3B, 0x47, 0xCF,
6081 6081
60820x56, 0x33, 0x56, 0xCF, 6082 0x56, 0x33, 0x56, 0xCF,
60830x67, 0x3B, 0x67, 0xCF, 6083 0x67, 0x3B, 0x67, 0xCF,
6084 6084
60850x0B, 0x48, 0xA0, 0xE8, 6085 0x0B, 0x48, 0xA0, 0xE8,
60860x1B, 0x58, 0xA0, 0xE8, 6086 0x1B, 0x58, 0xA0, 0xE8,
6087 6087
60880x2B, 0x68, 0xA0, 0xE8, 6088 0x2B, 0x68, 0xA0, 0xE8,
60890x0C, 0x49, 0xA0, 0xE8, 6089 0x0C, 0x49, 0xA0, 0xE8,
6090 6090
60910x1C, 0x59, 0xA0, 0xE8, 6091 0x1C, 0x59, 0xA0, 0xE8,
60920x2C, 0x69, 0xA0, 0xE8, 6092 0x2C, 0x69, 0xA0, 0xE8,
6093 6093
60940x0B, 0x00, 6094 0x0B, 0x00,
60950x1B, 0x00, 6095 0x1B, 0x00,
60960x2B, 0x00, 6096 0x2B, 0x00,
60970x00, 0xE0, 6097 0x00, 0xE0,
6098 6098
60990x0C, 0x00, 6099 0x0C, 0x00,
61000x1C, 0x00, 6100 0x1C, 0x00,
61010x2C, 0x00, 6101 0x2C, 0x00,
61020x00, 0xE0, 6102 0x00, 0xE0,
6103 6103
61040x0B, 0x65, 6104 0x0B, 0x65,
61050x1B, 0x65, 6105 0x1B, 0x65,
61060x2B, 0x65, 6106 0x2B, 0x65,
61070x00, 0xE0, 6107 0x00, 0xE0,
6108 6108
61090x0C, 0x65, 6109 0x0C, 0x65,
61100x1C, 0x65, 6110 0x1C, 0x65,
61110x2C, 0x65, 6111 0x2C, 0x65,
61120x00, 0xE0, 6112 0x00, 0xE0,
6113 6113
61140x0B, 0x1B, 0x60, 0xEC, 6114 0x0B, 0x1B, 0x60, 0xEC,
61150x34, 0xD7, 0x34, 0xAD, 6115 0x34, 0xD7, 0x34, 0xAD,
6116 6116
61170x2B, 0x80, 0x60, 0xEC, 6117 0x2B, 0x80, 0x60, 0xEC,
61180x0C, 0x1C, 0x60, 0xEC, 6118 0x0C, 0x1C, 0x60, 0xEC,
6119 6119
61200x3C, 0xD7, 0x3C, 0xAD, 6120 0x3C, 0xD7, 0x3C, 0xAD,
61210x2C, 0x80, 0x60, 0xEC, 6121 0x2C, 0x80, 0x60, 0xEC,
6122 6122
61230x0B, 0x2B, 0xDE, 0xE8, 6123 0x0B, 0x2B, 0xDE, 0xE8,
61240x1B, 0x80, 0xDE, 0xE8, 6124 0x1B, 0x80, 0xDE, 0xE8,
6125 6125
61260x34, 0x80, 0x34, 0xBD, 6126 0x34, 0x80, 0x34, 0xBD,
61270x3C, 0x80, 0x3C, 0xBD, 6127 0x3C, 0x80, 0x3C, 0xBD,
6128 6128
61290x33, 0xD7, 0x0B, 0xBD, 6129 0x33, 0xD7, 0x0B, 0xBD,
61300x3B, 0xD7, 0x1B, 0xBD, 6130 0x3B, 0xD7, 0x1B, 0xBD,
6131 6131
61320x48, 0x80, 0x48, 0xCF, 6132 0x48, 0x80, 0x48, 0xCF,
61330x59, 0x80, 0x59, 0xCF, 6133 0x59, 0x80, 0x59, 0xCF,
6134 6134
61350x68, 0x33, 0x68, 0xCF, 6135 0x68, 0x33, 0x68, 0xCF,
61360x49, 0x3B, 0x49, 0xCF, 6136 0x49, 0x3B, 0x49, 0xCF,
6137 6137
61380xB5, 0xFF, 0x20, 0xEA, 6138 0xB5, 0xFF, 0x20, 0xEA,
61390x00, 0x80, 0x00, 0xE8, 6139 0x00, 0x80, 0x00, 0xE8,
6140 6140
61410x58, 0x33, 0x58, 0xCF, 6141 0x58, 0x33, 0x58, 0xCF,
61420x69, 0x3B, 0x69, 0xCF, 6142 0x69, 0x3B, 0x69, 0xCF,
6143 6143
61440x74, 0xFF, 0x20, 0xEA, 6144 0x74, 0xFF, 0x20, 0xEA,
61450x57, 0xC0, 0xBF, 0xEA, 6145 0x57, 0xC0, 0xBF, 0xEA,
6146 6146
61470x00, 0x80, 0xA0, 0xE9, 6147 0x00, 0x80, 0xA0, 0xE9,
61480x00, 0x00, 0xD8, 0xEC, 6148 0x00, 0x00, 0xD8, 0xEC,
6149 6149
6150}; 6150};
6151 6151
6152static unsigned char warp_g400_t2gzf[] = { 6152static unsigned char warp_g400_t2gzf[] = {
6153 6153
61540x00, 0x8A, 0x98, 0xE9, 6154 0x00, 0x8A, 0x98, 0xE9,
61550x00, 0x80, 0x00, 0xE8, 6155 0x00, 0x80, 0x00, 0xE8,
6156 6156
61570x00, 0x80, 0xA0, 0xE9, 6157 0x00, 0x80, 0xA0, 0xE9,
61580x00, 0x00, 0xD8, 0xEC, 6158 0x00, 0x00, 0xD8, 0xEC,
6159 6159
61600xFF, 0x80, 0xC0, 0xE9, 6160 0xFF, 0x80, 0xC0, 0xE9,
61610x00, 0x80, 0x00, 0xE8, 6161 0x00, 0x80, 0x00, 0xE8,
6162 6162
61630x0A, 0x40, 0x50, 0xBF, 6163 0x0A, 0x40, 0x50, 0xBF,
61640x2A, 0x40, 0x60, 0xBF, 6164 0x2A, 0x40, 0x60, 0xBF,
6165 6165
61660x32, 0x41, 0x51, 0xBF, 6166 0x32, 0x41, 0x51, 0xBF,
61670x3A, 0x41, 0x61, 0xBF, 6167 0x3A, 0x41, 0x61, 0xBF,
6168 6168
61690xC3, 0x6B, 6169 0xC3, 0x6B,
61700xD3, 0x6B, 6170 0xD3, 0x6B,
61710x00, 0x8A, 0x98, 0xE9, 6171 0x00, 0x8A, 0x98, 0xE9,
6172 6172
61730x73, 0x7B, 0xC8, 0xEC, 6173 0x73, 0x7B, 0xC8, 0xEC,
61740x96, 0xE2, 6174 0x96, 0xE2,
61750x41, 0x04, 6175 0x41, 0x04,
6176 6176
61770x7B, 0x43, 0xA0, 0xE8, 6177 0x7B, 0x43, 0xA0, 0xE8,
61780x73, 0x53, 0xA0, 0xE8, 6178 0x73, 0x53, 0xA0, 0xE8,
6179 6179
61800xAD, 0xEE, 0x23, 0x9F, 6180 0xAD, 0xEE, 0x23, 0x9F,
61810x00, 0xE0, 6181 0x00, 0xE0,
61820x51, 0x04, 6182 0x51, 0x04,
6183 6183
61840x90, 0xE2, 6184 0x90, 0xE2,
61850x61, 0x04, 6185 0x61, 0x04,
61860x31, 0x46, 0xB1, 0xE8, 6186 0x31, 0x46, 0xB1, 0xE8,
6187 6187
61880x51, 0x41, 0xE0, 0xEC, 6188 0x51, 0x41, 0xE0, 0xEC,
61890x39, 0x67, 0xB1, 0xE8, 6189 0x39, 0x67, 0xB1, 0xE8,
6190 6190
61910x00, 0x04, 6191 0x00, 0x04,
61920x46, 0xE2, 6192 0x46, 0xE2,
61930x73, 0x63, 0xA0, 0xE8, 6193 0x73, 0x63, 0xA0, 0xE8,
6194 6194
61950x61, 0x41, 0xE0, 0xEC, 6195 0x61, 0x41, 0xE0, 0xEC,
61960x31, 0x00, 6196 0x31, 0x00,
61970x39, 0x00, 6197 0x39, 0x00,
6198 6198
61990x7D, 0x80, 0x15, 0xEA, 6199 0x7D, 0x80, 0x15, 0xEA,
62000x10, 0x04, 6200 0x10, 0x04,
62010x20, 0x04, 6201 0x20, 0x04,
6202 6202
62030x61, 0x51, 0xE0, 0xEC, 6203 0x61, 0x51, 0xE0, 0xEC,
62040x2F, 0x41, 0x60, 0xEA, 6204 0x2F, 0x41, 0x60, 0xEA,
6205 6205
62060x31, 0x20, 6206 0x31, 0x20,
62070x39, 0x20, 6207 0x39, 0x20,
62080x1F, 0x42, 0xA0, 0xE8, 6208 0x1F, 0x42, 0xA0, 0xE8,
6209 6209
62100x2A, 0x42, 0x52, 0xBF, 6210 0x2A, 0x42, 0x52, 0xBF,
62110x0F, 0x52, 0xA0, 0xE8, 6211 0x0F, 0x52, 0xA0, 0xE8,
6212 6212
62130x1A, 0x42, 0x62, 0xBF, 6213 0x1A, 0x42, 0x62, 0xBF,
62140x1E, 0x51, 0x60, 0xEA, 6214 0x1E, 0x51, 0x60, 0xEA,
6215 6215
62160x73, 0x7B, 0xC8, 0xEC, 6216 0x73, 0x7B, 0xC8, 0xEC,
62170x0E, 0x61, 0x60, 0xEA, 6217 0x0E, 0x61, 0x60, 0xEA,
6218 6218
62190x32, 0x40, 0x50, 0xBD, 6219 0x32, 0x40, 0x50, 0xBD,
62200x22, 0x40, 0x60, 0xBD, 6220 0x22, 0x40, 0x60, 0xBD,
6221 6221
62220x12, 0x41, 0x51, 0xBD, 6222 0x12, 0x41, 0x51, 0xBD,
62230x3A, 0x41, 0x61, 0xBD, 6223 0x3A, 0x41, 0x61, 0xBD,
6224 6224
62250xBF, 0x2F, 0x0E, 0xBD, 6225 0xBF, 0x2F, 0x0E, 0xBD,
62260x97, 0xE2, 6226 0x97, 0xE2,
62270x7B, 0x72, 6227 0x7B, 0x72,
6228 6228
62290x32, 0x20, 6229 0x32, 0x20,
62300x22, 0x20, 6230 0x22, 0x20,
62310x12, 0x20, 6231 0x12, 0x20,
62320x3A, 0x20, 6232 0x3A, 0x20,
6233 6233
62340x35, 0x48, 0xB1, 0xE8, 6234 0x35, 0x48, 0xB1, 0xE8,
62350x3D, 0x59, 0xB1, 0xE8, 6235 0x3D, 0x59, 0xB1, 0xE8,
6236 6236
62370x46, 0x31, 0x46, 0xBF, 6237 0x46, 0x31, 0x46, 0xBF,
62380x56, 0x31, 0x56, 0xBF, 6238 0x56, 0x31, 0x56, 0xBF,
6239 6239
62400xB3, 0xE2, 0x2D, 0x9F, 6240 0xB3, 0xE2, 0x2D, 0x9F,
62410x00, 0x80, 0x00, 0xE8, 6241 0x00, 0x80, 0x00, 0xE8,
6242 6242
62430x66, 0x31, 0x66, 0xBF, 6243 0x66, 0x31, 0x66, 0xBF,
62440x47, 0x39, 0x47, 0xBF, 6244 0x47, 0x39, 0x47, 0xBF,
6245 6245
62460x57, 0x39, 0x57, 0xBF, 6246 0x57, 0x39, 0x57, 0xBF,
62470x67, 0x39, 0x67, 0xBF, 6247 0x67, 0x39, 0x67, 0xBF,
6248 6248
62490x6E, 0x80, 0x07, 0xEA, 6249 0x6E, 0x80, 0x07, 0xEA,
62500x24, 0x41, 0x20, 0xE9, 6250 0x24, 0x41, 0x20, 0xE9,
6251 6251
62520x35, 0x00, 6252 0x35, 0x00,
62530x3D, 0x00, 6253 0x3D, 0x00,
62540x00, 0xE0, 6254 0x00, 0xE0,
62550x2D, 0x73, 6255 0x2D, 0x73,
6256 6256
62570x33, 0x72, 6257 0x33, 0x72,
62580x0C, 0xE3, 6258 0x0C, 0xE3,
62590x8D, 0x2F, 0x1E, 0xBD, 6259 0x8D, 0x2F, 0x1E, 0xBD,
6260 6260
62610x43, 0x75, 0xF8, 0xEC, 6261 0x43, 0x75, 0xF8, 0xEC,
62620x35, 0x20, 6262 0x35, 0x20,
62630x3D, 0x20, 6263 0x3D, 0x20,
6264 6264
62650x43, 0x43, 0x2D, 0xDF, 6265 0x43, 0x43, 0x2D, 0xDF,
62660x53, 0x53, 0x2D, 0xDF, 6266 0x53, 0x53, 0x2D, 0xDF,
6267 6267
62680xAE, 0x1E, 0x0E, 0xBD, 6268 0xAE, 0x1E, 0x0E, 0xBD,
62690x58, 0xE3, 6269 0x58, 0xE3,
62700x33, 0x66, 6270 0x33, 0x66,
6271 6271
62720x48, 0x35, 0x48, 0xBF, 6272 0x48, 0x35, 0x48, 0xBF,
62730x58, 0x35, 0x58, 0xBF, 6273 0x58, 0x35, 0x58, 0xBF,
6274 6274
62750x68, 0x35, 0x68, 0xBF, 6275 0x68, 0x35, 0x68, 0xBF,
62760x49, 0x3D, 0x49, 0xBF, 6276 0x49, 0x3D, 0x49, 0xBF,
6277 6277
62780x59, 0x3D, 0x59, 0xBF, 6278 0x59, 0x3D, 0x59, 0xBF,
62790x69, 0x3D, 0x69, 0xBF, 6279 0x69, 0x3D, 0x69, 0xBF,
6280 6280
62810x63, 0x63, 0x2D, 0xDF, 6281 0x63, 0x63, 0x2D, 0xDF,
62820x4D, 0x7D, 0xF8, 0xEC, 6282 0x4D, 0x7D, 0xF8, 0xEC,
6283 6283
62840x59, 0xE3, 6284 0x59, 0xE3,
62850x00, 0xE0, 6285 0x00, 0xE0,
62860xB8, 0x38, 0x33, 0xBF, 6286 0xB8, 0x38, 0x33, 0xBF,
6287 6287
62880x2D, 0x73, 6288 0x2D, 0x73,
62890x30, 0x76, 6289 0x30, 0x76,
62900x18, 0x3A, 0x41, 0xE9, 6290 0x18, 0x3A, 0x41, 0xE9,
6291 6291
62920x3F, 0x53, 0xA0, 0xE8, 6292 0x3F, 0x53, 0xA0, 0xE8,
62930x05, 0x80, 0x3D, 0xEA, 6293 0x05, 0x80, 0x3D, 0xEA,
6294 6294
62950x37, 0x43, 0xA0, 0xE8, 6295 0x37, 0x43, 0xA0, 0xE8,
62960x3D, 0x63, 0xA0, 0xE8, 6296 0x3D, 0x63, 0xA0, 0xE8,
6297 6297
62980x50, 0x70, 0xF8, 0xEC, 6298 0x50, 0x70, 0xF8, 0xEC,
62990x2B, 0x50, 0x3C, 0xE9, 6299 0x2B, 0x50, 0x3C, 0xE9,
6300 6300
63010x1F, 0x0F, 0xBC, 0xE8, 6301 0x1F, 0x0F, 0xBC, 0xE8,
63020x00, 0x80, 0x00, 0xE8, 6302 0x00, 0x80, 0x00, 0xE8,
6303 6303
63040x59, 0x78, 0xF8, 0xEC, 6304 0x59, 0x78, 0xF8, 0xEC,
63050x00, 0x80, 0x00, 0xE8, 6305 0x00, 0x80, 0x00, 0xE8,
6306 6306
63070x15, 0xC0, 0x20, 0xE9, 6307 0x15, 0xC0, 0x20, 0xE9,
63080x15, 0xC0, 0x20, 0xE9, 6308 0x15, 0xC0, 0x20, 0xE9,
6309 6309
63100x15, 0xC0, 0x20, 0xE9, 6310 0x15, 0xC0, 0x20, 0xE9,
63110x15, 0xC0, 0x20, 0xE9, 6311 0x15, 0xC0, 0x20, 0xE9,
6312 6312
63130x1E, 0x12, 0x41, 0xE9, 6313 0x1E, 0x12, 0x41, 0xE9,
63140x1A, 0x22, 0x41, 0xE9, 6314 0x1A, 0x22, 0x41, 0xE9,
6315 6315
63160x46, 0x37, 0x46, 0xDF, 6316 0x46, 0x37, 0x46, 0xDF,
63170x56, 0x3F, 0x56, 0xDF, 6317 0x56, 0x3F, 0x56, 0xDF,
6318 6318
63190x2B, 0x40, 0x3D, 0xE9, 6319 0x2B, 0x40, 0x3D, 0xE9,
63200x66, 0x3D, 0x66, 0xDF, 6320 0x66, 0x3D, 0x66, 0xDF,
6321 6321
63220x1D, 0x32, 0x41, 0xE9, 6322 0x1D, 0x32, 0x41, 0xE9,
63230x67, 0x3D, 0x67, 0xDF, 6323 0x67, 0x3D, 0x67, 0xDF,
6324 6324
63250x47, 0x37, 0x47, 0xDF, 6325 0x47, 0x37, 0x47, 0xDF,
63260x57, 0x3F, 0x57, 0xDF, 6326 0x57, 0x3F, 0x57, 0xDF,
6327 6327
63280x2A, 0x40, 0x20, 0xE9, 6328 0x2A, 0x40, 0x20, 0xE9,
63290x59, 0x3F, 0x59, 0xDF, 6329 0x59, 0x3F, 0x59, 0xDF,
6330 6330
63310x16, 0x30, 0x20, 0xE9, 6331 0x16, 0x30, 0x20, 0xE9,
63320x69, 0x3D, 0x69, 0xDF, 6332 0x69, 0x3D, 0x69, 0xDF,
6333 6333
63340x48, 0x37, 0x48, 0xDF, 6334 0x48, 0x37, 0x48, 0xDF,
63350x58, 0x3F, 0x58, 0xDF, 6335 0x58, 0x3F, 0x58, 0xDF,
6336 6336
63370x12, 0x12, 0x2D, 0xDF, 6337 0x12, 0x12, 0x2D, 0xDF,
63380x22, 0x22, 0x2D, 0xDF, 6338 0x22, 0x22, 0x2D, 0xDF,
6339 6339
63400x32, 0x32, 0x2D, 0xDF, 6340 0x32, 0x32, 0x2D, 0xDF,
63410x3A, 0x3A, 0x2D, 0xDF, 6341 0x3A, 0x3A, 0x2D, 0xDF,
6342 6342
63430x68, 0x3D, 0x68, 0xDF, 6343 0x68, 0x3D, 0x68, 0xDF,
63440x49, 0x37, 0x49, 0xDF, 6344 0x49, 0x37, 0x49, 0xDF,
6345 6345
63460x3D, 0xCF, 0x74, 0xC0, 6346 0x3D, 0xCF, 0x74, 0xC0,
63470x37, 0xCF, 0x74, 0xC4, 6347 0x37, 0xCF, 0x74, 0xC4,
6348 6348
63490x39, 0xE5, 0x2C, 0x9F, 6349 0x39, 0xE5, 0x2C, 0x9F,
63500x34, 0x80, 0x20, 0xE9, 6350 0x34, 0x80, 0x20, 0xE9,
6351 6351
63520x31, 0x53, 0x2F, 0x9F, 6352 0x31, 0x53, 0x2F, 0x9F,
63530x00, 0x80, 0x00, 0xE8, 6353 0x00, 0x80, 0x00, 0xE8,
6354 6354
63550x88, 0x73, 0x5E, 0xE9, 6355 0x88, 0x73, 0x5E, 0xE9,
63560x00, 0x80, 0x00, 0xE8, 6356 0x00, 0x80, 0x00, 0xE8,
6357 6357
63580x0F, 0xCF, 0x75, 0xC6, 6358 0x0F, 0xCF, 0x75, 0xC6,
63590x3C, 0x3D, 0x20, 0xE9, 6359 0x3C, 0x3D, 0x20, 0xE9,
6360 6360
63610x0A, 0x44, 0x54, 0xB0, 6361 0x0A, 0x44, 0x54, 0xB0,
63620x02, 0x44, 0x64, 0xB0, 6362 0x02, 0x44, 0x64, 0xB0,
6363 6363
63640x2A, 0x44, 0x54, 0xB2, 6364 0x2A, 0x44, 0x54, 0xB2,
63650x1A, 0x44, 0x64, 0xB2, 6365 0x1A, 0x44, 0x64, 0xB2,
6366 6366
63670x28, 0x80, 0x3A, 0xEA, 6367 0x28, 0x80, 0x3A, 0xEA,
63680x0A, 0x20, 6368 0x0A, 0x20,
63690x02, 0x20, 6369 0x02, 0x20,
6370 6370
63710x3D, 0xCF, 0x74, 0xC2, 6371 0x3D, 0xCF, 0x74, 0xC2,
63720x2A, 0x20, 6372 0x2A, 0x20,
63730x1A, 0x20, 6373 0x1A, 0x20,
6374 6374
63750x30, 0x50, 0x2E, 0x9F, 6375 0x30, 0x50, 0x2E, 0x9F,
63760x32, 0x31, 0x5F, 0xE9, 6376 0x32, 0x31, 0x5F, 0xE9,
6377 6377
63780x38, 0x21, 0x2C, 0x9F, 6378 0x38, 0x21, 0x2C, 0x9F,
63790x33, 0x39, 0x5F, 0xE9, 6379 0x33, 0x39, 0x5F, 0xE9,
6380 6380
63810x31, 0x53, 0x2F, 0x9F, 6381 0x31, 0x53, 0x2F, 0x9F,
63820x31, 0x0F, 0x20, 0xE9, 6382 0x31, 0x0F, 0x20, 0xE9,
6383 6383
63840x0A, 0x44, 0x54, 0xB4, 6384 0x0A, 0x44, 0x54, 0xB4,
63850x02, 0x44, 0x64, 0xB4, 6385 0x02, 0x44, 0x64, 0xB4,
6386 6386
63870x2A, 0x45, 0x55, 0xB6, 6387 0x2A, 0x45, 0x55, 0xB6,
63880x1A, 0x45, 0x65, 0xB6, 6388 0x1A, 0x45, 0x65, 0xB6,
6389 6389
63900x39, 0xE5, 0x2C, 0x9F, 6390 0x39, 0xE5, 0x2C, 0x9F,
63910x38, 0x3D, 0x20, 0xE9, 6391 0x38, 0x3D, 0x20, 0xE9,
6392 6392
63930x0A, 0x20, 6393 0x0A, 0x20,
63940x02, 0x20, 6394 0x02, 0x20,
63950x2A, 0x20, 6395 0x2A, 0x20,
63960x1A, 0x20, 6396 0x1A, 0x20,
6397 6397
63980x0A, 0x47, 0x57, 0xBF, 6398 0x0A, 0x47, 0x57, 0xBF,
63990x02, 0x47, 0x67, 0xBF, 6399 0x02, 0x47, 0x67, 0xBF,
6400 6400
64010x30, 0x50, 0x2E, 0x9F, 6401 0x30, 0x50, 0x2E, 0x9F,
64020x3E, 0x30, 0x4F, 0xE9, 6402 0x3E, 0x30, 0x4F, 0xE9,
6403 6403
64040x38, 0x21, 0x2C, 0x9F, 6404 0x38, 0x21, 0x2C, 0x9F,
64050x3F, 0x38, 0x4F, 0xE9, 6405 0x3F, 0x38, 0x4F, 0xE9,
6406 6406
64070x2A, 0x46, 0x56, 0xBF, 6407 0x2A, 0x46, 0x56, 0xBF,
64080x1A, 0x46, 0x66, 0xBF, 6408 0x1A, 0x46, 0x66, 0xBF,
6409 6409
64100x31, 0x53, 0x2F, 0x9F, 6410 0x31, 0x53, 0x2F, 0x9F,
64110x3A, 0x31, 0x4F, 0xE9, 6411 0x3A, 0x31, 0x4F, 0xE9,
6412 6412
64130x39, 0xE5, 0x2C, 0x9F, 6413 0x39, 0xE5, 0x2C, 0x9F,
64140x3B, 0x39, 0x4F, 0xE9, 6414 0x3B, 0x39, 0x4F, 0xE9,
6415 6415
64160x31, 0x53, 0x2F, 0x9F, 6416 0x31, 0x53, 0x2F, 0x9F,
64170x36, 0x30, 0x4F, 0xE9, 6417 0x36, 0x30, 0x4F, 0xE9,
6418 6418
64190x39, 0xE5, 0x2C, 0x9F, 6419 0x39, 0xE5, 0x2C, 0x9F,
64200x37, 0x38, 0x4F, 0xE9, 6420 0x37, 0x38, 0x4F, 0xE9,
6421 6421
64220x2A, 0x43, 0x53, 0xBF, 6422 0x2A, 0x43, 0x53, 0xBF,
64230x1A, 0x43, 0x63, 0xBF, 6423 0x1A, 0x43, 0x63, 0xBF,
6424 6424
64250x30, 0x50, 0x2E, 0x9F, 6425 0x30, 0x50, 0x2E, 0x9F,
64260x35, 0x31, 0x4F, 0xE9, 6426 0x35, 0x31, 0x4F, 0xE9,
6427 6427
64280x38, 0x21, 0x2C, 0x9F, 6428 0x38, 0x21, 0x2C, 0x9F,
64290x39, 0x39, 0x4F, 0xE9, 6429 0x39, 0x39, 0x4F, 0xE9,
6430 6430
64310x0A, 0x48, 0x58, 0xBF, 6431 0x0A, 0x48, 0x58, 0xBF,
64320x02, 0x48, 0x68, 0xBF, 6432 0x02, 0x48, 0x68, 0xBF,
6433 6433
64340x31, 0x53, 0x2F, 0x9F, 6434 0x31, 0x53, 0x2F, 0x9F,
64350x80, 0x31, 0x57, 0xE9, 6435 0x80, 0x31, 0x57, 0xE9,
6436 6436
64370x39, 0xE5, 0x2C, 0x9F, 6437 0x39, 0xE5, 0x2C, 0x9F,
64380x81, 0x39, 0x57, 0xE9, 6438 0x81, 0x39, 0x57, 0xE9,
6439 6439
64400x2A, 0x49, 0x59, 0xBF, 6440 0x2A, 0x49, 0x59, 0xBF,
64410x1A, 0x49, 0x69, 0xBF, 6441 0x1A, 0x49, 0x69, 0xBF,
6442 6442
64430x30, 0x50, 0x2E, 0x9F, 6443 0x30, 0x50, 0x2E, 0x9F,
64440x82, 0x30, 0x57, 0xE9, 6444 0x82, 0x30, 0x57, 0xE9,
6445 6445
64460x38, 0x21, 0x2C, 0x9F, 6446 0x38, 0x21, 0x2C, 0x9F,
64470x83, 0x38, 0x57, 0xE9, 6447 0x83, 0x38, 0x57, 0xE9,
6448 6448
64490x31, 0x53, 0x2F, 0x9F, 6449 0x31, 0x53, 0x2F, 0x9F,
64500x84, 0x31, 0x5E, 0xE9, 6450 0x84, 0x31, 0x5E, 0xE9,
6451 6451
64520x39, 0xE5, 0x2C, 0x9F, 6452 0x39, 0xE5, 0x2C, 0x9F,
64530x85, 0x39, 0x5E, 0xE9, 6453 0x85, 0x39, 0x5E, 0xE9,
6454 6454
64550x86, 0x76, 0x57, 0xE9, 6455 0x86, 0x76, 0x57, 0xE9,
64560x8A, 0x36, 0x20, 0xE9, 6456 0x8A, 0x36, 0x20, 0xE9,
6457 6457
64580x87, 0x77, 0x57, 0xE9, 6458 0x87, 0x77, 0x57, 0xE9,
64590x8B, 0x3E, 0xBF, 0xEA, 6459 0x8B, 0x3E, 0xBF, 0xEA,
6460 6460
64610x80, 0x30, 0x57, 0xE9, 6461 0x80, 0x30, 0x57, 0xE9,
64620x81, 0x38, 0x57, 0xE9, 6462 0x81, 0x38, 0x57, 0xE9,
6463 6463
64640x82, 0x31, 0x57, 0xE9, 6464 0x82, 0x31, 0x57, 0xE9,
64650x86, 0x78, 0x57, 0xE9, 6465 0x86, 0x78, 0x57, 0xE9,
6466 6466
64670x83, 0x39, 0x57, 0xE9, 6467 0x83, 0x39, 0x57, 0xE9,
64680x87, 0x79, 0x57, 0xE9, 6468 0x87, 0x79, 0x57, 0xE9,
6469 6469
64700x30, 0x1F, 0x5F, 0xE9, 6470 0x30, 0x1F, 0x5F, 0xE9,
64710x8A, 0x34, 0x20, 0xE9, 6471 0x8A, 0x34, 0x20, 0xE9,
6472 6472
64730x8B, 0x3C, 0x20, 0xE9, 6473 0x8B, 0x3C, 0x20, 0xE9,
64740x37, 0x50, 0x60, 0xBD, 6474 0x37, 0x50, 0x60, 0xBD,
6475 6475
64760x57, 0x0D, 0x20, 0xE9, 6476 0x57, 0x0D, 0x20, 0xE9,
64770x35, 0x51, 0x61, 0xBD, 6477 0x35, 0x51, 0x61, 0xBD,
6478 6478
64790x2B, 0x50, 0x20, 0xE9, 6479 0x2B, 0x50, 0x20, 0xE9,
64800x1D, 0x37, 0xE1, 0xEA, 6480 0x1D, 0x37, 0xE1, 0xEA,
6481 6481
64820x1E, 0x35, 0xE1, 0xEA, 6482 0x1E, 0x35, 0xE1, 0xEA,
64830x00, 0xE0, 6483 0x00, 0xE0,
64840x0E, 0x77, 6484 0x0E, 0x77,
6485 6485
64860x24, 0x51, 0x20, 0xE9, 6486 0x24, 0x51, 0x20, 0xE9,
64870x9A, 0xFF, 0x20, 0xEA, 6487 0x9A, 0xFF, 0x20, 0xEA,
6488 6488
64890x16, 0x0E, 0x20, 0xE9, 6489 0x16, 0x0E, 0x20, 0xE9,
64900x57, 0x2E, 0xBF, 0xEA, 6490 0x57, 0x2E, 0xBF, 0xEA,
6491 6491
64920x0B, 0x46, 0xA0, 0xE8, 6492 0x0B, 0x46, 0xA0, 0xE8,
64930x1B, 0x56, 0xA0, 0xE8, 6493 0x1B, 0x56, 0xA0, 0xE8,
6494 6494
64950x2B, 0x66, 0xA0, 0xE8, 6495 0x2B, 0x66, 0xA0, 0xE8,
64960x0C, 0x47, 0xA0, 0xE8, 6496 0x0C, 0x47, 0xA0, 0xE8,
6497 6497
64980x1C, 0x57, 0xA0, 0xE8, 6498 0x1C, 0x57, 0xA0, 0xE8,
64990x2C, 0x67, 0xA0, 0xE8, 6499 0x2C, 0x67, 0xA0, 0xE8,
6500 6500
65010x0B, 0x00, 6501 0x0B, 0x00,
65020x1B, 0x00, 6502 0x1B, 0x00,
65030x2B, 0x00, 6503 0x2B, 0x00,
65040x00, 0xE0, 6504 0x00, 0xE0,
6505 6505
65060x0C, 0x00, 6506 0x0C, 0x00,
65070x1C, 0x00, 6507 0x1C, 0x00,
65080x2C, 0x00, 6508 0x2C, 0x00,
65090x00, 0xE0, 6509 0x00, 0xE0,
6510 6510
65110x0B, 0x65, 6511 0x0B, 0x65,
65120x1B, 0x65, 6512 0x1B, 0x65,
65130x2B, 0x65, 6513 0x2B, 0x65,
65140x00, 0xE0, 6514 0x00, 0xE0,
6515 6515
65160x0C, 0x65, 6516 0x0C, 0x65,
65170x1C, 0x65, 6517 0x1C, 0x65,
65180x2C, 0x65, 6518 0x2C, 0x65,
65190x00, 0xE0, 6519 0x00, 0xE0,
6520 6520
65210x0B, 0x1B, 0x60, 0xEC, 6521 0x0B, 0x1B, 0x60, 0xEC,
65220x36, 0xD7, 0x36, 0xAD, 6522 0x36, 0xD7, 0x36, 0xAD,
6523 6523
65240x2B, 0x80, 0x60, 0xEC, 6524 0x2B, 0x80, 0x60, 0xEC,
65250x0C, 0x1C, 0x60, 0xEC, 6525 0x0C, 0x1C, 0x60, 0xEC,
6526 6526
65270x3E, 0xD7, 0x3E, 0xAD, 6527 0x3E, 0xD7, 0x3E, 0xAD,
65280x2C, 0x80, 0x60, 0xEC, 6528 0x2C, 0x80, 0x60, 0xEC,
6529 6529
65300x0B, 0x2B, 0xDE, 0xE8, 6530 0x0B, 0x2B, 0xDE, 0xE8,
65310x1B, 0x80, 0xDE, 0xE8, 6531 0x1B, 0x80, 0xDE, 0xE8,
6532 6532
65330x36, 0x80, 0x36, 0xBD, 6533 0x36, 0x80, 0x36, 0xBD,
65340x3E, 0x80, 0x3E, 0xBD, 6534 0x3E, 0x80, 0x3E, 0xBD,
6535 6535
65360x33, 0xD7, 0x0B, 0xBD, 6536 0x33, 0xD7, 0x0B, 0xBD,
65370x3B, 0xD7, 0x1B, 0xBD, 6537 0x3B, 0xD7, 0x1B, 0xBD,
6538 6538
65390x46, 0x80, 0x46, 0xCF, 6539 0x46, 0x80, 0x46, 0xCF,
65400x57, 0x80, 0x57, 0xCF, 6540 0x57, 0x80, 0x57, 0xCF,
6541 6541
65420x66, 0x33, 0x66, 0xCF, 6542 0x66, 0x33, 0x66, 0xCF,
65430x47, 0x3B, 0x47, 0xCF, 6543 0x47, 0x3B, 0x47, 0xCF,
6544 6544
65450x56, 0x33, 0x56, 0xCF, 6545 0x56, 0x33, 0x56, 0xCF,
65460x67, 0x3B, 0x67, 0xCF, 6546 0x67, 0x3B, 0x67, 0xCF,
6547 6547
65480x0B, 0x48, 0xA0, 0xE8, 6548 0x0B, 0x48, 0xA0, 0xE8,
65490x1B, 0x58, 0xA0, 0xE8, 6549 0x1B, 0x58, 0xA0, 0xE8,
6550 6550
65510x2B, 0x68, 0xA0, 0xE8, 6551 0x2B, 0x68, 0xA0, 0xE8,
65520x0C, 0x49, 0xA0, 0xE8, 6552 0x0C, 0x49, 0xA0, 0xE8,
6553 6553
65540x1C, 0x59, 0xA0, 0xE8, 6554 0x1C, 0x59, 0xA0, 0xE8,
65550x2C, 0x69, 0xA0, 0xE8, 6555 0x2C, 0x69, 0xA0, 0xE8,
6556 6556
65570x0B, 0x00, 6557 0x0B, 0x00,
65580x1B, 0x00, 6558 0x1B, 0x00,
65590x2B, 0x00, 6559 0x2B, 0x00,
65600x00, 0xE0, 6560 0x00, 0xE0,
6561 6561
65620x0C, 0x00, 6562 0x0C, 0x00,
65630x1C, 0x00, 6563 0x1C, 0x00,
65640x2C, 0x00, 6564 0x2C, 0x00,
65650x00, 0xE0, 6565 0x00, 0xE0,
6566 6566
65670x0B, 0x65, 6567 0x0B, 0x65,
65680x1B, 0x65, 6568 0x1B, 0x65,
65690x2B, 0x65, 6569 0x2B, 0x65,
65700x00, 0xE0, 6570 0x00, 0xE0,
6571 6571
65720x0C, 0x65, 6572 0x0C, 0x65,
65730x1C, 0x65, 6573 0x1C, 0x65,
65740x2C, 0x65, 6574 0x2C, 0x65,
65750x00, 0xE0, 6575 0x00, 0xE0,
6576 6576
65770x0B, 0x1B, 0x60, 0xEC, 6577 0x0B, 0x1B, 0x60, 0xEC,
65780x34, 0xD7, 0x34, 0xAD, 6578 0x34, 0xD7, 0x34, 0xAD,
6579 6579
65800x2B, 0x80, 0x60, 0xEC, 6580 0x2B, 0x80, 0x60, 0xEC,
65810x0C, 0x1C, 0x60, 0xEC, 6581 0x0C, 0x1C, 0x60, 0xEC,
6582 6582
65830x3C, 0xD7, 0x3C, 0xAD, 6583 0x3C, 0xD7, 0x3C, 0xAD,
65840x2C, 0x80, 0x60, 0xEC, 6584 0x2C, 0x80, 0x60, 0xEC,
6585 6585
65860x0B, 0x2B, 0xDE, 0xE8, 6586 0x0B, 0x2B, 0xDE, 0xE8,
65870x1B, 0x80, 0xDE, 0xE8, 6587 0x1B, 0x80, 0xDE, 0xE8,
6588 6588
65890x34, 0x80, 0x34, 0xBD, 6589 0x34, 0x80, 0x34, 0xBD,
65900x3C, 0x80, 0x3C, 0xBD, 6590 0x3C, 0x80, 0x3C, 0xBD,
6591 6591
65920x33, 0xD7, 0x0B, 0xBD, 6592 0x33, 0xD7, 0x0B, 0xBD,
65930x3B, 0xD7, 0x1B, 0xBD, 6593 0x3B, 0xD7, 0x1B, 0xBD,
6594 6594
65950x48, 0x80, 0x48, 0xCF, 6595 0x48, 0x80, 0x48, 0xCF,
65960x59, 0x80, 0x59, 0xCF, 6596 0x59, 0x80, 0x59, 0xCF,
6597 6597
65980x68, 0x33, 0x68, 0xCF, 6598 0x68, 0x33, 0x68, 0xCF,
65990x49, 0x3B, 0x49, 0xCF, 6599 0x49, 0x3B, 0x49, 0xCF,
6600 6600
66010xBB, 0xFF, 0x20, 0xEA, 6601 0xBB, 0xFF, 0x20, 0xEA,
66020x00, 0x80, 0x00, 0xE8, 6602 0x00, 0x80, 0x00, 0xE8,
6603 6603
66040x58, 0x33, 0x58, 0xCF, 6604 0x58, 0x33, 0x58, 0xCF,
66050x69, 0x3B, 0x69, 0xCF, 6605 0x69, 0x3B, 0x69, 0xCF,
6606 6606
66070x78, 0xFF, 0x20, 0xEA, 6607 0x78, 0xFF, 0x20, 0xEA,
66080x57, 0xC0, 0xBF, 0xEA, 6608 0x57, 0xC0, 0xBF, 0xEA,
6609 6609
66100x00, 0x80, 0xA0, 0xE9, 6610 0x00, 0x80, 0xA0, 0xE9,
66110x00, 0x00, 0xD8, 0xEC, 6611 0x00, 0x00, 0xD8, 0xEC,
6612 6612
6613}; 6613};
6614 6614
6615static unsigned char warp_g400_t2gzs[] = { 6615static unsigned char warp_g400_t2gzs[] = {
6616 6616
66170x00, 0x8A, 0x98, 0xE9, 6617 0x00, 0x8A, 0x98, 0xE9,
66180x00, 0x80, 0x00, 0xE8, 6618 0x00, 0x80, 0x00, 0xE8,
6619 6619
66200x00, 0x80, 0xA0, 0xE9, 6620 0x00, 0x80, 0xA0, 0xE9,
66210x00, 0x00, 0xD8, 0xEC, 6621 0x00, 0x00, 0xD8, 0xEC,
6622 6622
66230xFF, 0x80, 0xC0, 0xE9, 6623 0xFF, 0x80, 0xC0, 0xE9,
66240x00, 0x80, 0x00, 0xE8, 6624 0x00, 0x80, 0x00, 0xE8,
6625 6625
66260x0A, 0x40, 0x50, 0xBF, 6626 0x0A, 0x40, 0x50, 0xBF,
66270x2A, 0x40, 0x60, 0xBF, 6627 0x2A, 0x40, 0x60, 0xBF,
6628 6628
66290x32, 0x41, 0x51, 0xBF, 6629 0x32, 0x41, 0x51, 0xBF,
66300x3A, 0x41, 0x61, 0xBF, 6630 0x3A, 0x41, 0x61, 0xBF,
6631 6631
66320xC3, 0x6B, 6632 0xC3, 0x6B,
66330xD3, 0x6B, 6633 0xD3, 0x6B,
66340x00, 0x8A, 0x98, 0xE9, 6634 0x00, 0x8A, 0x98, 0xE9,
6635 6635
66360x73, 0x7B, 0xC8, 0xEC, 6636 0x73, 0x7B, 0xC8, 0xEC,
66370x96, 0xE2, 6637 0x96, 0xE2,
66380x41, 0x04, 6638 0x41, 0x04,
6639 6639
66400x7B, 0x43, 0xA0, 0xE8, 6640 0x7B, 0x43, 0xA0, 0xE8,
66410x73, 0x53, 0xA0, 0xE8, 6641 0x73, 0x53, 0xA0, 0xE8,
6642 6642
66430xAD, 0xEE, 0x23, 0x9F, 6643 0xAD, 0xEE, 0x23, 0x9F,
66440x00, 0xE0, 6644 0x00, 0xE0,
66450x51, 0x04, 6645 0x51, 0x04,
6646 6646
66470x90, 0xE2, 6647 0x90, 0xE2,
66480x61, 0x04, 6648 0x61, 0x04,
66490x31, 0x46, 0xB1, 0xE8, 6649 0x31, 0x46, 0xB1, 0xE8,
6650 6650
66510x51, 0x41, 0xE0, 0xEC, 6651 0x51, 0x41, 0xE0, 0xEC,
66520x39, 0x67, 0xB1, 0xE8, 6652 0x39, 0x67, 0xB1, 0xE8,
6653 6653
66540x00, 0x04, 6654 0x00, 0x04,
66550x46, 0xE2, 6655 0x46, 0xE2,
66560x73, 0x63, 0xA0, 0xE8, 6656 0x73, 0x63, 0xA0, 0xE8,
6657 6657
66580x61, 0x41, 0xE0, 0xEC, 6658 0x61, 0x41, 0xE0, 0xEC,
66590x31, 0x00, 6659 0x31, 0x00,
66600x39, 0x00, 6660 0x39, 0x00,
6661 6661
66620x85, 0x80, 0x15, 0xEA, 6662 0x85, 0x80, 0x15, 0xEA,
66630x10, 0x04, 6663 0x10, 0x04,
66640x20, 0x04, 6664 0x20, 0x04,
6665 6665
66660x61, 0x51, 0xE0, 0xEC, 6666 0x61, 0x51, 0xE0, 0xEC,
66670x2F, 0x41, 0x60, 0xEA, 6667 0x2F, 0x41, 0x60, 0xEA,
6668 6668
66690x31, 0x20, 6669 0x31, 0x20,
66700x39, 0x20, 6670 0x39, 0x20,
66710x1F, 0x42, 0xA0, 0xE8, 6671 0x1F, 0x42, 0xA0, 0xE8,
6672 6672
66730x2A, 0x42, 0x52, 0xBF, 6673 0x2A, 0x42, 0x52, 0xBF,
66740x0F, 0x52, 0xA0, 0xE8, 6674 0x0F, 0x52, 0xA0, 0xE8,
6675 6675
66760x1A, 0x42, 0x62, 0xBF, 6676 0x1A, 0x42, 0x62, 0xBF,
66770x1E, 0x51, 0x60, 0xEA, 6677 0x1E, 0x51, 0x60, 0xEA,
6678 6678
66790x73, 0x7B, 0xC8, 0xEC, 6679 0x73, 0x7B, 0xC8, 0xEC,
66800x0E, 0x61, 0x60, 0xEA, 6680 0x0E, 0x61, 0x60, 0xEA,
6681 6681
66820x32, 0x40, 0x50, 0xBD, 6682 0x32, 0x40, 0x50, 0xBD,
66830x22, 0x40, 0x60, 0xBD, 6683 0x22, 0x40, 0x60, 0xBD,
6684 6684
66850x12, 0x41, 0x51, 0xBD, 6685 0x12, 0x41, 0x51, 0xBD,
66860x3A, 0x41, 0x61, 0xBD, 6686 0x3A, 0x41, 0x61, 0xBD,
6687 6687
66880xBF, 0x2F, 0x0E, 0xBD, 6688 0xBF, 0x2F, 0x0E, 0xBD,
66890x97, 0xE2, 6689 0x97, 0xE2,
66900x7B, 0x72, 6690 0x7B, 0x72,
6691 6691
66920x32, 0x20, 6692 0x32, 0x20,
66930x22, 0x20, 6693 0x22, 0x20,
66940x12, 0x20, 6694 0x12, 0x20,
66950x3A, 0x20, 6695 0x3A, 0x20,
6696 6696
66970x35, 0x48, 0xB1, 0xE8, 6697 0x35, 0x48, 0xB1, 0xE8,
66980x3D, 0x59, 0xB1, 0xE8, 6698 0x3D, 0x59, 0xB1, 0xE8,
6699 6699
67000x46, 0x31, 0x46, 0xBF, 6700 0x46, 0x31, 0x46, 0xBF,
67010x56, 0x31, 0x56, 0xBF, 6701 0x56, 0x31, 0x56, 0xBF,
6702 6702
67030xB3, 0xE2, 0x2D, 0x9F, 6703 0xB3, 0xE2, 0x2D, 0x9F,
67040x00, 0x80, 0x00, 0xE8, 6704 0x00, 0x80, 0x00, 0xE8,
6705 6705
67060x66, 0x31, 0x66, 0xBF, 6706 0x66, 0x31, 0x66, 0xBF,
67070x47, 0x39, 0x47, 0xBF, 6707 0x47, 0x39, 0x47, 0xBF,
6708 6708
67090x57, 0x39, 0x57, 0xBF, 6709 0x57, 0x39, 0x57, 0xBF,
67100x67, 0x39, 0x67, 0xBF, 6710 0x67, 0x39, 0x67, 0xBF,
6711 6711
67120x76, 0x80, 0x07, 0xEA, 6712 0x76, 0x80, 0x07, 0xEA,
67130x24, 0x41, 0x20, 0xE9, 6713 0x24, 0x41, 0x20, 0xE9,
6714 6714
67150x35, 0x00, 6715 0x35, 0x00,
67160x3D, 0x00, 6716 0x3D, 0x00,
67170x00, 0xE0, 6717 0x00, 0xE0,
67180x2D, 0x73, 6718 0x2D, 0x73,
6719 6719
67200x33, 0x72, 6720 0x33, 0x72,
67210x0C, 0xE3, 6721 0x0C, 0xE3,
67220x8D, 0x2F, 0x1E, 0xBD, 6722 0x8D, 0x2F, 0x1E, 0xBD,
6723 6723
67240x43, 0x75, 0xF8, 0xEC, 6724 0x43, 0x75, 0xF8, 0xEC,
67250x35, 0x20, 6725 0x35, 0x20,
67260x3D, 0x20, 6726 0x3D, 0x20,
6727 6727
67280x43, 0x43, 0x2D, 0xDF, 6728 0x43, 0x43, 0x2D, 0xDF,
67290x53, 0x53, 0x2D, 0xDF, 6729 0x53, 0x53, 0x2D, 0xDF,
6730 6730
67310xAE, 0x1E, 0x0E, 0xBD, 6731 0xAE, 0x1E, 0x0E, 0xBD,
67320x58, 0xE3, 6732 0x58, 0xE3,
67330x33, 0x66, 6733 0x33, 0x66,
6734 6734
67350x48, 0x35, 0x48, 0xBF, 6735 0x48, 0x35, 0x48, 0xBF,
67360x58, 0x35, 0x58, 0xBF, 6736 0x58, 0x35, 0x58, 0xBF,
6737 6737
67380x68, 0x35, 0x68, 0xBF, 6738 0x68, 0x35, 0x68, 0xBF,
67390x49, 0x3D, 0x49, 0xBF, 6739 0x49, 0x3D, 0x49, 0xBF,
6740 6740
67410x59, 0x3D, 0x59, 0xBF, 6741 0x59, 0x3D, 0x59, 0xBF,
67420x69, 0x3D, 0x69, 0xBF, 6742 0x69, 0x3D, 0x69, 0xBF,
6743 6743
67440x63, 0x63, 0x2D, 0xDF, 6744 0x63, 0x63, 0x2D, 0xDF,
67450x4D, 0x7D, 0xF8, 0xEC, 6745 0x4D, 0x7D, 0xF8, 0xEC,
6746 6746
67470x59, 0xE3, 6747 0x59, 0xE3,
67480x00, 0xE0, 6748 0x00, 0xE0,
67490xB8, 0x38, 0x33, 0xBF, 6749 0xB8, 0x38, 0x33, 0xBF,
6750 6750
67510x2D, 0x73, 6751 0x2D, 0x73,
67520x30, 0x76, 6752 0x30, 0x76,
67530x18, 0x3A, 0x41, 0xE9, 6753 0x18, 0x3A, 0x41, 0xE9,
6754 6754
67550x3F, 0x53, 0xA0, 0xE8, 6755 0x3F, 0x53, 0xA0, 0xE8,
67560x05, 0x80, 0x3D, 0xEA, 6756 0x05, 0x80, 0x3D, 0xEA,
6757 6757
67580x37, 0x43, 0xA0, 0xE8, 6758 0x37, 0x43, 0xA0, 0xE8,
67590x3D, 0x63, 0xA0, 0xE8, 6759 0x3D, 0x63, 0xA0, 0xE8,
6760 6760
67610x50, 0x70, 0xF8, 0xEC, 6761 0x50, 0x70, 0xF8, 0xEC,
67620x2B, 0x50, 0x3C, 0xE9, 6762 0x2B, 0x50, 0x3C, 0xE9,
6763 6763
67640x1F, 0x0F, 0xBC, 0xE8, 6764 0x1F, 0x0F, 0xBC, 0xE8,
67650x00, 0x80, 0x00, 0xE8, 6765 0x00, 0x80, 0x00, 0xE8,
6766 6766
67670x59, 0x78, 0xF8, 0xEC, 6767 0x59, 0x78, 0xF8, 0xEC,
67680x00, 0x80, 0x00, 0xE8, 6768 0x00, 0x80, 0x00, 0xE8,
6769 6769
67700x15, 0xC0, 0x20, 0xE9, 6770 0x15, 0xC0, 0x20, 0xE9,
67710x15, 0xC0, 0x20, 0xE9, 6771 0x15, 0xC0, 0x20, 0xE9,
6772 6772
67730x15, 0xC0, 0x20, 0xE9, 6773 0x15, 0xC0, 0x20, 0xE9,
67740x15, 0xC0, 0x20, 0xE9, 6774 0x15, 0xC0, 0x20, 0xE9,
6775 6775
67760x1E, 0x12, 0x41, 0xE9, 6776 0x1E, 0x12, 0x41, 0xE9,
67770x1A, 0x22, 0x41, 0xE9, 6777 0x1A, 0x22, 0x41, 0xE9,
6778 6778
67790x46, 0x37, 0x46, 0xDF, 6779 0x46, 0x37, 0x46, 0xDF,
67800x56, 0x3F, 0x56, 0xDF, 6780 0x56, 0x3F, 0x56, 0xDF,
6781 6781
67820x2B, 0x40, 0x3D, 0xE9, 6782 0x2B, 0x40, 0x3D, 0xE9,
67830x66, 0x3D, 0x66, 0xDF, 6783 0x66, 0x3D, 0x66, 0xDF,
6784 6784
67850x1D, 0x32, 0x41, 0xE9, 6785 0x1D, 0x32, 0x41, 0xE9,
67860x67, 0x3D, 0x67, 0xDF, 6786 0x67, 0x3D, 0x67, 0xDF,
6787 6787
67880x47, 0x37, 0x47, 0xDF, 6788 0x47, 0x37, 0x47, 0xDF,
67890x57, 0x3F, 0x57, 0xDF, 6789 0x57, 0x3F, 0x57, 0xDF,
6790 6790
67910x2A, 0x40, 0x20, 0xE9, 6791 0x2A, 0x40, 0x20, 0xE9,
67920x59, 0x3F, 0x59, 0xDF, 6792 0x59, 0x3F, 0x59, 0xDF,
6793 6793
67940x16, 0x30, 0x20, 0xE9, 6794 0x16, 0x30, 0x20, 0xE9,
67950x69, 0x3D, 0x69, 0xDF, 6795 0x69, 0x3D, 0x69, 0xDF,
6796 6796
67970x48, 0x37, 0x48, 0xDF, 6797 0x48, 0x37, 0x48, 0xDF,
67980x58, 0x3F, 0x58, 0xDF, 6798 0x58, 0x3F, 0x58, 0xDF,
6799 6799
68000x68, 0x3D, 0x68, 0xDF, 6800 0x68, 0x3D, 0x68, 0xDF,
68010x49, 0x37, 0x49, 0xDF, 6801 0x49, 0x37, 0x49, 0xDF,
6802 6802
68030x32, 0x32, 0x2D, 0xDF, 6803 0x32, 0x32, 0x2D, 0xDF,
68040x22, 0x22, 0x2D, 0xDF, 6804 0x22, 0x22, 0x2D, 0xDF,
6805 6805
68060x12, 0x12, 0x2D, 0xDF, 6806 0x12, 0x12, 0x2D, 0xDF,
68070x3A, 0x3A, 0x2D, 0xDF, 6807 0x3A, 0x3A, 0x2D, 0xDF,
6808 6808
68090x0F, 0xCF, 0x74, 0xC2, 6809 0x0F, 0xCF, 0x74, 0xC2,
68100x37, 0xCF, 0x74, 0xC4, 6810 0x37, 0xCF, 0x74, 0xC4,
6811 6811
68120x0A, 0x44, 0x54, 0xB0, 6812 0x0A, 0x44, 0x54, 0xB0,
68130x02, 0x44, 0x64, 0xB0, 6813 0x02, 0x44, 0x64, 0xB0,
6814 6814
68150x3D, 0xCF, 0x74, 0xC0, 6815 0x3D, 0xCF, 0x74, 0xC0,
68160x34, 0x37, 0x20, 0xE9, 6816 0x34, 0x37, 0x20, 0xE9,
6817 6817
68180x31, 0x53, 0x2F, 0x9F, 6818 0x31, 0x53, 0x2F, 0x9F,
68190x38, 0x0F, 0x20, 0xE9, 6819 0x38, 0x0F, 0x20, 0xE9,
6820 6820
68210x39, 0xE5, 0x2C, 0x9F, 6821 0x39, 0xE5, 0x2C, 0x9F,
68220x3C, 0x3D, 0x20, 0xE9, 6822 0x3C, 0x3D, 0x20, 0xE9,
6823 6823
68240x2A, 0x44, 0x54, 0xB2, 6824 0x2A, 0x44, 0x54, 0xB2,
68250x1A, 0x44, 0x64, 0xB2, 6825 0x1A, 0x44, 0x64, 0xB2,
6826 6826
68270x31, 0x80, 0x3A, 0xEA, 6827 0x31, 0x80, 0x3A, 0xEA,
68280x0A, 0x20, 6828 0x0A, 0x20,
68290x02, 0x20, 6829 0x02, 0x20,
6830 6830
68310x0F, 0xCF, 0x75, 0xC0, 6831 0x0F, 0xCF, 0x75, 0xC0,
68320x2A, 0x20, 6832 0x2A, 0x20,
68330x1A, 0x20, 6833 0x1A, 0x20,
6834 6834
68350x30, 0x50, 0x2E, 0x9F, 6835 0x30, 0x50, 0x2E, 0x9F,
68360x32, 0x31, 0x5F, 0xE9, 6836 0x32, 0x31, 0x5F, 0xE9,
6837 6837
68380x38, 0x21, 0x2C, 0x9F, 6838 0x38, 0x21, 0x2C, 0x9F,
68390x33, 0x39, 0x5F, 0xE9, 6839 0x33, 0x39, 0x5F, 0xE9,
6840 6840
68410x3D, 0xCF, 0x75, 0xC2, 6841 0x3D, 0xCF, 0x75, 0xC2,
68420x37, 0xCF, 0x75, 0xC4, 6842 0x37, 0xCF, 0x75, 0xC4,
6843 6843
68440x31, 0x53, 0x2F, 0x9F, 6844 0x31, 0x53, 0x2F, 0x9F,
68450xA6, 0x0F, 0x20, 0xE9, 6845 0xA6, 0x0F, 0x20, 0xE9,
6846 6846
68470x39, 0xE5, 0x2C, 0x9F, 6847 0x39, 0xE5, 0x2C, 0x9F,
68480xA3, 0x3D, 0x20, 0xE9, 6848 0xA3, 0x3D, 0x20, 0xE9,
6849 6849
68500x2A, 0x44, 0x54, 0xB4, 6850 0x2A, 0x44, 0x54, 0xB4,
68510x1A, 0x44, 0x64, 0xB4, 6851 0x1A, 0x44, 0x64, 0xB4,
6852 6852
68530x0A, 0x45, 0x55, 0xB0, 6853 0x0A, 0x45, 0x55, 0xB0,
68540x02, 0x45, 0x65, 0xB0, 6854 0x02, 0x45, 0x65, 0xB0,
6855 6855
68560x88, 0x73, 0x5E, 0xE9, 6856 0x88, 0x73, 0x5E, 0xE9,
68570x2A, 0x20, 6857 0x2A, 0x20,
68580x1A, 0x20, 6858 0x1A, 0x20,
6859 6859
68600xA0, 0x37, 0x20, 0xE9, 6860 0xA0, 0x37, 0x20, 0xE9,
68610x0A, 0x20, 6861 0x0A, 0x20,
68620x02, 0x20, 6862 0x02, 0x20,
6863 6863
68640x31, 0x53, 0x2F, 0x9F, 6864 0x31, 0x53, 0x2F, 0x9F,
68650x3E, 0x30, 0x4F, 0xE9, 6865 0x3E, 0x30, 0x4F, 0xE9,
6866 6866
68670x39, 0xE5, 0x2C, 0x9F, 6867 0x39, 0xE5, 0x2C, 0x9F,
68680x3F, 0x38, 0x4F, 0xE9, 6868 0x3F, 0x38, 0x4F, 0xE9,
6869 6869
68700x30, 0x50, 0x2E, 0x9F, 6870 0x30, 0x50, 0x2E, 0x9F,
68710x3A, 0x31, 0x4F, 0xE9, 6871 0x3A, 0x31, 0x4F, 0xE9,
6872 6872
68730x2A, 0x45, 0x55, 0xB2, 6873 0x2A, 0x45, 0x55, 0xB2,
68740x1A, 0x45, 0x65, 0xB2, 6874 0x1A, 0x45, 0x65, 0xB2,
6875 6875
68760x0A, 0x45, 0x55, 0xB4, 6876 0x0A, 0x45, 0x55, 0xB4,
68770x02, 0x45, 0x65, 0xB4, 6877 0x02, 0x45, 0x65, 0xB4,
6878 6878
68790x38, 0x21, 0x2C, 0x9F, 6879 0x38, 0x21, 0x2C, 0x9F,
68800x3B, 0x39, 0x4F, 0xE9, 6880 0x3B, 0x39, 0x4F, 0xE9,
6881 6881
68820x2A, 0x20, 6882 0x2A, 0x20,
68830x1A, 0x20, 6883 0x1A, 0x20,
68840x0A, 0x20, 6884 0x0A, 0x20,
68850x02, 0x20, 6885 0x02, 0x20,
6886 6886
68870x2A, 0x46, 0x56, 0xBF, 6887 0x2A, 0x46, 0x56, 0xBF,
68880x1A, 0x46, 0x66, 0xBF, 6888 0x1A, 0x46, 0x66, 0xBF,
6889 6889
68900x31, 0x53, 0x2F, 0x9F, 6890 0x31, 0x53, 0x2F, 0x9F,
68910x36, 0x31, 0x4F, 0xE9, 6891 0x36, 0x31, 0x4F, 0xE9,
6892 6892
68930x39, 0xE5, 0x2C, 0x9F, 6893 0x39, 0xE5, 0x2C, 0x9F,
68940x37, 0x39, 0x4F, 0xE9, 6894 0x37, 0x39, 0x4F, 0xE9,
6895 6895
68960x30, 0x50, 0x2E, 0x9F, 6896 0x30, 0x50, 0x2E, 0x9F,
68970xA7, 0x30, 0x4F, 0xE9, 6897 0xA7, 0x30, 0x4F, 0xE9,
6898 6898
68990x38, 0x21, 0x2C, 0x9F, 6899 0x38, 0x21, 0x2C, 0x9F,
69000xA8, 0x38, 0x4F, 0xE9, 6900 0xA8, 0x38, 0x4F, 0xE9,
6901 6901
69020x0A, 0x47, 0x57, 0xBF, 6902 0x0A, 0x47, 0x57, 0xBF,
69030x02, 0x47, 0x67, 0xBF, 6903 0x02, 0x47, 0x67, 0xBF,
6904 6904
69050x31, 0x53, 0x2F, 0x9F, 6905 0x31, 0x53, 0x2F, 0x9F,
69060xA4, 0x31, 0x4F, 0xE9, 6906 0xA4, 0x31, 0x4F, 0xE9,
6907 6907
69080x39, 0xE5, 0x2C, 0x9F, 6908 0x39, 0xE5, 0x2C, 0x9F,
69090xA5, 0x39, 0x4F, 0xE9, 6909 0xA5, 0x39, 0x4F, 0xE9,
6910 6910
69110x2A, 0x43, 0x53, 0xBF, 6911 0x2A, 0x43, 0x53, 0xBF,
69120x1A, 0x43, 0x63, 0xBF, 6912 0x1A, 0x43, 0x63, 0xBF,
6913 6913
69140x30, 0x50, 0x2E, 0x9F, 6914 0x30, 0x50, 0x2E, 0x9F,
69150xA1, 0x30, 0x4F, 0xE9, 6915 0xA1, 0x30, 0x4F, 0xE9,
6916 6916
69170x38, 0x21, 0x2C, 0x9F, 6917 0x38, 0x21, 0x2C, 0x9F,
69180xA2, 0x38, 0x4F, 0xE9, 6918 0xA2, 0x38, 0x4F, 0xE9,
6919 6919
69200x0A, 0x48, 0x58, 0xBF, 6920 0x0A, 0x48, 0x58, 0xBF,
69210x02, 0x48, 0x68, 0xBF, 6921 0x02, 0x48, 0x68, 0xBF,
6922 6922
69230x31, 0x53, 0x2F, 0x9F, 6923 0x31, 0x53, 0x2F, 0x9F,
69240x80, 0x31, 0x57, 0xE9, 6924 0x80, 0x31, 0x57, 0xE9,
6925 6925
69260x39, 0xE5, 0x2C, 0x9F, 6926 0x39, 0xE5, 0x2C, 0x9F,
69270x81, 0x39, 0x57, 0xE9, 6927 0x81, 0x39, 0x57, 0xE9,
6928 6928
69290x2A, 0x49, 0x59, 0xBF, 6929 0x2A, 0x49, 0x59, 0xBF,
69300x1A, 0x49, 0x69, 0xBF, 6930 0x1A, 0x49, 0x69, 0xBF,
6931 6931
69320x30, 0x50, 0x2E, 0x9F, 6932 0x30, 0x50, 0x2E, 0x9F,
69330x82, 0x30, 0x57, 0xE9, 6933 0x82, 0x30, 0x57, 0xE9,
6934 6934
69350x38, 0x21, 0x2C, 0x9F, 6935 0x38, 0x21, 0x2C, 0x9F,
69360x83, 0x38, 0x57, 0xE9, 6936 0x83, 0x38, 0x57, 0xE9,
6937 6937
69380x31, 0x53, 0x2F, 0x9F, 6938 0x31, 0x53, 0x2F, 0x9F,
69390x84, 0x31, 0x5E, 0xE9, 6939 0x84, 0x31, 0x5E, 0xE9,
6940 6940
69410x39, 0xE5, 0x2C, 0x9F, 6941 0x39, 0xE5, 0x2C, 0x9F,
69420x85, 0x39, 0x5E, 0xE9, 6942 0x85, 0x39, 0x5E, 0xE9,
6943 6943
69440x86, 0x76, 0x57, 0xE9, 6944 0x86, 0x76, 0x57, 0xE9,
69450x8A, 0x36, 0x20, 0xE9, 6945 0x8A, 0x36, 0x20, 0xE9,
6946 6946
69470x87, 0x77, 0x57, 0xE9, 6947 0x87, 0x77, 0x57, 0xE9,
69480x8B, 0x3E, 0xBF, 0xEA, 6948 0x8B, 0x3E, 0xBF, 0xEA,
6949 6949
69500x80, 0x30, 0x57, 0xE9, 6950 0x80, 0x30, 0x57, 0xE9,
69510x81, 0x38, 0x57, 0xE9, 6951 0x81, 0x38, 0x57, 0xE9,
6952 6952
69530x82, 0x31, 0x57, 0xE9, 6953 0x82, 0x31, 0x57, 0xE9,
69540x86, 0x78, 0x57, 0xE9, 6954 0x86, 0x78, 0x57, 0xE9,
6955 6955
69560x83, 0x39, 0x57, 0xE9, 6956 0x83, 0x39, 0x57, 0xE9,
69570x87, 0x79, 0x57, 0xE9, 6957 0x87, 0x79, 0x57, 0xE9,
6958 6958
69590x30, 0x1F, 0x5F, 0xE9, 6959 0x30, 0x1F, 0x5F, 0xE9,
69600x8A, 0x34, 0x20, 0xE9, 6960 0x8A, 0x34, 0x20, 0xE9,
6961 6961
69620x8B, 0x3C, 0x20, 0xE9, 6962 0x8B, 0x3C, 0x20, 0xE9,
69630x37, 0x50, 0x60, 0xBD, 6963 0x37, 0x50, 0x60, 0xBD,
6964 6964
69650x57, 0x0D, 0x20, 0xE9, 6965 0x57, 0x0D, 0x20, 0xE9,
69660x35, 0x51, 0x61, 0xBD, 6966 0x35, 0x51, 0x61, 0xBD,
6967 6967
69680x2B, 0x50, 0x20, 0xE9, 6968 0x2B, 0x50, 0x20, 0xE9,
69690x1D, 0x37, 0xE1, 0xEA, 6969 0x1D, 0x37, 0xE1, 0xEA,
6970 6970
69710x1E, 0x35, 0xE1, 0xEA, 6971 0x1E, 0x35, 0xE1, 0xEA,
69720x00, 0xE0, 6972 0x00, 0xE0,
69730x0E, 0x77, 6973 0x0E, 0x77,
6974 6974
69750x24, 0x51, 0x20, 0xE9, 6975 0x24, 0x51, 0x20, 0xE9,
69760x92, 0xFF, 0x20, 0xEA, 6976 0x92, 0xFF, 0x20, 0xEA,
6977 6977
69780x16, 0x0E, 0x20, 0xE9, 6978 0x16, 0x0E, 0x20, 0xE9,
69790x57, 0x2E, 0xBF, 0xEA, 6979 0x57, 0x2E, 0xBF, 0xEA,
6980 6980
69810x0B, 0x46, 0xA0, 0xE8, 6981 0x0B, 0x46, 0xA0, 0xE8,
69820x1B, 0x56, 0xA0, 0xE8, 6982 0x1B, 0x56, 0xA0, 0xE8,
6983 6983
69840x2B, 0x66, 0xA0, 0xE8, 6984 0x2B, 0x66, 0xA0, 0xE8,
69850x0C, 0x47, 0xA0, 0xE8, 6985 0x0C, 0x47, 0xA0, 0xE8,
6986 6986
69870x1C, 0x57, 0xA0, 0xE8, 6987 0x1C, 0x57, 0xA0, 0xE8,
69880x2C, 0x67, 0xA0, 0xE8, 6988 0x2C, 0x67, 0xA0, 0xE8,
6989 6989
69900x0B, 0x00, 6990 0x0B, 0x00,
69910x1B, 0x00, 6991 0x1B, 0x00,
69920x2B, 0x00, 6992 0x2B, 0x00,
69930x00, 0xE0, 6993 0x00, 0xE0,
6994 6994
69950x0C, 0x00, 6995 0x0C, 0x00,
69960x1C, 0x00, 6996 0x1C, 0x00,
69970x2C, 0x00, 6997 0x2C, 0x00,
69980x00, 0xE0, 6998 0x00, 0xE0,
6999 6999
70000x0B, 0x65, 7000 0x0B, 0x65,
70010x1B, 0x65, 7001 0x1B, 0x65,
70020x2B, 0x65, 7002 0x2B, 0x65,
70030x00, 0xE0, 7003 0x00, 0xE0,
7004 7004
70050x0C, 0x65, 7005 0x0C, 0x65,
70060x1C, 0x65, 7006 0x1C, 0x65,
70070x2C, 0x65, 7007 0x2C, 0x65,
70080x00, 0xE0, 7008 0x00, 0xE0,
7009 7009
70100x0B, 0x1B, 0x60, 0xEC, 7010 0x0B, 0x1B, 0x60, 0xEC,
70110x36, 0xD7, 0x36, 0xAD, 7011 0x36, 0xD7, 0x36, 0xAD,
7012 7012
70130x2B, 0x80, 0x60, 0xEC, 7013 0x2B, 0x80, 0x60, 0xEC,
70140x0C, 0x1C, 0x60, 0xEC, 7014 0x0C, 0x1C, 0x60, 0xEC,
7015 7015
70160x3E, 0xD7, 0x3E, 0xAD, 7016 0x3E, 0xD7, 0x3E, 0xAD,
70170x2C, 0x80, 0x60, 0xEC, 7017 0x2C, 0x80, 0x60, 0xEC,
7018 7018
70190x0B, 0x2B, 0xDE, 0xE8, 7019 0x0B, 0x2B, 0xDE, 0xE8,
70200x1B, 0x80, 0xDE, 0xE8, 7020 0x1B, 0x80, 0xDE, 0xE8,
7021 7021
70220x36, 0x80, 0x36, 0xBD, 7022 0x36, 0x80, 0x36, 0xBD,
70230x3E, 0x80, 0x3E, 0xBD, 7023 0x3E, 0x80, 0x3E, 0xBD,
7024 7024
70250x33, 0xD7, 0x0B, 0xBD, 7025 0x33, 0xD7, 0x0B, 0xBD,
70260x3B, 0xD7, 0x1B, 0xBD, 7026 0x3B, 0xD7, 0x1B, 0xBD,
7027 7027
70280x46, 0x80, 0x46, 0xCF, 7028 0x46, 0x80, 0x46, 0xCF,
70290x57, 0x80, 0x57, 0xCF, 7029 0x57, 0x80, 0x57, 0xCF,
7030 7030
70310x66, 0x33, 0x66, 0xCF, 7031 0x66, 0x33, 0x66, 0xCF,
70320x47, 0x3B, 0x47, 0xCF, 7032 0x47, 0x3B, 0x47, 0xCF,
7033 7033
70340x56, 0x33, 0x56, 0xCF, 7034 0x56, 0x33, 0x56, 0xCF,
70350x67, 0x3B, 0x67, 0xCF, 7035 0x67, 0x3B, 0x67, 0xCF,
7036 7036
70370x0B, 0x48, 0xA0, 0xE8, 7037 0x0B, 0x48, 0xA0, 0xE8,
70380x1B, 0x58, 0xA0, 0xE8, 7038 0x1B, 0x58, 0xA0, 0xE8,
7039 7039
70400x2B, 0x68, 0xA0, 0xE8, 7040 0x2B, 0x68, 0xA0, 0xE8,
70410x0C, 0x49, 0xA0, 0xE8, 7041 0x0C, 0x49, 0xA0, 0xE8,
7042 7042
70430x1C, 0x59, 0xA0, 0xE8, 7043 0x1C, 0x59, 0xA0, 0xE8,
70440x2C, 0x69, 0xA0, 0xE8, 7044 0x2C, 0x69, 0xA0, 0xE8,
7045 7045
70460x0B, 0x00, 7046 0x0B, 0x00,
70470x1B, 0x00, 7047 0x1B, 0x00,
70480x2B, 0x00, 7048 0x2B, 0x00,
70490x00, 0xE0, 7049 0x00, 0xE0,
7050 7050
70510x0C, 0x00, 7051 0x0C, 0x00,
70520x1C, 0x00, 7052 0x1C, 0x00,
70530x2C, 0x00, 7053 0x2C, 0x00,
70540x00, 0xE0, 7054 0x00, 0xE0,
7055 7055
70560x0B, 0x65, 7056 0x0B, 0x65,
70570x1B, 0x65, 7057 0x1B, 0x65,
70580x2B, 0x65, 7058 0x2B, 0x65,
70590x00, 0xE0, 7059 0x00, 0xE0,
7060 7060
70610x0C, 0x65, 7061 0x0C, 0x65,
70620x1C, 0x65, 7062 0x1C, 0x65,
70630x2C, 0x65, 7063 0x2C, 0x65,
70640x00, 0xE0, 7064 0x00, 0xE0,
7065 7065
70660x0B, 0x1B, 0x60, 0xEC, 7066 0x0B, 0x1B, 0x60, 0xEC,
70670x34, 0xD7, 0x34, 0xAD, 7067 0x34, 0xD7, 0x34, 0xAD,
7068 7068
70690x2B, 0x80, 0x60, 0xEC, 7069 0x2B, 0x80, 0x60, 0xEC,
70700x0C, 0x1C, 0x60, 0xEC, 7070 0x0C, 0x1C, 0x60, 0xEC,
7071 7071
70720x3C, 0xD7, 0x3C, 0xAD, 7072 0x3C, 0xD7, 0x3C, 0xAD,
70730x2C, 0x80, 0x60, 0xEC, 7073 0x2C, 0x80, 0x60, 0xEC,
7074 7074
70750x0B, 0x2B, 0xDE, 0xE8, 7075 0x0B, 0x2B, 0xDE, 0xE8,
70760x1B, 0x80, 0xDE, 0xE8, 7076 0x1B, 0x80, 0xDE, 0xE8,
7077 7077
70780x34, 0x80, 0x34, 0xBD, 7078 0x34, 0x80, 0x34, 0xBD,
70790x3C, 0x80, 0x3C, 0xBD, 7079 0x3C, 0x80, 0x3C, 0xBD,
7080 7080
70810x33, 0xD7, 0x0B, 0xBD, 7081 0x33, 0xD7, 0x0B, 0xBD,
70820x3B, 0xD7, 0x1B, 0xBD, 7082 0x3B, 0xD7, 0x1B, 0xBD,
7083 7083
70840x48, 0x80, 0x48, 0xCF, 7084 0x48, 0x80, 0x48, 0xCF,
70850x59, 0x80, 0x59, 0xCF, 7085 0x59, 0x80, 0x59, 0xCF,
7086 7086
70870x68, 0x33, 0x68, 0xCF, 7087 0x68, 0x33, 0x68, 0xCF,
70880x49, 0x3B, 0x49, 0xCF, 7088 0x49, 0x3B, 0x49, 0xCF,
7089 7089
70900xB2, 0xFF, 0x20, 0xEA, 7090 0xB2, 0xFF, 0x20, 0xEA,
70910x00, 0x80, 0x00, 0xE8, 7091 0x00, 0x80, 0x00, 0xE8,
7092 7092
70930x58, 0x33, 0x58, 0xCF, 7093 0x58, 0x33, 0x58, 0xCF,
70940x69, 0x3B, 0x69, 0xCF, 7094 0x69, 0x3B, 0x69, 0xCF,
7095 7095
70960x70, 0xFF, 0x20, 0xEA, 7096 0x70, 0xFF, 0x20, 0xEA,
70970x57, 0xC0, 0xBF, 0xEA, 7097 0x57, 0xC0, 0xBF, 0xEA,
7098 7098
70990x00, 0x80, 0xA0, 0xE9, 7099 0x00, 0x80, 0xA0, 0xE9,
71000x00, 0x00, 0xD8, 0xEC, 7100 0x00, 0x00, 0xD8, 0xEC,
7101 7101
7102}; 7102};
7103 7103
7104static unsigned char warp_g400_t2gzsa[] = { 7104static unsigned char warp_g400_t2gzsa[] = {
7105 7105
71060x00, 0x8A, 0x98, 0xE9, 7106 0x00, 0x8A, 0x98, 0xE9,
71070x00, 0x80, 0x00, 0xE8, 7107 0x00, 0x80, 0x00, 0xE8,
7108 7108
71090x00, 0x80, 0xA0, 0xE9, 7109 0x00, 0x80, 0xA0, 0xE9,
71100x00, 0x00, 0xD8, 0xEC, 7110 0x00, 0x00, 0xD8, 0xEC,
7111 7111
71120xFF, 0x80, 0xC0, 0xE9, 7112 0xFF, 0x80, 0xC0, 0xE9,
71130x00, 0x80, 0x00, 0xE8, 7113 0x00, 0x80, 0x00, 0xE8,
7114 7114
71150x0A, 0x40, 0x50, 0xBF, 7115 0x0A, 0x40, 0x50, 0xBF,
71160x2A, 0x40, 0x60, 0xBF, 7116 0x2A, 0x40, 0x60, 0xBF,
7117 7117
71180x32, 0x41, 0x51, 0xBF, 7118 0x32, 0x41, 0x51, 0xBF,
71190x3A, 0x41, 0x61, 0xBF, 7119 0x3A, 0x41, 0x61, 0xBF,
7120 7120
71210xC3, 0x6B, 7121 0xC3, 0x6B,
71220xD3, 0x6B, 7122 0xD3, 0x6B,
71230x00, 0x8A, 0x98, 0xE9, 7123 0x00, 0x8A, 0x98, 0xE9,
7124 7124
71250x73, 0x7B, 0xC8, 0xEC, 7125 0x73, 0x7B, 0xC8, 0xEC,
71260x96, 0xE2, 7126 0x96, 0xE2,
71270x41, 0x04, 7127 0x41, 0x04,
7128 7128
71290x7B, 0x43, 0xA0, 0xE8, 7129 0x7B, 0x43, 0xA0, 0xE8,
71300x73, 0x53, 0xA0, 0xE8, 7130 0x73, 0x53, 0xA0, 0xE8,
7131 7131
71320xAD, 0xEE, 0x23, 0x9F, 7132 0xAD, 0xEE, 0x23, 0x9F,
71330x00, 0xE0, 7133 0x00, 0xE0,
71340x51, 0x04, 7134 0x51, 0x04,
7135 7135
71360x90, 0xE2, 7136 0x90, 0xE2,
71370x61, 0x04, 7137 0x61, 0x04,
71380x31, 0x46, 0xB1, 0xE8, 7138 0x31, 0x46, 0xB1, 0xE8,
7139 7139
71400x51, 0x41, 0xE0, 0xEC, 7140 0x51, 0x41, 0xE0, 0xEC,
71410x39, 0x67, 0xB1, 0xE8, 7141 0x39, 0x67, 0xB1, 0xE8,
7142 7142
71430x00, 0x04, 7143 0x00, 0x04,
71440x46, 0xE2, 7144 0x46, 0xE2,
71450x73, 0x63, 0xA0, 0xE8, 7145 0x73, 0x63, 0xA0, 0xE8,
7146 7146
71470x61, 0x41, 0xE0, 0xEC, 7147 0x61, 0x41, 0xE0, 0xEC,
71480x31, 0x00, 7148 0x31, 0x00,
71490x39, 0x00, 7149 0x39, 0x00,
7150 7150
71510x8A, 0x80, 0x15, 0xEA, 7151 0x8A, 0x80, 0x15, 0xEA,
71520x10, 0x04, 7152 0x10, 0x04,
71530x20, 0x04, 7153 0x20, 0x04,
7154 7154
71550x61, 0x51, 0xE0, 0xEC, 7155 0x61, 0x51, 0xE0, 0xEC,
71560x2F, 0x41, 0x60, 0xEA, 7156 0x2F, 0x41, 0x60, 0xEA,
7157 7157
71580x31, 0x20, 7158 0x31, 0x20,
71590x39, 0x20, 7159 0x39, 0x20,
71600x1F, 0x42, 0xA0, 0xE8, 7160 0x1F, 0x42, 0xA0, 0xE8,
7161 7161
71620x2A, 0x42, 0x52, 0xBF, 7162 0x2A, 0x42, 0x52, 0xBF,
71630x0F, 0x52, 0xA0, 0xE8, 7163 0x0F, 0x52, 0xA0, 0xE8,
7164 7164
71650x1A, 0x42, 0x62, 0xBF, 7165 0x1A, 0x42, 0x62, 0xBF,
71660x1E, 0x51, 0x60, 0xEA, 7166 0x1E, 0x51, 0x60, 0xEA,
7167 7167
71680x73, 0x7B, 0xC8, 0xEC, 7168 0x73, 0x7B, 0xC8, 0xEC,
71690x0E, 0x61, 0x60, 0xEA, 7169 0x0E, 0x61, 0x60, 0xEA,
7170 7170
71710x32, 0x40, 0x50, 0xBD, 7171 0x32, 0x40, 0x50, 0xBD,
71720x22, 0x40, 0x60, 0xBD, 7172 0x22, 0x40, 0x60, 0xBD,
7173 7173
71740x12, 0x41, 0x51, 0xBD, 7174 0x12, 0x41, 0x51, 0xBD,
71750x3A, 0x41, 0x61, 0xBD, 7175 0x3A, 0x41, 0x61, 0xBD,
7176 7176
71770xBF, 0x2F, 0x0E, 0xBD, 7177 0xBF, 0x2F, 0x0E, 0xBD,
71780x97, 0xE2, 7178 0x97, 0xE2,
71790x7B, 0x72, 7179 0x7B, 0x72,
7180 7180
71810x32, 0x20, 7181 0x32, 0x20,
71820x22, 0x20, 7182 0x22, 0x20,
71830x12, 0x20, 7183 0x12, 0x20,
71840x3A, 0x20, 7184 0x3A, 0x20,
7185 7185
71860x35, 0x48, 0xB1, 0xE8, 7186 0x35, 0x48, 0xB1, 0xE8,
71870x3D, 0x59, 0xB1, 0xE8, 7187 0x3D, 0x59, 0xB1, 0xE8,
7188 7188
71890x46, 0x31, 0x46, 0xBF, 7189 0x46, 0x31, 0x46, 0xBF,
71900x56, 0x31, 0x56, 0xBF, 7190 0x56, 0x31, 0x56, 0xBF,
7191 7191
71920xB3, 0xE2, 0x2D, 0x9F, 7192 0xB3, 0xE2, 0x2D, 0x9F,
71930x00, 0x80, 0x00, 0xE8, 7193 0x00, 0x80, 0x00, 0xE8,
7194 7194
71950x66, 0x31, 0x66, 0xBF, 7195 0x66, 0x31, 0x66, 0xBF,
71960x47, 0x39, 0x47, 0xBF, 7196 0x47, 0x39, 0x47, 0xBF,
7197 7197
71980x57, 0x39, 0x57, 0xBF, 7198 0x57, 0x39, 0x57, 0xBF,
71990x67, 0x39, 0x67, 0xBF, 7199 0x67, 0x39, 0x67, 0xBF,
7200 7200
72010x7B, 0x80, 0x07, 0xEA, 7201 0x7B, 0x80, 0x07, 0xEA,
72020x24, 0x41, 0x20, 0xE9, 7202 0x24, 0x41, 0x20, 0xE9,
7203 7203
72040x35, 0x00, 7204 0x35, 0x00,
72050x3D, 0x00, 7205 0x3D, 0x00,
72060x00, 0xE0, 7206 0x00, 0xE0,
72070x2D, 0x73, 7207 0x2D, 0x73,
7208 7208
72090x33, 0x72, 7209 0x33, 0x72,
72100x0C, 0xE3, 7210 0x0C, 0xE3,
72110x8D, 0x2F, 0x1E, 0xBD, 7211 0x8D, 0x2F, 0x1E, 0xBD,
7212 7212
72130x43, 0x75, 0xF8, 0xEC, 7213 0x43, 0x75, 0xF8, 0xEC,
72140x35, 0x20, 7214 0x35, 0x20,
72150x3D, 0x20, 7215 0x3D, 0x20,
7216 7216
72170x43, 0x43, 0x2D, 0xDF, 7217 0x43, 0x43, 0x2D, 0xDF,
72180x53, 0x53, 0x2D, 0xDF, 7218 0x53, 0x53, 0x2D, 0xDF,
7219 7219
72200xAE, 0x1E, 0x0E, 0xBD, 7220 0xAE, 0x1E, 0x0E, 0xBD,
72210x58, 0xE3, 7221 0x58, 0xE3,
72220x33, 0x66, 7222 0x33, 0x66,
7223 7223
72240x48, 0x35, 0x48, 0xBF, 7224 0x48, 0x35, 0x48, 0xBF,
72250x58, 0x35, 0x58, 0xBF, 7225 0x58, 0x35, 0x58, 0xBF,
7226 7226
72270x68, 0x35, 0x68, 0xBF, 7227 0x68, 0x35, 0x68, 0xBF,
72280x49, 0x3D, 0x49, 0xBF, 7228 0x49, 0x3D, 0x49, 0xBF,
7229 7229
72300x59, 0x3D, 0x59, 0xBF, 7230 0x59, 0x3D, 0x59, 0xBF,
72310x69, 0x3D, 0x69, 0xBF, 7231 0x69, 0x3D, 0x69, 0xBF,
7232 7232
72330x63, 0x63, 0x2D, 0xDF, 7233 0x63, 0x63, 0x2D, 0xDF,
72340x4D, 0x7D, 0xF8, 0xEC, 7234 0x4D, 0x7D, 0xF8, 0xEC,
7235 7235
72360x59, 0xE3, 7236 0x59, 0xE3,
72370x00, 0xE0, 7237 0x00, 0xE0,
72380xB8, 0x38, 0x33, 0xBF, 7238 0xB8, 0x38, 0x33, 0xBF,
7239 7239
72400x2D, 0x73, 7240 0x2D, 0x73,
72410x30, 0x76, 7241 0x30, 0x76,
72420x18, 0x3A, 0x41, 0xE9, 7242 0x18, 0x3A, 0x41, 0xE9,
7243 7243
72440x3F, 0x53, 0xA0, 0xE8, 7244 0x3F, 0x53, 0xA0, 0xE8,
72450x05, 0x80, 0x3D, 0xEA, 7245 0x05, 0x80, 0x3D, 0xEA,
7246 7246
72470x37, 0x43, 0xA0, 0xE8, 7247 0x37, 0x43, 0xA0, 0xE8,
72480x3D, 0x63, 0xA0, 0xE8, 7248 0x3D, 0x63, 0xA0, 0xE8,
7249 7249
72500x50, 0x70, 0xF8, 0xEC, 7250 0x50, 0x70, 0xF8, 0xEC,
72510x2B, 0x50, 0x3C, 0xE9, 7251 0x2B, 0x50, 0x3C, 0xE9,
7252 7252
72530x1F, 0x0F, 0xBC, 0xE8, 7253 0x1F, 0x0F, 0xBC, 0xE8,
72540x00, 0x80, 0x00, 0xE8, 7254 0x00, 0x80, 0x00, 0xE8,
7255 7255
72560x59, 0x78, 0xF8, 0xEC, 7256 0x59, 0x78, 0xF8, 0xEC,
72570x00, 0x80, 0x00, 0xE8, 7257 0x00, 0x80, 0x00, 0xE8,
7258 7258
72590x15, 0xC0, 0x20, 0xE9, 7259 0x15, 0xC0, 0x20, 0xE9,
72600x15, 0xC0, 0x20, 0xE9, 7260 0x15, 0xC0, 0x20, 0xE9,
7261 7261
72620x15, 0xC0, 0x20, 0xE9, 7262 0x15, 0xC0, 0x20, 0xE9,
72630x15, 0xC0, 0x20, 0xE9, 7263 0x15, 0xC0, 0x20, 0xE9,
7264 7264
72650x1E, 0x12, 0x41, 0xE9, 7265 0x1E, 0x12, 0x41, 0xE9,
72660x1A, 0x22, 0x41, 0xE9, 7266 0x1A, 0x22, 0x41, 0xE9,
7267 7267
72680x46, 0x37, 0x46, 0xDF, 7268 0x46, 0x37, 0x46, 0xDF,
72690x56, 0x3F, 0x56, 0xDF, 7269 0x56, 0x3F, 0x56, 0xDF,
7270 7270
72710x2B, 0x40, 0x3D, 0xE9, 7271 0x2B, 0x40, 0x3D, 0xE9,
72720x66, 0x3D, 0x66, 0xDF, 7272 0x66, 0x3D, 0x66, 0xDF,
7273 7273
72740x1D, 0x32, 0x41, 0xE9, 7274 0x1D, 0x32, 0x41, 0xE9,
72750x67, 0x3D, 0x67, 0xDF, 7275 0x67, 0x3D, 0x67, 0xDF,
7276 7276
72770x47, 0x37, 0x47, 0xDF, 7277 0x47, 0x37, 0x47, 0xDF,
72780x57, 0x3F, 0x57, 0xDF, 7278 0x57, 0x3F, 0x57, 0xDF,
7279 7279
72800x2A, 0x40, 0x20, 0xE9, 7280 0x2A, 0x40, 0x20, 0xE9,
72810x59, 0x3F, 0x59, 0xDF, 7281 0x59, 0x3F, 0x59, 0xDF,
7282 7282
72830x16, 0x30, 0x20, 0xE9, 7283 0x16, 0x30, 0x20, 0xE9,
72840x69, 0x3D, 0x69, 0xDF, 7284 0x69, 0x3D, 0x69, 0xDF,
7285 7285
72860x48, 0x37, 0x48, 0xDF, 7286 0x48, 0x37, 0x48, 0xDF,
72870x58, 0x3F, 0x58, 0xDF, 7287 0x58, 0x3F, 0x58, 0xDF,
7288 7288
72890x68, 0x3D, 0x68, 0xDF, 7289 0x68, 0x3D, 0x68, 0xDF,
72900x49, 0x37, 0x49, 0xDF, 7290 0x49, 0x37, 0x49, 0xDF,
7291 7291
72920x32, 0x32, 0x2D, 0xDF, 7292 0x32, 0x32, 0x2D, 0xDF,
72930x22, 0x22, 0x2D, 0xDF, 7293 0x22, 0x22, 0x2D, 0xDF,
7294 7294
72950x12, 0x12, 0x2D, 0xDF, 7295 0x12, 0x12, 0x2D, 0xDF,
72960x3A, 0x3A, 0x2D, 0xDF, 7296 0x3A, 0x3A, 0x2D, 0xDF,
7297 7297
72980x0F, 0xCF, 0x74, 0xC2, 7298 0x0F, 0xCF, 0x74, 0xC2,
72990x37, 0xCF, 0x74, 0xC4, 7299 0x37, 0xCF, 0x74, 0xC4,
7300 7300
73010x0A, 0x44, 0x54, 0xB0, 7301 0x0A, 0x44, 0x54, 0xB0,
73020x02, 0x44, 0x64, 0xB0, 7302 0x02, 0x44, 0x64, 0xB0,
7303 7303
73040x3D, 0xCF, 0x74, 0xC0, 7304 0x3D, 0xCF, 0x74, 0xC0,
73050x34, 0x37, 0x20, 0xE9, 7305 0x34, 0x37, 0x20, 0xE9,
7306 7306
73070x31, 0x53, 0x2F, 0x9F, 7307 0x31, 0x53, 0x2F, 0x9F,
73080x38, 0x0F, 0x20, 0xE9, 7308 0x38, 0x0F, 0x20, 0xE9,
7309 7309
73100x39, 0xE5, 0x2C, 0x9F, 7310 0x39, 0xE5, 0x2C, 0x9F,
73110x3C, 0x3D, 0x20, 0xE9, 7311 0x3C, 0x3D, 0x20, 0xE9,
7312 7312
73130x2A, 0x44, 0x54, 0xB2, 7313 0x2A, 0x44, 0x54, 0xB2,
73140x1A, 0x44, 0x64, 0xB2, 7314 0x1A, 0x44, 0x64, 0xB2,
7315 7315
73160x36, 0x80, 0x3A, 0xEA, 7316 0x36, 0x80, 0x3A, 0xEA,
73170x0A, 0x20, 7317 0x0A, 0x20,
73180x02, 0x20, 7318 0x02, 0x20,
7319 7319
73200x0F, 0xCF, 0x75, 0xC0, 7320 0x0F, 0xCF, 0x75, 0xC0,
73210x2A, 0x20, 7321 0x2A, 0x20,
73220x1A, 0x20, 7322 0x1A, 0x20,
7323 7323
73240x30, 0x50, 0x2E, 0x9F, 7324 0x30, 0x50, 0x2E, 0x9F,
73250x32, 0x31, 0x5F, 0xE9, 7325 0x32, 0x31, 0x5F, 0xE9,
7326 7326
73270x38, 0x21, 0x2C, 0x9F, 7327 0x38, 0x21, 0x2C, 0x9F,
73280x33, 0x39, 0x5F, 0xE9, 7328 0x33, 0x39, 0x5F, 0xE9,
7329 7329
73300x3D, 0xCF, 0x75, 0xC2, 7330 0x3D, 0xCF, 0x75, 0xC2,
73310x37, 0xCF, 0x75, 0xC4, 7331 0x37, 0xCF, 0x75, 0xC4,
7332 7332
73330x31, 0x53, 0x2F, 0x9F, 7333 0x31, 0x53, 0x2F, 0x9F,
73340xA6, 0x0F, 0x20, 0xE9, 7334 0xA6, 0x0F, 0x20, 0xE9,
7335 7335
73360x39, 0xE5, 0x2C, 0x9F, 7336 0x39, 0xE5, 0x2C, 0x9F,
73370xA3, 0x3D, 0x20, 0xE9, 7337 0xA3, 0x3D, 0x20, 0xE9,
7338 7338
73390x2A, 0x44, 0x54, 0xB4, 7339 0x2A, 0x44, 0x54, 0xB4,
73400x1A, 0x44, 0x64, 0xB4, 7340 0x1A, 0x44, 0x64, 0xB4,
7341 7341
73420x0A, 0x45, 0x55, 0xB0, 7342 0x0A, 0x45, 0x55, 0xB0,
73430x02, 0x45, 0x65, 0xB0, 7343 0x02, 0x45, 0x65, 0xB0,
7344 7344
73450x88, 0x73, 0x5E, 0xE9, 7345 0x88, 0x73, 0x5E, 0xE9,
73460x2A, 0x20, 7346 0x2A, 0x20,
73470x1A, 0x20, 7347 0x1A, 0x20,
7348 7348
73490xA0, 0x37, 0x20, 0xE9, 7349 0xA0, 0x37, 0x20, 0xE9,
73500x0A, 0x20, 7350 0x0A, 0x20,
73510x02, 0x20, 7351 0x02, 0x20,
7352 7352
73530x31, 0x53, 0x2F, 0x9F, 7353 0x31, 0x53, 0x2F, 0x9F,
73540x3E, 0x30, 0x4F, 0xE9, 7354 0x3E, 0x30, 0x4F, 0xE9,
7355 7355
73560x39, 0xE5, 0x2C, 0x9F, 7356 0x39, 0xE5, 0x2C, 0x9F,
73570x3F, 0x38, 0x4F, 0xE9, 7357 0x3F, 0x38, 0x4F, 0xE9,
7358 7358
73590x30, 0x50, 0x2E, 0x9F, 7359 0x30, 0x50, 0x2E, 0x9F,
73600x3A, 0x31, 0x4F, 0xE9, 7360 0x3A, 0x31, 0x4F, 0xE9,
7361 7361
73620x38, 0x21, 0x2C, 0x9F, 7362 0x38, 0x21, 0x2C, 0x9F,
73630x3B, 0x39, 0x4F, 0xE9, 7363 0x3B, 0x39, 0x4F, 0xE9,
7364 7364
73650x2A, 0x45, 0x55, 0xB2, 7365 0x2A, 0x45, 0x55, 0xB2,
73660x1A, 0x45, 0x65, 0xB2, 7366 0x1A, 0x45, 0x65, 0xB2,
7367 7367
73680x0A, 0x45, 0x55, 0xB4, 7368 0x0A, 0x45, 0x55, 0xB4,
73690x02, 0x45, 0x65, 0xB4, 7369 0x02, 0x45, 0x65, 0xB4,
7370 7370
73710x0F, 0xCF, 0x74, 0xC6, 7371 0x0F, 0xCF, 0x74, 0xC6,
73720x2A, 0x20, 7372 0x2A, 0x20,
73730x1A, 0x20, 7373 0x1A, 0x20,
7374 7374
73750xA7, 0x30, 0x4F, 0xE9, 7375 0xA7, 0x30, 0x4F, 0xE9,
73760x0A, 0x20, 7376 0x0A, 0x20,
73770x02, 0x20, 7377 0x02, 0x20,
7378 7378
73790x31, 0x53, 0x2F, 0x9F, 7379 0x31, 0x53, 0x2F, 0x9F,
73800x9C, 0x0F, 0x20, 0xE9, 7380 0x9C, 0x0F, 0x20, 0xE9,
7381 7381
73820x39, 0xE5, 0x2C, 0x9F, 7382 0x39, 0xE5, 0x2C, 0x9F,
73830xA8, 0x38, 0x4F, 0xE9, 7383 0xA8, 0x38, 0x4F, 0xE9,
7384 7384
73850x2A, 0x44, 0x54, 0xB6, 7385 0x2A, 0x44, 0x54, 0xB6,
73860x1A, 0x44, 0x64, 0xB6, 7386 0x1A, 0x44, 0x64, 0xB6,
7387 7387
73880x30, 0x50, 0x2E, 0x9F, 7388 0x30, 0x50, 0x2E, 0x9F,
73890x36, 0x31, 0x4F, 0xE9, 7389 0x36, 0x31, 0x4F, 0xE9,
7390 7390
73910x38, 0x21, 0x2C, 0x9F, 7391 0x38, 0x21, 0x2C, 0x9F,
73920x37, 0x39, 0x4F, 0xE9, 7392 0x37, 0x39, 0x4F, 0xE9,
7393 7393
73940x00, 0x80, 0x00, 0xE8, 7394 0x00, 0x80, 0x00, 0xE8,
73950x2A, 0x20, 7395 0x2A, 0x20,
73960x1A, 0x20, 7396 0x1A, 0x20,
7397 7397
73980x2A, 0x46, 0x56, 0xBF, 7398 0x2A, 0x46, 0x56, 0xBF,
73990x1A, 0x46, 0x66, 0xBF, 7399 0x1A, 0x46, 0x66, 0xBF,
7400 7400
74010x31, 0x53, 0x2F, 0x9F, 7401 0x31, 0x53, 0x2F, 0x9F,
74020xA4, 0x31, 0x4F, 0xE9, 7402 0xA4, 0x31, 0x4F, 0xE9,
7403 7403
74040x39, 0xE5, 0x2C, 0x9F, 7404 0x39, 0xE5, 0x2C, 0x9F,
74050xA5, 0x39, 0x4F, 0xE9, 7405 0xA5, 0x39, 0x4F, 0xE9,
7406 7406
74070x0A, 0x47, 0x57, 0xBF, 7407 0x0A, 0x47, 0x57, 0xBF,
74080x02, 0x47, 0x67, 0xBF, 7408 0x02, 0x47, 0x67, 0xBF,
7409 7409
74100x31, 0x53, 0x2F, 0x9F, 7410 0x31, 0x53, 0x2F, 0x9F,
74110xA1, 0x30, 0x4F, 0xE9, 7411 0xA1, 0x30, 0x4F, 0xE9,
7412 7412
74130x39, 0xE5, 0x2C, 0x9F, 7413 0x39, 0xE5, 0x2C, 0x9F,
74140xA2, 0x38, 0x4F, 0xE9, 7414 0xA2, 0x38, 0x4F, 0xE9,
7415 7415
74160x2A, 0x43, 0x53, 0xBF, 7416 0x2A, 0x43, 0x53, 0xBF,
74170x1A, 0x43, 0x63, 0xBF, 7417 0x1A, 0x43, 0x63, 0xBF,
7418 7418
74190x30, 0x50, 0x2E, 0x9F, 7419 0x30, 0x50, 0x2E, 0x9F,
74200x9D, 0x31, 0x4F, 0xE9, 7420 0x9D, 0x31, 0x4F, 0xE9,
7421 7421
74220x38, 0x21, 0x2C, 0x9F, 7422 0x38, 0x21, 0x2C, 0x9F,
74230x9E, 0x39, 0x4F, 0xE9, 7423 0x9E, 0x39, 0x4F, 0xE9,
7424 7424
74250x0A, 0x48, 0x58, 0xBF, 7425 0x0A, 0x48, 0x58, 0xBF,
74260x02, 0x48, 0x68, 0xBF, 7426 0x02, 0x48, 0x68, 0xBF,
7427 7427
74280x31, 0x53, 0x2F, 0x9F, 7428 0x31, 0x53, 0x2F, 0x9F,
74290x80, 0x31, 0x57, 0xE9, 7429 0x80, 0x31, 0x57, 0xE9,
7430 7430
74310x39, 0xE5, 0x2C, 0x9F, 7431 0x39, 0xE5, 0x2C, 0x9F,
74320x81, 0x39, 0x57, 0xE9, 7432 0x81, 0x39, 0x57, 0xE9,
7433 7433
74340x2A, 0x49, 0x59, 0xBF, 7434 0x2A, 0x49, 0x59, 0xBF,
74350x1A, 0x49, 0x69, 0xBF, 7435 0x1A, 0x49, 0x69, 0xBF,
7436 7436
74370x30, 0x50, 0x2E, 0x9F, 7437 0x30, 0x50, 0x2E, 0x9F,
74380x82, 0x30, 0x57, 0xE9, 7438 0x82, 0x30, 0x57, 0xE9,
7439 7439
74400x38, 0x21, 0x2C, 0x9F, 7440 0x38, 0x21, 0x2C, 0x9F,
74410x83, 0x38, 0x57, 0xE9, 7441 0x83, 0x38, 0x57, 0xE9,
7442 7442
74430x31, 0x53, 0x2F, 0x9F, 7443 0x31, 0x53, 0x2F, 0x9F,
74440x84, 0x31, 0x5E, 0xE9, 7444 0x84, 0x31, 0x5E, 0xE9,
7445 7445
74460x39, 0xE5, 0x2C, 0x9F, 7446 0x39, 0xE5, 0x2C, 0x9F,
74470x85, 0x39, 0x5E, 0xE9, 7447 0x85, 0x39, 0x5E, 0xE9,
7448 7448
74490x86, 0x76, 0x57, 0xE9, 7449 0x86, 0x76, 0x57, 0xE9,
74500x8A, 0x36, 0x20, 0xE9, 7450 0x8A, 0x36, 0x20, 0xE9,
7451 7451
74520x87, 0x77, 0x57, 0xE9, 7452 0x87, 0x77, 0x57, 0xE9,
74530x8B, 0x3E, 0xBF, 0xEA, 7453 0x8B, 0x3E, 0xBF, 0xEA,
7454 7454
74550x80, 0x30, 0x57, 0xE9, 7455 0x80, 0x30, 0x57, 0xE9,
74560x81, 0x38, 0x57, 0xE9, 7456 0x81, 0x38, 0x57, 0xE9,
7457 7457
74580x82, 0x31, 0x57, 0xE9, 7458 0x82, 0x31, 0x57, 0xE9,
74590x86, 0x78, 0x57, 0xE9, 7459 0x86, 0x78, 0x57, 0xE9,
7460 7460
74610x83, 0x39, 0x57, 0xE9, 7461 0x83, 0x39, 0x57, 0xE9,
74620x87, 0x79, 0x57, 0xE9, 7462 0x87, 0x79, 0x57, 0xE9,
7463 7463
74640x30, 0x1F, 0x5F, 0xE9, 7464 0x30, 0x1F, 0x5F, 0xE9,
74650x8A, 0x34, 0x20, 0xE9, 7465 0x8A, 0x34, 0x20, 0xE9,
7466 7466
74670x8B, 0x3C, 0x20, 0xE9, 7467 0x8B, 0x3C, 0x20, 0xE9,
74680x37, 0x50, 0x60, 0xBD, 7468 0x37, 0x50, 0x60, 0xBD,
7469 7469
74700x57, 0x0D, 0x20, 0xE9, 7470 0x57, 0x0D, 0x20, 0xE9,
74710x35, 0x51, 0x61, 0xBD, 7471 0x35, 0x51, 0x61, 0xBD,
7472 7472
74730x2B, 0x50, 0x20, 0xE9, 7473 0x2B, 0x50, 0x20, 0xE9,
74740x1D, 0x37, 0xE1, 0xEA, 7474 0x1D, 0x37, 0xE1, 0xEA,
7475 7475
74760x1E, 0x35, 0xE1, 0xEA, 7476 0x1E, 0x35, 0xE1, 0xEA,
74770x00, 0xE0, 7477 0x00, 0xE0,
74780x0E, 0x77, 7478 0x0E, 0x77,
7479 7479
74800x24, 0x51, 0x20, 0xE9, 7480 0x24, 0x51, 0x20, 0xE9,
74810x8D, 0xFF, 0x20, 0xEA, 7481 0x8D, 0xFF, 0x20, 0xEA,
7482 7482
74830x16, 0x0E, 0x20, 0xE9, 7483 0x16, 0x0E, 0x20, 0xE9,
74840x57, 0x2E, 0xBF, 0xEA, 7484 0x57, 0x2E, 0xBF, 0xEA,
7485 7485
74860x0B, 0x46, 0xA0, 0xE8, 7486 0x0B, 0x46, 0xA0, 0xE8,
74870x1B, 0x56, 0xA0, 0xE8, 7487 0x1B, 0x56, 0xA0, 0xE8,
7488 7488
74890x2B, 0x66, 0xA0, 0xE8, 7489 0x2B, 0x66, 0xA0, 0xE8,
74900x0C, 0x47, 0xA0, 0xE8, 7490 0x0C, 0x47, 0xA0, 0xE8,
7491 7491
74920x1C, 0x57, 0xA0, 0xE8, 7492 0x1C, 0x57, 0xA0, 0xE8,
74930x2C, 0x67, 0xA0, 0xE8, 7493 0x2C, 0x67, 0xA0, 0xE8,
7494 7494
74950x0B, 0x00, 7495 0x0B, 0x00,
74960x1B, 0x00, 7496 0x1B, 0x00,
74970x2B, 0x00, 7497 0x2B, 0x00,
74980x00, 0xE0, 7498 0x00, 0xE0,
7499 7499
75000x0C, 0x00, 7500 0x0C, 0x00,
75010x1C, 0x00, 7501 0x1C, 0x00,
75020x2C, 0x00, 7502 0x2C, 0x00,
75030x00, 0xE0, 7503 0x00, 0xE0,
7504 7504
75050x0B, 0x65, 7505 0x0B, 0x65,
75060x1B, 0x65, 7506 0x1B, 0x65,
75070x2B, 0x65, 7507 0x2B, 0x65,
75080x00, 0xE0, 7508 0x00, 0xE0,
7509 7509
75100x0C, 0x65, 7510 0x0C, 0x65,
75110x1C, 0x65, 7511 0x1C, 0x65,
75120x2C, 0x65, 7512 0x2C, 0x65,
75130x00, 0xE0, 7513 0x00, 0xE0,
7514 7514
75150x0B, 0x1B, 0x60, 0xEC, 7515 0x0B, 0x1B, 0x60, 0xEC,
75160x36, 0xD7, 0x36, 0xAD, 7516 0x36, 0xD7, 0x36, 0xAD,
7517 7517
75180x2B, 0x80, 0x60, 0xEC, 7518 0x2B, 0x80, 0x60, 0xEC,
75190x0C, 0x1C, 0x60, 0xEC, 7519 0x0C, 0x1C, 0x60, 0xEC,
7520 7520
75210x3E, 0xD7, 0x3E, 0xAD, 7521 0x3E, 0xD7, 0x3E, 0xAD,
75220x2C, 0x80, 0x60, 0xEC, 7522 0x2C, 0x80, 0x60, 0xEC,
7523 7523
75240x0B, 0x2B, 0xDE, 0xE8, 7524 0x0B, 0x2B, 0xDE, 0xE8,
75250x1B, 0x80, 0xDE, 0xE8, 7525 0x1B, 0x80, 0xDE, 0xE8,
7526 7526
75270x36, 0x80, 0x36, 0xBD, 7527 0x36, 0x80, 0x36, 0xBD,
75280x3E, 0x80, 0x3E, 0xBD, 7528 0x3E, 0x80, 0x3E, 0xBD,
7529 7529
75300x33, 0xD7, 0x0B, 0xBD, 7530 0x33, 0xD7, 0x0B, 0xBD,
75310x3B, 0xD7, 0x1B, 0xBD, 7531 0x3B, 0xD7, 0x1B, 0xBD,
7532 7532
75330x46, 0x80, 0x46, 0xCF, 7533 0x46, 0x80, 0x46, 0xCF,
75340x57, 0x80, 0x57, 0xCF, 7534 0x57, 0x80, 0x57, 0xCF,
7535 7535
75360x66, 0x33, 0x66, 0xCF, 7536 0x66, 0x33, 0x66, 0xCF,
75370x47, 0x3B, 0x47, 0xCF, 7537 0x47, 0x3B, 0x47, 0xCF,
7538 7538
75390x56, 0x33, 0x56, 0xCF, 7539 0x56, 0x33, 0x56, 0xCF,
75400x67, 0x3B, 0x67, 0xCF, 7540 0x67, 0x3B, 0x67, 0xCF,
7541 7541
75420x0B, 0x48, 0xA0, 0xE8, 7542 0x0B, 0x48, 0xA0, 0xE8,
75430x1B, 0x58, 0xA0, 0xE8, 7543 0x1B, 0x58, 0xA0, 0xE8,
7544 7544
75450x2B, 0x68, 0xA0, 0xE8, 7545 0x2B, 0x68, 0xA0, 0xE8,
75460x0C, 0x49, 0xA0, 0xE8, 7546 0x0C, 0x49, 0xA0, 0xE8,
7547 7547
75480x1C, 0x59, 0xA0, 0xE8, 7548 0x1C, 0x59, 0xA0, 0xE8,
75490x2C, 0x69, 0xA0, 0xE8, 7549 0x2C, 0x69, 0xA0, 0xE8,
7550 7550
75510x0B, 0x00, 7551 0x0B, 0x00,
75520x1B, 0x00, 7552 0x1B, 0x00,
75530x2B, 0x00, 7553 0x2B, 0x00,
75540x00, 0xE0, 7554 0x00, 0xE0,
7555 7555
75560x0C, 0x00, 7556 0x0C, 0x00,
75570x1C, 0x00, 7557 0x1C, 0x00,
75580x2C, 0x00, 7558 0x2C, 0x00,
75590x00, 0xE0, 7559 0x00, 0xE0,
7560 7560
75610x0B, 0x65, 7561 0x0B, 0x65,
75620x1B, 0x65, 7562 0x1B, 0x65,
75630x2B, 0x65, 7563 0x2B, 0x65,
75640x00, 0xE0, 7564 0x00, 0xE0,
7565 7565
75660x0C, 0x65, 7566 0x0C, 0x65,
75670x1C, 0x65, 7567 0x1C, 0x65,
75680x2C, 0x65, 7568 0x2C, 0x65,
75690x00, 0xE0, 7569 0x00, 0xE0,
7570 7570
75710x0B, 0x1B, 0x60, 0xEC, 7571 0x0B, 0x1B, 0x60, 0xEC,
75720x34, 0xD7, 0x34, 0xAD, 7572 0x34, 0xD7, 0x34, 0xAD,
7573 7573
75740x2B, 0x80, 0x60, 0xEC, 7574 0x2B, 0x80, 0x60, 0xEC,
75750x0C, 0x1C, 0x60, 0xEC, 7575 0x0C, 0x1C, 0x60, 0xEC,
7576 7576
75770x3C, 0xD7, 0x3C, 0xAD, 7577 0x3C, 0xD7, 0x3C, 0xAD,
75780x2C, 0x80, 0x60, 0xEC, 7578 0x2C, 0x80, 0x60, 0xEC,
7579 7579
75800x0B, 0x2B, 0xDE, 0xE8, 7580 0x0B, 0x2B, 0xDE, 0xE8,
75810x1B, 0x80, 0xDE, 0xE8, 7581 0x1B, 0x80, 0xDE, 0xE8,
7582 7582
75830x34, 0x80, 0x34, 0xBD, 7583 0x34, 0x80, 0x34, 0xBD,
75840x3C, 0x80, 0x3C, 0xBD, 7584 0x3C, 0x80, 0x3C, 0xBD,
7585 7585
75860x33, 0xD7, 0x0B, 0xBD, 7586 0x33, 0xD7, 0x0B, 0xBD,
75870x3B, 0xD7, 0x1B, 0xBD, 7587 0x3B, 0xD7, 0x1B, 0xBD,
7588 7588
75890x48, 0x80, 0x48, 0xCF, 7589 0x48, 0x80, 0x48, 0xCF,
75900x59, 0x80, 0x59, 0xCF, 7590 0x59, 0x80, 0x59, 0xCF,
7591 7591
75920x68, 0x33, 0x68, 0xCF, 7592 0x68, 0x33, 0x68, 0xCF,
75930x49, 0x3B, 0x49, 0xCF, 7593 0x49, 0x3B, 0x49, 0xCF,
7594 7594
75950xAD, 0xFF, 0x20, 0xEA, 7595 0xAD, 0xFF, 0x20, 0xEA,
75960x00, 0x80, 0x00, 0xE8, 7596 0x00, 0x80, 0x00, 0xE8,
7597 7597
75980x58, 0x33, 0x58, 0xCF, 7598 0x58, 0x33, 0x58, 0xCF,
75990x69, 0x3B, 0x69, 0xCF, 7599 0x69, 0x3B, 0x69, 0xCF,
7600 7600
76010x6B, 0xFF, 0x20, 0xEA, 7601 0x6B, 0xFF, 0x20, 0xEA,
76020x57, 0xC0, 0xBF, 0xEA, 7602 0x57, 0xC0, 0xBF, 0xEA,
7603 7603
76040x00, 0x80, 0xA0, 0xE9, 7604 0x00, 0x80, 0xA0, 0xE9,
76050x00, 0x00, 0xD8, 0xEC, 7605 0x00, 0x00, 0xD8, 0xEC,
7606 7606
7607}; 7607};
7608 7608
7609static unsigned char warp_g400_t2gzsaf[] = { 7609static unsigned char warp_g400_t2gzsaf[] = {
7610 7610
76110x00, 0x8A, 0x98, 0xE9, 7611 0x00, 0x8A, 0x98, 0xE9,
76120x00, 0x80, 0x00, 0xE8, 7612 0x00, 0x80, 0x00, 0xE8,
7613 7613
76140x00, 0x80, 0xA0, 0xE9, 7614 0x00, 0x80, 0xA0, 0xE9,
76150x00, 0x00, 0xD8, 0xEC, 7615 0x00, 0x00, 0xD8, 0xEC,
7616 7616
76170xFF, 0x80, 0xC0, 0xE9, 7617 0xFF, 0x80, 0xC0, 0xE9,
76180x00, 0x80, 0x00, 0xE8, 7618 0x00, 0x80, 0x00, 0xE8,
7619 7619
76200x0A, 0x40, 0x50, 0xBF, 7620 0x0A, 0x40, 0x50, 0xBF,
76210x2A, 0x40, 0x60, 0xBF, 7621 0x2A, 0x40, 0x60, 0xBF,
7622 7622
76230x32, 0x41, 0x51, 0xBF, 7623 0x32, 0x41, 0x51, 0xBF,
76240x3A, 0x41, 0x61, 0xBF, 7624 0x3A, 0x41, 0x61, 0xBF,
7625 7625
76260xC3, 0x6B, 7626 0xC3, 0x6B,
76270xD3, 0x6B, 7627 0xD3, 0x6B,
76280x00, 0x8A, 0x98, 0xE9, 7628 0x00, 0x8A, 0x98, 0xE9,
7629 7629
76300x73, 0x7B, 0xC8, 0xEC, 7630 0x73, 0x7B, 0xC8, 0xEC,
76310x96, 0xE2, 7631 0x96, 0xE2,
76320x41, 0x04, 7632 0x41, 0x04,
7633 7633
76340x7B, 0x43, 0xA0, 0xE8, 7634 0x7B, 0x43, 0xA0, 0xE8,
76350x73, 0x53, 0xA0, 0xE8, 7635 0x73, 0x53, 0xA0, 0xE8,
7636 7636
76370xAD, 0xEE, 0x23, 0x9F, 7637 0xAD, 0xEE, 0x23, 0x9F,
76380x00, 0xE0, 7638 0x00, 0xE0,
76390x51, 0x04, 7639 0x51, 0x04,
7640 7640
76410x90, 0xE2, 7641 0x90, 0xE2,
76420x61, 0x04, 7642 0x61, 0x04,
76430x31, 0x46, 0xB1, 0xE8, 7643 0x31, 0x46, 0xB1, 0xE8,
7644 7644
76450x51, 0x41, 0xE0, 0xEC, 7645 0x51, 0x41, 0xE0, 0xEC,
76460x39, 0x67, 0xB1, 0xE8, 7646 0x39, 0x67, 0xB1, 0xE8,
7647 7647
76480x00, 0x04, 7648 0x00, 0x04,
76490x46, 0xE2, 7649 0x46, 0xE2,
76500x73, 0x63, 0xA0, 0xE8, 7650 0x73, 0x63, 0xA0, 0xE8,
7651 7651
76520x61, 0x41, 0xE0, 0xEC, 7652 0x61, 0x41, 0xE0, 0xEC,
76530x31, 0x00, 7653 0x31, 0x00,
76540x39, 0x00, 7654 0x39, 0x00,
7655 7655
76560x8E, 0x80, 0x15, 0xEA, 7656 0x8E, 0x80, 0x15, 0xEA,
76570x10, 0x04, 7657 0x10, 0x04,
76580x20, 0x04, 7658 0x20, 0x04,
7659 7659
76600x61, 0x51, 0xE0, 0xEC, 7660 0x61, 0x51, 0xE0, 0xEC,
76610x2F, 0x41, 0x60, 0xEA, 7661 0x2F, 0x41, 0x60, 0xEA,
7662 7662
76630x31, 0x20, 7663 0x31, 0x20,
76640x39, 0x20, 7664 0x39, 0x20,
76650x1F, 0x42, 0xA0, 0xE8, 7665 0x1F, 0x42, 0xA0, 0xE8,
7666 7666
76670x2A, 0x42, 0x52, 0xBF, 7667 0x2A, 0x42, 0x52, 0xBF,
76680x0F, 0x52, 0xA0, 0xE8, 7668 0x0F, 0x52, 0xA0, 0xE8,
7669 7669
76700x1A, 0x42, 0x62, 0xBF, 7670 0x1A, 0x42, 0x62, 0xBF,
76710x1E, 0x51, 0x60, 0xEA, 7671 0x1E, 0x51, 0x60, 0xEA,
7672 7672
76730x73, 0x7B, 0xC8, 0xEC, 7673 0x73, 0x7B, 0xC8, 0xEC,
76740x0E, 0x61, 0x60, 0xEA, 7674 0x0E, 0x61, 0x60, 0xEA,
7675 7675
76760x32, 0x40, 0x50, 0xBD, 7676 0x32, 0x40, 0x50, 0xBD,
76770x22, 0x40, 0x60, 0xBD, 7677 0x22, 0x40, 0x60, 0xBD,
7678 7678
76790x12, 0x41, 0x51, 0xBD, 7679 0x12, 0x41, 0x51, 0xBD,
76800x3A, 0x41, 0x61, 0xBD, 7680 0x3A, 0x41, 0x61, 0xBD,
7681 7681
76820xBF, 0x2F, 0x0E, 0xBD, 7682 0xBF, 0x2F, 0x0E, 0xBD,
76830x97, 0xE2, 7683 0x97, 0xE2,
76840x7B, 0x72, 7684 0x7B, 0x72,
7685 7685
76860x32, 0x20, 7686 0x32, 0x20,
76870x22, 0x20, 7687 0x22, 0x20,
76880x12, 0x20, 7688 0x12, 0x20,
76890x3A, 0x20, 7689 0x3A, 0x20,
7690 7690
76910x35, 0x48, 0xB1, 0xE8, 7691 0x35, 0x48, 0xB1, 0xE8,
76920x3D, 0x59, 0xB1, 0xE8, 7692 0x3D, 0x59, 0xB1, 0xE8,
7693 7693
76940x46, 0x31, 0x46, 0xBF, 7694 0x46, 0x31, 0x46, 0xBF,
76950x56, 0x31, 0x56, 0xBF, 7695 0x56, 0x31, 0x56, 0xBF,
7696 7696
76970xB3, 0xE2, 0x2D, 0x9F, 7697 0xB3, 0xE2, 0x2D, 0x9F,
76980x00, 0x80, 0x00, 0xE8, 7698 0x00, 0x80, 0x00, 0xE8,
7699 7699
77000x66, 0x31, 0x66, 0xBF, 7700 0x66, 0x31, 0x66, 0xBF,
77010x47, 0x39, 0x47, 0xBF, 7701 0x47, 0x39, 0x47, 0xBF,
7702 7702
77030x57, 0x39, 0x57, 0xBF, 7703 0x57, 0x39, 0x57, 0xBF,
77040x67, 0x39, 0x67, 0xBF, 7704 0x67, 0x39, 0x67, 0xBF,
7705 7705
77060x7F, 0x80, 0x07, 0xEA, 7706 0x7F, 0x80, 0x07, 0xEA,
77070x24, 0x41, 0x20, 0xE9, 7707 0x24, 0x41, 0x20, 0xE9,
7708 7708
77090x35, 0x00, 7709 0x35, 0x00,
77100x3D, 0x00, 7710 0x3D, 0x00,
77110x00, 0xE0, 7711 0x00, 0xE0,
77120x2D, 0x73, 7712 0x2D, 0x73,
7713 7713
77140x33, 0x72, 7714 0x33, 0x72,
77150x0C, 0xE3, 7715 0x0C, 0xE3,
77160x8D, 0x2F, 0x1E, 0xBD, 7716 0x8D, 0x2F, 0x1E, 0xBD,
7717 7717
77180x43, 0x75, 0xF8, 0xEC, 7718 0x43, 0x75, 0xF8, 0xEC,
77190x35, 0x20, 7719 0x35, 0x20,
77200x3D, 0x20, 7720 0x3D, 0x20,
7721 7721
77220x43, 0x43, 0x2D, 0xDF, 7722 0x43, 0x43, 0x2D, 0xDF,
77230x53, 0x53, 0x2D, 0xDF, 7723 0x53, 0x53, 0x2D, 0xDF,
7724 7724
77250xAE, 0x1E, 0x0E, 0xBD, 7725 0xAE, 0x1E, 0x0E, 0xBD,
77260x58, 0xE3, 7726 0x58, 0xE3,
77270x33, 0x66, 7727 0x33, 0x66,
7728 7728
77290x48, 0x35, 0x48, 0xBF, 7729 0x48, 0x35, 0x48, 0xBF,
77300x58, 0x35, 0x58, 0xBF, 7730 0x58, 0x35, 0x58, 0xBF,
7731 7731
77320x68, 0x35, 0x68, 0xBF, 7732 0x68, 0x35, 0x68, 0xBF,
77330x49, 0x3D, 0x49, 0xBF, 7733 0x49, 0x3D, 0x49, 0xBF,
7734 7734
77350x59, 0x3D, 0x59, 0xBF, 7735 0x59, 0x3D, 0x59, 0xBF,
77360x69, 0x3D, 0x69, 0xBF, 7736 0x69, 0x3D, 0x69, 0xBF,
7737 7737
77380x63, 0x63, 0x2D, 0xDF, 7738 0x63, 0x63, 0x2D, 0xDF,
77390x4D, 0x7D, 0xF8, 0xEC, 7739 0x4D, 0x7D, 0xF8, 0xEC,
7740 7740
77410x59, 0xE3, 7741 0x59, 0xE3,
77420x00, 0xE0, 7742 0x00, 0xE0,
77430xB8, 0x38, 0x33, 0xBF, 7743 0xB8, 0x38, 0x33, 0xBF,
7744 7744
77450x2D, 0x73, 7745 0x2D, 0x73,
77460x30, 0x76, 7746 0x30, 0x76,
77470x18, 0x3A, 0x41, 0xE9, 7747 0x18, 0x3A, 0x41, 0xE9,
7748 7748
77490x3F, 0x53, 0xA0, 0xE8, 7749 0x3F, 0x53, 0xA0, 0xE8,
77500x05, 0x80, 0x3D, 0xEA, 7750 0x05, 0x80, 0x3D, 0xEA,
7751 7751
77520x37, 0x43, 0xA0, 0xE8, 7752 0x37, 0x43, 0xA0, 0xE8,
77530x3D, 0x63, 0xA0, 0xE8, 7753 0x3D, 0x63, 0xA0, 0xE8,
7754 7754
77550x50, 0x70, 0xF8, 0xEC, 7755 0x50, 0x70, 0xF8, 0xEC,
77560x2B, 0x50, 0x3C, 0xE9, 7756 0x2B, 0x50, 0x3C, 0xE9,
7757 7757
77580x1F, 0x0F, 0xBC, 0xE8, 7758 0x1F, 0x0F, 0xBC, 0xE8,
77590x00, 0x80, 0x00, 0xE8, 7759 0x00, 0x80, 0x00, 0xE8,
7760 7760
77610x59, 0x78, 0xF8, 0xEC, 7761 0x59, 0x78, 0xF8, 0xEC,
77620x00, 0x80, 0x00, 0xE8, 7762 0x00, 0x80, 0x00, 0xE8,
7763 7763
77640x15, 0xC0, 0x20, 0xE9, 7764 0x15, 0xC0, 0x20, 0xE9,
77650x15, 0xC0, 0x20, 0xE9, 7765 0x15, 0xC0, 0x20, 0xE9,
7766 7766
77670x15, 0xC0, 0x20, 0xE9, 7767 0x15, 0xC0, 0x20, 0xE9,
77680x15, 0xC0, 0x20, 0xE9, 7768 0x15, 0xC0, 0x20, 0xE9,
7769 7769
77700x1E, 0x12, 0x41, 0xE9, 7770 0x1E, 0x12, 0x41, 0xE9,
77710x1A, 0x22, 0x41, 0xE9, 7771 0x1A, 0x22, 0x41, 0xE9,
7772 7772
77730x46, 0x37, 0x46, 0xDF, 7773 0x46, 0x37, 0x46, 0xDF,
77740x56, 0x3F, 0x56, 0xDF, 7774 0x56, 0x3F, 0x56, 0xDF,
7775 7775
77760x2B, 0x40, 0x3D, 0xE9, 7776 0x2B, 0x40, 0x3D, 0xE9,
77770x66, 0x3D, 0x66, 0xDF, 7777 0x66, 0x3D, 0x66, 0xDF,
7778 7778
77790x1D, 0x32, 0x41, 0xE9, 7779 0x1D, 0x32, 0x41, 0xE9,
77800x67, 0x3D, 0x67, 0xDF, 7780 0x67, 0x3D, 0x67, 0xDF,
7781 7781
77820x47, 0x37, 0x47, 0xDF, 7782 0x47, 0x37, 0x47, 0xDF,
77830x57, 0x3F, 0x57, 0xDF, 7783 0x57, 0x3F, 0x57, 0xDF,
7784 7784
77850x2A, 0x40, 0x20, 0xE9, 7785 0x2A, 0x40, 0x20, 0xE9,
77860x59, 0x3F, 0x59, 0xDF, 7786 0x59, 0x3F, 0x59, 0xDF,
7787 7787
77880x16, 0x30, 0x20, 0xE9, 7788 0x16, 0x30, 0x20, 0xE9,
77890x69, 0x3D, 0x69, 0xDF, 7789 0x69, 0x3D, 0x69, 0xDF,
7790 7790
77910x48, 0x37, 0x48, 0xDF, 7791 0x48, 0x37, 0x48, 0xDF,
77920x58, 0x3F, 0x58, 0xDF, 7792 0x58, 0x3F, 0x58, 0xDF,
7793 7793
77940x68, 0x3D, 0x68, 0xDF, 7794 0x68, 0x3D, 0x68, 0xDF,
77950x49, 0x37, 0x49, 0xDF, 7795 0x49, 0x37, 0x49, 0xDF,
7796 7796
77970x32, 0x32, 0x2D, 0xDF, 7797 0x32, 0x32, 0x2D, 0xDF,
77980x22, 0x22, 0x2D, 0xDF, 7798 0x22, 0x22, 0x2D, 0xDF,
7799 7799
78000x12, 0x12, 0x2D, 0xDF, 7800 0x12, 0x12, 0x2D, 0xDF,
78010x3A, 0x3A, 0x2D, 0xDF, 7801 0x3A, 0x3A, 0x2D, 0xDF,
7802 7802
78030x0F, 0xCF, 0x74, 0xC2, 7803 0x0F, 0xCF, 0x74, 0xC2,
78040x37, 0xCF, 0x74, 0xC4, 7804 0x37, 0xCF, 0x74, 0xC4,
7805 7805
78060x0A, 0x44, 0x54, 0xB0, 7806 0x0A, 0x44, 0x54, 0xB0,
78070x02, 0x44, 0x64, 0xB0, 7807 0x02, 0x44, 0x64, 0xB0,
7808 7808
78090x3D, 0xCF, 0x74, 0xC0, 7809 0x3D, 0xCF, 0x74, 0xC0,
78100x34, 0x37, 0x20, 0xE9, 7810 0x34, 0x37, 0x20, 0xE9,
7811 7811
78120x31, 0x53, 0x2F, 0x9F, 7812 0x31, 0x53, 0x2F, 0x9F,
78130x38, 0x0F, 0x20, 0xE9, 7813 0x38, 0x0F, 0x20, 0xE9,
7814 7814
78150x39, 0xE5, 0x2C, 0x9F, 7815 0x39, 0xE5, 0x2C, 0x9F,
78160x3C, 0x3D, 0x20, 0xE9, 7816 0x3C, 0x3D, 0x20, 0xE9,
7817 7817
78180x2A, 0x44, 0x54, 0xB2, 7818 0x2A, 0x44, 0x54, 0xB2,
78190x1A, 0x44, 0x64, 0xB2, 7819 0x1A, 0x44, 0x64, 0xB2,
7820 7820
78210x3A, 0x80, 0x3A, 0xEA, 7821 0x3A, 0x80, 0x3A, 0xEA,
78220x0A, 0x20, 7822 0x0A, 0x20,
78230x02, 0x20, 7823 0x02, 0x20,
7824 7824
78250x0F, 0xCF, 0x75, 0xC0, 7825 0x0F, 0xCF, 0x75, 0xC0,
78260x2A, 0x20, 7826 0x2A, 0x20,
78270x1A, 0x20, 7827 0x1A, 0x20,
7828 7828
78290x30, 0x50, 0x2E, 0x9F, 7829 0x30, 0x50, 0x2E, 0x9F,
78300x32, 0x31, 0x5F, 0xE9, 7830 0x32, 0x31, 0x5F, 0xE9,
7831 7831
78320x38, 0x21, 0x2C, 0x9F, 7832 0x38, 0x21, 0x2C, 0x9F,
78330x33, 0x39, 0x5F, 0xE9, 7833 0x33, 0x39, 0x5F, 0xE9,
7834 7834
78350x3D, 0xCF, 0x75, 0xC2, 7835 0x3D, 0xCF, 0x75, 0xC2,
78360x37, 0xCF, 0x75, 0xC4, 7836 0x37, 0xCF, 0x75, 0xC4,
7837 7837
78380x31, 0x53, 0x2F, 0x9F, 7838 0x31, 0x53, 0x2F, 0x9F,
78390xA6, 0x0F, 0x20, 0xE9, 7839 0xA6, 0x0F, 0x20, 0xE9,
7840 7840
78410x39, 0xE5, 0x2C, 0x9F, 7841 0x39, 0xE5, 0x2C, 0x9F,
78420xA3, 0x3D, 0x20, 0xE9, 7842 0xA3, 0x3D, 0x20, 0xE9,
7843 7843
78440x2A, 0x44, 0x54, 0xB4, 7844 0x2A, 0x44, 0x54, 0xB4,
78450x1A, 0x44, 0x64, 0xB4, 7845 0x1A, 0x44, 0x64, 0xB4,
7846 7846
78470x0A, 0x45, 0x55, 0xB0, 7847 0x0A, 0x45, 0x55, 0xB0,
78480x02, 0x45, 0x65, 0xB0, 7848 0x02, 0x45, 0x65, 0xB0,
7849 7849
78500x88, 0x73, 0x5E, 0xE9, 7850 0x88, 0x73, 0x5E, 0xE9,
78510x2A, 0x20, 7851 0x2A, 0x20,
78520x1A, 0x20, 7852 0x1A, 0x20,
7853 7853
78540xA0, 0x37, 0x20, 0xE9, 7854 0xA0, 0x37, 0x20, 0xE9,
78550x0A, 0x20, 7855 0x0A, 0x20,
78560x02, 0x20, 7856 0x02, 0x20,
7857 7857
78580x31, 0x53, 0x2F, 0x9F, 7858 0x31, 0x53, 0x2F, 0x9F,
78590x3E, 0x30, 0x4F, 0xE9, 7859 0x3E, 0x30, 0x4F, 0xE9,
7860 7860
78610x39, 0xE5, 0x2C, 0x9F, 7861 0x39, 0xE5, 0x2C, 0x9F,
78620x3F, 0x38, 0x4F, 0xE9, 7862 0x3F, 0x38, 0x4F, 0xE9,
7863 7863
78640x30, 0x50, 0x2E, 0x9F, 7864 0x30, 0x50, 0x2E, 0x9F,
78650x3A, 0x31, 0x4F, 0xE9, 7865 0x3A, 0x31, 0x4F, 0xE9,
7866 7866
78670x38, 0x21, 0x2C, 0x9F, 7867 0x38, 0x21, 0x2C, 0x9F,
78680x3B, 0x39, 0x4F, 0xE9, 7868 0x3B, 0x39, 0x4F, 0xE9,
7869 7869
78700x2A, 0x45, 0x55, 0xB2, 7870 0x2A, 0x45, 0x55, 0xB2,
78710x1A, 0x45, 0x65, 0xB2, 7871 0x1A, 0x45, 0x65, 0xB2,
7872 7872
78730x0A, 0x45, 0x55, 0xB4, 7873 0x0A, 0x45, 0x55, 0xB4,
78740x02, 0x45, 0x65, 0xB4, 7874 0x02, 0x45, 0x65, 0xB4,
7875 7875
78760x0F, 0xCF, 0x74, 0xC6, 7876 0x0F, 0xCF, 0x74, 0xC6,
78770x2A, 0x20, 7877 0x2A, 0x20,
78780x1A, 0x20, 7878 0x1A, 0x20,
7879 7879
78800xA7, 0x30, 0x4F, 0xE9, 7880 0xA7, 0x30, 0x4F, 0xE9,
78810x0A, 0x20, 7881 0x0A, 0x20,
78820x02, 0x20, 7882 0x02, 0x20,
7883 7883
78840x31, 0x53, 0x2F, 0x9F, 7884 0x31, 0x53, 0x2F, 0x9F,
78850x9C, 0x0F, 0x20, 0xE9, 7885 0x9C, 0x0F, 0x20, 0xE9,
7886 7886
78870x39, 0xE5, 0x2C, 0x9F, 7887 0x39, 0xE5, 0x2C, 0x9F,
78880xA8, 0x38, 0x4F, 0xE9, 7888 0xA8, 0x38, 0x4F, 0xE9,
7889 7889
78900x2A, 0x44, 0x54, 0xB6, 7890 0x2A, 0x44, 0x54, 0xB6,
78910x1A, 0x44, 0x64, 0xB6, 7891 0x1A, 0x44, 0x64, 0xB6,
7892 7892
78930x30, 0x50, 0x2E, 0x9F, 7893 0x30, 0x50, 0x2E, 0x9F,
78940x36, 0x31, 0x4F, 0xE9, 7894 0x36, 0x31, 0x4F, 0xE9,
7895 7895
78960x38, 0x21, 0x2C, 0x9F, 7896 0x38, 0x21, 0x2C, 0x9F,
78970x37, 0x39, 0x4F, 0xE9, 7897 0x37, 0x39, 0x4F, 0xE9,
7898 7898
78990x0A, 0x45, 0x55, 0xB6, 7899 0x0A, 0x45, 0x55, 0xB6,
79000x02, 0x45, 0x65, 0xB6, 7900 0x02, 0x45, 0x65, 0xB6,
7901 7901
79020x3D, 0xCF, 0x75, 0xC6, 7902 0x3D, 0xCF, 0x75, 0xC6,
79030x2A, 0x20, 7903 0x2A, 0x20,
79040x1A, 0x20, 7904 0x1A, 0x20,
7905 7905
79060x2A, 0x46, 0x56, 0xBF, 7906 0x2A, 0x46, 0x56, 0xBF,
79070x1A, 0x46, 0x66, 0xBF, 7907 0x1A, 0x46, 0x66, 0xBF,
7908 7908
79090x31, 0x53, 0x2F, 0x9F, 7909 0x31, 0x53, 0x2F, 0x9F,
79100xA4, 0x31, 0x4F, 0xE9, 7910 0xA4, 0x31, 0x4F, 0xE9,
7911 7911
79120x39, 0xE5, 0x2C, 0x9F, 7912 0x39, 0xE5, 0x2C, 0x9F,
79130xA5, 0x39, 0x4F, 0xE9, 7913 0xA5, 0x39, 0x4F, 0xE9,
7914 7914
79150x31, 0x3D, 0x20, 0xE9, 7915 0x31, 0x3D, 0x20, 0xE9,
79160x0A, 0x20, 7916 0x0A, 0x20,
79170x02, 0x20, 7917 0x02, 0x20,
7918 7918
79190x0A, 0x47, 0x57, 0xBF, 7919 0x0A, 0x47, 0x57, 0xBF,
79200x02, 0x47, 0x67, 0xBF, 7920 0x02, 0x47, 0x67, 0xBF,
7921 7921
79220x30, 0x50, 0x2E, 0x9F, 7922 0x30, 0x50, 0x2E, 0x9F,
79230xA1, 0x30, 0x4F, 0xE9, 7923 0xA1, 0x30, 0x4F, 0xE9,
7924 7924
79250x38, 0x21, 0x2C, 0x9F, 7925 0x38, 0x21, 0x2C, 0x9F,
79260xA2, 0x38, 0x4F, 0xE9, 7926 0xA2, 0x38, 0x4F, 0xE9,
7927 7927
79280x31, 0x53, 0x2F, 0x9F, 7928 0x31, 0x53, 0x2F, 0x9F,
79290x9D, 0x31, 0x4F, 0xE9, 7929 0x9D, 0x31, 0x4F, 0xE9,
7930 7930
79310x39, 0xE5, 0x2C, 0x9F, 7931 0x39, 0xE5, 0x2C, 0x9F,
79320x9E, 0x39, 0x4F, 0xE9, 7932 0x9E, 0x39, 0x4F, 0xE9,
7933 7933
79340x2A, 0x43, 0x53, 0xBF, 7934 0x2A, 0x43, 0x53, 0xBF,
79350x1A, 0x43, 0x63, 0xBF, 7935 0x1A, 0x43, 0x63, 0xBF,
7936 7936
79370x30, 0x50, 0x2E, 0x9F, 7937 0x30, 0x50, 0x2E, 0x9F,
79380x35, 0x30, 0x4F, 0xE9, 7938 0x35, 0x30, 0x4F, 0xE9,
7939 7939
79400x38, 0x21, 0x2C, 0x9F, 7940 0x38, 0x21, 0x2C, 0x9F,
79410x39, 0x38, 0x4F, 0xE9, 7941 0x39, 0x38, 0x4F, 0xE9,
7942 7942
79430x0A, 0x48, 0x58, 0xBF, 7943 0x0A, 0x48, 0x58, 0xBF,
79440x02, 0x48, 0x68, 0xBF, 7944 0x02, 0x48, 0x68, 0xBF,
7945 7945
79460x31, 0x53, 0x2F, 0x9F, 7946 0x31, 0x53, 0x2F, 0x9F,
79470x80, 0x31, 0x57, 0xE9, 7947 0x80, 0x31, 0x57, 0xE9,
7948 7948
79490x39, 0xE5, 0x2C, 0x9F, 7949 0x39, 0xE5, 0x2C, 0x9F,
79500x81, 0x39, 0x57, 0xE9, 7950 0x81, 0x39, 0x57, 0xE9,
7951 7951
79520x2A, 0x49, 0x59, 0xBF, 7952 0x2A, 0x49, 0x59, 0xBF,
79530x1A, 0x49, 0x69, 0xBF, 7953 0x1A, 0x49, 0x69, 0xBF,
7954 7954
79550x30, 0x50, 0x2E, 0x9F, 7955 0x30, 0x50, 0x2E, 0x9F,
79560x82, 0x30, 0x57, 0xE9, 7956 0x82, 0x30, 0x57, 0xE9,
7957 7957
79580x38, 0x21, 0x2C, 0x9F, 7958 0x38, 0x21, 0x2C, 0x9F,
79590x83, 0x38, 0x57, 0xE9, 7959 0x83, 0x38, 0x57, 0xE9,
7960 7960
79610x31, 0x53, 0x2F, 0x9F, 7961 0x31, 0x53, 0x2F, 0x9F,
79620x84, 0x31, 0x5E, 0xE9, 7962 0x84, 0x31, 0x5E, 0xE9,
7963 7963
79640x39, 0xE5, 0x2C, 0x9F, 7964 0x39, 0xE5, 0x2C, 0x9F,
79650x85, 0x39, 0x5E, 0xE9, 7965 0x85, 0x39, 0x5E, 0xE9,
7966 7966
79670x86, 0x76, 0x57, 0xE9, 7967 0x86, 0x76, 0x57, 0xE9,
79680x8A, 0x36, 0x20, 0xE9, 7968 0x8A, 0x36, 0x20, 0xE9,
7969 7969
79700x87, 0x77, 0x57, 0xE9, 7970 0x87, 0x77, 0x57, 0xE9,
79710x8B, 0x3E, 0xBF, 0xEA, 7971 0x8B, 0x3E, 0xBF, 0xEA,
7972 7972
79730x80, 0x30, 0x57, 0xE9, 7973 0x80, 0x30, 0x57, 0xE9,
79740x81, 0x38, 0x57, 0xE9, 7974 0x81, 0x38, 0x57, 0xE9,
7975 7975
79760x82, 0x31, 0x57, 0xE9, 7976 0x82, 0x31, 0x57, 0xE9,
79770x86, 0x78, 0x57, 0xE9, 7977 0x86, 0x78, 0x57, 0xE9,
7978 7978
79790x83, 0x39, 0x57, 0xE9, 7979 0x83, 0x39, 0x57, 0xE9,
79800x87, 0x79, 0x57, 0xE9, 7980 0x87, 0x79, 0x57, 0xE9,
7981 7981
79820x30, 0x1F, 0x5F, 0xE9, 7982 0x30, 0x1F, 0x5F, 0xE9,
79830x8A, 0x34, 0x20, 0xE9, 7983 0x8A, 0x34, 0x20, 0xE9,
7984 7984
79850x8B, 0x3C, 0x20, 0xE9, 7985 0x8B, 0x3C, 0x20, 0xE9,
79860x37, 0x50, 0x60, 0xBD, 7986 0x37, 0x50, 0x60, 0xBD,
7987 7987
79880x57, 0x0D, 0x20, 0xE9, 7988 0x57, 0x0D, 0x20, 0xE9,
79890x35, 0x51, 0x61, 0xBD, 7989 0x35, 0x51, 0x61, 0xBD,
7990 7990
79910x2B, 0x50, 0x20, 0xE9, 7991 0x2B, 0x50, 0x20, 0xE9,
79920x1D, 0x37, 0xE1, 0xEA, 7992 0x1D, 0x37, 0xE1, 0xEA,
7993 7993
79940x1E, 0x35, 0xE1, 0xEA, 7994 0x1E, 0x35, 0xE1, 0xEA,
79950x00, 0xE0, 7995 0x00, 0xE0,
79960x0E, 0x77, 7996 0x0E, 0x77,
7997 7997
79980x24, 0x51, 0x20, 0xE9, 7998 0x24, 0x51, 0x20, 0xE9,
79990x89, 0xFF, 0x20, 0xEA, 7999 0x89, 0xFF, 0x20, 0xEA,
8000 8000
80010x16, 0x0E, 0x20, 0xE9, 8001 0x16, 0x0E, 0x20, 0xE9,
80020x57, 0x2E, 0xBF, 0xEA, 8002 0x57, 0x2E, 0xBF, 0xEA,
8003 8003
80040x0B, 0x46, 0xA0, 0xE8, 8004 0x0B, 0x46, 0xA0, 0xE8,
80050x1B, 0x56, 0xA0, 0xE8, 8005 0x1B, 0x56, 0xA0, 0xE8,
8006 8006
80070x2B, 0x66, 0xA0, 0xE8, 8007 0x2B, 0x66, 0xA0, 0xE8,
80080x0C, 0x47, 0xA0, 0xE8, 8008 0x0C, 0x47, 0xA0, 0xE8,
8009 8009
80100x1C, 0x57, 0xA0, 0xE8, 8010 0x1C, 0x57, 0xA0, 0xE8,
80110x2C, 0x67, 0xA0, 0xE8, 8011 0x2C, 0x67, 0xA0, 0xE8,
8012 8012
80130x0B, 0x00, 8013 0x0B, 0x00,
80140x1B, 0x00, 8014 0x1B, 0x00,
80150x2B, 0x00, 8015 0x2B, 0x00,
80160x00, 0xE0, 8016 0x00, 0xE0,
8017 8017
80180x0C, 0x00, 8018 0x0C, 0x00,
80190x1C, 0x00, 8019 0x1C, 0x00,
80200x2C, 0x00, 8020 0x2C, 0x00,
80210x00, 0xE0, 8021 0x00, 0xE0,
8022 8022
80230x0B, 0x65, 8023 0x0B, 0x65,
80240x1B, 0x65, 8024 0x1B, 0x65,
80250x2B, 0x65, 8025 0x2B, 0x65,
80260x00, 0xE0, 8026 0x00, 0xE0,
8027 8027
80280x0C, 0x65, 8028 0x0C, 0x65,
80290x1C, 0x65, 8029 0x1C, 0x65,
80300x2C, 0x65, 8030 0x2C, 0x65,
80310x00, 0xE0, 8031 0x00, 0xE0,
8032 8032
80330x0B, 0x1B, 0x60, 0xEC, 8033 0x0B, 0x1B, 0x60, 0xEC,
80340x36, 0xD7, 0x36, 0xAD, 8034 0x36, 0xD7, 0x36, 0xAD,
8035 8035
80360x2B, 0x80, 0x60, 0xEC, 8036 0x2B, 0x80, 0x60, 0xEC,
80370x0C, 0x1C, 0x60, 0xEC, 8037 0x0C, 0x1C, 0x60, 0xEC,
8038 8038
80390x3E, 0xD7, 0x3E, 0xAD, 8039 0x3E, 0xD7, 0x3E, 0xAD,
80400x2C, 0x80, 0x60, 0xEC, 8040 0x2C, 0x80, 0x60, 0xEC,
8041 8041
80420x0B, 0x2B, 0xDE, 0xE8, 8042 0x0B, 0x2B, 0xDE, 0xE8,
80430x1B, 0x80, 0xDE, 0xE8, 8043 0x1B, 0x80, 0xDE, 0xE8,
8044 8044
80450x36, 0x80, 0x36, 0xBD, 8045 0x36, 0x80, 0x36, 0xBD,
80460x3E, 0x80, 0x3E, 0xBD, 8046 0x3E, 0x80, 0x3E, 0xBD,
8047 8047
80480x33, 0xD7, 0x0B, 0xBD, 8048 0x33, 0xD7, 0x0B, 0xBD,
80490x3B, 0xD7, 0x1B, 0xBD, 8049 0x3B, 0xD7, 0x1B, 0xBD,
8050 8050
80510x46, 0x80, 0x46, 0xCF, 8051 0x46, 0x80, 0x46, 0xCF,
80520x57, 0x80, 0x57, 0xCF, 8052 0x57, 0x80, 0x57, 0xCF,
8053 8053
80540x66, 0x33, 0x66, 0xCF, 8054 0x66, 0x33, 0x66, 0xCF,
80550x47, 0x3B, 0x47, 0xCF, 8055 0x47, 0x3B, 0x47, 0xCF,
8056 8056
80570x56, 0x33, 0x56, 0xCF, 8057 0x56, 0x33, 0x56, 0xCF,
80580x67, 0x3B, 0x67, 0xCF, 8058 0x67, 0x3B, 0x67, 0xCF,
8059 8059
80600x0B, 0x48, 0xA0, 0xE8, 8060 0x0B, 0x48, 0xA0, 0xE8,
80610x1B, 0x58, 0xA0, 0xE8, 8061 0x1B, 0x58, 0xA0, 0xE8,
8062 8062
80630x2B, 0x68, 0xA0, 0xE8, 8063 0x2B, 0x68, 0xA0, 0xE8,
80640x0C, 0x49, 0xA0, 0xE8, 8064 0x0C, 0x49, 0xA0, 0xE8,
8065 8065
80660x1C, 0x59, 0xA0, 0xE8, 8066 0x1C, 0x59, 0xA0, 0xE8,
80670x2C, 0x69, 0xA0, 0xE8, 8067 0x2C, 0x69, 0xA0, 0xE8,
8068 8068
80690x0B, 0x00, 8069 0x0B, 0x00,
80700x1B, 0x00, 8070 0x1B, 0x00,
80710x2B, 0x00, 8071 0x2B, 0x00,
80720x00, 0xE0, 8072 0x00, 0xE0,
8073 8073
80740x0C, 0x00, 8074 0x0C, 0x00,
80750x1C, 0x00, 8075 0x1C, 0x00,
80760x2C, 0x00, 8076 0x2C, 0x00,
80770x00, 0xE0, 8077 0x00, 0xE0,
8078 8078
80790x0B, 0x65, 8079 0x0B, 0x65,
80800x1B, 0x65, 8080 0x1B, 0x65,
80810x2B, 0x65, 8081 0x2B, 0x65,
80820x00, 0xE0, 8082 0x00, 0xE0,
8083 8083
80840x0C, 0x65, 8084 0x0C, 0x65,
80850x1C, 0x65, 8085 0x1C, 0x65,
80860x2C, 0x65, 8086 0x2C, 0x65,
80870x00, 0xE0, 8087 0x00, 0xE0,
8088 8088
80890x0B, 0x1B, 0x60, 0xEC, 8089 0x0B, 0x1B, 0x60, 0xEC,
80900x34, 0xD7, 0x34, 0xAD, 8090 0x34, 0xD7, 0x34, 0xAD,
8091 8091
80920x2B, 0x80, 0x60, 0xEC, 8092 0x2B, 0x80, 0x60, 0xEC,
80930x0C, 0x1C, 0x60, 0xEC, 8093 0x0C, 0x1C, 0x60, 0xEC,
8094 8094
80950x3C, 0xD7, 0x3C, 0xAD, 8095 0x3C, 0xD7, 0x3C, 0xAD,
80960x2C, 0x80, 0x60, 0xEC, 8096 0x2C, 0x80, 0x60, 0xEC,
8097 8097
80980x0B, 0x2B, 0xDE, 0xE8, 8098 0x0B, 0x2B, 0xDE, 0xE8,
80990x1B, 0x80, 0xDE, 0xE8, 8099 0x1B, 0x80, 0xDE, 0xE8,
8100 8100
81010x34, 0x80, 0x34, 0xBD, 8101 0x34, 0x80, 0x34, 0xBD,
81020x3C, 0x80, 0x3C, 0xBD, 8102 0x3C, 0x80, 0x3C, 0xBD,
8103 8103
81040x33, 0xD7, 0x0B, 0xBD, 8104 0x33, 0xD7, 0x0B, 0xBD,
81050x3B, 0xD7, 0x1B, 0xBD, 8105 0x3B, 0xD7, 0x1B, 0xBD,
8106 8106
81070x48, 0x80, 0x48, 0xCF, 8107 0x48, 0x80, 0x48, 0xCF,
81080x59, 0x80, 0x59, 0xCF, 8108 0x59, 0x80, 0x59, 0xCF,
8109 8109
81100x68, 0x33, 0x68, 0xCF, 8110 0x68, 0x33, 0x68, 0xCF,
81110x49, 0x3B, 0x49, 0xCF, 8111 0x49, 0x3B, 0x49, 0xCF,
8112 8112
81130xA9, 0xFF, 0x20, 0xEA, 8113 0xA9, 0xFF, 0x20, 0xEA,
81140x00, 0x80, 0x00, 0xE8, 8114 0x00, 0x80, 0x00, 0xE8,
8115 8115
81160x58, 0x33, 0x58, 0xCF, 8116 0x58, 0x33, 0x58, 0xCF,
81170x69, 0x3B, 0x69, 0xCF, 8117 0x69, 0x3B, 0x69, 0xCF,
8118 8118
81190x67, 0xFF, 0x20, 0xEA, 8119 0x67, 0xFF, 0x20, 0xEA,
81200x57, 0xC0, 0xBF, 0xEA, 8120 0x57, 0xC0, 0xBF, 0xEA,
8121 8121
81220x00, 0x80, 0xA0, 0xE9, 8122 0x00, 0x80, 0xA0, 0xE9,
81230x00, 0x00, 0xD8, 0xEC, 8123 0x00, 0x00, 0xD8, 0xEC,
8124 8124
8125}; 8125};
8126 8126
8127static unsigned char warp_g400_t2gzsf[] = { 8127static unsigned char warp_g400_t2gzsf[] = {
8128 8128
81290x00, 0x8A, 0x98, 0xE9, 8129 0x00, 0x8A, 0x98, 0xE9,
81300x00, 0x80, 0x00, 0xE8, 8130 0x00, 0x80, 0x00, 0xE8,
8131 8131
81320x00, 0x80, 0xA0, 0xE9, 8132 0x00, 0x80, 0xA0, 0xE9,
81330x00, 0x00, 0xD8, 0xEC, 8133 0x00, 0x00, 0xD8, 0xEC,
8134 8134
81350xFF, 0x80, 0xC0, 0xE9, 8135 0xFF, 0x80, 0xC0, 0xE9,
81360x00, 0x80, 0x00, 0xE8, 8136 0x00, 0x80, 0x00, 0xE8,
8137 8137
81380x0A, 0x40, 0x50, 0xBF, 8138 0x0A, 0x40, 0x50, 0xBF,
81390x2A, 0x40, 0x60, 0xBF, 8139 0x2A, 0x40, 0x60, 0xBF,
8140 8140
81410x32, 0x41, 0x51, 0xBF, 8141 0x32, 0x41, 0x51, 0xBF,
81420x3A, 0x41, 0x61, 0xBF, 8142 0x3A, 0x41, 0x61, 0xBF,
8143 8143
81440xC3, 0x6B, 8144 0xC3, 0x6B,
81450xD3, 0x6B, 8145 0xD3, 0x6B,
81460x00, 0x8A, 0x98, 0xE9, 8146 0x00, 0x8A, 0x98, 0xE9,
8147 8147
81480x73, 0x7B, 0xC8, 0xEC, 8148 0x73, 0x7B, 0xC8, 0xEC,
81490x96, 0xE2, 8149 0x96, 0xE2,
81500x41, 0x04, 8150 0x41, 0x04,
8151 8151
81520x7B, 0x43, 0xA0, 0xE8, 8152 0x7B, 0x43, 0xA0, 0xE8,
81530x73, 0x53, 0xA0, 0xE8, 8153 0x73, 0x53, 0xA0, 0xE8,
8154 8154
81550xAD, 0xEE, 0x23, 0x9F, 8155 0xAD, 0xEE, 0x23, 0x9F,
81560x00, 0xE0, 8156 0x00, 0xE0,
81570x51, 0x04, 8157 0x51, 0x04,
8158 8158
81590x90, 0xE2, 8159 0x90, 0xE2,
81600x61, 0x04, 8160 0x61, 0x04,
81610x31, 0x46, 0xB1, 0xE8, 8161 0x31, 0x46, 0xB1, 0xE8,
8162 8162
81630x51, 0x41, 0xE0, 0xEC, 8163 0x51, 0x41, 0xE0, 0xEC,
81640x39, 0x67, 0xB1, 0xE8, 8164 0x39, 0x67, 0xB1, 0xE8,
8165 8165
81660x00, 0x04, 8166 0x00, 0x04,
81670x46, 0xE2, 8167 0x46, 0xE2,
81680x73, 0x63, 0xA0, 0xE8, 8168 0x73, 0x63, 0xA0, 0xE8,
8169 8169
81700x61, 0x41, 0xE0, 0xEC, 8170 0x61, 0x41, 0xE0, 0xEC,
81710x31, 0x00, 8171 0x31, 0x00,
81720x39, 0x00, 8172 0x39, 0x00,
8173 8173
81740x8A, 0x80, 0x15, 0xEA, 8174 0x8A, 0x80, 0x15, 0xEA,
81750x10, 0x04, 8175 0x10, 0x04,
81760x20, 0x04, 8176 0x20, 0x04,
8177 8177
81780x61, 0x51, 0xE0, 0xEC, 8178 0x61, 0x51, 0xE0, 0xEC,
81790x2F, 0x41, 0x60, 0xEA, 8179 0x2F, 0x41, 0x60, 0xEA,
8180 8180
81810x31, 0x20, 8181 0x31, 0x20,
81820x39, 0x20, 8182 0x39, 0x20,
81830x1F, 0x42, 0xA0, 0xE8, 8183 0x1F, 0x42, 0xA0, 0xE8,
8184 8184
81850x2A, 0x42, 0x52, 0xBF, 8185 0x2A, 0x42, 0x52, 0xBF,
81860x0F, 0x52, 0xA0, 0xE8, 8186 0x0F, 0x52, 0xA0, 0xE8,
8187 8187
81880x1A, 0x42, 0x62, 0xBF, 8188 0x1A, 0x42, 0x62, 0xBF,
81890x1E, 0x51, 0x60, 0xEA, 8189 0x1E, 0x51, 0x60, 0xEA,
8190 8190
81910x73, 0x7B, 0xC8, 0xEC, 8191 0x73, 0x7B, 0xC8, 0xEC,
81920x0E, 0x61, 0x60, 0xEA, 8192 0x0E, 0x61, 0x60, 0xEA,
8193 8193
81940x32, 0x40, 0x50, 0xBD, 8194 0x32, 0x40, 0x50, 0xBD,
81950x22, 0x40, 0x60, 0xBD, 8195 0x22, 0x40, 0x60, 0xBD,
8196 8196
81970x12, 0x41, 0x51, 0xBD, 8197 0x12, 0x41, 0x51, 0xBD,
81980x3A, 0x41, 0x61, 0xBD, 8198 0x3A, 0x41, 0x61, 0xBD,
8199 8199
82000xBF, 0x2F, 0x0E, 0xBD, 8200 0xBF, 0x2F, 0x0E, 0xBD,
82010x97, 0xE2, 8201 0x97, 0xE2,
82020x7B, 0x72, 8202 0x7B, 0x72,
8203 8203
82040x32, 0x20, 8204 0x32, 0x20,
82050x22, 0x20, 8205 0x22, 0x20,
82060x12, 0x20, 8206 0x12, 0x20,
82070x3A, 0x20, 8207 0x3A, 0x20,
8208 8208
82090x35, 0x48, 0xB1, 0xE8, 8209 0x35, 0x48, 0xB1, 0xE8,
82100x3D, 0x59, 0xB1, 0xE8, 8210 0x3D, 0x59, 0xB1, 0xE8,
8211 8211
82120x46, 0x31, 0x46, 0xBF, 8212 0x46, 0x31, 0x46, 0xBF,
82130x56, 0x31, 0x56, 0xBF, 8213 0x56, 0x31, 0x56, 0xBF,
8214 8214
82150xB3, 0xE2, 0x2D, 0x9F, 8215 0xB3, 0xE2, 0x2D, 0x9F,
82160x00, 0x80, 0x00, 0xE8, 8216 0x00, 0x80, 0x00, 0xE8,
8217 8217
82180x66, 0x31, 0x66, 0xBF, 8218 0x66, 0x31, 0x66, 0xBF,
82190x47, 0x39, 0x47, 0xBF, 8219 0x47, 0x39, 0x47, 0xBF,
8220 8220
82210x57, 0x39, 0x57, 0xBF, 8221 0x57, 0x39, 0x57, 0xBF,
82220x67, 0x39, 0x67, 0xBF, 8222 0x67, 0x39, 0x67, 0xBF,
8223 8223
82240x7B, 0x80, 0x07, 0xEA, 8224 0x7B, 0x80, 0x07, 0xEA,
82250x24, 0x41, 0x20, 0xE9, 8225 0x24, 0x41, 0x20, 0xE9,
8226 8226
82270x35, 0x00, 8227 0x35, 0x00,
82280x3D, 0x00, 8228 0x3D, 0x00,
82290x00, 0xE0, 8229 0x00, 0xE0,
82300x2D, 0x73, 8230 0x2D, 0x73,
8231 8231
82320x33, 0x72, 8232 0x33, 0x72,
82330x0C, 0xE3, 8233 0x0C, 0xE3,
82340x8D, 0x2F, 0x1E, 0xBD, 8234 0x8D, 0x2F, 0x1E, 0xBD,
8235 8235
82360x43, 0x75, 0xF8, 0xEC, 8236 0x43, 0x75, 0xF8, 0xEC,
82370x35, 0x20, 8237 0x35, 0x20,
82380x3D, 0x20, 8238 0x3D, 0x20,
8239 8239
82400x43, 0x43, 0x2D, 0xDF, 8240 0x43, 0x43, 0x2D, 0xDF,
82410x53, 0x53, 0x2D, 0xDF, 8241 0x53, 0x53, 0x2D, 0xDF,
8242 8242
82430xAE, 0x1E, 0x0E, 0xBD, 8243 0xAE, 0x1E, 0x0E, 0xBD,
82440x58, 0xE3, 8244 0x58, 0xE3,
82450x33, 0x66, 8245 0x33, 0x66,
8246 8246
82470x48, 0x35, 0x48, 0xBF, 8247 0x48, 0x35, 0x48, 0xBF,
82480x58, 0x35, 0x58, 0xBF, 8248 0x58, 0x35, 0x58, 0xBF,
8249 8249
82500x68, 0x35, 0x68, 0xBF, 8250 0x68, 0x35, 0x68, 0xBF,
82510x49, 0x3D, 0x49, 0xBF, 8251 0x49, 0x3D, 0x49, 0xBF,
8252 8252
82530x59, 0x3D, 0x59, 0xBF, 8253 0x59, 0x3D, 0x59, 0xBF,
82540x69, 0x3D, 0x69, 0xBF, 8254 0x69, 0x3D, 0x69, 0xBF,
8255 8255
82560x63, 0x63, 0x2D, 0xDF, 8256 0x63, 0x63, 0x2D, 0xDF,
82570x4D, 0x7D, 0xF8, 0xEC, 8257 0x4D, 0x7D, 0xF8, 0xEC,
8258 8258
82590x59, 0xE3, 8259 0x59, 0xE3,
82600x00, 0xE0, 8260 0x00, 0xE0,
82610xB8, 0x38, 0x33, 0xBF, 8261 0xB8, 0x38, 0x33, 0xBF,
8262 8262
82630x2D, 0x73, 8263 0x2D, 0x73,
82640x30, 0x76, 8264 0x30, 0x76,
82650x18, 0x3A, 0x41, 0xE9, 8265 0x18, 0x3A, 0x41, 0xE9,
8266 8266
82670x3F, 0x53, 0xA0, 0xE8, 8267 0x3F, 0x53, 0xA0, 0xE8,
82680x05, 0x80, 0x3D, 0xEA, 8268 0x05, 0x80, 0x3D, 0xEA,
8269 8269
82700x37, 0x43, 0xA0, 0xE8, 8270 0x37, 0x43, 0xA0, 0xE8,
82710x3D, 0x63, 0xA0, 0xE8, 8271 0x3D, 0x63, 0xA0, 0xE8,
8272 8272
82730x50, 0x70, 0xF8, 0xEC, 8273 0x50, 0x70, 0xF8, 0xEC,
82740x2B, 0x50, 0x3C, 0xE9, 8274 0x2B, 0x50, 0x3C, 0xE9,
8275 8275
82760x1F, 0x0F, 0xBC, 0xE8, 8276 0x1F, 0x0F, 0xBC, 0xE8,
82770x00, 0x80, 0x00, 0xE8, 8277 0x00, 0x80, 0x00, 0xE8,
8278 8278
82790x59, 0x78, 0xF8, 0xEC, 8279 0x59, 0x78, 0xF8, 0xEC,
82800x00, 0x80, 0x00, 0xE8, 8280 0x00, 0x80, 0x00, 0xE8,
8281 8281
82820x15, 0xC0, 0x20, 0xE9, 8282 0x15, 0xC0, 0x20, 0xE9,
82830x15, 0xC0, 0x20, 0xE9, 8283 0x15, 0xC0, 0x20, 0xE9,
8284 8284
82850x15, 0xC0, 0x20, 0xE9, 8285 0x15, 0xC0, 0x20, 0xE9,
82860x15, 0xC0, 0x20, 0xE9, 8286 0x15, 0xC0, 0x20, 0xE9,
8287 8287
82880x1E, 0x12, 0x41, 0xE9, 8288 0x1E, 0x12, 0x41, 0xE9,
82890x1A, 0x22, 0x41, 0xE9, 8289 0x1A, 0x22, 0x41, 0xE9,
8290 8290
82910x46, 0x37, 0x46, 0xDF, 8291 0x46, 0x37, 0x46, 0xDF,
82920x56, 0x3F, 0x56, 0xDF, 8292 0x56, 0x3F, 0x56, 0xDF,
8293 8293
82940x2B, 0x40, 0x3D, 0xE9, 8294 0x2B, 0x40, 0x3D, 0xE9,
82950x66, 0x3D, 0x66, 0xDF, 8295 0x66, 0x3D, 0x66, 0xDF,
8296 8296
82970x1D, 0x32, 0x41, 0xE9, 8297 0x1D, 0x32, 0x41, 0xE9,
82980x67, 0x3D, 0x67, 0xDF, 8298 0x67, 0x3D, 0x67, 0xDF,
8299 8299
83000x47, 0x37, 0x47, 0xDF, 8300 0x47, 0x37, 0x47, 0xDF,
83010x57, 0x3F, 0x57, 0xDF, 8301 0x57, 0x3F, 0x57, 0xDF,
8302 8302
83030x2A, 0x40, 0x20, 0xE9, 8303 0x2A, 0x40, 0x20, 0xE9,
83040x59, 0x3F, 0x59, 0xDF, 8304 0x59, 0x3F, 0x59, 0xDF,
8305 8305
83060x16, 0x30, 0x20, 0xE9, 8306 0x16, 0x30, 0x20, 0xE9,
83070x69, 0x3D, 0x69, 0xDF, 8307 0x69, 0x3D, 0x69, 0xDF,
8308 8308
83090x48, 0x37, 0x48, 0xDF, 8309 0x48, 0x37, 0x48, 0xDF,
83100x58, 0x3F, 0x58, 0xDF, 8310 0x58, 0x3F, 0x58, 0xDF,
8311 8311
83120x68, 0x3D, 0x68, 0xDF, 8312 0x68, 0x3D, 0x68, 0xDF,
83130x49, 0x37, 0x49, 0xDF, 8313 0x49, 0x37, 0x49, 0xDF,
8314 8314
83150x32, 0x32, 0x2D, 0xDF, 8315 0x32, 0x32, 0x2D, 0xDF,
83160x22, 0x22, 0x2D, 0xDF, 8316 0x22, 0x22, 0x2D, 0xDF,
8317 8317
83180x12, 0x12, 0x2D, 0xDF, 8318 0x12, 0x12, 0x2D, 0xDF,
83190x3A, 0x3A, 0x2D, 0xDF, 8319 0x3A, 0x3A, 0x2D, 0xDF,
8320 8320
83210x0F, 0xCF, 0x74, 0xC2, 8321 0x0F, 0xCF, 0x74, 0xC2,
83220x37, 0xCF, 0x74, 0xC4, 8322 0x37, 0xCF, 0x74, 0xC4,
8323 8323
83240x0A, 0x44, 0x54, 0xB0, 8324 0x0A, 0x44, 0x54, 0xB0,
83250x02, 0x44, 0x64, 0xB0, 8325 0x02, 0x44, 0x64, 0xB0,
8326 8326
83270x3D, 0xCF, 0x74, 0xC0, 8327 0x3D, 0xCF, 0x74, 0xC0,
83280x34, 0x37, 0x20, 0xE9, 8328 0x34, 0x37, 0x20, 0xE9,
8329 8329
83300x31, 0x53, 0x2F, 0x9F, 8330 0x31, 0x53, 0x2F, 0x9F,
83310x38, 0x0F, 0x20, 0xE9, 8331 0x38, 0x0F, 0x20, 0xE9,
8332 8332
83330x39, 0xE5, 0x2C, 0x9F, 8333 0x39, 0xE5, 0x2C, 0x9F,
83340x3C, 0x3D, 0x20, 0xE9, 8334 0x3C, 0x3D, 0x20, 0xE9,
8335 8335
83360x2A, 0x44, 0x54, 0xB2, 8336 0x2A, 0x44, 0x54, 0xB2,
83370x1A, 0x44, 0x64, 0xB2, 8337 0x1A, 0x44, 0x64, 0xB2,
8338 8338
83390x36, 0x80, 0x3A, 0xEA, 8339 0x36, 0x80, 0x3A, 0xEA,
83400x0A, 0x20, 8340 0x0A, 0x20,
83410x02, 0x20, 8341 0x02, 0x20,
8342 8342
83430x0F, 0xCF, 0x75, 0xC0, 8343 0x0F, 0xCF, 0x75, 0xC0,
83440x2A, 0x20, 8344 0x2A, 0x20,
83450x1A, 0x20, 8345 0x1A, 0x20,
8346 8346
83470x30, 0x50, 0x2E, 0x9F, 8347 0x30, 0x50, 0x2E, 0x9F,
83480x32, 0x31, 0x5F, 0xE9, 8348 0x32, 0x31, 0x5F, 0xE9,
8349 8349
83500x38, 0x21, 0x2C, 0x9F, 8350 0x38, 0x21, 0x2C, 0x9F,
83510x33, 0x39, 0x5F, 0xE9, 8351 0x33, 0x39, 0x5F, 0xE9,
8352 8352
83530x3D, 0xCF, 0x75, 0xC2, 8353 0x3D, 0xCF, 0x75, 0xC2,
83540x37, 0xCF, 0x75, 0xC4, 8354 0x37, 0xCF, 0x75, 0xC4,
8355 8355
83560x31, 0x53, 0x2F, 0x9F, 8356 0x31, 0x53, 0x2F, 0x9F,
83570xA6, 0x0F, 0x20, 0xE9, 8357 0xA6, 0x0F, 0x20, 0xE9,
8358 8358
83590x39, 0xE5, 0x2C, 0x9F, 8359 0x39, 0xE5, 0x2C, 0x9F,
83600xA3, 0x3D, 0x20, 0xE9, 8360 0xA3, 0x3D, 0x20, 0xE9,
8361 8361
83620x2A, 0x44, 0x54, 0xB4, 8362 0x2A, 0x44, 0x54, 0xB4,
83630x1A, 0x44, 0x64, 0xB4, 8363 0x1A, 0x44, 0x64, 0xB4,
8364 8364
83650x0A, 0x45, 0x55, 0xB0, 8365 0x0A, 0x45, 0x55, 0xB0,
83660x02, 0x45, 0x65, 0xB0, 8366 0x02, 0x45, 0x65, 0xB0,
8367 8367
83680x88, 0x73, 0x5E, 0xE9, 8368 0x88, 0x73, 0x5E, 0xE9,
83690x2A, 0x20, 8369 0x2A, 0x20,
83700x1A, 0x20, 8370 0x1A, 0x20,
8371 8371
83720xA0, 0x37, 0x20, 0xE9, 8372 0xA0, 0x37, 0x20, 0xE9,
83730x0A, 0x20, 8373 0x0A, 0x20,
83740x02, 0x20, 8374 0x02, 0x20,
8375 8375
83760x31, 0x53, 0x2F, 0x9F, 8376 0x31, 0x53, 0x2F, 0x9F,
83770x3E, 0x30, 0x4F, 0xE9, 8377 0x3E, 0x30, 0x4F, 0xE9,
8378 8378
83790x39, 0xE5, 0x2C, 0x9F, 8379 0x39, 0xE5, 0x2C, 0x9F,
83800x3F, 0x38, 0x4F, 0xE9, 8380 0x3F, 0x38, 0x4F, 0xE9,
8381 8381
83820x30, 0x50, 0x2E, 0x9F, 8382 0x30, 0x50, 0x2E, 0x9F,
83830x3A, 0x31, 0x4F, 0xE9, 8383 0x3A, 0x31, 0x4F, 0xE9,
8384 8384
83850x38, 0x21, 0x2C, 0x9F, 8385 0x38, 0x21, 0x2C, 0x9F,
83860x3B, 0x39, 0x4F, 0xE9, 8386 0x3B, 0x39, 0x4F, 0xE9,
8387 8387
83880x2A, 0x45, 0x55, 0xB2, 8388 0x2A, 0x45, 0x55, 0xB2,
83890x1A, 0x45, 0x65, 0xB2, 8389 0x1A, 0x45, 0x65, 0xB2,
8390 8390
83910x0A, 0x45, 0x55, 0xB4, 8391 0x0A, 0x45, 0x55, 0xB4,
83920x02, 0x45, 0x65, 0xB4, 8392 0x02, 0x45, 0x65, 0xB4,
8393 8393
83940x0F, 0xCF, 0x75, 0xC6, 8394 0x0F, 0xCF, 0x75, 0xC6,
83950x2A, 0x20, 8395 0x2A, 0x20,
83960x1A, 0x20, 8396 0x1A, 0x20,
8397 8397
83980xA7, 0x30, 0x4F, 0xE9, 8398 0xA7, 0x30, 0x4F, 0xE9,
83990x0A, 0x20, 8399 0x0A, 0x20,
84000x02, 0x20, 8400 0x02, 0x20,
8401 8401
84020x31, 0x53, 0x2F, 0x9F, 8402 0x31, 0x53, 0x2F, 0x9F,
84030x31, 0x0F, 0x20, 0xE9, 8403 0x31, 0x0F, 0x20, 0xE9,
8404 8404
84050x39, 0xE5, 0x2C, 0x9F, 8405 0x39, 0xE5, 0x2C, 0x9F,
84060xA8, 0x38, 0x4F, 0xE9, 8406 0xA8, 0x38, 0x4F, 0xE9,
8407 8407
84080x2A, 0x45, 0x55, 0xB6, 8408 0x2A, 0x45, 0x55, 0xB6,
84090x1A, 0x45, 0x65, 0xB6, 8409 0x1A, 0x45, 0x65, 0xB6,
8410 8410
84110x30, 0x50, 0x2E, 0x9F, 8411 0x30, 0x50, 0x2E, 0x9F,
84120x36, 0x31, 0x4F, 0xE9, 8412 0x36, 0x31, 0x4F, 0xE9,
8413 8413
84140x38, 0x21, 0x2C, 0x9F, 8414 0x38, 0x21, 0x2C, 0x9F,
84150x37, 0x39, 0x4F, 0xE9, 8415 0x37, 0x39, 0x4F, 0xE9,
8416 8416
84170x00, 0x80, 0x00, 0xE8, 8417 0x00, 0x80, 0x00, 0xE8,
84180x2A, 0x20, 8418 0x2A, 0x20,
84190x1A, 0x20, 8419 0x1A, 0x20,
8420 8420
84210x2A, 0x46, 0x56, 0xBF, 8421 0x2A, 0x46, 0x56, 0xBF,
84220x1A, 0x46, 0x66, 0xBF, 8422 0x1A, 0x46, 0x66, 0xBF,
8423 8423
84240x31, 0x53, 0x2F, 0x9F, 8424 0x31, 0x53, 0x2F, 0x9F,
84250xA4, 0x31, 0x4F, 0xE9, 8425 0xA4, 0x31, 0x4F, 0xE9,
8426 8426
84270x39, 0xE5, 0x2C, 0x9F, 8427 0x39, 0xE5, 0x2C, 0x9F,
84280xA5, 0x39, 0x4F, 0xE9, 8428 0xA5, 0x39, 0x4F, 0xE9,
8429 8429
84300x0A, 0x47, 0x57, 0xBF, 8430 0x0A, 0x47, 0x57, 0xBF,
84310x02, 0x47, 0x67, 0xBF, 8431 0x02, 0x47, 0x67, 0xBF,
8432 8432
84330x31, 0x53, 0x2F, 0x9F, 8433 0x31, 0x53, 0x2F, 0x9F,
84340xA1, 0x30, 0x4F, 0xE9, 8434 0xA1, 0x30, 0x4F, 0xE9,
8435 8435
84360x39, 0xE5, 0x2C, 0x9F, 8436 0x39, 0xE5, 0x2C, 0x9F,
84370xA2, 0x38, 0x4F, 0xE9, 8437 0xA2, 0x38, 0x4F, 0xE9,
8438 8438
84390x2A, 0x43, 0x53, 0xBF, 8439 0x2A, 0x43, 0x53, 0xBF,
84400x1A, 0x43, 0x63, 0xBF, 8440 0x1A, 0x43, 0x63, 0xBF,
8441 8441
84420x30, 0x50, 0x2E, 0x9F, 8442 0x30, 0x50, 0x2E, 0x9F,
84430x35, 0x31, 0x4F, 0xE9, 8443 0x35, 0x31, 0x4F, 0xE9,
8444 8444
84450x38, 0x21, 0x2C, 0x9F, 8445 0x38, 0x21, 0x2C, 0x9F,
84460x39, 0x39, 0x4F, 0xE9, 8446 0x39, 0x39, 0x4F, 0xE9,
8447 8447
84480x0A, 0x48, 0x58, 0xBF, 8448 0x0A, 0x48, 0x58, 0xBF,
84490x02, 0x48, 0x68, 0xBF, 8449 0x02, 0x48, 0x68, 0xBF,
8450 8450
84510x31, 0x53, 0x2F, 0x9F, 8451 0x31, 0x53, 0x2F, 0x9F,
84520x80, 0x31, 0x57, 0xE9, 8452 0x80, 0x31, 0x57, 0xE9,
8453 8453
84540x39, 0xE5, 0x2C, 0x9F, 8454 0x39, 0xE5, 0x2C, 0x9F,
84550x81, 0x39, 0x57, 0xE9, 8455 0x81, 0x39, 0x57, 0xE9,
8456 8456
84570x2A, 0x49, 0x59, 0xBF, 8457 0x2A, 0x49, 0x59, 0xBF,
84580x1A, 0x49, 0x69, 0xBF, 8458 0x1A, 0x49, 0x69, 0xBF,
8459 8459
84600x30, 0x50, 0x2E, 0x9F, 8460 0x30, 0x50, 0x2E, 0x9F,
84610x82, 0x30, 0x57, 0xE9, 8461 0x82, 0x30, 0x57, 0xE9,
8462 8462
84630x38, 0x21, 0x2C, 0x9F, 8463 0x38, 0x21, 0x2C, 0x9F,
84640x83, 0x38, 0x57, 0xE9, 8464 0x83, 0x38, 0x57, 0xE9,
8465 8465
84660x31, 0x53, 0x2F, 0x9F, 8466 0x31, 0x53, 0x2F, 0x9F,
84670x84, 0x31, 0x5E, 0xE9, 8467 0x84, 0x31, 0x5E, 0xE9,
8468 8468
84690x39, 0xE5, 0x2C, 0x9F, 8469 0x39, 0xE5, 0x2C, 0x9F,
84700x85, 0x39, 0x5E, 0xE9, 8470 0x85, 0x39, 0x5E, 0xE9,
8471 8471
84720x86, 0x76, 0x57, 0xE9, 8472 0x86, 0x76, 0x57, 0xE9,
84730x8A, 0x36, 0x20, 0xE9, 8473 0x8A, 0x36, 0x20, 0xE9,
8474 8474
84750x87, 0x77, 0x57, 0xE9, 8475 0x87, 0x77, 0x57, 0xE9,
84760x8B, 0x3E, 0xBF, 0xEA, 8476 0x8B, 0x3E, 0xBF, 0xEA,
8477 8477
84780x80, 0x30, 0x57, 0xE9, 8478 0x80, 0x30, 0x57, 0xE9,
84790x81, 0x38, 0x57, 0xE9, 8479 0x81, 0x38, 0x57, 0xE9,
8480 8480
84810x82, 0x31, 0x57, 0xE9, 8481 0x82, 0x31, 0x57, 0xE9,
84820x86, 0x78, 0x57, 0xE9, 8482 0x86, 0x78, 0x57, 0xE9,
8483 8483
84840x83, 0x39, 0x57, 0xE9, 8484 0x83, 0x39, 0x57, 0xE9,
84850x87, 0x79, 0x57, 0xE9, 8485 0x87, 0x79, 0x57, 0xE9,
8486 8486
84870x30, 0x1F, 0x5F, 0xE9, 8487 0x30, 0x1F, 0x5F, 0xE9,
84880x8A, 0x34, 0x20, 0xE9, 8488 0x8A, 0x34, 0x20, 0xE9,
8489 8489
84900x8B, 0x3C, 0x20, 0xE9, 8490 0x8B, 0x3C, 0x20, 0xE9,
84910x37, 0x50, 0x60, 0xBD, 8491 0x37, 0x50, 0x60, 0xBD,
8492 8492
84930x57, 0x0D, 0x20, 0xE9, 8493 0x57, 0x0D, 0x20, 0xE9,
84940x35, 0x51, 0x61, 0xBD, 8494 0x35, 0x51, 0x61, 0xBD,
8495 8495
84960x2B, 0x50, 0x20, 0xE9, 8496 0x2B, 0x50, 0x20, 0xE9,
84970x1D, 0x37, 0xE1, 0xEA, 8497 0x1D, 0x37, 0xE1, 0xEA,
8498 8498
84990x1E, 0x35, 0xE1, 0xEA, 8499 0x1E, 0x35, 0xE1, 0xEA,
85000x00, 0xE0, 8500 0x00, 0xE0,
85010x0E, 0x77, 8501 0x0E, 0x77,
8502 8502
85030x24, 0x51, 0x20, 0xE9, 8503 0x24, 0x51, 0x20, 0xE9,
85040x8D, 0xFF, 0x20, 0xEA, 8504 0x8D, 0xFF, 0x20, 0xEA,
8505 8505
85060x16, 0x0E, 0x20, 0xE9, 8506 0x16, 0x0E, 0x20, 0xE9,
85070x57, 0x2E, 0xBF, 0xEA, 8507 0x57, 0x2E, 0xBF, 0xEA,
8508 8508
85090x0B, 0x46, 0xA0, 0xE8, 8509 0x0B, 0x46, 0xA0, 0xE8,
85100x1B, 0x56, 0xA0, 0xE8, 8510 0x1B, 0x56, 0xA0, 0xE8,
8511 8511
85120x2B, 0x66, 0xA0, 0xE8, 8512 0x2B, 0x66, 0xA0, 0xE8,
85130x0C, 0x47, 0xA0, 0xE8, 8513 0x0C, 0x47, 0xA0, 0xE8,
8514 8514
85150x1C, 0x57, 0xA0, 0xE8, 8515 0x1C, 0x57, 0xA0, 0xE8,
85160x2C, 0x67, 0xA0, 0xE8, 8516 0x2C, 0x67, 0xA0, 0xE8,
8517 8517
85180x0B, 0x00, 8518 0x0B, 0x00,
85190x1B, 0x00, 8519 0x1B, 0x00,
85200x2B, 0x00, 8520 0x2B, 0x00,
85210x00, 0xE0, 8521 0x00, 0xE0,
8522 8522
85230x0C, 0x00, 8523 0x0C, 0x00,
85240x1C, 0x00, 8524 0x1C, 0x00,
85250x2C, 0x00, 8525 0x2C, 0x00,
85260x00, 0xE0, 8526 0x00, 0xE0,
8527 8527
85280x0B, 0x65, 8528 0x0B, 0x65,
85290x1B, 0x65, 8529 0x1B, 0x65,
85300x2B, 0x65, 8530 0x2B, 0x65,
85310x00, 0xE0, 8531 0x00, 0xE0,
8532 8532
85330x0C, 0x65, 8533 0x0C, 0x65,
85340x1C, 0x65, 8534 0x1C, 0x65,
85350x2C, 0x65, 8535 0x2C, 0x65,
85360x00, 0xE0, 8536 0x00, 0xE0,
8537 8537
85380x0B, 0x1B, 0x60, 0xEC, 8538 0x0B, 0x1B, 0x60, 0xEC,
85390x36, 0xD7, 0x36, 0xAD, 8539 0x36, 0xD7, 0x36, 0xAD,
8540 8540
85410x2B, 0x80, 0x60, 0xEC, 8541 0x2B, 0x80, 0x60, 0xEC,
85420x0C, 0x1C, 0x60, 0xEC, 8542 0x0C, 0x1C, 0x60, 0xEC,
8543 8543
85440x3E, 0xD7, 0x3E, 0xAD, 8544 0x3E, 0xD7, 0x3E, 0xAD,
85450x2C, 0x80, 0x60, 0xEC, 8545 0x2C, 0x80, 0x60, 0xEC,
8546 8546
85470x0B, 0x2B, 0xDE, 0xE8, 8547 0x0B, 0x2B, 0xDE, 0xE8,
85480x1B, 0x80, 0xDE, 0xE8, 8548 0x1B, 0x80, 0xDE, 0xE8,
8549 8549
85500x36, 0x80, 0x36, 0xBD, 8550 0x36, 0x80, 0x36, 0xBD,
85510x3E, 0x80, 0x3E, 0xBD, 8551 0x3E, 0x80, 0x3E, 0xBD,
8552 8552
85530x33, 0xD7, 0x0B, 0xBD, 8553 0x33, 0xD7, 0x0B, 0xBD,
85540x3B, 0xD7, 0x1B, 0xBD, 8554 0x3B, 0xD7, 0x1B, 0xBD,
8555 8555
85560x46, 0x80, 0x46, 0xCF, 8556 0x46, 0x80, 0x46, 0xCF,
85570x57, 0x80, 0x57, 0xCF, 8557 0x57, 0x80, 0x57, 0xCF,
8558 8558
85590x66, 0x33, 0x66, 0xCF, 8559 0x66, 0x33, 0x66, 0xCF,
85600x47, 0x3B, 0x47, 0xCF, 8560 0x47, 0x3B, 0x47, 0xCF,
8561 8561
85620x56, 0x33, 0x56, 0xCF, 8562 0x56, 0x33, 0x56, 0xCF,
85630x67, 0x3B, 0x67, 0xCF, 8563 0x67, 0x3B, 0x67, 0xCF,
8564 8564
85650x0B, 0x48, 0xA0, 0xE8, 8565 0x0B, 0x48, 0xA0, 0xE8,
85660x1B, 0x58, 0xA0, 0xE8, 8566 0x1B, 0x58, 0xA0, 0xE8,
8567 8567
85680x2B, 0x68, 0xA0, 0xE8, 8568 0x2B, 0x68, 0xA0, 0xE8,
85690x0C, 0x49, 0xA0, 0xE8, 8569 0x0C, 0x49, 0xA0, 0xE8,
8570 8570
85710x1C, 0x59, 0xA0, 0xE8, 8571 0x1C, 0x59, 0xA0, 0xE8,
85720x2C, 0x69, 0xA0, 0xE8, 8572 0x2C, 0x69, 0xA0, 0xE8,
8573 8573
85740x0B, 0x00, 8574 0x0B, 0x00,
85750x1B, 0x00, 8575 0x1B, 0x00,
85760x2B, 0x00, 8576 0x2B, 0x00,
85770x00, 0xE0, 8577 0x00, 0xE0,
8578 8578
85790x0C, 0x00, 8579 0x0C, 0x00,
85800x1C, 0x00, 8580 0x1C, 0x00,
85810x2C, 0x00, 8581 0x2C, 0x00,
85820x00, 0xE0, 8582 0x00, 0xE0,
8583 8583
85840x0B, 0x65, 8584 0x0B, 0x65,
85850x1B, 0x65, 8585 0x1B, 0x65,
85860x2B, 0x65, 8586 0x2B, 0x65,
85870x00, 0xE0, 8587 0x00, 0xE0,
8588 8588
85890x0C, 0x65, 8589 0x0C, 0x65,
85900x1C, 0x65, 8590 0x1C, 0x65,
85910x2C, 0x65, 8591 0x2C, 0x65,
85920x00, 0xE0, 8592 0x00, 0xE0,
8593 8593
85940x0B, 0x1B, 0x60, 0xEC, 8594 0x0B, 0x1B, 0x60, 0xEC,
85950x34, 0xD7, 0x34, 0xAD, 8595 0x34, 0xD7, 0x34, 0xAD,
8596 8596
85970x2B, 0x80, 0x60, 0xEC, 8597 0x2B, 0x80, 0x60, 0xEC,
85980x0C, 0x1C, 0x60, 0xEC, 8598 0x0C, 0x1C, 0x60, 0xEC,
8599 8599
86000x3C, 0xD7, 0x3C, 0xAD, 8600 0x3C, 0xD7, 0x3C, 0xAD,
86010x2C, 0x80, 0x60, 0xEC, 8601 0x2C, 0x80, 0x60, 0xEC,
8602 8602
86030x0B, 0x2B, 0xDE, 0xE8, 8603 0x0B, 0x2B, 0xDE, 0xE8,
86040x1B, 0x80, 0xDE, 0xE8, 8604 0x1B, 0x80, 0xDE, 0xE8,
8605 8605
86060x34, 0x80, 0x34, 0xBD, 8606 0x34, 0x80, 0x34, 0xBD,
86070x3C, 0x80, 0x3C, 0xBD, 8607 0x3C, 0x80, 0x3C, 0xBD,
8608 8608
86090x33, 0xD7, 0x0B, 0xBD, 8609 0x33, 0xD7, 0x0B, 0xBD,
86100x3B, 0xD7, 0x1B, 0xBD, 8610 0x3B, 0xD7, 0x1B, 0xBD,
8611 8611
86120x48, 0x80, 0x48, 0xCF, 8612 0x48, 0x80, 0x48, 0xCF,
86130x59, 0x80, 0x59, 0xCF, 8613 0x59, 0x80, 0x59, 0xCF,
8614 8614
86150x68, 0x33, 0x68, 0xCF, 8615 0x68, 0x33, 0x68, 0xCF,
86160x49, 0x3B, 0x49, 0xCF, 8616 0x49, 0x3B, 0x49, 0xCF,
8617 8617
86180xAD, 0xFF, 0x20, 0xEA, 8618 0xAD, 0xFF, 0x20, 0xEA,
86190x00, 0x80, 0x00, 0xE8, 8619 0x00, 0x80, 0x00, 0xE8,
8620 8620
86210x58, 0x33, 0x58, 0xCF, 8621 0x58, 0x33, 0x58, 0xCF,
86220x69, 0x3B, 0x69, 0xCF, 8622 0x69, 0x3B, 0x69, 0xCF,
8623 8623
86240x6B, 0xFF, 0x20, 0xEA, 8624 0x6B, 0xFF, 0x20, 0xEA,
86250x57, 0xC0, 0xBF, 0xEA, 8625 0x57, 0xC0, 0xBF, 0xEA,
8626 8626
86270x00, 0x80, 0xA0, 0xE9, 8627 0x00, 0x80, 0xA0, 0xE9,
86280x00, 0x00, 0xD8, 0xEC, 8628 0x00, 0x00, 0xD8, 0xEC,
8629 8629
8630}; 8630};
8631 8631
8632static unsigned char warp_g400_tgz[] = { 8632static unsigned char warp_g400_tgz[] = {
8633 8633
86340x00, 0x88, 0x98, 0xE9, 8634 0x00, 0x88, 0x98, 0xE9,
86350x00, 0x80, 0x00, 0xE8, 8635 0x00, 0x80, 0x00, 0xE8,
8636 8636
86370x00, 0x80, 0xA0, 0xE9, 8637 0x00, 0x80, 0xA0, 0xE9,
86380x00, 0x00, 0xD8, 0xEC, 8638 0x00, 0x00, 0xD8, 0xEC,
8639 8639
86400xFF, 0x80, 0xC0, 0xE9, 8640 0xFF, 0x80, 0xC0, 0xE9,
86410x00, 0x80, 0x00, 0xE8, 8641 0x00, 0x80, 0x00, 0xE8,
8642 8642
86430x22, 0x40, 0x48, 0xBF, 8643 0x22, 0x40, 0x48, 0xBF,
86440x2A, 0x40, 0x50, 0xBF, 8644 0x2A, 0x40, 0x50, 0xBF,
8645 8645
86460x32, 0x41, 0x49, 0xBF, 8646 0x32, 0x41, 0x49, 0xBF,
86470x3A, 0x41, 0x51, 0xBF, 8647 0x3A, 0x41, 0x51, 0xBF,
8648 8648
86490xC3, 0x6B, 8649 0xC3, 0x6B,
86500xCB, 0x6B, 8650 0xCB, 0x6B,
86510x00, 0x88, 0x98, 0xE9, 8651 0x00, 0x88, 0x98, 0xE9,
8652 8652
86530x73, 0x7B, 0xC8, 0xEC, 8653 0x73, 0x7B, 0xC8, 0xEC,
86540x96, 0xE2, 8654 0x96, 0xE2,
86550x41, 0x04, 8655 0x41, 0x04,
8656 8656
86570x7B, 0x43, 0xA0, 0xE8, 8657 0x7B, 0x43, 0xA0, 0xE8,
86580x73, 0x4B, 0xA0, 0xE8, 8658 0x73, 0x4B, 0xA0, 0xE8,
8659 8659
86600xAD, 0xEE, 0x29, 0x9F, 8660 0xAD, 0xEE, 0x29, 0x9F,
86610x00, 0xE0, 8661 0x00, 0xE0,
86620x49, 0x04, 8662 0x49, 0x04,
8663 8663
86640x90, 0xE2, 8664 0x90, 0xE2,
86650x51, 0x04, 8665 0x51, 0x04,
86660x31, 0x46, 0xB1, 0xE8, 8666 0x31, 0x46, 0xB1, 0xE8,
8667 8667
86680x49, 0x41, 0xC0, 0xEC, 8668 0x49, 0x41, 0xC0, 0xEC,
86690x39, 0x57, 0xB1, 0xE8, 8669 0x39, 0x57, 0xB1, 0xE8,
8670 8670
86710x00, 0x04, 8671 0x00, 0x04,
86720x46, 0xE2, 8672 0x46, 0xE2,
86730x73, 0x53, 0xA0, 0xE8, 8673 0x73, 0x53, 0xA0, 0xE8,
8674 8674
86750x51, 0x41, 0xC0, 0xEC, 8675 0x51, 0x41, 0xC0, 0xEC,
86760x31, 0x00, 8676 0x31, 0x00,
86770x39, 0x00, 8677 0x39, 0x00,
8678 8678
86790x58, 0x80, 0x15, 0xEA, 8679 0x58, 0x80, 0x15, 0xEA,
86800x08, 0x04, 8680 0x08, 0x04,
86810x10, 0x04, 8681 0x10, 0x04,
8682 8682
86830x51, 0x49, 0xC0, 0xEC, 8683 0x51, 0x49, 0xC0, 0xEC,
86840x2F, 0x41, 0x60, 0xEA, 8684 0x2F, 0x41, 0x60, 0xEA,
8685 8685
86860x31, 0x20, 8686 0x31, 0x20,
86870x39, 0x20, 8687 0x39, 0x20,
86880x1F, 0x42, 0xA0, 0xE8, 8688 0x1F, 0x42, 0xA0, 0xE8,
8689 8689
86900x2A, 0x42, 0x4A, 0xBF, 8690 0x2A, 0x42, 0x4A, 0xBF,
86910x27, 0x4A, 0xA0, 0xE8, 8691 0x27, 0x4A, 0xA0, 0xE8,
8692 8692
86930x1A, 0x42, 0x52, 0xBF, 8693 0x1A, 0x42, 0x52, 0xBF,
86940x1E, 0x49, 0x60, 0xEA, 8694 0x1E, 0x49, 0x60, 0xEA,
8695 8695
86960x73, 0x7B, 0xC8, 0xEC, 8696 0x73, 0x7B, 0xC8, 0xEC,
86970x26, 0x51, 0x60, 0xEA, 8697 0x26, 0x51, 0x60, 0xEA,
8698 8698
86990x32, 0x40, 0x48, 0xBD, 8699 0x32, 0x40, 0x48, 0xBD,
87000x22, 0x40, 0x50, 0xBD, 8700 0x22, 0x40, 0x50, 0xBD,
8701 8701
87020x12, 0x41, 0x49, 0xBD, 8702 0x12, 0x41, 0x49, 0xBD,
87030x3A, 0x41, 0x51, 0xBD, 8703 0x3A, 0x41, 0x51, 0xBD,
8704 8704
87050xBF, 0x2F, 0x26, 0xBD, 8705 0xBF, 0x2F, 0x26, 0xBD,
87060x00, 0xE0, 8706 0x00, 0xE0,
87070x7B, 0x72, 8707 0x7B, 0x72,
8708 8708
87090x32, 0x20, 8709 0x32, 0x20,
87100x22, 0x20, 8710 0x22, 0x20,
87110x12, 0x20, 8711 0x12, 0x20,
87120x3A, 0x20, 8712 0x3A, 0x20,
8713 8713
87140x46, 0x31, 0x46, 0xBF, 8714 0x46, 0x31, 0x46, 0xBF,
87150x4E, 0x31, 0x4E, 0xBF, 8715 0x4E, 0x31, 0x4E, 0xBF,
8716 8716
87170xB3, 0xE2, 0x2D, 0x9F, 8717 0xB3, 0xE2, 0x2D, 0x9F,
87180x00, 0x80, 0x00, 0xE8, 8718 0x00, 0x80, 0x00, 0xE8,
8719 8719
87200x56, 0x31, 0x56, 0xBF, 8720 0x56, 0x31, 0x56, 0xBF,
87210x47, 0x39, 0x47, 0xBF, 8721 0x47, 0x39, 0x47, 0xBF,
8722 8722
87230x4F, 0x39, 0x4F, 0xBF, 8723 0x4F, 0x39, 0x4F, 0xBF,
87240x57, 0x39, 0x57, 0xBF, 8724 0x57, 0x39, 0x57, 0xBF,
8725 8725
87260x4A, 0x80, 0x07, 0xEA, 8726 0x4A, 0x80, 0x07, 0xEA,
87270x24, 0x41, 0x20, 0xE9, 8727 0x24, 0x41, 0x20, 0xE9,
8728 8728
87290x42, 0x73, 0xF8, 0xEC, 8729 0x42, 0x73, 0xF8, 0xEC,
87300x00, 0xE0, 8730 0x00, 0xE0,
87310x2D, 0x73, 8731 0x2D, 0x73,
8732 8732
87330x33, 0x72, 8733 0x33, 0x72,
87340x0C, 0xE3, 8734 0x0C, 0xE3,
87350xA5, 0x2F, 0x1E, 0xBD, 8735 0xA5, 0x2F, 0x1E, 0xBD,
8736 8736
87370x43, 0x43, 0x2D, 0xDF, 8737 0x43, 0x43, 0x2D, 0xDF,
87380x4B, 0x4B, 0x2D, 0xDF, 8738 0x4B, 0x4B, 0x2D, 0xDF,
8739 8739
87400xAE, 0x1E, 0x26, 0xBD, 8740 0xAE, 0x1E, 0x26, 0xBD,
87410x58, 0xE3, 8741 0x58, 0xE3,
87420x33, 0x66, 8742 0x33, 0x66,
8743 8743
87440x53, 0x53, 0x2D, 0xDF, 8744 0x53, 0x53, 0x2D, 0xDF,
87450x00, 0x80, 0x00, 0xE8, 8745 0x00, 0x80, 0x00, 0xE8,
8746 8746
87470xB8, 0x38, 0x33, 0xBF, 8747 0xB8, 0x38, 0x33, 0xBF,
87480x00, 0xE0, 8748 0x00, 0xE0,
87490x59, 0xE3, 8749 0x59, 0xE3,
8750 8750
87510x1E, 0x12, 0x41, 0xE9, 8751 0x1E, 0x12, 0x41, 0xE9,
87520x1A, 0x22, 0x41, 0xE9, 8752 0x1A, 0x22, 0x41, 0xE9,
8753 8753
87540x2B, 0x40, 0x3D, 0xE9, 8754 0x2B, 0x40, 0x3D, 0xE9,
87550x3F, 0x4B, 0xA0, 0xE8, 8755 0x3F, 0x4B, 0xA0, 0xE8,
8756 8756
87570x2D, 0x73, 8757 0x2D, 0x73,
87580x30, 0x76, 8758 0x30, 0x76,
87590x05, 0x80, 0x3D, 0xEA, 8759 0x05, 0x80, 0x3D, 0xEA,
8760 8760
87610x37, 0x43, 0xA0, 0xE8, 8761 0x37, 0x43, 0xA0, 0xE8,
87620x3D, 0x53, 0xA0, 0xE8, 8762 0x3D, 0x53, 0xA0, 0xE8,
8763 8763
87640x48, 0x70, 0xF8, 0xEC, 8764 0x48, 0x70, 0xF8, 0xEC,
87650x2B, 0x48, 0x3C, 0xE9, 8765 0x2B, 0x48, 0x3C, 0xE9,
8766 8766
87670x1F, 0x27, 0xBC, 0xE8, 8767 0x1F, 0x27, 0xBC, 0xE8,
87680x00, 0x80, 0x00, 0xE8, 8768 0x00, 0x80, 0x00, 0xE8,
8769 8769
87700x00, 0x80, 0x00, 0xE8, 8770 0x00, 0x80, 0x00, 0xE8,
87710x00, 0x80, 0x00, 0xE8, 8771 0x00, 0x80, 0x00, 0xE8,
8772 8772
87730x15, 0xC0, 0x20, 0xE9, 8773 0x15, 0xC0, 0x20, 0xE9,
87740x15, 0xC0, 0x20, 0xE9, 8774 0x15, 0xC0, 0x20, 0xE9,
8775 8775
87760x15, 0xC0, 0x20, 0xE9, 8776 0x15, 0xC0, 0x20, 0xE9,
87770x15, 0xC0, 0x20, 0xE9, 8777 0x15, 0xC0, 0x20, 0xE9,
8778 8778
87790x18, 0x3A, 0x41, 0xE9, 8779 0x18, 0x3A, 0x41, 0xE9,
87800x1D, 0x32, 0x41, 0xE9, 8780 0x1D, 0x32, 0x41, 0xE9,
8781 8781
87820x2A, 0x40, 0x20, 0xE9, 8782 0x2A, 0x40, 0x20, 0xE9,
87830x56, 0x3D, 0x56, 0xDF, 8783 0x56, 0x3D, 0x56, 0xDF,
8784 8784
87850x46, 0x37, 0x46, 0xDF, 8785 0x46, 0x37, 0x46, 0xDF,
87860x4E, 0x3F, 0x4E, 0xDF, 8786 0x4E, 0x3F, 0x4E, 0xDF,
8787 8787
87880x16, 0x30, 0x20, 0xE9, 8788 0x16, 0x30, 0x20, 0xE9,
87890x4F, 0x3F, 0x4F, 0xDF, 8789 0x4F, 0x3F, 0x4F, 0xDF,
8790 8790
87910x32, 0x32, 0x2D, 0xDF, 8791 0x32, 0x32, 0x2D, 0xDF,
87920x22, 0x22, 0x2D, 0xDF, 8792 0x22, 0x22, 0x2D, 0xDF,
8793 8793
87940x12, 0x12, 0x2D, 0xDF, 8794 0x12, 0x12, 0x2D, 0xDF,
87950x3A, 0x3A, 0x2D, 0xDF, 8795 0x3A, 0x3A, 0x2D, 0xDF,
8796 8796
87970x47, 0x37, 0x47, 0xDF, 8797 0x47, 0x37, 0x47, 0xDF,
87980x57, 0x3D, 0x57, 0xDF, 8798 0x57, 0x3D, 0x57, 0xDF,
8799 8799
88000x3D, 0xCF, 0x74, 0xC0, 8800 0x3D, 0xCF, 0x74, 0xC0,
88010x37, 0xCF, 0x74, 0xC4, 8801 0x37, 0xCF, 0x74, 0xC4,
8802 8802
88030x31, 0x53, 0x2F, 0x9F, 8803 0x31, 0x53, 0x2F, 0x9F,
88040x34, 0x80, 0x20, 0xE9, 8804 0x34, 0x80, 0x20, 0xE9,
8805 8805
88060x39, 0xE5, 0x2C, 0x9F, 8806 0x39, 0xE5, 0x2C, 0x9F,
88070x3C, 0x3D, 0x20, 0xE9, 8807 0x3C, 0x3D, 0x20, 0xE9,
8808 8808
88090x0A, 0x44, 0x4C, 0xB0, 8809 0x0A, 0x44, 0x4C, 0xB0,
88100x02, 0x44, 0x54, 0xB0, 8810 0x02, 0x44, 0x54, 0xB0,
8811 8811
88120x2A, 0x44, 0x4C, 0xB2, 8812 0x2A, 0x44, 0x4C, 0xB2,
88130x1A, 0x44, 0x54, 0xB2, 8813 0x1A, 0x44, 0x54, 0xB2,
8814 8814
88150x1D, 0x80, 0x3A, 0xEA, 8815 0x1D, 0x80, 0x3A, 0xEA,
88160x0A, 0x20, 8816 0x0A, 0x20,
88170x02, 0x20, 8817 0x02, 0x20,
8818 8818
88190x3D, 0xCF, 0x74, 0xC2, 8819 0x3D, 0xCF, 0x74, 0xC2,
88200x2A, 0x20, 8820 0x2A, 0x20,
88210x1A, 0x20, 8821 0x1A, 0x20,
8822 8822
88230x30, 0x50, 0x2E, 0x9F, 8823 0x30, 0x50, 0x2E, 0x9F,
88240x32, 0x31, 0x5F, 0xE9, 8824 0x32, 0x31, 0x5F, 0xE9,
8825 8825
88260x38, 0x21, 0x2C, 0x9F, 8826 0x38, 0x21, 0x2C, 0x9F,
88270x33, 0x39, 0x5F, 0xE9, 8827 0x33, 0x39, 0x5F, 0xE9,
8828 8828
88290x31, 0x53, 0x2F, 0x9F, 8829 0x31, 0x53, 0x2F, 0x9F,
88300x00, 0x80, 0x00, 0xE8, 8830 0x00, 0x80, 0x00, 0xE8,
8831 8831
88320x2A, 0x44, 0x4C, 0xB4, 8832 0x2A, 0x44, 0x4C, 0xB4,
88330x1A, 0x44, 0x54, 0xB4, 8833 0x1A, 0x44, 0x54, 0xB4,
8834 8834
88350x39, 0xE5, 0x2C, 0x9F, 8835 0x39, 0xE5, 0x2C, 0x9F,
88360x38, 0x3D, 0x20, 0xE9, 8836 0x38, 0x3D, 0x20, 0xE9,
8837 8837
88380x88, 0x73, 0x5E, 0xE9, 8838 0x88, 0x73, 0x5E, 0xE9,
88390x2A, 0x20, 8839 0x2A, 0x20,
88400x1A, 0x20, 8840 0x1A, 0x20,
8841 8841
88420x2A, 0x46, 0x4E, 0xBF, 8842 0x2A, 0x46, 0x4E, 0xBF,
88430x1A, 0x46, 0x56, 0xBF, 8843 0x1A, 0x46, 0x56, 0xBF,
8844 8844
88450x31, 0x53, 0x2F, 0x9F, 8845 0x31, 0x53, 0x2F, 0x9F,
88460x3E, 0x30, 0x4F, 0xE9, 8846 0x3E, 0x30, 0x4F, 0xE9,
8847 8847
88480x39, 0xE5, 0x2C, 0x9F, 8848 0x39, 0xE5, 0x2C, 0x9F,
88490x3F, 0x38, 0x4F, 0xE9, 8849 0x3F, 0x38, 0x4F, 0xE9,
8850 8850
88510x0A, 0x47, 0x4F, 0xBF, 8851 0x0A, 0x47, 0x4F, 0xBF,
88520x02, 0x47, 0x57, 0xBF, 8852 0x02, 0x47, 0x57, 0xBF,
8853 8853
88540x31, 0x53, 0x2F, 0x9F, 8854 0x31, 0x53, 0x2F, 0x9F,
88550x3A, 0x31, 0x4F, 0xE9, 8855 0x3A, 0x31, 0x4F, 0xE9,
8856 8856
88570x39, 0xE5, 0x2C, 0x9F, 8857 0x39, 0xE5, 0x2C, 0x9F,
88580x3B, 0x39, 0x4F, 0xE9, 8858 0x3B, 0x39, 0x4F, 0xE9,
8859 8859
88600x2A, 0x43, 0x4B, 0xBF, 8860 0x2A, 0x43, 0x4B, 0xBF,
88610x1A, 0x43, 0x53, 0xBF, 8861 0x1A, 0x43, 0x53, 0xBF,
8862 8862
88630x30, 0x50, 0x2E, 0x9F, 8863 0x30, 0x50, 0x2E, 0x9F,
88640x36, 0x31, 0x4F, 0xE9, 8864 0x36, 0x31, 0x4F, 0xE9,
8865 8865
88660x38, 0x21, 0x2C, 0x9F, 8866 0x38, 0x21, 0x2C, 0x9F,
88670x37, 0x39, 0x4F, 0xE9, 8867 0x37, 0x39, 0x4F, 0xE9,
8868 8868
88690x31, 0x53, 0x2F, 0x9F, 8869 0x31, 0x53, 0x2F, 0x9F,
88700x80, 0x31, 0x57, 0xE9, 8870 0x80, 0x31, 0x57, 0xE9,
8871 8871
88720x39, 0xE5, 0x2C, 0x9F, 8872 0x39, 0xE5, 0x2C, 0x9F,
88730x81, 0x39, 0x57, 0xE9, 8873 0x81, 0x39, 0x57, 0xE9,
8874 8874
88750x37, 0x48, 0x50, 0xBD, 8875 0x37, 0x48, 0x50, 0xBD,
88760x8A, 0x36, 0x20, 0xE9, 8876 0x8A, 0x36, 0x20, 0xE9,
8877 8877
88780x86, 0x76, 0x57, 0xE9, 8878 0x86, 0x76, 0x57, 0xE9,
88790x8B, 0x3E, 0x20, 0xE9, 8879 0x8B, 0x3E, 0x20, 0xE9,
8880 8880
88810x82, 0x30, 0x57, 0xE9, 8881 0x82, 0x30, 0x57, 0xE9,
88820x87, 0x77, 0x57, 0xE9, 8882 0x87, 0x77, 0x57, 0xE9,
8883 8883
88840x83, 0x38, 0x57, 0xE9, 8884 0x83, 0x38, 0x57, 0xE9,
88850x35, 0x49, 0x51, 0xBD, 8885 0x35, 0x49, 0x51, 0xBD,
8886 8886
88870x84, 0x31, 0x5E, 0xE9, 8887 0x84, 0x31, 0x5E, 0xE9,
88880x30, 0x1F, 0x5F, 0xE9, 8888 0x30, 0x1F, 0x5F, 0xE9,
8889 8889
88900x85, 0x39, 0x5E, 0xE9, 8890 0x85, 0x39, 0x5E, 0xE9,
88910x57, 0x25, 0x20, 0xE9, 8891 0x57, 0x25, 0x20, 0xE9,
8892 8892
88930x2B, 0x48, 0x20, 0xE9, 8893 0x2B, 0x48, 0x20, 0xE9,
88940x1D, 0x37, 0xE1, 0xEA, 8894 0x1D, 0x37, 0xE1, 0xEA,
8895 8895
88960x1E, 0x35, 0xE1, 0xEA, 8896 0x1E, 0x35, 0xE1, 0xEA,
88970x00, 0xE0, 8897 0x00, 0xE0,
88980x26, 0x77, 8898 0x26, 0x77,
8899 8899
89000x24, 0x49, 0x20, 0xE9, 8900 0x24, 0x49, 0x20, 0xE9,
89010xAF, 0xFF, 0x20, 0xEA, 8901 0xAF, 0xFF, 0x20, 0xEA,
8902 8902
89030x16, 0x26, 0x20, 0xE9, 8903 0x16, 0x26, 0x20, 0xE9,
89040x57, 0x2E, 0xBF, 0xEA, 8904 0x57, 0x2E, 0xBF, 0xEA,
8905 8905
89060x1C, 0x46, 0xA0, 0xE8, 8906 0x1C, 0x46, 0xA0, 0xE8,
89070x23, 0x4E, 0xA0, 0xE8, 8907 0x23, 0x4E, 0xA0, 0xE8,
8908 8908
89090x2B, 0x56, 0xA0, 0xE8, 8909 0x2B, 0x56, 0xA0, 0xE8,
89100x1D, 0x47, 0xA0, 0xE8, 8910 0x1D, 0x47, 0xA0, 0xE8,
8911 8911
89120x24, 0x4F, 0xA0, 0xE8, 8912 0x24, 0x4F, 0xA0, 0xE8,
89130x2C, 0x57, 0xA0, 0xE8, 8913 0x2C, 0x57, 0xA0, 0xE8,
8914 8914
89150x1C, 0x00, 8915 0x1C, 0x00,
89160x23, 0x00, 8916 0x23, 0x00,
89170x2B, 0x00, 8917 0x2B, 0x00,
89180x00, 0xE0, 8918 0x00, 0xE0,
8919 8919
89200x1D, 0x00, 8920 0x1D, 0x00,
89210x24, 0x00, 8921 0x24, 0x00,
89220x2C, 0x00, 8922 0x2C, 0x00,
89230x00, 0xE0, 8923 0x00, 0xE0,
8924 8924
89250x1C, 0x65, 8925 0x1C, 0x65,
89260x23, 0x65, 8926 0x23, 0x65,
89270x2B, 0x65, 8927 0x2B, 0x65,
89280x00, 0xE0, 8928 0x00, 0xE0,
8929 8929
89300x1D, 0x65, 8930 0x1D, 0x65,
89310x24, 0x65, 8931 0x24, 0x65,
89320x2C, 0x65, 8932 0x2C, 0x65,
89330x00, 0xE0, 8933 0x00, 0xE0,
8934 8934
89350x1C, 0x23, 0x60, 0xEC, 8935 0x1C, 0x23, 0x60, 0xEC,
89360x36, 0xD7, 0x36, 0xAD, 8936 0x36, 0xD7, 0x36, 0xAD,
8937 8937
89380x2B, 0x80, 0x60, 0xEC, 8938 0x2B, 0x80, 0x60, 0xEC,
89390x1D, 0x24, 0x60, 0xEC, 8939 0x1D, 0x24, 0x60, 0xEC,
8940 8940
89410x3E, 0xD7, 0x3E, 0xAD, 8941 0x3E, 0xD7, 0x3E, 0xAD,
89420x2C, 0x80, 0x60, 0xEC, 8942 0x2C, 0x80, 0x60, 0xEC,
8943 8943
89440x1C, 0x2B, 0xDE, 0xE8, 8944 0x1C, 0x2B, 0xDE, 0xE8,
89450x23, 0x80, 0xDE, 0xE8, 8945 0x23, 0x80, 0xDE, 0xE8,
8946 8946
89470x36, 0x80, 0x36, 0xBD, 8947 0x36, 0x80, 0x36, 0xBD,
89480x3E, 0x80, 0x3E, 0xBD, 8948 0x3E, 0x80, 0x3E, 0xBD,
8949 8949
89500x33, 0xD7, 0x1C, 0xBD, 8950 0x33, 0xD7, 0x1C, 0xBD,
89510x3B, 0xD7, 0x23, 0xBD, 8951 0x3B, 0xD7, 0x23, 0xBD,
8952 8952
89530x46, 0x80, 0x46, 0xCF, 8953 0x46, 0x80, 0x46, 0xCF,
89540x4F, 0x80, 0x4F, 0xCF, 8954 0x4F, 0x80, 0x4F, 0xCF,
8955 8955
89560x56, 0x33, 0x56, 0xCF, 8956 0x56, 0x33, 0x56, 0xCF,
89570x47, 0x3B, 0x47, 0xCF, 8957 0x47, 0x3B, 0x47, 0xCF,
8958 8958
89590xD6, 0xFF, 0x20, 0xEA, 8959 0xD6, 0xFF, 0x20, 0xEA,
89600x00, 0x80, 0x00, 0xE8, 8960 0x00, 0x80, 0x00, 0xE8,
8961 8961
89620x4E, 0x33, 0x4E, 0xCF, 8962 0x4E, 0x33, 0x4E, 0xCF,
89630x57, 0x3B, 0x57, 0xCF, 8963 0x57, 0x3B, 0x57, 0xCF,
8964 8964
89650x9D, 0xFF, 0x20, 0xEA, 8965 0x9D, 0xFF, 0x20, 0xEA,
89660x57, 0xC0, 0xBF, 0xEA, 8966 0x57, 0xC0, 0xBF, 0xEA,
8967 8967
89680x00, 0x80, 0xA0, 0xE9, 8968 0x00, 0x80, 0xA0, 0xE9,
89690x00, 0x00, 0xD8, 0xEC, 8969 0x00, 0x00, 0xD8, 0xEC,
8970 8970
8971}; 8971};
8972 8972
8973static unsigned char warp_g400_tgza[] = { 8973static unsigned char warp_g400_tgza[] = {
8974 8974
89750x00, 0x88, 0x98, 0xE9, 8975 0x00, 0x88, 0x98, 0xE9,
89760x00, 0x80, 0x00, 0xE8, 8976 0x00, 0x80, 0x00, 0xE8,
8977 8977
89780x00, 0x80, 0xA0, 0xE9, 8978 0x00, 0x80, 0xA0, 0xE9,
89790x00, 0x00, 0xD8, 0xEC, 8979 0x00, 0x00, 0xD8, 0xEC,
8980 8980
89810xFF, 0x80, 0xC0, 0xE9, 8981 0xFF, 0x80, 0xC0, 0xE9,
89820x00, 0x80, 0x00, 0xE8, 8982 0x00, 0x80, 0x00, 0xE8,
8983 8983
89840x22, 0x40, 0x48, 0xBF, 8984 0x22, 0x40, 0x48, 0xBF,
89850x2A, 0x40, 0x50, 0xBF, 8985 0x2A, 0x40, 0x50, 0xBF,
8986 8986
89870x32, 0x41, 0x49, 0xBF, 8987 0x32, 0x41, 0x49, 0xBF,
89880x3A, 0x41, 0x51, 0xBF, 8988 0x3A, 0x41, 0x51, 0xBF,
8989 8989
89900xC3, 0x6B, 8990 0xC3, 0x6B,
89910xCB, 0x6B, 8991 0xCB, 0x6B,
89920x00, 0x88, 0x98, 0xE9, 8992 0x00, 0x88, 0x98, 0xE9,
8993 8993
89940x73, 0x7B, 0xC8, 0xEC, 8994 0x73, 0x7B, 0xC8, 0xEC,
89950x96, 0xE2, 8995 0x96, 0xE2,
89960x41, 0x04, 8996 0x41, 0x04,
8997 8997
89980x7B, 0x43, 0xA0, 0xE8, 8998 0x7B, 0x43, 0xA0, 0xE8,
89990x73, 0x4B, 0xA0, 0xE8, 8999 0x73, 0x4B, 0xA0, 0xE8,
9000 9000
90010xAD, 0xEE, 0x29, 0x9F, 9001 0xAD, 0xEE, 0x29, 0x9F,
90020x00, 0xE0, 9002 0x00, 0xE0,
90030x49, 0x04, 9003 0x49, 0x04,
9004 9004
90050x90, 0xE2, 9005 0x90, 0xE2,
90060x51, 0x04, 9006 0x51, 0x04,
90070x31, 0x46, 0xB1, 0xE8, 9007 0x31, 0x46, 0xB1, 0xE8,
9008 9008
90090x49, 0x41, 0xC0, 0xEC, 9009 0x49, 0x41, 0xC0, 0xEC,
90100x39, 0x57, 0xB1, 0xE8, 9010 0x39, 0x57, 0xB1, 0xE8,
9011 9011
90120x00, 0x04, 9012 0x00, 0x04,
90130x46, 0xE2, 9013 0x46, 0xE2,
90140x73, 0x53, 0xA0, 0xE8, 9014 0x73, 0x53, 0xA0, 0xE8,
9015 9015
90160x51, 0x41, 0xC0, 0xEC, 9016 0x51, 0x41, 0xC0, 0xEC,
90170x31, 0x00, 9017 0x31, 0x00,
90180x39, 0x00, 9018 0x39, 0x00,
9019 9019
90200x5C, 0x80, 0x15, 0xEA, 9020 0x5C, 0x80, 0x15, 0xEA,
90210x08, 0x04, 9021 0x08, 0x04,
90220x10, 0x04, 9022 0x10, 0x04,
9023 9023
90240x51, 0x49, 0xC0, 0xEC, 9024 0x51, 0x49, 0xC0, 0xEC,
90250x2F, 0x41, 0x60, 0xEA, 9025 0x2F, 0x41, 0x60, 0xEA,
9026 9026
90270x31, 0x20, 9027 0x31, 0x20,
90280x39, 0x20, 9028 0x39, 0x20,
90290x1F, 0x42, 0xA0, 0xE8, 9029 0x1F, 0x42, 0xA0, 0xE8,
9030 9030
90310x2A, 0x42, 0x4A, 0xBF, 9031 0x2A, 0x42, 0x4A, 0xBF,
90320x27, 0x4A, 0xA0, 0xE8, 9032 0x27, 0x4A, 0xA0, 0xE8,
9033 9033
90340x1A, 0x42, 0x52, 0xBF, 9034 0x1A, 0x42, 0x52, 0xBF,
90350x1E, 0x49, 0x60, 0xEA, 9035 0x1E, 0x49, 0x60, 0xEA,
9036 9036
90370x73, 0x7B, 0xC8, 0xEC, 9037 0x73, 0x7B, 0xC8, 0xEC,
90380x26, 0x51, 0x60, 0xEA, 9038 0x26, 0x51, 0x60, 0xEA,
9039 9039
90400x32, 0x40, 0x48, 0xBD, 9040 0x32, 0x40, 0x48, 0xBD,
90410x22, 0x40, 0x50, 0xBD, 9041 0x22, 0x40, 0x50, 0xBD,
9042 9042
90430x12, 0x41, 0x49, 0xBD, 9043 0x12, 0x41, 0x49, 0xBD,
90440x3A, 0x41, 0x51, 0xBD, 9044 0x3A, 0x41, 0x51, 0xBD,
9045 9045
90460xBF, 0x2F, 0x26, 0xBD, 9046 0xBF, 0x2F, 0x26, 0xBD,
90470x00, 0xE0, 9047 0x00, 0xE0,
90480x7B, 0x72, 9048 0x7B, 0x72,
9049 9049
90500x32, 0x20, 9050 0x32, 0x20,
90510x22, 0x20, 9051 0x22, 0x20,
90520x12, 0x20, 9052 0x12, 0x20,
90530x3A, 0x20, 9053 0x3A, 0x20,
9054 9054
90550x46, 0x31, 0x46, 0xBF, 9055 0x46, 0x31, 0x46, 0xBF,
90560x4E, 0x31, 0x4E, 0xBF, 9056 0x4E, 0x31, 0x4E, 0xBF,
9057 9057
90580xB3, 0xE2, 0x2D, 0x9F, 9058 0xB3, 0xE2, 0x2D, 0x9F,
90590x00, 0x80, 0x00, 0xE8, 9059 0x00, 0x80, 0x00, 0xE8,
9060 9060
90610x56, 0x31, 0x56, 0xBF, 9061 0x56, 0x31, 0x56, 0xBF,
90620x47, 0x39, 0x47, 0xBF, 9062 0x47, 0x39, 0x47, 0xBF,
9063 9063
90640x4F, 0x39, 0x4F, 0xBF, 9064 0x4F, 0x39, 0x4F, 0xBF,
90650x57, 0x39, 0x57, 0xBF, 9065 0x57, 0x39, 0x57, 0xBF,
9066 9066
90670x4E, 0x80, 0x07, 0xEA, 9067 0x4E, 0x80, 0x07, 0xEA,
90680x24, 0x41, 0x20, 0xE9, 9068 0x24, 0x41, 0x20, 0xE9,
9069 9069
90700x42, 0x73, 0xF8, 0xEC, 9070 0x42, 0x73, 0xF8, 0xEC,
90710x00, 0xE0, 9071 0x00, 0xE0,
90720x2D, 0x73, 9072 0x2D, 0x73,
9073 9073
90740x33, 0x72, 9074 0x33, 0x72,
90750x0C, 0xE3, 9075 0x0C, 0xE3,
90760xA5, 0x2F, 0x1E, 0xBD, 9076 0xA5, 0x2F, 0x1E, 0xBD,
9077 9077
90780x43, 0x43, 0x2D, 0xDF, 9078 0x43, 0x43, 0x2D, 0xDF,
90790x4B, 0x4B, 0x2D, 0xDF, 9079 0x4B, 0x4B, 0x2D, 0xDF,
9080 9080
90810xAE, 0x1E, 0x26, 0xBD, 9081 0xAE, 0x1E, 0x26, 0xBD,
90820x58, 0xE3, 9082 0x58, 0xE3,
90830x33, 0x66, 9083 0x33, 0x66,
9084 9084
90850x53, 0x53, 0x2D, 0xDF, 9085 0x53, 0x53, 0x2D, 0xDF,
90860x00, 0x80, 0x00, 0xE8, 9086 0x00, 0x80, 0x00, 0xE8,
9087 9087
90880xB8, 0x38, 0x33, 0xBF, 9088 0xB8, 0x38, 0x33, 0xBF,
90890x00, 0xE0, 9089 0x00, 0xE0,
90900x59, 0xE3, 9090 0x59, 0xE3,
9091 9091
90920x1E, 0x12, 0x41, 0xE9, 9092 0x1E, 0x12, 0x41, 0xE9,
90930x1A, 0x22, 0x41, 0xE9, 9093 0x1A, 0x22, 0x41, 0xE9,
9094 9094
90950x2B, 0x40, 0x3D, 0xE9, 9095 0x2B, 0x40, 0x3D, 0xE9,
90960x3F, 0x4B, 0xA0, 0xE8, 9096 0x3F, 0x4B, 0xA0, 0xE8,
9097 9097
90980x2D, 0x73, 9098 0x2D, 0x73,
90990x30, 0x76, 9099 0x30, 0x76,
91000x05, 0x80, 0x3D, 0xEA, 9100 0x05, 0x80, 0x3D, 0xEA,
9101 9101
91020x37, 0x43, 0xA0, 0xE8, 9102 0x37, 0x43, 0xA0, 0xE8,
91030x3D, 0x53, 0xA0, 0xE8, 9103 0x3D, 0x53, 0xA0, 0xE8,
9104 9104
91050x48, 0x70, 0xF8, 0xEC, 9105 0x48, 0x70, 0xF8, 0xEC,
91060x2B, 0x48, 0x3C, 0xE9, 9106 0x2B, 0x48, 0x3C, 0xE9,
9107 9107
91080x1F, 0x27, 0xBC, 0xE8, 9108 0x1F, 0x27, 0xBC, 0xE8,
91090x00, 0x80, 0x00, 0xE8, 9109 0x00, 0x80, 0x00, 0xE8,
9110 9110
91110x00, 0x80, 0x00, 0xE8, 9111 0x00, 0x80, 0x00, 0xE8,
91120x00, 0x80, 0x00, 0xE8, 9112 0x00, 0x80, 0x00, 0xE8,
9113 9113
91140x15, 0xC0, 0x20, 0xE9, 9114 0x15, 0xC0, 0x20, 0xE9,
91150x15, 0xC0, 0x20, 0xE9, 9115 0x15, 0xC0, 0x20, 0xE9,
9116 9116
91170x15, 0xC0, 0x20, 0xE9, 9117 0x15, 0xC0, 0x20, 0xE9,
91180x15, 0xC0, 0x20, 0xE9, 9118 0x15, 0xC0, 0x20, 0xE9,
9119 9119
91200x18, 0x3A, 0x41, 0xE9, 9120 0x18, 0x3A, 0x41, 0xE9,
91210x1D, 0x32, 0x41, 0xE9, 9121 0x1D, 0x32, 0x41, 0xE9,
9122 9122
91230x2A, 0x40, 0x20, 0xE9, 9123 0x2A, 0x40, 0x20, 0xE9,
91240x56, 0x3D, 0x56, 0xDF, 9124 0x56, 0x3D, 0x56, 0xDF,
9125 9125
91260x46, 0x37, 0x46, 0xDF, 9126 0x46, 0x37, 0x46, 0xDF,
91270x4E, 0x3F, 0x4E, 0xDF, 9127 0x4E, 0x3F, 0x4E, 0xDF,
9128 9128
91290x16, 0x30, 0x20, 0xE9, 9129 0x16, 0x30, 0x20, 0xE9,
91300x4F, 0x3F, 0x4F, 0xDF, 9130 0x4F, 0x3F, 0x4F, 0xDF,
9131 9131
91320x32, 0x32, 0x2D, 0xDF, 9132 0x32, 0x32, 0x2D, 0xDF,
91330x22, 0x22, 0x2D, 0xDF, 9133 0x22, 0x22, 0x2D, 0xDF,
9134 9134
91350x12, 0x12, 0x2D, 0xDF, 9135 0x12, 0x12, 0x2D, 0xDF,
91360x3A, 0x3A, 0x2D, 0xDF, 9136 0x3A, 0x3A, 0x2D, 0xDF,
9137 9137
91380x47, 0x37, 0x47, 0xDF, 9138 0x47, 0x37, 0x47, 0xDF,
91390x57, 0x3D, 0x57, 0xDF, 9139 0x57, 0x3D, 0x57, 0xDF,
9140 9140
91410x3D, 0xCF, 0x74, 0xC0, 9141 0x3D, 0xCF, 0x74, 0xC0,
91420x37, 0xCF, 0x74, 0xC4, 9142 0x37, 0xCF, 0x74, 0xC4,
9143 9143
91440x31, 0x53, 0x2F, 0x9F, 9144 0x31, 0x53, 0x2F, 0x9F,
91450x34, 0x80, 0x20, 0xE9, 9145 0x34, 0x80, 0x20, 0xE9,
9146 9146
91470x39, 0xE5, 0x2C, 0x9F, 9147 0x39, 0xE5, 0x2C, 0x9F,
91480x3C, 0x3D, 0x20, 0xE9, 9148 0x3C, 0x3D, 0x20, 0xE9,
9149 9149
91500x27, 0xCF, 0x74, 0xC6, 9150 0x27, 0xCF, 0x74, 0xC6,
91510x3D, 0xCF, 0x74, 0xC2, 9151 0x3D, 0xCF, 0x74, 0xC2,
9152 9152
91530x0A, 0x44, 0x4C, 0xB0, 9153 0x0A, 0x44, 0x4C, 0xB0,
91540x02, 0x44, 0x54, 0xB0, 9154 0x02, 0x44, 0x54, 0xB0,
9155 9155
91560x2A, 0x44, 0x4C, 0xB2, 9156 0x2A, 0x44, 0x4C, 0xB2,
91570x1A, 0x44, 0x54, 0xB2, 9157 0x1A, 0x44, 0x54, 0xB2,
9158 9158
91590x20, 0x80, 0x3A, 0xEA, 9159 0x20, 0x80, 0x3A, 0xEA,
91600x0A, 0x20, 9160 0x0A, 0x20,
91610x02, 0x20, 9161 0x02, 0x20,
9162 9162
91630x88, 0x73, 0x5E, 0xE9, 9163 0x88, 0x73, 0x5E, 0xE9,
91640x2A, 0x20, 9164 0x2A, 0x20,
91650x1A, 0x20, 9165 0x1A, 0x20,
9166 9166
91670x30, 0x50, 0x2E, 0x9F, 9167 0x30, 0x50, 0x2E, 0x9F,
91680x32, 0x31, 0x5F, 0xE9, 9168 0x32, 0x31, 0x5F, 0xE9,
9169 9169
91700x38, 0x21, 0x2C, 0x9F, 9170 0x38, 0x21, 0x2C, 0x9F,
91710x33, 0x39, 0x5F, 0xE9, 9171 0x33, 0x39, 0x5F, 0xE9,
9172 9172
91730x31, 0x53, 0x2F, 0x9F, 9173 0x31, 0x53, 0x2F, 0x9F,
91740x9C, 0x27, 0x20, 0xE9, 9174 0x9C, 0x27, 0x20, 0xE9,
9175 9175
91760x0A, 0x44, 0x4C, 0xB4, 9176 0x0A, 0x44, 0x4C, 0xB4,
91770x02, 0x44, 0x54, 0xB4, 9177 0x02, 0x44, 0x54, 0xB4,
9178 9178
91790x2A, 0x44, 0x4C, 0xB6, 9179 0x2A, 0x44, 0x4C, 0xB6,
91800x1A, 0x44, 0x54, 0xB6, 9180 0x1A, 0x44, 0x54, 0xB6,
9181 9181
91820x39, 0xE5, 0x2C, 0x9F, 9182 0x39, 0xE5, 0x2C, 0x9F,
91830x38, 0x3D, 0x20, 0xE9, 9183 0x38, 0x3D, 0x20, 0xE9,
9184 9184
91850x0A, 0x20, 9185 0x0A, 0x20,
91860x02, 0x20, 9186 0x02, 0x20,
91870x2A, 0x20, 9187 0x2A, 0x20,
91880x1A, 0x20, 9188 0x1A, 0x20,
9189 9189
91900x0A, 0x47, 0x4F, 0xBF, 9190 0x0A, 0x47, 0x4F, 0xBF,
91910x02, 0x47, 0x57, 0xBF, 9191 0x02, 0x47, 0x57, 0xBF,
9192 9192
91930x30, 0x50, 0x2E, 0x9F, 9193 0x30, 0x50, 0x2E, 0x9F,
91940x3E, 0x30, 0x4F, 0xE9, 9194 0x3E, 0x30, 0x4F, 0xE9,
9195 9195
91960x38, 0x21, 0x2C, 0x9F, 9196 0x38, 0x21, 0x2C, 0x9F,
91970x3F, 0x38, 0x4F, 0xE9, 9197 0x3F, 0x38, 0x4F, 0xE9,
9198 9198
91990x2A, 0x46, 0x4E, 0xBF, 9199 0x2A, 0x46, 0x4E, 0xBF,
92000x1A, 0x46, 0x56, 0xBF, 9200 0x1A, 0x46, 0x56, 0xBF,
9201 9201
92020x31, 0x53, 0x2F, 0x9F, 9202 0x31, 0x53, 0x2F, 0x9F,
92030x3A, 0x31, 0x4F, 0xE9, 9203 0x3A, 0x31, 0x4F, 0xE9,
9204 9204
92050x39, 0xE5, 0x2C, 0x9F, 9205 0x39, 0xE5, 0x2C, 0x9F,
92060x3B, 0x39, 0x4F, 0xE9, 9206 0x3B, 0x39, 0x4F, 0xE9,
9207 9207
92080x31, 0x53, 0x2F, 0x9F, 9208 0x31, 0x53, 0x2F, 0x9F,
92090x36, 0x30, 0x4F, 0xE9, 9209 0x36, 0x30, 0x4F, 0xE9,
9210 9210
92110x39, 0xE5, 0x2C, 0x9F, 9211 0x39, 0xE5, 0x2C, 0x9F,
92120x37, 0x38, 0x4F, 0xE9, 9212 0x37, 0x38, 0x4F, 0xE9,
9213 9213
92140x2A, 0x43, 0x4B, 0xBF, 9214 0x2A, 0x43, 0x4B, 0xBF,
92150x1A, 0x43, 0x53, 0xBF, 9215 0x1A, 0x43, 0x53, 0xBF,
9216 9216
92170x30, 0x50, 0x2E, 0x9F, 9217 0x30, 0x50, 0x2E, 0x9F,
92180x9D, 0x31, 0x4F, 0xE9, 9218 0x9D, 0x31, 0x4F, 0xE9,
9219 9219
92200x38, 0x21, 0x2C, 0x9F, 9220 0x38, 0x21, 0x2C, 0x9F,
92210x9E, 0x39, 0x4F, 0xE9, 9221 0x9E, 0x39, 0x4F, 0xE9,
9222 9222
92230x31, 0x53, 0x2F, 0x9F, 9223 0x31, 0x53, 0x2F, 0x9F,
92240x80, 0x31, 0x57, 0xE9, 9224 0x80, 0x31, 0x57, 0xE9,
9225 9225
92260x39, 0xE5, 0x2C, 0x9F, 9226 0x39, 0xE5, 0x2C, 0x9F,
92270x81, 0x39, 0x57, 0xE9, 9227 0x81, 0x39, 0x57, 0xE9,
9228 9228
92290x37, 0x48, 0x50, 0xBD, 9229 0x37, 0x48, 0x50, 0xBD,
92300x8A, 0x36, 0x20, 0xE9, 9230 0x8A, 0x36, 0x20, 0xE9,
9231 9231
92320x86, 0x76, 0x57, 0xE9, 9232 0x86, 0x76, 0x57, 0xE9,
92330x8B, 0x3E, 0x20, 0xE9, 9233 0x8B, 0x3E, 0x20, 0xE9,
9234 9234
92350x82, 0x30, 0x57, 0xE9, 9235 0x82, 0x30, 0x57, 0xE9,
92360x87, 0x77, 0x57, 0xE9, 9236 0x87, 0x77, 0x57, 0xE9,
9237 9237
92380x83, 0x38, 0x57, 0xE9, 9238 0x83, 0x38, 0x57, 0xE9,
92390x35, 0x49, 0x51, 0xBD, 9239 0x35, 0x49, 0x51, 0xBD,
9240 9240
92410x84, 0x31, 0x5E, 0xE9, 9241 0x84, 0x31, 0x5E, 0xE9,
92420x30, 0x1F, 0x5F, 0xE9, 9242 0x30, 0x1F, 0x5F, 0xE9,
9243 9243
92440x85, 0x39, 0x5E, 0xE9, 9244 0x85, 0x39, 0x5E, 0xE9,
92450x57, 0x25, 0x20, 0xE9, 9245 0x57, 0x25, 0x20, 0xE9,
9246 9246
92470x2B, 0x48, 0x20, 0xE9, 9247 0x2B, 0x48, 0x20, 0xE9,
92480x1D, 0x37, 0xE1, 0xEA, 9248 0x1D, 0x37, 0xE1, 0xEA,
9249 9249
92500x1E, 0x35, 0xE1, 0xEA, 9250 0x1E, 0x35, 0xE1, 0xEA,
92510x00, 0xE0, 9251 0x00, 0xE0,
92520x26, 0x77, 9252 0x26, 0x77,
9253 9253
92540x24, 0x49, 0x20, 0xE9, 9254 0x24, 0x49, 0x20, 0xE9,
92550xAB, 0xFF, 0x20, 0xEA, 9255 0xAB, 0xFF, 0x20, 0xEA,
9256 9256
92570x16, 0x26, 0x20, 0xE9, 9257 0x16, 0x26, 0x20, 0xE9,
92580x57, 0x2E, 0xBF, 0xEA, 9258 0x57, 0x2E, 0xBF, 0xEA,
9259 9259
92600x1C, 0x46, 0xA0, 0xE8, 9260 0x1C, 0x46, 0xA0, 0xE8,
92610x23, 0x4E, 0xA0, 0xE8, 9261 0x23, 0x4E, 0xA0, 0xE8,
9262 9262
92630x2B, 0x56, 0xA0, 0xE8, 9263 0x2B, 0x56, 0xA0, 0xE8,
92640x1D, 0x47, 0xA0, 0xE8, 9264 0x1D, 0x47, 0xA0, 0xE8,
9265 9265
92660x24, 0x4F, 0xA0, 0xE8, 9266 0x24, 0x4F, 0xA0, 0xE8,
92670x2C, 0x57, 0xA0, 0xE8, 9267 0x2C, 0x57, 0xA0, 0xE8,
9268 9268
92690x1C, 0x00, 9269 0x1C, 0x00,
92700x23, 0x00, 9270 0x23, 0x00,
92710x2B, 0x00, 9271 0x2B, 0x00,
92720x00, 0xE0, 9272 0x00, 0xE0,
9273 9273
92740x1D, 0x00, 9274 0x1D, 0x00,
92750x24, 0x00, 9275 0x24, 0x00,
92760x2C, 0x00, 9276 0x2C, 0x00,
92770x00, 0xE0, 9277 0x00, 0xE0,
9278 9278
92790x1C, 0x65, 9279 0x1C, 0x65,
92800x23, 0x65, 9280 0x23, 0x65,
92810x2B, 0x65, 9281 0x2B, 0x65,
92820x00, 0xE0, 9282 0x00, 0xE0,
9283 9283
92840x1D, 0x65, 9284 0x1D, 0x65,
92850x24, 0x65, 9285 0x24, 0x65,
92860x2C, 0x65, 9286 0x2C, 0x65,
92870x00, 0xE0, 9287 0x00, 0xE0,
9288 9288
92890x1C, 0x23, 0x60, 0xEC, 9289 0x1C, 0x23, 0x60, 0xEC,
92900x36, 0xD7, 0x36, 0xAD, 9290 0x36, 0xD7, 0x36, 0xAD,
9291 9291
92920x2B, 0x80, 0x60, 0xEC, 9292 0x2B, 0x80, 0x60, 0xEC,
92930x1D, 0x24, 0x60, 0xEC, 9293 0x1D, 0x24, 0x60, 0xEC,
9294 9294
92950x3E, 0xD7, 0x3E, 0xAD, 9295 0x3E, 0xD7, 0x3E, 0xAD,
92960x2C, 0x80, 0x60, 0xEC, 9296 0x2C, 0x80, 0x60, 0xEC,
9297 9297
92980x1C, 0x2B, 0xDE, 0xE8, 9298 0x1C, 0x2B, 0xDE, 0xE8,
92990x23, 0x80, 0xDE, 0xE8, 9299 0x23, 0x80, 0xDE, 0xE8,
9300 9300
93010x36, 0x80, 0x36, 0xBD, 9301 0x36, 0x80, 0x36, 0xBD,
93020x3E, 0x80, 0x3E, 0xBD, 9302 0x3E, 0x80, 0x3E, 0xBD,
9303 9303
93040x33, 0xD7, 0x1C, 0xBD, 9304 0x33, 0xD7, 0x1C, 0xBD,
93050x3B, 0xD7, 0x23, 0xBD, 9305 0x3B, 0xD7, 0x23, 0xBD,
9306 9306
93070x46, 0x80, 0x46, 0xCF, 9307 0x46, 0x80, 0x46, 0xCF,
93080x4F, 0x80, 0x4F, 0xCF, 9308 0x4F, 0x80, 0x4F, 0xCF,
9309 9309
93100x56, 0x33, 0x56, 0xCF, 9310 0x56, 0x33, 0x56, 0xCF,
93110x47, 0x3B, 0x47, 0xCF, 9311 0x47, 0x3B, 0x47, 0xCF,
9312 9312
93130xD3, 0xFF, 0x20, 0xEA, 9313 0xD3, 0xFF, 0x20, 0xEA,
93140x00, 0x80, 0x00, 0xE8, 9314 0x00, 0x80, 0x00, 0xE8,
9315 9315
93160x4E, 0x33, 0x4E, 0xCF, 9316 0x4E, 0x33, 0x4E, 0xCF,
93170x57, 0x3B, 0x57, 0xCF, 9317 0x57, 0x3B, 0x57, 0xCF,
9318 9318
93190x99, 0xFF, 0x20, 0xEA, 9319 0x99, 0xFF, 0x20, 0xEA,
93200x57, 0xC0, 0xBF, 0xEA, 9320 0x57, 0xC0, 0xBF, 0xEA,
9321 9321
93220x00, 0x80, 0xA0, 0xE9, 9322 0x00, 0x80, 0xA0, 0xE9,
93230x00, 0x00, 0xD8, 0xEC, 9323 0x00, 0x00, 0xD8, 0xEC,
9324 9324
9325}; 9325};
9326 9326
9327static unsigned char warp_g400_tgzaf[] = { 9327static unsigned char warp_g400_tgzaf[] = {
9328 9328
93290x00, 0x88, 0x98, 0xE9, 9329 0x00, 0x88, 0x98, 0xE9,
93300x00, 0x80, 0x00, 0xE8, 9330 0x00, 0x80, 0x00, 0xE8,
9331 9331
93320x00, 0x80, 0xA0, 0xE9, 9332 0x00, 0x80, 0xA0, 0xE9,
93330x00, 0x00, 0xD8, 0xEC, 9333 0x00, 0x00, 0xD8, 0xEC,
9334 9334
93350xFF, 0x80, 0xC0, 0xE9, 9335 0xFF, 0x80, 0xC0, 0xE9,
93360x00, 0x80, 0x00, 0xE8, 9336 0x00, 0x80, 0x00, 0xE8,
9337 9337
93380x22, 0x40, 0x48, 0xBF, 9338 0x22, 0x40, 0x48, 0xBF,
93390x2A, 0x40, 0x50, 0xBF, 9339 0x2A, 0x40, 0x50, 0xBF,
9340 9340
93410x32, 0x41, 0x49, 0xBF, 9341 0x32, 0x41, 0x49, 0xBF,
93420x3A, 0x41, 0x51, 0xBF, 9342 0x3A, 0x41, 0x51, 0xBF,
9343 9343
93440xC3, 0x6B, 9344 0xC3, 0x6B,
93450xCB, 0x6B, 9345 0xCB, 0x6B,
93460x00, 0x88, 0x98, 0xE9, 9346 0x00, 0x88, 0x98, 0xE9,
9347 9347
93480x73, 0x7B, 0xC8, 0xEC, 9348 0x73, 0x7B, 0xC8, 0xEC,
93490x96, 0xE2, 9349 0x96, 0xE2,
93500x41, 0x04, 9350 0x41, 0x04,
9351 9351
93520x7B, 0x43, 0xA0, 0xE8, 9352 0x7B, 0x43, 0xA0, 0xE8,
93530x73, 0x4B, 0xA0, 0xE8, 9353 0x73, 0x4B, 0xA0, 0xE8,
9354 9354
93550xAD, 0xEE, 0x29, 0x9F, 9355 0xAD, 0xEE, 0x29, 0x9F,
93560x00, 0xE0, 9356 0x00, 0xE0,
93570x49, 0x04, 9357 0x49, 0x04,
9358 9358
93590x90, 0xE2, 9359 0x90, 0xE2,
93600x51, 0x04, 9360 0x51, 0x04,
93610x31, 0x46, 0xB1, 0xE8, 9361 0x31, 0x46, 0xB1, 0xE8,
9362 9362
93630x49, 0x41, 0xC0, 0xEC, 9363 0x49, 0x41, 0xC0, 0xEC,
93640x39, 0x57, 0xB1, 0xE8, 9364 0x39, 0x57, 0xB1, 0xE8,
9365 9365
93660x00, 0x04, 9366 0x00, 0x04,
93670x46, 0xE2, 9367 0x46, 0xE2,
93680x73, 0x53, 0xA0, 0xE8, 9368 0x73, 0x53, 0xA0, 0xE8,
9369 9369
93700x51, 0x41, 0xC0, 0xEC, 9370 0x51, 0x41, 0xC0, 0xEC,
93710x31, 0x00, 9371 0x31, 0x00,
93720x39, 0x00, 9372 0x39, 0x00,
9373 9373
93740x61, 0x80, 0x15, 0xEA, 9374 0x61, 0x80, 0x15, 0xEA,
93750x08, 0x04, 9375 0x08, 0x04,
93760x10, 0x04, 9376 0x10, 0x04,
9377 9377
93780x51, 0x49, 0xC0, 0xEC, 9378 0x51, 0x49, 0xC0, 0xEC,
93790x2F, 0x41, 0x60, 0xEA, 9379 0x2F, 0x41, 0x60, 0xEA,
9380 9380
93810x31, 0x20, 9381 0x31, 0x20,
93820x39, 0x20, 9382 0x39, 0x20,
93830x1F, 0x42, 0xA0, 0xE8, 9383 0x1F, 0x42, 0xA0, 0xE8,
9384 9384
93850x2A, 0x42, 0x4A, 0xBF, 9385 0x2A, 0x42, 0x4A, 0xBF,
93860x27, 0x4A, 0xA0, 0xE8, 9386 0x27, 0x4A, 0xA0, 0xE8,
9387 9387
93880x1A, 0x42, 0x52, 0xBF, 9388 0x1A, 0x42, 0x52, 0xBF,
93890x1E, 0x49, 0x60, 0xEA, 9389 0x1E, 0x49, 0x60, 0xEA,
9390 9390
93910x73, 0x7B, 0xC8, 0xEC, 9391 0x73, 0x7B, 0xC8, 0xEC,
93920x26, 0x51, 0x60, 0xEA, 9392 0x26, 0x51, 0x60, 0xEA,
9393 9393
93940x32, 0x40, 0x48, 0xBD, 9394 0x32, 0x40, 0x48, 0xBD,
93950x22, 0x40, 0x50, 0xBD, 9395 0x22, 0x40, 0x50, 0xBD,
9396 9396
93970x12, 0x41, 0x49, 0xBD, 9397 0x12, 0x41, 0x49, 0xBD,
93980x3A, 0x41, 0x51, 0xBD, 9398 0x3A, 0x41, 0x51, 0xBD,
9399 9399
94000xBF, 0x2F, 0x26, 0xBD, 9400 0xBF, 0x2F, 0x26, 0xBD,
94010x00, 0xE0, 9401 0x00, 0xE0,
94020x7B, 0x72, 9402 0x7B, 0x72,
9403 9403
94040x32, 0x20, 9404 0x32, 0x20,
94050x22, 0x20, 9405 0x22, 0x20,
94060x12, 0x20, 9406 0x12, 0x20,
94070x3A, 0x20, 9407 0x3A, 0x20,
9408 9408
94090x46, 0x31, 0x46, 0xBF, 9409 0x46, 0x31, 0x46, 0xBF,
94100x4E, 0x31, 0x4E, 0xBF, 9410 0x4E, 0x31, 0x4E, 0xBF,
9411 9411
94120xB3, 0xE2, 0x2D, 0x9F, 9412 0xB3, 0xE2, 0x2D, 0x9F,
94130x00, 0x80, 0x00, 0xE8, 9413 0x00, 0x80, 0x00, 0xE8,
9414 9414
94150x56, 0x31, 0x56, 0xBF, 9415 0x56, 0x31, 0x56, 0xBF,
94160x47, 0x39, 0x47, 0xBF, 9416 0x47, 0x39, 0x47, 0xBF,
9417 9417
94180x4F, 0x39, 0x4F, 0xBF, 9418 0x4F, 0x39, 0x4F, 0xBF,
94190x57, 0x39, 0x57, 0xBF, 9419 0x57, 0x39, 0x57, 0xBF,
9420 9420
94210x53, 0x80, 0x07, 0xEA, 9421 0x53, 0x80, 0x07, 0xEA,
94220x24, 0x41, 0x20, 0xE9, 9422 0x24, 0x41, 0x20, 0xE9,
9423 9423
94240x42, 0x73, 0xF8, 0xEC, 9424 0x42, 0x73, 0xF8, 0xEC,
94250x00, 0xE0, 9425 0x00, 0xE0,
94260x2D, 0x73, 9426 0x2D, 0x73,
9427 9427
94280x33, 0x72, 9428 0x33, 0x72,
94290x0C, 0xE3, 9429 0x0C, 0xE3,
94300xA5, 0x2F, 0x1E, 0xBD, 9430 0xA5, 0x2F, 0x1E, 0xBD,
9431 9431
94320x43, 0x43, 0x2D, 0xDF, 9432 0x43, 0x43, 0x2D, 0xDF,
94330x4B, 0x4B, 0x2D, 0xDF, 9433 0x4B, 0x4B, 0x2D, 0xDF,
9434 9434
94350xAE, 0x1E, 0x26, 0xBD, 9435 0xAE, 0x1E, 0x26, 0xBD,
94360x58, 0xE3, 9436 0x58, 0xE3,
94370x33, 0x66, 9437 0x33, 0x66,
9438 9438
94390x53, 0x53, 0x2D, 0xDF, 9439 0x53, 0x53, 0x2D, 0xDF,
94400x00, 0x80, 0x00, 0xE8, 9440 0x00, 0x80, 0x00, 0xE8,
9441 9441
94420xB8, 0x38, 0x33, 0xBF, 9442 0xB8, 0x38, 0x33, 0xBF,
94430x00, 0xE0, 9443 0x00, 0xE0,
94440x59, 0xE3, 9444 0x59, 0xE3,
9445 9445
94460x1E, 0x12, 0x41, 0xE9, 9446 0x1E, 0x12, 0x41, 0xE9,
94470x1A, 0x22, 0x41, 0xE9, 9447 0x1A, 0x22, 0x41, 0xE9,
9448 9448
94490x2B, 0x40, 0x3D, 0xE9, 9449 0x2B, 0x40, 0x3D, 0xE9,
94500x3F, 0x4B, 0xA0, 0xE8, 9450 0x3F, 0x4B, 0xA0, 0xE8,
9451 9451
94520x2D, 0x73, 9452 0x2D, 0x73,
94530x30, 0x76, 9453 0x30, 0x76,
94540x05, 0x80, 0x3D, 0xEA, 9454 0x05, 0x80, 0x3D, 0xEA,
9455 9455
94560x37, 0x43, 0xA0, 0xE8, 9456 0x37, 0x43, 0xA0, 0xE8,
94570x3D, 0x53, 0xA0, 0xE8, 9457 0x3D, 0x53, 0xA0, 0xE8,
9458 9458
94590x48, 0x70, 0xF8, 0xEC, 9459 0x48, 0x70, 0xF8, 0xEC,
94600x2B, 0x48, 0x3C, 0xE9, 9460 0x2B, 0x48, 0x3C, 0xE9,
9461 9461
94620x1F, 0x27, 0xBC, 0xE8, 9462 0x1F, 0x27, 0xBC, 0xE8,
94630x00, 0x80, 0x00, 0xE8, 9463 0x00, 0x80, 0x00, 0xE8,
9464 9464
94650x00, 0x80, 0x00, 0xE8, 9465 0x00, 0x80, 0x00, 0xE8,
94660x00, 0x80, 0x00, 0xE8, 9466 0x00, 0x80, 0x00, 0xE8,
9467 9467
94680x15, 0xC0, 0x20, 0xE9, 9468 0x15, 0xC0, 0x20, 0xE9,
94690x15, 0xC0, 0x20, 0xE9, 9469 0x15, 0xC0, 0x20, 0xE9,
9470 9470
94710x15, 0xC0, 0x20, 0xE9, 9471 0x15, 0xC0, 0x20, 0xE9,
94720x15, 0xC0, 0x20, 0xE9, 9472 0x15, 0xC0, 0x20, 0xE9,
9473 9473
94740x18, 0x3A, 0x41, 0xE9, 9474 0x18, 0x3A, 0x41, 0xE9,
94750x1D, 0x32, 0x41, 0xE9, 9475 0x1D, 0x32, 0x41, 0xE9,
9476 9476
94770x2A, 0x40, 0x20, 0xE9, 9477 0x2A, 0x40, 0x20, 0xE9,
94780x56, 0x3D, 0x56, 0xDF, 9478 0x56, 0x3D, 0x56, 0xDF,
9479 9479
94800x46, 0x37, 0x46, 0xDF, 9480 0x46, 0x37, 0x46, 0xDF,
94810x4E, 0x3F, 0x4E, 0xDF, 9481 0x4E, 0x3F, 0x4E, 0xDF,
9482 9482
94830x16, 0x30, 0x20, 0xE9, 9483 0x16, 0x30, 0x20, 0xE9,
94840x4F, 0x3F, 0x4F, 0xDF, 9484 0x4F, 0x3F, 0x4F, 0xDF,
9485 9485
94860x32, 0x32, 0x2D, 0xDF, 9486 0x32, 0x32, 0x2D, 0xDF,
94870x22, 0x22, 0x2D, 0xDF, 9487 0x22, 0x22, 0x2D, 0xDF,
9488 9488
94890x12, 0x12, 0x2D, 0xDF, 9489 0x12, 0x12, 0x2D, 0xDF,
94900x3A, 0x3A, 0x2D, 0xDF, 9490 0x3A, 0x3A, 0x2D, 0xDF,
9491 9491
94920x47, 0x37, 0x47, 0xDF, 9492 0x47, 0x37, 0x47, 0xDF,
94930x57, 0x3D, 0x57, 0xDF, 9493 0x57, 0x3D, 0x57, 0xDF,
9494 9494
94950x3D, 0xCF, 0x74, 0xC0, 9495 0x3D, 0xCF, 0x74, 0xC0,
94960x37, 0xCF, 0x74, 0xC4, 9496 0x37, 0xCF, 0x74, 0xC4,
9497 9497
94980x0A, 0x44, 0x4C, 0xB0, 9498 0x0A, 0x44, 0x4C, 0xB0,
94990x02, 0x44, 0x54, 0xB0, 9499 0x02, 0x44, 0x54, 0xB0,
9500 9500
95010x31, 0x53, 0x2F, 0x9F, 9501 0x31, 0x53, 0x2F, 0x9F,
95020x34, 0x37, 0x20, 0xE9, 9502 0x34, 0x37, 0x20, 0xE9,
9503 9503
95040x39, 0xE5, 0x2C, 0x9F, 9504 0x39, 0xE5, 0x2C, 0x9F,
95050x3C, 0x3D, 0x20, 0xE9, 9505 0x3C, 0x3D, 0x20, 0xE9,
9506 9506
95070x2A, 0x44, 0x4C, 0xB2, 9507 0x2A, 0x44, 0x4C, 0xB2,
95080x1A, 0x44, 0x54, 0xB2, 9508 0x1A, 0x44, 0x54, 0xB2,
9509 9509
95100x26, 0x80, 0x3A, 0xEA, 9510 0x26, 0x80, 0x3A, 0xEA,
95110x0A, 0x20, 9511 0x0A, 0x20,
95120x02, 0x20, 9512 0x02, 0x20,
9513 9513
95140x88, 0x73, 0x5E, 0xE9, 9514 0x88, 0x73, 0x5E, 0xE9,
95150x2A, 0x20, 9515 0x2A, 0x20,
95160x1A, 0x20, 9516 0x1A, 0x20,
9517 9517
95180x3D, 0xCF, 0x74, 0xC2, 9518 0x3D, 0xCF, 0x74, 0xC2,
95190x27, 0xCF, 0x74, 0xC6, 9519 0x27, 0xCF, 0x74, 0xC6,
9520 9520
95210x30, 0x50, 0x2E, 0x9F, 9521 0x30, 0x50, 0x2E, 0x9F,
95220x32, 0x31, 0x5F, 0xE9, 9522 0x32, 0x31, 0x5F, 0xE9,
9523 9523
95240x38, 0x21, 0x2C, 0x9F, 9524 0x38, 0x21, 0x2C, 0x9F,
95250x33, 0x39, 0x5F, 0xE9, 9525 0x33, 0x39, 0x5F, 0xE9,
9526 9526
95270x31, 0x53, 0x2F, 0x9F, 9527 0x31, 0x53, 0x2F, 0x9F,
95280x9C, 0x27, 0x20, 0xE9, 9528 0x9C, 0x27, 0x20, 0xE9,
9529 9529
95300x0A, 0x44, 0x4C, 0xB4, 9530 0x0A, 0x44, 0x4C, 0xB4,
95310x02, 0x44, 0x54, 0xB4, 9531 0x02, 0x44, 0x54, 0xB4,
9532 9532
95330x2A, 0x44, 0x4C, 0xB6, 9533 0x2A, 0x44, 0x4C, 0xB6,
95340x1A, 0x44, 0x54, 0xB6, 9534 0x1A, 0x44, 0x54, 0xB6,
9535 9535
95360x39, 0xE5, 0x2C, 0x9F, 9536 0x39, 0xE5, 0x2C, 0x9F,
95370x38, 0x3D, 0x20, 0xE9, 9537 0x38, 0x3D, 0x20, 0xE9,
9538 9538
95390x0A, 0x20, 9539 0x0A, 0x20,
95400x02, 0x20, 9540 0x02, 0x20,
95410x2A, 0x20, 9541 0x2A, 0x20,
95420x1A, 0x20, 9542 0x1A, 0x20,
9543 9543
95440x3D, 0xCF, 0x75, 0xC6, 9544 0x3D, 0xCF, 0x75, 0xC6,
95450x00, 0x80, 0x00, 0xE8, 9545 0x00, 0x80, 0x00, 0xE8,
9546 9546
95470x30, 0x50, 0x2E, 0x9F, 9547 0x30, 0x50, 0x2E, 0x9F,
95480x3E, 0x30, 0x4F, 0xE9, 9548 0x3E, 0x30, 0x4F, 0xE9,
9549 9549
95500x38, 0x21, 0x2C, 0x9F, 9550 0x38, 0x21, 0x2C, 0x9F,
95510x3F, 0x38, 0x4F, 0xE9, 9551 0x3F, 0x38, 0x4F, 0xE9,
9552 9552
95530x0A, 0x45, 0x4D, 0xB6, 9553 0x0A, 0x45, 0x4D, 0xB6,
95540x02, 0x45, 0x55, 0xB6, 9554 0x02, 0x45, 0x55, 0xB6,
9555 9555
95560x31, 0x53, 0x2F, 0x9F, 9556 0x31, 0x53, 0x2F, 0x9F,
95570x3A, 0x31, 0x4F, 0xE9, 9557 0x3A, 0x31, 0x4F, 0xE9,
9558 9558
95590x39, 0xE5, 0x2C, 0x9F, 9559 0x39, 0xE5, 0x2C, 0x9F,
95600x3B, 0x39, 0x4F, 0xE9, 9560 0x3B, 0x39, 0x4F, 0xE9,
9561 9561
95620x31, 0x3D, 0x20, 0xE9, 9562 0x31, 0x3D, 0x20, 0xE9,
95630x0A, 0x20, 9563 0x0A, 0x20,
95640x02, 0x20, 9564 0x02, 0x20,
9565 9565
95660x2A, 0x46, 0x4E, 0xBF, 9566 0x2A, 0x46, 0x4E, 0xBF,
95670x1A, 0x46, 0x56, 0xBF, 9567 0x1A, 0x46, 0x56, 0xBF,
9568 9568
95690x0A, 0x47, 0x4F, 0xBF, 9569 0x0A, 0x47, 0x4F, 0xBF,
95700x02, 0x47, 0x57, 0xBF, 9570 0x02, 0x47, 0x57, 0xBF,
9571 9571
95720x30, 0x50, 0x2E, 0x9F, 9572 0x30, 0x50, 0x2E, 0x9F,
95730x36, 0x30, 0x4F, 0xE9, 9573 0x36, 0x30, 0x4F, 0xE9,
9574 9574
95750x38, 0x21, 0x2C, 0x9F, 9575 0x38, 0x21, 0x2C, 0x9F,
95760x37, 0x38, 0x4F, 0xE9, 9576 0x37, 0x38, 0x4F, 0xE9,
9577 9577
95780x31, 0x53, 0x2F, 0x9F, 9578 0x31, 0x53, 0x2F, 0x9F,
95790x9D, 0x31, 0x4F, 0xE9, 9579 0x9D, 0x31, 0x4F, 0xE9,
9580 9580
95810x39, 0xE5, 0x2C, 0x9F, 9581 0x39, 0xE5, 0x2C, 0x9F,
95820x9E, 0x39, 0x4F, 0xE9, 9582 0x9E, 0x39, 0x4F, 0xE9,
9583 9583
95840x2A, 0x43, 0x4B, 0xBF, 9584 0x2A, 0x43, 0x4B, 0xBF,
95850x1A, 0x43, 0x53, 0xBF, 9585 0x1A, 0x43, 0x53, 0xBF,
9586 9586
95870x30, 0x50, 0x2E, 0x9F, 9587 0x30, 0x50, 0x2E, 0x9F,
95880x35, 0x30, 0x4F, 0xE9, 9588 0x35, 0x30, 0x4F, 0xE9,
9589 9589
95900x38, 0x21, 0x2C, 0x9F, 9590 0x38, 0x21, 0x2C, 0x9F,
95910x39, 0x38, 0x4F, 0xE9, 9591 0x39, 0x38, 0x4F, 0xE9,
9592 9592
95930x31, 0x53, 0x2F, 0x9F, 9593 0x31, 0x53, 0x2F, 0x9F,
95940x80, 0x31, 0x57, 0xE9, 9594 0x80, 0x31, 0x57, 0xE9,
9595 9595
95960x39, 0xE5, 0x2C, 0x9F, 9596 0x39, 0xE5, 0x2C, 0x9F,
95970x81, 0x39, 0x57, 0xE9, 9597 0x81, 0x39, 0x57, 0xE9,
9598 9598
95990x37, 0x48, 0x50, 0xBD, 9599 0x37, 0x48, 0x50, 0xBD,
96000x8A, 0x36, 0x20, 0xE9, 9600 0x8A, 0x36, 0x20, 0xE9,
9601 9601
96020x86, 0x76, 0x57, 0xE9, 9602 0x86, 0x76, 0x57, 0xE9,
96030x8B, 0x3E, 0x20, 0xE9, 9603 0x8B, 0x3E, 0x20, 0xE9,
9604 9604
96050x82, 0x30, 0x57, 0xE9, 9605 0x82, 0x30, 0x57, 0xE9,
96060x87, 0x77, 0x57, 0xE9, 9606 0x87, 0x77, 0x57, 0xE9,
9607 9607
96080x83, 0x38, 0x57, 0xE9, 9608 0x83, 0x38, 0x57, 0xE9,
96090x35, 0x49, 0x51, 0xBD, 9609 0x35, 0x49, 0x51, 0xBD,
9610 9610
96110x84, 0x31, 0x5E, 0xE9, 9611 0x84, 0x31, 0x5E, 0xE9,
96120x30, 0x1F, 0x5F, 0xE9, 9612 0x30, 0x1F, 0x5F, 0xE9,
9613 9613
96140x85, 0x39, 0x5E, 0xE9, 9614 0x85, 0x39, 0x5E, 0xE9,
96150x57, 0x25, 0x20, 0xE9, 9615 0x57, 0x25, 0x20, 0xE9,
9616 9616
96170x2B, 0x48, 0x20, 0xE9, 9617 0x2B, 0x48, 0x20, 0xE9,
96180x1D, 0x37, 0xE1, 0xEA, 9618 0x1D, 0x37, 0xE1, 0xEA,
9619 9619
96200x1E, 0x35, 0xE1, 0xEA, 9620 0x1E, 0x35, 0xE1, 0xEA,
96210x00, 0xE0, 9621 0x00, 0xE0,
96220x26, 0x77, 9622 0x26, 0x77,
9623 9623
96240x24, 0x49, 0x20, 0xE9, 9624 0x24, 0x49, 0x20, 0xE9,
96250xA6, 0xFF, 0x20, 0xEA, 9625 0xA6, 0xFF, 0x20, 0xEA,
9626 9626
96270x16, 0x26, 0x20, 0xE9, 9627 0x16, 0x26, 0x20, 0xE9,
96280x57, 0x2E, 0xBF, 0xEA, 9628 0x57, 0x2E, 0xBF, 0xEA,
9629 9629
96300x1C, 0x46, 0xA0, 0xE8, 9630 0x1C, 0x46, 0xA0, 0xE8,
96310x23, 0x4E, 0xA0, 0xE8, 9631 0x23, 0x4E, 0xA0, 0xE8,
9632 9632
96330x2B, 0x56, 0xA0, 0xE8, 9633 0x2B, 0x56, 0xA0, 0xE8,
96340x1D, 0x47, 0xA0, 0xE8, 9634 0x1D, 0x47, 0xA0, 0xE8,
9635 9635
96360x24, 0x4F, 0xA0, 0xE8, 9636 0x24, 0x4F, 0xA0, 0xE8,
96370x2C, 0x57, 0xA0, 0xE8, 9637 0x2C, 0x57, 0xA0, 0xE8,
9638 9638
96390x1C, 0x00, 9639 0x1C, 0x00,
96400x23, 0x00, 9640 0x23, 0x00,
96410x2B, 0x00, 9641 0x2B, 0x00,
96420x00, 0xE0, 9642 0x00, 0xE0,
9643 9643
96440x1D, 0x00, 9644 0x1D, 0x00,
96450x24, 0x00, 9645 0x24, 0x00,
96460x2C, 0x00, 9646 0x2C, 0x00,
96470x00, 0xE0, 9647 0x00, 0xE0,
9648 9648
96490x1C, 0x65, 9649 0x1C, 0x65,
96500x23, 0x65, 9650 0x23, 0x65,
96510x2B, 0x65, 9651 0x2B, 0x65,
96520x00, 0xE0, 9652 0x00, 0xE0,
9653 9653
96540x1D, 0x65, 9654 0x1D, 0x65,
96550x24, 0x65, 9655 0x24, 0x65,
96560x2C, 0x65, 9656 0x2C, 0x65,
96570x00, 0xE0, 9657 0x00, 0xE0,
9658 9658
96590x1C, 0x23, 0x60, 0xEC, 9659 0x1C, 0x23, 0x60, 0xEC,
96600x36, 0xD7, 0x36, 0xAD, 9660 0x36, 0xD7, 0x36, 0xAD,
9661 9661
96620x2B, 0x80, 0x60, 0xEC, 9662 0x2B, 0x80, 0x60, 0xEC,
96630x1D, 0x24, 0x60, 0xEC, 9663 0x1D, 0x24, 0x60, 0xEC,
9664 9664
96650x3E, 0xD7, 0x3E, 0xAD, 9665 0x3E, 0xD7, 0x3E, 0xAD,
96660x2C, 0x80, 0x60, 0xEC, 9666 0x2C, 0x80, 0x60, 0xEC,
9667 9667
96680x1C, 0x2B, 0xDE, 0xE8, 9668 0x1C, 0x2B, 0xDE, 0xE8,
96690x23, 0x80, 0xDE, 0xE8, 9669 0x23, 0x80, 0xDE, 0xE8,
9670 9670
96710x36, 0x80, 0x36, 0xBD, 9671 0x36, 0x80, 0x36, 0xBD,
96720x3E, 0x80, 0x3E, 0xBD, 9672 0x3E, 0x80, 0x3E, 0xBD,
9673 9673
96740x33, 0xD7, 0x1C, 0xBD, 9674 0x33, 0xD7, 0x1C, 0xBD,
96750x3B, 0xD7, 0x23, 0xBD, 9675 0x3B, 0xD7, 0x23, 0xBD,
9676 9676
96770x46, 0x80, 0x46, 0xCF, 9677 0x46, 0x80, 0x46, 0xCF,
96780x4F, 0x80, 0x4F, 0xCF, 9678 0x4F, 0x80, 0x4F, 0xCF,
9679 9679
96800x56, 0x33, 0x56, 0xCF, 9680 0x56, 0x33, 0x56, 0xCF,
96810x47, 0x3B, 0x47, 0xCF, 9681 0x47, 0x3B, 0x47, 0xCF,
9682 9682
96830xCD, 0xFF, 0x20, 0xEA, 9683 0xCD, 0xFF, 0x20, 0xEA,
96840x00, 0x80, 0x00, 0xE8, 9684 0x00, 0x80, 0x00, 0xE8,
9685 9685
96860x4E, 0x33, 0x4E, 0xCF, 9686 0x4E, 0x33, 0x4E, 0xCF,
96870x57, 0x3B, 0x57, 0xCF, 9687 0x57, 0x3B, 0x57, 0xCF,
9688 9688
96890x94, 0xFF, 0x20, 0xEA, 9689 0x94, 0xFF, 0x20, 0xEA,
96900x57, 0xC0, 0xBF, 0xEA, 9690 0x57, 0xC0, 0xBF, 0xEA,
9691 9691
96920x00, 0x80, 0xA0, 0xE9, 9692 0x00, 0x80, 0xA0, 0xE9,
96930x00, 0x00, 0xD8, 0xEC, 9693 0x00, 0x00, 0xD8, 0xEC,
9694 9694
9695}; 9695};
9696 9696
9697static unsigned char warp_g400_tgzf[] = { 9697static unsigned char warp_g400_tgzf[] = {
9698 9698
96990x00, 0x88, 0x98, 0xE9, 9699 0x00, 0x88, 0x98, 0xE9,
97000x00, 0x80, 0x00, 0xE8, 9700 0x00, 0x80, 0x00, 0xE8,
9701 9701
97020x00, 0x80, 0xA0, 0xE9, 9702 0x00, 0x80, 0xA0, 0xE9,
97030x00, 0x00, 0xD8, 0xEC, 9703 0x00, 0x00, 0xD8, 0xEC,
9704 9704
97050xFF, 0x80, 0xC0, 0xE9, 9705 0xFF, 0x80, 0xC0, 0xE9,
97060x00, 0x80, 0x00, 0xE8, 9706 0x00, 0x80, 0x00, 0xE8,
9707 9707
97080x22, 0x40, 0x48, 0xBF, 9708 0x22, 0x40, 0x48, 0xBF,
97090x2A, 0x40, 0x50, 0xBF, 9709 0x2A, 0x40, 0x50, 0xBF,
9710 9710
97110x32, 0x41, 0x49, 0xBF, 9711 0x32, 0x41, 0x49, 0xBF,
97120x3A, 0x41, 0x51, 0xBF, 9712 0x3A, 0x41, 0x51, 0xBF,
9713 9713
97140xC3, 0x6B, 9714 0xC3, 0x6B,
97150xCB, 0x6B, 9715 0xCB, 0x6B,
97160x00, 0x88, 0x98, 0xE9, 9716 0x00, 0x88, 0x98, 0xE9,
9717 9717
97180x73, 0x7B, 0xC8, 0xEC, 9718 0x73, 0x7B, 0xC8, 0xEC,
97190x96, 0xE2, 9719 0x96, 0xE2,
97200x41, 0x04, 9720 0x41, 0x04,
9721 9721
97220x7B, 0x43, 0xA0, 0xE8, 9722 0x7B, 0x43, 0xA0, 0xE8,
97230x73, 0x4B, 0xA0, 0xE8, 9723 0x73, 0x4B, 0xA0, 0xE8,
9724 9724
97250xAD, 0xEE, 0x29, 0x9F, 9725 0xAD, 0xEE, 0x29, 0x9F,
97260x00, 0xE0, 9726 0x00, 0xE0,
97270x49, 0x04, 9727 0x49, 0x04,
9728 9728
97290x90, 0xE2, 9729 0x90, 0xE2,
97300x51, 0x04, 9730 0x51, 0x04,
97310x31, 0x46, 0xB1, 0xE8, 9731 0x31, 0x46, 0xB1, 0xE8,
9732 9732
97330x49, 0x41, 0xC0, 0xEC, 9733 0x49, 0x41, 0xC0, 0xEC,
97340x39, 0x57, 0xB1, 0xE8, 9734 0x39, 0x57, 0xB1, 0xE8,
9735 9735
97360x00, 0x04, 9736 0x00, 0x04,
97370x46, 0xE2, 9737 0x46, 0xE2,
97380x73, 0x53, 0xA0, 0xE8, 9738 0x73, 0x53, 0xA0, 0xE8,
9739 9739
97400x51, 0x41, 0xC0, 0xEC, 9740 0x51, 0x41, 0xC0, 0xEC,
97410x31, 0x00, 9741 0x31, 0x00,
97420x39, 0x00, 9742 0x39, 0x00,
9743 9743
97440x5D, 0x80, 0x15, 0xEA, 9744 0x5D, 0x80, 0x15, 0xEA,
97450x08, 0x04, 9745 0x08, 0x04,
97460x10, 0x04, 9746 0x10, 0x04,
9747 9747
97480x51, 0x49, 0xC0, 0xEC, 9748 0x51, 0x49, 0xC0, 0xEC,
97490x2F, 0x41, 0x60, 0xEA, 9749 0x2F, 0x41, 0x60, 0xEA,
9750 9750
97510x31, 0x20, 9751 0x31, 0x20,
97520x39, 0x20, 9752 0x39, 0x20,
97530x1F, 0x42, 0xA0, 0xE8, 9753 0x1F, 0x42, 0xA0, 0xE8,
9754 9754
97550x2A, 0x42, 0x4A, 0xBF, 9755 0x2A, 0x42, 0x4A, 0xBF,
97560x27, 0x4A, 0xA0, 0xE8, 9756 0x27, 0x4A, 0xA0, 0xE8,
9757 9757
97580x1A, 0x42, 0x52, 0xBF, 9758 0x1A, 0x42, 0x52, 0xBF,
97590x1E, 0x49, 0x60, 0xEA, 9759 0x1E, 0x49, 0x60, 0xEA,
9760 9760
97610x73, 0x7B, 0xC8, 0xEC, 9761 0x73, 0x7B, 0xC8, 0xEC,
97620x26, 0x51, 0x60, 0xEA, 9762 0x26, 0x51, 0x60, 0xEA,
9763 9763
97640x32, 0x40, 0x48, 0xBD, 9764 0x32, 0x40, 0x48, 0xBD,
97650x22, 0x40, 0x50, 0xBD, 9765 0x22, 0x40, 0x50, 0xBD,
9766 9766
97670x12, 0x41, 0x49, 0xBD, 9767 0x12, 0x41, 0x49, 0xBD,
97680x3A, 0x41, 0x51, 0xBD, 9768 0x3A, 0x41, 0x51, 0xBD,
9769 9769
97700xBF, 0x2F, 0x26, 0xBD, 9770 0xBF, 0x2F, 0x26, 0xBD,
97710x00, 0xE0, 9771 0x00, 0xE0,
97720x7B, 0x72, 9772 0x7B, 0x72,
9773 9773
97740x32, 0x20, 9774 0x32, 0x20,
97750x22, 0x20, 9775 0x22, 0x20,
97760x12, 0x20, 9776 0x12, 0x20,
97770x3A, 0x20, 9777 0x3A, 0x20,
9778 9778
97790x46, 0x31, 0x46, 0xBF, 9779 0x46, 0x31, 0x46, 0xBF,
97800x4E, 0x31, 0x4E, 0xBF, 9780 0x4E, 0x31, 0x4E, 0xBF,
9781 9781
97820xB3, 0xE2, 0x2D, 0x9F, 9782 0xB3, 0xE2, 0x2D, 0x9F,
97830x00, 0x80, 0x00, 0xE8, 9783 0x00, 0x80, 0x00, 0xE8,
9784 9784
97850x56, 0x31, 0x56, 0xBF, 9785 0x56, 0x31, 0x56, 0xBF,
97860x47, 0x39, 0x47, 0xBF, 9786 0x47, 0x39, 0x47, 0xBF,
9787 9787
97880x4F, 0x39, 0x4F, 0xBF, 9788 0x4F, 0x39, 0x4F, 0xBF,
97890x57, 0x39, 0x57, 0xBF, 9789 0x57, 0x39, 0x57, 0xBF,
9790 9790
97910x4F, 0x80, 0x07, 0xEA, 9791 0x4F, 0x80, 0x07, 0xEA,
97920x24, 0x41, 0x20, 0xE9, 9792 0x24, 0x41, 0x20, 0xE9,
9793 9793
97940x42, 0x73, 0xF8, 0xEC, 9794 0x42, 0x73, 0xF8, 0xEC,
97950x00, 0xE0, 9795 0x00, 0xE0,
97960x2D, 0x73, 9796 0x2D, 0x73,
9797 9797
97980x33, 0x72, 9798 0x33, 0x72,
97990x0C, 0xE3, 9799 0x0C, 0xE3,
98000xA5, 0x2F, 0x1E, 0xBD, 9800 0xA5, 0x2F, 0x1E, 0xBD,
9801 9801
98020x43, 0x43, 0x2D, 0xDF, 9802 0x43, 0x43, 0x2D, 0xDF,
98030x4B, 0x4B, 0x2D, 0xDF, 9803 0x4B, 0x4B, 0x2D, 0xDF,
9804 9804
98050xAE, 0x1E, 0x26, 0xBD, 9805 0xAE, 0x1E, 0x26, 0xBD,
98060x58, 0xE3, 9806 0x58, 0xE3,
98070x33, 0x66, 9807 0x33, 0x66,
9808 9808
98090x53, 0x53, 0x2D, 0xDF, 9809 0x53, 0x53, 0x2D, 0xDF,
98100x00, 0x80, 0x00, 0xE8, 9810 0x00, 0x80, 0x00, 0xE8,
9811 9811
98120xB8, 0x38, 0x33, 0xBF, 9812 0xB8, 0x38, 0x33, 0xBF,
98130x00, 0xE0, 9813 0x00, 0xE0,
98140x59, 0xE3, 9814 0x59, 0xE3,
9815 9815
98160x1E, 0x12, 0x41, 0xE9, 9816 0x1E, 0x12, 0x41, 0xE9,
98170x1A, 0x22, 0x41, 0xE9, 9817 0x1A, 0x22, 0x41, 0xE9,
9818 9818
98190x2B, 0x40, 0x3D, 0xE9, 9819 0x2B, 0x40, 0x3D, 0xE9,
98200x3F, 0x4B, 0xA0, 0xE8, 9820 0x3F, 0x4B, 0xA0, 0xE8,
9821 9821
98220x2D, 0x73, 9822 0x2D, 0x73,
98230x30, 0x76, 9823 0x30, 0x76,
98240x05, 0x80, 0x3D, 0xEA, 9824 0x05, 0x80, 0x3D, 0xEA,
9825 9825
98260x37, 0x43, 0xA0, 0xE8, 9826 0x37, 0x43, 0xA0, 0xE8,
98270x3D, 0x53, 0xA0, 0xE8, 9827 0x3D, 0x53, 0xA0, 0xE8,
9828 9828
98290x48, 0x70, 0xF8, 0xEC, 9829 0x48, 0x70, 0xF8, 0xEC,
98300x2B, 0x48, 0x3C, 0xE9, 9830 0x2B, 0x48, 0x3C, 0xE9,
9831 9831
98320x1F, 0x27, 0xBC, 0xE8, 9832 0x1F, 0x27, 0xBC, 0xE8,
98330x00, 0x80, 0x00, 0xE8, 9833 0x00, 0x80, 0x00, 0xE8,
9834 9834
98350x00, 0x80, 0x00, 0xE8, 9835 0x00, 0x80, 0x00, 0xE8,
98360x00, 0x80, 0x00, 0xE8, 9836 0x00, 0x80, 0x00, 0xE8,
9837 9837
98380x15, 0xC0, 0x20, 0xE9, 9838 0x15, 0xC0, 0x20, 0xE9,
98390x15, 0xC0, 0x20, 0xE9, 9839 0x15, 0xC0, 0x20, 0xE9,
9840 9840
98410x15, 0xC0, 0x20, 0xE9, 9841 0x15, 0xC0, 0x20, 0xE9,
98420x15, 0xC0, 0x20, 0xE9, 9842 0x15, 0xC0, 0x20, 0xE9,
9843 9843
98440x18, 0x3A, 0x41, 0xE9, 9844 0x18, 0x3A, 0x41, 0xE9,
98450x1D, 0x32, 0x41, 0xE9, 9845 0x1D, 0x32, 0x41, 0xE9,
9846 9846
98470x2A, 0x40, 0x20, 0xE9, 9847 0x2A, 0x40, 0x20, 0xE9,
98480x56, 0x3D, 0x56, 0xDF, 9848 0x56, 0x3D, 0x56, 0xDF,
9849 9849
98500x46, 0x37, 0x46, 0xDF, 9850 0x46, 0x37, 0x46, 0xDF,
98510x4E, 0x3F, 0x4E, 0xDF, 9851 0x4E, 0x3F, 0x4E, 0xDF,
9852 9852
98530x16, 0x30, 0x20, 0xE9, 9853 0x16, 0x30, 0x20, 0xE9,
98540x4F, 0x3F, 0x4F, 0xDF, 9854 0x4F, 0x3F, 0x4F, 0xDF,
9855 9855
98560x32, 0x32, 0x2D, 0xDF, 9856 0x32, 0x32, 0x2D, 0xDF,
98570x22, 0x22, 0x2D, 0xDF, 9857 0x22, 0x22, 0x2D, 0xDF,
9858 9858
98590x12, 0x12, 0x2D, 0xDF, 9859 0x12, 0x12, 0x2D, 0xDF,
98600x3A, 0x3A, 0x2D, 0xDF, 9860 0x3A, 0x3A, 0x2D, 0xDF,
9861 9861
98620x47, 0x37, 0x47, 0xDF, 9862 0x47, 0x37, 0x47, 0xDF,
98630x57, 0x3D, 0x57, 0xDF, 9863 0x57, 0x3D, 0x57, 0xDF,
9864 9864
98650x3D, 0xCF, 0x74, 0xC0, 9865 0x3D, 0xCF, 0x74, 0xC0,
98660x37, 0xCF, 0x74, 0xC4, 9866 0x37, 0xCF, 0x74, 0xC4,
9867 9867
98680x39, 0xE5, 0x2C, 0x9F, 9868 0x39, 0xE5, 0x2C, 0x9F,
98690x34, 0x80, 0x20, 0xE9, 9869 0x34, 0x80, 0x20, 0xE9,
9870 9870
98710x31, 0x53, 0x2F, 0x9F, 9871 0x31, 0x53, 0x2F, 0x9F,
98720x00, 0x80, 0x00, 0xE8, 9872 0x00, 0x80, 0x00, 0xE8,
9873 9873
98740x88, 0x73, 0x5E, 0xE9, 9874 0x88, 0x73, 0x5E, 0xE9,
98750x00, 0x80, 0x00, 0xE8, 9875 0x00, 0x80, 0x00, 0xE8,
9876 9876
98770x27, 0xCF, 0x75, 0xC6, 9877 0x27, 0xCF, 0x75, 0xC6,
98780x3C, 0x3D, 0x20, 0xE9, 9878 0x3C, 0x3D, 0x20, 0xE9,
9879 9879
98800x0A, 0x44, 0x4C, 0xB0, 9880 0x0A, 0x44, 0x4C, 0xB0,
98810x02, 0x44, 0x54, 0xB0, 9881 0x02, 0x44, 0x54, 0xB0,
9882 9882
98830x2A, 0x44, 0x4C, 0xB2, 9883 0x2A, 0x44, 0x4C, 0xB2,
98840x1A, 0x44, 0x54, 0xB2, 9884 0x1A, 0x44, 0x54, 0xB2,
9885 9885
98860x20, 0x80, 0x3A, 0xEA, 9886 0x20, 0x80, 0x3A, 0xEA,
98870x0A, 0x20, 9887 0x0A, 0x20,
98880x02, 0x20, 9888 0x02, 0x20,
9889 9889
98900x3D, 0xCF, 0x74, 0xC2, 9890 0x3D, 0xCF, 0x74, 0xC2,
98910x2A, 0x20, 9891 0x2A, 0x20,
98920x1A, 0x20, 9892 0x1A, 0x20,
9893 9893
98940x30, 0x50, 0x2E, 0x9F, 9894 0x30, 0x50, 0x2E, 0x9F,
98950x32, 0x31, 0x5F, 0xE9, 9895 0x32, 0x31, 0x5F, 0xE9,
9896 9896
98970x38, 0x21, 0x2C, 0x9F, 9897 0x38, 0x21, 0x2C, 0x9F,
98980x33, 0x39, 0x5F, 0xE9, 9898 0x33, 0x39, 0x5F, 0xE9,
9899 9899
99000x31, 0x53, 0x2F, 0x9F, 9900 0x31, 0x53, 0x2F, 0x9F,
99010x31, 0x27, 0x20, 0xE9, 9901 0x31, 0x27, 0x20, 0xE9,
9902 9902
99030x0A, 0x44, 0x4C, 0xB4, 9903 0x0A, 0x44, 0x4C, 0xB4,
99040x02, 0x44, 0x54, 0xB4, 9904 0x02, 0x44, 0x54, 0xB4,
9905 9905
99060x2A, 0x45, 0x4D, 0xB6, 9906 0x2A, 0x45, 0x4D, 0xB6,
99070x1A, 0x45, 0x55, 0xB6, 9907 0x1A, 0x45, 0x55, 0xB6,
9908 9908
99090x39, 0xE5, 0x2C, 0x9F, 9909 0x39, 0xE5, 0x2C, 0x9F,
99100x38, 0x3D, 0x20, 0xE9, 9910 0x38, 0x3D, 0x20, 0xE9,
9911 9911
99120x0A, 0x20, 9912 0x0A, 0x20,
99130x02, 0x20, 9913 0x02, 0x20,
99140x2A, 0x20, 9914 0x2A, 0x20,
99150x1A, 0x20, 9915 0x1A, 0x20,
9916 9916
99170x0A, 0x47, 0x4F, 0xBF, 9917 0x0A, 0x47, 0x4F, 0xBF,
99180x02, 0x47, 0x57, 0xBF, 9918 0x02, 0x47, 0x57, 0xBF,
9919 9919
99200x30, 0x50, 0x2E, 0x9F, 9920 0x30, 0x50, 0x2E, 0x9F,
99210x3E, 0x30, 0x4F, 0xE9, 9921 0x3E, 0x30, 0x4F, 0xE9,
9922 9922
99230x38, 0x21, 0x2C, 0x9F, 9923 0x38, 0x21, 0x2C, 0x9F,
99240x3F, 0x38, 0x4F, 0xE9, 9924 0x3F, 0x38, 0x4F, 0xE9,
9925 9925
99260x2A, 0x46, 0x4E, 0xBF, 9926 0x2A, 0x46, 0x4E, 0xBF,
99270x1A, 0x46, 0x56, 0xBF, 9927 0x1A, 0x46, 0x56, 0xBF,
9928 9928
99290x31, 0x53, 0x2F, 0x9F, 9929 0x31, 0x53, 0x2F, 0x9F,
99300x3A, 0x31, 0x4F, 0xE9, 9930 0x3A, 0x31, 0x4F, 0xE9,
9931 9931
99320x39, 0xE5, 0x2C, 0x9F, 9932 0x39, 0xE5, 0x2C, 0x9F,
99330x3B, 0x39, 0x4F, 0xE9, 9933 0x3B, 0x39, 0x4F, 0xE9,
9934 9934
99350x31, 0x53, 0x2F, 0x9F, 9935 0x31, 0x53, 0x2F, 0x9F,
99360x36, 0x30, 0x4F, 0xE9, 9936 0x36, 0x30, 0x4F, 0xE9,
9937 9937
99380x39, 0xE5, 0x2C, 0x9F, 9938 0x39, 0xE5, 0x2C, 0x9F,
99390x37, 0x38, 0x4F, 0xE9, 9939 0x37, 0x38, 0x4F, 0xE9,
9940 9940
99410x2A, 0x43, 0x4B, 0xBF, 9941 0x2A, 0x43, 0x4B, 0xBF,
99420x1A, 0x43, 0x53, 0xBF, 9942 0x1A, 0x43, 0x53, 0xBF,
9943 9943
99440x30, 0x50, 0x2E, 0x9F, 9944 0x30, 0x50, 0x2E, 0x9F,
99450x35, 0x31, 0x4F, 0xE9, 9945 0x35, 0x31, 0x4F, 0xE9,
9946 9946
99470x38, 0x21, 0x2C, 0x9F, 9947 0x38, 0x21, 0x2C, 0x9F,
99480x39, 0x39, 0x4F, 0xE9, 9948 0x39, 0x39, 0x4F, 0xE9,
9949 9949
99500x31, 0x53, 0x2F, 0x9F, 9950 0x31, 0x53, 0x2F, 0x9F,
99510x80, 0x31, 0x57, 0xE9, 9951 0x80, 0x31, 0x57, 0xE9,
9952 9952
99530x39, 0xE5, 0x2C, 0x9F, 9953 0x39, 0xE5, 0x2C, 0x9F,
99540x81, 0x39, 0x57, 0xE9, 9954 0x81, 0x39, 0x57, 0xE9,
9955 9955
99560x37, 0x48, 0x50, 0xBD, 9956 0x37, 0x48, 0x50, 0xBD,
99570x8A, 0x36, 0x20, 0xE9, 9957 0x8A, 0x36, 0x20, 0xE9,
9958 9958
99590x86, 0x76, 0x57, 0xE9, 9959 0x86, 0x76, 0x57, 0xE9,
99600x8B, 0x3E, 0x20, 0xE9, 9960 0x8B, 0x3E, 0x20, 0xE9,
9961 9961
99620x82, 0x30, 0x57, 0xE9, 9962 0x82, 0x30, 0x57, 0xE9,
99630x87, 0x77, 0x57, 0xE9, 9963 0x87, 0x77, 0x57, 0xE9,
9964 9964
99650x83, 0x38, 0x57, 0xE9, 9965 0x83, 0x38, 0x57, 0xE9,
99660x35, 0x49, 0x51, 0xBD, 9966 0x35, 0x49, 0x51, 0xBD,
9967 9967
99680x84, 0x31, 0x5E, 0xE9, 9968 0x84, 0x31, 0x5E, 0xE9,
99690x30, 0x1F, 0x5F, 0xE9, 9969 0x30, 0x1F, 0x5F, 0xE9,
9970 9970
99710x85, 0x39, 0x5E, 0xE9, 9971 0x85, 0x39, 0x5E, 0xE9,
99720x57, 0x25, 0x20, 0xE9, 9972 0x57, 0x25, 0x20, 0xE9,
9973 9973
99740x2B, 0x48, 0x20, 0xE9, 9974 0x2B, 0x48, 0x20, 0xE9,
99750x1D, 0x37, 0xE1, 0xEA, 9975 0x1D, 0x37, 0xE1, 0xEA,
9976 9976
99770x1E, 0x35, 0xE1, 0xEA, 9977 0x1E, 0x35, 0xE1, 0xEA,
99780x00, 0xE0, 9978 0x00, 0xE0,
99790x26, 0x77, 9979 0x26, 0x77,
9980 9980
99810x24, 0x49, 0x20, 0xE9, 9981 0x24, 0x49, 0x20, 0xE9,
99820xAA, 0xFF, 0x20, 0xEA, 9982 0xAA, 0xFF, 0x20, 0xEA,
9983 9983
99840x16, 0x26, 0x20, 0xE9, 9984 0x16, 0x26, 0x20, 0xE9,
99850x57, 0x2E, 0xBF, 0xEA, 9985 0x57, 0x2E, 0xBF, 0xEA,
9986 9986
99870x1C, 0x46, 0xA0, 0xE8, 9987 0x1C, 0x46, 0xA0, 0xE8,
99880x23, 0x4E, 0xA0, 0xE8, 9988 0x23, 0x4E, 0xA0, 0xE8,
9989 9989
99900x2B, 0x56, 0xA0, 0xE8, 9990 0x2B, 0x56, 0xA0, 0xE8,
99910x1D, 0x47, 0xA0, 0xE8, 9991 0x1D, 0x47, 0xA0, 0xE8,
9992 9992
99930x24, 0x4F, 0xA0, 0xE8, 9993 0x24, 0x4F, 0xA0, 0xE8,
99940x2C, 0x57, 0xA0, 0xE8, 9994 0x2C, 0x57, 0xA0, 0xE8,
9995 9995
99960x1C, 0x00, 9996 0x1C, 0x00,
99970x23, 0x00, 9997 0x23, 0x00,
99980x2B, 0x00, 9998 0x2B, 0x00,
99990x00, 0xE0, 9999 0x00, 0xE0,
10000 10000
100010x1D, 0x00, 10001 0x1D, 0x00,
100020x24, 0x00, 10002 0x24, 0x00,
100030x2C, 0x00, 10003 0x2C, 0x00,
100040x00, 0xE0, 10004 0x00, 0xE0,
10005 10005
100060x1C, 0x65, 10006 0x1C, 0x65,
100070x23, 0x65, 10007 0x23, 0x65,
100080x2B, 0x65, 10008 0x2B, 0x65,
100090x00, 0xE0, 10009 0x00, 0xE0,
10010 10010
100110x1D, 0x65, 10011 0x1D, 0x65,
100120x24, 0x65, 10012 0x24, 0x65,
100130x2C, 0x65, 10013 0x2C, 0x65,
100140x00, 0xE0, 10014 0x00, 0xE0,
10015 10015
100160x1C, 0x23, 0x60, 0xEC, 10016 0x1C, 0x23, 0x60, 0xEC,
100170x36, 0xD7, 0x36, 0xAD, 10017 0x36, 0xD7, 0x36, 0xAD,
10018 10018
100190x2B, 0x80, 0x60, 0xEC, 10019 0x2B, 0x80, 0x60, 0xEC,
100200x1D, 0x24, 0x60, 0xEC, 10020 0x1D, 0x24, 0x60, 0xEC,
10021 10021
100220x3E, 0xD7, 0x3E, 0xAD, 10022 0x3E, 0xD7, 0x3E, 0xAD,
100230x2C, 0x80, 0x60, 0xEC, 10023 0x2C, 0x80, 0x60, 0xEC,
10024 10024
100250x1C, 0x2B, 0xDE, 0xE8, 10025 0x1C, 0x2B, 0xDE, 0xE8,
100260x23, 0x80, 0xDE, 0xE8, 10026 0x23, 0x80, 0xDE, 0xE8,
10027 10027
100280x36, 0x80, 0x36, 0xBD, 10028 0x36, 0x80, 0x36, 0xBD,
100290x3E, 0x80, 0x3E, 0xBD, 10029 0x3E, 0x80, 0x3E, 0xBD,
10030 10030
100310x33, 0xD7, 0x1C, 0xBD, 10031 0x33, 0xD7, 0x1C, 0xBD,
100320x3B, 0xD7, 0x23, 0xBD, 10032 0x3B, 0xD7, 0x23, 0xBD,
10033 10033
100340x46, 0x80, 0x46, 0xCF, 10034 0x46, 0x80, 0x46, 0xCF,
100350x4F, 0x80, 0x4F, 0xCF, 10035 0x4F, 0x80, 0x4F, 0xCF,
10036 10036
100370x56, 0x33, 0x56, 0xCF, 10037 0x56, 0x33, 0x56, 0xCF,
100380x47, 0x3B, 0x47, 0xCF, 10038 0x47, 0x3B, 0x47, 0xCF,
10039 10039
100400xD3, 0xFF, 0x20, 0xEA, 10040 0xD3, 0xFF, 0x20, 0xEA,
100410x00, 0x80, 0x00, 0xE8, 10041 0x00, 0x80, 0x00, 0xE8,
10042 10042
100430x4E, 0x33, 0x4E, 0xCF, 10043 0x4E, 0x33, 0x4E, 0xCF,
100440x57, 0x3B, 0x57, 0xCF, 10044 0x57, 0x3B, 0x57, 0xCF,
10045 10045
100460x98, 0xFF, 0x20, 0xEA, 10046 0x98, 0xFF, 0x20, 0xEA,
100470x57, 0xC0, 0xBF, 0xEA, 10047 0x57, 0xC0, 0xBF, 0xEA,
10048 10048
100490x00, 0x80, 0xA0, 0xE9, 10049 0x00, 0x80, 0xA0, 0xE9,
100500x00, 0x00, 0xD8, 0xEC, 10050 0x00, 0x00, 0xD8, 0xEC,
10051 10051
10052}; 10052};
10053 10053
10054static unsigned char warp_g400_tgzs[] = { 10054static unsigned char warp_g400_tgzs[] = {
10055 10055
100560x00, 0x88, 0x98, 0xE9, 10056 0x00, 0x88, 0x98, 0xE9,
100570x00, 0x80, 0x00, 0xE8, 10057 0x00, 0x80, 0x00, 0xE8,
10058 10058
100590x00, 0x80, 0xA0, 0xE9, 10059 0x00, 0x80, 0xA0, 0xE9,
100600x00, 0x00, 0xD8, 0xEC, 10060 0x00, 0x00, 0xD8, 0xEC,
10061 10061
100620xFF, 0x80, 0xC0, 0xE9, 10062 0xFF, 0x80, 0xC0, 0xE9,
100630x00, 0x80, 0x00, 0xE8, 10063 0x00, 0x80, 0x00, 0xE8,
10064 10064
100650x22, 0x40, 0x48, 0xBF, 10065 0x22, 0x40, 0x48, 0xBF,
100660x2A, 0x40, 0x50, 0xBF, 10066 0x2A, 0x40, 0x50, 0xBF,
10067 10067
100680x32, 0x41, 0x49, 0xBF, 10068 0x32, 0x41, 0x49, 0xBF,
100690x3A, 0x41, 0x51, 0xBF, 10069 0x3A, 0x41, 0x51, 0xBF,
10070 10070
100710xC3, 0x6B, 10071 0xC3, 0x6B,
100720xCB, 0x6B, 10072 0xCB, 0x6B,
100730x00, 0x88, 0x98, 0xE9, 10073 0x00, 0x88, 0x98, 0xE9,
10074 10074
100750x73, 0x7B, 0xC8, 0xEC, 10075 0x73, 0x7B, 0xC8, 0xEC,
100760x96, 0xE2, 10076 0x96, 0xE2,
100770x41, 0x04, 10077 0x41, 0x04,
10078 10078
100790x7B, 0x43, 0xA0, 0xE8, 10079 0x7B, 0x43, 0xA0, 0xE8,
100800x73, 0x4B, 0xA0, 0xE8, 10080 0x73, 0x4B, 0xA0, 0xE8,
10081 10081
100820xAD, 0xEE, 0x29, 0x9F, 10082 0xAD, 0xEE, 0x29, 0x9F,
100830x00, 0xE0, 10083 0x00, 0xE0,
100840x49, 0x04, 10084 0x49, 0x04,
10085 10085
100860x90, 0xE2, 10086 0x90, 0xE2,
100870x51, 0x04, 10087 0x51, 0x04,
100880x31, 0x46, 0xB1, 0xE8, 10088 0x31, 0x46, 0xB1, 0xE8,
10089 10089
100900x49, 0x41, 0xC0, 0xEC, 10090 0x49, 0x41, 0xC0, 0xEC,
100910x39, 0x57, 0xB1, 0xE8, 10091 0x39, 0x57, 0xB1, 0xE8,
10092 10092
100930x00, 0x04, 10093 0x00, 0x04,
100940x46, 0xE2, 10094 0x46, 0xE2,
100950x73, 0x53, 0xA0, 0xE8, 10095 0x73, 0x53, 0xA0, 0xE8,
10096 10096
100970x51, 0x41, 0xC0, 0xEC, 10097 0x51, 0x41, 0xC0, 0xEC,
100980x31, 0x00, 10098 0x31, 0x00,
100990x39, 0x00, 10099 0x39, 0x00,
10100 10100
101010x65, 0x80, 0x15, 0xEA, 10101 0x65, 0x80, 0x15, 0xEA,
101020x08, 0x04, 10102 0x08, 0x04,
101030x10, 0x04, 10103 0x10, 0x04,
10104 10104
101050x51, 0x49, 0xC0, 0xEC, 10105 0x51, 0x49, 0xC0, 0xEC,
101060x2F, 0x41, 0x60, 0xEA, 10106 0x2F, 0x41, 0x60, 0xEA,
10107 10107
101080x31, 0x20, 10108 0x31, 0x20,
101090x39, 0x20, 10109 0x39, 0x20,
101100x1F, 0x42, 0xA0, 0xE8, 10110 0x1F, 0x42, 0xA0, 0xE8,
10111 10111
101120x2A, 0x42, 0x4A, 0xBF, 10112 0x2A, 0x42, 0x4A, 0xBF,
101130x27, 0x4A, 0xA0, 0xE8, 10113 0x27, 0x4A, 0xA0, 0xE8,
10114 10114
101150x1A, 0x42, 0x52, 0xBF, 10115 0x1A, 0x42, 0x52, 0xBF,
101160x1E, 0x49, 0x60, 0xEA, 10116 0x1E, 0x49, 0x60, 0xEA,
10117 10117
101180x73, 0x7B, 0xC8, 0xEC, 10118 0x73, 0x7B, 0xC8, 0xEC,
101190x26, 0x51, 0x60, 0xEA, 10119 0x26, 0x51, 0x60, 0xEA,
10120 10120
101210x32, 0x40, 0x48, 0xBD, 10121 0x32, 0x40, 0x48, 0xBD,
101220x22, 0x40, 0x50, 0xBD, 10122 0x22, 0x40, 0x50, 0xBD,
10123 10123
101240x12, 0x41, 0x49, 0xBD, 10124 0x12, 0x41, 0x49, 0xBD,
101250x3A, 0x41, 0x51, 0xBD, 10125 0x3A, 0x41, 0x51, 0xBD,
10126 10126
101270xBF, 0x2F, 0x26, 0xBD, 10127 0xBF, 0x2F, 0x26, 0xBD,
101280x00, 0xE0, 10128 0x00, 0xE0,
101290x7B, 0x72, 10129 0x7B, 0x72,
10130 10130
101310x32, 0x20, 10131 0x32, 0x20,
101320x22, 0x20, 10132 0x22, 0x20,
101330x12, 0x20, 10133 0x12, 0x20,
101340x3A, 0x20, 10134 0x3A, 0x20,
10135 10135
101360x46, 0x31, 0x46, 0xBF, 10136 0x46, 0x31, 0x46, 0xBF,
101370x4E, 0x31, 0x4E, 0xBF, 10137 0x4E, 0x31, 0x4E, 0xBF,
10138 10138
101390xB3, 0xE2, 0x2D, 0x9F, 10139 0xB3, 0xE2, 0x2D, 0x9F,
101400x00, 0x80, 0x00, 0xE8, 10140 0x00, 0x80, 0x00, 0xE8,
10141 10141
101420x56, 0x31, 0x56, 0xBF, 10142 0x56, 0x31, 0x56, 0xBF,
101430x47, 0x39, 0x47, 0xBF, 10143 0x47, 0x39, 0x47, 0xBF,
10144 10144
101450x4F, 0x39, 0x4F, 0xBF, 10145 0x4F, 0x39, 0x4F, 0xBF,
101460x57, 0x39, 0x57, 0xBF, 10146 0x57, 0x39, 0x57, 0xBF,
10147 10147
101480x57, 0x80, 0x07, 0xEA, 10148 0x57, 0x80, 0x07, 0xEA,
101490x24, 0x41, 0x20, 0xE9, 10149 0x24, 0x41, 0x20, 0xE9,
10150 10150
101510x42, 0x73, 0xF8, 0xEC, 10151 0x42, 0x73, 0xF8, 0xEC,
101520x00, 0xE0, 10152 0x00, 0xE0,
101530x2D, 0x73, 10153 0x2D, 0x73,
10154 10154
101550x33, 0x72, 10155 0x33, 0x72,
101560x0C, 0xE3, 10156 0x0C, 0xE3,
101570xA5, 0x2F, 0x1E, 0xBD, 10157 0xA5, 0x2F, 0x1E, 0xBD,
10158 10158
101590x43, 0x43, 0x2D, 0xDF, 10159 0x43, 0x43, 0x2D, 0xDF,
101600x4B, 0x4B, 0x2D, 0xDF, 10160 0x4B, 0x4B, 0x2D, 0xDF,
10161 10161
101620xAE, 0x1E, 0x26, 0xBD, 10162 0xAE, 0x1E, 0x26, 0xBD,
101630x58, 0xE3, 10163 0x58, 0xE3,
101640x33, 0x66, 10164 0x33, 0x66,
10165 10165
101660x53, 0x53, 0x2D, 0xDF, 10166 0x53, 0x53, 0x2D, 0xDF,
101670x00, 0x80, 0x00, 0xE8, 10167 0x00, 0x80, 0x00, 0xE8,
10168 10168
101690xB8, 0x38, 0x33, 0xBF, 10169 0xB8, 0x38, 0x33, 0xBF,
101700x00, 0xE0, 10170 0x00, 0xE0,
101710x59, 0xE3, 10171 0x59, 0xE3,
10172 10172
101730x1E, 0x12, 0x41, 0xE9, 10173 0x1E, 0x12, 0x41, 0xE9,
101740x1A, 0x22, 0x41, 0xE9, 10174 0x1A, 0x22, 0x41, 0xE9,
10175 10175
101760x2B, 0x40, 0x3D, 0xE9, 10176 0x2B, 0x40, 0x3D, 0xE9,
101770x3F, 0x4B, 0xA0, 0xE8, 10177 0x3F, 0x4B, 0xA0, 0xE8,
10178 10178
101790x2D, 0x73, 10179 0x2D, 0x73,
101800x30, 0x76, 10180 0x30, 0x76,
101810x05, 0x80, 0x3D, 0xEA, 10181 0x05, 0x80, 0x3D, 0xEA,
10182 10182
101830x37, 0x43, 0xA0, 0xE8, 10183 0x37, 0x43, 0xA0, 0xE8,
101840x3D, 0x53, 0xA0, 0xE8, 10184 0x3D, 0x53, 0xA0, 0xE8,
10185 10185
101860x48, 0x70, 0xF8, 0xEC, 10186 0x48, 0x70, 0xF8, 0xEC,
101870x2B, 0x48, 0x3C, 0xE9, 10187 0x2B, 0x48, 0x3C, 0xE9,
10188 10188
101890x1F, 0x27, 0xBC, 0xE8, 10189 0x1F, 0x27, 0xBC, 0xE8,
101900x00, 0x80, 0x00, 0xE8, 10190 0x00, 0x80, 0x00, 0xE8,
10191 10191
101920x00, 0x80, 0x00, 0xE8, 10192 0x00, 0x80, 0x00, 0xE8,
101930x00, 0x80, 0x00, 0xE8, 10193 0x00, 0x80, 0x00, 0xE8,
10194 10194
101950x15, 0xC0, 0x20, 0xE9, 10195 0x15, 0xC0, 0x20, 0xE9,
101960x15, 0xC0, 0x20, 0xE9, 10196 0x15, 0xC0, 0x20, 0xE9,
10197 10197
101980x15, 0xC0, 0x20, 0xE9, 10198 0x15, 0xC0, 0x20, 0xE9,
101990x15, 0xC0, 0x20, 0xE9, 10199 0x15, 0xC0, 0x20, 0xE9,
10200 10200
102010x18, 0x3A, 0x41, 0xE9, 10201 0x18, 0x3A, 0x41, 0xE9,
102020x1D, 0x32, 0x41, 0xE9, 10202 0x1D, 0x32, 0x41, 0xE9,
10203 10203
102040x2A, 0x40, 0x20, 0xE9, 10204 0x2A, 0x40, 0x20, 0xE9,
102050x56, 0x3D, 0x56, 0xDF, 10205 0x56, 0x3D, 0x56, 0xDF,
10206 10206
102070x46, 0x37, 0x46, 0xDF, 10207 0x46, 0x37, 0x46, 0xDF,
102080x4E, 0x3F, 0x4E, 0xDF, 10208 0x4E, 0x3F, 0x4E, 0xDF,
10209 10209
102100x16, 0x30, 0x20, 0xE9, 10210 0x16, 0x30, 0x20, 0xE9,
102110x4F, 0x3F, 0x4F, 0xDF, 10211 0x4F, 0x3F, 0x4F, 0xDF,
10212 10212
102130x47, 0x37, 0x47, 0xDF, 10213 0x47, 0x37, 0x47, 0xDF,
102140x57, 0x3D, 0x57, 0xDF, 10214 0x57, 0x3D, 0x57, 0xDF,
10215 10215
102160x32, 0x32, 0x2D, 0xDF, 10216 0x32, 0x32, 0x2D, 0xDF,
102170x22, 0x22, 0x2D, 0xDF, 10217 0x22, 0x22, 0x2D, 0xDF,
10218 10218
102190x12, 0x12, 0x2D, 0xDF, 10219 0x12, 0x12, 0x2D, 0xDF,
102200x3A, 0x3A, 0x2D, 0xDF, 10220 0x3A, 0x3A, 0x2D, 0xDF,
10221 10221
102220x27, 0xCF, 0x74, 0xC2, 10222 0x27, 0xCF, 0x74, 0xC2,
102230x37, 0xCF, 0x74, 0xC4, 10223 0x37, 0xCF, 0x74, 0xC4,
10224 10224
102250x0A, 0x44, 0x4C, 0xB0, 10225 0x0A, 0x44, 0x4C, 0xB0,
102260x02, 0x44, 0x54, 0xB0, 10226 0x02, 0x44, 0x54, 0xB0,
10227 10227
102280x3D, 0xCF, 0x74, 0xC0, 10228 0x3D, 0xCF, 0x74, 0xC0,
102290x34, 0x37, 0x20, 0xE9, 10229 0x34, 0x37, 0x20, 0xE9,
10230 10230
102310x31, 0x53, 0x2F, 0x9F, 10231 0x31, 0x53, 0x2F, 0x9F,
102320x38, 0x27, 0x20, 0xE9, 10232 0x38, 0x27, 0x20, 0xE9,
10233 10233
102340x39, 0xE5, 0x2C, 0x9F, 10234 0x39, 0xE5, 0x2C, 0x9F,
102350x3C, 0x3D, 0x20, 0xE9, 10235 0x3C, 0x3D, 0x20, 0xE9,
10236 10236
102370x2A, 0x44, 0x4C, 0xB2, 10237 0x2A, 0x44, 0x4C, 0xB2,
102380x1A, 0x44, 0x54, 0xB2, 10238 0x1A, 0x44, 0x54, 0xB2,
10239 10239
102400x29, 0x80, 0x3A, 0xEA, 10240 0x29, 0x80, 0x3A, 0xEA,
102410x0A, 0x20, 10241 0x0A, 0x20,
102420x02, 0x20, 10242 0x02, 0x20,
10243 10243
102440x27, 0xCF, 0x75, 0xC0, 10244 0x27, 0xCF, 0x75, 0xC0,
102450x2A, 0x20, 10245 0x2A, 0x20,
102460x1A, 0x20, 10246 0x1A, 0x20,
10247 10247
102480x30, 0x50, 0x2E, 0x9F, 10248 0x30, 0x50, 0x2E, 0x9F,
102490x32, 0x31, 0x5F, 0xE9, 10249 0x32, 0x31, 0x5F, 0xE9,
10250 10250
102510x38, 0x21, 0x2C, 0x9F, 10251 0x38, 0x21, 0x2C, 0x9F,
102520x33, 0x39, 0x5F, 0xE9, 10252 0x33, 0x39, 0x5F, 0xE9,
10253 10253
102540x3D, 0xCF, 0x75, 0xC2, 10254 0x3D, 0xCF, 0x75, 0xC2,
102550x37, 0xCF, 0x75, 0xC4, 10255 0x37, 0xCF, 0x75, 0xC4,
10256 10256
102570x31, 0x53, 0x2F, 0x9F, 10257 0x31, 0x53, 0x2F, 0x9F,
102580xA6, 0x27, 0x20, 0xE9, 10258 0xA6, 0x27, 0x20, 0xE9,
10259 10259
102600x39, 0xE5, 0x2C, 0x9F, 10260 0x39, 0xE5, 0x2C, 0x9F,
102610xA3, 0x3D, 0x20, 0xE9, 10261 0xA3, 0x3D, 0x20, 0xE9,
10262 10262
102630x2A, 0x44, 0x4C, 0xB4, 10263 0x2A, 0x44, 0x4C, 0xB4,
102640x1A, 0x44, 0x54, 0xB4, 10264 0x1A, 0x44, 0x54, 0xB4,
10265 10265
102660x0A, 0x45, 0x4D, 0xB0, 10266 0x0A, 0x45, 0x4D, 0xB0,
102670x02, 0x45, 0x55, 0xB0, 10267 0x02, 0x45, 0x55, 0xB0,
10268 10268
102690x88, 0x73, 0x5E, 0xE9, 10269 0x88, 0x73, 0x5E, 0xE9,
102700x2A, 0x20, 10270 0x2A, 0x20,
102710x1A, 0x20, 10271 0x1A, 0x20,
10272 10272
102730xA0, 0x37, 0x20, 0xE9, 10273 0xA0, 0x37, 0x20, 0xE9,
102740x0A, 0x20, 10274 0x0A, 0x20,
102750x02, 0x20, 10275 0x02, 0x20,
10276 10276
102770x31, 0x53, 0x2F, 0x9F, 10277 0x31, 0x53, 0x2F, 0x9F,
102780x3E, 0x30, 0x4F, 0xE9, 10278 0x3E, 0x30, 0x4F, 0xE9,
10279 10279
102800x39, 0xE5, 0x2C, 0x9F, 10280 0x39, 0xE5, 0x2C, 0x9F,
102810x3F, 0x38, 0x4F, 0xE9, 10281 0x3F, 0x38, 0x4F, 0xE9,
10282 10282
102830x30, 0x50, 0x2E, 0x9F, 10283 0x30, 0x50, 0x2E, 0x9F,
102840x3A, 0x31, 0x4F, 0xE9, 10284 0x3A, 0x31, 0x4F, 0xE9,
10285 10285
102860x2A, 0x45, 0x4D, 0xB2, 10286 0x2A, 0x45, 0x4D, 0xB2,
102870x1A, 0x45, 0x55, 0xB2, 10287 0x1A, 0x45, 0x55, 0xB2,
10288 10288
102890x0A, 0x45, 0x4D, 0xB4, 10289 0x0A, 0x45, 0x4D, 0xB4,
102900x02, 0x45, 0x55, 0xB4, 10290 0x02, 0x45, 0x55, 0xB4,
10291 10291
102920x38, 0x21, 0x2C, 0x9F, 10292 0x38, 0x21, 0x2C, 0x9F,
102930x3B, 0x39, 0x4F, 0xE9, 10293 0x3B, 0x39, 0x4F, 0xE9,
10294 10294
102950x0A, 0x20, 10295 0x0A, 0x20,
102960x02, 0x20, 10296 0x02, 0x20,
102970x2A, 0x20, 10297 0x2A, 0x20,
102980x1A, 0x20, 10298 0x1A, 0x20,
10299 10299
103000x2A, 0x46, 0x4E, 0xBF, 10300 0x2A, 0x46, 0x4E, 0xBF,
103010x1A, 0x46, 0x56, 0xBF, 10301 0x1A, 0x46, 0x56, 0xBF,
10302 10302
103030x31, 0x53, 0x2F, 0x9F, 10303 0x31, 0x53, 0x2F, 0x9F,
103040x36, 0x31, 0x4F, 0xE9, 10304 0x36, 0x31, 0x4F, 0xE9,
10305 10305
103060x39, 0xE5, 0x2C, 0x9F, 10306 0x39, 0xE5, 0x2C, 0x9F,
103070x37, 0x39, 0x4F, 0xE9, 10307 0x37, 0x39, 0x4F, 0xE9,
10308 10308
103090x30, 0x50, 0x2E, 0x9F, 10309 0x30, 0x50, 0x2E, 0x9F,
103100xA7, 0x30, 0x4F, 0xE9, 10310 0xA7, 0x30, 0x4F, 0xE9,
10311 10311
103120x38, 0x21, 0x2C, 0x9F, 10312 0x38, 0x21, 0x2C, 0x9F,
103130xA8, 0x38, 0x4F, 0xE9, 10313 0xA8, 0x38, 0x4F, 0xE9,
10314 10314
103150x0A, 0x47, 0x4F, 0xBF, 10315 0x0A, 0x47, 0x4F, 0xBF,
103160x02, 0x47, 0x57, 0xBF, 10316 0x02, 0x47, 0x57, 0xBF,
10317 10317
103180x31, 0x53, 0x2F, 0x9F, 10318 0x31, 0x53, 0x2F, 0x9F,
103190xA4, 0x31, 0x4F, 0xE9, 10319 0xA4, 0x31, 0x4F, 0xE9,
10320 10320
103210x39, 0xE5, 0x2C, 0x9F, 10321 0x39, 0xE5, 0x2C, 0x9F,
103220xA5, 0x39, 0x4F, 0xE9, 10322 0xA5, 0x39, 0x4F, 0xE9,
10323 10323
103240x2A, 0x43, 0x4B, 0xBF, 10324 0x2A, 0x43, 0x4B, 0xBF,
103250x1A, 0x43, 0x53, 0xBF, 10325 0x1A, 0x43, 0x53, 0xBF,
10326 10326
103270x30, 0x50, 0x2E, 0x9F, 10327 0x30, 0x50, 0x2E, 0x9F,
103280xA1, 0x30, 0x4F, 0xE9, 10328 0xA1, 0x30, 0x4F, 0xE9,
10329 10329
103300x38, 0x21, 0x2C, 0x9F, 10330 0x38, 0x21, 0x2C, 0x9F,
103310xA2, 0x38, 0x4F, 0xE9, 10331 0xA2, 0x38, 0x4F, 0xE9,
10332 10332
103330x31, 0x53, 0x2F, 0x9F, 10333 0x31, 0x53, 0x2F, 0x9F,
103340x80, 0x31, 0x57, 0xE9, 10334 0x80, 0x31, 0x57, 0xE9,
10335 10335
103360x39, 0xE5, 0x2C, 0x9F, 10336 0x39, 0xE5, 0x2C, 0x9F,
103370x81, 0x39, 0x57, 0xE9, 10337 0x81, 0x39, 0x57, 0xE9,
10338 10338
103390x37, 0x48, 0x50, 0xBD, 10339 0x37, 0x48, 0x50, 0xBD,
103400x8A, 0x36, 0x20, 0xE9, 10340 0x8A, 0x36, 0x20, 0xE9,
10341 10341
103420x86, 0x76, 0x57, 0xE9, 10342 0x86, 0x76, 0x57, 0xE9,
103430x8B, 0x3E, 0x20, 0xE9, 10343 0x8B, 0x3E, 0x20, 0xE9,
10344 10344
103450x82, 0x30, 0x57, 0xE9, 10345 0x82, 0x30, 0x57, 0xE9,
103460x87, 0x77, 0x57, 0xE9, 10346 0x87, 0x77, 0x57, 0xE9,
10347 10347
103480x83, 0x38, 0x57, 0xE9, 10348 0x83, 0x38, 0x57, 0xE9,
103490x35, 0x49, 0x51, 0xBD, 10349 0x35, 0x49, 0x51, 0xBD,
10350 10350
103510x84, 0x31, 0x5E, 0xE9, 10351 0x84, 0x31, 0x5E, 0xE9,
103520x30, 0x1F, 0x5F, 0xE9, 10352 0x30, 0x1F, 0x5F, 0xE9,
10353 10353
103540x85, 0x39, 0x5E, 0xE9, 10354 0x85, 0x39, 0x5E, 0xE9,
103550x57, 0x25, 0x20, 0xE9, 10355 0x57, 0x25, 0x20, 0xE9,
10356 10356
103570x2B, 0x48, 0x20, 0xE9, 10357 0x2B, 0x48, 0x20, 0xE9,
103580x1D, 0x37, 0xE1, 0xEA, 10358 0x1D, 0x37, 0xE1, 0xEA,
10359 10359
103600x1E, 0x35, 0xE1, 0xEA, 10360 0x1E, 0x35, 0xE1, 0xEA,
103610x00, 0xE0, 10361 0x00, 0xE0,
103620x26, 0x77, 10362 0x26, 0x77,
10363 10363
103640x24, 0x49, 0x20, 0xE9, 10364 0x24, 0x49, 0x20, 0xE9,
103650xA2, 0xFF, 0x20, 0xEA, 10365 0xA2, 0xFF, 0x20, 0xEA,
10366 10366
103670x16, 0x26, 0x20, 0xE9, 10367 0x16, 0x26, 0x20, 0xE9,
103680x57, 0x2E, 0xBF, 0xEA, 10368 0x57, 0x2E, 0xBF, 0xEA,
10369 10369
103700x1C, 0x46, 0xA0, 0xE8, 10370 0x1C, 0x46, 0xA0, 0xE8,
103710x23, 0x4E, 0xA0, 0xE8, 10371 0x23, 0x4E, 0xA0, 0xE8,
10372 10372
103730x2B, 0x56, 0xA0, 0xE8, 10373 0x2B, 0x56, 0xA0, 0xE8,
103740x1D, 0x47, 0xA0, 0xE8, 10374 0x1D, 0x47, 0xA0, 0xE8,
10375 10375
103760x24, 0x4F, 0xA0, 0xE8, 10376 0x24, 0x4F, 0xA0, 0xE8,
103770x2C, 0x57, 0xA0, 0xE8, 10377 0x2C, 0x57, 0xA0, 0xE8,
10378 10378
103790x1C, 0x00, 10379 0x1C, 0x00,
103800x23, 0x00, 10380 0x23, 0x00,
103810x2B, 0x00, 10381 0x2B, 0x00,
103820x00, 0xE0, 10382 0x00, 0xE0,
10383 10383
103840x1D, 0x00, 10384 0x1D, 0x00,
103850x24, 0x00, 10385 0x24, 0x00,
103860x2C, 0x00, 10386 0x2C, 0x00,
103870x00, 0xE0, 10387 0x00, 0xE0,
10388 10388
103890x1C, 0x65, 10389 0x1C, 0x65,
103900x23, 0x65, 10390 0x23, 0x65,
103910x2B, 0x65, 10391 0x2B, 0x65,
103920x00, 0xE0, 10392 0x00, 0xE0,
10393 10393
103940x1D, 0x65, 10394 0x1D, 0x65,
103950x24, 0x65, 10395 0x24, 0x65,
103960x2C, 0x65, 10396 0x2C, 0x65,
103970x00, 0xE0, 10397 0x00, 0xE0,
10398 10398
103990x1C, 0x23, 0x60, 0xEC, 10399 0x1C, 0x23, 0x60, 0xEC,
104000x36, 0xD7, 0x36, 0xAD, 10400 0x36, 0xD7, 0x36, 0xAD,
10401 10401
104020x2B, 0x80, 0x60, 0xEC, 10402 0x2B, 0x80, 0x60, 0xEC,
104030x1D, 0x24, 0x60, 0xEC, 10403 0x1D, 0x24, 0x60, 0xEC,
10404 10404
104050x3E, 0xD7, 0x3E, 0xAD, 10405 0x3E, 0xD7, 0x3E, 0xAD,
104060x2C, 0x80, 0x60, 0xEC, 10406 0x2C, 0x80, 0x60, 0xEC,
10407 10407
104080x1C, 0x2B, 0xDE, 0xE8, 10408 0x1C, 0x2B, 0xDE, 0xE8,
104090x23, 0x80, 0xDE, 0xE8, 10409 0x23, 0x80, 0xDE, 0xE8,
10410 10410
104110x36, 0x80, 0x36, 0xBD, 10411 0x36, 0x80, 0x36, 0xBD,
104120x3E, 0x80, 0x3E, 0xBD, 10412 0x3E, 0x80, 0x3E, 0xBD,
10413 10413
104140x33, 0xD7, 0x1C, 0xBD, 10414 0x33, 0xD7, 0x1C, 0xBD,
104150x3B, 0xD7, 0x23, 0xBD, 10415 0x3B, 0xD7, 0x23, 0xBD,
10416 10416
104170x46, 0x80, 0x46, 0xCF, 10417 0x46, 0x80, 0x46, 0xCF,
104180x4F, 0x80, 0x4F, 0xCF, 10418 0x4F, 0x80, 0x4F, 0xCF,
10419 10419
104200x56, 0x33, 0x56, 0xCF, 10420 0x56, 0x33, 0x56, 0xCF,
104210x47, 0x3B, 0x47, 0xCF, 10421 0x47, 0x3B, 0x47, 0xCF,
10422 10422
104230xCA, 0xFF, 0x20, 0xEA, 10423 0xCA, 0xFF, 0x20, 0xEA,
104240x00, 0x80, 0x00, 0xE8, 10424 0x00, 0x80, 0x00, 0xE8,
10425 10425
104260x4E, 0x33, 0x4E, 0xCF, 10426 0x4E, 0x33, 0x4E, 0xCF,
104270x57, 0x3B, 0x57, 0xCF, 10427 0x57, 0x3B, 0x57, 0xCF,
10428 10428
104290x90, 0xFF, 0x20, 0xEA, 10429 0x90, 0xFF, 0x20, 0xEA,
104300x57, 0xC0, 0xBF, 0xEA, 10430 0x57, 0xC0, 0xBF, 0xEA,
10431 10431
104320x00, 0x80, 0xA0, 0xE9, 10432 0x00, 0x80, 0xA0, 0xE9,
104330x00, 0x00, 0xD8, 0xEC, 10433 0x00, 0x00, 0xD8, 0xEC,
10434 10434
10435}; 10435};
10436 10436
10437static unsigned char warp_g400_tgzsa[] = { 10437static unsigned char warp_g400_tgzsa[] = {
10438 10438
104390x00, 0x88, 0x98, 0xE9, 10439 0x00, 0x88, 0x98, 0xE9,
104400x00, 0x80, 0x00, 0xE8, 10440 0x00, 0x80, 0x00, 0xE8,
10441 10441
104420x00, 0x80, 0xA0, 0xE9, 10442 0x00, 0x80, 0xA0, 0xE9,
104430x00, 0x00, 0xD8, 0xEC, 10443 0x00, 0x00, 0xD8, 0xEC,
10444 10444
104450xFF, 0x80, 0xC0, 0xE9, 10445 0xFF, 0x80, 0xC0, 0xE9,
104460x00, 0x80, 0x00, 0xE8, 10446 0x00, 0x80, 0x00, 0xE8,
10447 10447
104480x22, 0x40, 0x48, 0xBF, 10448 0x22, 0x40, 0x48, 0xBF,
104490x2A, 0x40, 0x50, 0xBF, 10449 0x2A, 0x40, 0x50, 0xBF,
10450 10450
104510x32, 0x41, 0x49, 0xBF, 10451 0x32, 0x41, 0x49, 0xBF,
104520x3A, 0x41, 0x51, 0xBF, 10452 0x3A, 0x41, 0x51, 0xBF,
10453 10453
104540xC3, 0x6B, 10454 0xC3, 0x6B,
104550xCB, 0x6B, 10455 0xCB, 0x6B,
104560x00, 0x88, 0x98, 0xE9, 10456 0x00, 0x88, 0x98, 0xE9,
10457 10457
104580x73, 0x7B, 0xC8, 0xEC, 10458 0x73, 0x7B, 0xC8, 0xEC,
104590x96, 0xE2, 10459 0x96, 0xE2,
104600x41, 0x04, 10460 0x41, 0x04,
10461 10461
104620x7B, 0x43, 0xA0, 0xE8, 10462 0x7B, 0x43, 0xA0, 0xE8,
104630x73, 0x4B, 0xA0, 0xE8, 10463 0x73, 0x4B, 0xA0, 0xE8,
10464 10464
104650xAD, 0xEE, 0x29, 0x9F, 10465 0xAD, 0xEE, 0x29, 0x9F,
104660x00, 0xE0, 10466 0x00, 0xE0,
104670x49, 0x04, 10467 0x49, 0x04,
10468 10468
104690x90, 0xE2, 10469 0x90, 0xE2,
104700x51, 0x04, 10470 0x51, 0x04,
104710x31, 0x46, 0xB1, 0xE8, 10471 0x31, 0x46, 0xB1, 0xE8,
10472 10472
104730x49, 0x41, 0xC0, 0xEC, 10473 0x49, 0x41, 0xC0, 0xEC,
104740x39, 0x57, 0xB1, 0xE8, 10474 0x39, 0x57, 0xB1, 0xE8,
10475 10475
104760x00, 0x04, 10476 0x00, 0x04,
104770x46, 0xE2, 10477 0x46, 0xE2,
104780x73, 0x53, 0xA0, 0xE8, 10478 0x73, 0x53, 0xA0, 0xE8,
10479 10479
104800x51, 0x41, 0xC0, 0xEC, 10480 0x51, 0x41, 0xC0, 0xEC,
104810x31, 0x00, 10481 0x31, 0x00,
104820x39, 0x00, 10482 0x39, 0x00,
10483 10483
104840x6A, 0x80, 0x15, 0xEA, 10484 0x6A, 0x80, 0x15, 0xEA,
104850x08, 0x04, 10485 0x08, 0x04,
104860x10, 0x04, 10486 0x10, 0x04,
10487 10487
104880x51, 0x49, 0xC0, 0xEC, 10488 0x51, 0x49, 0xC0, 0xEC,
104890x2F, 0x41, 0x60, 0xEA, 10489 0x2F, 0x41, 0x60, 0xEA,
10490 10490
104910x31, 0x20, 10491 0x31, 0x20,
104920x39, 0x20, 10492 0x39, 0x20,
104930x1F, 0x42, 0xA0, 0xE8, 10493 0x1F, 0x42, 0xA0, 0xE8,
10494 10494
104950x2A, 0x42, 0x4A, 0xBF, 10495 0x2A, 0x42, 0x4A, 0xBF,
104960x27, 0x4A, 0xA0, 0xE8, 10496 0x27, 0x4A, 0xA0, 0xE8,
10497 10497
104980x1A, 0x42, 0x52, 0xBF, 10498 0x1A, 0x42, 0x52, 0xBF,
104990x1E, 0x49, 0x60, 0xEA, 10499 0x1E, 0x49, 0x60, 0xEA,
10500 10500
105010x73, 0x7B, 0xC8, 0xEC, 10501 0x73, 0x7B, 0xC8, 0xEC,
105020x26, 0x51, 0x60, 0xEA, 10502 0x26, 0x51, 0x60, 0xEA,
10503 10503
105040x32, 0x40, 0x48, 0xBD, 10504 0x32, 0x40, 0x48, 0xBD,
105050x22, 0x40, 0x50, 0xBD, 10505 0x22, 0x40, 0x50, 0xBD,
10506 10506
105070x12, 0x41, 0x49, 0xBD, 10507 0x12, 0x41, 0x49, 0xBD,
105080x3A, 0x41, 0x51, 0xBD, 10508 0x3A, 0x41, 0x51, 0xBD,
10509 10509
105100xBF, 0x2F, 0x26, 0xBD, 10510 0xBF, 0x2F, 0x26, 0xBD,
105110x00, 0xE0, 10511 0x00, 0xE0,
105120x7B, 0x72, 10512 0x7B, 0x72,
10513 10513
105140x32, 0x20, 10514 0x32, 0x20,
105150x22, 0x20, 10515 0x22, 0x20,
105160x12, 0x20, 10516 0x12, 0x20,
105170x3A, 0x20, 10517 0x3A, 0x20,
10518 10518
105190x46, 0x31, 0x46, 0xBF, 10519 0x46, 0x31, 0x46, 0xBF,
105200x4E, 0x31, 0x4E, 0xBF, 10520 0x4E, 0x31, 0x4E, 0xBF,
10521 10521
105220xB3, 0xE2, 0x2D, 0x9F, 10522 0xB3, 0xE2, 0x2D, 0x9F,
105230x00, 0x80, 0x00, 0xE8, 10523 0x00, 0x80, 0x00, 0xE8,
10524 10524
105250x56, 0x31, 0x56, 0xBF, 10525 0x56, 0x31, 0x56, 0xBF,
105260x47, 0x39, 0x47, 0xBF, 10526 0x47, 0x39, 0x47, 0xBF,
10527 10527
105280x4F, 0x39, 0x4F, 0xBF, 10528 0x4F, 0x39, 0x4F, 0xBF,
105290x57, 0x39, 0x57, 0xBF, 10529 0x57, 0x39, 0x57, 0xBF,
10530 10530
105310x5C, 0x80, 0x07, 0xEA, 10531 0x5C, 0x80, 0x07, 0xEA,
105320x24, 0x41, 0x20, 0xE9, 10532 0x24, 0x41, 0x20, 0xE9,
10533 10533
105340x42, 0x73, 0xF8, 0xEC, 10534 0x42, 0x73, 0xF8, 0xEC,
105350x00, 0xE0, 10535 0x00, 0xE0,
105360x2D, 0x73, 10536 0x2D, 0x73,
10537 10537
105380x33, 0x72, 10538 0x33, 0x72,
105390x0C, 0xE3, 10539 0x0C, 0xE3,
105400xA5, 0x2F, 0x1E, 0xBD, 10540 0xA5, 0x2F, 0x1E, 0xBD,
10541 10541
105420x43, 0x43, 0x2D, 0xDF, 10542 0x43, 0x43, 0x2D, 0xDF,
105430x4B, 0x4B, 0x2D, 0xDF, 10543 0x4B, 0x4B, 0x2D, 0xDF,
10544 10544
105450xAE, 0x1E, 0x26, 0xBD, 10545 0xAE, 0x1E, 0x26, 0xBD,
105460x58, 0xE3, 10546 0x58, 0xE3,
105470x33, 0x66, 10547 0x33, 0x66,
10548 10548
105490x53, 0x53, 0x2D, 0xDF, 10549 0x53, 0x53, 0x2D, 0xDF,
105500x00, 0x80, 0x00, 0xE8, 10550 0x00, 0x80, 0x00, 0xE8,
10551 10551
105520xB8, 0x38, 0x33, 0xBF, 10552 0xB8, 0x38, 0x33, 0xBF,
105530x00, 0xE0, 10553 0x00, 0xE0,
105540x59, 0xE3, 10554 0x59, 0xE3,
10555 10555
105560x1E, 0x12, 0x41, 0xE9, 10556 0x1E, 0x12, 0x41, 0xE9,
105570x1A, 0x22, 0x41, 0xE9, 10557 0x1A, 0x22, 0x41, 0xE9,
10558 10558
105590x2B, 0x40, 0x3D, 0xE9, 10559 0x2B, 0x40, 0x3D, 0xE9,
105600x3F, 0x4B, 0xA0, 0xE8, 10560 0x3F, 0x4B, 0xA0, 0xE8,
10561 10561
105620x2D, 0x73, 10562 0x2D, 0x73,
105630x30, 0x76, 10563 0x30, 0x76,
105640x05, 0x80, 0x3D, 0xEA, 10564 0x05, 0x80, 0x3D, 0xEA,
10565 10565
105660x37, 0x43, 0xA0, 0xE8, 10566 0x37, 0x43, 0xA0, 0xE8,
105670x3D, 0x53, 0xA0, 0xE8, 10567 0x3D, 0x53, 0xA0, 0xE8,
10568 10568
105690x48, 0x70, 0xF8, 0xEC, 10569 0x48, 0x70, 0xF8, 0xEC,
105700x2B, 0x48, 0x3C, 0xE9, 10570 0x2B, 0x48, 0x3C, 0xE9,
10571 10571
105720x1F, 0x27, 0xBC, 0xE8, 10572 0x1F, 0x27, 0xBC, 0xE8,
105730x00, 0x80, 0x00, 0xE8, 10573 0x00, 0x80, 0x00, 0xE8,
10574 10574
105750x00, 0x80, 0x00, 0xE8, 10575 0x00, 0x80, 0x00, 0xE8,
105760x00, 0x80, 0x00, 0xE8, 10576 0x00, 0x80, 0x00, 0xE8,
10577 10577
105780x15, 0xC0, 0x20, 0xE9, 10578 0x15, 0xC0, 0x20, 0xE9,
105790x15, 0xC0, 0x20, 0xE9, 10579 0x15, 0xC0, 0x20, 0xE9,
10580 10580
105810x15, 0xC0, 0x20, 0xE9, 10581 0x15, 0xC0, 0x20, 0xE9,
105820x15, 0xC0, 0x20, 0xE9, 10582 0x15, 0xC0, 0x20, 0xE9,
10583 10583
105840x18, 0x3A, 0x41, 0xE9, 10584 0x18, 0x3A, 0x41, 0xE9,
105850x1D, 0x32, 0x41, 0xE9, 10585 0x1D, 0x32, 0x41, 0xE9,
10586 10586
105870x2A, 0x40, 0x20, 0xE9, 10587 0x2A, 0x40, 0x20, 0xE9,
105880x56, 0x3D, 0x56, 0xDF, 10588 0x56, 0x3D, 0x56, 0xDF,
10589 10589
105900x46, 0x37, 0x46, 0xDF, 10590 0x46, 0x37, 0x46, 0xDF,
105910x4E, 0x3F, 0x4E, 0xDF, 10591 0x4E, 0x3F, 0x4E, 0xDF,
10592 10592
105930x16, 0x30, 0x20, 0xE9, 10593 0x16, 0x30, 0x20, 0xE9,
105940x4F, 0x3F, 0x4F, 0xDF, 10594 0x4F, 0x3F, 0x4F, 0xDF,
10595 10595
105960x47, 0x37, 0x47, 0xDF, 10596 0x47, 0x37, 0x47, 0xDF,
105970x57, 0x3D, 0x57, 0xDF, 10597 0x57, 0x3D, 0x57, 0xDF,
10598 10598
105990x32, 0x32, 0x2D, 0xDF, 10599 0x32, 0x32, 0x2D, 0xDF,
106000x22, 0x22, 0x2D, 0xDF, 10600 0x22, 0x22, 0x2D, 0xDF,
10601 10601
106020x12, 0x12, 0x2D, 0xDF, 10602 0x12, 0x12, 0x2D, 0xDF,
106030x3A, 0x3A, 0x2D, 0xDF, 10603 0x3A, 0x3A, 0x2D, 0xDF,
10604 10604
106050x27, 0xCF, 0x74, 0xC2, 10605 0x27, 0xCF, 0x74, 0xC2,
106060x37, 0xCF, 0x74, 0xC4, 10606 0x37, 0xCF, 0x74, 0xC4,
10607 10607
106080x0A, 0x44, 0x4C, 0xB0, 10608 0x0A, 0x44, 0x4C, 0xB0,
106090x02, 0x44, 0x54, 0xB0, 10609 0x02, 0x44, 0x54, 0xB0,
10610 10610
106110x3D, 0xCF, 0x74, 0xC0, 10611 0x3D, 0xCF, 0x74, 0xC0,
106120x34, 0x37, 0x20, 0xE9, 10612 0x34, 0x37, 0x20, 0xE9,
10613 10613
106140x31, 0x53, 0x2F, 0x9F, 10614 0x31, 0x53, 0x2F, 0x9F,
106150x38, 0x27, 0x20, 0xE9, 10615 0x38, 0x27, 0x20, 0xE9,
10616 10616
106170x39, 0xE5, 0x2C, 0x9F, 10617 0x39, 0xE5, 0x2C, 0x9F,
106180x3C, 0x3D, 0x20, 0xE9, 10618 0x3C, 0x3D, 0x20, 0xE9,
10619 10619
106200x2A, 0x44, 0x4C, 0xB2, 10620 0x2A, 0x44, 0x4C, 0xB2,
106210x1A, 0x44, 0x54, 0xB2, 10621 0x1A, 0x44, 0x54, 0xB2,
10622 10622
106230x2E, 0x80, 0x3A, 0xEA, 10623 0x2E, 0x80, 0x3A, 0xEA,
106240x0A, 0x20, 10624 0x0A, 0x20,
106250x02, 0x20, 10625 0x02, 0x20,
10626 10626
106270x27, 0xCF, 0x75, 0xC0, 10627 0x27, 0xCF, 0x75, 0xC0,
106280x2A, 0x20, 10628 0x2A, 0x20,
106290x1A, 0x20, 10629 0x1A, 0x20,
10630 10630
106310x30, 0x50, 0x2E, 0x9F, 10631 0x30, 0x50, 0x2E, 0x9F,
106320x32, 0x31, 0x5F, 0xE9, 10632 0x32, 0x31, 0x5F, 0xE9,
10633 10633
106340x38, 0x21, 0x2C, 0x9F, 10634 0x38, 0x21, 0x2C, 0x9F,
106350x33, 0x39, 0x5F, 0xE9, 10635 0x33, 0x39, 0x5F, 0xE9,
10636 10636
106370x3D, 0xCF, 0x75, 0xC2, 10637 0x3D, 0xCF, 0x75, 0xC2,
106380x37, 0xCF, 0x75, 0xC4, 10638 0x37, 0xCF, 0x75, 0xC4,
10639 10639
106400x31, 0x53, 0x2F, 0x9F, 10640 0x31, 0x53, 0x2F, 0x9F,
106410xA6, 0x27, 0x20, 0xE9, 10641 0xA6, 0x27, 0x20, 0xE9,
10642 10642
106430x39, 0xE5, 0x2C, 0x9F, 10643 0x39, 0xE5, 0x2C, 0x9F,
106440xA3, 0x3D, 0x20, 0xE9, 10644 0xA3, 0x3D, 0x20, 0xE9,
10645 10645
106460x2A, 0x44, 0x4C, 0xB4, 10646 0x2A, 0x44, 0x4C, 0xB4,
106470x1A, 0x44, 0x54, 0xB4, 10647 0x1A, 0x44, 0x54, 0xB4,
10648 10648
106490x0A, 0x45, 0x4D, 0xB0, 10649 0x0A, 0x45, 0x4D, 0xB0,
106500x02, 0x45, 0x55, 0xB0, 10650 0x02, 0x45, 0x55, 0xB0,
10651 10651
106520x88, 0x73, 0x5E, 0xE9, 10652 0x88, 0x73, 0x5E, 0xE9,
106530x2A, 0x20, 10653 0x2A, 0x20,
106540x1A, 0x20, 10654 0x1A, 0x20,
10655 10655
106560xA0, 0x37, 0x20, 0xE9, 10656 0xA0, 0x37, 0x20, 0xE9,
106570x0A, 0x20, 10657 0x0A, 0x20,
106580x02, 0x20, 10658 0x02, 0x20,
10659 10659
106600x31, 0x53, 0x2F, 0x9F, 10660 0x31, 0x53, 0x2F, 0x9F,
106610x3E, 0x30, 0x4F, 0xE9, 10661 0x3E, 0x30, 0x4F, 0xE9,
10662 10662
106630x39, 0xE5, 0x2C, 0x9F, 10663 0x39, 0xE5, 0x2C, 0x9F,
106640x3F, 0x38, 0x4F, 0xE9, 10664 0x3F, 0x38, 0x4F, 0xE9,
10665 10665
106660x30, 0x50, 0x2E, 0x9F, 10666 0x30, 0x50, 0x2E, 0x9F,
106670x3A, 0x31, 0x4F, 0xE9, 10667 0x3A, 0x31, 0x4F, 0xE9,
10668 10668
106690x38, 0x21, 0x2C, 0x9F, 10669 0x38, 0x21, 0x2C, 0x9F,
106700x3B, 0x39, 0x4F, 0xE9, 10670 0x3B, 0x39, 0x4F, 0xE9,
10671 10671
106720x2A, 0x45, 0x4D, 0xB2, 10672 0x2A, 0x45, 0x4D, 0xB2,
106730x1A, 0x45, 0x55, 0xB2, 10673 0x1A, 0x45, 0x55, 0xB2,
10674 10674
106750x0A, 0x45, 0x4D, 0xB4, 10675 0x0A, 0x45, 0x4D, 0xB4,
106760x02, 0x45, 0x55, 0xB4, 10676 0x02, 0x45, 0x55, 0xB4,
10677 10677
106780x27, 0xCF, 0x74, 0xC6, 10678 0x27, 0xCF, 0x74, 0xC6,
106790x2A, 0x20, 10679 0x2A, 0x20,
106800x1A, 0x20, 10680 0x1A, 0x20,
10681 10681
106820xA7, 0x30, 0x4F, 0xE9, 10682 0xA7, 0x30, 0x4F, 0xE9,
106830x0A, 0x20, 10683 0x0A, 0x20,
106840x02, 0x20, 10684 0x02, 0x20,
10685 10685
106860x31, 0x53, 0x2F, 0x9F, 10686 0x31, 0x53, 0x2F, 0x9F,
106870x9C, 0x27, 0x20, 0xE9, 10687 0x9C, 0x27, 0x20, 0xE9,
10688 10688
106890x39, 0xE5, 0x2C, 0x9F, 10689 0x39, 0xE5, 0x2C, 0x9F,
106900xA8, 0x38, 0x4F, 0xE9, 10690 0xA8, 0x38, 0x4F, 0xE9,
10691 10691
106920x2A, 0x44, 0x4C, 0xB6, 10692 0x2A, 0x44, 0x4C, 0xB6,
106930x1A, 0x44, 0x54, 0xB6, 10693 0x1A, 0x44, 0x54, 0xB6,
10694 10694
106950x30, 0x50, 0x2E, 0x9F, 10695 0x30, 0x50, 0x2E, 0x9F,
106960x36, 0x31, 0x4F, 0xE9, 10696 0x36, 0x31, 0x4F, 0xE9,
10697 10697
106980x38, 0x21, 0x2C, 0x9F, 10698 0x38, 0x21, 0x2C, 0x9F,
106990x37, 0x39, 0x4F, 0xE9, 10699 0x37, 0x39, 0x4F, 0xE9,
10700 10700
107010x00, 0x80, 0x00, 0xE8, 10701 0x00, 0x80, 0x00, 0xE8,
107020x2A, 0x20, 10702 0x2A, 0x20,
107030x1A, 0x20, 10703 0x1A, 0x20,
10704 10704
107050x2A, 0x46, 0x4E, 0xBF, 10705 0x2A, 0x46, 0x4E, 0xBF,
107060x1A, 0x46, 0x56, 0xBF, 10706 0x1A, 0x46, 0x56, 0xBF,
10707 10707
107080x31, 0x53, 0x2F, 0x9F, 10708 0x31, 0x53, 0x2F, 0x9F,
107090xA4, 0x31, 0x4F, 0xE9, 10709 0xA4, 0x31, 0x4F, 0xE9,
10710 10710
107110x39, 0xE5, 0x2C, 0x9F, 10711 0x39, 0xE5, 0x2C, 0x9F,
107120xA5, 0x39, 0x4F, 0xE9, 10712 0xA5, 0x39, 0x4F, 0xE9,
10713 10713
107140x0A, 0x47, 0x4F, 0xBF, 10714 0x0A, 0x47, 0x4F, 0xBF,
107150x02, 0x47, 0x57, 0xBF, 10715 0x02, 0x47, 0x57, 0xBF,
10716 10716
107170x31, 0x53, 0x2F, 0x9F, 10717 0x31, 0x53, 0x2F, 0x9F,
107180xA1, 0x30, 0x4F, 0xE9, 10718 0xA1, 0x30, 0x4F, 0xE9,
10719 10719
107200x39, 0xE5, 0x2C, 0x9F, 10720 0x39, 0xE5, 0x2C, 0x9F,
107210xA2, 0x38, 0x4F, 0xE9, 10721 0xA2, 0x38, 0x4F, 0xE9,
10722 10722
107230x2A, 0x43, 0x4B, 0xBF, 10723 0x2A, 0x43, 0x4B, 0xBF,
107240x1A, 0x43, 0x53, 0xBF, 10724 0x1A, 0x43, 0x53, 0xBF,
10725 10725
107260x30, 0x50, 0x2E, 0x9F, 10726 0x30, 0x50, 0x2E, 0x9F,
107270x9D, 0x31, 0x4F, 0xE9, 10727 0x9D, 0x31, 0x4F, 0xE9,
10728 10728
107290x38, 0x21, 0x2C, 0x9F, 10729 0x38, 0x21, 0x2C, 0x9F,
107300x9E, 0x39, 0x4F, 0xE9, 10730 0x9E, 0x39, 0x4F, 0xE9,
10731 10731
107320x31, 0x53, 0x2F, 0x9F, 10732 0x31, 0x53, 0x2F, 0x9F,
107330x80, 0x31, 0x57, 0xE9, 10733 0x80, 0x31, 0x57, 0xE9,
10734 10734
107350x39, 0xE5, 0x2C, 0x9F, 10735 0x39, 0xE5, 0x2C, 0x9F,
107360x81, 0x39, 0x57, 0xE9, 10736 0x81, 0x39, 0x57, 0xE9,
10737 10737
107380x37, 0x48, 0x50, 0xBD, 10738 0x37, 0x48, 0x50, 0xBD,
107390x8A, 0x36, 0x20, 0xE9, 10739 0x8A, 0x36, 0x20, 0xE9,
10740 10740
107410x86, 0x76, 0x57, 0xE9, 10741 0x86, 0x76, 0x57, 0xE9,
107420x8B, 0x3E, 0x20, 0xE9, 10742 0x8B, 0x3E, 0x20, 0xE9,
10743 10743
107440x82, 0x30, 0x57, 0xE9, 10744 0x82, 0x30, 0x57, 0xE9,
107450x87, 0x77, 0x57, 0xE9, 10745 0x87, 0x77, 0x57, 0xE9,
10746 10746
107470x83, 0x38, 0x57, 0xE9, 10747 0x83, 0x38, 0x57, 0xE9,
107480x35, 0x49, 0x51, 0xBD, 10748 0x35, 0x49, 0x51, 0xBD,
10749 10749
107500x84, 0x31, 0x5E, 0xE9, 10750 0x84, 0x31, 0x5E, 0xE9,
107510x30, 0x1F, 0x5F, 0xE9, 10751 0x30, 0x1F, 0x5F, 0xE9,
10752 10752
107530x85, 0x39, 0x5E, 0xE9, 10753 0x85, 0x39, 0x5E, 0xE9,
107540x57, 0x25, 0x20, 0xE9, 10754 0x57, 0x25, 0x20, 0xE9,
10755 10755
107560x2B, 0x48, 0x20, 0xE9, 10756 0x2B, 0x48, 0x20, 0xE9,
107570x1D, 0x37, 0xE1, 0xEA, 10757 0x1D, 0x37, 0xE1, 0xEA,
10758 10758
107590x1E, 0x35, 0xE1, 0xEA, 10759 0x1E, 0x35, 0xE1, 0xEA,
107600x00, 0xE0, 10760 0x00, 0xE0,
107610x26, 0x77, 10761 0x26, 0x77,
10762 10762
107630x24, 0x49, 0x20, 0xE9, 10763 0x24, 0x49, 0x20, 0xE9,
107640x9D, 0xFF, 0x20, 0xEA, 10764 0x9D, 0xFF, 0x20, 0xEA,
10765 10765
107660x16, 0x26, 0x20, 0xE9, 10766 0x16, 0x26, 0x20, 0xE9,
107670x57, 0x2E, 0xBF, 0xEA, 10767 0x57, 0x2E, 0xBF, 0xEA,
10768 10768
107690x1C, 0x46, 0xA0, 0xE8, 10769 0x1C, 0x46, 0xA0, 0xE8,
107700x23, 0x4E, 0xA0, 0xE8, 10770 0x23, 0x4E, 0xA0, 0xE8,
10771 10771
107720x2B, 0x56, 0xA0, 0xE8, 10772 0x2B, 0x56, 0xA0, 0xE8,
107730x1D, 0x47, 0xA0, 0xE8, 10773 0x1D, 0x47, 0xA0, 0xE8,
10774 10774
107750x24, 0x4F, 0xA0, 0xE8, 10775 0x24, 0x4F, 0xA0, 0xE8,
107760x2C, 0x57, 0xA0, 0xE8, 10776 0x2C, 0x57, 0xA0, 0xE8,
10777 10777
107780x1C, 0x00, 10778 0x1C, 0x00,
107790x23, 0x00, 10779 0x23, 0x00,
107800x2B, 0x00, 10780 0x2B, 0x00,
107810x00, 0xE0, 10781 0x00, 0xE0,
10782 10782
107830x1D, 0x00, 10783 0x1D, 0x00,
107840x24, 0x00, 10784 0x24, 0x00,
107850x2C, 0x00, 10785 0x2C, 0x00,
107860x00, 0xE0, 10786 0x00, 0xE0,
10787 10787
107880x1C, 0x65, 10788 0x1C, 0x65,
107890x23, 0x65, 10789 0x23, 0x65,
107900x2B, 0x65, 10790 0x2B, 0x65,
107910x00, 0xE0, 10791 0x00, 0xE0,
10792 10792
107930x1D, 0x65, 10793 0x1D, 0x65,
107940x24, 0x65, 10794 0x24, 0x65,
107950x2C, 0x65, 10795 0x2C, 0x65,
107960x00, 0xE0, 10796 0x00, 0xE0,
10797 10797
107980x1C, 0x23, 0x60, 0xEC, 10798 0x1C, 0x23, 0x60, 0xEC,
107990x36, 0xD7, 0x36, 0xAD, 10799 0x36, 0xD7, 0x36, 0xAD,
10800 10800
108010x2B, 0x80, 0x60, 0xEC, 10801 0x2B, 0x80, 0x60, 0xEC,
108020x1D, 0x24, 0x60, 0xEC, 10802 0x1D, 0x24, 0x60, 0xEC,
10803 10803
108040x3E, 0xD7, 0x3E, 0xAD, 10804 0x3E, 0xD7, 0x3E, 0xAD,
108050x2C, 0x80, 0x60, 0xEC, 10805 0x2C, 0x80, 0x60, 0xEC,
10806 10806
108070x1C, 0x2B, 0xDE, 0xE8, 10807 0x1C, 0x2B, 0xDE, 0xE8,
108080x23, 0x80, 0xDE, 0xE8, 10808 0x23, 0x80, 0xDE, 0xE8,
10809 10809
108100x36, 0x80, 0x36, 0xBD, 10810 0x36, 0x80, 0x36, 0xBD,
108110x3E, 0x80, 0x3E, 0xBD, 10811 0x3E, 0x80, 0x3E, 0xBD,
10812 10812
108130x33, 0xD7, 0x1C, 0xBD, 10813 0x33, 0xD7, 0x1C, 0xBD,
108140x3B, 0xD7, 0x23, 0xBD, 10814 0x3B, 0xD7, 0x23, 0xBD,
10815 10815
108160x46, 0x80, 0x46, 0xCF, 10816 0x46, 0x80, 0x46, 0xCF,
108170x4F, 0x80, 0x4F, 0xCF, 10817 0x4F, 0x80, 0x4F, 0xCF,
10818 10818
108190x56, 0x33, 0x56, 0xCF, 10819 0x56, 0x33, 0x56, 0xCF,
108200x47, 0x3B, 0x47, 0xCF, 10820 0x47, 0x3B, 0x47, 0xCF,
10821 10821
108220xC5, 0xFF, 0x20, 0xEA, 10822 0xC5, 0xFF, 0x20, 0xEA,
108230x00, 0x80, 0x00, 0xE8, 10823 0x00, 0x80, 0x00, 0xE8,
10824 10824
108250x4E, 0x33, 0x4E, 0xCF, 10825 0x4E, 0x33, 0x4E, 0xCF,
108260x57, 0x3B, 0x57, 0xCF, 10826 0x57, 0x3B, 0x57, 0xCF,
10827 10827
108280x8B, 0xFF, 0x20, 0xEA, 10828 0x8B, 0xFF, 0x20, 0xEA,
108290x57, 0xC0, 0xBF, 0xEA, 10829 0x57, 0xC0, 0xBF, 0xEA,
10830 10830
108310x00, 0x80, 0xA0, 0xE9, 10831 0x00, 0x80, 0xA0, 0xE9,
108320x00, 0x00, 0xD8, 0xEC, 10832 0x00, 0x00, 0xD8, 0xEC,
10833 10833
10834}; 10834};
10835 10835
10836static unsigned char warp_g400_tgzsaf[] = { 10836static unsigned char warp_g400_tgzsaf[] = {
10837 10837
108380x00, 0x88, 0x98, 0xE9, 10838 0x00, 0x88, 0x98, 0xE9,
108390x00, 0x80, 0x00, 0xE8, 10839 0x00, 0x80, 0x00, 0xE8,
10840 10840
108410x00, 0x80, 0xA0, 0xE9, 10841 0x00, 0x80, 0xA0, 0xE9,
108420x00, 0x00, 0xD8, 0xEC, 10842 0x00, 0x00, 0xD8, 0xEC,
10843 10843
108440xFF, 0x80, 0xC0, 0xE9, 10844 0xFF, 0x80, 0xC0, 0xE9,
108450x00, 0x80, 0x00, 0xE8, 10845 0x00, 0x80, 0x00, 0xE8,
10846 10846
108470x22, 0x40, 0x48, 0xBF, 10847 0x22, 0x40, 0x48, 0xBF,
108480x2A, 0x40, 0x50, 0xBF, 10848 0x2A, 0x40, 0x50, 0xBF,
10849 10849
108500x32, 0x41, 0x49, 0xBF, 10850 0x32, 0x41, 0x49, 0xBF,
108510x3A, 0x41, 0x51, 0xBF, 10851 0x3A, 0x41, 0x51, 0xBF,
10852 10852
108530xC3, 0x6B, 10853 0xC3, 0x6B,
108540xCB, 0x6B, 10854 0xCB, 0x6B,
108550x00, 0x88, 0x98, 0xE9, 10855 0x00, 0x88, 0x98, 0xE9,
10856 10856
108570x73, 0x7B, 0xC8, 0xEC, 10857 0x73, 0x7B, 0xC8, 0xEC,
108580x96, 0xE2, 10858 0x96, 0xE2,
108590x41, 0x04, 10859 0x41, 0x04,
10860 10860
108610x7B, 0x43, 0xA0, 0xE8, 10861 0x7B, 0x43, 0xA0, 0xE8,
108620x73, 0x4B, 0xA0, 0xE8, 10862 0x73, 0x4B, 0xA0, 0xE8,
10863 10863
108640xAD, 0xEE, 0x29, 0x9F, 10864 0xAD, 0xEE, 0x29, 0x9F,
108650x00, 0xE0, 10865 0x00, 0xE0,
108660x49, 0x04, 10866 0x49, 0x04,
10867 10867
108680x90, 0xE2, 10868 0x90, 0xE2,
108690x51, 0x04, 10869 0x51, 0x04,
108700x31, 0x46, 0xB1, 0xE8, 10870 0x31, 0x46, 0xB1, 0xE8,
10871 10871
108720x49, 0x41, 0xC0, 0xEC, 10872 0x49, 0x41, 0xC0, 0xEC,
108730x39, 0x57, 0xB1, 0xE8, 10873 0x39, 0x57, 0xB1, 0xE8,
10874 10874
108750x00, 0x04, 10875 0x00, 0x04,
108760x46, 0xE2, 10876 0x46, 0xE2,
108770x73, 0x53, 0xA0, 0xE8, 10877 0x73, 0x53, 0xA0, 0xE8,
10878 10878
108790x51, 0x41, 0xC0, 0xEC, 10879 0x51, 0x41, 0xC0, 0xEC,
108800x31, 0x00, 10880 0x31, 0x00,
108810x39, 0x00, 10881 0x39, 0x00,
10882 10882
108830x6E, 0x80, 0x15, 0xEA, 10883 0x6E, 0x80, 0x15, 0xEA,
108840x08, 0x04, 10884 0x08, 0x04,
108850x10, 0x04, 10885 0x10, 0x04,
10886 10886
108870x51, 0x49, 0xC0, 0xEC, 10887 0x51, 0x49, 0xC0, 0xEC,
108880x2F, 0x41, 0x60, 0xEA, 10888 0x2F, 0x41, 0x60, 0xEA,
10889 10889
108900x31, 0x20, 10890 0x31, 0x20,
108910x39, 0x20, 10891 0x39, 0x20,
108920x1F, 0x42, 0xA0, 0xE8, 10892 0x1F, 0x42, 0xA0, 0xE8,
10893 10893
108940x2A, 0x42, 0x4A, 0xBF, 10894 0x2A, 0x42, 0x4A, 0xBF,
108950x27, 0x4A, 0xA0, 0xE8, 10895 0x27, 0x4A, 0xA0, 0xE8,
10896 10896
108970x1A, 0x42, 0x52, 0xBF, 10897 0x1A, 0x42, 0x52, 0xBF,
108980x1E, 0x49, 0x60, 0xEA, 10898 0x1E, 0x49, 0x60, 0xEA,
10899 10899
109000x73, 0x7B, 0xC8, 0xEC, 10900 0x73, 0x7B, 0xC8, 0xEC,
109010x26, 0x51, 0x60, 0xEA, 10901 0x26, 0x51, 0x60, 0xEA,
10902 10902
109030x32, 0x40, 0x48, 0xBD, 10903 0x32, 0x40, 0x48, 0xBD,
109040x22, 0x40, 0x50, 0xBD, 10904 0x22, 0x40, 0x50, 0xBD,
10905 10905
109060x12, 0x41, 0x49, 0xBD, 10906 0x12, 0x41, 0x49, 0xBD,
109070x3A, 0x41, 0x51, 0xBD, 10907 0x3A, 0x41, 0x51, 0xBD,
10908 10908
109090xBF, 0x2F, 0x26, 0xBD, 10909 0xBF, 0x2F, 0x26, 0xBD,
109100x00, 0xE0, 10910 0x00, 0xE0,
109110x7B, 0x72, 10911 0x7B, 0x72,
10912 10912
109130x32, 0x20, 10913 0x32, 0x20,
109140x22, 0x20, 10914 0x22, 0x20,
109150x12, 0x20, 10915 0x12, 0x20,
109160x3A, 0x20, 10916 0x3A, 0x20,
10917 10917
109180x46, 0x31, 0x46, 0xBF, 10918 0x46, 0x31, 0x46, 0xBF,
109190x4E, 0x31, 0x4E, 0xBF, 10919 0x4E, 0x31, 0x4E, 0xBF,
10920 10920
109210xB3, 0xE2, 0x2D, 0x9F, 10921 0xB3, 0xE2, 0x2D, 0x9F,
109220x00, 0x80, 0x00, 0xE8, 10922 0x00, 0x80, 0x00, 0xE8,
10923 10923
109240x56, 0x31, 0x56, 0xBF, 10924 0x56, 0x31, 0x56, 0xBF,
109250x47, 0x39, 0x47, 0xBF, 10925 0x47, 0x39, 0x47, 0xBF,
10926 10926
109270x4F, 0x39, 0x4F, 0xBF, 10927 0x4F, 0x39, 0x4F, 0xBF,
109280x57, 0x39, 0x57, 0xBF, 10928 0x57, 0x39, 0x57, 0xBF,
10929 10929
109300x60, 0x80, 0x07, 0xEA, 10930 0x60, 0x80, 0x07, 0xEA,
109310x24, 0x41, 0x20, 0xE9, 10931 0x24, 0x41, 0x20, 0xE9,
10932 10932
109330x42, 0x73, 0xF8, 0xEC, 10933 0x42, 0x73, 0xF8, 0xEC,
109340x00, 0xE0, 10934 0x00, 0xE0,
109350x2D, 0x73, 10935 0x2D, 0x73,
10936 10936
109370x33, 0x72, 10937 0x33, 0x72,
109380x0C, 0xE3, 10938 0x0C, 0xE3,
109390xA5, 0x2F, 0x1E, 0xBD, 10939 0xA5, 0x2F, 0x1E, 0xBD,
10940 10940
109410x43, 0x43, 0x2D, 0xDF, 10941 0x43, 0x43, 0x2D, 0xDF,
109420x4B, 0x4B, 0x2D, 0xDF, 10942 0x4B, 0x4B, 0x2D, 0xDF,
10943 10943
109440xAE, 0x1E, 0x26, 0xBD, 10944 0xAE, 0x1E, 0x26, 0xBD,
109450x58, 0xE3, 10945 0x58, 0xE3,
109460x33, 0x66, 10946 0x33, 0x66,
10947 10947
109480x53, 0x53, 0x2D, 0xDF, 10948 0x53, 0x53, 0x2D, 0xDF,
109490x00, 0x80, 0x00, 0xE8, 10949 0x00, 0x80, 0x00, 0xE8,
10950 10950
109510xB8, 0x38, 0x33, 0xBF, 10951 0xB8, 0x38, 0x33, 0xBF,
109520x00, 0xE0, 10952 0x00, 0xE0,
109530x59, 0xE3, 10953 0x59, 0xE3,
10954 10954
109550x1E, 0x12, 0x41, 0xE9, 10955 0x1E, 0x12, 0x41, 0xE9,
109560x1A, 0x22, 0x41, 0xE9, 10956 0x1A, 0x22, 0x41, 0xE9,
10957 10957
109580x2B, 0x40, 0x3D, 0xE9, 10958 0x2B, 0x40, 0x3D, 0xE9,
109590x3F, 0x4B, 0xA0, 0xE8, 10959 0x3F, 0x4B, 0xA0, 0xE8,
10960 10960
109610x2D, 0x73, 10961 0x2D, 0x73,
109620x30, 0x76, 10962 0x30, 0x76,
109630x05, 0x80, 0x3D, 0xEA, 10963 0x05, 0x80, 0x3D, 0xEA,
10964 10964
109650x37, 0x43, 0xA0, 0xE8, 10965 0x37, 0x43, 0xA0, 0xE8,
109660x3D, 0x53, 0xA0, 0xE8, 10966 0x3D, 0x53, 0xA0, 0xE8,
10967 10967
109680x48, 0x70, 0xF8, 0xEC, 10968 0x48, 0x70, 0xF8, 0xEC,
109690x2B, 0x48, 0x3C, 0xE9, 10969 0x2B, 0x48, 0x3C, 0xE9,
10970 10970
109710x1F, 0x27, 0xBC, 0xE8, 10971 0x1F, 0x27, 0xBC, 0xE8,
109720x00, 0x80, 0x00, 0xE8, 10972 0x00, 0x80, 0x00, 0xE8,
10973 10973
109740x00, 0x80, 0x00, 0xE8, 10974 0x00, 0x80, 0x00, 0xE8,
109750x00, 0x80, 0x00, 0xE8, 10975 0x00, 0x80, 0x00, 0xE8,
10976 10976
109770x15, 0xC0, 0x20, 0xE9, 10977 0x15, 0xC0, 0x20, 0xE9,
109780x15, 0xC0, 0x20, 0xE9, 10978 0x15, 0xC0, 0x20, 0xE9,
10979 10979
109800x15, 0xC0, 0x20, 0xE9, 10980 0x15, 0xC0, 0x20, 0xE9,
109810x15, 0xC0, 0x20, 0xE9, 10981 0x15, 0xC0, 0x20, 0xE9,
10982 10982
109830x18, 0x3A, 0x41, 0xE9, 10983 0x18, 0x3A, 0x41, 0xE9,
109840x1D, 0x32, 0x41, 0xE9, 10984 0x1D, 0x32, 0x41, 0xE9,
10985 10985
109860x2A, 0x40, 0x20, 0xE9, 10986 0x2A, 0x40, 0x20, 0xE9,
109870x56, 0x3D, 0x56, 0xDF, 10987 0x56, 0x3D, 0x56, 0xDF,
10988 10988
109890x46, 0x37, 0x46, 0xDF, 10989 0x46, 0x37, 0x46, 0xDF,
109900x4E, 0x3F, 0x4E, 0xDF, 10990 0x4E, 0x3F, 0x4E, 0xDF,
10991 10991
109920x16, 0x30, 0x20, 0xE9, 10992 0x16, 0x30, 0x20, 0xE9,
109930x4F, 0x3F, 0x4F, 0xDF, 10993 0x4F, 0x3F, 0x4F, 0xDF,
10994 10994
109950x47, 0x37, 0x47, 0xDF, 10995 0x47, 0x37, 0x47, 0xDF,
109960x57, 0x3D, 0x57, 0xDF, 10996 0x57, 0x3D, 0x57, 0xDF,
10997 10997
109980x32, 0x32, 0x2D, 0xDF, 10998 0x32, 0x32, 0x2D, 0xDF,
109990x22, 0x22, 0x2D, 0xDF, 10999 0x22, 0x22, 0x2D, 0xDF,
11000 11000
110010x12, 0x12, 0x2D, 0xDF, 11001 0x12, 0x12, 0x2D, 0xDF,
110020x3A, 0x3A, 0x2D, 0xDF, 11002 0x3A, 0x3A, 0x2D, 0xDF,
11003 11003
110040x27, 0xCF, 0x74, 0xC2, 11004 0x27, 0xCF, 0x74, 0xC2,
110050x37, 0xCF, 0x74, 0xC4, 11005 0x37, 0xCF, 0x74, 0xC4,
11006 11006
110070x0A, 0x44, 0x4C, 0xB0, 11007 0x0A, 0x44, 0x4C, 0xB0,
110080x02, 0x44, 0x54, 0xB0, 11008 0x02, 0x44, 0x54, 0xB0,
11009 11009
110100x3D, 0xCF, 0x74, 0xC0, 11010 0x3D, 0xCF, 0x74, 0xC0,
110110x34, 0x37, 0x20, 0xE9, 11011 0x34, 0x37, 0x20, 0xE9,
11012 11012
110130x31, 0x53, 0x2F, 0x9F, 11013 0x31, 0x53, 0x2F, 0x9F,
110140x38, 0x27, 0x20, 0xE9, 11014 0x38, 0x27, 0x20, 0xE9,
11015 11015
110160x39, 0xE5, 0x2C, 0x9F, 11016 0x39, 0xE5, 0x2C, 0x9F,
110170x3C, 0x3D, 0x20, 0xE9, 11017 0x3C, 0x3D, 0x20, 0xE9,
11018 11018
110190x2A, 0x44, 0x4C, 0xB2, 11019 0x2A, 0x44, 0x4C, 0xB2,
110200x1A, 0x44, 0x54, 0xB2, 11020 0x1A, 0x44, 0x54, 0xB2,
11021 11021
110220x32, 0x80, 0x3A, 0xEA, 11022 0x32, 0x80, 0x3A, 0xEA,
110230x0A, 0x20, 11023 0x0A, 0x20,
110240x02, 0x20, 11024 0x02, 0x20,
11025 11025
110260x27, 0xCF, 0x75, 0xC0, 11026 0x27, 0xCF, 0x75, 0xC0,
110270x2A, 0x20, 11027 0x2A, 0x20,
110280x1A, 0x20, 11028 0x1A, 0x20,
11029 11029
110300x30, 0x50, 0x2E, 0x9F, 11030 0x30, 0x50, 0x2E, 0x9F,
110310x32, 0x31, 0x5F, 0xE9, 11031 0x32, 0x31, 0x5F, 0xE9,
11032 11032
110330x38, 0x21, 0x2C, 0x9F, 11033 0x38, 0x21, 0x2C, 0x9F,
110340x33, 0x39, 0x5F, 0xE9, 11034 0x33, 0x39, 0x5F, 0xE9,
11035 11035
110360x3D, 0xCF, 0x75, 0xC2, 11036 0x3D, 0xCF, 0x75, 0xC2,
110370x37, 0xCF, 0x75, 0xC4, 11037 0x37, 0xCF, 0x75, 0xC4,
11038 11038
110390x31, 0x53, 0x2F, 0x9F, 11039 0x31, 0x53, 0x2F, 0x9F,
110400xA6, 0x27, 0x20, 0xE9, 11040 0xA6, 0x27, 0x20, 0xE9,
11041 11041
110420x39, 0xE5, 0x2C, 0x9F, 11042 0x39, 0xE5, 0x2C, 0x9F,
110430xA3, 0x3D, 0x20, 0xE9, 11043 0xA3, 0x3D, 0x20, 0xE9,
11044 11044
110450x2A, 0x44, 0x4C, 0xB4, 11045 0x2A, 0x44, 0x4C, 0xB4,
110460x1A, 0x44, 0x54, 0xB4, 11046 0x1A, 0x44, 0x54, 0xB4,
11047 11047
110480x0A, 0x45, 0x4D, 0xB0, 11048 0x0A, 0x45, 0x4D, 0xB0,
110490x02, 0x45, 0x55, 0xB0, 11049 0x02, 0x45, 0x55, 0xB0,
11050 11050
110510x88, 0x73, 0x5E, 0xE9, 11051 0x88, 0x73, 0x5E, 0xE9,
110520x2A, 0x20, 11052 0x2A, 0x20,
110530x1A, 0x20, 11053 0x1A, 0x20,
11054 11054
110550xA0, 0x37, 0x20, 0xE9, 11055 0xA0, 0x37, 0x20, 0xE9,
110560x0A, 0x20, 11056 0x0A, 0x20,
110570x02, 0x20, 11057 0x02, 0x20,
11058 11058
110590x31, 0x53, 0x2F, 0x9F, 11059 0x31, 0x53, 0x2F, 0x9F,
110600x3E, 0x30, 0x4F, 0xE9, 11060 0x3E, 0x30, 0x4F, 0xE9,
11061 11061
110620x39, 0xE5, 0x2C, 0x9F, 11062 0x39, 0xE5, 0x2C, 0x9F,
110630x3F, 0x38, 0x4F, 0xE9, 11063 0x3F, 0x38, 0x4F, 0xE9,
11064 11064
110650x30, 0x50, 0x2E, 0x9F, 11065 0x30, 0x50, 0x2E, 0x9F,
110660x3A, 0x31, 0x4F, 0xE9, 11066 0x3A, 0x31, 0x4F, 0xE9,
11067 11067
110680x38, 0x21, 0x2C, 0x9F, 11068 0x38, 0x21, 0x2C, 0x9F,
110690x3B, 0x39, 0x4F, 0xE9, 11069 0x3B, 0x39, 0x4F, 0xE9,
11070 11070
110710x2A, 0x45, 0x4D, 0xB2, 11071 0x2A, 0x45, 0x4D, 0xB2,
110720x1A, 0x45, 0x55, 0xB2, 11072 0x1A, 0x45, 0x55, 0xB2,
11073 11073
110740x0A, 0x45, 0x4D, 0xB4, 11074 0x0A, 0x45, 0x4D, 0xB4,
110750x02, 0x45, 0x55, 0xB4, 11075 0x02, 0x45, 0x55, 0xB4,
11076 11076
110770x27, 0xCF, 0x74, 0xC6, 11077 0x27, 0xCF, 0x74, 0xC6,
110780x2A, 0x20, 11078 0x2A, 0x20,
110790x1A, 0x20, 11079 0x1A, 0x20,
11080 11080
110810xA7, 0x30, 0x4F, 0xE9, 11081 0xA7, 0x30, 0x4F, 0xE9,
110820x0A, 0x20, 11082 0x0A, 0x20,
110830x02, 0x20, 11083 0x02, 0x20,
11084 11084
110850x31, 0x53, 0x2F, 0x9F, 11085 0x31, 0x53, 0x2F, 0x9F,
110860x9C, 0x27, 0x20, 0xE9, 11086 0x9C, 0x27, 0x20, 0xE9,
11087 11087
110880x39, 0xE5, 0x2C, 0x9F, 11088 0x39, 0xE5, 0x2C, 0x9F,
110890xA8, 0x38, 0x4F, 0xE9, 11089 0xA8, 0x38, 0x4F, 0xE9,
11090 11090
110910x2A, 0x44, 0x4C, 0xB6, 11091 0x2A, 0x44, 0x4C, 0xB6,
110920x1A, 0x44, 0x54, 0xB6, 11092 0x1A, 0x44, 0x54, 0xB6,
11093 11093
110940x30, 0x50, 0x2E, 0x9F, 11094 0x30, 0x50, 0x2E, 0x9F,
110950x36, 0x31, 0x4F, 0xE9, 11095 0x36, 0x31, 0x4F, 0xE9,
11096 11096
110970x38, 0x21, 0x2C, 0x9F, 11097 0x38, 0x21, 0x2C, 0x9F,
110980x37, 0x39, 0x4F, 0xE9, 11098 0x37, 0x39, 0x4F, 0xE9,
11099 11099
111000x0A, 0x45, 0x4D, 0xB6, 11100 0x0A, 0x45, 0x4D, 0xB6,
111010x02, 0x45, 0x55, 0xB6, 11101 0x02, 0x45, 0x55, 0xB6,
11102 11102
111030x3D, 0xCF, 0x75, 0xC6, 11103 0x3D, 0xCF, 0x75, 0xC6,
111040x2A, 0x20, 11104 0x2A, 0x20,
111050x1A, 0x20, 11105 0x1A, 0x20,
11106 11106
111070x2A, 0x46, 0x4E, 0xBF, 11107 0x2A, 0x46, 0x4E, 0xBF,
111080x1A, 0x46, 0x56, 0xBF, 11108 0x1A, 0x46, 0x56, 0xBF,
11109 11109
111100x31, 0x53, 0x2F, 0x9F, 11110 0x31, 0x53, 0x2F, 0x9F,
111110xA4, 0x31, 0x4F, 0xE9, 11111 0xA4, 0x31, 0x4F, 0xE9,
11112 11112
111130x39, 0xE5, 0x2C, 0x9F, 11113 0x39, 0xE5, 0x2C, 0x9F,
111140xA5, 0x39, 0x4F, 0xE9, 11114 0xA5, 0x39, 0x4F, 0xE9,
11115 11115
111160x31, 0x3D, 0x20, 0xE9, 11116 0x31, 0x3D, 0x20, 0xE9,
111170x0A, 0x20, 11117 0x0A, 0x20,
111180x02, 0x20, 11118 0x02, 0x20,
11119 11119
111200x0A, 0x47, 0x4F, 0xBF, 11120 0x0A, 0x47, 0x4F, 0xBF,
111210x02, 0x47, 0x57, 0xBF, 11121 0x02, 0x47, 0x57, 0xBF,
11122 11122
111230x30, 0x50, 0x2E, 0x9F, 11123 0x30, 0x50, 0x2E, 0x9F,
111240xA1, 0x30, 0x4F, 0xE9, 11124 0xA1, 0x30, 0x4F, 0xE9,
11125 11125
111260x38, 0x21, 0x2C, 0x9F, 11126 0x38, 0x21, 0x2C, 0x9F,
111270xA2, 0x38, 0x4F, 0xE9, 11127 0xA2, 0x38, 0x4F, 0xE9,
11128 11128
111290x31, 0x53, 0x2F, 0x9F, 11129 0x31, 0x53, 0x2F, 0x9F,
111300x9D, 0x31, 0x4F, 0xE9, 11130 0x9D, 0x31, 0x4F, 0xE9,
11131 11131
111320x39, 0xE5, 0x2C, 0x9F, 11132 0x39, 0xE5, 0x2C, 0x9F,
111330x9E, 0x39, 0x4F, 0xE9, 11133 0x9E, 0x39, 0x4F, 0xE9,
11134 11134
111350x2A, 0x43, 0x4B, 0xBF, 11135 0x2A, 0x43, 0x4B, 0xBF,
111360x1A, 0x43, 0x53, 0xBF, 11136 0x1A, 0x43, 0x53, 0xBF,
11137 11137
111380x30, 0x50, 0x2E, 0x9F, 11138 0x30, 0x50, 0x2E, 0x9F,
111390x35, 0x30, 0x4F, 0xE9, 11139 0x35, 0x30, 0x4F, 0xE9,
11140 11140
111410x38, 0x21, 0x2C, 0x9F, 11141 0x38, 0x21, 0x2C, 0x9F,
111420x39, 0x38, 0x4F, 0xE9, 11142 0x39, 0x38, 0x4F, 0xE9,
11143 11143
111440x31, 0x53, 0x2F, 0x9F, 11144 0x31, 0x53, 0x2F, 0x9F,
111450x80, 0x31, 0x57, 0xE9, 11145 0x80, 0x31, 0x57, 0xE9,
11146 11146
111470x39, 0xE5, 0x2C, 0x9F, 11147 0x39, 0xE5, 0x2C, 0x9F,
111480x81, 0x39, 0x57, 0xE9, 11148 0x81, 0x39, 0x57, 0xE9,
11149 11149
111500x37, 0x48, 0x50, 0xBD, 11150 0x37, 0x48, 0x50, 0xBD,
111510x8A, 0x36, 0x20, 0xE9, 11151 0x8A, 0x36, 0x20, 0xE9,
11152 11152
111530x86, 0x76, 0x57, 0xE9, 11153 0x86, 0x76, 0x57, 0xE9,
111540x8B, 0x3E, 0x20, 0xE9, 11154 0x8B, 0x3E, 0x20, 0xE9,
11155 11155
111560x82, 0x30, 0x57, 0xE9, 11156 0x82, 0x30, 0x57, 0xE9,
111570x87, 0x77, 0x57, 0xE9, 11157 0x87, 0x77, 0x57, 0xE9,
11158 11158
111590x83, 0x38, 0x57, 0xE9, 11159 0x83, 0x38, 0x57, 0xE9,
111600x35, 0x49, 0x51, 0xBD, 11160 0x35, 0x49, 0x51, 0xBD,
11161 11161
111620x84, 0x31, 0x5E, 0xE9, 11162 0x84, 0x31, 0x5E, 0xE9,
111630x30, 0x1F, 0x5F, 0xE9, 11163 0x30, 0x1F, 0x5F, 0xE9,
11164 11164
111650x85, 0x39, 0x5E, 0xE9, 11165 0x85, 0x39, 0x5E, 0xE9,
111660x57, 0x25, 0x20, 0xE9, 11166 0x57, 0x25, 0x20, 0xE9,
11167 11167
111680x2B, 0x48, 0x20, 0xE9, 11168 0x2B, 0x48, 0x20, 0xE9,
111690x1D, 0x37, 0xE1, 0xEA, 11169 0x1D, 0x37, 0xE1, 0xEA,
11170 11170
111710x1E, 0x35, 0xE1, 0xEA, 11171 0x1E, 0x35, 0xE1, 0xEA,
111720x00, 0xE0, 11172 0x00, 0xE0,
111730x26, 0x77, 11173 0x26, 0x77,
11174 11174
111750x24, 0x49, 0x20, 0xE9, 11175 0x24, 0x49, 0x20, 0xE9,
111760x99, 0xFF, 0x20, 0xEA, 11176 0x99, 0xFF, 0x20, 0xEA,
11177 11177
111780x16, 0x26, 0x20, 0xE9, 11178 0x16, 0x26, 0x20, 0xE9,
111790x57, 0x2E, 0xBF, 0xEA, 11179 0x57, 0x2E, 0xBF, 0xEA,
11180 11180
111810x1C, 0x46, 0xA0, 0xE8, 11181 0x1C, 0x46, 0xA0, 0xE8,
111820x23, 0x4E, 0xA0, 0xE8, 11182 0x23, 0x4E, 0xA0, 0xE8,
11183 11183
111840x2B, 0x56, 0xA0, 0xE8, 11184 0x2B, 0x56, 0xA0, 0xE8,
111850x1D, 0x47, 0xA0, 0xE8, 11185 0x1D, 0x47, 0xA0, 0xE8,
11186 11186
111870x24, 0x4F, 0xA0, 0xE8, 11187 0x24, 0x4F, 0xA0, 0xE8,
111880x2C, 0x57, 0xA0, 0xE8, 11188 0x2C, 0x57, 0xA0, 0xE8,
11189 11189
111900x1C, 0x00, 11190 0x1C, 0x00,
111910x23, 0x00, 11191 0x23, 0x00,
111920x2B, 0x00, 11192 0x2B, 0x00,
111930x00, 0xE0, 11193 0x00, 0xE0,
11194 11194
111950x1D, 0x00, 11195 0x1D, 0x00,
111960x24, 0x00, 11196 0x24, 0x00,
111970x2C, 0x00, 11197 0x2C, 0x00,
111980x00, 0xE0, 11198 0x00, 0xE0,
11199 11199
112000x1C, 0x65, 11200 0x1C, 0x65,
112010x23, 0x65, 11201 0x23, 0x65,
112020x2B, 0x65, 11202 0x2B, 0x65,
112030x00, 0xE0, 11203 0x00, 0xE0,
11204 11204
112050x1D, 0x65, 11205 0x1D, 0x65,
112060x24, 0x65, 11206 0x24, 0x65,
112070x2C, 0x65, 11207 0x2C, 0x65,
112080x00, 0xE0, 11208 0x00, 0xE0,
11209 11209
112100x1C, 0x23, 0x60, 0xEC, 11210 0x1C, 0x23, 0x60, 0xEC,
112110x36, 0xD7, 0x36, 0xAD, 11211 0x36, 0xD7, 0x36, 0xAD,
11212 11212
112130x2B, 0x80, 0x60, 0xEC, 11213 0x2B, 0x80, 0x60, 0xEC,
112140x1D, 0x24, 0x60, 0xEC, 11214 0x1D, 0x24, 0x60, 0xEC,
11215 11215
112160x3E, 0xD7, 0x3E, 0xAD, 11216 0x3E, 0xD7, 0x3E, 0xAD,
112170x2C, 0x80, 0x60, 0xEC, 11217 0x2C, 0x80, 0x60, 0xEC,
11218 11218
112190x1C, 0x2B, 0xDE, 0xE8, 11219 0x1C, 0x2B, 0xDE, 0xE8,
112200x23, 0x80, 0xDE, 0xE8, 11220 0x23, 0x80, 0xDE, 0xE8,
11221 11221
112220x36, 0x80, 0x36, 0xBD, 11222 0x36, 0x80, 0x36, 0xBD,
112230x3E, 0x80, 0x3E, 0xBD, 11223 0x3E, 0x80, 0x3E, 0xBD,
11224 11224
112250x33, 0xD7, 0x1C, 0xBD, 11225 0x33, 0xD7, 0x1C, 0xBD,
112260x3B, 0xD7, 0x23, 0xBD, 11226 0x3B, 0xD7, 0x23, 0xBD,
11227 11227
112280x46, 0x80, 0x46, 0xCF, 11228 0x46, 0x80, 0x46, 0xCF,
112290x4F, 0x80, 0x4F, 0xCF, 11229 0x4F, 0x80, 0x4F, 0xCF,
11230 11230
112310x56, 0x33, 0x56, 0xCF, 11231 0x56, 0x33, 0x56, 0xCF,
112320x47, 0x3B, 0x47, 0xCF, 11232 0x47, 0x3B, 0x47, 0xCF,
11233 11233
112340xC1, 0xFF, 0x20, 0xEA, 11234 0xC1, 0xFF, 0x20, 0xEA,
112350x00, 0x80, 0x00, 0xE8, 11235 0x00, 0x80, 0x00, 0xE8,
11236 11236
112370x4E, 0x33, 0x4E, 0xCF, 11237 0x4E, 0x33, 0x4E, 0xCF,
112380x57, 0x3B, 0x57, 0xCF, 11238 0x57, 0x3B, 0x57, 0xCF,
11239 11239
112400x87, 0xFF, 0x20, 0xEA, 11240 0x87, 0xFF, 0x20, 0xEA,
112410x57, 0xC0, 0xBF, 0xEA, 11241 0x57, 0xC0, 0xBF, 0xEA,
11242 11242
112430x00, 0x80, 0xA0, 0xE9, 11243 0x00, 0x80, 0xA0, 0xE9,
112440x00, 0x00, 0xD8, 0xEC, 11244 0x00, 0x00, 0xD8, 0xEC,
11245 11245
11246}; 11246};
11247 11247
11248static unsigned char warp_g400_tgzsf[] = { 11248static unsigned char warp_g400_tgzsf[] = {
11249 11249
112500x00, 0x88, 0x98, 0xE9, 11250 0x00, 0x88, 0x98, 0xE9,
112510x00, 0x80, 0x00, 0xE8, 11251 0x00, 0x80, 0x00, 0xE8,
11252 11252
112530x00, 0x80, 0xA0, 0xE9, 11253 0x00, 0x80, 0xA0, 0xE9,
112540x00, 0x00, 0xD8, 0xEC, 11254 0x00, 0x00, 0xD8, 0xEC,
11255 11255
112560xFF, 0x80, 0xC0, 0xE9, 11256 0xFF, 0x80, 0xC0, 0xE9,
112570x00, 0x80, 0x00, 0xE8, 11257 0x00, 0x80, 0x00, 0xE8,
11258 11258
112590x22, 0x40, 0x48, 0xBF, 11259 0x22, 0x40, 0x48, 0xBF,
112600x2A, 0x40, 0x50, 0xBF, 11260 0x2A, 0x40, 0x50, 0xBF,
11261 11261
112620x32, 0x41, 0x49, 0xBF, 11262 0x32, 0x41, 0x49, 0xBF,
112630x3A, 0x41, 0x51, 0xBF, 11263 0x3A, 0x41, 0x51, 0xBF,
11264 11264
112650xC3, 0x6B, 11265 0xC3, 0x6B,
112660xCB, 0x6B, 11266 0xCB, 0x6B,
112670x00, 0x88, 0x98, 0xE9, 11267 0x00, 0x88, 0x98, 0xE9,
11268 11268
112690x73, 0x7B, 0xC8, 0xEC, 11269 0x73, 0x7B, 0xC8, 0xEC,
112700x96, 0xE2, 11270 0x96, 0xE2,
112710x41, 0x04, 11271 0x41, 0x04,
11272 11272
112730x7B, 0x43, 0xA0, 0xE8, 11273 0x7B, 0x43, 0xA0, 0xE8,
112740x73, 0x4B, 0xA0, 0xE8, 11274 0x73, 0x4B, 0xA0, 0xE8,
11275 11275
112760xAD, 0xEE, 0x29, 0x9F, 11276 0xAD, 0xEE, 0x29, 0x9F,
112770x00, 0xE0, 11277 0x00, 0xE0,
112780x49, 0x04, 11278 0x49, 0x04,
11279 11279
112800x90, 0xE2, 11280 0x90, 0xE2,
112810x51, 0x04, 11281 0x51, 0x04,
112820x31, 0x46, 0xB1, 0xE8, 11282 0x31, 0x46, 0xB1, 0xE8,
11283 11283
112840x49, 0x41, 0xC0, 0xEC, 11284 0x49, 0x41, 0xC0, 0xEC,
112850x39, 0x57, 0xB1, 0xE8, 11285 0x39, 0x57, 0xB1, 0xE8,
11286 11286
112870x00, 0x04, 11287 0x00, 0x04,
112880x46, 0xE2, 11288 0x46, 0xE2,
112890x73, 0x53, 0xA0, 0xE8, 11289 0x73, 0x53, 0xA0, 0xE8,
11290 11290
112910x51, 0x41, 0xC0, 0xEC, 11291 0x51, 0x41, 0xC0, 0xEC,
112920x31, 0x00, 11292 0x31, 0x00,
112930x39, 0x00, 11293 0x39, 0x00,
11294 11294
112950x6A, 0x80, 0x15, 0xEA, 11295 0x6A, 0x80, 0x15, 0xEA,
112960x08, 0x04, 11296 0x08, 0x04,
112970x10, 0x04, 11297 0x10, 0x04,
11298 11298
112990x51, 0x49, 0xC0, 0xEC, 11299 0x51, 0x49, 0xC0, 0xEC,
113000x2F, 0x41, 0x60, 0xEA, 11300 0x2F, 0x41, 0x60, 0xEA,
11301 11301
113020x31, 0x20, 11302 0x31, 0x20,
113030x39, 0x20, 11303 0x39, 0x20,
113040x1F, 0x42, 0xA0, 0xE8, 11304 0x1F, 0x42, 0xA0, 0xE8,
11305 11305
113060x2A, 0x42, 0x4A, 0xBF, 11306 0x2A, 0x42, 0x4A, 0xBF,
113070x27, 0x4A, 0xA0, 0xE8, 11307 0x27, 0x4A, 0xA0, 0xE8,
11308 11308
113090x1A, 0x42, 0x52, 0xBF, 11309 0x1A, 0x42, 0x52, 0xBF,
113100x1E, 0x49, 0x60, 0xEA, 11310 0x1E, 0x49, 0x60, 0xEA,
11311 11311
113120x73, 0x7B, 0xC8, 0xEC, 11312 0x73, 0x7B, 0xC8, 0xEC,
113130x26, 0x51, 0x60, 0xEA, 11313 0x26, 0x51, 0x60, 0xEA,
11314 11314
113150x32, 0x40, 0x48, 0xBD, 11315 0x32, 0x40, 0x48, 0xBD,
113160x22, 0x40, 0x50, 0xBD, 11316 0x22, 0x40, 0x50, 0xBD,
11317 11317
113180x12, 0x41, 0x49, 0xBD, 11318 0x12, 0x41, 0x49, 0xBD,
113190x3A, 0x41, 0x51, 0xBD, 11319 0x3A, 0x41, 0x51, 0xBD,
11320 11320
113210xBF, 0x2F, 0x26, 0xBD, 11321 0xBF, 0x2F, 0x26, 0xBD,
113220x00, 0xE0, 11322 0x00, 0xE0,
113230x7B, 0x72, 11323 0x7B, 0x72,
11324 11324
113250x32, 0x20, 11325 0x32, 0x20,
113260x22, 0x20, 11326 0x22, 0x20,
113270x12, 0x20, 11327 0x12, 0x20,
113280x3A, 0x20, 11328 0x3A, 0x20,
11329 11329
113300x46, 0x31, 0x46, 0xBF, 11330 0x46, 0x31, 0x46, 0xBF,
113310x4E, 0x31, 0x4E, 0xBF, 11331 0x4E, 0x31, 0x4E, 0xBF,
11332 11332
113330xB3, 0xE2, 0x2D, 0x9F, 11333 0xB3, 0xE2, 0x2D, 0x9F,
113340x00, 0x80, 0x00, 0xE8, 11334 0x00, 0x80, 0x00, 0xE8,
11335 11335
113360x56, 0x31, 0x56, 0xBF, 11336 0x56, 0x31, 0x56, 0xBF,
113370x47, 0x39, 0x47, 0xBF, 11337 0x47, 0x39, 0x47, 0xBF,
11338 11338
113390x4F, 0x39, 0x4F, 0xBF, 11339 0x4F, 0x39, 0x4F, 0xBF,
113400x57, 0x39, 0x57, 0xBF, 11340 0x57, 0x39, 0x57, 0xBF,
11341 11341
113420x5C, 0x80, 0x07, 0xEA, 11342 0x5C, 0x80, 0x07, 0xEA,
113430x24, 0x41, 0x20, 0xE9, 11343 0x24, 0x41, 0x20, 0xE9,
11344 11344
113450x42, 0x73, 0xF8, 0xEC, 11345 0x42, 0x73, 0xF8, 0xEC,
113460x00, 0xE0, 11346 0x00, 0xE0,
113470x2D, 0x73, 11347 0x2D, 0x73,
11348 11348
113490x33, 0x72, 11349 0x33, 0x72,
113500x0C, 0xE3, 11350 0x0C, 0xE3,
113510xA5, 0x2F, 0x1E, 0xBD, 11351 0xA5, 0x2F, 0x1E, 0xBD,
11352 11352
113530x43, 0x43, 0x2D, 0xDF, 11353 0x43, 0x43, 0x2D, 0xDF,
113540x4B, 0x4B, 0x2D, 0xDF, 11354 0x4B, 0x4B, 0x2D, 0xDF,
11355 11355
113560xAE, 0x1E, 0x26, 0xBD, 11356 0xAE, 0x1E, 0x26, 0xBD,
113570x58, 0xE3, 11357 0x58, 0xE3,
113580x33, 0x66, 11358 0x33, 0x66,
11359 11359
113600x53, 0x53, 0x2D, 0xDF, 11360 0x53, 0x53, 0x2D, 0xDF,
113610x00, 0x80, 0x00, 0xE8, 11361 0x00, 0x80, 0x00, 0xE8,
11362 11362
113630xB8, 0x38, 0x33, 0xBF, 11363 0xB8, 0x38, 0x33, 0xBF,
113640x00, 0xE0, 11364 0x00, 0xE0,
113650x59, 0xE3, 11365 0x59, 0xE3,
11366 11366
113670x1E, 0x12, 0x41, 0xE9, 11367 0x1E, 0x12, 0x41, 0xE9,
113680x1A, 0x22, 0x41, 0xE9, 11368 0x1A, 0x22, 0x41, 0xE9,
11369 11369
113700x2B, 0x40, 0x3D, 0xE9, 11370 0x2B, 0x40, 0x3D, 0xE9,
113710x3F, 0x4B, 0xA0, 0xE8, 11371 0x3F, 0x4B, 0xA0, 0xE8,
11372 11372
113730x2D, 0x73, 11373 0x2D, 0x73,
113740x30, 0x76, 11374 0x30, 0x76,
113750x05, 0x80, 0x3D, 0xEA, 11375 0x05, 0x80, 0x3D, 0xEA,
11376 11376
113770x37, 0x43, 0xA0, 0xE8, 11377 0x37, 0x43, 0xA0, 0xE8,
113780x3D, 0x53, 0xA0, 0xE8, 11378 0x3D, 0x53, 0xA0, 0xE8,
11379 11379
113800x48, 0x70, 0xF8, 0xEC, 11380 0x48, 0x70, 0xF8, 0xEC,
113810x2B, 0x48, 0x3C, 0xE9, 11381 0x2B, 0x48, 0x3C, 0xE9,
11382 11382
113830x1F, 0x27, 0xBC, 0xE8, 11383 0x1F, 0x27, 0xBC, 0xE8,
113840x00, 0x80, 0x00, 0xE8, 11384 0x00, 0x80, 0x00, 0xE8,
11385 11385
113860x00, 0x80, 0x00, 0xE8, 11386 0x00, 0x80, 0x00, 0xE8,
113870x00, 0x80, 0x00, 0xE8, 11387 0x00, 0x80, 0x00, 0xE8,
11388 11388
113890x15, 0xC0, 0x20, 0xE9, 11389 0x15, 0xC0, 0x20, 0xE9,
113900x15, 0xC0, 0x20, 0xE9, 11390 0x15, 0xC0, 0x20, 0xE9,
11391 11391
113920x15, 0xC0, 0x20, 0xE9, 11392 0x15, 0xC0, 0x20, 0xE9,
113930x15, 0xC0, 0x20, 0xE9, 11393 0x15, 0xC0, 0x20, 0xE9,
11394 11394
113950x18, 0x3A, 0x41, 0xE9, 11395 0x18, 0x3A, 0x41, 0xE9,
113960x1D, 0x32, 0x41, 0xE9, 11396 0x1D, 0x32, 0x41, 0xE9,
11397 11397
113980x2A, 0x40, 0x20, 0xE9, 11398 0x2A, 0x40, 0x20, 0xE9,
113990x56, 0x3D, 0x56, 0xDF, 11399 0x56, 0x3D, 0x56, 0xDF,
11400 11400
114010x46, 0x37, 0x46, 0xDF, 11401 0x46, 0x37, 0x46, 0xDF,
114020x4E, 0x3F, 0x4E, 0xDF, 11402 0x4E, 0x3F, 0x4E, 0xDF,
11403 11403
114040x16, 0x30, 0x20, 0xE9, 11404 0x16, 0x30, 0x20, 0xE9,
114050x4F, 0x3F, 0x4F, 0xDF, 11405 0x4F, 0x3F, 0x4F, 0xDF,
11406 11406
114070x47, 0x37, 0x47, 0xDF, 11407 0x47, 0x37, 0x47, 0xDF,
114080x57, 0x3D, 0x57, 0xDF, 11408 0x57, 0x3D, 0x57, 0xDF,
11409 11409
114100x32, 0x32, 0x2D, 0xDF, 11410 0x32, 0x32, 0x2D, 0xDF,
114110x22, 0x22, 0x2D, 0xDF, 11411 0x22, 0x22, 0x2D, 0xDF,
11412 11412
114130x12, 0x12, 0x2D, 0xDF, 11413 0x12, 0x12, 0x2D, 0xDF,
114140x3A, 0x3A, 0x2D, 0xDF, 11414 0x3A, 0x3A, 0x2D, 0xDF,
11415 11415
114160x27, 0xCF, 0x74, 0xC2, 11416 0x27, 0xCF, 0x74, 0xC2,
114170x37, 0xCF, 0x74, 0xC4, 11417 0x37, 0xCF, 0x74, 0xC4,
11418 11418
114190x0A, 0x44, 0x4C, 0xB0, 11419 0x0A, 0x44, 0x4C, 0xB0,
114200x02, 0x44, 0x54, 0xB0, 11420 0x02, 0x44, 0x54, 0xB0,
11421 11421
114220x3D, 0xCF, 0x74, 0xC0, 11422 0x3D, 0xCF, 0x74, 0xC0,
114230x34, 0x37, 0x20, 0xE9, 11423 0x34, 0x37, 0x20, 0xE9,
11424 11424
114250x31, 0x53, 0x2F, 0x9F, 11425 0x31, 0x53, 0x2F, 0x9F,
114260x38, 0x27, 0x20, 0xE9, 11426 0x38, 0x27, 0x20, 0xE9,
11427 11427
114280x39, 0xE5, 0x2C, 0x9F, 11428 0x39, 0xE5, 0x2C, 0x9F,
114290x3C, 0x3D, 0x20, 0xE9, 11429 0x3C, 0x3D, 0x20, 0xE9,
11430 11430
114310x2A, 0x44, 0x4C, 0xB2, 11431 0x2A, 0x44, 0x4C, 0xB2,
114320x1A, 0x44, 0x54, 0xB2, 11432 0x1A, 0x44, 0x54, 0xB2,
11433 11433
114340x2E, 0x80, 0x3A, 0xEA, 11434 0x2E, 0x80, 0x3A, 0xEA,
114350x0A, 0x20, 11435 0x0A, 0x20,
114360x02, 0x20, 11436 0x02, 0x20,
11437 11437
114380x27, 0xCF, 0x75, 0xC0, 11438 0x27, 0xCF, 0x75, 0xC0,
114390x2A, 0x20, 11439 0x2A, 0x20,
114400x1A, 0x20, 11440 0x1A, 0x20,
11441 11441
114420x30, 0x50, 0x2E, 0x9F, 11442 0x30, 0x50, 0x2E, 0x9F,
114430x32, 0x31, 0x5F, 0xE9, 11443 0x32, 0x31, 0x5F, 0xE9,
11444 11444
114450x38, 0x21, 0x2C, 0x9F, 11445 0x38, 0x21, 0x2C, 0x9F,
114460x33, 0x39, 0x5F, 0xE9, 11446 0x33, 0x39, 0x5F, 0xE9,
11447 11447
114480x3D, 0xCF, 0x75, 0xC2, 11448 0x3D, 0xCF, 0x75, 0xC2,
114490x37, 0xCF, 0x75, 0xC4, 11449 0x37, 0xCF, 0x75, 0xC4,
11450 11450
114510x31, 0x53, 0x2F, 0x9F, 11451 0x31, 0x53, 0x2F, 0x9F,
114520xA6, 0x27, 0x20, 0xE9, 11452 0xA6, 0x27, 0x20, 0xE9,
11453 11453
114540x39, 0xE5, 0x2C, 0x9F, 11454 0x39, 0xE5, 0x2C, 0x9F,
114550xA3, 0x3D, 0x20, 0xE9, 11455 0xA3, 0x3D, 0x20, 0xE9,
11456 11456
114570x2A, 0x44, 0x4C, 0xB4, 11457 0x2A, 0x44, 0x4C, 0xB4,
114580x1A, 0x44, 0x54, 0xB4, 11458 0x1A, 0x44, 0x54, 0xB4,
11459 11459
114600x0A, 0x45, 0x4D, 0xB0, 11460 0x0A, 0x45, 0x4D, 0xB0,
114610x02, 0x45, 0x55, 0xB0, 11461 0x02, 0x45, 0x55, 0xB0,
11462 11462
114630x88, 0x73, 0x5E, 0xE9, 11463 0x88, 0x73, 0x5E, 0xE9,
114640x2A, 0x20, 11464 0x2A, 0x20,
114650x1A, 0x20, 11465 0x1A, 0x20,
11466 11466
114670xA0, 0x37, 0x20, 0xE9, 11467 0xA0, 0x37, 0x20, 0xE9,
114680x0A, 0x20, 11468 0x0A, 0x20,
114690x02, 0x20, 11469 0x02, 0x20,
11470 11470
114710x31, 0x53, 0x2F, 0x9F, 11471 0x31, 0x53, 0x2F, 0x9F,
114720x3E, 0x30, 0x4F, 0xE9, 11472 0x3E, 0x30, 0x4F, 0xE9,
11473 11473
114740x39, 0xE5, 0x2C, 0x9F, 11474 0x39, 0xE5, 0x2C, 0x9F,
114750x3F, 0x38, 0x4F, 0xE9, 11475 0x3F, 0x38, 0x4F, 0xE9,
11476 11476
114770x30, 0x50, 0x2E, 0x9F, 11477 0x30, 0x50, 0x2E, 0x9F,
114780x3A, 0x31, 0x4F, 0xE9, 11478 0x3A, 0x31, 0x4F, 0xE9,
11479 11479
114800x38, 0x21, 0x2C, 0x9F, 11480 0x38, 0x21, 0x2C, 0x9F,
114810x3B, 0x39, 0x4F, 0xE9, 11481 0x3B, 0x39, 0x4F, 0xE9,
11482 11482
114830x2A, 0x45, 0x4D, 0xB2, 11483 0x2A, 0x45, 0x4D, 0xB2,
114840x1A, 0x45, 0x55, 0xB2, 11484 0x1A, 0x45, 0x55, 0xB2,
11485 11485
114860x0A, 0x45, 0x4D, 0xB4, 11486 0x0A, 0x45, 0x4D, 0xB4,
114870x02, 0x45, 0x55, 0xB4, 11487 0x02, 0x45, 0x55, 0xB4,
11488 11488
114890x27, 0xCF, 0x75, 0xC6, 11489 0x27, 0xCF, 0x75, 0xC6,
114900x2A, 0x20, 11490 0x2A, 0x20,
114910x1A, 0x20, 11491 0x1A, 0x20,
11492 11492
114930xA7, 0x30, 0x4F, 0xE9, 11493 0xA7, 0x30, 0x4F, 0xE9,
114940x0A, 0x20, 11494 0x0A, 0x20,
114950x02, 0x20, 11495 0x02, 0x20,
11496 11496
114970x31, 0x53, 0x2F, 0x9F, 11497 0x31, 0x53, 0x2F, 0x9F,
114980x31, 0x27, 0x20, 0xE9, 11498 0x31, 0x27, 0x20, 0xE9,
11499 11499
115000x39, 0xE5, 0x2C, 0x9F, 11500 0x39, 0xE5, 0x2C, 0x9F,
115010xA8, 0x38, 0x4F, 0xE9, 11501 0xA8, 0x38, 0x4F, 0xE9,
11502 11502
115030x2A, 0x45, 0x4D, 0xB6, 11503 0x2A, 0x45, 0x4D, 0xB6,
115040x1A, 0x45, 0x55, 0xB6, 11504 0x1A, 0x45, 0x55, 0xB6,
11505 11505
115060x30, 0x50, 0x2E, 0x9F, 11506 0x30, 0x50, 0x2E, 0x9F,
115070x36, 0x31, 0x4F, 0xE9, 11507 0x36, 0x31, 0x4F, 0xE9,
11508 11508
115090x38, 0x21, 0x2C, 0x9F, 11509 0x38, 0x21, 0x2C, 0x9F,
115100x37, 0x39, 0x4F, 0xE9, 11510 0x37, 0x39, 0x4F, 0xE9,
11511 11511
115120x00, 0x80, 0x00, 0xE8, 11512 0x00, 0x80, 0x00, 0xE8,
115130x2A, 0x20, 11513 0x2A, 0x20,
115140x1A, 0x20, 11514 0x1A, 0x20,
11515 11515
115160x2A, 0x46, 0x4E, 0xBF, 11516 0x2A, 0x46, 0x4E, 0xBF,
115170x1A, 0x46, 0x56, 0xBF, 11517 0x1A, 0x46, 0x56, 0xBF,
11518 11518
115190x31, 0x53, 0x2F, 0x9F, 11519 0x31, 0x53, 0x2F, 0x9F,
115200xA4, 0x31, 0x4F, 0xE9, 11520 0xA4, 0x31, 0x4F, 0xE9,
11521 11521
115220x39, 0xE5, 0x2C, 0x9F, 11522 0x39, 0xE5, 0x2C, 0x9F,
115230xA5, 0x39, 0x4F, 0xE9, 11523 0xA5, 0x39, 0x4F, 0xE9,
11524 11524
115250x0A, 0x47, 0x4F, 0xBF, 11525 0x0A, 0x47, 0x4F, 0xBF,
115260x02, 0x47, 0x57, 0xBF, 11526 0x02, 0x47, 0x57, 0xBF,
11527 11527
115280x31, 0x53, 0x2F, 0x9F, 11528 0x31, 0x53, 0x2F, 0x9F,
115290xA1, 0x30, 0x4F, 0xE9, 11529 0xA1, 0x30, 0x4F, 0xE9,
11530 11530
115310x39, 0xE5, 0x2C, 0x9F, 11531 0x39, 0xE5, 0x2C, 0x9F,
115320xA2, 0x38, 0x4F, 0xE9, 11532 0xA2, 0x38, 0x4F, 0xE9,
11533 11533
115340x2A, 0x43, 0x4B, 0xBF, 11534 0x2A, 0x43, 0x4B, 0xBF,
115350x1A, 0x43, 0x53, 0xBF, 11535 0x1A, 0x43, 0x53, 0xBF,
11536 11536
115370x30, 0x50, 0x2E, 0x9F, 11537 0x30, 0x50, 0x2E, 0x9F,
115380x35, 0x31, 0x4F, 0xE9, 11538 0x35, 0x31, 0x4F, 0xE9,
11539 11539
115400x38, 0x21, 0x2C, 0x9F, 11540 0x38, 0x21, 0x2C, 0x9F,
115410x39, 0x39, 0x4F, 0xE9, 11541 0x39, 0x39, 0x4F, 0xE9,
11542 11542
115430x31, 0x53, 0x2F, 0x9F, 11543 0x31, 0x53, 0x2F, 0x9F,
115440x80, 0x31, 0x57, 0xE9, 11544 0x80, 0x31, 0x57, 0xE9,
11545 11545
115460x39, 0xE5, 0x2C, 0x9F, 11546 0x39, 0xE5, 0x2C, 0x9F,
115470x81, 0x39, 0x57, 0xE9, 11547 0x81, 0x39, 0x57, 0xE9,
11548 11548
115490x37, 0x48, 0x50, 0xBD, 11549 0x37, 0x48, 0x50, 0xBD,
115500x8A, 0x36, 0x20, 0xE9, 11550 0x8A, 0x36, 0x20, 0xE9,
11551 11551
115520x86, 0x76, 0x57, 0xE9, 11552 0x86, 0x76, 0x57, 0xE9,
115530x8B, 0x3E, 0x20, 0xE9, 11553 0x8B, 0x3E, 0x20, 0xE9,
11554 11554
115550x82, 0x30, 0x57, 0xE9, 11555 0x82, 0x30, 0x57, 0xE9,
115560x87, 0x77, 0x57, 0xE9, 11556 0x87, 0x77, 0x57, 0xE9,
11557 11557
115580x83, 0x38, 0x57, 0xE9, 11558 0x83, 0x38, 0x57, 0xE9,
115590x35, 0x49, 0x51, 0xBD, 11559 0x35, 0x49, 0x51, 0xBD,
11560 11560
115610x84, 0x31, 0x5E, 0xE9, 11561 0x84, 0x31, 0x5E, 0xE9,
115620x30, 0x1F, 0x5F, 0xE9, 11562 0x30, 0x1F, 0x5F, 0xE9,
11563 11563
115640x85, 0x39, 0x5E, 0xE9, 11564 0x85, 0x39, 0x5E, 0xE9,
115650x57, 0x25, 0x20, 0xE9, 11565 0x57, 0x25, 0x20, 0xE9,
11566 11566
115670x2B, 0x48, 0x20, 0xE9, 11567 0x2B, 0x48, 0x20, 0xE9,
115680x1D, 0x37, 0xE1, 0xEA, 11568 0x1D, 0x37, 0xE1, 0xEA,
11569 11569
115700x1E, 0x35, 0xE1, 0xEA, 11570 0x1E, 0x35, 0xE1, 0xEA,
115710x00, 0xE0, 11571 0x00, 0xE0,
115720x26, 0x77, 11572 0x26, 0x77,
11573 11573
115740x24, 0x49, 0x20, 0xE9, 11574 0x24, 0x49, 0x20, 0xE9,
115750x9D, 0xFF, 0x20, 0xEA, 11575 0x9D, 0xFF, 0x20, 0xEA,
11576 11576
115770x16, 0x26, 0x20, 0xE9, 11577 0x16, 0x26, 0x20, 0xE9,
115780x57, 0x2E, 0xBF, 0xEA, 11578 0x57, 0x2E, 0xBF, 0xEA,
11579 11579
115800x1C, 0x46, 0xA0, 0xE8, 11580 0x1C, 0x46, 0xA0, 0xE8,
115810x23, 0x4E, 0xA0, 0xE8, 11581 0x23, 0x4E, 0xA0, 0xE8,
11582 11582
115830x2B, 0x56, 0xA0, 0xE8, 11583 0x2B, 0x56, 0xA0, 0xE8,
115840x1D, 0x47, 0xA0, 0xE8, 11584 0x1D, 0x47, 0xA0, 0xE8,
11585 11585
115860x24, 0x4F, 0xA0, 0xE8, 11586 0x24, 0x4F, 0xA0, 0xE8,
115870x2C, 0x57, 0xA0, 0xE8, 11587 0x2C, 0x57, 0xA0, 0xE8,
11588 11588
115890x1C, 0x00, 11589 0x1C, 0x00,
115900x23, 0x00, 11590 0x23, 0x00,
115910x2B, 0x00, 11591 0x2B, 0x00,
115920x00, 0xE0, 11592 0x00, 0xE0,
11593 11593
115940x1D, 0x00, 11594 0x1D, 0x00,
115950x24, 0x00, 11595 0x24, 0x00,
115960x2C, 0x00, 11596 0x2C, 0x00,
115970x00, 0xE0, 11597 0x00, 0xE0,
11598 11598
115990x1C, 0x65, 11599 0x1C, 0x65,
116000x23, 0x65, 11600 0x23, 0x65,
116010x2B, 0x65, 11601 0x2B, 0x65,
116020x00, 0xE0, 11602 0x00, 0xE0,
11603 11603
116040x1D, 0x65, 11604 0x1D, 0x65,
116050x24, 0x65, 11605 0x24, 0x65,
116060x2C, 0x65, 11606 0x2C, 0x65,
116070x00, 0xE0, 11607 0x00, 0xE0,
11608 11608
116090x1C, 0x23, 0x60, 0xEC, 11609 0x1C, 0x23, 0x60, 0xEC,
116100x36, 0xD7, 0x36, 0xAD, 11610 0x36, 0xD7, 0x36, 0xAD,
11611 11611
116120x2B, 0x80, 0x60, 0xEC, 11612 0x2B, 0x80, 0x60, 0xEC,
116130x1D, 0x24, 0x60, 0xEC, 11613 0x1D, 0x24, 0x60, 0xEC,
11614 11614
116150x3E, 0xD7, 0x3E, 0xAD, 11615 0x3E, 0xD7, 0x3E, 0xAD,
116160x2C, 0x80, 0x60, 0xEC, 11616 0x2C, 0x80, 0x60, 0xEC,
11617 11617
116180x1C, 0x2B, 0xDE, 0xE8, 11618 0x1C, 0x2B, 0xDE, 0xE8,
116190x23, 0x80, 0xDE, 0xE8, 11619 0x23, 0x80, 0xDE, 0xE8,
11620 11620
116210x36, 0x80, 0x36, 0xBD, 11621 0x36, 0x80, 0x36, 0xBD,
116220x3E, 0x80, 0x3E, 0xBD, 11622 0x3E, 0x80, 0x3E, 0xBD,
11623 11623
116240x33, 0xD7, 0x1C, 0xBD, 11624 0x33, 0xD7, 0x1C, 0xBD,
116250x3B, 0xD7, 0x23, 0xBD, 11625 0x3B, 0xD7, 0x23, 0xBD,
11626 11626
116270x46, 0x80, 0x46, 0xCF, 11627 0x46, 0x80, 0x46, 0xCF,
116280x4F, 0x80, 0x4F, 0xCF, 11628 0x4F, 0x80, 0x4F, 0xCF,
11629 11629
116300x56, 0x33, 0x56, 0xCF, 11630 0x56, 0x33, 0x56, 0xCF,
116310x47, 0x3B, 0x47, 0xCF, 11631 0x47, 0x3B, 0x47, 0xCF,
11632 11632
116330xC5, 0xFF, 0x20, 0xEA, 11633 0xC5, 0xFF, 0x20, 0xEA,
116340x00, 0x80, 0x00, 0xE8, 11634 0x00, 0x80, 0x00, 0xE8,
11635 11635
116360x4E, 0x33, 0x4E, 0xCF, 11636 0x4E, 0x33, 0x4E, 0xCF,
116370x57, 0x3B, 0x57, 0xCF, 11637 0x57, 0x3B, 0x57, 0xCF,
11638 11638
116390x8B, 0xFF, 0x20, 0xEA, 11639 0x8B, 0xFF, 0x20, 0xEA,
116400x57, 0xC0, 0xBF, 0xEA, 11640 0x57, 0xC0, 0xBF, 0xEA,
11641 11641
116420x00, 0x80, 0xA0, 0xE9, 11642 0x00, 0x80, 0xA0, 0xE9,
116430x00, 0x00, 0xD8, 0xEC, 11643 0x00, 0x00, 0xD8, 0xEC,
11644 11644
11645}; 11645};
diff --git a/drivers/char/drm/mga_warp.c b/drivers/char/drm/mga_warp.c
index 55ccc8a0ac29..d67f4925fbac 100644
--- a/drivers/char/drm/mga_warp.c
+++ b/drivers/char/drm/mga_warp.c
@@ -33,8 +33,7 @@
33#include "mga_drv.h" 33#include "mga_drv.h"
34#include "mga_ucode.h" 34#include "mga_ucode.h"
35 35
36 36#define MGA_WARP_CODE_ALIGN 256 /* in bytes */
37#define MGA_WARP_CODE_ALIGN 256 /* in bytes */
38 37
39#define WARP_UCODE_SIZE( which ) \ 38#define WARP_UCODE_SIZE( which ) \
40 ((sizeof(which) / MGA_WARP_CODE_ALIGN + 1) * MGA_WARP_CODE_ALIGN) 39 ((sizeof(which) / MGA_WARP_CODE_ALIGN + 1) * MGA_WARP_CODE_ALIGN)
@@ -49,33 +48,30 @@ do { \
49} while (0) 48} while (0)
50 49
51static const unsigned int mga_warp_g400_microcode_size = 50static const unsigned int mga_warp_g400_microcode_size =
52 (WARP_UCODE_SIZE(warp_g400_tgz) + 51 (WARP_UCODE_SIZE(warp_g400_tgz) +
53 WARP_UCODE_SIZE(warp_g400_tgza) + 52 WARP_UCODE_SIZE(warp_g400_tgza) +
54 WARP_UCODE_SIZE(warp_g400_tgzaf) + 53 WARP_UCODE_SIZE(warp_g400_tgzaf) +
55 WARP_UCODE_SIZE(warp_g400_tgzf) + 54 WARP_UCODE_SIZE(warp_g400_tgzf) +
56 WARP_UCODE_SIZE(warp_g400_tgzs) + 55 WARP_UCODE_SIZE(warp_g400_tgzs) +
57 WARP_UCODE_SIZE(warp_g400_tgzsa) + 56 WARP_UCODE_SIZE(warp_g400_tgzsa) +
58 WARP_UCODE_SIZE(warp_g400_tgzsaf) + 57 WARP_UCODE_SIZE(warp_g400_tgzsaf) +
59 WARP_UCODE_SIZE(warp_g400_tgzsf) + 58 WARP_UCODE_SIZE(warp_g400_tgzsf) +
60 WARP_UCODE_SIZE(warp_g400_t2gz) + 59 WARP_UCODE_SIZE(warp_g400_t2gz) +
61 WARP_UCODE_SIZE(warp_g400_t2gza) + 60 WARP_UCODE_SIZE(warp_g400_t2gza) +
62 WARP_UCODE_SIZE(warp_g400_t2gzaf) + 61 WARP_UCODE_SIZE(warp_g400_t2gzaf) +
63 WARP_UCODE_SIZE(warp_g400_t2gzf) + 62 WARP_UCODE_SIZE(warp_g400_t2gzf) +
64 WARP_UCODE_SIZE(warp_g400_t2gzs) + 63 WARP_UCODE_SIZE(warp_g400_t2gzs) +
65 WARP_UCODE_SIZE(warp_g400_t2gzsa) + 64 WARP_UCODE_SIZE(warp_g400_t2gzsa) +
66 WARP_UCODE_SIZE(warp_g400_t2gzsaf) + 65 WARP_UCODE_SIZE(warp_g400_t2gzsaf) + WARP_UCODE_SIZE(warp_g400_t2gzsf));
67 WARP_UCODE_SIZE(warp_g400_t2gzsf));
68 66
69static const unsigned int mga_warp_g200_microcode_size = 67static const unsigned int mga_warp_g200_microcode_size =
70 (WARP_UCODE_SIZE(warp_g200_tgz) + 68 (WARP_UCODE_SIZE(warp_g200_tgz) +
71 WARP_UCODE_SIZE(warp_g200_tgza) + 69 WARP_UCODE_SIZE(warp_g200_tgza) +
72 WARP_UCODE_SIZE(warp_g200_tgzaf) + 70 WARP_UCODE_SIZE(warp_g200_tgzaf) +
73 WARP_UCODE_SIZE(warp_g200_tgzf) + 71 WARP_UCODE_SIZE(warp_g200_tgzf) +
74 WARP_UCODE_SIZE(warp_g200_tgzs) + 72 WARP_UCODE_SIZE(warp_g200_tgzs) +
75 WARP_UCODE_SIZE(warp_g200_tgzsa) + 73 WARP_UCODE_SIZE(warp_g200_tgzsa) +
76 WARP_UCODE_SIZE(warp_g200_tgzsaf) + 74 WARP_UCODE_SIZE(warp_g200_tgzsaf) + WARP_UCODE_SIZE(warp_g200_tgzsf));
77 WARP_UCODE_SIZE(warp_g200_tgzsf));
78
79 75
80unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv) 76unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv)
81{ 77{
@@ -90,36 +86,35 @@ unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv)
90 } 86 }
91} 87}
92 88
93static int mga_warp_install_g400_microcode( drm_mga_private_t *dev_priv ) 89static int mga_warp_install_g400_microcode(drm_mga_private_t * dev_priv)
94{ 90{
95 unsigned char *vcbase = dev_priv->warp->handle; 91 unsigned char *vcbase = dev_priv->warp->handle;
96 unsigned long pcbase = dev_priv->warp->offset; 92 unsigned long pcbase = dev_priv->warp->offset;
97 93
98 memset( dev_priv->warp_pipe_phys, 0, 94 memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys));
99 sizeof(dev_priv->warp_pipe_phys) ); 95
100 96 WARP_UCODE_INSTALL(warp_g400_tgz, MGA_WARP_TGZ);
101 WARP_UCODE_INSTALL( warp_g400_tgz, MGA_WARP_TGZ ); 97 WARP_UCODE_INSTALL(warp_g400_tgzf, MGA_WARP_TGZF);
102 WARP_UCODE_INSTALL( warp_g400_tgzf, MGA_WARP_TGZF ); 98 WARP_UCODE_INSTALL(warp_g400_tgza, MGA_WARP_TGZA);
103 WARP_UCODE_INSTALL( warp_g400_tgza, MGA_WARP_TGZA ); 99 WARP_UCODE_INSTALL(warp_g400_tgzaf, MGA_WARP_TGZAF);
104 WARP_UCODE_INSTALL( warp_g400_tgzaf, MGA_WARP_TGZAF ); 100 WARP_UCODE_INSTALL(warp_g400_tgzs, MGA_WARP_TGZS);
105 WARP_UCODE_INSTALL( warp_g400_tgzs, MGA_WARP_TGZS ); 101 WARP_UCODE_INSTALL(warp_g400_tgzsf, MGA_WARP_TGZSF);
106 WARP_UCODE_INSTALL( warp_g400_tgzsf, MGA_WARP_TGZSF ); 102 WARP_UCODE_INSTALL(warp_g400_tgzsa, MGA_WARP_TGZSA);
107 WARP_UCODE_INSTALL( warp_g400_tgzsa, MGA_WARP_TGZSA ); 103 WARP_UCODE_INSTALL(warp_g400_tgzsaf, MGA_WARP_TGZSAF);
108 WARP_UCODE_INSTALL( warp_g400_tgzsaf, MGA_WARP_TGZSAF ); 104
109 105 WARP_UCODE_INSTALL(warp_g400_t2gz, MGA_WARP_T2GZ);
110 WARP_UCODE_INSTALL( warp_g400_t2gz, MGA_WARP_T2GZ ); 106 WARP_UCODE_INSTALL(warp_g400_t2gzf, MGA_WARP_T2GZF);
111 WARP_UCODE_INSTALL( warp_g400_t2gzf, MGA_WARP_T2GZF ); 107 WARP_UCODE_INSTALL(warp_g400_t2gza, MGA_WARP_T2GZA);
112 WARP_UCODE_INSTALL( warp_g400_t2gza, MGA_WARP_T2GZA ); 108 WARP_UCODE_INSTALL(warp_g400_t2gzaf, MGA_WARP_T2GZAF);
113 WARP_UCODE_INSTALL( warp_g400_t2gzaf, MGA_WARP_T2GZAF ); 109 WARP_UCODE_INSTALL(warp_g400_t2gzs, MGA_WARP_T2GZS);
114 WARP_UCODE_INSTALL( warp_g400_t2gzs, MGA_WARP_T2GZS ); 110 WARP_UCODE_INSTALL(warp_g400_t2gzsf, MGA_WARP_T2GZSF);
115 WARP_UCODE_INSTALL( warp_g400_t2gzsf, MGA_WARP_T2GZSF ); 111 WARP_UCODE_INSTALL(warp_g400_t2gzsa, MGA_WARP_T2GZSA);
116 WARP_UCODE_INSTALL( warp_g400_t2gzsa, MGA_WARP_T2GZSA ); 112 WARP_UCODE_INSTALL(warp_g400_t2gzsaf, MGA_WARP_T2GZSAF);
117 WARP_UCODE_INSTALL( warp_g400_t2gzsaf, MGA_WARP_T2GZSAF );
118 113
119 return 0; 114 return 0;
120} 115}
121 116
122static int mga_warp_install_g200_microcode( drm_mga_private_t *dev_priv ) 117static int mga_warp_install_g200_microcode(drm_mga_private_t * dev_priv)
123{ 118{
124 unsigned char *vcbase = dev_priv->warp->handle; 119 unsigned char *vcbase = dev_priv->warp->handle;
125 unsigned long pcbase = dev_priv->warp->offset; 120 unsigned long pcbase = dev_priv->warp->offset;
@@ -138,7 +133,7 @@ static int mga_warp_install_g200_microcode( drm_mga_private_t *dev_priv )
138 return 0; 133 return 0;
139} 134}
140 135
141int mga_warp_install_microcode( drm_mga_private_t *dev_priv ) 136int mga_warp_install_microcode(drm_mga_private_t * dev_priv)
142{ 137{
143 const unsigned int size = mga_warp_microcode_size(dev_priv); 138 const unsigned int size = mga_warp_microcode_size(dev_priv);
144 139
@@ -154,7 +149,7 @@ int mga_warp_install_microcode( drm_mga_private_t *dev_priv )
154 case MGA_CARD_TYPE_G550: 149 case MGA_CARD_TYPE_G550:
155 return mga_warp_install_g400_microcode(dev_priv); 150 return mga_warp_install_g400_microcode(dev_priv);
156 case MGA_CARD_TYPE_G200: 151 case MGA_CARD_TYPE_G200:
157 return mga_warp_install_g200_microcode( dev_priv ); 152 return mga_warp_install_g200_microcode(dev_priv);
158 default: 153 default:
159 return DRM_ERR(EINVAL); 154 return DRM_ERR(EINVAL);
160 } 155 }
@@ -162,13 +157,13 @@ int mga_warp_install_microcode( drm_mga_private_t *dev_priv )
162 157
163#define WMISC_EXPECTED (MGA_WUCODECACHE_ENABLE | MGA_WMASTER_ENABLE) 158#define WMISC_EXPECTED (MGA_WUCODECACHE_ENABLE | MGA_WMASTER_ENABLE)
164 159
165int mga_warp_init( drm_mga_private_t *dev_priv ) 160int mga_warp_init(drm_mga_private_t * dev_priv)
166{ 161{
167 u32 wmisc; 162 u32 wmisc;
168 163
169 /* FIXME: Get rid of these damned magic numbers... 164 /* FIXME: Get rid of these damned magic numbers...
170 */ 165 */
171 switch ( dev_priv->chipset ) { 166 switch (dev_priv->chipset) {
172 case MGA_CARD_TYPE_G400: 167 case MGA_CARD_TYPE_G400:
173 case MGA_CARD_TYPE_G550: 168 case MGA_CARD_TYPE_G550:
174 MGA_WRITE(MGA_WIADDR2, MGA_WMODE_SUSPEND); 169 MGA_WRITE(MGA_WIADDR2, MGA_WMODE_SUSPEND);
@@ -177,21 +172,20 @@ int mga_warp_init( drm_mga_private_t *dev_priv )
177 MGA_WRITE(MGA_WACCEPTSEQ, 0x18000000); 172 MGA_WRITE(MGA_WACCEPTSEQ, 0x18000000);
178 break; 173 break;
179 case MGA_CARD_TYPE_G200: 174 case MGA_CARD_TYPE_G200:
180 MGA_WRITE( MGA_WIADDR, MGA_WMODE_SUSPEND ); 175 MGA_WRITE(MGA_WIADDR, MGA_WMODE_SUSPEND);
181 MGA_WRITE( MGA_WGETMSB, 0x1606 ); 176 MGA_WRITE(MGA_WGETMSB, 0x1606);
182 MGA_WRITE( MGA_WVRTXSZ, 7 ); 177 MGA_WRITE(MGA_WVRTXSZ, 7);
183 break; 178 break;
184 default: 179 default:
185 return DRM_ERR(EINVAL); 180 return DRM_ERR(EINVAL);
186 } 181 }
187 182
188 MGA_WRITE( MGA_WMISC, (MGA_WUCODECACHE_ENABLE | 183 MGA_WRITE(MGA_WMISC, (MGA_WUCODECACHE_ENABLE |
189 MGA_WMASTER_ENABLE | 184 MGA_WMASTER_ENABLE | MGA_WCACHEFLUSH_ENABLE));
190 MGA_WCACHEFLUSH_ENABLE) ); 185 wmisc = MGA_READ(MGA_WMISC);
191 wmisc = MGA_READ( MGA_WMISC ); 186 if (wmisc != WMISC_EXPECTED) {
192 if ( wmisc != WMISC_EXPECTED ) { 187 DRM_ERROR("WARP engine config failed! 0x%x != 0x%x\n",
193 DRM_ERROR( "WARP engine config failed! 0x%x != 0x%x\n", 188 wmisc, WMISC_EXPECTED);
194 wmisc, WMISC_EXPECTED );
195 return DRM_ERR(EINVAL); 189 return DRM_ERR(EINVAL);
196 } 190 }
197 191
diff --git a/drivers/char/drm/r128_cce.c b/drivers/char/drm/r128_cce.c
index ac3ea2bc9b28..7452753d4d01 100644
--- a/drivers/char/drm/r128_cce.c
+++ b/drivers/char/drm/r128_cce.c
@@ -80,7 +80,7 @@ static u32 r128_cce_microcode[] = {
80 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 80 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
81}; 81};
82 82
83static int R128_READ_PLL(drm_device_t *dev, int addr) 83static int R128_READ_PLL(drm_device_t * dev, int addr)
84{ 84{
85 drm_r128_private_t *dev_priv = dev->dev_private; 85 drm_r128_private_t *dev_priv = dev->dev_private;
86 86
@@ -89,106 +89,105 @@ static int R128_READ_PLL(drm_device_t *dev, int addr)
89} 89}
90 90
91#if R128_FIFO_DEBUG 91#if R128_FIFO_DEBUG
92static void r128_status( drm_r128_private_t *dev_priv ) 92static void r128_status(drm_r128_private_t * dev_priv)
93{ 93{
94 printk( "GUI_STAT = 0x%08x\n", 94 printk("GUI_STAT = 0x%08x\n",
95 (unsigned int)R128_READ( R128_GUI_STAT ) ); 95 (unsigned int)R128_READ(R128_GUI_STAT));
96 printk( "PM4_STAT = 0x%08x\n", 96 printk("PM4_STAT = 0x%08x\n",
97 (unsigned int)R128_READ( R128_PM4_STAT ) ); 97 (unsigned int)R128_READ(R128_PM4_STAT));
98 printk( "PM4_BUFFER_DL_WPTR = 0x%08x\n", 98 printk("PM4_BUFFER_DL_WPTR = 0x%08x\n",
99 (unsigned int)R128_READ( R128_PM4_BUFFER_DL_WPTR ) ); 99 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR));
100 printk( "PM4_BUFFER_DL_RPTR = 0x%08x\n", 100 printk("PM4_BUFFER_DL_RPTR = 0x%08x\n",
101 (unsigned int)R128_READ( R128_PM4_BUFFER_DL_RPTR ) ); 101 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR));
102 printk( "PM4_MICRO_CNTL = 0x%08x\n", 102 printk("PM4_MICRO_CNTL = 0x%08x\n",
103 (unsigned int)R128_READ( R128_PM4_MICRO_CNTL ) ); 103 (unsigned int)R128_READ(R128_PM4_MICRO_CNTL));
104 printk( "PM4_BUFFER_CNTL = 0x%08x\n", 104 printk("PM4_BUFFER_CNTL = 0x%08x\n",
105 (unsigned int)R128_READ( R128_PM4_BUFFER_CNTL ) ); 105 (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL));
106} 106}
107#endif 107#endif
108 108
109
110/* ================================================================ 109/* ================================================================
111 * Engine, FIFO control 110 * Engine, FIFO control
112 */ 111 */
113 112
114static int r128_do_pixcache_flush( drm_r128_private_t *dev_priv ) 113static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv)
115{ 114{
116 u32 tmp; 115 u32 tmp;
117 int i; 116 int i;
118 117
119 tmp = R128_READ( R128_PC_NGUI_CTLSTAT ) | R128_PC_FLUSH_ALL; 118 tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL;
120 R128_WRITE( R128_PC_NGUI_CTLSTAT, tmp ); 119 R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp);
121 120
122 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 121 for (i = 0; i < dev_priv->usec_timeout; i++) {
123 if ( !(R128_READ( R128_PC_NGUI_CTLSTAT ) & R128_PC_BUSY) ) { 122 if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY)) {
124 return 0; 123 return 0;
125 } 124 }
126 DRM_UDELAY( 1 ); 125 DRM_UDELAY(1);
127 } 126 }
128 127
129#if R128_FIFO_DEBUG 128#if R128_FIFO_DEBUG
130 DRM_ERROR( "failed!\n" ); 129 DRM_ERROR("failed!\n");
131#endif 130#endif
132 return DRM_ERR(EBUSY); 131 return DRM_ERR(EBUSY);
133} 132}
134 133
135static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries ) 134static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries)
136{ 135{
137 int i; 136 int i;
138 137
139 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 138 for (i = 0; i < dev_priv->usec_timeout; i++) {
140 int slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK; 139 int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK;
141 if ( slots >= entries ) return 0; 140 if (slots >= entries)
142 DRM_UDELAY( 1 ); 141 return 0;
142 DRM_UDELAY(1);
143 } 143 }
144 144
145#if R128_FIFO_DEBUG 145#if R128_FIFO_DEBUG
146 DRM_ERROR( "failed!\n" ); 146 DRM_ERROR("failed!\n");
147#endif 147#endif
148 return DRM_ERR(EBUSY); 148 return DRM_ERR(EBUSY);
149} 149}
150 150
151static int r128_do_wait_for_idle( drm_r128_private_t *dev_priv ) 151static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv)
152{ 152{
153 int i, ret; 153 int i, ret;
154 154
155 ret = r128_do_wait_for_fifo( dev_priv, 64 ); 155 ret = r128_do_wait_for_fifo(dev_priv, 64);
156 if ( ret ) return ret; 156 if (ret)
157 return ret;
157 158
158 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 159 for (i = 0; i < dev_priv->usec_timeout; i++) {
159 if ( !(R128_READ( R128_GUI_STAT ) & R128_GUI_ACTIVE) ) { 160 if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) {
160 r128_do_pixcache_flush( dev_priv ); 161 r128_do_pixcache_flush(dev_priv);
161 return 0; 162 return 0;
162 } 163 }
163 DRM_UDELAY( 1 ); 164 DRM_UDELAY(1);
164 } 165 }
165 166
166#if R128_FIFO_DEBUG 167#if R128_FIFO_DEBUG
167 DRM_ERROR( "failed!\n" ); 168 DRM_ERROR("failed!\n");
168#endif 169#endif
169 return DRM_ERR(EBUSY); 170 return DRM_ERR(EBUSY);
170} 171}
171 172
172
173/* ================================================================ 173/* ================================================================
174 * CCE control, initialization 174 * CCE control, initialization
175 */ 175 */
176 176
177/* Load the microcode for the CCE */ 177/* Load the microcode for the CCE */
178static void r128_cce_load_microcode( drm_r128_private_t *dev_priv ) 178static void r128_cce_load_microcode(drm_r128_private_t * dev_priv)
179{ 179{
180 int i; 180 int i;
181 181
182 DRM_DEBUG( "\n" ); 182 DRM_DEBUG("\n");
183 183
184 r128_do_wait_for_idle( dev_priv ); 184 r128_do_wait_for_idle(dev_priv);
185 185
186 R128_WRITE( R128_PM4_MICROCODE_ADDR, 0 ); 186 R128_WRITE(R128_PM4_MICROCODE_ADDR, 0);
187 for ( i = 0 ; i < 256 ; i++ ) { 187 for (i = 0; i < 256; i++) {
188 R128_WRITE( R128_PM4_MICROCODE_DATAH, 188 R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]);
189 r128_cce_microcode[i * 2] ); 189 R128_WRITE(R128_PM4_MICROCODE_DATAL,
190 R128_WRITE( R128_PM4_MICROCODE_DATAL, 190 r128_cce_microcode[i * 2 + 1]);
191 r128_cce_microcode[i * 2 + 1] );
192 } 191 }
193} 192}
194 193
@@ -196,51 +195,51 @@ static void r128_cce_load_microcode( drm_r128_private_t *dev_priv )
196 * prior to a wait for idle, as it informs the engine that the command 195 * prior to a wait for idle, as it informs the engine that the command
197 * stream is ending. 196 * stream is ending.
198 */ 197 */
199static void r128_do_cce_flush( drm_r128_private_t *dev_priv ) 198static void r128_do_cce_flush(drm_r128_private_t * dev_priv)
200{ 199{
201 u32 tmp; 200 u32 tmp;
202 201
203 tmp = R128_READ( R128_PM4_BUFFER_DL_WPTR ) | R128_PM4_BUFFER_DL_DONE; 202 tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE;
204 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, tmp ); 203 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp);
205} 204}
206 205
207/* Wait for the CCE to go idle. 206/* Wait for the CCE to go idle.
208 */ 207 */
209int r128_do_cce_idle( drm_r128_private_t *dev_priv ) 208int r128_do_cce_idle(drm_r128_private_t * dev_priv)
210{ 209{
211 int i; 210 int i;
212 211
213 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 212 for (i = 0; i < dev_priv->usec_timeout; i++) {
214 if ( GET_RING_HEAD( dev_priv ) == dev_priv->ring.tail ) { 213 if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) {
215 int pm4stat = R128_READ( R128_PM4_STAT ); 214 int pm4stat = R128_READ(R128_PM4_STAT);
216 if ( ( (pm4stat & R128_PM4_FIFOCNT_MASK) >= 215 if (((pm4stat & R128_PM4_FIFOCNT_MASK) >=
217 dev_priv->cce_fifo_size ) && 216 dev_priv->cce_fifo_size) &&
218 !(pm4stat & (R128_PM4_BUSY | 217 !(pm4stat & (R128_PM4_BUSY |
219 R128_PM4_GUI_ACTIVE)) ) { 218 R128_PM4_GUI_ACTIVE))) {
220 return r128_do_pixcache_flush( dev_priv ); 219 return r128_do_pixcache_flush(dev_priv);
221 } 220 }
222 } 221 }
223 DRM_UDELAY( 1 ); 222 DRM_UDELAY(1);
224 } 223 }
225 224
226#if R128_FIFO_DEBUG 225#if R128_FIFO_DEBUG
227 DRM_ERROR( "failed!\n" ); 226 DRM_ERROR("failed!\n");
228 r128_status( dev_priv ); 227 r128_status(dev_priv);
229#endif 228#endif
230 return DRM_ERR(EBUSY); 229 return DRM_ERR(EBUSY);
231} 230}
232 231
233/* Start the Concurrent Command Engine. 232/* Start the Concurrent Command Engine.
234 */ 233 */
235static void r128_do_cce_start( drm_r128_private_t *dev_priv ) 234static void r128_do_cce_start(drm_r128_private_t * dev_priv)
236{ 235{
237 r128_do_wait_for_idle( dev_priv ); 236 r128_do_wait_for_idle(dev_priv);
238 237
239 R128_WRITE( R128_PM4_BUFFER_CNTL, 238 R128_WRITE(R128_PM4_BUFFER_CNTL,
240 dev_priv->cce_mode | dev_priv->ring.size_l2qw 239 dev_priv->cce_mode | dev_priv->ring.size_l2qw
241 | R128_PM4_BUFFER_CNTL_NOUPDATE ); 240 | R128_PM4_BUFFER_CNTL_NOUPDATE);
242 R128_READ( R128_PM4_BUFFER_ADDR ); /* as per the sample code */ 241 R128_READ(R128_PM4_BUFFER_ADDR); /* as per the sample code */
243 R128_WRITE( R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN ); 242 R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN);
244 243
245 dev_priv->cce_running = 1; 244 dev_priv->cce_running = 1;
246} 245}
@@ -249,10 +248,10 @@ static void r128_do_cce_start( drm_r128_private_t *dev_priv )
249 * commands, so you must wait for the CCE command stream to complete 248 * commands, so you must wait for the CCE command stream to complete
250 * before calling this routine. 249 * before calling this routine.
251 */ 250 */
252static void r128_do_cce_reset( drm_r128_private_t *dev_priv ) 251static void r128_do_cce_reset(drm_r128_private_t * dev_priv)
253{ 252{
254 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 ); 253 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
255 R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 ); 254 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
256 dev_priv->ring.tail = 0; 255 dev_priv->ring.tail = 0;
257} 256}
258 257
@@ -260,122 +259,120 @@ static void r128_do_cce_reset( drm_r128_private_t *dev_priv )
260 * commands, so you must flush the command stream and wait for the CCE 259 * commands, so you must flush the command stream and wait for the CCE
261 * to go idle before calling this routine. 260 * to go idle before calling this routine.
262 */ 261 */
263static void r128_do_cce_stop( drm_r128_private_t *dev_priv ) 262static void r128_do_cce_stop(drm_r128_private_t * dev_priv)
264{ 263{
265 R128_WRITE( R128_PM4_MICRO_CNTL, 0 ); 264 R128_WRITE(R128_PM4_MICRO_CNTL, 0);
266 R128_WRITE( R128_PM4_BUFFER_CNTL, 265 R128_WRITE(R128_PM4_BUFFER_CNTL,
267 R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE ); 266 R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE);
268 267
269 dev_priv->cce_running = 0; 268 dev_priv->cce_running = 0;
270} 269}
271 270
272/* Reset the engine. This will stop the CCE if it is running. 271/* Reset the engine. This will stop the CCE if it is running.
273 */ 272 */
274static int r128_do_engine_reset( drm_device_t *dev ) 273static int r128_do_engine_reset(drm_device_t * dev)
275{ 274{
276 drm_r128_private_t *dev_priv = dev->dev_private; 275 drm_r128_private_t *dev_priv = dev->dev_private;
277 u32 clock_cntl_index, mclk_cntl, gen_reset_cntl; 276 u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
278 277
279 r128_do_pixcache_flush( dev_priv ); 278 r128_do_pixcache_flush(dev_priv);
280 279
281 clock_cntl_index = R128_READ( R128_CLOCK_CNTL_INDEX ); 280 clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX);
282 mclk_cntl = R128_READ_PLL( dev, R128_MCLK_CNTL ); 281 mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL);
283 282
284 R128_WRITE_PLL( R128_MCLK_CNTL, 283 R128_WRITE_PLL(R128_MCLK_CNTL,
285 mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP ); 284 mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP);
286 285
287 gen_reset_cntl = R128_READ( R128_GEN_RESET_CNTL ); 286 gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL);
288 287
289 /* Taken from the sample code - do not change */ 288 /* Taken from the sample code - do not change */
290 R128_WRITE( R128_GEN_RESET_CNTL, 289 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI);
291 gen_reset_cntl | R128_SOFT_RESET_GUI ); 290 R128_READ(R128_GEN_RESET_CNTL);
292 R128_READ( R128_GEN_RESET_CNTL ); 291 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI);
293 R128_WRITE( R128_GEN_RESET_CNTL, 292 R128_READ(R128_GEN_RESET_CNTL);
294 gen_reset_cntl & ~R128_SOFT_RESET_GUI );
295 R128_READ( R128_GEN_RESET_CNTL );
296 293
297 R128_WRITE_PLL( R128_MCLK_CNTL, mclk_cntl ); 294 R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl);
298 R128_WRITE( R128_CLOCK_CNTL_INDEX, clock_cntl_index ); 295 R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index);
299 R128_WRITE( R128_GEN_RESET_CNTL, gen_reset_cntl ); 296 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl);
300 297
301 /* Reset the CCE ring */ 298 /* Reset the CCE ring */
302 r128_do_cce_reset( dev_priv ); 299 r128_do_cce_reset(dev_priv);
303 300
304 /* The CCE is no longer running after an engine reset */ 301 /* The CCE is no longer running after an engine reset */
305 dev_priv->cce_running = 0; 302 dev_priv->cce_running = 0;
306 303
307 /* Reset any pending vertex, indirect buffers */ 304 /* Reset any pending vertex, indirect buffers */
308 r128_freelist_reset( dev ); 305 r128_freelist_reset(dev);
309 306
310 return 0; 307 return 0;
311} 308}
312 309
313static void r128_cce_init_ring_buffer( drm_device_t *dev, 310static void r128_cce_init_ring_buffer(drm_device_t * dev,
314 drm_r128_private_t *dev_priv ) 311 drm_r128_private_t * dev_priv)
315{ 312{
316 u32 ring_start; 313 u32 ring_start;
317 u32 tmp; 314 u32 tmp;
318 315
319 DRM_DEBUG( "\n" ); 316 DRM_DEBUG("\n");
320 317
321 /* The manual (p. 2) says this address is in "VM space". This 318 /* The manual (p. 2) says this address is in "VM space". This
322 * means it's an offset from the start of AGP space. 319 * means it's an offset from the start of AGP space.
323 */ 320 */
324#if __OS_HAS_AGP 321#if __OS_HAS_AGP
325 if ( !dev_priv->is_pci ) 322 if (!dev_priv->is_pci)
326 ring_start = dev_priv->cce_ring->offset - dev->agp->base; 323 ring_start = dev_priv->cce_ring->offset - dev->agp->base;
327 else 324 else
328#endif 325#endif
329 ring_start = dev_priv->cce_ring->offset - 326 ring_start = dev_priv->cce_ring->offset -
330 (unsigned long)dev->sg->virtual; 327 (unsigned long)dev->sg->virtual;
331 328
332 R128_WRITE( R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET ); 329 R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET);
333 330
334 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 ); 331 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
335 R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 ); 332 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
336 333
337 /* Set watermark control */ 334 /* Set watermark control */
338 R128_WRITE( R128_PM4_BUFFER_WM_CNTL, 335 R128_WRITE(R128_PM4_BUFFER_WM_CNTL,
339 ((R128_WATERMARK_L/4) << R128_WMA_SHIFT) 336 ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT)
340 | ((R128_WATERMARK_M/4) << R128_WMB_SHIFT) 337 | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT)
341 | ((R128_WATERMARK_N/4) << R128_WMC_SHIFT) 338 | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT)
342 | ((R128_WATERMARK_K/64) << R128_WB_WM_SHIFT) ); 339 | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT));
343 340
344 /* Force read. Why? Because it's in the examples... */ 341 /* Force read. Why? Because it's in the examples... */
345 R128_READ( R128_PM4_BUFFER_ADDR ); 342 R128_READ(R128_PM4_BUFFER_ADDR);
346 343
347 /* Turn on bus mastering */ 344 /* Turn on bus mastering */
348 tmp = R128_READ( R128_BUS_CNTL ) & ~R128_BUS_MASTER_DIS; 345 tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS;
349 R128_WRITE( R128_BUS_CNTL, tmp ); 346 R128_WRITE(R128_BUS_CNTL, tmp);
350} 347}
351 348
352static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) 349static int r128_do_init_cce(drm_device_t * dev, drm_r128_init_t * init)
353{ 350{
354 drm_r128_private_t *dev_priv; 351 drm_r128_private_t *dev_priv;
355 352
356 DRM_DEBUG( "\n" ); 353 DRM_DEBUG("\n");
357 354
358 dev_priv = drm_alloc( sizeof(drm_r128_private_t), DRM_MEM_DRIVER ); 355 dev_priv = drm_alloc(sizeof(drm_r128_private_t), DRM_MEM_DRIVER);
359 if ( dev_priv == NULL ) 356 if (dev_priv == NULL)
360 return DRM_ERR(ENOMEM); 357 return DRM_ERR(ENOMEM);
361 358
362 memset( dev_priv, 0, sizeof(drm_r128_private_t) ); 359 memset(dev_priv, 0, sizeof(drm_r128_private_t));
363 360
364 dev_priv->is_pci = init->is_pci; 361 dev_priv->is_pci = init->is_pci;
365 362
366 if ( dev_priv->is_pci && !dev->sg ) { 363 if (dev_priv->is_pci && !dev->sg) {
367 DRM_ERROR( "PCI GART memory not allocated!\n" ); 364 DRM_ERROR("PCI GART memory not allocated!\n");
368 dev->dev_private = (void *)dev_priv; 365 dev->dev_private = (void *)dev_priv;
369 r128_do_cleanup_cce( dev ); 366 r128_do_cleanup_cce(dev);
370 return DRM_ERR(EINVAL); 367 return DRM_ERR(EINVAL);
371 } 368 }
372 369
373 dev_priv->usec_timeout = init->usec_timeout; 370 dev_priv->usec_timeout = init->usec_timeout;
374 if ( dev_priv->usec_timeout < 1 || 371 if (dev_priv->usec_timeout < 1 ||
375 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT ) { 372 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) {
376 DRM_DEBUG( "TIMEOUT problem!\n" ); 373 DRM_DEBUG("TIMEOUT problem!\n");
377 dev->dev_private = (void *)dev_priv; 374 dev->dev_private = (void *)dev_priv;
378 r128_do_cleanup_cce( dev ); 375 r128_do_cleanup_cce(dev);
379 return DRM_ERR(EINVAL); 376 return DRM_ERR(EINVAL);
380 } 377 }
381 378
@@ -383,23 +380,23 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
383 380
384 /* GH: Simple idle check. 381 /* GH: Simple idle check.
385 */ 382 */
386 atomic_set( &dev_priv->idle_count, 0 ); 383 atomic_set(&dev_priv->idle_count, 0);
387 384
388 /* We don't support anything other than bus-mastering ring mode, 385 /* We don't support anything other than bus-mastering ring mode,
389 * but the ring can be in either AGP or PCI space for the ring 386 * but the ring can be in either AGP or PCI space for the ring
390 * read pointer. 387 * read pointer.
391 */ 388 */
392 if ( ( init->cce_mode != R128_PM4_192BM ) && 389 if ((init->cce_mode != R128_PM4_192BM) &&
393 ( init->cce_mode != R128_PM4_128BM_64INDBM ) && 390 (init->cce_mode != R128_PM4_128BM_64INDBM) &&
394 ( init->cce_mode != R128_PM4_64BM_128INDBM ) && 391 (init->cce_mode != R128_PM4_64BM_128INDBM) &&
395 ( init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM ) ) { 392 (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) {
396 DRM_DEBUG( "Bad cce_mode!\n" ); 393 DRM_DEBUG("Bad cce_mode!\n");
397 dev->dev_private = (void *)dev_priv; 394 dev->dev_private = (void *)dev_priv;
398 r128_do_cleanup_cce( dev ); 395 r128_do_cleanup_cce(dev);
399 return DRM_ERR(EINVAL); 396 return DRM_ERR(EINVAL);
400 } 397 }
401 398
402 switch ( init->cce_mode ) { 399 switch (init->cce_mode) {
403 case R128_PM4_NONPM4: 400 case R128_PM4_NONPM4:
404 dev_priv->cce_fifo_size = 0; 401 dev_priv->cce_fifo_size = 0;
405 break; 402 break;
@@ -420,7 +417,7 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
420 break; 417 break;
421 } 418 }
422 419
423 switch ( init->fb_bpp ) { 420 switch (init->fb_bpp) {
424 case 16: 421 case 16:
425 dev_priv->color_fmt = R128_DATATYPE_RGB565; 422 dev_priv->color_fmt = R128_DATATYPE_RGB565;
426 break; 423 break;
@@ -429,12 +426,12 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
429 dev_priv->color_fmt = R128_DATATYPE_ARGB8888; 426 dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
430 break; 427 break;
431 } 428 }
432 dev_priv->front_offset = init->front_offset; 429 dev_priv->front_offset = init->front_offset;
433 dev_priv->front_pitch = init->front_pitch; 430 dev_priv->front_pitch = init->front_pitch;
434 dev_priv->back_offset = init->back_offset; 431 dev_priv->back_offset = init->back_offset;
435 dev_priv->back_pitch = init->back_pitch; 432 dev_priv->back_pitch = init->back_pitch;
436 433
437 switch ( init->depth_bpp ) { 434 switch (init->depth_bpp) {
438 case 16: 435 case 16:
439 dev_priv->depth_fmt = R128_DATATYPE_RGB565; 436 dev_priv->depth_fmt = R128_DATATYPE_RGB565;
440 break; 437 break;
@@ -444,131 +441,130 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
444 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888; 441 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
445 break; 442 break;
446 } 443 }
447 dev_priv->depth_offset = init->depth_offset; 444 dev_priv->depth_offset = init->depth_offset;
448 dev_priv->depth_pitch = init->depth_pitch; 445 dev_priv->depth_pitch = init->depth_pitch;
449 dev_priv->span_offset = init->span_offset; 446 dev_priv->span_offset = init->span_offset;
450 447
451 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch/8) << 21) | 448 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) |
452 (dev_priv->front_offset >> 5)); 449 (dev_priv->front_offset >> 5));
453 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch/8) << 21) | 450 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) |
454 (dev_priv->back_offset >> 5)); 451 (dev_priv->back_offset >> 5));
455 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) | 452 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
456 (dev_priv->depth_offset >> 5) | 453 (dev_priv->depth_offset >> 5) |
457 R128_DST_TILE); 454 R128_DST_TILE);
458 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) | 455 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
459 (dev_priv->span_offset >> 5)); 456 (dev_priv->span_offset >> 5));
460 457
461 DRM_GETSAREA(); 458 DRM_GETSAREA();
462 459
463 if(!dev_priv->sarea) { 460 if (!dev_priv->sarea) {
464 DRM_ERROR("could not find sarea!\n"); 461 DRM_ERROR("could not find sarea!\n");
465 dev->dev_private = (void *)dev_priv; 462 dev->dev_private = (void *)dev_priv;
466 r128_do_cleanup_cce( dev ); 463 r128_do_cleanup_cce(dev);
467 return DRM_ERR(EINVAL); 464 return DRM_ERR(EINVAL);
468 } 465 }
469 466
470 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); 467 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
471 if(!dev_priv->mmio) { 468 if (!dev_priv->mmio) {
472 DRM_ERROR("could not find mmio region!\n"); 469 DRM_ERROR("could not find mmio region!\n");
473 dev->dev_private = (void *)dev_priv; 470 dev->dev_private = (void *)dev_priv;
474 r128_do_cleanup_cce( dev ); 471 r128_do_cleanup_cce(dev);
475 return DRM_ERR(EINVAL); 472 return DRM_ERR(EINVAL);
476 } 473 }
477 dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset); 474 dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset);
478 if(!dev_priv->cce_ring) { 475 if (!dev_priv->cce_ring) {
479 DRM_ERROR("could not find cce ring region!\n"); 476 DRM_ERROR("could not find cce ring region!\n");
480 dev->dev_private = (void *)dev_priv; 477 dev->dev_private = (void *)dev_priv;
481 r128_do_cleanup_cce( dev ); 478 r128_do_cleanup_cce(dev);
482 return DRM_ERR(EINVAL); 479 return DRM_ERR(EINVAL);
483 } 480 }
484 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 481 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
485 if(!dev_priv->ring_rptr) { 482 if (!dev_priv->ring_rptr) {
486 DRM_ERROR("could not find ring read pointer!\n"); 483 DRM_ERROR("could not find ring read pointer!\n");
487 dev->dev_private = (void *)dev_priv; 484 dev->dev_private = (void *)dev_priv;
488 r128_do_cleanup_cce( dev ); 485 r128_do_cleanup_cce(dev);
489 return DRM_ERR(EINVAL); 486 return DRM_ERR(EINVAL);
490 } 487 }
491 dev->agp_buffer_token = init->buffers_offset; 488 dev->agp_buffer_token = init->buffers_offset;
492 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 489 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
493 if(!dev->agp_buffer_map) { 490 if (!dev->agp_buffer_map) {
494 DRM_ERROR("could not find dma buffer region!\n"); 491 DRM_ERROR("could not find dma buffer region!\n");
495 dev->dev_private = (void *)dev_priv; 492 dev->dev_private = (void *)dev_priv;
496 r128_do_cleanup_cce( dev ); 493 r128_do_cleanup_cce(dev);
497 return DRM_ERR(EINVAL); 494 return DRM_ERR(EINVAL);
498 } 495 }
499 496
500 if ( !dev_priv->is_pci ) { 497 if (!dev_priv->is_pci) {
501 dev_priv->agp_textures = drm_core_findmap(dev, init->agp_textures_offset); 498 dev_priv->agp_textures =
502 if(!dev_priv->agp_textures) { 499 drm_core_findmap(dev, init->agp_textures_offset);
500 if (!dev_priv->agp_textures) {
503 DRM_ERROR("could not find agp texture region!\n"); 501 DRM_ERROR("could not find agp texture region!\n");
504 dev->dev_private = (void *)dev_priv; 502 dev->dev_private = (void *)dev_priv;
505 r128_do_cleanup_cce( dev ); 503 r128_do_cleanup_cce(dev);
506 return DRM_ERR(EINVAL); 504 return DRM_ERR(EINVAL);
507 } 505 }
508 } 506 }
509 507
510 dev_priv->sarea_priv = 508 dev_priv->sarea_priv =
511 (drm_r128_sarea_t *)((u8 *)dev_priv->sarea->handle + 509 (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle +
512 init->sarea_priv_offset); 510 init->sarea_priv_offset);
513 511
514#if __OS_HAS_AGP 512#if __OS_HAS_AGP
515 if ( !dev_priv->is_pci ) { 513 if (!dev_priv->is_pci) {
516 drm_core_ioremap( dev_priv->cce_ring, dev ); 514 drm_core_ioremap(dev_priv->cce_ring, dev);
517 drm_core_ioremap( dev_priv->ring_rptr, dev ); 515 drm_core_ioremap(dev_priv->ring_rptr, dev);
518 drm_core_ioremap( dev->agp_buffer_map, dev ); 516 drm_core_ioremap(dev->agp_buffer_map, dev);
519 if(!dev_priv->cce_ring->handle || 517 if (!dev_priv->cce_ring->handle ||
520 !dev_priv->ring_rptr->handle || 518 !dev_priv->ring_rptr->handle ||
521 !dev->agp_buffer_map->handle) { 519 !dev->agp_buffer_map->handle) {
522 DRM_ERROR("Could not ioremap agp regions!\n"); 520 DRM_ERROR("Could not ioremap agp regions!\n");
523 dev->dev_private = (void *)dev_priv; 521 dev->dev_private = (void *)dev_priv;
524 r128_do_cleanup_cce( dev ); 522 r128_do_cleanup_cce(dev);
525 return DRM_ERR(ENOMEM); 523 return DRM_ERR(ENOMEM);
526 } 524 }
527 } else 525 } else
528#endif 526#endif
529 { 527 {
530 dev_priv->cce_ring->handle = 528 dev_priv->cce_ring->handle = (void *)dev_priv->cce_ring->offset;
531 (void *)dev_priv->cce_ring->offset;
532 dev_priv->ring_rptr->handle = 529 dev_priv->ring_rptr->handle =
533 (void *)dev_priv->ring_rptr->offset; 530 (void *)dev_priv->ring_rptr->offset;
534 dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset; 531 dev->agp_buffer_map->handle =
532 (void *)dev->agp_buffer_map->offset;
535 } 533 }
536 534
537#if __OS_HAS_AGP 535#if __OS_HAS_AGP
538 if ( !dev_priv->is_pci ) 536 if (!dev_priv->is_pci)
539 dev_priv->cce_buffers_offset = dev->agp->base; 537 dev_priv->cce_buffers_offset = dev->agp->base;
540 else 538 else
541#endif 539#endif
542 dev_priv->cce_buffers_offset = (unsigned long)dev->sg->virtual; 540 dev_priv->cce_buffers_offset = (unsigned long)dev->sg->virtual;
543 541
544 dev_priv->ring.start = (u32 *)dev_priv->cce_ring->handle; 542 dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle;
545 dev_priv->ring.end = ((u32 *)dev_priv->cce_ring->handle 543 dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle
546 + init->ring_size / sizeof(u32)); 544 + init->ring_size / sizeof(u32));
547 dev_priv->ring.size = init->ring_size; 545 dev_priv->ring.size = init->ring_size;
548 dev_priv->ring.size_l2qw = drm_order( init->ring_size / 8 ); 546 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
549 547
550 dev_priv->ring.tail_mask = 548 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
551 (dev_priv->ring.size / sizeof(u32)) - 1;
552 549
553 dev_priv->ring.high_mark = 128; 550 dev_priv->ring.high_mark = 128;
554 551
555 dev_priv->sarea_priv->last_frame = 0; 552 dev_priv->sarea_priv->last_frame = 0;
556 R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame ); 553 R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
557 554
558 dev_priv->sarea_priv->last_dispatch = 0; 555 dev_priv->sarea_priv->last_dispatch = 0;
559 R128_WRITE( R128_LAST_DISPATCH_REG, 556 R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch);
560 dev_priv->sarea_priv->last_dispatch );
561 557
562#if __OS_HAS_AGP 558#if __OS_HAS_AGP
563 if ( dev_priv->is_pci ) { 559 if (dev_priv->is_pci) {
564#endif 560#endif
565 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN; 561 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN;
566 dev_priv->gart_info.addr = dev_priv->gart_info.bus_addr = 0; 562 dev_priv->gart_info.addr = dev_priv->gart_info.bus_addr = 0;
567 dev_priv->gart_info.is_pcie = 0; 563 dev_priv->gart_info.is_pcie = 0;
568 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) { 564 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
569 DRM_ERROR( "failed to init PCI GART!\n" ); 565 DRM_ERROR("failed to init PCI GART!\n");
570 dev->dev_private = (void *)dev_priv; 566 dev->dev_private = (void *)dev_priv;
571 r128_do_cleanup_cce( dev ); 567 r128_do_cleanup_cce(dev);
572 return DRM_ERR(ENOMEM); 568 return DRM_ERR(ENOMEM);
573 } 569 }
574 R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr); 570 R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr);
@@ -576,88 +572,92 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
576 } 572 }
577#endif 573#endif
578 574
579 r128_cce_init_ring_buffer( dev, dev_priv ); 575 r128_cce_init_ring_buffer(dev, dev_priv);
580 r128_cce_load_microcode( dev_priv ); 576 r128_cce_load_microcode(dev_priv);
581 577
582 dev->dev_private = (void *)dev_priv; 578 dev->dev_private = (void *)dev_priv;
583 579
584 r128_do_engine_reset( dev ); 580 r128_do_engine_reset(dev);
585 581
586 return 0; 582 return 0;
587} 583}
588 584
589int r128_do_cleanup_cce( drm_device_t *dev ) 585int r128_do_cleanup_cce(drm_device_t * dev)
590{ 586{
591 587
592 /* Make sure interrupts are disabled here because the uninstall ioctl 588 /* Make sure interrupts are disabled here because the uninstall ioctl
593 * may not have been called from userspace and after dev_private 589 * may not have been called from userspace and after dev_private
594 * is freed, it's too late. 590 * is freed, it's too late.
595 */ 591 */
596 if ( dev->irq_enabled ) drm_irq_uninstall(dev); 592 if (dev->irq_enabled)
593 drm_irq_uninstall(dev);
597 594
598 if ( dev->dev_private ) { 595 if (dev->dev_private) {
599 drm_r128_private_t *dev_priv = dev->dev_private; 596 drm_r128_private_t *dev_priv = dev->dev_private;
600 597
601#if __OS_HAS_AGP 598#if __OS_HAS_AGP
602 if ( !dev_priv->is_pci ) { 599 if (!dev_priv->is_pci) {
603 if ( dev_priv->cce_ring != NULL ) 600 if (dev_priv->cce_ring != NULL)
604 drm_core_ioremapfree( dev_priv->cce_ring, dev ); 601 drm_core_ioremapfree(dev_priv->cce_ring, dev);
605 if ( dev_priv->ring_rptr != NULL ) 602 if (dev_priv->ring_rptr != NULL)
606 drm_core_ioremapfree( dev_priv->ring_rptr, dev ); 603 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
607 if ( dev->agp_buffer_map != NULL ) 604 if (dev->agp_buffer_map != NULL)
608 drm_core_ioremapfree( dev->agp_buffer_map, dev ); 605 drm_core_ioremapfree(dev->agp_buffer_map, dev);
609 } else 606 } else
610#endif 607#endif
611 { 608 {
612 if (dev_priv->gart_info.bus_addr) 609 if (dev_priv->gart_info.bus_addr)
613 if (!drm_ati_pcigart_cleanup( dev, 610 if (!drm_ati_pcigart_cleanup(dev,
614 &dev_priv->gart_info)) 611 &dev_priv->
615 DRM_ERROR( "failed to cleanup PCI GART!\n" ); 612 gart_info))
613 DRM_ERROR
614 ("failed to cleanup PCI GART!\n");
616 } 615 }
617 616
618 drm_free( dev->dev_private, sizeof(drm_r128_private_t), 617 drm_free(dev->dev_private, sizeof(drm_r128_private_t),
619 DRM_MEM_DRIVER ); 618 DRM_MEM_DRIVER);
620 dev->dev_private = NULL; 619 dev->dev_private = NULL;
621 } 620 }
622 621
623 return 0; 622 return 0;
624} 623}
625 624
626int r128_cce_init( DRM_IOCTL_ARGS ) 625int r128_cce_init(DRM_IOCTL_ARGS)
627{ 626{
628 DRM_DEVICE; 627 DRM_DEVICE;
629 drm_r128_init_t init; 628 drm_r128_init_t init;
630 629
631 DRM_DEBUG( "\n" ); 630 DRM_DEBUG("\n");
632 631
633 LOCK_TEST_WITH_RETURN( dev, filp ); 632 LOCK_TEST_WITH_RETURN(dev, filp);
634 633
635 DRM_COPY_FROM_USER_IOCTL( init, (drm_r128_init_t __user *)data, sizeof(init) ); 634 DRM_COPY_FROM_USER_IOCTL(init, (drm_r128_init_t __user *) data,
635 sizeof(init));
636 636
637 switch ( init.func ) { 637 switch (init.func) {
638 case R128_INIT_CCE: 638 case R128_INIT_CCE:
639 return r128_do_init_cce( dev, &init ); 639 return r128_do_init_cce(dev, &init);
640 case R128_CLEANUP_CCE: 640 case R128_CLEANUP_CCE:
641 return r128_do_cleanup_cce( dev ); 641 return r128_do_cleanup_cce(dev);
642 } 642 }
643 643
644 return DRM_ERR(EINVAL); 644 return DRM_ERR(EINVAL);
645} 645}
646 646
647int r128_cce_start( DRM_IOCTL_ARGS ) 647int r128_cce_start(DRM_IOCTL_ARGS)
648{ 648{
649 DRM_DEVICE; 649 DRM_DEVICE;
650 drm_r128_private_t *dev_priv = dev->dev_private; 650 drm_r128_private_t *dev_priv = dev->dev_private;
651 DRM_DEBUG( "\n" ); 651 DRM_DEBUG("\n");
652 652
653 LOCK_TEST_WITH_RETURN( dev, filp ); 653 LOCK_TEST_WITH_RETURN(dev, filp);
654 654
655 if ( dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4 ) { 655 if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {
656 DRM_DEBUG( "%s while CCE running\n", __FUNCTION__ ); 656 DRM_DEBUG("%s while CCE running\n", __FUNCTION__);
657 return 0; 657 return 0;
658 } 658 }
659 659
660 r128_do_cce_start( dev_priv ); 660 r128_do_cce_start(dev_priv);
661 661
662 return 0; 662 return 0;
663} 663}
@@ -665,61 +665,63 @@ int r128_cce_start( DRM_IOCTL_ARGS )
665/* Stop the CCE. The engine must have been idled before calling this 665/* Stop the CCE. The engine must have been idled before calling this
666 * routine. 666 * routine.
667 */ 667 */
668int r128_cce_stop( DRM_IOCTL_ARGS ) 668int r128_cce_stop(DRM_IOCTL_ARGS)
669{ 669{
670 DRM_DEVICE; 670 DRM_DEVICE;
671 drm_r128_private_t *dev_priv = dev->dev_private; 671 drm_r128_private_t *dev_priv = dev->dev_private;
672 drm_r128_cce_stop_t stop; 672 drm_r128_cce_stop_t stop;
673 int ret; 673 int ret;
674 DRM_DEBUG( "\n" ); 674 DRM_DEBUG("\n");
675 675
676 LOCK_TEST_WITH_RETURN( dev, filp ); 676 LOCK_TEST_WITH_RETURN(dev, filp);
677 677
678 DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t __user *)data, sizeof(stop) ); 678 DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t __user *) data,
679 sizeof(stop));
679 680
680 /* Flush any pending CCE commands. This ensures any outstanding 681 /* Flush any pending CCE commands. This ensures any outstanding
681 * commands are exectuted by the engine before we turn it off. 682 * commands are exectuted by the engine before we turn it off.
682 */ 683 */
683 if ( stop.flush ) { 684 if (stop.flush) {
684 r128_do_cce_flush( dev_priv ); 685 r128_do_cce_flush(dev_priv);
685 } 686 }
686 687
687 /* If we fail to make the engine go idle, we return an error 688 /* If we fail to make the engine go idle, we return an error
688 * code so that the DRM ioctl wrapper can try again. 689 * code so that the DRM ioctl wrapper can try again.
689 */ 690 */
690 if ( stop.idle ) { 691 if (stop.idle) {
691 ret = r128_do_cce_idle( dev_priv ); 692 ret = r128_do_cce_idle(dev_priv);
692 if ( ret ) return ret; 693 if (ret)
694 return ret;
693 } 695 }
694 696
695 /* Finally, we can turn off the CCE. If the engine isn't idle, 697 /* Finally, we can turn off the CCE. If the engine isn't idle,
696 * we will get some dropped triangles as they won't be fully 698 * we will get some dropped triangles as they won't be fully
697 * rendered before the CCE is shut down. 699 * rendered before the CCE is shut down.
698 */ 700 */
699 r128_do_cce_stop( dev_priv ); 701 r128_do_cce_stop(dev_priv);
700 702
701 /* Reset the engine */ 703 /* Reset the engine */
702 r128_do_engine_reset( dev ); 704 r128_do_engine_reset(dev);
703 705
704 return 0; 706 return 0;
705} 707}
706 708
707/* Just reset the CCE ring. Called as part of an X Server engine reset. 709/* Just reset the CCE ring. Called as part of an X Server engine reset.
708 */ 710 */
709int r128_cce_reset( DRM_IOCTL_ARGS ) 711int r128_cce_reset(DRM_IOCTL_ARGS)
710{ 712{
711 DRM_DEVICE; 713 DRM_DEVICE;
712 drm_r128_private_t *dev_priv = dev->dev_private; 714 drm_r128_private_t *dev_priv = dev->dev_private;
713 DRM_DEBUG( "\n" ); 715 DRM_DEBUG("\n");
714 716
715 LOCK_TEST_WITH_RETURN( dev, filp ); 717 LOCK_TEST_WITH_RETURN(dev, filp);
716 718
717 if ( !dev_priv ) { 719 if (!dev_priv) {
718 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ ); 720 DRM_DEBUG("%s called before init done\n", __FUNCTION__);
719 return DRM_ERR(EINVAL); 721 return DRM_ERR(EINVAL);
720 } 722 }
721 723
722 r128_do_cce_reset( dev_priv ); 724 r128_do_cce_reset(dev_priv);
723 725
724 /* The CCE is no longer running after an engine reset */ 726 /* The CCE is no longer running after an engine reset */
725 dev_priv->cce_running = 0; 727 dev_priv->cce_running = 0;
@@ -727,37 +729,36 @@ int r128_cce_reset( DRM_IOCTL_ARGS )
727 return 0; 729 return 0;
728} 730}
729 731
730int r128_cce_idle( DRM_IOCTL_ARGS ) 732int r128_cce_idle(DRM_IOCTL_ARGS)
731{ 733{
732 DRM_DEVICE; 734 DRM_DEVICE;
733 drm_r128_private_t *dev_priv = dev->dev_private; 735 drm_r128_private_t *dev_priv = dev->dev_private;
734 DRM_DEBUG( "\n" ); 736 DRM_DEBUG("\n");
735 737
736 LOCK_TEST_WITH_RETURN( dev, filp ); 738 LOCK_TEST_WITH_RETURN(dev, filp);
737 739
738 if ( dev_priv->cce_running ) { 740 if (dev_priv->cce_running) {
739 r128_do_cce_flush( dev_priv ); 741 r128_do_cce_flush(dev_priv);
740 } 742 }
741 743
742 return r128_do_cce_idle( dev_priv ); 744 return r128_do_cce_idle(dev_priv);
743} 745}
744 746
745int r128_engine_reset( DRM_IOCTL_ARGS ) 747int r128_engine_reset(DRM_IOCTL_ARGS)
746{ 748{
747 DRM_DEVICE; 749 DRM_DEVICE;
748 DRM_DEBUG( "\n" ); 750 DRM_DEBUG("\n");
749 751
750 LOCK_TEST_WITH_RETURN( dev, filp ); 752 LOCK_TEST_WITH_RETURN(dev, filp);
751 753
752 return r128_do_engine_reset( dev ); 754 return r128_do_engine_reset(dev);
753} 755}
754 756
755int r128_fullscreen( DRM_IOCTL_ARGS ) 757int r128_fullscreen(DRM_IOCTL_ARGS)
756{ 758{
757 return DRM_ERR(EINVAL); 759 return DRM_ERR(EINVAL);
758} 760}
759 761
760
761/* ================================================================ 762/* ================================================================
762 * Freelist management 763 * Freelist management
763 */ 764 */
@@ -765,7 +766,7 @@ int r128_fullscreen( DRM_IOCTL_ARGS )
765#define R128_BUFFER_FREE 0 766#define R128_BUFFER_FREE 0
766 767
767#if 0 768#if 0
768static int r128_freelist_init( drm_device_t *dev ) 769static int r128_freelist_init(drm_device_t * dev)
769{ 770{
770 drm_device_dma_t *dma = dev->dma; 771 drm_device_dma_t *dma = dev->dma;
771 drm_r128_private_t *dev_priv = dev->dev_private; 772 drm_r128_private_t *dev_priv = dev->dev_private;
@@ -774,27 +775,26 @@ static int r128_freelist_init( drm_device_t *dev )
774 drm_r128_freelist_t *entry; 775 drm_r128_freelist_t *entry;
775 int i; 776 int i;
776 777
777 dev_priv->head = drm_alloc( sizeof(drm_r128_freelist_t), 778 dev_priv->head = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);
778 DRM_MEM_DRIVER ); 779 if (dev_priv->head == NULL)
779 if ( dev_priv->head == NULL )
780 return DRM_ERR(ENOMEM); 780 return DRM_ERR(ENOMEM);
781 781
782 memset( dev_priv->head, 0, sizeof(drm_r128_freelist_t) ); 782 memset(dev_priv->head, 0, sizeof(drm_r128_freelist_t));
783 dev_priv->head->age = R128_BUFFER_USED; 783 dev_priv->head->age = R128_BUFFER_USED;
784 784
785 for ( i = 0 ; i < dma->buf_count ; i++ ) { 785 for (i = 0; i < dma->buf_count; i++) {
786 buf = dma->buflist[i]; 786 buf = dma->buflist[i];
787 buf_priv = buf->dev_private; 787 buf_priv = buf->dev_private;
788 788
789 entry = drm_alloc( sizeof(drm_r128_freelist_t), 789 entry = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER);
790 DRM_MEM_DRIVER ); 790 if (!entry)
791 if ( !entry ) return DRM_ERR(ENOMEM); 791 return DRM_ERR(ENOMEM);
792 792
793 entry->age = R128_BUFFER_FREE; 793 entry->age = R128_BUFFER_FREE;
794 entry->buf = buf; 794 entry->buf = buf;
795 entry->prev = dev_priv->head; 795 entry->prev = dev_priv->head;
796 entry->next = dev_priv->head->next; 796 entry->next = dev_priv->head->next;
797 if ( !entry->next ) 797 if (!entry->next)
798 dev_priv->tail = entry; 798 dev_priv->tail = entry;
799 799
800 buf_priv->discard = 0; 800 buf_priv->discard = 0;
@@ -803,7 +803,7 @@ static int r128_freelist_init( drm_device_t *dev )
803 803
804 dev_priv->head->next = entry; 804 dev_priv->head->next = entry;
805 805
806 if ( dev_priv->head->next ) 806 if (dev_priv->head->next)
807 dev_priv->head->next->prev = entry; 807 dev_priv->head->next->prev = entry;
808 } 808 }
809 809
@@ -812,7 +812,7 @@ static int r128_freelist_init( drm_device_t *dev )
812} 812}
813#endif 813#endif
814 814
815static drm_buf_t *r128_freelist_get( drm_device_t *dev ) 815static drm_buf_t *r128_freelist_get(drm_device_t * dev)
816{ 816{
817 drm_device_dma_t *dma = dev->dma; 817 drm_device_dma_t *dma = dev->dma;
818 drm_r128_private_t *dev_priv = dev->dev_private; 818 drm_r128_private_t *dev_priv = dev->dev_private;
@@ -822,20 +822,20 @@ static drm_buf_t *r128_freelist_get( drm_device_t *dev )
822 822
823 /* FIXME: Optimize -- use freelist code */ 823 /* FIXME: Optimize -- use freelist code */
824 824
825 for ( i = 0 ; i < dma->buf_count ; i++ ) { 825 for (i = 0; i < dma->buf_count; i++) {
826 buf = dma->buflist[i]; 826 buf = dma->buflist[i];
827 buf_priv = buf->dev_private; 827 buf_priv = buf->dev_private;
828 if ( buf->filp == 0 ) 828 if (buf->filp == 0)
829 return buf; 829 return buf;
830 } 830 }
831 831
832 for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) { 832 for (t = 0; t < dev_priv->usec_timeout; t++) {
833 u32 done_age = R128_READ( R128_LAST_DISPATCH_REG ); 833 u32 done_age = R128_READ(R128_LAST_DISPATCH_REG);
834 834
835 for ( i = 0 ; i < dma->buf_count ; i++ ) { 835 for (i = 0; i < dma->buf_count; i++) {
836 buf = dma->buflist[i]; 836 buf = dma->buflist[i];
837 buf_priv = buf->dev_private; 837 buf_priv = buf->dev_private;
838 if ( buf->pending && buf_priv->age <= done_age ) { 838 if (buf->pending && buf_priv->age <= done_age) {
839 /* The buffer has been processed, so it 839 /* The buffer has been processed, so it
840 * can now be used. 840 * can now be used.
841 */ 841 */
@@ -843,63 +843,63 @@ static drm_buf_t *r128_freelist_get( drm_device_t *dev )
843 return buf; 843 return buf;
844 } 844 }
845 } 845 }
846 DRM_UDELAY( 1 ); 846 DRM_UDELAY(1);
847 } 847 }
848 848
849 DRM_DEBUG( "returning NULL!\n" ); 849 DRM_DEBUG("returning NULL!\n");
850 return NULL; 850 return NULL;
851} 851}
852 852
853void r128_freelist_reset( drm_device_t *dev ) 853void r128_freelist_reset(drm_device_t * dev)
854{ 854{
855 drm_device_dma_t *dma = dev->dma; 855 drm_device_dma_t *dma = dev->dma;
856 int i; 856 int i;
857 857
858 for ( i = 0 ; i < dma->buf_count ; i++ ) { 858 for (i = 0; i < dma->buf_count; i++) {
859 drm_buf_t *buf = dma->buflist[i]; 859 drm_buf_t *buf = dma->buflist[i];
860 drm_r128_buf_priv_t *buf_priv = buf->dev_private; 860 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
861 buf_priv->age = 0; 861 buf_priv->age = 0;
862 } 862 }
863} 863}
864 864
865
866/* ================================================================ 865/* ================================================================
867 * CCE command submission 866 * CCE command submission
868 */ 867 */
869 868
870int r128_wait_ring( drm_r128_private_t *dev_priv, int n ) 869int r128_wait_ring(drm_r128_private_t * dev_priv, int n)
871{ 870{
872 drm_r128_ring_buffer_t *ring = &dev_priv->ring; 871 drm_r128_ring_buffer_t *ring = &dev_priv->ring;
873 int i; 872 int i;
874 873
875 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 874 for (i = 0; i < dev_priv->usec_timeout; i++) {
876 r128_update_ring_snapshot( dev_priv ); 875 r128_update_ring_snapshot(dev_priv);
877 if ( ring->space >= n ) 876 if (ring->space >= n)
878 return 0; 877 return 0;
879 DRM_UDELAY( 1 ); 878 DRM_UDELAY(1);
880 } 879 }
881 880
882 /* FIXME: This is being ignored... */ 881 /* FIXME: This is being ignored... */
883 DRM_ERROR( "failed!\n" ); 882 DRM_ERROR("failed!\n");
884 return DRM_ERR(EBUSY); 883 return DRM_ERR(EBUSY);
885} 884}
886 885
887static int r128_cce_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d ) 886static int r128_cce_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d)
888{ 887{
889 int i; 888 int i;
890 drm_buf_t *buf; 889 drm_buf_t *buf;
891 890
892 for ( i = d->granted_count ; i < d->request_count ; i++ ) { 891 for (i = d->granted_count; i < d->request_count; i++) {
893 buf = r128_freelist_get( dev ); 892 buf = r128_freelist_get(dev);
894 if ( !buf ) return DRM_ERR(EAGAIN); 893 if (!buf)
894 return DRM_ERR(EAGAIN);
895 895
896 buf->filp = filp; 896 buf->filp = filp;
897 897
898 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx, 898 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
899 sizeof(buf->idx) ) ) 899 sizeof(buf->idx)))
900 return DRM_ERR(EFAULT); 900 return DRM_ERR(EFAULT);
901 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total, 901 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
902 sizeof(buf->total) ) ) 902 sizeof(buf->total)))
903 return DRM_ERR(EFAULT); 903 return DRM_ERR(EFAULT);
904 904
905 d->granted_count++; 905 d->granted_count++;
@@ -907,7 +907,7 @@ static int r128_cce_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d )
907 return 0; 907 return 0;
908} 908}
909 909
910int r128_cce_buffers( DRM_IOCTL_ARGS ) 910int r128_cce_buffers(DRM_IOCTL_ARGS)
911{ 911{
912 DRM_DEVICE; 912 DRM_DEVICE;
913 drm_device_dma_t *dma = dev->dma; 913 drm_device_dma_t *dma = dev->dma;
@@ -915,33 +915,33 @@ int r128_cce_buffers( DRM_IOCTL_ARGS )
915 drm_dma_t __user *argp = (void __user *)data; 915 drm_dma_t __user *argp = (void __user *)data;
916 drm_dma_t d; 916 drm_dma_t d;
917 917
918 LOCK_TEST_WITH_RETURN( dev, filp ); 918 LOCK_TEST_WITH_RETURN(dev, filp);
919 919
920 DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) ); 920 DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
921 921
922 /* Please don't send us buffers. 922 /* Please don't send us buffers.
923 */ 923 */
924 if ( d.send_count != 0 ) { 924 if (d.send_count != 0) {
925 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", 925 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
926 DRM_CURRENTPID, d.send_count ); 926 DRM_CURRENTPID, d.send_count);
927 return DRM_ERR(EINVAL); 927 return DRM_ERR(EINVAL);
928 } 928 }
929 929
930 /* We'll send you buffers. 930 /* We'll send you buffers.
931 */ 931 */
932 if ( d.request_count < 0 || d.request_count > dma->buf_count ) { 932 if (d.request_count < 0 || d.request_count > dma->buf_count) {
933 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", 933 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
934 DRM_CURRENTPID, d.request_count, dma->buf_count ); 934 DRM_CURRENTPID, d.request_count, dma->buf_count);
935 return DRM_ERR(EINVAL); 935 return DRM_ERR(EINVAL);
936 } 936 }
937 937
938 d.granted_count = 0; 938 d.granted_count = 0;
939 939
940 if ( d.request_count ) { 940 if (d.request_count) {
941 ret = r128_cce_get_buffers( filp, dev, &d ); 941 ret = r128_cce_get_buffers(filp, dev, &d);
942 } 942 }
943 943
944 DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d) ); 944 DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
945 945
946 return ret; 946 return ret;
947} 947}
diff --git a/drivers/char/drm/r128_drm.h b/drivers/char/drm/r128_drm.h
index b616cd3ed2cd..5ddc03202411 100644
--- a/drivers/char/drm/r128_drm.h
+++ b/drivers/char/drm/r128_drm.h
@@ -93,7 +93,7 @@
93#define R128_MAX_TEXTURE_LEVELS 11 93#define R128_MAX_TEXTURE_LEVELS 11
94#define R128_MAX_TEXTURE_UNITS 2 94#define R128_MAX_TEXTURE_UNITS 2
95 95
96#endif /* __R128_SAREA_DEFINES__ */ 96#endif /* __R128_SAREA_DEFINES__ */
97 97
98typedef struct { 98typedef struct {
99 /* Context state - can be written in one large chunk */ 99 /* Context state - can be written in one large chunk */
@@ -140,7 +140,6 @@ typedef struct {
140 unsigned int tex_border_color; 140 unsigned int tex_border_color;
141} drm_r128_texture_regs_t; 141} drm_r128_texture_regs_t;
142 142
143
144typedef struct drm_r128_sarea { 143typedef struct drm_r128_sarea {
145 /* The channel for communication of state information to the kernel 144 /* The channel for communication of state information to the kernel
146 * on firing a vertex buffer. 145 * on firing a vertex buffer.
@@ -161,14 +160,13 @@ typedef struct drm_r128_sarea {
161 unsigned int last_frame; 160 unsigned int last_frame;
162 unsigned int last_dispatch; 161 unsigned int last_dispatch;
163 162
164 drm_tex_region_t tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS+1]; 163 drm_tex_region_t tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1];
165 unsigned int tex_age[R128_NR_TEX_HEAPS]; 164 unsigned int tex_age[R128_NR_TEX_HEAPS];
166 int ctx_owner; 165 int ctx_owner;
167 int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */ 166 int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */
168 int pfCurrentPage; /* which buffer is being displayed? */ 167 int pfCurrentPage; /* which buffer is being displayed? */
169} drm_r128_sarea_t; 168} drm_r128_sarea_t;
170 169
171
172/* WARNING: If you change any of these defines, make sure to change the 170/* WARNING: If you change any of these defines, make sure to change the
173 * defines in the Xserver file (xf86drmR128.h) 171 * defines in the Xserver file (xf86drmR128.h)
174 */ 172 */
@@ -220,7 +218,7 @@ typedef struct drm_r128_sarea {
220 218
221typedef struct drm_r128_init { 219typedef struct drm_r128_init {
222 enum { 220 enum {
223 R128_INIT_CCE = 0x01, 221 R128_INIT_CCE = 0x01,
224 R128_CLEANUP_CCE = 0x02 222 R128_CLEANUP_CCE = 0x02
225 } func; 223 } func;
226#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) 224#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
@@ -278,9 +276,9 @@ typedef struct drm_r128_clear {
278 276
279typedef struct drm_r128_vertex { 277typedef struct drm_r128_vertex {
280 int prim; 278 int prim;
281 int idx; /* Index of vertex buffer */ 279 int idx; /* Index of vertex buffer */
282 int count; /* Number of vertices in buffer */ 280 int count; /* Number of vertices in buffer */
283 int discard; /* Client finished with buffer? */ 281 int discard; /* Client finished with buffer? */
284} drm_r128_vertex_t; 282} drm_r128_vertex_t;
285 283
286typedef struct drm_r128_indices { 284typedef struct drm_r128_indices {
@@ -288,7 +286,7 @@ typedef struct drm_r128_indices {
288 int idx; 286 int idx;
289 int start; 287 int start;
290 int end; 288 int end;
291 int discard; /* Client finished with buffer? */ 289 int discard; /* Client finished with buffer? */
292} drm_r128_indices_t; 290} drm_r128_indices_t;
293 291
294typedef struct drm_r128_blit { 292typedef struct drm_r128_blit {
@@ -302,10 +300,10 @@ typedef struct drm_r128_blit {
302 300
303typedef struct drm_r128_depth { 301typedef struct drm_r128_depth {
304 enum { 302 enum {
305 R128_WRITE_SPAN = 0x01, 303 R128_WRITE_SPAN = 0x01,
306 R128_WRITE_PIXELS = 0x02, 304 R128_WRITE_PIXELS = 0x02,
307 R128_READ_SPAN = 0x03, 305 R128_READ_SPAN = 0x03,
308 R128_READ_PIXELS = 0x04 306 R128_READ_PIXELS = 0x04
309 } func; 307 } func;
310 int n; 308 int n;
311 int __user *x; 309 int __user *x;
@@ -327,13 +325,13 @@ typedef struct drm_r128_indirect {
327 325
328typedef struct drm_r128_fullscreen { 326typedef struct drm_r128_fullscreen {
329 enum { 327 enum {
330 R128_INIT_FULLSCREEN = 0x01, 328 R128_INIT_FULLSCREEN = 0x01,
331 R128_CLEANUP_FULLSCREEN = 0x02 329 R128_CLEANUP_FULLSCREEN = 0x02
332 } func; 330 } func;
333} drm_r128_fullscreen_t; 331} drm_r128_fullscreen_t;
334 332
335/* 2.3: An ioctl to get parameters that aren't available to the 3d 333/* 2.3: An ioctl to get parameters that aren't available to the 3d
336 * client any other way. 334 * client any other way.
337 */ 335 */
338#define R128_PARAM_IRQ_NR 1 336#define R128_PARAM_IRQ_NR 1
339 337
diff --git a/drivers/char/drm/r128_drv.c b/drivers/char/drm/r128_drv.c
index bc446da1b210..4d9224645f04 100644
--- a/drivers/char/drm/r128_drv.c
+++ b/drivers/char/drm/r128_drv.c
@@ -37,30 +37,28 @@
37 37
38#include "drm_pciids.h" 38#include "drm_pciids.h"
39 39
40static int postinit( struct drm_device *dev, unsigned long flags ) 40static int postinit(struct drm_device *dev, unsigned long flags)
41{ 41{
42 DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", 42 DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n",
43 DRIVER_NAME, 43 DRIVER_NAME,
44 DRIVER_MAJOR, 44 DRIVER_MAJOR,
45 DRIVER_MINOR, 45 DRIVER_MINOR,
46 DRIVER_PATCHLEVEL, 46 DRIVER_PATCHLEVEL,
47 DRIVER_DATE, 47 DRIVER_DATE, dev->primary.minor, pci_pretty_name(dev->pdev)
48 dev->primary.minor, 48 );
49 pci_pretty_name(dev->pdev)
50 );
51 return 0; 49 return 0;
52} 50}
53 51
54static int version( drm_version_t *version ) 52static int version(drm_version_t * version)
55{ 53{
56 int len; 54 int len;
57 55
58 version->version_major = DRIVER_MAJOR; 56 version->version_major = DRIVER_MAJOR;
59 version->version_minor = DRIVER_MINOR; 57 version->version_minor = DRIVER_MINOR;
60 version->version_patchlevel = DRIVER_PATCHLEVEL; 58 version->version_patchlevel = DRIVER_PATCHLEVEL;
61 DRM_COPY( version->name, DRIVER_NAME ); 59 DRM_COPY(version->name, DRIVER_NAME);
62 DRM_COPY( version->date, DRIVER_DATE ); 60 DRM_COPY(version->date, DRIVER_DATE);
63 DRM_COPY( version->desc, DRIVER_DESC ); 61 DRM_COPY(version->desc, DRIVER_DESC);
64 return 0; 62 return 0;
65} 63}
66 64
@@ -72,7 +70,10 @@ extern drm_ioctl_desc_t r128_ioctls[];
72extern int r128_max_ioctl; 70extern int r128_max_ioctl;
73 71
74static struct drm_driver driver = { 72static struct drm_driver driver = {
75 .driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL, 73 .driver_features =
74 DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG |
75 DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
76 DRIVER_IRQ_VBL,
76 .dev_priv_size = sizeof(drm_r128_buf_priv_t), 77 .dev_priv_size = sizeof(drm_r128_buf_priv_t),
77 .prerelease = r128_driver_prerelease, 78 .prerelease = r128_driver_prerelease,
78 .pretakedown = r128_driver_pretakedown, 79 .pretakedown = r128_driver_pretakedown,
@@ -89,21 +90,22 @@ static struct drm_driver driver = {
89 .ioctls = r128_ioctls, 90 .ioctls = r128_ioctls,
90 .dma_ioctl = r128_cce_buffers, 91 .dma_ioctl = r128_cce_buffers,
91 .fops = { 92 .fops = {
92 .owner = THIS_MODULE, 93 .owner = THIS_MODULE,
93 .open = drm_open, 94 .open = drm_open,
94 .release = drm_release, 95 .release = drm_release,
95 .ioctl = drm_ioctl, 96 .ioctl = drm_ioctl,
96 .mmap = drm_mmap, 97 .mmap = drm_mmap,
97 .poll = drm_poll, 98 .poll = drm_poll,
98 .fasync = drm_fasync, 99 .fasync = drm_fasync,
99#ifdef CONFIG_COMPAT 100#ifdef CONFIG_COMPAT
100 .compat_ioctl = r128_compat_ioctl, 101 .compat_ioctl = r128_compat_ioctl,
101#endif 102#endif
102 }, 103 }
104 ,
103 .pci_driver = { 105 .pci_driver = {
104 .name = DRIVER_NAME, 106 .name = DRIVER_NAME,
105 .id_table = pciidlist, 107 .id_table = pciidlist,
106 } 108 }
107}; 109};
108 110
109static int __init r128_init(void) 111static int __init r128_init(void)
@@ -120,6 +122,6 @@ static void __exit r128_exit(void)
120module_init(r128_init); 122module_init(r128_init);
121module_exit(r128_exit); 123module_exit(r128_exit);
122 124
123MODULE_AUTHOR( DRIVER_AUTHOR ); 125MODULE_AUTHOR(DRIVER_AUTHOR);
124MODULE_DESCRIPTION( DRIVER_DESC ); 126MODULE_DESCRIPTION(DRIVER_DESC);
125MODULE_LICENSE("GPL and additional rights"); 127MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/char/drm/r128_drv.h b/drivers/char/drm/r128_drv.h
index 938dfaea553a..87c5e1381ba2 100644
--- a/drivers/char/drm/r128_drv.h
+++ b/drivers/char/drm/r128_drv.h
@@ -52,14 +52,13 @@
52#define DRIVER_MINOR 5 52#define DRIVER_MINOR 5
53#define DRIVER_PATCHLEVEL 0 53#define DRIVER_PATCHLEVEL 0
54 54
55
56#define GET_RING_HEAD(dev_priv) R128_READ( R128_PM4_BUFFER_DL_RPTR ) 55#define GET_RING_HEAD(dev_priv) R128_READ( R128_PM4_BUFFER_DL_RPTR )
57 56
58typedef struct drm_r128_freelist { 57typedef struct drm_r128_freelist {
59 unsigned int age; 58 unsigned int age;
60 drm_buf_t *buf; 59 drm_buf_t *buf;
61 struct drm_r128_freelist *next; 60 struct drm_r128_freelist *next;
62 struct drm_r128_freelist *prev; 61 struct drm_r128_freelist *prev;
63} drm_r128_freelist_t; 62} drm_r128_freelist_t;
64 63
65typedef struct drm_r128_ring_buffer { 64typedef struct drm_r128_ring_buffer {
@@ -83,8 +82,8 @@ typedef struct drm_r128_private {
83 int cce_fifo_size; 82 int cce_fifo_size;
84 int cce_running; 83 int cce_running;
85 84
86 drm_r128_freelist_t *head; 85 drm_r128_freelist_t *head;
87 drm_r128_freelist_t *tail; 86 drm_r128_freelist_t *tail;
88 87
89 int usec_timeout; 88 int usec_timeout;
90 int is_pci; 89 int is_pci;
@@ -126,34 +125,34 @@ typedef struct drm_r128_buf_priv {
126 int prim; 125 int prim;
127 int discard; 126 int discard;
128 int dispatched; 127 int dispatched;
129 drm_r128_freelist_t *list_entry; 128 drm_r128_freelist_t *list_entry;
130} drm_r128_buf_priv_t; 129} drm_r128_buf_priv_t;
131 130
132 /* r128_cce.c */ 131 /* r128_cce.c */
133extern int r128_cce_init( DRM_IOCTL_ARGS ); 132extern int r128_cce_init(DRM_IOCTL_ARGS);
134extern int r128_cce_start( DRM_IOCTL_ARGS ); 133extern int r128_cce_start(DRM_IOCTL_ARGS);
135extern int r128_cce_stop( DRM_IOCTL_ARGS ); 134extern int r128_cce_stop(DRM_IOCTL_ARGS);
136extern int r128_cce_reset( DRM_IOCTL_ARGS ); 135extern int r128_cce_reset(DRM_IOCTL_ARGS);
137extern int r128_cce_idle( DRM_IOCTL_ARGS ); 136extern int r128_cce_idle(DRM_IOCTL_ARGS);
138extern int r128_engine_reset( DRM_IOCTL_ARGS ); 137extern int r128_engine_reset(DRM_IOCTL_ARGS);
139extern int r128_fullscreen( DRM_IOCTL_ARGS ); 138extern int r128_fullscreen(DRM_IOCTL_ARGS);
140extern int r128_cce_buffers( DRM_IOCTL_ARGS ); 139extern int r128_cce_buffers(DRM_IOCTL_ARGS);
141 140
142extern void r128_freelist_reset( drm_device_t *dev ); 141extern void r128_freelist_reset(drm_device_t * dev);
143 142
144extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n ); 143extern int r128_wait_ring(drm_r128_private_t * dev_priv, int n);
145 144
146extern int r128_do_cce_idle( drm_r128_private_t *dev_priv ); 145extern int r128_do_cce_idle(drm_r128_private_t * dev_priv);
147extern int r128_do_cleanup_cce( drm_device_t *dev ); 146extern int r128_do_cleanup_cce(drm_device_t * dev);
148 147
149extern int r128_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence); 148extern int r128_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence);
150 149
151extern irqreturn_t r128_driver_irq_handler( DRM_IRQ_ARGS ); 150extern irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS);
152extern void r128_driver_irq_preinstall( drm_device_t *dev ); 151extern void r128_driver_irq_preinstall(drm_device_t * dev);
153extern void r128_driver_irq_postinstall( drm_device_t *dev ); 152extern void r128_driver_irq_postinstall(drm_device_t * dev);
154extern void r128_driver_irq_uninstall( drm_device_t *dev ); 153extern void r128_driver_irq_uninstall(drm_device_t * dev);
155extern void r128_driver_pretakedown(drm_device_t *dev); 154extern void r128_driver_pretakedown(drm_device_t * dev);
156extern void r128_driver_prerelease(drm_device_t *dev, DRMFILE filp); 155extern void r128_driver_prerelease(drm_device_t * dev, DRMFILE filp);
157 156
158extern long r128_compat_ioctl(struct file *filp, unsigned int cmd, 157extern long r128_compat_ioctl(struct file *filp, unsigned int cmd,
159 unsigned long arg); 158 unsigned long arg);
@@ -265,7 +264,6 @@ extern long r128_compat_ioctl(struct file *filp, unsigned int cmd,
265# define R128_EVENT_CRTC_OFFSET (1 << 0) 264# define R128_EVENT_CRTC_OFFSET (1 << 0)
266#define R128_WINDOW_XY_OFFSET 0x1bcc 265#define R128_WINDOW_XY_OFFSET 0x1bcc
267 266
268
269/* CCE registers 267/* CCE registers
270 */ 268 */
271#define R128_PM4_BUFFER_OFFSET 0x0700 269#define R128_PM4_BUFFER_OFFSET 0x0700
@@ -316,7 +314,6 @@ extern long r128_compat_ioctl(struct file *filp, unsigned int cmd,
316#define R128_PM4_FIFO_DATA_EVEN 0x1000 314#define R128_PM4_FIFO_DATA_EVEN 0x1000
317#define R128_PM4_FIFO_DATA_ODD 0x1004 315#define R128_PM4_FIFO_DATA_ODD 0x1004
318 316
319
320/* CCE command packets 317/* CCE command packets
321 */ 318 */
322#define R128_CCE_PACKET0 0x00000000 319#define R128_CCE_PACKET0 0x00000000
@@ -394,7 +391,6 @@ do { \
394 R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \ 391 R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \
395} while (0) 392} while (0)
396 393
397
398#define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \ 394#define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \
399 ((n) << 16) | ((reg) >> 2)) 395 ((n) << 16) | ((reg) >> 2))
400#define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \ 396#define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \
@@ -403,13 +399,11 @@ do { \
403#define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \ 399#define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \
404 (pkt) | ((n) << 16)) 400 (pkt) | ((n) << 16))
405 401
406 402static __inline__ void r128_update_ring_snapshot(drm_r128_private_t * dev_priv)
407static __inline__ void
408r128_update_ring_snapshot( drm_r128_private_t *dev_priv )
409{ 403{
410 drm_r128_ring_buffer_t *ring = &dev_priv->ring; 404 drm_r128_ring_buffer_t *ring = &dev_priv->ring;
411 ring->space = (GET_RING_HEAD( dev_priv ) - ring->tail) * sizeof(u32); 405 ring->space = (GET_RING_HEAD(dev_priv) - ring->tail) * sizeof(u32);
412 if ( ring->space <= 0 ) 406 if (ring->space <= 0)
413 ring->space += ring->size; 407 ring->space += ring->size;
414} 408}
415 409
@@ -450,7 +444,6 @@ do { \
450 OUT_RING( R128_EVENT_CRTC_OFFSET ); \ 444 OUT_RING( R128_EVENT_CRTC_OFFSET ); \
451} while (0) 445} while (0)
452 446
453
454/* ================================================================ 447/* ================================================================
455 * Ring control 448 * Ring control
456 */ 449 */
@@ -520,4 +513,4 @@ do { \
520 write &= tail_mask; \ 513 write &= tail_mask; \
521} while (0) 514} while (0)
522 515
523#endif /* __R128_DRV_H__ */ 516#endif /* __R128_DRV_H__ */
diff --git a/drivers/char/drm/r128_ioc32.c b/drivers/char/drm/r128_ioc32.c
index 60598ef9475a..1e2e367b8b82 100644
--- a/drivers/char/drm/r128_ioc32.c
+++ b/drivers/char/drm/r128_ioc32.c
@@ -65,10 +65,10 @@ static int compat_r128_init(struct file *file, unsigned int cmd,
65{ 65{
66 drm_r128_init32_t init32; 66 drm_r128_init32_t init32;
67 drm_r128_init_t __user *init; 67 drm_r128_init_t __user *init;
68 68
69 if (copy_from_user(&init32, (void __user *)arg, sizeof(init32))) 69 if (copy_from_user(&init32, (void __user *)arg, sizeof(init32)))
70 return -EFAULT; 70 return -EFAULT;
71 71
72 init = compat_alloc_user_space(sizeof(*init)); 72 init = compat_alloc_user_space(sizeof(*init));
73 if (!access_ok(VERIFY_WRITE, init, sizeof(*init)) 73 if (!access_ok(VERIFY_WRITE, init, sizeof(*init))
74 || __put_user(init32.func, &init->func) 74 || __put_user(init32.func, &init->func)
@@ -92,14 +92,14 @@ static int compat_r128_init(struct file *file, unsigned int cmd,
92 || __put_user(init32.ring_offset, &init->ring_offset) 92 || __put_user(init32.ring_offset, &init->ring_offset)
93 || __put_user(init32.ring_rptr_offset, &init->ring_rptr_offset) 93 || __put_user(init32.ring_rptr_offset, &init->ring_rptr_offset)
94 || __put_user(init32.buffers_offset, &init->buffers_offset) 94 || __put_user(init32.buffers_offset, &init->buffers_offset)
95 || __put_user(init32.agp_textures_offset, &init->agp_textures_offset)) 95 || __put_user(init32.agp_textures_offset,
96 &init->agp_textures_offset))
96 return -EFAULT; 97 return -EFAULT;
97 98
98 return drm_ioctl(file->f_dentry->d_inode, file, 99 return drm_ioctl(file->f_dentry->d_inode, file,
99 DRM_IOCTL_R128_INIT, (unsigned long)init); 100 DRM_IOCTL_R128_INIT, (unsigned long)init);
100} 101}
101 102
102
103typedef struct drm_r128_depth32 { 103typedef struct drm_r128_depth32 {
104 int func; 104 int func;
105 int n; 105 int n;
@@ -124,13 +124,15 @@ static int compat_r128_depth(struct file *file, unsigned int cmd,
124 || __put_user(depth32.n, &depth->n) 124 || __put_user(depth32.n, &depth->n)
125 || __put_user((int __user *)(unsigned long)depth32.x, &depth->x) 125 || __put_user((int __user *)(unsigned long)depth32.x, &depth->x)
126 || __put_user((int __user *)(unsigned long)depth32.y, &depth->y) 126 || __put_user((int __user *)(unsigned long)depth32.y, &depth->y)
127 || __put_user((unsigned int __user *)(unsigned long)depth32.buffer, &depth->buffer) 127 || __put_user((unsigned int __user *)(unsigned long)depth32.buffer,
128 || __put_user((unsigned char __user *)(unsigned long)depth32.mask, &depth->mask)) 128 &depth->buffer)
129 || __put_user((unsigned char __user *)(unsigned long)depth32.mask,
130 &depth->mask))
129 return -EFAULT; 131 return -EFAULT;
130 132
131 return drm_ioctl(file->f_dentry->d_inode, file, 133 return drm_ioctl(file->f_dentry->d_inode, file,
132 DRM_IOCTL_R128_DEPTH, (unsigned long)depth); 134 DRM_IOCTL_R128_DEPTH, (unsigned long)depth);
133 135
134} 136}
135 137
136typedef struct drm_r128_stipple32 { 138typedef struct drm_r128_stipple32 {
@@ -148,7 +150,8 @@ static int compat_r128_stipple(struct file *file, unsigned int cmd,
148 150
149 stipple = compat_alloc_user_space(sizeof(*stipple)); 151 stipple = compat_alloc_user_space(sizeof(*stipple));
150 if (!access_ok(VERIFY_WRITE, stipple, sizeof(*stipple)) 152 if (!access_ok(VERIFY_WRITE, stipple, sizeof(*stipple))
151 || __put_user((unsigned int __user *)(unsigned long)stipple32.mask, &stipple->mask)) 153 || __put_user((unsigned int __user *)(unsigned long)stipple32.mask,
154 &stipple->mask))
152 return -EFAULT; 155 return -EFAULT;
153 156
154 return drm_ioctl(file->f_dentry->d_inode, file, 157 return drm_ioctl(file->f_dentry->d_inode, file,
@@ -172,9 +175,10 @@ static int compat_r128_getparam(struct file *file, unsigned int cmd,
172 getparam = compat_alloc_user_space(sizeof(*getparam)); 175 getparam = compat_alloc_user_space(sizeof(*getparam));
173 if (!access_ok(VERIFY_WRITE, getparam, sizeof(*getparam)) 176 if (!access_ok(VERIFY_WRITE, getparam, sizeof(*getparam))
174 || __put_user(getparam32.param, &getparam->param) 177 || __put_user(getparam32.param, &getparam->param)
175 || __put_user((void __user *)(unsigned long)getparam32.value, &getparam->value)) 178 || __put_user((void __user *)(unsigned long)getparam32.value,
179 &getparam->value))
176 return -EFAULT; 180 return -EFAULT;
177 181
178 return drm_ioctl(file->f_dentry->d_inode, file, 182 return drm_ioctl(file->f_dentry->d_inode, file,
179 DRM_IOCTL_R128_GETPARAM, (unsigned long)getparam); 183 DRM_IOCTL_R128_GETPARAM, (unsigned long)getparam);
180} 184}
@@ -195,8 +199,7 @@ drm_ioctl_compat_t *r128_compat_ioctls[] = {
195 * \param arg user argument. 199 * \param arg user argument.
196 * \return zero on success or negative number on failure. 200 * \return zero on success or negative number on failure.
197 */ 201 */
198long r128_compat_ioctl(struct file *filp, unsigned int cmd, 202long r128_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
199 unsigned long arg)
200{ 203{
201 unsigned int nr = DRM_IOCTL_NR(cmd); 204 unsigned int nr = DRM_IOCTL_NR(cmd);
202 drm_ioctl_compat_t *fn = NULL; 205 drm_ioctl_compat_t *fn = NULL;
@@ -210,7 +213,7 @@ long r128_compat_ioctl(struct file *filp, unsigned int cmd,
210 213
211 lock_kernel(); /* XXX for now */ 214 lock_kernel(); /* XXX for now */
212 if (fn != NULL) 215 if (fn != NULL)
213 ret = (*fn)(filp, cmd, arg); 216 ret = (*fn) (filp, cmd, arg);
214 else 217 else
215 ret = drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg); 218 ret = drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg);
216 unlock_kernel(); 219 unlock_kernel();
diff --git a/drivers/char/drm/r128_irq.c b/drivers/char/drm/r128_irq.c
index 643a30785fe5..27eb0e31bd3b 100644
--- a/drivers/char/drm/r128_irq.c
+++ b/drivers/char/drm/r128_irq.c
@@ -1,7 +1,7 @@
1/* r128_irq.c -- IRQ handling for radeon -*- linux-c -*- 1/* r128_irq.c -- IRQ handling for radeon -*- linux-c -*-
2 * 2 *
3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 * 4 *
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the 5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license. 6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved. 7 * This notice must be preserved.
@@ -35,68 +35,67 @@
35#include "r128_drm.h" 35#include "r128_drm.h"
36#include "r128_drv.h" 36#include "r128_drv.h"
37 37
38irqreturn_t r128_driver_irq_handler( DRM_IRQ_ARGS ) 38irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS)
39{ 39{
40 drm_device_t *dev = (drm_device_t *) arg; 40 drm_device_t *dev = (drm_device_t *) arg;
41 drm_r128_private_t *dev_priv = 41 drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private;
42 (drm_r128_private_t *)dev->dev_private;
43 int status; 42 int status;
44 43
45 status = R128_READ( R128_GEN_INT_STATUS ); 44 status = R128_READ(R128_GEN_INT_STATUS);
46 45
47 /* VBLANK interrupt */ 46 /* VBLANK interrupt */
48 if ( status & R128_CRTC_VBLANK_INT ) { 47 if (status & R128_CRTC_VBLANK_INT) {
49 R128_WRITE( R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK ); 48 R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK);
50 atomic_inc(&dev->vbl_received); 49 atomic_inc(&dev->vbl_received);
51 DRM_WAKEUP(&dev->vbl_queue); 50 DRM_WAKEUP(&dev->vbl_queue);
52 drm_vbl_send_signals( dev ); 51 drm_vbl_send_signals(dev);
53 return IRQ_HANDLED; 52 return IRQ_HANDLED;
54 } 53 }
55 return IRQ_NONE; 54 return IRQ_NONE;
56} 55}
57 56
58int r128_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence) 57int r128_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence)
59{ 58{
60 unsigned int cur_vblank; 59 unsigned int cur_vblank;
61 int ret = 0; 60 int ret = 0;
62 61
63 /* Assume that the user has missed the current sequence number 62 /* Assume that the user has missed the current sequence number
64 * by about a day rather than she wants to wait for years 63 * by about a day rather than she wants to wait for years
65 * using vertical blanks... 64 * using vertical blanks...
66 */ 65 */
67 DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, 66 DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
68 ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) ) 67 (((cur_vblank = atomic_read(&dev->vbl_received))
69 - *sequence ) <= (1<<23) ) ); 68 - *sequence) <= (1 << 23)));
70 69
71 *sequence = cur_vblank; 70 *sequence = cur_vblank;
72 71
73 return ret; 72 return ret;
74} 73}
75 74
76void r128_driver_irq_preinstall( drm_device_t *dev ) { 75void r128_driver_irq_preinstall(drm_device_t * dev)
77 drm_r128_private_t *dev_priv = 76{
78 (drm_r128_private_t *)dev->dev_private; 77 drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private;
79 78
80 /* Disable *all* interrupts */ 79 /* Disable *all* interrupts */
81 R128_WRITE( R128_GEN_INT_CNTL, 0 ); 80 R128_WRITE(R128_GEN_INT_CNTL, 0);
82 /* Clear vblank bit if it's already high */ 81 /* Clear vblank bit if it's already high */
83 R128_WRITE( R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK ); 82 R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK);
84} 83}
85 84
86void r128_driver_irq_postinstall( drm_device_t *dev ) { 85void r128_driver_irq_postinstall(drm_device_t * dev)
87 drm_r128_private_t *dev_priv = 86{
88 (drm_r128_private_t *)dev->dev_private; 87 drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private;
89 88
90 /* Turn on VBL interrupt */ 89 /* Turn on VBL interrupt */
91 R128_WRITE( R128_GEN_INT_CNTL, R128_CRTC_VBLANK_INT_EN ); 90 R128_WRITE(R128_GEN_INT_CNTL, R128_CRTC_VBLANK_INT_EN);
92} 91}
93 92
94void r128_driver_irq_uninstall( drm_device_t *dev ) { 93void r128_driver_irq_uninstall(drm_device_t * dev)
95 drm_r128_private_t *dev_priv = 94{
96 (drm_r128_private_t *)dev->dev_private; 95 drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private;
97 if (!dev_priv) 96 if (!dev_priv)
98 return; 97 return;
99 98
100 /* Disable *all* interrupts */ 99 /* Disable *all* interrupts */
101 R128_WRITE( R128_GEN_INT_CNTL, 0 ); 100 R128_WRITE(R128_GEN_INT_CNTL, 0);
102} 101}
diff --git a/drivers/char/drm/r128_state.c b/drivers/char/drm/r128_state.c
index 426a71c049d9..14479cc08a57 100644
--- a/drivers/char/drm/r128_state.c
+++ b/drivers/char/drm/r128_state.c
@@ -32,235 +32,233 @@
32#include "r128_drm.h" 32#include "r128_drm.h"
33#include "r128_drv.h" 33#include "r128_drv.h"
34 34
35
36/* ================================================================ 35/* ================================================================
37 * CCE hardware state programming functions 36 * CCE hardware state programming functions
38 */ 37 */
39 38
40static void r128_emit_clip_rects( drm_r128_private_t *dev_priv, 39static void r128_emit_clip_rects(drm_r128_private_t * dev_priv,
41 drm_clip_rect_t *boxes, int count ) 40 drm_clip_rect_t * boxes, int count)
42{ 41{
43 u32 aux_sc_cntl = 0x00000000; 42 u32 aux_sc_cntl = 0x00000000;
44 RING_LOCALS; 43 RING_LOCALS;
45 DRM_DEBUG( " %s\n", __FUNCTION__ ); 44 DRM_DEBUG(" %s\n", __FUNCTION__);
46 45
47 BEGIN_RING( (count < 3? count: 3) * 5 + 2 ); 46 BEGIN_RING((count < 3 ? count : 3) * 5 + 2);
48 47
49 if ( count >= 1 ) { 48 if (count >= 1) {
50 OUT_RING( CCE_PACKET0( R128_AUX1_SC_LEFT, 3 ) ); 49 OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3));
51 OUT_RING( boxes[0].x1 ); 50 OUT_RING(boxes[0].x1);
52 OUT_RING( boxes[0].x2 - 1 ); 51 OUT_RING(boxes[0].x2 - 1);
53 OUT_RING( boxes[0].y1 ); 52 OUT_RING(boxes[0].y1);
54 OUT_RING( boxes[0].y2 - 1 ); 53 OUT_RING(boxes[0].y2 - 1);
55 54
56 aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR); 55 aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR);
57 } 56 }
58 if ( count >= 2 ) { 57 if (count >= 2) {
59 OUT_RING( CCE_PACKET0( R128_AUX2_SC_LEFT, 3 ) ); 58 OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3));
60 OUT_RING( boxes[1].x1 ); 59 OUT_RING(boxes[1].x1);
61 OUT_RING( boxes[1].x2 - 1 ); 60 OUT_RING(boxes[1].x2 - 1);
62 OUT_RING( boxes[1].y1 ); 61 OUT_RING(boxes[1].y1);
63 OUT_RING( boxes[1].y2 - 1 ); 62 OUT_RING(boxes[1].y2 - 1);
64 63
65 aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR); 64 aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR);
66 } 65 }
67 if ( count >= 3 ) { 66 if (count >= 3) {
68 OUT_RING( CCE_PACKET0( R128_AUX3_SC_LEFT, 3 ) ); 67 OUT_RING(CCE_PACKET0(R128_AUX3_SC_LEFT, 3));
69 OUT_RING( boxes[2].x1 ); 68 OUT_RING(boxes[2].x1);
70 OUT_RING( boxes[2].x2 - 1 ); 69 OUT_RING(boxes[2].x2 - 1);
71 OUT_RING( boxes[2].y1 ); 70 OUT_RING(boxes[2].y1);
72 OUT_RING( boxes[2].y2 - 1 ); 71 OUT_RING(boxes[2].y2 - 1);
73 72
74 aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR); 73 aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR);
75 } 74 }
76 75
77 OUT_RING( CCE_PACKET0( R128_AUX_SC_CNTL, 0 ) ); 76 OUT_RING(CCE_PACKET0(R128_AUX_SC_CNTL, 0));
78 OUT_RING( aux_sc_cntl ); 77 OUT_RING(aux_sc_cntl);
79 78
80 ADVANCE_RING(); 79 ADVANCE_RING();
81} 80}
82 81
83static __inline__ void r128_emit_core( drm_r128_private_t *dev_priv ) 82static __inline__ void r128_emit_core(drm_r128_private_t * dev_priv)
84{ 83{
85 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 84 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
86 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; 85 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
87 RING_LOCALS; 86 RING_LOCALS;
88 DRM_DEBUG( " %s\n", __FUNCTION__ ); 87 DRM_DEBUG(" %s\n", __FUNCTION__);
89 88
90 BEGIN_RING( 2 ); 89 BEGIN_RING(2);
91 90
92 OUT_RING( CCE_PACKET0( R128_SCALE_3D_CNTL, 0 ) ); 91 OUT_RING(CCE_PACKET0(R128_SCALE_3D_CNTL, 0));
93 OUT_RING( ctx->scale_3d_cntl ); 92 OUT_RING(ctx->scale_3d_cntl);
94 93
95 ADVANCE_RING(); 94 ADVANCE_RING();
96} 95}
97 96
98static __inline__ void r128_emit_context( drm_r128_private_t *dev_priv ) 97static __inline__ void r128_emit_context(drm_r128_private_t * dev_priv)
99{ 98{
100 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 99 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
101 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; 100 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
102 RING_LOCALS; 101 RING_LOCALS;
103 DRM_DEBUG( " %s\n", __FUNCTION__ ); 102 DRM_DEBUG(" %s\n", __FUNCTION__);
104 103
105 BEGIN_RING( 13 ); 104 BEGIN_RING(13);
106 105
107 OUT_RING( CCE_PACKET0( R128_DST_PITCH_OFFSET_C, 11 ) ); 106 OUT_RING(CCE_PACKET0(R128_DST_PITCH_OFFSET_C, 11));
108 OUT_RING( ctx->dst_pitch_offset_c ); 107 OUT_RING(ctx->dst_pitch_offset_c);
109 OUT_RING( ctx->dp_gui_master_cntl_c ); 108 OUT_RING(ctx->dp_gui_master_cntl_c);
110 OUT_RING( ctx->sc_top_left_c ); 109 OUT_RING(ctx->sc_top_left_c);
111 OUT_RING( ctx->sc_bottom_right_c ); 110 OUT_RING(ctx->sc_bottom_right_c);
112 OUT_RING( ctx->z_offset_c ); 111 OUT_RING(ctx->z_offset_c);
113 OUT_RING( ctx->z_pitch_c ); 112 OUT_RING(ctx->z_pitch_c);
114 OUT_RING( ctx->z_sten_cntl_c ); 113 OUT_RING(ctx->z_sten_cntl_c);
115 OUT_RING( ctx->tex_cntl_c ); 114 OUT_RING(ctx->tex_cntl_c);
116 OUT_RING( ctx->misc_3d_state_cntl_reg ); 115 OUT_RING(ctx->misc_3d_state_cntl_reg);
117 OUT_RING( ctx->texture_clr_cmp_clr_c ); 116 OUT_RING(ctx->texture_clr_cmp_clr_c);
118 OUT_RING( ctx->texture_clr_cmp_msk_c ); 117 OUT_RING(ctx->texture_clr_cmp_msk_c);
119 OUT_RING( ctx->fog_color_c ); 118 OUT_RING(ctx->fog_color_c);
120 119
121 ADVANCE_RING(); 120 ADVANCE_RING();
122} 121}
123 122
124static __inline__ void r128_emit_setup( drm_r128_private_t *dev_priv ) 123static __inline__ void r128_emit_setup(drm_r128_private_t * dev_priv)
125{ 124{
126 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 125 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
127 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; 126 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
128 RING_LOCALS; 127 RING_LOCALS;
129 DRM_DEBUG( " %s\n", __FUNCTION__ ); 128 DRM_DEBUG(" %s\n", __FUNCTION__);
130 129
131 BEGIN_RING( 3 ); 130 BEGIN_RING(3);
132 131
133 OUT_RING( CCE_PACKET1( R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP ) ); 132 OUT_RING(CCE_PACKET1(R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP));
134 OUT_RING( ctx->setup_cntl ); 133 OUT_RING(ctx->setup_cntl);
135 OUT_RING( ctx->pm4_vc_fpu_setup ); 134 OUT_RING(ctx->pm4_vc_fpu_setup);
136 135
137 ADVANCE_RING(); 136 ADVANCE_RING();
138} 137}
139 138
140static __inline__ void r128_emit_masks( drm_r128_private_t *dev_priv ) 139static __inline__ void r128_emit_masks(drm_r128_private_t * dev_priv)
141{ 140{
142 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 141 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
143 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; 142 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
144 RING_LOCALS; 143 RING_LOCALS;
145 DRM_DEBUG( " %s\n", __FUNCTION__ ); 144 DRM_DEBUG(" %s\n", __FUNCTION__);
146 145
147 BEGIN_RING( 5 ); 146 BEGIN_RING(5);
148 147
149 OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) ); 148 OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0));
150 OUT_RING( ctx->dp_write_mask ); 149 OUT_RING(ctx->dp_write_mask);
151 150
152 OUT_RING( CCE_PACKET0( R128_STEN_REF_MASK_C, 1 ) ); 151 OUT_RING(CCE_PACKET0(R128_STEN_REF_MASK_C, 1));
153 OUT_RING( ctx->sten_ref_mask_c ); 152 OUT_RING(ctx->sten_ref_mask_c);
154 OUT_RING( ctx->plane_3d_mask_c ); 153 OUT_RING(ctx->plane_3d_mask_c);
155 154
156 ADVANCE_RING(); 155 ADVANCE_RING();
157} 156}
158 157
159static __inline__ void r128_emit_window( drm_r128_private_t *dev_priv ) 158static __inline__ void r128_emit_window(drm_r128_private_t * dev_priv)
160{ 159{
161 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 160 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
162 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; 161 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
163 RING_LOCALS; 162 RING_LOCALS;
164 DRM_DEBUG( " %s\n", __FUNCTION__ ); 163 DRM_DEBUG(" %s\n", __FUNCTION__);
165 164
166 BEGIN_RING( 2 ); 165 BEGIN_RING(2);
167 166
168 OUT_RING( CCE_PACKET0( R128_WINDOW_XY_OFFSET, 0 ) ); 167 OUT_RING(CCE_PACKET0(R128_WINDOW_XY_OFFSET, 0));
169 OUT_RING( ctx->window_xy_offset ); 168 OUT_RING(ctx->window_xy_offset);
170 169
171 ADVANCE_RING(); 170 ADVANCE_RING();
172} 171}
173 172
174static __inline__ void r128_emit_tex0( drm_r128_private_t *dev_priv ) 173static __inline__ void r128_emit_tex0(drm_r128_private_t * dev_priv)
175{ 174{
176 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 175 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
177 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; 176 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
178 drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0]; 177 drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0];
179 int i; 178 int i;
180 RING_LOCALS; 179 RING_LOCALS;
181 DRM_DEBUG( " %s\n", __FUNCTION__ ); 180 DRM_DEBUG(" %s\n", __FUNCTION__);
182 181
183 BEGIN_RING( 7 + R128_MAX_TEXTURE_LEVELS ); 182 BEGIN_RING(7 + R128_MAX_TEXTURE_LEVELS);
184 183
185 OUT_RING( CCE_PACKET0( R128_PRIM_TEX_CNTL_C, 184 OUT_RING(CCE_PACKET0(R128_PRIM_TEX_CNTL_C,
186 2 + R128_MAX_TEXTURE_LEVELS ) ); 185 2 + R128_MAX_TEXTURE_LEVELS));
187 OUT_RING( tex->tex_cntl ); 186 OUT_RING(tex->tex_cntl);
188 OUT_RING( tex->tex_combine_cntl ); 187 OUT_RING(tex->tex_combine_cntl);
189 OUT_RING( ctx->tex_size_pitch_c ); 188 OUT_RING(ctx->tex_size_pitch_c);
190 for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) { 189 for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) {
191 OUT_RING( tex->tex_offset[i] ); 190 OUT_RING(tex->tex_offset[i]);
192 } 191 }
193 192
194 OUT_RING( CCE_PACKET0( R128_CONSTANT_COLOR_C, 1 ) ); 193 OUT_RING(CCE_PACKET0(R128_CONSTANT_COLOR_C, 1));
195 OUT_RING( ctx->constant_color_c ); 194 OUT_RING(ctx->constant_color_c);
196 OUT_RING( tex->tex_border_color ); 195 OUT_RING(tex->tex_border_color);
197 196
198 ADVANCE_RING(); 197 ADVANCE_RING();
199} 198}
200 199
201static __inline__ void r128_emit_tex1( drm_r128_private_t *dev_priv ) 200static __inline__ void r128_emit_tex1(drm_r128_private_t * dev_priv)
202{ 201{
203 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 202 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
204 drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1]; 203 drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1];
205 int i; 204 int i;
206 RING_LOCALS; 205 RING_LOCALS;
207 DRM_DEBUG( " %s\n", __FUNCTION__ ); 206 DRM_DEBUG(" %s\n", __FUNCTION__);
208 207
209 BEGIN_RING( 5 + R128_MAX_TEXTURE_LEVELS ); 208 BEGIN_RING(5 + R128_MAX_TEXTURE_LEVELS);
210 209
211 OUT_RING( CCE_PACKET0( R128_SEC_TEX_CNTL_C, 210 OUT_RING(CCE_PACKET0(R128_SEC_TEX_CNTL_C, 1 + R128_MAX_TEXTURE_LEVELS));
212 1 + R128_MAX_TEXTURE_LEVELS ) ); 211 OUT_RING(tex->tex_cntl);
213 OUT_RING( tex->tex_cntl ); 212 OUT_RING(tex->tex_combine_cntl);
214 OUT_RING( tex->tex_combine_cntl ); 213 for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) {
215 for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) { 214 OUT_RING(tex->tex_offset[i]);
216 OUT_RING( tex->tex_offset[i] );
217 } 215 }
218 216
219 OUT_RING( CCE_PACKET0( R128_SEC_TEXTURE_BORDER_COLOR_C, 0 ) ); 217 OUT_RING(CCE_PACKET0(R128_SEC_TEXTURE_BORDER_COLOR_C, 0));
220 OUT_RING( tex->tex_border_color ); 218 OUT_RING(tex->tex_border_color);
221 219
222 ADVANCE_RING(); 220 ADVANCE_RING();
223} 221}
224 222
225static __inline__ void r128_emit_state( drm_r128_private_t *dev_priv ) 223static __inline__ void r128_emit_state(drm_r128_private_t * dev_priv)
226{ 224{
227 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 225 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
228 unsigned int dirty = sarea_priv->dirty; 226 unsigned int dirty = sarea_priv->dirty;
229 227
230 DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty ); 228 DRM_DEBUG("%s: dirty=0x%08x\n", __FUNCTION__, dirty);
231 229
232 if ( dirty & R128_UPLOAD_CORE ) { 230 if (dirty & R128_UPLOAD_CORE) {
233 r128_emit_core( dev_priv ); 231 r128_emit_core(dev_priv);
234 sarea_priv->dirty &= ~R128_UPLOAD_CORE; 232 sarea_priv->dirty &= ~R128_UPLOAD_CORE;
235 } 233 }
236 234
237 if ( dirty & R128_UPLOAD_CONTEXT ) { 235 if (dirty & R128_UPLOAD_CONTEXT) {
238 r128_emit_context( dev_priv ); 236 r128_emit_context(dev_priv);
239 sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT; 237 sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT;
240 } 238 }
241 239
242 if ( dirty & R128_UPLOAD_SETUP ) { 240 if (dirty & R128_UPLOAD_SETUP) {
243 r128_emit_setup( dev_priv ); 241 r128_emit_setup(dev_priv);
244 sarea_priv->dirty &= ~R128_UPLOAD_SETUP; 242 sarea_priv->dirty &= ~R128_UPLOAD_SETUP;
245 } 243 }
246 244
247 if ( dirty & R128_UPLOAD_MASKS ) { 245 if (dirty & R128_UPLOAD_MASKS) {
248 r128_emit_masks( dev_priv ); 246 r128_emit_masks(dev_priv);
249 sarea_priv->dirty &= ~R128_UPLOAD_MASKS; 247 sarea_priv->dirty &= ~R128_UPLOAD_MASKS;
250 } 248 }
251 249
252 if ( dirty & R128_UPLOAD_WINDOW ) { 250 if (dirty & R128_UPLOAD_WINDOW) {
253 r128_emit_window( dev_priv ); 251 r128_emit_window(dev_priv);
254 sarea_priv->dirty &= ~R128_UPLOAD_WINDOW; 252 sarea_priv->dirty &= ~R128_UPLOAD_WINDOW;
255 } 253 }
256 254
257 if ( dirty & R128_UPLOAD_TEX0 ) { 255 if (dirty & R128_UPLOAD_TEX0) {
258 r128_emit_tex0( dev_priv ); 256 r128_emit_tex0(dev_priv);
259 sarea_priv->dirty &= ~R128_UPLOAD_TEX0; 257 sarea_priv->dirty &= ~R128_UPLOAD_TEX0;
260 } 258 }
261 259
262 if ( dirty & R128_UPLOAD_TEX1 ) { 260 if (dirty & R128_UPLOAD_TEX1) {
263 r128_emit_tex1( dev_priv ); 261 r128_emit_tex1(dev_priv);
264 sarea_priv->dirty &= ~R128_UPLOAD_TEX1; 262 sarea_priv->dirty &= ~R128_UPLOAD_TEX1;
265 } 263 }
266 264
@@ -270,26 +268,23 @@ static __inline__ void r128_emit_state( drm_r128_private_t *dev_priv )
270 sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE; 268 sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE;
271} 269}
272 270
273
274#if R128_PERFORMANCE_BOXES 271#if R128_PERFORMANCE_BOXES
275/* ================================================================ 272/* ================================================================
276 * Performance monitoring functions 273 * Performance monitoring functions
277 */ 274 */
278 275
279static void r128_clear_box( drm_r128_private_t *dev_priv, 276static void r128_clear_box(drm_r128_private_t * dev_priv,
280 int x, int y, int w, int h, 277 int x, int y, int w, int h, int r, int g, int b)
281 int r, int g, int b )
282{ 278{
283 u32 pitch, offset; 279 u32 pitch, offset;
284 u32 fb_bpp, color; 280 u32 fb_bpp, color;
285 RING_LOCALS; 281 RING_LOCALS;
286 282
287 switch ( dev_priv->fb_bpp ) { 283 switch (dev_priv->fb_bpp) {
288 case 16: 284 case 16:
289 fb_bpp = R128_GMC_DST_16BPP; 285 fb_bpp = R128_GMC_DST_16BPP;
290 color = (((r & 0xf8) << 8) | 286 color = (((r & 0xf8) << 8) |
291 ((g & 0xfc) << 3) | 287 ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
292 ((b & 0xf8) >> 3));
293 break; 288 break;
294 case 24: 289 case 24:
295 fb_bpp = R128_GMC_DST_24BPP; 290 fb_bpp = R128_GMC_DST_24BPP;
@@ -297,7 +292,7 @@ static void r128_clear_box( drm_r128_private_t *dev_priv,
297 break; 292 break;
298 case 32: 293 case 32:
299 fb_bpp = R128_GMC_DST_32BPP; 294 fb_bpp = R128_GMC_DST_32BPP;
300 color = (((0xff) << 24) | (r << 16) | (g << 8) | b); 295 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
301 break; 296 break;
302 default: 297 default:
303 return; 298 return;
@@ -306,60 +301,58 @@ static void r128_clear_box( drm_r128_private_t *dev_priv,
306 offset = dev_priv->back_offset; 301 offset = dev_priv->back_offset;
307 pitch = dev_priv->back_pitch >> 3; 302 pitch = dev_priv->back_pitch >> 3;
308 303
309 BEGIN_RING( 6 ); 304 BEGIN_RING(6);
310 305
311 OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); 306 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
312 OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | 307 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
313 R128_GMC_BRUSH_SOLID_COLOR | 308 R128_GMC_BRUSH_SOLID_COLOR |
314 fb_bpp | 309 fb_bpp |
315 R128_GMC_SRC_DATATYPE_COLOR | 310 R128_GMC_SRC_DATATYPE_COLOR |
316 R128_ROP3_P | 311 R128_ROP3_P |
317 R128_GMC_CLR_CMP_CNTL_DIS | 312 R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS);
318 R128_GMC_AUX_CLIP_DIS );
319 313
320 OUT_RING( (pitch << 21) | (offset >> 5) ); 314 OUT_RING((pitch << 21) | (offset >> 5));
321 OUT_RING( color ); 315 OUT_RING(color);
322 316
323 OUT_RING( (x << 16) | y ); 317 OUT_RING((x << 16) | y);
324 OUT_RING( (w << 16) | h ); 318 OUT_RING((w << 16) | h);
325 319
326 ADVANCE_RING(); 320 ADVANCE_RING();
327} 321}
328 322
329static void r128_cce_performance_boxes( drm_r128_private_t *dev_priv ) 323static void r128_cce_performance_boxes(drm_r128_private_t * dev_priv)
330{ 324{
331 if ( atomic_read( &dev_priv->idle_count ) == 0 ) { 325 if (atomic_read(&dev_priv->idle_count) == 0) {
332 r128_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 ); 326 r128_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0);
333 } else { 327 } else {
334 atomic_set( &dev_priv->idle_count, 0 ); 328 atomic_set(&dev_priv->idle_count, 0);
335 } 329 }
336} 330}
337 331
338#endif 332#endif
339 333
340
341/* ================================================================ 334/* ================================================================
342 * CCE command dispatch functions 335 * CCE command dispatch functions
343 */ 336 */
344 337
345static void r128_print_dirty( const char *msg, unsigned int flags ) 338static void r128_print_dirty(const char *msg, unsigned int flags)
346{ 339{
347 DRM_INFO( "%s: (0x%x) %s%s%s%s%s%s%s%s%s\n", 340 DRM_INFO("%s: (0x%x) %s%s%s%s%s%s%s%s%s\n",
348 msg, 341 msg,
349 flags, 342 flags,
350 (flags & R128_UPLOAD_CORE) ? "core, " : "", 343 (flags & R128_UPLOAD_CORE) ? "core, " : "",
351 (flags & R128_UPLOAD_CONTEXT) ? "context, " : "", 344 (flags & R128_UPLOAD_CONTEXT) ? "context, " : "",
352 (flags & R128_UPLOAD_SETUP) ? "setup, " : "", 345 (flags & R128_UPLOAD_SETUP) ? "setup, " : "",
353 (flags & R128_UPLOAD_TEX0) ? "tex0, " : "", 346 (flags & R128_UPLOAD_TEX0) ? "tex0, " : "",
354 (flags & R128_UPLOAD_TEX1) ? "tex1, " : "", 347 (flags & R128_UPLOAD_TEX1) ? "tex1, " : "",
355 (flags & R128_UPLOAD_MASKS) ? "masks, " : "", 348 (flags & R128_UPLOAD_MASKS) ? "masks, " : "",
356 (flags & R128_UPLOAD_WINDOW) ? "window, " : "", 349 (flags & R128_UPLOAD_WINDOW) ? "window, " : "",
357 (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "", 350 (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "",
358 (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "" ); 351 (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "");
359} 352}
360 353
361static void r128_cce_dispatch_clear( drm_device_t *dev, 354static void r128_cce_dispatch_clear(drm_device_t * dev,
362 drm_r128_clear_t *clear ) 355 drm_r128_clear_t * clear)
363{ 356{
364 drm_r128_private_t *dev_priv = dev->dev_private; 357 drm_r128_private_t *dev_priv = dev->dev_private;
365 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 358 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -368,102 +361,103 @@ static void r128_cce_dispatch_clear( drm_device_t *dev,
368 unsigned int flags = clear->flags; 361 unsigned int flags = clear->flags;
369 int i; 362 int i;
370 RING_LOCALS; 363 RING_LOCALS;
371 DRM_DEBUG( "%s\n", __FUNCTION__ ); 364 DRM_DEBUG("%s\n", __FUNCTION__);
372 365
373 if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { 366 if (dev_priv->page_flipping && dev_priv->current_page == 1) {
374 unsigned int tmp = flags; 367 unsigned int tmp = flags;
375 368
376 flags &= ~(R128_FRONT | R128_BACK); 369 flags &= ~(R128_FRONT | R128_BACK);
377 if ( tmp & R128_FRONT ) flags |= R128_BACK; 370 if (tmp & R128_FRONT)
378 if ( tmp & R128_BACK ) flags |= R128_FRONT; 371 flags |= R128_BACK;
372 if (tmp & R128_BACK)
373 flags |= R128_FRONT;
379 } 374 }
380 375
381 for ( i = 0 ; i < nbox ; i++ ) { 376 for (i = 0; i < nbox; i++) {
382 int x = pbox[i].x1; 377 int x = pbox[i].x1;
383 int y = pbox[i].y1; 378 int y = pbox[i].y1;
384 int w = pbox[i].x2 - x; 379 int w = pbox[i].x2 - x;
385 int h = pbox[i].y2 - y; 380 int h = pbox[i].y2 - y;
386 381
387 DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n", 382 DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n",
388 pbox[i].x1, pbox[i].y1, pbox[i].x2, 383 pbox[i].x1, pbox[i].y1, pbox[i].x2,
389 pbox[i].y2, flags ); 384 pbox[i].y2, flags);
390 385
391 if ( flags & (R128_FRONT | R128_BACK) ) { 386 if (flags & (R128_FRONT | R128_BACK)) {
392 BEGIN_RING( 2 ); 387 BEGIN_RING(2);
393 388
394 OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) ); 389 OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0));
395 OUT_RING( clear->color_mask ); 390 OUT_RING(clear->color_mask);
396 391
397 ADVANCE_RING(); 392 ADVANCE_RING();
398 } 393 }
399 394
400 if ( flags & R128_FRONT ) { 395 if (flags & R128_FRONT) {
401 BEGIN_RING( 6 ); 396 BEGIN_RING(6);
402 397
403 OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); 398 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
404 OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | 399 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
405 R128_GMC_BRUSH_SOLID_COLOR | 400 R128_GMC_BRUSH_SOLID_COLOR |
406 (dev_priv->color_fmt << 8) | 401 (dev_priv->color_fmt << 8) |
407 R128_GMC_SRC_DATATYPE_COLOR | 402 R128_GMC_SRC_DATATYPE_COLOR |
408 R128_ROP3_P | 403 R128_ROP3_P |
409 R128_GMC_CLR_CMP_CNTL_DIS | 404 R128_GMC_CLR_CMP_CNTL_DIS |
410 R128_GMC_AUX_CLIP_DIS ); 405 R128_GMC_AUX_CLIP_DIS);
411 406
412 OUT_RING( dev_priv->front_pitch_offset_c ); 407 OUT_RING(dev_priv->front_pitch_offset_c);
413 OUT_RING( clear->clear_color ); 408 OUT_RING(clear->clear_color);
414 409
415 OUT_RING( (x << 16) | y ); 410 OUT_RING((x << 16) | y);
416 OUT_RING( (w << 16) | h ); 411 OUT_RING((w << 16) | h);
417 412
418 ADVANCE_RING(); 413 ADVANCE_RING();
419 } 414 }
420 415
421 if ( flags & R128_BACK ) { 416 if (flags & R128_BACK) {
422 BEGIN_RING( 6 ); 417 BEGIN_RING(6);
423 418
424 OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); 419 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
425 OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | 420 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
426 R128_GMC_BRUSH_SOLID_COLOR | 421 R128_GMC_BRUSH_SOLID_COLOR |
427 (dev_priv->color_fmt << 8) | 422 (dev_priv->color_fmt << 8) |
428 R128_GMC_SRC_DATATYPE_COLOR | 423 R128_GMC_SRC_DATATYPE_COLOR |
429 R128_ROP3_P | 424 R128_ROP3_P |
430 R128_GMC_CLR_CMP_CNTL_DIS | 425 R128_GMC_CLR_CMP_CNTL_DIS |
431 R128_GMC_AUX_CLIP_DIS ); 426 R128_GMC_AUX_CLIP_DIS);
432 427
433 OUT_RING( dev_priv->back_pitch_offset_c ); 428 OUT_RING(dev_priv->back_pitch_offset_c);
434 OUT_RING( clear->clear_color ); 429 OUT_RING(clear->clear_color);
435 430
436 OUT_RING( (x << 16) | y ); 431 OUT_RING((x << 16) | y);
437 OUT_RING( (w << 16) | h ); 432 OUT_RING((w << 16) | h);
438 433
439 ADVANCE_RING(); 434 ADVANCE_RING();
440 } 435 }
441 436
442 if ( flags & R128_DEPTH ) { 437 if (flags & R128_DEPTH) {
443 BEGIN_RING( 6 ); 438 BEGIN_RING(6);
444 439
445 OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); 440 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
446 OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | 441 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
447 R128_GMC_BRUSH_SOLID_COLOR | 442 R128_GMC_BRUSH_SOLID_COLOR |
448 (dev_priv->depth_fmt << 8) | 443 (dev_priv->depth_fmt << 8) |
449 R128_GMC_SRC_DATATYPE_COLOR | 444 R128_GMC_SRC_DATATYPE_COLOR |
450 R128_ROP3_P | 445 R128_ROP3_P |
451 R128_GMC_CLR_CMP_CNTL_DIS | 446 R128_GMC_CLR_CMP_CNTL_DIS |
452 R128_GMC_AUX_CLIP_DIS | 447 R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS);
453 R128_GMC_WR_MSK_DIS );
454 448
455 OUT_RING( dev_priv->depth_pitch_offset_c ); 449 OUT_RING(dev_priv->depth_pitch_offset_c);
456 OUT_RING( clear->clear_depth ); 450 OUT_RING(clear->clear_depth);
457 451
458 OUT_RING( (x << 16) | y ); 452 OUT_RING((x << 16) | y);
459 OUT_RING( (w << 16) | h ); 453 OUT_RING((w << 16) | h);
460 454
461 ADVANCE_RING(); 455 ADVANCE_RING();
462 } 456 }
463 } 457 }
464} 458}
465 459
466static void r128_cce_dispatch_swap( drm_device_t *dev ) 460static void r128_cce_dispatch_swap(drm_device_t * dev)
467{ 461{
468 drm_r128_private_t *dev_priv = dev->dev_private; 462 drm_r128_private_t *dev_priv = dev->dev_private;
469 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 463 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -471,48 +465,46 @@ static void r128_cce_dispatch_swap( drm_device_t *dev )
471 drm_clip_rect_t *pbox = sarea_priv->boxes; 465 drm_clip_rect_t *pbox = sarea_priv->boxes;
472 int i; 466 int i;
473 RING_LOCALS; 467 RING_LOCALS;
474 DRM_DEBUG( "%s\n", __FUNCTION__ ); 468 DRM_DEBUG("%s\n", __FUNCTION__);
475 469
476#if R128_PERFORMANCE_BOXES 470#if R128_PERFORMANCE_BOXES
477 /* Do some trivial performance monitoring... 471 /* Do some trivial performance monitoring...
478 */ 472 */
479 r128_cce_performance_boxes( dev_priv ); 473 r128_cce_performance_boxes(dev_priv);
480#endif 474#endif
481 475
482 for ( i = 0 ; i < nbox ; i++ ) { 476 for (i = 0; i < nbox; i++) {
483 int x = pbox[i].x1; 477 int x = pbox[i].x1;
484 int y = pbox[i].y1; 478 int y = pbox[i].y1;
485 int w = pbox[i].x2 - x; 479 int w = pbox[i].x2 - x;
486 int h = pbox[i].y2 - y; 480 int h = pbox[i].y2 - y;
487 481
488 BEGIN_RING( 7 ); 482 BEGIN_RING(7);
489 483
490 OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); 484 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
491 OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | 485 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
492 R128_GMC_DST_PITCH_OFFSET_CNTL | 486 R128_GMC_DST_PITCH_OFFSET_CNTL |
493 R128_GMC_BRUSH_NONE | 487 R128_GMC_BRUSH_NONE |
494 (dev_priv->color_fmt << 8) | 488 (dev_priv->color_fmt << 8) |
495 R128_GMC_SRC_DATATYPE_COLOR | 489 R128_GMC_SRC_DATATYPE_COLOR |
496 R128_ROP3_S | 490 R128_ROP3_S |
497 R128_DP_SRC_SOURCE_MEMORY | 491 R128_DP_SRC_SOURCE_MEMORY |
498 R128_GMC_CLR_CMP_CNTL_DIS | 492 R128_GMC_CLR_CMP_CNTL_DIS |
499 R128_GMC_AUX_CLIP_DIS | 493 R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS);
500 R128_GMC_WR_MSK_DIS );
501 494
502 /* Make this work even if front & back are flipped: 495 /* Make this work even if front & back are flipped:
503 */ 496 */
504 if (dev_priv->current_page == 0) { 497 if (dev_priv->current_page == 0) {
505 OUT_RING( dev_priv->back_pitch_offset_c ); 498 OUT_RING(dev_priv->back_pitch_offset_c);
506 OUT_RING( dev_priv->front_pitch_offset_c ); 499 OUT_RING(dev_priv->front_pitch_offset_c);
507 } 500 } else {
508 else { 501 OUT_RING(dev_priv->front_pitch_offset_c);
509 OUT_RING( dev_priv->front_pitch_offset_c ); 502 OUT_RING(dev_priv->back_pitch_offset_c);
510 OUT_RING( dev_priv->back_pitch_offset_c );
511 } 503 }
512 504
513 OUT_RING( (x << 16) | y ); 505 OUT_RING((x << 16) | y);
514 OUT_RING( (x << 16) | y ); 506 OUT_RING((x << 16) | y);
515 OUT_RING( (w << 16) | h ); 507 OUT_RING((w << 16) | h);
516 508
517 ADVANCE_RING(); 509 ADVANCE_RING();
518 } 510 }
@@ -523,38 +515,37 @@ static void r128_cce_dispatch_swap( drm_device_t *dev )
523 */ 515 */
524 dev_priv->sarea_priv->last_frame++; 516 dev_priv->sarea_priv->last_frame++;
525 517
526 BEGIN_RING( 2 ); 518 BEGIN_RING(2);
527 519
528 OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) ); 520 OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0));
529 OUT_RING( dev_priv->sarea_priv->last_frame ); 521 OUT_RING(dev_priv->sarea_priv->last_frame);
530 522
531 ADVANCE_RING(); 523 ADVANCE_RING();
532} 524}
533 525
534static void r128_cce_dispatch_flip( drm_device_t *dev ) 526static void r128_cce_dispatch_flip(drm_device_t * dev)
535{ 527{
536 drm_r128_private_t *dev_priv = dev->dev_private; 528 drm_r128_private_t *dev_priv = dev->dev_private;
537 RING_LOCALS; 529 RING_LOCALS;
538 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", 530 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
539 __FUNCTION__, 531 __FUNCTION__,
540 dev_priv->current_page, 532 dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage);
541 dev_priv->sarea_priv->pfCurrentPage);
542 533
543#if R128_PERFORMANCE_BOXES 534#if R128_PERFORMANCE_BOXES
544 /* Do some trivial performance monitoring... 535 /* Do some trivial performance monitoring...
545 */ 536 */
546 r128_cce_performance_boxes( dev_priv ); 537 r128_cce_performance_boxes(dev_priv);
547#endif 538#endif
548 539
549 BEGIN_RING( 4 ); 540 BEGIN_RING(4);
550 541
551 R128_WAIT_UNTIL_PAGE_FLIPPED(); 542 R128_WAIT_UNTIL_PAGE_FLIPPED();
552 OUT_RING( CCE_PACKET0( R128_CRTC_OFFSET, 0 ) ); 543 OUT_RING(CCE_PACKET0(R128_CRTC_OFFSET, 0));
553 544
554 if ( dev_priv->current_page == 0 ) { 545 if (dev_priv->current_page == 0) {
555 OUT_RING( dev_priv->back_offset ); 546 OUT_RING(dev_priv->back_offset);
556 } else { 547 } else {
557 OUT_RING( dev_priv->front_offset ); 548 OUT_RING(dev_priv->front_offset);
558 } 549 }
559 550
560 ADVANCE_RING(); 551 ADVANCE_RING();
@@ -565,18 +556,17 @@ static void r128_cce_dispatch_flip( drm_device_t *dev )
565 */ 556 */
566 dev_priv->sarea_priv->last_frame++; 557 dev_priv->sarea_priv->last_frame++;
567 dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page = 558 dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
568 1 - dev_priv->current_page; 559 1 - dev_priv->current_page;
569 560
570 BEGIN_RING( 2 ); 561 BEGIN_RING(2);
571 562
572 OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) ); 563 OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0));
573 OUT_RING( dev_priv->sarea_priv->last_frame ); 564 OUT_RING(dev_priv->sarea_priv->last_frame);
574 565
575 ADVANCE_RING(); 566 ADVANCE_RING();
576} 567}
577 568
578static void r128_cce_dispatch_vertex( drm_device_t *dev, 569static void r128_cce_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf)
579 drm_buf_t *buf )
580{ 570{
581 drm_r128_private_t *dev_priv = dev->dev_private; 571 drm_r128_private_t *dev_priv = dev->dev_private;
582 drm_r128_buf_priv_t *buf_priv = buf->dev_private; 572 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
@@ -587,50 +577,50 @@ static void r128_cce_dispatch_vertex( drm_device_t *dev,
587 int prim = buf_priv->prim; 577 int prim = buf_priv->prim;
588 int i = 0; 578 int i = 0;
589 RING_LOCALS; 579 RING_LOCALS;
590 DRM_DEBUG( "buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox ); 580 DRM_DEBUG("buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox);
591 581
592 if ( 0 ) 582 if (0)
593 r128_print_dirty( "dispatch_vertex", sarea_priv->dirty ); 583 r128_print_dirty("dispatch_vertex", sarea_priv->dirty);
594 584
595 if ( buf->used ) { 585 if (buf->used) {
596 buf_priv->dispatched = 1; 586 buf_priv->dispatched = 1;
597 587
598 if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) { 588 if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) {
599 r128_emit_state( dev_priv ); 589 r128_emit_state(dev_priv);
600 } 590 }
601 591
602 do { 592 do {
603 /* Emit the next set of up to three cliprects */ 593 /* Emit the next set of up to three cliprects */
604 if ( i < sarea_priv->nbox ) { 594 if (i < sarea_priv->nbox) {
605 r128_emit_clip_rects( dev_priv, 595 r128_emit_clip_rects(dev_priv,
606 &sarea_priv->boxes[i], 596 &sarea_priv->boxes[i],
607 sarea_priv->nbox - i ); 597 sarea_priv->nbox - i);
608 } 598 }
609 599
610 /* Emit the vertex buffer rendering commands */ 600 /* Emit the vertex buffer rendering commands */
611 BEGIN_RING( 5 ); 601 BEGIN_RING(5);
612 602
613 OUT_RING( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, 3 ) ); 603 OUT_RING(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM, 3));
614 OUT_RING( offset ); 604 OUT_RING(offset);
615 OUT_RING( size ); 605 OUT_RING(size);
616 OUT_RING( format ); 606 OUT_RING(format);
617 OUT_RING( prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST | 607 OUT_RING(prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST |
618 (size << R128_CCE_VC_CNTL_NUM_SHIFT) ); 608 (size << R128_CCE_VC_CNTL_NUM_SHIFT));
619 609
620 ADVANCE_RING(); 610 ADVANCE_RING();
621 611
622 i += 3; 612 i += 3;
623 } while ( i < sarea_priv->nbox ); 613 } while (i < sarea_priv->nbox);
624 } 614 }
625 615
626 if ( buf_priv->discard ) { 616 if (buf_priv->discard) {
627 buf_priv->age = dev_priv->sarea_priv->last_dispatch; 617 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
628 618
629 /* Emit the vertex buffer age */ 619 /* Emit the vertex buffer age */
630 BEGIN_RING( 2 ); 620 BEGIN_RING(2);
631 621
632 OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); 622 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
633 OUT_RING( buf_priv->age ); 623 OUT_RING(buf_priv->age);
634 624
635 ADVANCE_RING(); 625 ADVANCE_RING();
636 626
@@ -646,17 +636,15 @@ static void r128_cce_dispatch_vertex( drm_device_t *dev,
646 sarea_priv->nbox = 0; 636 sarea_priv->nbox = 0;
647} 637}
648 638
649static void r128_cce_dispatch_indirect( drm_device_t *dev, 639static void r128_cce_dispatch_indirect(drm_device_t * dev,
650 drm_buf_t *buf, 640 drm_buf_t * buf, int start, int end)
651 int start, int end )
652{ 641{
653 drm_r128_private_t *dev_priv = dev->dev_private; 642 drm_r128_private_t *dev_priv = dev->dev_private;
654 drm_r128_buf_priv_t *buf_priv = buf->dev_private; 643 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
655 RING_LOCALS; 644 RING_LOCALS;
656 DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n", 645 DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end);
657 buf->idx, start, end );
658 646
659 if ( start != end ) { 647 if (start != end) {
660 int offset = buf->bus_address + start; 648 int offset = buf->bus_address + start;
661 int dwords = (end - start + 3) / sizeof(u32); 649 int dwords = (end - start + 3) / sizeof(u32);
662 650
@@ -664,33 +652,33 @@ static void r128_cce_dispatch_indirect( drm_device_t *dev,
664 * dwords, so if we've been given an odd number we must 652 * dwords, so if we've been given an odd number we must
665 * pad the data with a Type-2 CCE packet. 653 * pad the data with a Type-2 CCE packet.
666 */ 654 */
667 if ( dwords & 1 ) { 655 if (dwords & 1) {
668 u32 *data = (u32 *) 656 u32 *data = (u32 *)
669 ((char *)dev->agp_buffer_map->handle 657 ((char *)dev->agp_buffer_map->handle
670 + buf->offset + start); 658 + buf->offset + start);
671 data[dwords++] = cpu_to_le32( R128_CCE_PACKET2 ); 659 data[dwords++] = cpu_to_le32(R128_CCE_PACKET2);
672 } 660 }
673 661
674 buf_priv->dispatched = 1; 662 buf_priv->dispatched = 1;
675 663
676 /* Fire off the indirect buffer */ 664 /* Fire off the indirect buffer */
677 BEGIN_RING( 3 ); 665 BEGIN_RING(3);
678 666
679 OUT_RING( CCE_PACKET0( R128_PM4_IW_INDOFF, 1 ) ); 667 OUT_RING(CCE_PACKET0(R128_PM4_IW_INDOFF, 1));
680 OUT_RING( offset ); 668 OUT_RING(offset);
681 OUT_RING( dwords ); 669 OUT_RING(dwords);
682 670
683 ADVANCE_RING(); 671 ADVANCE_RING();
684 } 672 }
685 673
686 if ( buf_priv->discard ) { 674 if (buf_priv->discard) {
687 buf_priv->age = dev_priv->sarea_priv->last_dispatch; 675 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
688 676
689 /* Emit the indirect buffer age */ 677 /* Emit the indirect buffer age */
690 BEGIN_RING( 2 ); 678 BEGIN_RING(2);
691 679
692 OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); 680 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
693 OUT_RING( buf_priv->age ); 681 OUT_RING(buf_priv->age);
694 682
695 ADVANCE_RING(); 683 ADVANCE_RING();
696 684
@@ -703,10 +691,9 @@ static void r128_cce_dispatch_indirect( drm_device_t *dev,
703 dev_priv->sarea_priv->last_dispatch++; 691 dev_priv->sarea_priv->last_dispatch++;
704} 692}
705 693
706static void r128_cce_dispatch_indices( drm_device_t *dev, 694static void r128_cce_dispatch_indices(drm_device_t * dev,
707 drm_buf_t *buf, 695 drm_buf_t * buf,
708 int start, int end, 696 int start, int end, int count)
709 int count )
710{ 697{
711 drm_r128_private_t *dev_priv = dev->dev_private; 698 drm_r128_private_t *dev_priv = dev->dev_private;
712 drm_r128_buf_priv_t *buf_priv = buf->dev_private; 699 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
@@ -718,62 +705,62 @@ static void r128_cce_dispatch_indices( drm_device_t *dev,
718 int dwords; 705 int dwords;
719 int i = 0; 706 int i = 0;
720 RING_LOCALS; 707 RING_LOCALS;
721 DRM_DEBUG( "indices: s=%d e=%d c=%d\n", start, end, count ); 708 DRM_DEBUG("indices: s=%d e=%d c=%d\n", start, end, count);
722 709
723 if ( 0 ) 710 if (0)
724 r128_print_dirty( "dispatch_indices", sarea_priv->dirty ); 711 r128_print_dirty("dispatch_indices", sarea_priv->dirty);
725 712
726 if ( start != end ) { 713 if (start != end) {
727 buf_priv->dispatched = 1; 714 buf_priv->dispatched = 1;
728 715
729 if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) { 716 if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) {
730 r128_emit_state( dev_priv ); 717 r128_emit_state(dev_priv);
731 } 718 }
732 719
733 dwords = (end - start + 3) / sizeof(u32); 720 dwords = (end - start + 3) / sizeof(u32);
734 721
735 data = (u32 *)((char *)dev->agp_buffer_map->handle 722 data = (u32 *) ((char *)dev->agp_buffer_map->handle
736 + buf->offset + start); 723 + buf->offset + start);
737 724
738 data[0] = cpu_to_le32( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, 725 data[0] = cpu_to_le32(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM,
739 dwords-2 ) ); 726 dwords - 2));
740 727
741 data[1] = cpu_to_le32( offset ); 728 data[1] = cpu_to_le32(offset);
742 data[2] = cpu_to_le32( R128_MAX_VB_VERTS ); 729 data[2] = cpu_to_le32(R128_MAX_VB_VERTS);
743 data[3] = cpu_to_le32( format ); 730 data[3] = cpu_to_le32(format);
744 data[4] = cpu_to_le32( (prim | R128_CCE_VC_CNTL_PRIM_WALK_IND | 731 data[4] = cpu_to_le32((prim | R128_CCE_VC_CNTL_PRIM_WALK_IND |
745 (count << 16)) ); 732 (count << 16)));
746 733
747 if ( count & 0x1 ) { 734 if (count & 0x1) {
748#ifdef __LITTLE_ENDIAN 735#ifdef __LITTLE_ENDIAN
749 data[dwords-1] &= 0x0000ffff; 736 data[dwords - 1] &= 0x0000ffff;
750#else 737#else
751 data[dwords-1] &= 0xffff0000; 738 data[dwords - 1] &= 0xffff0000;
752#endif 739#endif
753 } 740 }
754 741
755 do { 742 do {
756 /* Emit the next set of up to three cliprects */ 743 /* Emit the next set of up to three cliprects */
757 if ( i < sarea_priv->nbox ) { 744 if (i < sarea_priv->nbox) {
758 r128_emit_clip_rects( dev_priv, 745 r128_emit_clip_rects(dev_priv,
759 &sarea_priv->boxes[i], 746 &sarea_priv->boxes[i],
760 sarea_priv->nbox - i ); 747 sarea_priv->nbox - i);
761 } 748 }
762 749
763 r128_cce_dispatch_indirect( dev, buf, start, end ); 750 r128_cce_dispatch_indirect(dev, buf, start, end);
764 751
765 i += 3; 752 i += 3;
766 } while ( i < sarea_priv->nbox ); 753 } while (i < sarea_priv->nbox);
767 } 754 }
768 755
769 if ( buf_priv->discard ) { 756 if (buf_priv->discard) {
770 buf_priv->age = dev_priv->sarea_priv->last_dispatch; 757 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
771 758
772 /* Emit the vertex buffer age */ 759 /* Emit the vertex buffer age */
773 BEGIN_RING( 2 ); 760 BEGIN_RING(2);
774 761
775 OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); 762 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
776 OUT_RING( buf_priv->age ); 763 OUT_RING(buf_priv->age);
777 764
778 ADVANCE_RING(); 765 ADVANCE_RING();
779 766
@@ -788,9 +775,8 @@ static void r128_cce_dispatch_indices( drm_device_t *dev,
788 sarea_priv->nbox = 0; 775 sarea_priv->nbox = 0;
789} 776}
790 777
791static int r128_cce_dispatch_blit( DRMFILE filp, 778static int r128_cce_dispatch_blit(DRMFILE filp,
792 drm_device_t *dev, 779 drm_device_t * dev, drm_r128_blit_t * blit)
793 drm_r128_blit_t *blit )
794{ 780{
795 drm_r128_private_t *dev_priv = dev->dev_private; 781 drm_r128_private_t *dev_priv = dev->dev_private;
796 drm_device_dma_t *dma = dev->dma; 782 drm_device_dma_t *dma = dev->dma;
@@ -799,13 +785,13 @@ static int r128_cce_dispatch_blit( DRMFILE filp,
799 u32 *data; 785 u32 *data;
800 int dword_shift, dwords; 786 int dword_shift, dwords;
801 RING_LOCALS; 787 RING_LOCALS;
802 DRM_DEBUG( "\n" ); 788 DRM_DEBUG("\n");
803 789
804 /* The compiler won't optimize away a division by a variable, 790 /* The compiler won't optimize away a division by a variable,
805 * even if the only legal values are powers of two. Thus, we'll 791 * even if the only legal values are powers of two. Thus, we'll
806 * use a shift instead. 792 * use a shift instead.
807 */ 793 */
808 switch ( blit->format ) { 794 switch (blit->format) {
809 case R128_DATATYPE_ARGB8888: 795 case R128_DATATYPE_ARGB8888:
810 dword_shift = 0; 796 dword_shift = 0;
811 break; 797 break;
@@ -821,7 +807,7 @@ static int r128_cce_dispatch_blit( DRMFILE filp,
821 dword_shift = 2; 807 dword_shift = 2;
822 break; 808 break;
823 default: 809 default:
824 DRM_ERROR( "invalid blit format %d\n", blit->format ); 810 DRM_ERROR("invalid blit format %d\n", blit->format);
825 return DRM_ERR(EINVAL); 811 return DRM_ERR(EINVAL);
826 } 812 }
827 813
@@ -830,10 +816,10 @@ static int r128_cce_dispatch_blit( DRMFILE filp,
830 * data from the host data blit, otherwise part of the texture 816 * data from the host data blit, otherwise part of the texture
831 * image may be corrupted. 817 * image may be corrupted.
832 */ 818 */
833 BEGIN_RING( 2 ); 819 BEGIN_RING(2);
834 820
835 OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) ); 821 OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0));
836 OUT_RING( R128_PC_RI_GUI | R128_PC_FLUSH_GUI ); 822 OUT_RING(R128_PC_RI_GUI | R128_PC_FLUSH_GUI);
837 823
838 ADVANCE_RING(); 824 ADVANCE_RING();
839 825
@@ -842,13 +828,13 @@ static int r128_cce_dispatch_blit( DRMFILE filp,
842 buf = dma->buflist[blit->idx]; 828 buf = dma->buflist[blit->idx];
843 buf_priv = buf->dev_private; 829 buf_priv = buf->dev_private;
844 830
845 if ( buf->filp != filp ) { 831 if (buf->filp != filp) {
846 DRM_ERROR( "process %d using buffer owned by %p\n", 832 DRM_ERROR("process %d using buffer owned by %p\n",
847 DRM_CURRENTPID, buf->filp ); 833 DRM_CURRENTPID, buf->filp);
848 return DRM_ERR(EINVAL); 834 return DRM_ERR(EINVAL);
849 } 835 }
850 if ( buf->pending ) { 836 if (buf->pending) {
851 DRM_ERROR( "sending pending buffer %d\n", blit->idx ); 837 DRM_ERROR("sending pending buffer %d\n", blit->idx);
852 return DRM_ERR(EINVAL); 838 return DRM_ERR(EINVAL);
853 } 839 }
854 840
@@ -856,45 +842,43 @@ static int r128_cce_dispatch_blit( DRMFILE filp,
856 842
857 dwords = (blit->width * blit->height) >> dword_shift; 843 dwords = (blit->width * blit->height) >> dword_shift;
858 844
859 data = (u32 *)((char *)dev->agp_buffer_map->handle + buf->offset); 845 data = (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
860 846
861 data[0] = cpu_to_le32( CCE_PACKET3( R128_CNTL_HOSTDATA_BLT, dwords + 6 ) ); 847 data[0] = cpu_to_le32(CCE_PACKET3(R128_CNTL_HOSTDATA_BLT, dwords + 6));
862 data[1] = cpu_to_le32( (R128_GMC_DST_PITCH_OFFSET_CNTL | 848 data[1] = cpu_to_le32((R128_GMC_DST_PITCH_OFFSET_CNTL |
863 R128_GMC_BRUSH_NONE | 849 R128_GMC_BRUSH_NONE |
864 (blit->format << 8) | 850 (blit->format << 8) |
865 R128_GMC_SRC_DATATYPE_COLOR | 851 R128_GMC_SRC_DATATYPE_COLOR |
866 R128_ROP3_S | 852 R128_ROP3_S |
867 R128_DP_SRC_SOURCE_HOST_DATA | 853 R128_DP_SRC_SOURCE_HOST_DATA |
868 R128_GMC_CLR_CMP_CNTL_DIS | 854 R128_GMC_CLR_CMP_CNTL_DIS |
869 R128_GMC_AUX_CLIP_DIS | 855 R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS));
870 R128_GMC_WR_MSK_DIS) ); 856
871 857 data[2] = cpu_to_le32((blit->pitch << 21) | (blit->offset >> 5));
872 data[2] = cpu_to_le32( (blit->pitch << 21) | (blit->offset >> 5) ); 858 data[3] = cpu_to_le32(0xffffffff);
873 data[3] = cpu_to_le32( 0xffffffff ); 859 data[4] = cpu_to_le32(0xffffffff);
874 data[4] = cpu_to_le32( 0xffffffff ); 860 data[5] = cpu_to_le32((blit->y << 16) | blit->x);
875 data[5] = cpu_to_le32( (blit->y << 16) | blit->x ); 861 data[6] = cpu_to_le32((blit->height << 16) | blit->width);
876 data[6] = cpu_to_le32( (blit->height << 16) | blit->width ); 862 data[7] = cpu_to_le32(dwords);
877 data[7] = cpu_to_le32( dwords );
878 863
879 buf->used = (dwords + 8) * sizeof(u32); 864 buf->used = (dwords + 8) * sizeof(u32);
880 865
881 r128_cce_dispatch_indirect( dev, buf, 0, buf->used ); 866 r128_cce_dispatch_indirect(dev, buf, 0, buf->used);
882 867
883 /* Flush the pixel cache after the blit completes. This ensures 868 /* Flush the pixel cache after the blit completes. This ensures
884 * the texture data is written out to memory before rendering 869 * the texture data is written out to memory before rendering
885 * continues. 870 * continues.
886 */ 871 */
887 BEGIN_RING( 2 ); 872 BEGIN_RING(2);
888 873
889 OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) ); 874 OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0));
890 OUT_RING( R128_PC_FLUSH_GUI ); 875 OUT_RING(R128_PC_FLUSH_GUI);
891 876
892 ADVANCE_RING(); 877 ADVANCE_RING();
893 878
894 return 0; 879 return 0;
895} 880}
896 881
897
898/* ================================================================ 882/* ================================================================
899 * Tiled depth buffer management 883 * Tiled depth buffer management
900 * 884 *
@@ -902,8 +886,8 @@ static int r128_cce_dispatch_blit( DRMFILE filp,
902 * have hardware stencil support. 886 * have hardware stencil support.
903 */ 887 */
904 888
905static int r128_cce_dispatch_write_span( drm_device_t *dev, 889static int r128_cce_dispatch_write_span(drm_device_t * dev,
906 drm_r128_depth_t *depth ) 890 drm_r128_depth_t * depth)
907{ 891{
908 drm_r128_private_t *dev_priv = dev->dev_private; 892 drm_r128_private_t *dev_priv = dev->dev_private;
909 int count, x, y; 893 int count, x, y;
@@ -911,95 +895,95 @@ static int r128_cce_dispatch_write_span( drm_device_t *dev,
911 u8 *mask; 895 u8 *mask;
912 int i, buffer_size, mask_size; 896 int i, buffer_size, mask_size;
913 RING_LOCALS; 897 RING_LOCALS;
914 DRM_DEBUG( "\n" ); 898 DRM_DEBUG("\n");
915 899
916 count = depth->n; 900 count = depth->n;
917 if (count > 4096 || count <= 0) 901 if (count > 4096 || count <= 0)
918 return DRM_ERR(EMSGSIZE); 902 return DRM_ERR(EMSGSIZE);
919 903
920 if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) { 904 if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) {
921 return DRM_ERR(EFAULT); 905 return DRM_ERR(EFAULT);
922 } 906 }
923 if ( DRM_COPY_FROM_USER( &y, depth->y, sizeof(y) ) ) { 907 if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) {
924 return DRM_ERR(EFAULT); 908 return DRM_ERR(EFAULT);
925 } 909 }
926 910
927 buffer_size = depth->n * sizeof(u32); 911 buffer_size = depth->n * sizeof(u32);
928 buffer = drm_alloc( buffer_size, DRM_MEM_BUFS ); 912 buffer = drm_alloc(buffer_size, DRM_MEM_BUFS);
929 if ( buffer == NULL ) 913 if (buffer == NULL)
930 return DRM_ERR(ENOMEM); 914 return DRM_ERR(ENOMEM);
931 if ( DRM_COPY_FROM_USER( buffer, depth->buffer, buffer_size ) ) { 915 if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) {
932 drm_free( buffer, buffer_size, DRM_MEM_BUFS); 916 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
933 return DRM_ERR(EFAULT); 917 return DRM_ERR(EFAULT);
934 } 918 }
935 919
936 mask_size = depth->n * sizeof(u8); 920 mask_size = depth->n * sizeof(u8);
937 if ( depth->mask ) { 921 if (depth->mask) {
938 mask = drm_alloc( mask_size, DRM_MEM_BUFS ); 922 mask = drm_alloc(mask_size, DRM_MEM_BUFS);
939 if ( mask == NULL ) { 923 if (mask == NULL) {
940 drm_free( buffer, buffer_size, DRM_MEM_BUFS ); 924 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
941 return DRM_ERR(ENOMEM); 925 return DRM_ERR(ENOMEM);
942 } 926 }
943 if ( DRM_COPY_FROM_USER( mask, depth->mask, mask_size ) ) { 927 if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) {
944 drm_free( buffer, buffer_size, DRM_MEM_BUFS ); 928 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
945 drm_free( mask, mask_size, DRM_MEM_BUFS ); 929 drm_free(mask, mask_size, DRM_MEM_BUFS);
946 return DRM_ERR(EFAULT); 930 return DRM_ERR(EFAULT);
947 } 931 }
948 932
949 for ( i = 0 ; i < count ; i++, x++ ) { 933 for (i = 0; i < count; i++, x++) {
950 if ( mask[i] ) { 934 if (mask[i]) {
951 BEGIN_RING( 6 ); 935 BEGIN_RING(6);
952 936
953 OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); 937 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
954 OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | 938 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
955 R128_GMC_BRUSH_SOLID_COLOR | 939 R128_GMC_BRUSH_SOLID_COLOR |
956 (dev_priv->depth_fmt << 8) | 940 (dev_priv->depth_fmt << 8) |
957 R128_GMC_SRC_DATATYPE_COLOR | 941 R128_GMC_SRC_DATATYPE_COLOR |
958 R128_ROP3_P | 942 R128_ROP3_P |
959 R128_GMC_CLR_CMP_CNTL_DIS | 943 R128_GMC_CLR_CMP_CNTL_DIS |
960 R128_GMC_WR_MSK_DIS ); 944 R128_GMC_WR_MSK_DIS);
961 945
962 OUT_RING( dev_priv->depth_pitch_offset_c ); 946 OUT_RING(dev_priv->depth_pitch_offset_c);
963 OUT_RING( buffer[i] ); 947 OUT_RING(buffer[i]);
964 948
965 OUT_RING( (x << 16) | y ); 949 OUT_RING((x << 16) | y);
966 OUT_RING( (1 << 16) | 1 ); 950 OUT_RING((1 << 16) | 1);
967 951
968 ADVANCE_RING(); 952 ADVANCE_RING();
969 } 953 }
970 } 954 }
971 955
972 drm_free( mask, mask_size, DRM_MEM_BUFS ); 956 drm_free(mask, mask_size, DRM_MEM_BUFS);
973 } else { 957 } else {
974 for ( i = 0 ; i < count ; i++, x++ ) { 958 for (i = 0; i < count; i++, x++) {
975 BEGIN_RING( 6 ); 959 BEGIN_RING(6);
976 960
977 OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); 961 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
978 OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | 962 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
979 R128_GMC_BRUSH_SOLID_COLOR | 963 R128_GMC_BRUSH_SOLID_COLOR |
980 (dev_priv->depth_fmt << 8) | 964 (dev_priv->depth_fmt << 8) |
981 R128_GMC_SRC_DATATYPE_COLOR | 965 R128_GMC_SRC_DATATYPE_COLOR |
982 R128_ROP3_P | 966 R128_ROP3_P |
983 R128_GMC_CLR_CMP_CNTL_DIS | 967 R128_GMC_CLR_CMP_CNTL_DIS |
984 R128_GMC_WR_MSK_DIS ); 968 R128_GMC_WR_MSK_DIS);
985 969
986 OUT_RING( dev_priv->depth_pitch_offset_c ); 970 OUT_RING(dev_priv->depth_pitch_offset_c);
987 OUT_RING( buffer[i] ); 971 OUT_RING(buffer[i]);
988 972
989 OUT_RING( (x << 16) | y ); 973 OUT_RING((x << 16) | y);
990 OUT_RING( (1 << 16) | 1 ); 974 OUT_RING((1 << 16) | 1);
991 975
992 ADVANCE_RING(); 976 ADVANCE_RING();
993 } 977 }
994 } 978 }
995 979
996 drm_free( buffer, buffer_size, DRM_MEM_BUFS ); 980 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
997 981
998 return 0; 982 return 0;
999} 983}
1000 984
1001static int r128_cce_dispatch_write_pixels( drm_device_t *dev, 985static int r128_cce_dispatch_write_pixels(drm_device_t * dev,
1002 drm_r128_depth_t *depth ) 986 drm_r128_depth_t * depth)
1003{ 987{
1004 drm_r128_private_t *dev_priv = dev->dev_private; 988 drm_r128_private_t *dev_priv = dev->dev_private;
1005 int count, *x, *y; 989 int count, *x, *y;
@@ -1007,7 +991,7 @@ static int r128_cce_dispatch_write_pixels( drm_device_t *dev,
1007 u8 *mask; 991 u8 *mask;
1008 int i, xbuf_size, ybuf_size, buffer_size, mask_size; 992 int i, xbuf_size, ybuf_size, buffer_size, mask_size;
1009 RING_LOCALS; 993 RING_LOCALS;
1010 DRM_DEBUG( "\n" ); 994 DRM_DEBUG("\n");
1011 995
1012 count = depth->n; 996 count = depth->n;
1013 if (count > 4096 || count <= 0) 997 if (count > 4096 || count <= 0)
@@ -1015,270 +999,266 @@ static int r128_cce_dispatch_write_pixels( drm_device_t *dev,
1015 999
1016 xbuf_size = count * sizeof(*x); 1000 xbuf_size = count * sizeof(*x);
1017 ybuf_size = count * sizeof(*y); 1001 ybuf_size = count * sizeof(*y);
1018 x = drm_alloc( xbuf_size, DRM_MEM_BUFS ); 1002 x = drm_alloc(xbuf_size, DRM_MEM_BUFS);
1019 if ( x == NULL ) { 1003 if (x == NULL) {
1020 return DRM_ERR(ENOMEM); 1004 return DRM_ERR(ENOMEM);
1021 } 1005 }
1022 y = drm_alloc( ybuf_size, DRM_MEM_BUFS ); 1006 y = drm_alloc(ybuf_size, DRM_MEM_BUFS);
1023 if ( y == NULL ) { 1007 if (y == NULL) {
1024 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1008 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1025 return DRM_ERR(ENOMEM); 1009 return DRM_ERR(ENOMEM);
1026 } 1010 }
1027 if ( DRM_COPY_FROM_USER( x, depth->x, xbuf_size ) ) { 1011 if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) {
1028 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1012 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1029 drm_free( y, ybuf_size, DRM_MEM_BUFS ); 1013 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1030 return DRM_ERR(EFAULT); 1014 return DRM_ERR(EFAULT);
1031 } 1015 }
1032 if ( DRM_COPY_FROM_USER( y, depth->y, xbuf_size ) ) { 1016 if (DRM_COPY_FROM_USER(y, depth->y, xbuf_size)) {
1033 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1017 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1034 drm_free( y, ybuf_size, DRM_MEM_BUFS ); 1018 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1035 return DRM_ERR(EFAULT); 1019 return DRM_ERR(EFAULT);
1036 } 1020 }
1037 1021
1038 buffer_size = depth->n * sizeof(u32); 1022 buffer_size = depth->n * sizeof(u32);
1039 buffer = drm_alloc( buffer_size, DRM_MEM_BUFS ); 1023 buffer = drm_alloc(buffer_size, DRM_MEM_BUFS);
1040 if ( buffer == NULL ) { 1024 if (buffer == NULL) {
1041 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1025 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1042 drm_free( y, ybuf_size, DRM_MEM_BUFS ); 1026 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1043 return DRM_ERR(ENOMEM); 1027 return DRM_ERR(ENOMEM);
1044 } 1028 }
1045 if ( DRM_COPY_FROM_USER( buffer, depth->buffer, buffer_size ) ) { 1029 if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) {
1046 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1030 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1047 drm_free( y, ybuf_size, DRM_MEM_BUFS ); 1031 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1048 drm_free( buffer, buffer_size, DRM_MEM_BUFS ); 1032 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1049 return DRM_ERR(EFAULT); 1033 return DRM_ERR(EFAULT);
1050 } 1034 }
1051 1035
1052 if ( depth->mask ) { 1036 if (depth->mask) {
1053 mask_size = depth->n * sizeof(u8); 1037 mask_size = depth->n * sizeof(u8);
1054 mask = drm_alloc( mask_size, DRM_MEM_BUFS ); 1038 mask = drm_alloc(mask_size, DRM_MEM_BUFS);
1055 if ( mask == NULL ) { 1039 if (mask == NULL) {
1056 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1040 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1057 drm_free( y, ybuf_size, DRM_MEM_BUFS ); 1041 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1058 drm_free( buffer, buffer_size, DRM_MEM_BUFS ); 1042 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1059 return DRM_ERR(ENOMEM); 1043 return DRM_ERR(ENOMEM);
1060 } 1044 }
1061 if ( DRM_COPY_FROM_USER( mask, depth->mask, mask_size ) ) { 1045 if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) {
1062 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1046 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1063 drm_free( y, ybuf_size, DRM_MEM_BUFS ); 1047 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1064 drm_free( buffer, buffer_size, DRM_MEM_BUFS ); 1048 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1065 drm_free( mask, mask_size, DRM_MEM_BUFS ); 1049 drm_free(mask, mask_size, DRM_MEM_BUFS);
1066 return DRM_ERR(EFAULT); 1050 return DRM_ERR(EFAULT);
1067 } 1051 }
1068 1052
1069 for ( i = 0 ; i < count ; i++ ) { 1053 for (i = 0; i < count; i++) {
1070 if ( mask[i] ) { 1054 if (mask[i]) {
1071 BEGIN_RING( 6 ); 1055 BEGIN_RING(6);
1072 1056
1073 OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); 1057 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
1074 OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | 1058 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
1075 R128_GMC_BRUSH_SOLID_COLOR | 1059 R128_GMC_BRUSH_SOLID_COLOR |
1076 (dev_priv->depth_fmt << 8) | 1060 (dev_priv->depth_fmt << 8) |
1077 R128_GMC_SRC_DATATYPE_COLOR | 1061 R128_GMC_SRC_DATATYPE_COLOR |
1078 R128_ROP3_P | 1062 R128_ROP3_P |
1079 R128_GMC_CLR_CMP_CNTL_DIS | 1063 R128_GMC_CLR_CMP_CNTL_DIS |
1080 R128_GMC_WR_MSK_DIS ); 1064 R128_GMC_WR_MSK_DIS);
1081 1065
1082 OUT_RING( dev_priv->depth_pitch_offset_c ); 1066 OUT_RING(dev_priv->depth_pitch_offset_c);
1083 OUT_RING( buffer[i] ); 1067 OUT_RING(buffer[i]);
1084 1068
1085 OUT_RING( (x[i] << 16) | y[i] ); 1069 OUT_RING((x[i] << 16) | y[i]);
1086 OUT_RING( (1 << 16) | 1 ); 1070 OUT_RING((1 << 16) | 1);
1087 1071
1088 ADVANCE_RING(); 1072 ADVANCE_RING();
1089 } 1073 }
1090 } 1074 }
1091 1075
1092 drm_free( mask, mask_size, DRM_MEM_BUFS ); 1076 drm_free(mask, mask_size, DRM_MEM_BUFS);
1093 } else { 1077 } else {
1094 for ( i = 0 ; i < count ; i++ ) { 1078 for (i = 0; i < count; i++) {
1095 BEGIN_RING( 6 ); 1079 BEGIN_RING(6);
1096 1080
1097 OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); 1081 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
1098 OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | 1082 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
1099 R128_GMC_BRUSH_SOLID_COLOR | 1083 R128_GMC_BRUSH_SOLID_COLOR |
1100 (dev_priv->depth_fmt << 8) | 1084 (dev_priv->depth_fmt << 8) |
1101 R128_GMC_SRC_DATATYPE_COLOR | 1085 R128_GMC_SRC_DATATYPE_COLOR |
1102 R128_ROP3_P | 1086 R128_ROP3_P |
1103 R128_GMC_CLR_CMP_CNTL_DIS | 1087 R128_GMC_CLR_CMP_CNTL_DIS |
1104 R128_GMC_WR_MSK_DIS ); 1088 R128_GMC_WR_MSK_DIS);
1105 1089
1106 OUT_RING( dev_priv->depth_pitch_offset_c ); 1090 OUT_RING(dev_priv->depth_pitch_offset_c);
1107 OUT_RING( buffer[i] ); 1091 OUT_RING(buffer[i]);
1108 1092
1109 OUT_RING( (x[i] << 16) | y[i] ); 1093 OUT_RING((x[i] << 16) | y[i]);
1110 OUT_RING( (1 << 16) | 1 ); 1094 OUT_RING((1 << 16) | 1);
1111 1095
1112 ADVANCE_RING(); 1096 ADVANCE_RING();
1113 } 1097 }
1114 } 1098 }
1115 1099
1116 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1100 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1117 drm_free( y, ybuf_size, DRM_MEM_BUFS ); 1101 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1118 drm_free( buffer, buffer_size, DRM_MEM_BUFS ); 1102 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1119 1103
1120 return 0; 1104 return 0;
1121} 1105}
1122 1106
1123static int r128_cce_dispatch_read_span( drm_device_t *dev, 1107static int r128_cce_dispatch_read_span(drm_device_t * dev,
1124 drm_r128_depth_t *depth ) 1108 drm_r128_depth_t * depth)
1125{ 1109{
1126 drm_r128_private_t *dev_priv = dev->dev_private; 1110 drm_r128_private_t *dev_priv = dev->dev_private;
1127 int count, x, y; 1111 int count, x, y;
1128 RING_LOCALS; 1112 RING_LOCALS;
1129 DRM_DEBUG( "\n" ); 1113 DRM_DEBUG("\n");
1130 1114
1131 count = depth->n; 1115 count = depth->n;
1132 if (count > 4096 || count <= 0) 1116 if (count > 4096 || count <= 0)
1133 return DRM_ERR(EMSGSIZE); 1117 return DRM_ERR(EMSGSIZE);
1134 1118
1135 if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) { 1119 if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) {
1136 return DRM_ERR(EFAULT); 1120 return DRM_ERR(EFAULT);
1137 } 1121 }
1138 if ( DRM_COPY_FROM_USER( &y, depth->y, sizeof(y) ) ) { 1122 if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) {
1139 return DRM_ERR(EFAULT); 1123 return DRM_ERR(EFAULT);
1140 } 1124 }
1141 1125
1142 BEGIN_RING( 7 ); 1126 BEGIN_RING(7);
1143 1127
1144 OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); 1128 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
1145 OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | 1129 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
1146 R128_GMC_DST_PITCH_OFFSET_CNTL | 1130 R128_GMC_DST_PITCH_OFFSET_CNTL |
1147 R128_GMC_BRUSH_NONE | 1131 R128_GMC_BRUSH_NONE |
1148 (dev_priv->depth_fmt << 8) | 1132 (dev_priv->depth_fmt << 8) |
1149 R128_GMC_SRC_DATATYPE_COLOR | 1133 R128_GMC_SRC_DATATYPE_COLOR |
1150 R128_ROP3_S | 1134 R128_ROP3_S |
1151 R128_DP_SRC_SOURCE_MEMORY | 1135 R128_DP_SRC_SOURCE_MEMORY |
1152 R128_GMC_CLR_CMP_CNTL_DIS | 1136 R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS);
1153 R128_GMC_WR_MSK_DIS );
1154 1137
1155 OUT_RING( dev_priv->depth_pitch_offset_c ); 1138 OUT_RING(dev_priv->depth_pitch_offset_c);
1156 OUT_RING( dev_priv->span_pitch_offset_c ); 1139 OUT_RING(dev_priv->span_pitch_offset_c);
1157 1140
1158 OUT_RING( (x << 16) | y ); 1141 OUT_RING((x << 16) | y);
1159 OUT_RING( (0 << 16) | 0 ); 1142 OUT_RING((0 << 16) | 0);
1160 OUT_RING( (count << 16) | 1 ); 1143 OUT_RING((count << 16) | 1);
1161 1144
1162 ADVANCE_RING(); 1145 ADVANCE_RING();
1163 1146
1164 return 0; 1147 return 0;
1165} 1148}
1166 1149
1167static int r128_cce_dispatch_read_pixels( drm_device_t *dev, 1150static int r128_cce_dispatch_read_pixels(drm_device_t * dev,
1168 drm_r128_depth_t *depth ) 1151 drm_r128_depth_t * depth)
1169{ 1152{
1170 drm_r128_private_t *dev_priv = dev->dev_private; 1153 drm_r128_private_t *dev_priv = dev->dev_private;
1171 int count, *x, *y; 1154 int count, *x, *y;
1172 int i, xbuf_size, ybuf_size; 1155 int i, xbuf_size, ybuf_size;
1173 RING_LOCALS; 1156 RING_LOCALS;
1174 DRM_DEBUG( "%s\n", __FUNCTION__ ); 1157 DRM_DEBUG("%s\n", __FUNCTION__);
1175 1158
1176 count = depth->n; 1159 count = depth->n;
1177 if (count > 4096 || count <= 0) 1160 if (count > 4096 || count <= 0)
1178 return DRM_ERR(EMSGSIZE); 1161 return DRM_ERR(EMSGSIZE);
1179 1162
1180 if ( count > dev_priv->depth_pitch ) { 1163 if (count > dev_priv->depth_pitch) {
1181 count = dev_priv->depth_pitch; 1164 count = dev_priv->depth_pitch;
1182 } 1165 }
1183 1166
1184 xbuf_size = count * sizeof(*x); 1167 xbuf_size = count * sizeof(*x);
1185 ybuf_size = count * sizeof(*y); 1168 ybuf_size = count * sizeof(*y);
1186 x = drm_alloc( xbuf_size, DRM_MEM_BUFS ); 1169 x = drm_alloc(xbuf_size, DRM_MEM_BUFS);
1187 if ( x == NULL ) { 1170 if (x == NULL) {
1188 return DRM_ERR(ENOMEM); 1171 return DRM_ERR(ENOMEM);
1189 } 1172 }
1190 y = drm_alloc( ybuf_size, DRM_MEM_BUFS ); 1173 y = drm_alloc(ybuf_size, DRM_MEM_BUFS);
1191 if ( y == NULL ) { 1174 if (y == NULL) {
1192 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1175 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1193 return DRM_ERR(ENOMEM); 1176 return DRM_ERR(ENOMEM);
1194 } 1177 }
1195 if ( DRM_COPY_FROM_USER( x, depth->x, xbuf_size ) ) { 1178 if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) {
1196 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1179 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1197 drm_free( y, ybuf_size, DRM_MEM_BUFS ); 1180 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1198 return DRM_ERR(EFAULT); 1181 return DRM_ERR(EFAULT);
1199 } 1182 }
1200 if ( DRM_COPY_FROM_USER( y, depth->y, ybuf_size ) ) { 1183 if (DRM_COPY_FROM_USER(y, depth->y, ybuf_size)) {
1201 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1184 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1202 drm_free( y, ybuf_size, DRM_MEM_BUFS ); 1185 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1203 return DRM_ERR(EFAULT); 1186 return DRM_ERR(EFAULT);
1204 } 1187 }
1205 1188
1206 for ( i = 0 ; i < count ; i++ ) { 1189 for (i = 0; i < count; i++) {
1207 BEGIN_RING( 7 ); 1190 BEGIN_RING(7);
1208 1191
1209 OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); 1192 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
1210 OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | 1193 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
1211 R128_GMC_DST_PITCH_OFFSET_CNTL | 1194 R128_GMC_DST_PITCH_OFFSET_CNTL |
1212 R128_GMC_BRUSH_NONE | 1195 R128_GMC_BRUSH_NONE |
1213 (dev_priv->depth_fmt << 8) | 1196 (dev_priv->depth_fmt << 8) |
1214 R128_GMC_SRC_DATATYPE_COLOR | 1197 R128_GMC_SRC_DATATYPE_COLOR |
1215 R128_ROP3_S | 1198 R128_ROP3_S |
1216 R128_DP_SRC_SOURCE_MEMORY | 1199 R128_DP_SRC_SOURCE_MEMORY |
1217 R128_GMC_CLR_CMP_CNTL_DIS | 1200 R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS);
1218 R128_GMC_WR_MSK_DIS );
1219 1201
1220 OUT_RING( dev_priv->depth_pitch_offset_c ); 1202 OUT_RING(dev_priv->depth_pitch_offset_c);
1221 OUT_RING( dev_priv->span_pitch_offset_c ); 1203 OUT_RING(dev_priv->span_pitch_offset_c);
1222 1204
1223 OUT_RING( (x[i] << 16) | y[i] ); 1205 OUT_RING((x[i] << 16) | y[i]);
1224 OUT_RING( (i << 16) | 0 ); 1206 OUT_RING((i << 16) | 0);
1225 OUT_RING( (1 << 16) | 1 ); 1207 OUT_RING((1 << 16) | 1);
1226 1208
1227 ADVANCE_RING(); 1209 ADVANCE_RING();
1228 } 1210 }
1229 1211
1230 drm_free( x, xbuf_size, DRM_MEM_BUFS ); 1212 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1231 drm_free( y, ybuf_size, DRM_MEM_BUFS ); 1213 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1232 1214
1233 return 0; 1215 return 0;
1234} 1216}
1235 1217
1236
1237/* ================================================================ 1218/* ================================================================
1238 * Polygon stipple 1219 * Polygon stipple
1239 */ 1220 */
1240 1221
1241static void r128_cce_dispatch_stipple( drm_device_t *dev, u32 *stipple ) 1222static void r128_cce_dispatch_stipple(drm_device_t * dev, u32 * stipple)
1242{ 1223{
1243 drm_r128_private_t *dev_priv = dev->dev_private; 1224 drm_r128_private_t *dev_priv = dev->dev_private;
1244 int i; 1225 int i;
1245 RING_LOCALS; 1226 RING_LOCALS;
1246 DRM_DEBUG( "%s\n", __FUNCTION__ ); 1227 DRM_DEBUG("%s\n", __FUNCTION__);
1247 1228
1248 BEGIN_RING( 33 ); 1229 BEGIN_RING(33);
1249 1230
1250 OUT_RING( CCE_PACKET0( R128_BRUSH_DATA0, 31 ) ); 1231 OUT_RING(CCE_PACKET0(R128_BRUSH_DATA0, 31));
1251 for ( i = 0 ; i < 32 ; i++ ) { 1232 for (i = 0; i < 32; i++) {
1252 OUT_RING( stipple[i] ); 1233 OUT_RING(stipple[i]);
1253 } 1234 }
1254 1235
1255 ADVANCE_RING(); 1236 ADVANCE_RING();
1256} 1237}
1257 1238
1258
1259/* ================================================================ 1239/* ================================================================
1260 * IOCTL functions 1240 * IOCTL functions
1261 */ 1241 */
1262 1242
1263static int r128_cce_clear( DRM_IOCTL_ARGS ) 1243static int r128_cce_clear(DRM_IOCTL_ARGS)
1264{ 1244{
1265 DRM_DEVICE; 1245 DRM_DEVICE;
1266 drm_r128_private_t *dev_priv = dev->dev_private; 1246 drm_r128_private_t *dev_priv = dev->dev_private;
1267 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 1247 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
1268 drm_r128_clear_t clear; 1248 drm_r128_clear_t clear;
1269 DRM_DEBUG( "\n" ); 1249 DRM_DEBUG("\n");
1270 1250
1271 LOCK_TEST_WITH_RETURN( dev, filp ); 1251 LOCK_TEST_WITH_RETURN(dev, filp);
1272 1252
1273 DRM_COPY_FROM_USER_IOCTL( clear, (drm_r128_clear_t __user *) data, 1253 DRM_COPY_FROM_USER_IOCTL(clear, (drm_r128_clear_t __user *) data,
1274 sizeof(clear) ); 1254 sizeof(clear));
1275 1255
1276 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 1256 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1277 1257
1278 if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS ) 1258 if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
1279 sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; 1259 sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
1280 1260
1281 r128_cce_dispatch_clear( dev, &clear ); 1261 r128_cce_dispatch_clear(dev, &clear);
1282 COMMIT_RING(); 1262 COMMIT_RING();
1283 1263
1284 /* Make sure we restore the 3D state next time. 1264 /* Make sure we restore the 3D state next time.
@@ -1288,17 +1268,17 @@ static int r128_cce_clear( DRM_IOCTL_ARGS )
1288 return 0; 1268 return 0;
1289} 1269}
1290 1270
1291static int r128_do_init_pageflip( drm_device_t *dev ) 1271static int r128_do_init_pageflip(drm_device_t * dev)
1292{ 1272{
1293 drm_r128_private_t *dev_priv = dev->dev_private; 1273 drm_r128_private_t *dev_priv = dev->dev_private;
1294 DRM_DEBUG( "\n" ); 1274 DRM_DEBUG("\n");
1295 1275
1296 dev_priv->crtc_offset = R128_READ( R128_CRTC_OFFSET ); 1276 dev_priv->crtc_offset = R128_READ(R128_CRTC_OFFSET);
1297 dev_priv->crtc_offset_cntl = R128_READ( R128_CRTC_OFFSET_CNTL ); 1277 dev_priv->crtc_offset_cntl = R128_READ(R128_CRTC_OFFSET_CNTL);
1298 1278
1299 R128_WRITE( R128_CRTC_OFFSET, dev_priv->front_offset ); 1279 R128_WRITE(R128_CRTC_OFFSET, dev_priv->front_offset);
1300 R128_WRITE( R128_CRTC_OFFSET_CNTL, 1280 R128_WRITE(R128_CRTC_OFFSET_CNTL,
1301 dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL ); 1281 dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL);
1302 1282
1303 dev_priv->page_flipping = 1; 1283 dev_priv->page_flipping = 1;
1304 dev_priv->current_page = 0; 1284 dev_priv->current_page = 0;
@@ -1307,16 +1287,16 @@ static int r128_do_init_pageflip( drm_device_t *dev )
1307 return 0; 1287 return 0;
1308} 1288}
1309 1289
1310static int r128_do_cleanup_pageflip( drm_device_t *dev ) 1290static int r128_do_cleanup_pageflip(drm_device_t * dev)
1311{ 1291{
1312 drm_r128_private_t *dev_priv = dev->dev_private; 1292 drm_r128_private_t *dev_priv = dev->dev_private;
1313 DRM_DEBUG( "\n" ); 1293 DRM_DEBUG("\n");
1314 1294
1315 R128_WRITE( R128_CRTC_OFFSET, dev_priv->crtc_offset ); 1295 R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset);
1316 R128_WRITE( R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl ); 1296 R128_WRITE(R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl);
1317 1297
1318 if (dev_priv->current_page != 0) { 1298 if (dev_priv->current_page != 0) {
1319 r128_cce_dispatch_flip( dev ); 1299 r128_cce_dispatch_flip(dev);
1320 COMMIT_RING(); 1300 COMMIT_RING();
1321 } 1301 }
1322 1302
@@ -1325,43 +1305,43 @@ static int r128_do_cleanup_pageflip( drm_device_t *dev )
1325} 1305}
1326 1306
1327/* Swapping and flipping are different operations, need different ioctls. 1307/* Swapping and flipping are different operations, need different ioctls.
1328 * They can & should be intermixed to support multiple 3d windows. 1308 * They can & should be intermixed to support multiple 3d windows.
1329 */ 1309 */
1330 1310
1331static int r128_cce_flip( DRM_IOCTL_ARGS ) 1311static int r128_cce_flip(DRM_IOCTL_ARGS)
1332{ 1312{
1333 DRM_DEVICE; 1313 DRM_DEVICE;
1334 drm_r128_private_t *dev_priv = dev->dev_private; 1314 drm_r128_private_t *dev_priv = dev->dev_private;
1335 DRM_DEBUG( "%s\n", __FUNCTION__ ); 1315 DRM_DEBUG("%s\n", __FUNCTION__);
1336 1316
1337 LOCK_TEST_WITH_RETURN( dev, filp ); 1317 LOCK_TEST_WITH_RETURN(dev, filp);
1338 1318
1339 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 1319 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1340 1320
1341 if (!dev_priv->page_flipping) 1321 if (!dev_priv->page_flipping)
1342 r128_do_init_pageflip( dev ); 1322 r128_do_init_pageflip(dev);
1343 1323
1344 r128_cce_dispatch_flip( dev ); 1324 r128_cce_dispatch_flip(dev);
1345 1325
1346 COMMIT_RING(); 1326 COMMIT_RING();
1347 return 0; 1327 return 0;
1348} 1328}
1349 1329
1350static int r128_cce_swap( DRM_IOCTL_ARGS ) 1330static int r128_cce_swap(DRM_IOCTL_ARGS)
1351{ 1331{
1352 DRM_DEVICE; 1332 DRM_DEVICE;
1353 drm_r128_private_t *dev_priv = dev->dev_private; 1333 drm_r128_private_t *dev_priv = dev->dev_private;
1354 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; 1334 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
1355 DRM_DEBUG( "%s\n", __FUNCTION__ ); 1335 DRM_DEBUG("%s\n", __FUNCTION__);
1356 1336
1357 LOCK_TEST_WITH_RETURN( dev, filp ); 1337 LOCK_TEST_WITH_RETURN(dev, filp);
1358 1338
1359 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 1339 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1360 1340
1361 if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS ) 1341 if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
1362 sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; 1342 sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
1363 1343
1364 r128_cce_dispatch_swap( dev ); 1344 r128_cce_dispatch_swap(dev);
1365 dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT | 1345 dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT |
1366 R128_UPLOAD_MASKS); 1346 R128_UPLOAD_MASKS);
1367 1347
@@ -1369,7 +1349,7 @@ static int r128_cce_swap( DRM_IOCTL_ARGS )
1369 return 0; 1349 return 0;
1370} 1350}
1371 1351
1372static int r128_cce_vertex( DRM_IOCTL_ARGS ) 1352static int r128_cce_vertex(DRM_IOCTL_ARGS)
1373{ 1353{
1374 DRM_DEVICE; 1354 DRM_DEVICE;
1375 drm_r128_private_t *dev_priv = dev->dev_private; 1355 drm_r128_private_t *dev_priv = dev->dev_private;
@@ -1378,44 +1358,43 @@ static int r128_cce_vertex( DRM_IOCTL_ARGS )
1378 drm_r128_buf_priv_t *buf_priv; 1358 drm_r128_buf_priv_t *buf_priv;
1379 drm_r128_vertex_t vertex; 1359 drm_r128_vertex_t vertex;
1380 1360
1381 LOCK_TEST_WITH_RETURN( dev, filp ); 1361 LOCK_TEST_WITH_RETURN(dev, filp);
1382 1362
1383 if ( !dev_priv ) { 1363 if (!dev_priv) {
1384 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 1364 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1385 return DRM_ERR(EINVAL); 1365 return DRM_ERR(EINVAL);
1386 } 1366 }
1387 1367
1388 DRM_COPY_FROM_USER_IOCTL( vertex, (drm_r128_vertex_t __user *) data, 1368 DRM_COPY_FROM_USER_IOCTL(vertex, (drm_r128_vertex_t __user *) data,
1389 sizeof(vertex) ); 1369 sizeof(vertex));
1390 1370
1391 DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n", 1371 DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
1392 DRM_CURRENTPID, 1372 DRM_CURRENTPID, vertex.idx, vertex.count, vertex.discard);
1393 vertex.idx, vertex.count, vertex.discard );
1394 1373
1395 if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { 1374 if (vertex.idx < 0 || vertex.idx >= dma->buf_count) {
1396 DRM_ERROR( "buffer index %d (of %d max)\n", 1375 DRM_ERROR("buffer index %d (of %d max)\n",
1397 vertex.idx, dma->buf_count - 1 ); 1376 vertex.idx, dma->buf_count - 1);
1398 return DRM_ERR(EINVAL); 1377 return DRM_ERR(EINVAL);
1399 } 1378 }
1400 if ( vertex.prim < 0 || 1379 if (vertex.prim < 0 ||
1401 vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) { 1380 vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) {
1402 DRM_ERROR( "buffer prim %d\n", vertex.prim ); 1381 DRM_ERROR("buffer prim %d\n", vertex.prim);
1403 return DRM_ERR(EINVAL); 1382 return DRM_ERR(EINVAL);
1404 } 1383 }
1405 1384
1406 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 1385 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1407 VB_AGE_TEST_WITH_RETURN( dev_priv ); 1386 VB_AGE_TEST_WITH_RETURN(dev_priv);
1408 1387
1409 buf = dma->buflist[vertex.idx]; 1388 buf = dma->buflist[vertex.idx];
1410 buf_priv = buf->dev_private; 1389 buf_priv = buf->dev_private;
1411 1390
1412 if ( buf->filp != filp ) { 1391 if (buf->filp != filp) {
1413 DRM_ERROR( "process %d using buffer owned by %p\n", 1392 DRM_ERROR("process %d using buffer owned by %p\n",
1414 DRM_CURRENTPID, buf->filp ); 1393 DRM_CURRENTPID, buf->filp);
1415 return DRM_ERR(EINVAL); 1394 return DRM_ERR(EINVAL);
1416 } 1395 }
1417 if ( buf->pending ) { 1396 if (buf->pending) {
1418 DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); 1397 DRM_ERROR("sending pending buffer %d\n", vertex.idx);
1419 return DRM_ERR(EINVAL); 1398 return DRM_ERR(EINVAL);
1420 } 1399 }
1421 1400
@@ -1423,13 +1402,13 @@ static int r128_cce_vertex( DRM_IOCTL_ARGS )
1423 buf_priv->prim = vertex.prim; 1402 buf_priv->prim = vertex.prim;
1424 buf_priv->discard = vertex.discard; 1403 buf_priv->discard = vertex.discard;
1425 1404
1426 r128_cce_dispatch_vertex( dev, buf ); 1405 r128_cce_dispatch_vertex(dev, buf);
1427 1406
1428 COMMIT_RING(); 1407 COMMIT_RING();
1429 return 0; 1408 return 0;
1430} 1409}
1431 1410
1432static int r128_cce_indices( DRM_IOCTL_ARGS ) 1411static int r128_cce_indices(DRM_IOCTL_ARGS)
1433{ 1412{
1434 DRM_DEVICE; 1413 DRM_DEVICE;
1435 drm_r128_private_t *dev_priv = dev->dev_private; 1414 drm_r128_private_t *dev_priv = dev->dev_private;
@@ -1439,55 +1418,54 @@ static int r128_cce_indices( DRM_IOCTL_ARGS )
1439 drm_r128_indices_t elts; 1418 drm_r128_indices_t elts;
1440 int count; 1419 int count;
1441 1420
1442 LOCK_TEST_WITH_RETURN( dev, filp ); 1421 LOCK_TEST_WITH_RETURN(dev, filp);
1443 1422
1444 if ( !dev_priv ) { 1423 if (!dev_priv) {
1445 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 1424 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1446 return DRM_ERR(EINVAL); 1425 return DRM_ERR(EINVAL);
1447 } 1426 }
1448 1427
1449 DRM_COPY_FROM_USER_IOCTL( elts, (drm_r128_indices_t __user *) data, 1428 DRM_COPY_FROM_USER_IOCTL(elts, (drm_r128_indices_t __user *) data,
1450 sizeof(elts) ); 1429 sizeof(elts));
1451 1430
1452 DRM_DEBUG( "pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID, 1431 DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID,
1453 elts.idx, elts.start, elts.end, elts.discard ); 1432 elts.idx, elts.start, elts.end, elts.discard);
1454 1433
1455 if ( elts.idx < 0 || elts.idx >= dma->buf_count ) { 1434 if (elts.idx < 0 || elts.idx >= dma->buf_count) {
1456 DRM_ERROR( "buffer index %d (of %d max)\n", 1435 DRM_ERROR("buffer index %d (of %d max)\n",
1457 elts.idx, dma->buf_count - 1 ); 1436 elts.idx, dma->buf_count - 1);
1458 return DRM_ERR(EINVAL); 1437 return DRM_ERR(EINVAL);
1459 } 1438 }
1460 if ( elts.prim < 0 || 1439 if (elts.prim < 0 || elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) {
1461 elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) { 1440 DRM_ERROR("buffer prim %d\n", elts.prim);
1462 DRM_ERROR( "buffer prim %d\n", elts.prim );
1463 return DRM_ERR(EINVAL); 1441 return DRM_ERR(EINVAL);
1464 } 1442 }
1465 1443
1466 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 1444 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1467 VB_AGE_TEST_WITH_RETURN( dev_priv ); 1445 VB_AGE_TEST_WITH_RETURN(dev_priv);
1468 1446
1469 buf = dma->buflist[elts.idx]; 1447 buf = dma->buflist[elts.idx];
1470 buf_priv = buf->dev_private; 1448 buf_priv = buf->dev_private;
1471 1449
1472 if ( buf->filp != filp ) { 1450 if (buf->filp != filp) {
1473 DRM_ERROR( "process %d using buffer owned by %p\n", 1451 DRM_ERROR("process %d using buffer owned by %p\n",
1474 DRM_CURRENTPID, buf->filp ); 1452 DRM_CURRENTPID, buf->filp);
1475 return DRM_ERR(EINVAL); 1453 return DRM_ERR(EINVAL);
1476 } 1454 }
1477 if ( buf->pending ) { 1455 if (buf->pending) {
1478 DRM_ERROR( "sending pending buffer %d\n", elts.idx ); 1456 DRM_ERROR("sending pending buffer %d\n", elts.idx);
1479 return DRM_ERR(EINVAL); 1457 return DRM_ERR(EINVAL);
1480 } 1458 }
1481 1459
1482 count = (elts.end - elts.start) / sizeof(u16); 1460 count = (elts.end - elts.start) / sizeof(u16);
1483 elts.start -= R128_INDEX_PRIM_OFFSET; 1461 elts.start -= R128_INDEX_PRIM_OFFSET;
1484 1462
1485 if ( elts.start & 0x7 ) { 1463 if (elts.start & 0x7) {
1486 DRM_ERROR( "misaligned buffer 0x%x\n", elts.start ); 1464 DRM_ERROR("misaligned buffer 0x%x\n", elts.start);
1487 return DRM_ERR(EINVAL); 1465 return DRM_ERR(EINVAL);
1488 } 1466 }
1489 if ( elts.start < buf->used ) { 1467 if (elts.start < buf->used) {
1490 DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used ); 1468 DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used);
1491 return DRM_ERR(EINVAL); 1469 return DRM_ERR(EINVAL);
1492 } 1470 }
1493 1471
@@ -1495,13 +1473,13 @@ static int r128_cce_indices( DRM_IOCTL_ARGS )
1495 buf_priv->prim = elts.prim; 1473 buf_priv->prim = elts.prim;
1496 buf_priv->discard = elts.discard; 1474 buf_priv->discard = elts.discard;
1497 1475
1498 r128_cce_dispatch_indices( dev, buf, elts.start, elts.end, count ); 1476 r128_cce_dispatch_indices(dev, buf, elts.start, elts.end, count);
1499 1477
1500 COMMIT_RING(); 1478 COMMIT_RING();
1501 return 0; 1479 return 0;
1502} 1480}
1503 1481
1504static int r128_cce_blit( DRM_IOCTL_ARGS ) 1482static int r128_cce_blit(DRM_IOCTL_ARGS)
1505{ 1483{
1506 DRM_DEVICE; 1484 DRM_DEVICE;
1507 drm_device_dma_t *dma = dev->dma; 1485 drm_device_dma_t *dma = dev->dma;
@@ -1509,55 +1487,55 @@ static int r128_cce_blit( DRM_IOCTL_ARGS )
1509 drm_r128_blit_t blit; 1487 drm_r128_blit_t blit;
1510 int ret; 1488 int ret;
1511 1489
1512 LOCK_TEST_WITH_RETURN( dev, filp ); 1490 LOCK_TEST_WITH_RETURN(dev, filp);
1513 1491
1514 DRM_COPY_FROM_USER_IOCTL( blit, (drm_r128_blit_t __user *) data, 1492 DRM_COPY_FROM_USER_IOCTL(blit, (drm_r128_blit_t __user *) data,
1515 sizeof(blit) ); 1493 sizeof(blit));
1516 1494
1517 DRM_DEBUG( "pid=%d index=%d\n", DRM_CURRENTPID, blit.idx ); 1495 DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit.idx);
1518 1496
1519 if ( blit.idx < 0 || blit.idx >= dma->buf_count ) { 1497 if (blit.idx < 0 || blit.idx >= dma->buf_count) {
1520 DRM_ERROR( "buffer index %d (of %d max)\n", 1498 DRM_ERROR("buffer index %d (of %d max)\n",
1521 blit.idx, dma->buf_count - 1 ); 1499 blit.idx, dma->buf_count - 1);
1522 return DRM_ERR(EINVAL); 1500 return DRM_ERR(EINVAL);
1523 } 1501 }
1524 1502
1525 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 1503 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1526 VB_AGE_TEST_WITH_RETURN( dev_priv ); 1504 VB_AGE_TEST_WITH_RETURN(dev_priv);
1527 1505
1528 ret = r128_cce_dispatch_blit( filp, dev, &blit ); 1506 ret = r128_cce_dispatch_blit(filp, dev, &blit);
1529 1507
1530 COMMIT_RING(); 1508 COMMIT_RING();
1531 return ret; 1509 return ret;
1532} 1510}
1533 1511
1534static int r128_cce_depth( DRM_IOCTL_ARGS ) 1512static int r128_cce_depth(DRM_IOCTL_ARGS)
1535{ 1513{
1536 DRM_DEVICE; 1514 DRM_DEVICE;
1537 drm_r128_private_t *dev_priv = dev->dev_private; 1515 drm_r128_private_t *dev_priv = dev->dev_private;
1538 drm_r128_depth_t depth; 1516 drm_r128_depth_t depth;
1539 int ret; 1517 int ret;
1540 1518
1541 LOCK_TEST_WITH_RETURN( dev, filp ); 1519 LOCK_TEST_WITH_RETURN(dev, filp);
1542 1520
1543 DRM_COPY_FROM_USER_IOCTL( depth, (drm_r128_depth_t __user *) data, 1521 DRM_COPY_FROM_USER_IOCTL(depth, (drm_r128_depth_t __user *) data,
1544 sizeof(depth) ); 1522 sizeof(depth));
1545 1523
1546 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 1524 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1547 1525
1548 ret = DRM_ERR(EINVAL); 1526 ret = DRM_ERR(EINVAL);
1549 switch ( depth.func ) { 1527 switch (depth.func) {
1550 case R128_WRITE_SPAN: 1528 case R128_WRITE_SPAN:
1551 ret = r128_cce_dispatch_write_span( dev, &depth ); 1529 ret = r128_cce_dispatch_write_span(dev, &depth);
1552 break; 1530 break;
1553 case R128_WRITE_PIXELS: 1531 case R128_WRITE_PIXELS:
1554 ret = r128_cce_dispatch_write_pixels( dev, &depth ); 1532 ret = r128_cce_dispatch_write_pixels(dev, &depth);
1555 break; 1533 break;
1556 case R128_READ_SPAN: 1534 case R128_READ_SPAN:
1557 ret = r128_cce_dispatch_read_span( dev, &depth ); 1535 ret = r128_cce_dispatch_read_span(dev, &depth);
1558 break; 1536 break;
1559 case R128_READ_PIXELS: 1537 case R128_READ_PIXELS:
1560 ret = r128_cce_dispatch_read_pixels( dev, &depth ); 1538 ret = r128_cce_dispatch_read_pixels(dev, &depth);
1561 break; 1539 break;
1562 } 1540 }
1563 1541
@@ -1565,31 +1543,30 @@ static int r128_cce_depth( DRM_IOCTL_ARGS )
1565 return ret; 1543 return ret;
1566} 1544}
1567 1545
1568static int r128_cce_stipple( DRM_IOCTL_ARGS ) 1546static int r128_cce_stipple(DRM_IOCTL_ARGS)
1569{ 1547{
1570 DRM_DEVICE; 1548 DRM_DEVICE;
1571 drm_r128_private_t *dev_priv = dev->dev_private; 1549 drm_r128_private_t *dev_priv = dev->dev_private;
1572 drm_r128_stipple_t stipple; 1550 drm_r128_stipple_t stipple;
1573 u32 mask[32]; 1551 u32 mask[32];
1574 1552
1575 LOCK_TEST_WITH_RETURN( dev, filp ); 1553 LOCK_TEST_WITH_RETURN(dev, filp);
1576 1554
1577 DRM_COPY_FROM_USER_IOCTL( stipple, (drm_r128_stipple_t __user *) data, 1555 DRM_COPY_FROM_USER_IOCTL(stipple, (drm_r128_stipple_t __user *) data,
1578 sizeof(stipple) ); 1556 sizeof(stipple));
1579 1557
1580 if ( DRM_COPY_FROM_USER( &mask, stipple.mask, 1558 if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32)))
1581 32 * sizeof(u32) ) ) 1559 return DRM_ERR(EFAULT);
1582 return DRM_ERR( EFAULT );
1583 1560
1584 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 1561 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1585 1562
1586 r128_cce_dispatch_stipple( dev, mask ); 1563 r128_cce_dispatch_stipple(dev, mask);
1587 1564
1588 COMMIT_RING(); 1565 COMMIT_RING();
1589 return 0; 1566 return 0;
1590} 1567}
1591 1568
1592static int r128_cce_indirect( DRM_IOCTL_ARGS ) 1569static int r128_cce_indirect(DRM_IOCTL_ARGS)
1593{ 1570{
1594 DRM_DEVICE; 1571 DRM_DEVICE;
1595 drm_r128_private_t *dev_priv = dev->dev_private; 1572 drm_r128_private_t *dev_priv = dev->dev_private;
@@ -1601,47 +1578,46 @@ static int r128_cce_indirect( DRM_IOCTL_ARGS )
1601 RING_LOCALS; 1578 RING_LOCALS;
1602#endif 1579#endif
1603 1580
1604 LOCK_TEST_WITH_RETURN( dev, filp ); 1581 LOCK_TEST_WITH_RETURN(dev, filp);
1605 1582
1606 if ( !dev_priv ) { 1583 if (!dev_priv) {
1607 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 1584 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1608 return DRM_ERR(EINVAL); 1585 return DRM_ERR(EINVAL);
1609 } 1586 }
1610 1587
1611 DRM_COPY_FROM_USER_IOCTL( indirect, (drm_r128_indirect_t __user *) data, 1588 DRM_COPY_FROM_USER_IOCTL(indirect, (drm_r128_indirect_t __user *) data,
1612 sizeof(indirect) ); 1589 sizeof(indirect));
1613 1590
1614 DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n", 1591 DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n",
1615 indirect.idx, indirect.start, 1592 indirect.idx, indirect.start, indirect.end, indirect.discard);
1616 indirect.end, indirect.discard );
1617 1593
1618 if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) { 1594 if (indirect.idx < 0 || indirect.idx >= dma->buf_count) {
1619 DRM_ERROR( "buffer index %d (of %d max)\n", 1595 DRM_ERROR("buffer index %d (of %d max)\n",
1620 indirect.idx, dma->buf_count - 1 ); 1596 indirect.idx, dma->buf_count - 1);
1621 return DRM_ERR(EINVAL); 1597 return DRM_ERR(EINVAL);
1622 } 1598 }
1623 1599
1624 buf = dma->buflist[indirect.idx]; 1600 buf = dma->buflist[indirect.idx];
1625 buf_priv = buf->dev_private; 1601 buf_priv = buf->dev_private;
1626 1602
1627 if ( buf->filp != filp ) { 1603 if (buf->filp != filp) {
1628 DRM_ERROR( "process %d using buffer owned by %p\n", 1604 DRM_ERROR("process %d using buffer owned by %p\n",
1629 DRM_CURRENTPID, buf->filp ); 1605 DRM_CURRENTPID, buf->filp);
1630 return DRM_ERR(EINVAL); 1606 return DRM_ERR(EINVAL);
1631 } 1607 }
1632 if ( buf->pending ) { 1608 if (buf->pending) {
1633 DRM_ERROR( "sending pending buffer %d\n", indirect.idx ); 1609 DRM_ERROR("sending pending buffer %d\n", indirect.idx);
1634 return DRM_ERR(EINVAL); 1610 return DRM_ERR(EINVAL);
1635 } 1611 }
1636 1612
1637 if ( indirect.start < buf->used ) { 1613 if (indirect.start < buf->used) {
1638 DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n", 1614 DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n",
1639 indirect.start, buf->used ); 1615 indirect.start, buf->used);
1640 return DRM_ERR(EINVAL); 1616 return DRM_ERR(EINVAL);
1641 } 1617 }
1642 1618
1643 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 1619 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1644 VB_AGE_TEST_WITH_RETURN( dev_priv ); 1620 VB_AGE_TEST_WITH_RETURN(dev_priv);
1645 1621
1646 buf->used = indirect.end; 1622 buf->used = indirect.end;
1647 buf_priv->discard = indirect.discard; 1623 buf_priv->discard = indirect.discard;
@@ -1650,7 +1626,7 @@ static int r128_cce_indirect( DRM_IOCTL_ARGS )
1650 /* Wait for the 3D stream to idle before the indirect buffer 1626 /* Wait for the 3D stream to idle before the indirect buffer
1651 * containing 2D acceleration commands is processed. 1627 * containing 2D acceleration commands is processed.
1652 */ 1628 */
1653 BEGIN_RING( 2 ); 1629 BEGIN_RING(2);
1654 RADEON_WAIT_UNTIL_3D_IDLE(); 1630 RADEON_WAIT_UNTIL_3D_IDLE();
1655 ADVANCE_RING(); 1631 ADVANCE_RING();
1656#endif 1632#endif
@@ -1659,30 +1635,30 @@ static int r128_cce_indirect( DRM_IOCTL_ARGS )
1659 * X server. This is insecure and is thus only available to 1635 * X server. This is insecure and is thus only available to
1660 * privileged clients. 1636 * privileged clients.
1661 */ 1637 */
1662 r128_cce_dispatch_indirect( dev, buf, indirect.start, indirect.end ); 1638 r128_cce_dispatch_indirect(dev, buf, indirect.start, indirect.end);
1663 1639
1664 COMMIT_RING(); 1640 COMMIT_RING();
1665 return 0; 1641 return 0;
1666} 1642}
1667 1643
1668static int r128_getparam( DRM_IOCTL_ARGS ) 1644static int r128_getparam(DRM_IOCTL_ARGS)
1669{ 1645{
1670 DRM_DEVICE; 1646 DRM_DEVICE;
1671 drm_r128_private_t *dev_priv = dev->dev_private; 1647 drm_r128_private_t *dev_priv = dev->dev_private;
1672 drm_r128_getparam_t param; 1648 drm_r128_getparam_t param;
1673 int value; 1649 int value;
1674 1650
1675 if ( !dev_priv ) { 1651 if (!dev_priv) {
1676 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 1652 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1677 return DRM_ERR(EINVAL); 1653 return DRM_ERR(EINVAL);
1678 } 1654 }
1679 1655
1680 DRM_COPY_FROM_USER_IOCTL( param, (drm_r128_getparam_t __user *)data, 1656 DRM_COPY_FROM_USER_IOCTL(param, (drm_r128_getparam_t __user *) data,
1681 sizeof(param) ); 1657 sizeof(param));
1682 1658
1683 DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); 1659 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1684 1660
1685 switch( param.param ) { 1661 switch (param.param) {
1686 case R128_PARAM_IRQ_NR: 1662 case R128_PARAM_IRQ_NR:
1687 value = dev->irq; 1663 value = dev->irq;
1688 break; 1664 break;
@@ -1690,47 +1666,47 @@ static int r128_getparam( DRM_IOCTL_ARGS )
1690 return DRM_ERR(EINVAL); 1666 return DRM_ERR(EINVAL);
1691 } 1667 }
1692 1668
1693 if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { 1669 if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
1694 DRM_ERROR( "copy_to_user\n" ); 1670 DRM_ERROR("copy_to_user\n");
1695 return DRM_ERR(EFAULT); 1671 return DRM_ERR(EFAULT);
1696 } 1672 }
1697 1673
1698 return 0; 1674 return 0;
1699} 1675}
1700 1676
1701void r128_driver_prerelease(drm_device_t *dev, DRMFILE filp) 1677void r128_driver_prerelease(drm_device_t * dev, DRMFILE filp)
1702{ 1678{
1703 if ( dev->dev_private ) { 1679 if (dev->dev_private) {
1704 drm_r128_private_t *dev_priv = dev->dev_private; 1680 drm_r128_private_t *dev_priv = dev->dev_private;
1705 if ( dev_priv->page_flipping ) { 1681 if (dev_priv->page_flipping) {
1706 r128_do_cleanup_pageflip( dev ); 1682 r128_do_cleanup_pageflip(dev);
1707 } 1683 }
1708 } 1684 }
1709} 1685}
1710 1686
1711void r128_driver_pretakedown(drm_device_t *dev) 1687void r128_driver_pretakedown(drm_device_t * dev)
1712{ 1688{
1713 r128_do_cleanup_cce( dev ); 1689 r128_do_cleanup_cce(dev);
1714} 1690}
1715 1691
1716drm_ioctl_desc_t r128_ioctls[] = { 1692drm_ioctl_desc_t r128_ioctls[] = {
1717 [DRM_IOCTL_NR(DRM_R128_INIT)] = { r128_cce_init, 1, 1 }, 1693 [DRM_IOCTL_NR(DRM_R128_INIT)] = {r128_cce_init, 1, 1},
1718 [DRM_IOCTL_NR(DRM_R128_CCE_START)] = { r128_cce_start, 1, 1 }, 1694 [DRM_IOCTL_NR(DRM_R128_CCE_START)] = {r128_cce_start, 1, 1},
1719 [DRM_IOCTL_NR(DRM_R128_CCE_STOP)] = { r128_cce_stop, 1, 1 }, 1695 [DRM_IOCTL_NR(DRM_R128_CCE_STOP)] = {r128_cce_stop, 1, 1},
1720 [DRM_IOCTL_NR(DRM_R128_CCE_RESET)] = { r128_cce_reset, 1, 1 }, 1696 [DRM_IOCTL_NR(DRM_R128_CCE_RESET)] = {r128_cce_reset, 1, 1},
1721 [DRM_IOCTL_NR(DRM_R128_CCE_IDLE)] = { r128_cce_idle, 1, 0 }, 1697 [DRM_IOCTL_NR(DRM_R128_CCE_IDLE)] = {r128_cce_idle, 1, 0},
1722 [DRM_IOCTL_NR(DRM_R128_RESET)] = { r128_engine_reset, 1, 0 }, 1698 [DRM_IOCTL_NR(DRM_R128_RESET)] = {r128_engine_reset, 1, 0},
1723 [DRM_IOCTL_NR(DRM_R128_FULLSCREEN)] = { r128_fullscreen, 1, 0 }, 1699 [DRM_IOCTL_NR(DRM_R128_FULLSCREEN)] = {r128_fullscreen, 1, 0},
1724 [DRM_IOCTL_NR(DRM_R128_SWAP)] = { r128_cce_swap, 1, 0 }, 1700 [DRM_IOCTL_NR(DRM_R128_SWAP)] = {r128_cce_swap, 1, 0},
1725 [DRM_IOCTL_NR(DRM_R128_FLIP)] = { r128_cce_flip, 1, 0 }, 1701 [DRM_IOCTL_NR(DRM_R128_FLIP)] = {r128_cce_flip, 1, 0},
1726 [DRM_IOCTL_NR(DRM_R128_CLEAR)] = { r128_cce_clear, 1, 0 }, 1702 [DRM_IOCTL_NR(DRM_R128_CLEAR)] = {r128_cce_clear, 1, 0},
1727 [DRM_IOCTL_NR(DRM_R128_VERTEX)] = { r128_cce_vertex, 1, 0 }, 1703 [DRM_IOCTL_NR(DRM_R128_VERTEX)] = {r128_cce_vertex, 1, 0},
1728 [DRM_IOCTL_NR(DRM_R128_INDICES)] = { r128_cce_indices, 1, 0 }, 1704 [DRM_IOCTL_NR(DRM_R128_INDICES)] = {r128_cce_indices, 1, 0},
1729 [DRM_IOCTL_NR(DRM_R128_BLIT)] = { r128_cce_blit, 1, 0 }, 1705 [DRM_IOCTL_NR(DRM_R128_BLIT)] = {r128_cce_blit, 1, 0},
1730 [DRM_IOCTL_NR(DRM_R128_DEPTH)] = { r128_cce_depth, 1, 0 }, 1706 [DRM_IOCTL_NR(DRM_R128_DEPTH)] = {r128_cce_depth, 1, 0},
1731 [DRM_IOCTL_NR(DRM_R128_STIPPLE)] = { r128_cce_stipple, 1, 0 }, 1707 [DRM_IOCTL_NR(DRM_R128_STIPPLE)] = {r128_cce_stipple, 1, 0},
1732 [DRM_IOCTL_NR(DRM_R128_INDIRECT)] = { r128_cce_indirect, 1, 1 }, 1708 [DRM_IOCTL_NR(DRM_R128_INDIRECT)] = {r128_cce_indirect, 1, 1},
1733 [DRM_IOCTL_NR(DRM_R128_GETPARAM)] = { r128_getparam, 1, 0 }, 1709 [DRM_IOCTL_NR(DRM_R128_GETPARAM)] = {r128_getparam, 1, 0},
1734}; 1710};
1735 1711
1736int r128_max_ioctl = DRM_ARRAY_SIZE(r128_ioctls); 1712int r128_max_ioctl = DRM_ARRAY_SIZE(r128_ioctls);
diff --git a/drivers/char/drm/r300_cmdbuf.c b/drivers/char/drm/r300_cmdbuf.c
index 623f1f460cb5..aa66f46279e7 100644
--- a/drivers/char/drm/r300_cmdbuf.c
+++ b/drivers/char/drm/r300_cmdbuf.c
@@ -37,7 +37,6 @@
37#include "radeon_drv.h" 37#include "radeon_drv.h"
38#include "r300_reg.h" 38#include "r300_reg.h"
39 39
40
41#define R300_SIMULTANEOUS_CLIPRECTS 4 40#define R300_SIMULTANEOUS_CLIPRECTS 4
42 41
43/* Values for R300_RE_CLIPRECT_CNTL depending on the number of cliprects 42/* Values for R300_RE_CLIPRECT_CNTL depending on the number of cliprects
@@ -49,14 +48,12 @@ static const int r300_cliprect_cntl[4] = {
49 0xFFFE 48 0xFFFE
50}; 49};
51 50
52
53/** 51/**
54 * Emit up to R300_SIMULTANEOUS_CLIPRECTS cliprects from the given command 52 * Emit up to R300_SIMULTANEOUS_CLIPRECTS cliprects from the given command
55 * buffer, starting with index n. 53 * buffer, starting with index n.
56 */ 54 */
57static int r300_emit_cliprects(drm_radeon_private_t* dev_priv, 55static int r300_emit_cliprects(drm_radeon_private_t * dev_priv,
58 drm_radeon_cmd_buffer_t* cmdbuf, 56 drm_radeon_cmd_buffer_t * cmdbuf, int n)
59 int n)
60{ 57{
61 drm_clip_rect_t box; 58 drm_clip_rect_t box;
62 int nr; 59 int nr;
@@ -70,38 +67,47 @@ static int r300_emit_cliprects(drm_radeon_private_t* dev_priv,
70 DRM_DEBUG("%i cliprects\n", nr); 67 DRM_DEBUG("%i cliprects\n", nr);
71 68
72 if (nr) { 69 if (nr) {
73 BEGIN_RING(6 + nr*2); 70 BEGIN_RING(6 + nr * 2);
74 OUT_RING( CP_PACKET0( R300_RE_CLIPRECT_TL_0, nr*2 - 1 ) ); 71 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1));
75 72
76 for(i = 0; i < nr; ++i) { 73 for (i = 0; i < nr; ++i) {
77 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &cmdbuf->boxes[n+i], sizeof(box))) { 74 if (DRM_COPY_FROM_USER_UNCHECKED
75 (&box, &cmdbuf->boxes[n + i], sizeof(box))) {
78 DRM_ERROR("copy cliprect faulted\n"); 76 DRM_ERROR("copy cliprect faulted\n");
79 return DRM_ERR(EFAULT); 77 return DRM_ERR(EFAULT);
80 } 78 }
81 79
82 box.x1 = (box.x1 + R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK; 80 box.x1 =
83 box.y1 = (box.y1 + R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK; 81 (box.x1 +
84 box.x2 = (box.x2 + R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK; 82 R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
85 box.y2 = (box.y2 + R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK; 83 box.y1 =
84 (box.y1 +
85 R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
86 box.x2 =
87 (box.x2 +
88 R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
89 box.y2 =
90 (box.y2 +
91 R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
86 92
87 OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) | 93 OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) |
88 (box.y1 << R300_CLIPRECT_Y_SHIFT)); 94 (box.y1 << R300_CLIPRECT_Y_SHIFT));
89 OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) | 95 OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) |
90 (box.y2 << R300_CLIPRECT_Y_SHIFT)); 96 (box.y2 << R300_CLIPRECT_Y_SHIFT));
91 } 97 }
92 98
93 OUT_RING_REG( R300_RE_CLIPRECT_CNTL, r300_cliprect_cntl[nr-1] ); 99 OUT_RING_REG(R300_RE_CLIPRECT_CNTL, r300_cliprect_cntl[nr - 1]);
94 100
95 /* TODO/SECURITY: Force scissors to a safe value, otherwise the 101 /* TODO/SECURITY: Force scissors to a safe value, otherwise the
96 * client might be able to trample over memory. 102 * client might be able to trample over memory.
97 * The impact should be very limited, but I'd rather be safe than 103 * The impact should be very limited, but I'd rather be safe than
98 * sorry. 104 * sorry.
99 */ 105 */
100 OUT_RING( CP_PACKET0( R300_RE_SCISSORS_TL, 1 ) ); 106 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1));
101 OUT_RING( 0 ); 107 OUT_RING(0);
102 OUT_RING( R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK ); 108 OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK);
103 ADVANCE_RING(); 109 ADVANCE_RING();
104 } else { 110 } else {
105 /* Why we allow zero cliprect rendering: 111 /* Why we allow zero cliprect rendering:
106 * There are some commands in a command buffer that must be submitted 112 * There are some commands in a command buffer that must be submitted
107 * even when there are no cliprects, e.g. DMA buffer discard 113 * even when there are no cliprects, e.g. DMA buffer discard
@@ -118,28 +124,27 @@ static int r300_emit_cliprects(drm_radeon_private_t* dev_priv,
118 * can't produce any fragments. 124 * can't produce any fragments.
119 */ 125 */
120 BEGIN_RING(2); 126 BEGIN_RING(2);
121 OUT_RING_REG( R300_RE_CLIPRECT_CNTL, 0 ); 127 OUT_RING_REG(R300_RE_CLIPRECT_CNTL, 0);
122 ADVANCE_RING(); 128 ADVANCE_RING();
123 } 129 }
124 130
125 return 0; 131 return 0;
126} 132}
127 133
128u8 r300_reg_flags[0x10000>>2]; 134u8 r300_reg_flags[0x10000 >> 2];
129
130 135
131void r300_init_reg_flags(void) 136void r300_init_reg_flags(void)
132{ 137{
133 int i; 138 int i;
134 memset(r300_reg_flags, 0, 0x10000>>2); 139 memset(r300_reg_flags, 0, 0x10000 >> 2);
135 #define ADD_RANGE_MARK(reg, count,mark) \ 140#define ADD_RANGE_MARK(reg, count,mark) \
136 for(i=((reg)>>2);i<((reg)>>2)+(count);i++)\ 141 for(i=((reg)>>2);i<((reg)>>2)+(count);i++)\
137 r300_reg_flags[i]|=(mark); 142 r300_reg_flags[i]|=(mark);
138 143
139 #define MARK_SAFE 1 144#define MARK_SAFE 1
140 #define MARK_CHECK_OFFSET 2 145#define MARK_CHECK_OFFSET 2
141 146
142 #define ADD_RANGE(reg, count) ADD_RANGE_MARK(reg, count, MARK_SAFE) 147#define ADD_RANGE(reg, count) ADD_RANGE_MARK(reg, count, MARK_SAFE)
143 148
144 /* these match cmducs() command in r300_driver/r300/r300_cmdbuf.c */ 149 /* these match cmducs() command in r300_driver/r300/r300_cmdbuf.c */
145 ADD_RANGE(R300_SE_VPORT_XSCALE, 6); 150 ADD_RANGE(R300_SE_VPORT_XSCALE, 6);
@@ -193,15 +198,15 @@ void r300_init_reg_flags(void)
193 ADD_RANGE(R300_RB3D_CBLEND, 2); 198 ADD_RANGE(R300_RB3D_CBLEND, 2);
194 ADD_RANGE(R300_RB3D_COLORMASK, 1); 199 ADD_RANGE(R300_RB3D_COLORMASK, 1);
195 ADD_RANGE(0x4E10, 3); 200 ADD_RANGE(0x4E10, 3);
196 ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0, 1, MARK_CHECK_OFFSET); /* check offset */ 201 ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0, 1, MARK_CHECK_OFFSET); /* check offset */
197 ADD_RANGE(R300_RB3D_COLORPITCH0, 1); 202 ADD_RANGE(R300_RB3D_COLORPITCH0, 1);
198 ADD_RANGE(0x4E50, 9); 203 ADD_RANGE(0x4E50, 9);
199 ADD_RANGE(0x4E88, 1); 204 ADD_RANGE(0x4E88, 1);
200 ADD_RANGE(0x4EA0, 2); 205 ADD_RANGE(0x4EA0, 2);
201 ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3); 206 ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3);
202 ADD_RANGE(0x4F10, 4); 207 ADD_RANGE(0x4F10, 4);
203 ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */ 208 ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */
204 ADD_RANGE(R300_RB3D_DEPTHPITCH, 1); 209 ADD_RANGE(R300_RB3D_DEPTHPITCH, 1);
205 ADD_RANGE(0x4F28, 1); 210 ADD_RANGE(0x4F28, 1);
206 ADD_RANGE(0x4F30, 2); 211 ADD_RANGE(0x4F30, 2);
207 ADD_RANGE(0x4F44, 1); 212 ADD_RANGE(0x4F44, 1);
@@ -211,7 +216,7 @@ void r300_init_reg_flags(void)
211 ADD_RANGE(R300_TX_UNK1_0, 16); 216 ADD_RANGE(R300_TX_UNK1_0, 16);
212 ADD_RANGE(R300_TX_SIZE_0, 16); 217 ADD_RANGE(R300_TX_SIZE_0, 16);
213 ADD_RANGE(R300_TX_FORMAT_0, 16); 218 ADD_RANGE(R300_TX_FORMAT_0, 16);
214 /* Texture offset is dangerous and needs more checking */ 219 /* Texture offset is dangerous and needs more checking */
215 ADD_RANGE_MARK(R300_TX_OFFSET_0, 16, MARK_CHECK_OFFSET); 220 ADD_RANGE_MARK(R300_TX_OFFSET_0, 16, MARK_CHECK_OFFSET);
216 ADD_RANGE(R300_TX_UNK4_0, 16); 221 ADD_RANGE(R300_TX_UNK4_0, 16);
217 ADD_RANGE(R300_TX_BORDER_COLOR_0, 16); 222 ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
@@ -224,33 +229,41 @@ void r300_init_reg_flags(void)
224 229
225} 230}
226 231
227static __inline__ int r300_check_range(unsigned reg, int count) 232static __inline__ int r300_check_range(unsigned reg, int count)
228{ 233{
229 int i; 234 int i;
230 if(reg & ~0xffff)return -1; 235 if (reg & ~0xffff)
231 for(i=(reg>>2);i<(reg>>2)+count;i++) 236 return -1;
232 if(r300_reg_flags[i]!=MARK_SAFE)return 1; 237 for (i = (reg >> 2); i < (reg >> 2) + count; i++)
238 if (r300_reg_flags[i] != MARK_SAFE)
239 return 1;
233 return 0; 240 return 0;
234} 241}
235 242
236 /* we expect offsets passed to the framebuffer to be either within video memory or 243 /* we expect offsets passed to the framebuffer to be either within video memory or
237 within AGP space */ 244 within AGP space */
238static __inline__ int r300_check_offset(drm_radeon_private_t* dev_priv, u32 offset) 245static __inline__ int r300_check_offset(drm_radeon_private_t * dev_priv,
246 u32 offset)
239{ 247{
240 /* we realy want to check against end of video aperture 248 /* we realy want to check against end of video aperture
241 but this value is not being kept. 249 but this value is not being kept.
242 This code is correct for now (does the same thing as the 250 This code is correct for now (does the same thing as the
243 code that sets MC_FB_LOCATION) in radeon_cp.c */ 251 code that sets MC_FB_LOCATION) in radeon_cp.c */
244 if((offset>=dev_priv->fb_location) && 252 if ((offset >= dev_priv->fb_location) &&
245 (offset<dev_priv->gart_vm_start))return 0; 253 (offset < dev_priv->gart_vm_start))
246 if((offset>=dev_priv->gart_vm_start) && 254 return 0;
247 (offset<dev_priv->gart_vm_start+dev_priv->gart_size))return 0; 255 if ((offset >= dev_priv->gart_vm_start) &&
256 (offset < dev_priv->gart_vm_start + dev_priv->gart_size))
257 return 0;
248 return 1; 258 return 1;
249} 259}
250 260
251static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t* dev_priv, 261static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t *
252 drm_radeon_cmd_buffer_t* cmdbuf, 262 dev_priv,
253 drm_r300_cmd_header_t header) 263 drm_radeon_cmd_buffer_t
264 * cmdbuf,
265 drm_r300_cmd_header_t
266 header)
254{ 267{
255 int reg; 268 int reg;
256 int sz; 269 int sz;
@@ -260,35 +273,40 @@ static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t*
260 273
261 sz = header.packet0.count; 274 sz = header.packet0.count;
262 reg = (header.packet0.reghi << 8) | header.packet0.reglo; 275 reg = (header.packet0.reghi << 8) | header.packet0.reglo;
263 276
264 if((sz>64)||(sz<0)){ 277 if ((sz > 64) || (sz < 0)) {
265 DRM_ERROR("Cannot emit more than 64 values at a time (reg=%04x sz=%d)\n", reg, sz); 278 DRM_ERROR
279 ("Cannot emit more than 64 values at a time (reg=%04x sz=%d)\n",
280 reg, sz);
266 return DRM_ERR(EINVAL); 281 return DRM_ERR(EINVAL);
267 } 282 }
268 for(i=0;i<sz;i++){ 283 for (i = 0; i < sz; i++) {
269 values[i]=((int __user*)cmdbuf->buf)[i]; 284 values[i] = ((int __user *)cmdbuf->buf)[i];
270 switch(r300_reg_flags[(reg>>2)+i]){ 285 switch (r300_reg_flags[(reg >> 2) + i]) {
271 case MARK_SAFE: 286 case MARK_SAFE:
272 break; 287 break;
273 case MARK_CHECK_OFFSET: 288 case MARK_CHECK_OFFSET:
274 if(r300_check_offset(dev_priv, (u32)values[i])){ 289 if (r300_check_offset(dev_priv, (u32) values[i])) {
275 DRM_ERROR("Offset failed range check (reg=%04x sz=%d)\n", reg, sz); 290 DRM_ERROR
291 ("Offset failed range check (reg=%04x sz=%d)\n",
292 reg, sz);
276 return DRM_ERR(EINVAL); 293 return DRM_ERR(EINVAL);
277 } 294 }
278 break; 295 break;
279 default: 296 default:
280 DRM_ERROR("Register %04x failed check as flag=%02x\n", reg+i*4, r300_reg_flags[(reg>>2)+i]); 297 DRM_ERROR("Register %04x failed check as flag=%02x\n",
298 reg + i * 4, r300_reg_flags[(reg >> 2) + i]);
281 return DRM_ERR(EINVAL); 299 return DRM_ERR(EINVAL);
282 }
283 } 300 }
284 301 }
285 BEGIN_RING(1+sz); 302
286 OUT_RING( CP_PACKET0( reg, sz-1 ) ); 303 BEGIN_RING(1 + sz);
287 OUT_RING_TABLE( values, sz ); 304 OUT_RING(CP_PACKET0(reg, sz - 1));
305 OUT_RING_TABLE(values, sz);
288 ADVANCE_RING(); 306 ADVANCE_RING();
289 307
290 cmdbuf->buf += sz*4; 308 cmdbuf->buf += sz * 4;
291 cmdbuf->bufsz -= sz*4; 309 cmdbuf->bufsz -= sz * 4;
292 310
293 return 0; 311 return 0;
294} 312}
@@ -299,9 +317,9 @@ static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t*
299 * 317 *
300 * Note that checks are performed on contents and addresses of the registers 318 * Note that checks are performed on contents and addresses of the registers
301 */ 319 */
302static __inline__ int r300_emit_packet0(drm_radeon_private_t* dev_priv, 320static __inline__ int r300_emit_packet0(drm_radeon_private_t * dev_priv,
303 drm_radeon_cmd_buffer_t* cmdbuf, 321 drm_radeon_cmd_buffer_t * cmdbuf,
304 drm_r300_cmd_header_t header) 322 drm_r300_cmd_header_t header)
305{ 323{
306 int reg; 324 int reg;
307 int sz; 325 int sz;
@@ -313,39 +331,40 @@ static __inline__ int r300_emit_packet0(drm_radeon_private_t* dev_priv,
313 if (!sz) 331 if (!sz)
314 return 0; 332 return 0;
315 333
316 if (sz*4 > cmdbuf->bufsz) 334 if (sz * 4 > cmdbuf->bufsz)
317 return DRM_ERR(EINVAL); 335 return DRM_ERR(EINVAL);
318 336
319 if (reg+sz*4 >= 0x10000){ 337 if (reg + sz * 4 >= 0x10000) {
320 DRM_ERROR("No such registers in hardware reg=%04x sz=%d\n", reg, sz); 338 DRM_ERROR("No such registers in hardware reg=%04x sz=%d\n", reg,
339 sz);
321 return DRM_ERR(EINVAL); 340 return DRM_ERR(EINVAL);
322 } 341 }
323 342
324 if(r300_check_range(reg, sz)){ 343 if (r300_check_range(reg, sz)) {
325 /* go and check everything */ 344 /* go and check everything */
326 return r300_emit_carefully_checked_packet0(dev_priv, cmdbuf, header); 345 return r300_emit_carefully_checked_packet0(dev_priv, cmdbuf,
327 } 346 header);
347 }
328 /* the rest of the data is safe to emit, whatever the values the user passed */ 348 /* the rest of the data is safe to emit, whatever the values the user passed */
329 349
330 BEGIN_RING(1+sz); 350 BEGIN_RING(1 + sz);
331 OUT_RING( CP_PACKET0( reg, sz-1 ) ); 351 OUT_RING(CP_PACKET0(reg, sz - 1));
332 OUT_RING_TABLE( (int __user*)cmdbuf->buf, sz ); 352 OUT_RING_TABLE((int __user *)cmdbuf->buf, sz);
333 ADVANCE_RING(); 353 ADVANCE_RING();
334 354
335 cmdbuf->buf += sz*4; 355 cmdbuf->buf += sz * 4;
336 cmdbuf->bufsz -= sz*4; 356 cmdbuf->bufsz -= sz * 4;
337 357
338 return 0; 358 return 0;
339} 359}
340 360
341
342/** 361/**
343 * Uploads user-supplied vertex program instructions or parameters onto 362 * Uploads user-supplied vertex program instructions or parameters onto
344 * the graphics card. 363 * the graphics card.
345 * Called by r300_do_cp_cmdbuf. 364 * Called by r300_do_cp_cmdbuf.
346 */ 365 */
347static __inline__ int r300_emit_vpu(drm_radeon_private_t* dev_priv, 366static __inline__ int r300_emit_vpu(drm_radeon_private_t * dev_priv,
348 drm_radeon_cmd_buffer_t* cmdbuf, 367 drm_radeon_cmd_buffer_t * cmdbuf,
349 drm_r300_cmd_header_t header) 368 drm_r300_cmd_header_t header)
350{ 369{
351 int sz; 370 int sz;
@@ -357,114 +376,121 @@ static __inline__ int r300_emit_vpu(drm_radeon_private_t* dev_priv,
357 376
358 if (!sz) 377 if (!sz)
359 return 0; 378 return 0;
360 if (sz*16 > cmdbuf->bufsz) 379 if (sz * 16 > cmdbuf->bufsz)
361 return DRM_ERR(EINVAL); 380 return DRM_ERR(EINVAL);
362 381
363 BEGIN_RING(5+sz*4); 382 BEGIN_RING(5 + sz * 4);
364 /* Wait for VAP to come to senses.. */ 383 /* Wait for VAP to come to senses.. */
365 /* there is no need to emit it multiple times, (only once before VAP is programmed, 384 /* there is no need to emit it multiple times, (only once before VAP is programmed,
366 but this optimization is for later */ 385 but this optimization is for later */
367 OUT_RING_REG( R300_VAP_PVS_WAITIDLE, 0 ); 386 OUT_RING_REG(R300_VAP_PVS_WAITIDLE, 0);
368 OUT_RING_REG( R300_VAP_PVS_UPLOAD_ADDRESS, addr ); 387 OUT_RING_REG(R300_VAP_PVS_UPLOAD_ADDRESS, addr);
369 OUT_RING( CP_PACKET0_TABLE( R300_VAP_PVS_UPLOAD_DATA, sz*4 - 1 ) ); 388 OUT_RING(CP_PACKET0_TABLE(R300_VAP_PVS_UPLOAD_DATA, sz * 4 - 1));
370 OUT_RING_TABLE( (int __user*)cmdbuf->buf, sz*4 ); 389 OUT_RING_TABLE((int __user *)cmdbuf->buf, sz * 4);
371 390
372 ADVANCE_RING(); 391 ADVANCE_RING();
373 392
374 cmdbuf->buf += sz*16; 393 cmdbuf->buf += sz * 16;
375 cmdbuf->bufsz -= sz*16; 394 cmdbuf->bufsz -= sz * 16;
376 395
377 return 0; 396 return 0;
378} 397}
379 398
380
381/** 399/**
382 * Emit a clear packet from userspace. 400 * Emit a clear packet from userspace.
383 * Called by r300_emit_packet3. 401 * Called by r300_emit_packet3.
384 */ 402 */
385static __inline__ int r300_emit_clear(drm_radeon_private_t* dev_priv, 403static __inline__ int r300_emit_clear(drm_radeon_private_t * dev_priv,
386 drm_radeon_cmd_buffer_t* cmdbuf) 404 drm_radeon_cmd_buffer_t * cmdbuf)
387{ 405{
388 RING_LOCALS; 406 RING_LOCALS;
389 407
390 if (8*4 > cmdbuf->bufsz) 408 if (8 * 4 > cmdbuf->bufsz)
391 return DRM_ERR(EINVAL); 409 return DRM_ERR(EINVAL);
392 410
393 BEGIN_RING(10); 411 BEGIN_RING(10);
394 OUT_RING( CP_PACKET3( R200_3D_DRAW_IMMD_2, 8 ) ); 412 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
395 OUT_RING( R300_PRIM_TYPE_POINT|R300_PRIM_WALK_RING| 413 OUT_RING(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
396 (1<<R300_PRIM_NUM_VERTICES_SHIFT) ); 414 (1 << R300_PRIM_NUM_VERTICES_SHIFT));
397 OUT_RING_TABLE( (int __user*)cmdbuf->buf, 8 ); 415 OUT_RING_TABLE((int __user *)cmdbuf->buf, 8);
398 ADVANCE_RING(); 416 ADVANCE_RING();
399 417
400 cmdbuf->buf += 8*4; 418 cmdbuf->buf += 8 * 4;
401 cmdbuf->bufsz -= 8*4; 419 cmdbuf->bufsz -= 8 * 4;
402 420
403 return 0; 421 return 0;
404} 422}
405 423
406static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t* dev_priv, 424static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t * dev_priv,
407 drm_radeon_cmd_buffer_t* cmdbuf, 425 drm_radeon_cmd_buffer_t * cmdbuf,
408 u32 header) 426 u32 header)
409{ 427{
410 int count, i,k; 428 int count, i, k;
411 #define MAX_ARRAY_PACKET 64 429#define MAX_ARRAY_PACKET 64
412 u32 payload[MAX_ARRAY_PACKET]; 430 u32 payload[MAX_ARRAY_PACKET];
413 u32 narrays; 431 u32 narrays;
414 RING_LOCALS; 432 RING_LOCALS;
415 433
416 count=(header>>16) & 0x3fff; 434 count = (header >> 16) & 0x3fff;
417 435
418 if((count+1)>MAX_ARRAY_PACKET){ 436 if ((count + 1) > MAX_ARRAY_PACKET) {
419 DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n", count); 437 DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n",
438 count);
420 return DRM_ERR(EINVAL); 439 return DRM_ERR(EINVAL);
421 } 440 }
422 memset(payload, 0, MAX_ARRAY_PACKET*4); 441 memset(payload, 0, MAX_ARRAY_PACKET * 4);
423 memcpy(payload, cmdbuf->buf+4, (count+1)*4); 442 memcpy(payload, cmdbuf->buf + 4, (count + 1) * 4);
424 443
425 /* carefully check packet contents */ 444 /* carefully check packet contents */
426 445
427 narrays=payload[0]; 446 narrays = payload[0];
428 k=0; 447 k = 0;
429 i=1; 448 i = 1;
430 while((k<narrays) && (i<(count+1))){ 449 while ((k < narrays) && (i < (count + 1))) {
431 i++; /* skip attribute field */ 450 i++; /* skip attribute field */
432 if(r300_check_offset(dev_priv, payload[i])){ 451 if (r300_check_offset(dev_priv, payload[i])) {
433 DRM_ERROR("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n", k, i); 452 DRM_ERROR
453 ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n",
454 k, i);
434 return DRM_ERR(EINVAL); 455 return DRM_ERR(EINVAL);
435 } 456 }
436 k++; 457 k++;
437 i++; 458 i++;
438 if(k==narrays)break; 459 if (k == narrays)
460 break;
439 /* have one more to process, they come in pairs */ 461 /* have one more to process, they come in pairs */
440 if(r300_check_offset(dev_priv, payload[i])){ 462 if (r300_check_offset(dev_priv, payload[i])) {
441 DRM_ERROR("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n", k, i); 463 DRM_ERROR
464 ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n",
465 k, i);
442 return DRM_ERR(EINVAL); 466 return DRM_ERR(EINVAL);
443 }
444 k++;
445 i++;
446 } 467 }
468 k++;
469 i++;
470 }
447 /* do the counts match what we expect ? */ 471 /* do the counts match what we expect ? */
448 if((k!=narrays) || (i!=(count+1))){ 472 if ((k != narrays) || (i != (count + 1))) {
449 DRM_ERROR("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n", k, i, narrays, count+1); 473 DRM_ERROR
474 ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n",
475 k, i, narrays, count + 1);
450 return DRM_ERR(EINVAL); 476 return DRM_ERR(EINVAL);
451 } 477 }
452 478
453 /* all clear, output packet */ 479 /* all clear, output packet */
454 480
455 BEGIN_RING(count+2); 481 BEGIN_RING(count + 2);
456 OUT_RING(header); 482 OUT_RING(header);
457 OUT_RING_TABLE(payload, count+1); 483 OUT_RING_TABLE(payload, count + 1);
458 ADVANCE_RING(); 484 ADVANCE_RING();
459 485
460 cmdbuf->buf += (count+2)*4; 486 cmdbuf->buf += (count + 2) * 4;
461 cmdbuf->bufsz -= (count+2)*4; 487 cmdbuf->bufsz -= (count + 2) * 4;
462 488
463 return 0; 489 return 0;
464} 490}
465 491
466static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t* dev_priv, 492static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t * dev_priv,
467 drm_radeon_cmd_buffer_t* cmdbuf) 493 drm_radeon_cmd_buffer_t * cmdbuf)
468{ 494{
469 u32 header; 495 u32 header;
470 int count; 496 int count;
@@ -473,36 +499,37 @@ static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t* dev_priv,
473 if (4 > cmdbuf->bufsz) 499 if (4 > cmdbuf->bufsz)
474 return DRM_ERR(EINVAL); 500 return DRM_ERR(EINVAL);
475 501
476 /* Fixme !! This simply emits a packet without much checking. 502 /* Fixme !! This simply emits a packet without much checking.
477 We need to be smarter. */ 503 We need to be smarter. */
478 504
479 /* obtain first word - actual packet3 header */ 505 /* obtain first word - actual packet3 header */
480 header = *(u32 __user*)cmdbuf->buf; 506 header = *(u32 __user *) cmdbuf->buf;
481 507
482 /* Is it packet 3 ? */ 508 /* Is it packet 3 ? */
483 if( (header>>30)!=0x3 ) { 509 if ((header >> 30) != 0x3) {
484 DRM_ERROR("Not a packet3 header (0x%08x)\n", header); 510 DRM_ERROR("Not a packet3 header (0x%08x)\n", header);
485 return DRM_ERR(EINVAL); 511 return DRM_ERR(EINVAL);
486 } 512 }
487 513
488 count=(header>>16) & 0x3fff; 514 count = (header >> 16) & 0x3fff;
489 515
490 /* Check again now that we know how much data to expect */ 516 /* Check again now that we know how much data to expect */
491 if ((count+2)*4 > cmdbuf->bufsz){ 517 if ((count + 2) * 4 > cmdbuf->bufsz) {
492 DRM_ERROR("Expected packet3 of length %d but have only %d bytes left\n", 518 DRM_ERROR
493 (count+2)*4, cmdbuf->bufsz); 519 ("Expected packet3 of length %d but have only %d bytes left\n",
520 (count + 2) * 4, cmdbuf->bufsz);
494 return DRM_ERR(EINVAL); 521 return DRM_ERR(EINVAL);
495 } 522 }
496 523
497 /* Is it a packet type we know about ? */ 524 /* Is it a packet type we know about ? */
498 switch(header & 0xff00){ 525 switch (header & 0xff00) {
499 case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */ 526 case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */
500 return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, header); 527 return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, header);
501 528
502 case RADEON_CP_3D_DRAW_IMMD_2: /* triggers drawing using in-packet vertex data */ 529 case RADEON_CP_3D_DRAW_IMMD_2: /* triggers drawing using in-packet vertex data */
503 case RADEON_CP_3D_DRAW_VBUF_2: /* triggers drawing of vertex buffers setup elsewhere */ 530 case RADEON_CP_3D_DRAW_VBUF_2: /* triggers drawing of vertex buffers setup elsewhere */
504 case RADEON_CP_3D_DRAW_INDX_2: /* triggers drawing using indices to vertex buffer */ 531 case RADEON_CP_3D_DRAW_INDX_2: /* triggers drawing using indices to vertex buffer */
505 case RADEON_CP_INDX_BUFFER: /* DRAW_INDX_2 without INDX_BUFFER seems to lock up the gpu */ 532 case RADEON_CP_INDX_BUFFER: /* DRAW_INDX_2 without INDX_BUFFER seems to lock up the gpu */
506 case RADEON_WAIT_FOR_IDLE: 533 case RADEON_WAIT_FOR_IDLE:
507 case RADEON_CP_NOP: 534 case RADEON_CP_NOP:
508 /* these packets are safe */ 535 /* these packets are safe */
@@ -510,32 +537,30 @@ static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t* dev_priv,
510 default: 537 default:
511 DRM_ERROR("Unknown packet3 header (0x%08x)\n", header); 538 DRM_ERROR("Unknown packet3 header (0x%08x)\n", header);
512 return DRM_ERR(EINVAL); 539 return DRM_ERR(EINVAL);
513 } 540 }
514
515 541
516 BEGIN_RING(count+2); 542 BEGIN_RING(count + 2);
517 OUT_RING(header); 543 OUT_RING(header);
518 OUT_RING_TABLE( (int __user*)(cmdbuf->buf+4), count+1); 544 OUT_RING_TABLE((int __user *)(cmdbuf->buf + 4), count + 1);
519 ADVANCE_RING(); 545 ADVANCE_RING();
520 546
521 cmdbuf->buf += (count+2)*4; 547 cmdbuf->buf += (count + 2) * 4;
522 cmdbuf->bufsz -= (count+2)*4; 548 cmdbuf->bufsz -= (count + 2) * 4;
523 549
524 return 0; 550 return 0;
525} 551}
526 552
527
528/** 553/**
529 * Emit a rendering packet3 from userspace. 554 * Emit a rendering packet3 from userspace.
530 * Called by r300_do_cp_cmdbuf. 555 * Called by r300_do_cp_cmdbuf.
531 */ 556 */
532static __inline__ int r300_emit_packet3(drm_radeon_private_t* dev_priv, 557static __inline__ int r300_emit_packet3(drm_radeon_private_t * dev_priv,
533 drm_radeon_cmd_buffer_t* cmdbuf, 558 drm_radeon_cmd_buffer_t * cmdbuf,
534 drm_r300_cmd_header_t header) 559 drm_r300_cmd_header_t header)
535{ 560{
536 int n; 561 int n;
537 int ret; 562 int ret;
538 char __user* orig_buf = cmdbuf->buf; 563 char __user *orig_buf = cmdbuf->buf;
539 int orig_bufsz = cmdbuf->bufsz; 564 int orig_bufsz = cmdbuf->bufsz;
540 565
541 /* This is a do-while-loop so that we run the interior at least once, 566 /* This is a do-while-loop so that we run the interior at least once,
@@ -550,16 +575,16 @@ static __inline__ int r300_emit_packet3(drm_radeon_private_t* dev_priv,
550 575
551 cmdbuf->buf = orig_buf; 576 cmdbuf->buf = orig_buf;
552 cmdbuf->bufsz = orig_bufsz; 577 cmdbuf->bufsz = orig_bufsz;
553 } 578 }
554 579
555 switch(header.packet3.packet) { 580 switch (header.packet3.packet) {
556 case R300_CMD_PACKET3_CLEAR: 581 case R300_CMD_PACKET3_CLEAR:
557 DRM_DEBUG("R300_CMD_PACKET3_CLEAR\n"); 582 DRM_DEBUG("R300_CMD_PACKET3_CLEAR\n");
558 ret = r300_emit_clear(dev_priv, cmdbuf); 583 ret = r300_emit_clear(dev_priv, cmdbuf);
559 if (ret) { 584 if (ret) {
560 DRM_ERROR("r300_emit_clear failed\n"); 585 DRM_ERROR("r300_emit_clear failed\n");
561 return ret; 586 return ret;
562 } 587 }
563 break; 588 break;
564 589
565 case R300_CMD_PACKET3_RAW: 590 case R300_CMD_PACKET3_RAW:
@@ -568,18 +593,18 @@ static __inline__ int r300_emit_packet3(drm_radeon_private_t* dev_priv,
568 if (ret) { 593 if (ret) {
569 DRM_ERROR("r300_emit_raw_packet3 failed\n"); 594 DRM_ERROR("r300_emit_raw_packet3 failed\n");
570 return ret; 595 return ret;
571 } 596 }
572 break; 597 break;
573 598
574 default: 599 default:
575 DRM_ERROR("bad packet3 type %i at %p\n", 600 DRM_ERROR("bad packet3 type %i at %p\n",
576 header.packet3.packet, 601 header.packet3.packet,
577 cmdbuf->buf - sizeof(header)); 602 cmdbuf->buf - sizeof(header));
578 return DRM_ERR(EINVAL); 603 return DRM_ERR(EINVAL);
579 } 604 }
580 605
581 n += R300_SIMULTANEOUS_CLIPRECTS; 606 n += R300_SIMULTANEOUS_CLIPRECTS;
582 } while(n < cmdbuf->nbox); 607 } while (n < cmdbuf->nbox);
583 608
584 return 0; 609 return 0;
585} 610}
@@ -598,21 +623,20 @@ static __inline__ int r300_emit_packet3(drm_radeon_private_t* dev_priv,
598/** 623/**
599 * Emit the sequence to pacify R300. 624 * Emit the sequence to pacify R300.
600 */ 625 */
601static __inline__ void r300_pacify(drm_radeon_private_t* dev_priv) 626static __inline__ void r300_pacify(drm_radeon_private_t * dev_priv)
602{ 627{
603 RING_LOCALS; 628 RING_LOCALS;
604 629
605 BEGIN_RING(6); 630 BEGIN_RING(6);
606 OUT_RING( CP_PACKET0( R300_RB3D_DSTCACHE_CTLSTAT, 0 ) ); 631 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
607 OUT_RING( 0xa ); 632 OUT_RING(0xa);
608 OUT_RING( CP_PACKET0( 0x4f18, 0 ) ); 633 OUT_RING(CP_PACKET0(0x4f18, 0));
609 OUT_RING( 0x3 ); 634 OUT_RING(0x3);
610 OUT_RING( CP_PACKET3( RADEON_CP_NOP, 0 ) ); 635 OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0));
611 OUT_RING( 0x0 ); 636 OUT_RING(0x0);
612 ADVANCE_RING(); 637 ADVANCE_RING();
613} 638}
614 639
615
616/** 640/**
617 * Called by r300_do_cp_cmdbuf to update the internal buffer age and state. 641 * Called by r300_do_cp_cmdbuf to update the internal buffer age and state.
618 * The actual age emit is done by r300_do_cp_cmdbuf, which is why you must 642 * The actual age emit is done by r300_do_cp_cmdbuf, which is why you must
@@ -628,20 +652,18 @@ static void r300_discard_buffer(drm_device_t * dev, drm_buf_t * buf)
628 buf->used = 0; 652 buf->used = 0;
629} 653}
630 654
631
632/** 655/**
633 * Parses and validates a user-supplied command buffer and emits appropriate 656 * Parses and validates a user-supplied command buffer and emits appropriate
634 * commands on the DMA ring buffer. 657 * commands on the DMA ring buffer.
635 * Called by the ioctl handler function radeon_cp_cmdbuf. 658 * Called by the ioctl handler function radeon_cp_cmdbuf.
636 */ 659 */
637int r300_do_cp_cmdbuf(drm_device_t* dev, 660int r300_do_cp_cmdbuf(drm_device_t * dev,
638 DRMFILE filp, 661 DRMFILE filp,
639 drm_file_t* filp_priv, 662 drm_file_t * filp_priv, drm_radeon_cmd_buffer_t * cmdbuf)
640 drm_radeon_cmd_buffer_t* cmdbuf)
641{ 663{
642 drm_radeon_private_t *dev_priv = dev->dev_private; 664 drm_radeon_private_t *dev_priv = dev->dev_private;
643 drm_device_dma_t *dma = dev->dma; 665 drm_device_dma_t *dma = dev->dma;
644 drm_buf_t *buf = NULL; 666 drm_buf_t *buf = NULL;
645 int emit_dispatch_age = 0; 667 int emit_dispatch_age = 0;
646 int ret = 0; 668 int ret = 0;
647 669
@@ -655,9 +677,9 @@ int r300_do_cp_cmdbuf(drm_device_t* dev,
655 ret = r300_emit_cliprects(dev_priv, cmdbuf, 0); 677 ret = r300_emit_cliprects(dev_priv, cmdbuf, 0);
656 if (ret) 678 if (ret)
657 goto cleanup; 679 goto cleanup;
658 } 680 }
659 681
660 while(cmdbuf->bufsz >= sizeof(drm_r300_cmd_header_t)) { 682 while (cmdbuf->bufsz >= sizeof(drm_r300_cmd_header_t)) {
661 int idx; 683 int idx;
662 drm_r300_cmd_header_t header; 684 drm_r300_cmd_header_t header;
663 685
@@ -666,14 +688,14 @@ int r300_do_cp_cmdbuf(drm_device_t* dev,
666 cmdbuf->buf += sizeof(header); 688 cmdbuf->buf += sizeof(header);
667 cmdbuf->bufsz -= sizeof(header); 689 cmdbuf->bufsz -= sizeof(header);
668 690
669 switch(header.header.cmd_type) { 691 switch (header.header.cmd_type) {
670 case R300_CMD_PACKET0: 692 case R300_CMD_PACKET0:
671 DRM_DEBUG("R300_CMD_PACKET0\n"); 693 DRM_DEBUG("R300_CMD_PACKET0\n");
672 ret = r300_emit_packet0(dev_priv, cmdbuf, header); 694 ret = r300_emit_packet0(dev_priv, cmdbuf, header);
673 if (ret) { 695 if (ret) {
674 DRM_ERROR("r300_emit_packet0 failed\n"); 696 DRM_ERROR("r300_emit_packet0 failed\n");
675 goto cleanup; 697 goto cleanup;
676 } 698 }
677 break; 699 break;
678 700
679 case R300_CMD_VPU: 701 case R300_CMD_VPU:
@@ -682,7 +704,7 @@ int r300_do_cp_cmdbuf(drm_device_t* dev,
682 if (ret) { 704 if (ret) {
683 DRM_ERROR("r300_emit_vpu failed\n"); 705 DRM_ERROR("r300_emit_vpu failed\n");
684 goto cleanup; 706 goto cleanup;
685 } 707 }
686 break; 708 break;
687 709
688 case R300_CMD_PACKET3: 710 case R300_CMD_PACKET3:
@@ -691,26 +713,26 @@ int r300_do_cp_cmdbuf(drm_device_t* dev,
691 if (ret) { 713 if (ret) {
692 DRM_ERROR("r300_emit_packet3 failed\n"); 714 DRM_ERROR("r300_emit_packet3 failed\n");
693 goto cleanup; 715 goto cleanup;
694 } 716 }
695 break; 717 break;
696 718
697 case R300_CMD_END3D: 719 case R300_CMD_END3D:
698 DRM_DEBUG("R300_CMD_END3D\n"); 720 DRM_DEBUG("R300_CMD_END3D\n");
699 /* TODO: 721 /* TODO:
700 Ideally userspace driver should not need to issue this call, 722 Ideally userspace driver should not need to issue this call,
701 i.e. the drm driver should issue it automatically and prevent 723 i.e. the drm driver should issue it automatically and prevent
702 lockups. 724 lockups.
703 725
704 In practice, we do not understand why this call is needed and what 726 In practice, we do not understand why this call is needed and what
705 it does (except for some vague guesses that it has to do with cache 727 it does (except for some vague guesses that it has to do with cache
706 coherence) and so the user space driver does it. 728 coherence) and so the user space driver does it.
707 729
708 Once we are sure which uses prevent lockups the code could be moved 730 Once we are sure which uses prevent lockups the code could be moved
709 into the kernel and the userspace driver will not 731 into the kernel and the userspace driver will not
710 need to use this command. 732 need to use this command.
711 733
712 Note that issuing this command does not hurt anything 734 Note that issuing this command does not hurt anything
713 except, possibly, performance */ 735 except, possibly, performance */
714 r300_pacify(dev_priv); 736 r300_pacify(dev_priv);
715 break; 737 break;
716 738
@@ -722,7 +744,7 @@ int r300_do_cp_cmdbuf(drm_device_t* dev,
722 RING_LOCALS; 744 RING_LOCALS;
723 745
724 BEGIN_RING(header.delay.count); 746 BEGIN_RING(header.delay.count);
725 for(i=0;i<header.delay.count;i++) 747 for (i = 0; i < header.delay.count; i++)
726 OUT_RING(RADEON_CP_PACKET2); 748 OUT_RING(RADEON_CP_PACKET2);
727 ADVANCE_RING(); 749 ADVANCE_RING();
728 } 750 }
@@ -730,53 +752,54 @@ int r300_do_cp_cmdbuf(drm_device_t* dev,
730 752
731 case R300_CMD_DMA_DISCARD: 753 case R300_CMD_DMA_DISCARD:
732 DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n"); 754 DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
733 idx = header.dma.buf_idx; 755 idx = header.dma.buf_idx;
734 if (idx < 0 || idx >= dma->buf_count) { 756 if (idx < 0 || idx >= dma->buf_count) {
735 DRM_ERROR("buffer index %d (of %d max)\n", 757 DRM_ERROR("buffer index %d (of %d max)\n",
736 idx, dma->buf_count - 1); 758 idx, dma->buf_count - 1);
737 ret = DRM_ERR(EINVAL); 759 ret = DRM_ERR(EINVAL);
738 goto cleanup;
739 }
740
741 buf = dma->buflist[idx];
742 if (buf->filp != filp || buf->pending) {
743 DRM_ERROR("bad buffer %p %p %d\n",
744 buf->filp, filp, buf->pending);
745 ret = DRM_ERR(EINVAL);
746 goto cleanup; 760 goto cleanup;
747 } 761 }
762
763 buf = dma->buflist[idx];
764 if (buf->filp != filp || buf->pending) {
765 DRM_ERROR("bad buffer %p %p %d\n",
766 buf->filp, filp, buf->pending);
767 ret = DRM_ERR(EINVAL);
768 goto cleanup;
769 }
748 770
749 emit_dispatch_age = 1; 771 emit_dispatch_age = 1;
750 r300_discard_buffer(dev, buf); 772 r300_discard_buffer(dev, buf);
751 break; 773 break;
752 774
753 case R300_CMD_WAIT: 775 case R300_CMD_WAIT:
754 /* simple enough, we can do it here */ 776 /* simple enough, we can do it here */
755 DRM_DEBUG("R300_CMD_WAIT\n"); 777 DRM_DEBUG("R300_CMD_WAIT\n");
756 if(header.wait.flags==0)break; /* nothing to do */ 778 if (header.wait.flags == 0)
779 break; /* nothing to do */
757 780
758 { 781 {
759 RING_LOCALS; 782 RING_LOCALS;
760 783
761 BEGIN_RING(2); 784 BEGIN_RING(2);
762 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); 785 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
763 OUT_RING( (header.wait.flags & 0xf)<<14 ); 786 OUT_RING((header.wait.flags & 0xf) << 14);
764 ADVANCE_RING(); 787 ADVANCE_RING();
765 } 788 }
766 break; 789 break;
767 790
768 default: 791 default:
769 DRM_ERROR("bad cmd_type %i at %p\n", 792 DRM_ERROR("bad cmd_type %i at %p\n",
770 header.header.cmd_type, 793 header.header.cmd_type,
771 cmdbuf->buf - sizeof(header)); 794 cmdbuf->buf - sizeof(header));
772 ret = DRM_ERR(EINVAL); 795 ret = DRM_ERR(EINVAL);
773 goto cleanup; 796 goto cleanup;
774 } 797 }
775 } 798 }
776 799
777 DRM_DEBUG("END\n"); 800 DRM_DEBUG("END\n");
778 801
779cleanup: 802 cleanup:
780 r300_pacify(dev_priv); 803 r300_pacify(dev_priv);
781 804
782 /* We emit the vertex buffer age here, outside the pacifier "brackets" 805 /* We emit the vertex buffer age here, outside the pacifier "brackets"
@@ -792,10 +815,9 @@ cleanup:
792 BEGIN_RING(2); 815 BEGIN_RING(2);
793 RADEON_DISPATCH_AGE(dev_priv->sarea_priv->last_dispatch); 816 RADEON_DISPATCH_AGE(dev_priv->sarea_priv->last_dispatch);
794 ADVANCE_RING(); 817 ADVANCE_RING();
795 } 818 }
796 819
797 COMMIT_RING(); 820 COMMIT_RING();
798 821
799 return ret; 822 return ret;
800} 823}
801
diff --git a/drivers/char/drm/r300_reg.h b/drivers/char/drm/r300_reg.h
index c3e7ca3dbe3d..e5b73c002394 100644
--- a/drivers/char/drm/r300_reg.h
+++ b/drivers/char/drm/r300_reg.h
@@ -36,7 +36,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
36# define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT 24 36# define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT 24
37# define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT 28 37# define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT 28
38 38
39
40#define R300_MC_INIT_GFX_LAT_TIMER 0x154 39#define R300_MC_INIT_GFX_LAT_TIMER 0x154
41# define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 0 40# define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 0
42# define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT 4 41# define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT 4
@@ -62,7 +61,6 @@ I am fairly certain that they are correct unless stated otherwise in comments.
62#define R300_SE_VPORT_ZSCALE 0x1DA8 61#define R300_SE_VPORT_ZSCALE 0x1DA8
63#define R300_SE_VPORT_ZOFFSET 0x1DAC 62#define R300_SE_VPORT_ZOFFSET 0x1DAC
64 63
65
66/* This register is written directly and also starts data section in many 3d CP_PACKET3's */ 64/* This register is written directly and also starts data section in many 3d CP_PACKET3's */
67#define R300_VAP_VF_CNTL 0x2084 65#define R300_VAP_VF_CNTL 0x2084
68 66
@@ -93,17 +91,17 @@ I am fairly certain that they are correct unless stated otherwise in comments.
93 91
94 /* index size - when not set the indices are assumed to be 16 bit */ 92 /* index size - when not set the indices are assumed to be 16 bit */
95# define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11) 93# define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11)
96 /* number of vertices */ 94 /* number of vertices */
97# define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16 95# define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16
98 96
99/* BEGIN: Wild guesses */ 97/* BEGIN: Wild guesses */
100#define R300_VAP_OUTPUT_VTX_FMT_0 0x2090 98#define R300_VAP_OUTPUT_VTX_FMT_0 0x2090
101# define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0) 99# define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0)
102# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT (1<<1) 100# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT (1<<1)
103# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) /* GUESS */ 101# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) /* GUESS */
104# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) /* GUESS */ 102# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) /* GUESS */
105# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) /* GUESS */ 103# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) /* GUESS */
106# define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */ 104# define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */
107 105
108#define R300_VAP_OUTPUT_VTX_FMT_1 0x2094 106#define R300_VAP_OUTPUT_VTX_FMT_1 0x2094
109# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 107# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
@@ -159,14 +157,14 @@ I am fairly certain that they are correct unless stated otherwise in comments.
159# define R300_INPUT_ROUTE_COMPONENTS_2 (1 << 0) 157# define R300_INPUT_ROUTE_COMPONENTS_2 (1 << 0)
160# define R300_INPUT_ROUTE_COMPONENTS_3 (2 << 0) 158# define R300_INPUT_ROUTE_COMPONENTS_3 (2 << 0)
161# define R300_INPUT_ROUTE_COMPONENTS_4 (3 << 0) 159# define R300_INPUT_ROUTE_COMPONENTS_4 (3 << 0)
162# define R300_INPUT_ROUTE_COMPONENTS_RGBA (4 << 0) /* GUESS */ 160# define R300_INPUT_ROUTE_COMPONENTS_RGBA (4 << 0) /* GUESS */
163# define R300_VAP_INPUT_ROUTE_IDX_SHIFT 8 161# define R300_VAP_INPUT_ROUTE_IDX_SHIFT 8
164# define R300_VAP_INPUT_ROUTE_IDX_MASK (31 << 8) /* GUESS */ 162# define R300_VAP_INPUT_ROUTE_IDX_MASK (31 << 8) /* GUESS */
165# define R300_VAP_INPUT_ROUTE_END (1 << 13) 163# define R300_VAP_INPUT_ROUTE_END (1 << 13)
166# define R300_INPUT_ROUTE_IMMEDIATE_MODE (0 << 14) /* GUESS */ 164# define R300_INPUT_ROUTE_IMMEDIATE_MODE (0 << 14) /* GUESS */
167# define R300_INPUT_ROUTE_FLOAT (1 << 14) /* GUESS */ 165# define R300_INPUT_ROUTE_FLOAT (1 << 14) /* GUESS */
168# define R300_INPUT_ROUTE_UNSIGNED_BYTE (2 << 14) /* GUESS */ 166# define R300_INPUT_ROUTE_UNSIGNED_BYTE (2 << 14) /* GUESS */
169# define R300_INPUT_ROUTE_FLOAT_COLOR (3 << 14) /* GUESS */ 167# define R300_INPUT_ROUTE_FLOAT_COLOR (3 << 14) /* GUESS */
170#define R300_VAP_INPUT_ROUTE_0_1 0x2154 168#define R300_VAP_INPUT_ROUTE_0_1 0x2154
171#define R300_VAP_INPUT_ROUTE_0_2 0x2158 169#define R300_VAP_INPUT_ROUTE_0_2 0x2158
172#define R300_VAP_INPUT_ROUTE_0_3 0x215C 170#define R300_VAP_INPUT_ROUTE_0_3 0x215C
@@ -188,12 +186,12 @@ I am fairly certain that they are correct unless stated otherwise in comments.
188# define R300_INPUT_CNTL_COLOR 0x00000004 186# define R300_INPUT_CNTL_COLOR 0x00000004
189# define R300_INPUT_CNTL_TC0 0x00000400 187# define R300_INPUT_CNTL_TC0 0x00000400
190# define R300_INPUT_CNTL_TC1 0x00000800 188# define R300_INPUT_CNTL_TC1 0x00000800
191# define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */ 189# define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */
192# define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */ 190# define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */
193# define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */ 191# define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */
194# define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */ 192# define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */
195# define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */ 193# define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */
196# define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */ 194# define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */
197 195
198/* gap */ 196/* gap */
199/* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0 197/* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0
@@ -270,12 +268,12 @@ I am fairly certain that they are correct unless stated otherwise in comments.
270// rendering commands and overwriting vertex program parameters. 268// rendering commands and overwriting vertex program parameters.
271// Therefore, I suspect writing zero to 0x2284 synchronizes the engine and 269// Therefore, I suspect writing zero to 0x2284 synchronizes the engine and
272// avoids bugs caused by still running shaders reading bad data from memory. */ 270// avoids bugs caused by still running shaders reading bad data from memory. */
273#define R300_VAP_PVS_WAITIDLE 0x2284 /* GUESS */ 271#define R300_VAP_PVS_WAITIDLE 0x2284 /* GUESS */
274 272
275/* Absolutely no clue what this register is about. */ 273/* Absolutely no clue what this register is about. */
276#define R300_VAP_UNKNOWN_2288 0x2288 274#define R300_VAP_UNKNOWN_2288 0x2288
277# define R300_2288_R300 0x00750000 /* -- nh */ 275# define R300_2288_R300 0x00750000 /* -- nh */
278# define R300_2288_RV350 0x0000FFFF /* -- Vladimir */ 276# define R300_2288_RV350 0x0000FFFF /* -- Vladimir */
279 277
280/* gap */ 278/* gap */
281/* Addresses are relative to the vertex program instruction area of the 279/* Addresses are relative to the vertex program instruction area of the
@@ -286,10 +284,10 @@ I am fairly certain that they are correct unless stated otherwise in comments.
286// experiments so far have shown that both *must* point to an instruction 284// experiments so far have shown that both *must* point to an instruction
287// inside the vertex program, otherwise the GPU locks up. 285// inside the vertex program, otherwise the GPU locks up.
288// fglrx usually sets CNTL_3_UNKNOWN to the end of the program and 286// fglrx usually sets CNTL_3_UNKNOWN to the end of the program and
289// CNTL_1_UNKNOWN points to instruction where last write to position takes place. 287// CNTL_1_UNKNOWN points to instruction where last write to position takes place.
290// Most likely this is used to ignore rest of the program in cases where group of verts arent visible. 288// Most likely this is used to ignore rest of the program in cases where group of verts arent visible.
291// For some reason this "section" is sometimes accepted other instruction that have 289// For some reason this "section" is sometimes accepted other instruction that have
292// no relationship with position calculations. 290// no relationship with position calculations.
293*/ 291*/
294#define R300_VAP_PVS_CNTL_1 0x22D0 292#define R300_VAP_PVS_CNTL_1 0x22D0
295# define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0 293# define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0
@@ -308,13 +306,13 @@ I am fairly certain that they are correct unless stated otherwise in comments.
308#define R300_VAP_VTX_COLOR_R 0x2464 306#define R300_VAP_VTX_COLOR_R 0x2464
309#define R300_VAP_VTX_COLOR_G 0x2468 307#define R300_VAP_VTX_COLOR_G 0x2468
310#define R300_VAP_VTX_COLOR_B 0x246C 308#define R300_VAP_VTX_COLOR_B 0x246C
311#define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */ 309#define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */
312#define R300_VAP_VTX_POS_0_Y_1 0x2494 310#define R300_VAP_VTX_POS_0_Y_1 0x2494
313#define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */ 311#define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */
314#define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */ 312#define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */
315#define R300_VAP_VTX_POS_0_Y_2 0x24A4 313#define R300_VAP_VTX_POS_0_Y_2 0x24A4
316#define R300_VAP_VTX_POS_0_Z_2 0x24A8 314#define R300_VAP_VTX_POS_0_Z_2 0x24A8
317#define R300_VAP_VTX_END_OF_PKT 0x24AC /* write 0 to indicate end of packet? */ 315#define R300_VAP_VTX_END_OF_PKT 0x24AC /* write 0 to indicate end of packet? */
318 316
319/* gap */ 317/* gap */
320 318
@@ -385,7 +383,6 @@ I am fairly certain that they are correct unless stated otherwise in comments.
385# define R300_GB_MSPOS1__MS_Y5_SHIFT 20 383# define R300_GB_MSPOS1__MS_Y5_SHIFT 20
386# define R300_GB_MSPOS1__MSBD1 24 384# define R300_GB_MSPOS1__MSBD1 24
387 385
388
389#define R300_GB_TILE_CONFIG 0x4018 386#define R300_GB_TILE_CONFIG 0x4018
390# define R300_GB_TILE_ENABLE (1<<0) 387# define R300_GB_TILE_ENABLE (1<<0)
391# define R300_GB_TILE_PIPE_COUNT_RV300 0 388# define R300_GB_TILE_PIPE_COUNT_RV300 0
@@ -478,9 +475,9 @@ I am fairly certain that they are correct unless stated otherwise in comments.
478// framebuffer. */ 475// framebuffer. */
479#define R300_RE_POINTSIZE 0x421C 476#define R300_RE_POINTSIZE 0x421C
480# define R300_POINTSIZE_Y_SHIFT 0 477# define R300_POINTSIZE_Y_SHIFT 0
481# define R300_POINTSIZE_Y_MASK (0xFFFF << 0) /* GUESS */ 478# define R300_POINTSIZE_Y_MASK (0xFFFF << 0) /* GUESS */
482# define R300_POINTSIZE_X_SHIFT 16 479# define R300_POINTSIZE_X_SHIFT 16
483# define R300_POINTSIZE_X_MASK (0xFFFF << 16) /* GUESS */ 480# define R300_POINTSIZE_X_MASK (0xFFFF << 16) /* GUESS */
484# define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6) 481# define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6)
485 482
486/* The line width is given in multiples of 6. 483/* The line width is given in multiples of 6.
@@ -491,7 +488,7 @@ I am fairly certain that they are correct unless stated otherwise in comments.
491*/ 488*/
492#define R300_RE_LINE_CNT 0x4234 489#define R300_RE_LINE_CNT 0x4234
493# define R300_LINESIZE_SHIFT 0 490# define R300_LINESIZE_SHIFT 0
494# define R300_LINESIZE_MASK (0xFFFF << 0) /* GUESS */ 491# define R300_LINESIZE_MASK (0xFFFF << 0) /* GUESS */
495# define R300_LINESIZE_MAX (R300_LINESIZE_MASK / 6) 492# define R300_LINESIZE_MAX (R300_LINESIZE_MASK / 6)
496# define R300_LINE_CNT_HO (1 << 16) 493# define R300_LINE_CNT_HO (1 << 16)
497# define R300_LINE_CNT_VE (1 << 17) 494# define R300_LINE_CNT_VE (1 << 17)
@@ -513,8 +510,8 @@ I am fairly certain that they are correct unless stated otherwise in comments.
513# define R300_PM_BACK_LINE (1 << 7) 510# define R300_PM_BACK_LINE (1 << 7)
514# define R300_PM_BACK_FILL (1 << 8) 511# define R300_PM_BACK_FILL (1 << 8)
515 512
516/* Not sure why there are duplicate of factor and constant values. 513/* Not sure why there are duplicate of factor and constant values.
517 My best guess so far is that there are seperate zbiases for test and write. 514 My best guess so far is that there are seperate zbiases for test and write.
518 Ordering might be wrong. 515 Ordering might be wrong.
519 Some of the tests indicate that fgl has a fallback implementation of zbias 516 Some of the tests indicate that fgl has a fallback implementation of zbias
520 via pixel shaders. */ 517 via pixel shaders. */
@@ -540,7 +537,6 @@ I am fairly certain that they are correct unless stated otherwise in comments.
540# define R300_FRONT_FACE_CCW (0 << 2) 537# define R300_FRONT_FACE_CCW (0 << 2)
541# define R300_FRONT_FACE_CW (1 << 2) 538# define R300_FRONT_FACE_CW (1 << 2)
542 539
543
544/* BEGIN: Rasterization / Interpolators - many guesses 540/* BEGIN: Rasterization / Interpolators - many guesses
545// 0_UNKNOWN_18 has always been set except for clear operations. 541// 0_UNKNOWN_18 has always been set except for clear operations.
546// TC_CNT is the number of incoming texture coordinate sets (i.e. it depends 542// TC_CNT is the number of incoming texture coordinate sets (i.e. it depends
@@ -548,7 +544,7 @@ I am fairly certain that they are correct unless stated otherwise in comments.
548#define R300_RS_CNTL_0 0x4300 544#define R300_RS_CNTL_0 0x4300
549# define R300_RS_CNTL_TC_CNT_SHIFT 2 545# define R300_RS_CNTL_TC_CNT_SHIFT 2
550# define R300_RS_CNTL_TC_CNT_MASK (7 << 2) 546# define R300_RS_CNTL_TC_CNT_MASK (7 << 2)
551# define R300_RS_CNTL_CI_CNT_SHIFT 7 /* number of color interpolators used */ 547# define R300_RS_CNTL_CI_CNT_SHIFT 7 /* number of color interpolators used */
552# define R300_RS_CNTL_0_UNKNOWN_18 (1 << 18) 548# define R300_RS_CNTL_0_UNKNOWN_18 (1 << 18)
553/* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n register. */ 549/* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n register. */
554#define R300_RS_CNTL_1 0x4304 550#define R300_RS_CNTL_1 0x4304
@@ -585,29 +581,29 @@ I am fairly certain that they are correct unless stated otherwise in comments.
585#define R300_RS_ROUTE_0 0x4330 581#define R300_RS_ROUTE_0 0x4330
586#define R300_RS_ROUTE_1 0x4334 582#define R300_RS_ROUTE_1 0x4334
587#define R300_RS_ROUTE_2 0x4338 583#define R300_RS_ROUTE_2 0x4338
588#define R300_RS_ROUTE_3 0x433C /* GUESS */ 584#define R300_RS_ROUTE_3 0x433C /* GUESS */
589#define R300_RS_ROUTE_4 0x4340 /* GUESS */ 585#define R300_RS_ROUTE_4 0x4340 /* GUESS */
590#define R300_RS_ROUTE_5 0x4344 /* GUESS */ 586#define R300_RS_ROUTE_5 0x4344 /* GUESS */
591#define R300_RS_ROUTE_6 0x4348 /* GUESS */ 587#define R300_RS_ROUTE_6 0x4348 /* GUESS */
592#define R300_RS_ROUTE_7 0x434C /* GUESS */ 588#define R300_RS_ROUTE_7 0x434C /* GUESS */
593# define R300_RS_ROUTE_SOURCE_INTERP_0 0 589# define R300_RS_ROUTE_SOURCE_INTERP_0 0
594# define R300_RS_ROUTE_SOURCE_INTERP_1 1 590# define R300_RS_ROUTE_SOURCE_INTERP_1 1
595# define R300_RS_ROUTE_SOURCE_INTERP_2 2 591# define R300_RS_ROUTE_SOURCE_INTERP_2 2
596# define R300_RS_ROUTE_SOURCE_INTERP_3 3 592# define R300_RS_ROUTE_SOURCE_INTERP_3 3
597# define R300_RS_ROUTE_SOURCE_INTERP_4 4 593# define R300_RS_ROUTE_SOURCE_INTERP_4 4
598# define R300_RS_ROUTE_SOURCE_INTERP_5 5 /* GUESS */ 594# define R300_RS_ROUTE_SOURCE_INTERP_5 5 /* GUESS */
599# define R300_RS_ROUTE_SOURCE_INTERP_6 6 /* GUESS */ 595# define R300_RS_ROUTE_SOURCE_INTERP_6 6 /* GUESS */
600# define R300_RS_ROUTE_SOURCE_INTERP_7 7 /* GUESS */ 596# define R300_RS_ROUTE_SOURCE_INTERP_7 7 /* GUESS */
601# define R300_RS_ROUTE_ENABLE (1 << 3) /* GUESS */ 597# define R300_RS_ROUTE_ENABLE (1 << 3) /* GUESS */
602# define R300_RS_ROUTE_DEST_SHIFT 6 598# define R300_RS_ROUTE_DEST_SHIFT 6
603# define R300_RS_ROUTE_DEST_MASK (31 << 6) /* GUESS */ 599# define R300_RS_ROUTE_DEST_MASK (31 << 6) /* GUESS */
604 600
605/* Special handling for color: When the fragment program uses color, 601/* Special handling for color: When the fragment program uses color,
606// the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the 602// the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the
607// color register index. */ 603// color register index. */
608# define R300_RS_ROUTE_0_COLOR (1 << 14) 604# define R300_RS_ROUTE_0_COLOR (1 << 14)
609# define R300_RS_ROUTE_0_COLOR_DEST_SHIFT 17 605# define R300_RS_ROUTE_0_COLOR_DEST_SHIFT 17
610# define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 17) /* GUESS */ 606# define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 17) /* GUESS */
611/* As above, but for secondary color */ 607/* As above, but for secondary color */
612# define R300_RS_ROUTE_1_COLOR1 (1 << 14) 608# define R300_RS_ROUTE_1_COLOR1 (1 << 14)
613# define R300_RS_ROUTE_1_COLOR1_DEST_SHIFT 17 609# define R300_RS_ROUTE_1_COLOR1_DEST_SHIFT 17
@@ -721,7 +717,7 @@ I am fairly certain that they are correct unless stated otherwise in comments.
721# define R300_TX_HEIGHTMASK_SHIFT 11 717# define R300_TX_HEIGHTMASK_SHIFT 11
722# define R300_TX_HEIGHTMASK_MASK (2047 << 11) 718# define R300_TX_HEIGHTMASK_MASK (2047 << 11)
723# define R300_TX_UNK23 (1 << 23) 719# define R300_TX_UNK23 (1 << 23)
724# define R300_TX_SIZE_SHIFT 26 /* largest of width, height */ 720# define R300_TX_SIZE_SHIFT 26 /* largest of width, height */
725# define R300_TX_SIZE_MASK (15 << 26) 721# define R300_TX_SIZE_MASK (15 << 26)
726#define R300_TX_FORMAT_0 0x44C0 722#define R300_TX_FORMAT_0 0x44C0
727 /* The interpretation of the format word by Wladimir van der Laan */ 723 /* The interpretation of the format word by Wladimir van der Laan */
@@ -746,12 +742,12 @@ I am fairly certain that they are correct unless stated otherwise in comments.
746# define R300_TX_FORMAT_DXT1 0xF 742# define R300_TX_FORMAT_DXT1 0xF
747# define R300_TX_FORMAT_DXT3 0x10 743# define R300_TX_FORMAT_DXT3 0x10
748# define R300_TX_FORMAT_DXT5 0x11 744# define R300_TX_FORMAT_DXT5 0x11
749# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ 745# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */
750# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ 746# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */
751# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ 747# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */
752# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ 748# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */
753 /* 0x16 - some 16 bit green format.. ?? */ 749 /* 0x16 - some 16 bit green format.. ?? */
754# define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */ 750# define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */
755 751
756 /* gap */ 752 /* gap */
757 /* Floating point formats */ 753 /* Floating point formats */
@@ -777,8 +773,8 @@ I am fairly certain that they are correct unless stated otherwise in comments.
777# define R300_TX_FORMAT_W 3 773# define R300_TX_FORMAT_W 3
778# define R300_TX_FORMAT_ZERO 4 774# define R300_TX_FORMAT_ZERO 4
779# define R300_TX_FORMAT_ONE 5 775# define R300_TX_FORMAT_ONE 5
780# define R300_TX_FORMAT_CUT_Z 6 /* 2.0*Z, everything above 1.0 is set to 0.0 */ 776# define R300_TX_FORMAT_CUT_Z 6 /* 2.0*Z, everything above 1.0 is set to 0.0 */
781# define R300_TX_FORMAT_CUT_W 7 /* 2.0*W, everything above 1.0 is set to 0.0 */ 777# define R300_TX_FORMAT_CUT_W 7 /* 2.0*W, everything above 1.0 is set to 0.0 */
782 778
783# define R300_TX_FORMAT_B_SHIFT 18 779# define R300_TX_FORMAT_B_SHIFT 18
784# define R300_TX_FORMAT_G_SHIFT 15 780# define R300_TX_FORMAT_G_SHIFT 15
@@ -811,7 +807,7 @@ I am fairly certain that they are correct unless stated otherwise in comments.
811# define R300_TXO_OFFSET_SHIFT 5 807# define R300_TXO_OFFSET_SHIFT 5
812/* END */ 808/* END */
813#define R300_TX_UNK4_0 0x4580 809#define R300_TX_UNK4_0 0x4580
814#define R300_TX_BORDER_COLOR_0 0x45C0 //ff00ff00 == { 0, 1.0, 0, 1.0 } 810#define R300_TX_BORDER_COLOR_0 0x45C0 //ff00ff00 == { 0, 1.0, 0, 1.0 }
815 811
816/* END */ 812/* END */
817 813
@@ -844,9 +840,9 @@ I am fairly certain that they are correct unless stated otherwise in comments.
844# define R300_PFS_CNTL_ALU_END_SHIFT 6 840# define R300_PFS_CNTL_ALU_END_SHIFT 6
845# define R300_PFS_CNTL_ALU_END_MASK (63 << 0) 841# define R300_PFS_CNTL_ALU_END_MASK (63 << 0)
846# define R300_PFS_CNTL_TEX_OFFSET_SHIFT 12 842# define R300_PFS_CNTL_TEX_OFFSET_SHIFT 12
847# define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 12) /* GUESS */ 843# define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 12) /* GUESS */
848# define R300_PFS_CNTL_TEX_END_SHIFT 18 844# define R300_PFS_CNTL_TEX_END_SHIFT 18
849# define R300_PFS_CNTL_TEX_END_MASK (31 << 18) /* GUESS */ 845# define R300_PFS_CNTL_TEX_END_MASK (31 << 18) /* GUESS */
850 846
851/* gap */ 847/* gap */
852/* Nodes are stored backwards. The last active node is always stored in 848/* Nodes are stored backwards. The last active node is always stored in
@@ -877,11 +873,11 @@ I am fairly certain that they are correct unless stated otherwise in comments.
877#define R300_PFS_TEXI_0 0x4620 873#define R300_PFS_TEXI_0 0x4620
878# define R300_FPITX_SRC_SHIFT 0 874# define R300_FPITX_SRC_SHIFT 0
879# define R300_FPITX_SRC_MASK (31 << 0) 875# define R300_FPITX_SRC_MASK (31 << 0)
880# define R300_FPITX_SRC_CONST (1 << 5) /* GUESS */ 876# define R300_FPITX_SRC_CONST (1 << 5) /* GUESS */
881# define R300_FPITX_DST_SHIFT 6 877# define R300_FPITX_DST_SHIFT 6
882# define R300_FPITX_DST_MASK (31 << 6) 878# define R300_FPITX_DST_MASK (31 << 6)
883# define R300_FPITX_IMAGE_SHIFT 11 879# define R300_FPITX_IMAGE_SHIFT 11
884# define R300_FPITX_IMAGE_MASK (15 << 11) /* GUESS based on layout and native limits */ 880# define R300_FPITX_IMAGE_MASK (15 << 11) /* GUESS based on layout and native limits */
885/* Unsure if these are opcodes, or some kind of bitfield, but this is how 881/* Unsure if these are opcodes, or some kind of bitfield, but this is how
886 * they were set when I checked 882 * they were set when I checked
887 */ 883 */
@@ -1003,7 +999,7 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1003# define R300_FPI0_ARGC_SRC1C_LRP 15 999# define R300_FPI0_ARGC_SRC1C_LRP 15
1004# define R300_FPI0_ARGC_ZERO 20 1000# define R300_FPI0_ARGC_ZERO 20
1005# define R300_FPI0_ARGC_ONE 21 1001# define R300_FPI0_ARGC_ONE 21
1006# define R300_FPI0_ARGC_HALF 22 /* GUESS */ 1002# define R300_FPI0_ARGC_HALF 22 /* GUESS */
1007# define R300_FPI0_ARGC_SRC0C_YZX 23 1003# define R300_FPI0_ARGC_SRC0C_YZX 23
1008# define R300_FPI0_ARGC_SRC1C_YZX 24 1004# define R300_FPI0_ARGC_SRC1C_YZX 24
1009# define R300_FPI0_ARGC_SRC2C_YZX 25 1005# define R300_FPI0_ARGC_SRC2C_YZX 25
@@ -1054,20 +1050,20 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1054# define R300_FPI2_ARGA_SRC1A_LRP 15 1050# define R300_FPI2_ARGA_SRC1A_LRP 15
1055# define R300_FPI2_ARGA_ZERO 16 1051# define R300_FPI2_ARGA_ZERO 16
1056# define R300_FPI2_ARGA_ONE 17 1052# define R300_FPI2_ARGA_ONE 17
1057# define R300_FPI2_ARGA_HALF 18 /* GUESS */ 1053# define R300_FPI2_ARGA_HALF 18 /* GUESS */
1058 1054
1059# define R300_FPI2_ARG0A_SHIFT 0 1055# define R300_FPI2_ARG0A_SHIFT 0
1060# define R300_FPI2_ARG0A_MASK (31 << 0) 1056# define R300_FPI2_ARG0A_MASK (31 << 0)
1061# define R300_FPI2_ARG0A_NEG (1 << 5) 1057# define R300_FPI2_ARG0A_NEG (1 << 5)
1062# define R300_FPI2_ARG0A_ABS (1 << 6) /* GUESS */ 1058# define R300_FPI2_ARG0A_ABS (1 << 6) /* GUESS */
1063# define R300_FPI2_ARG1A_SHIFT 7 1059# define R300_FPI2_ARG1A_SHIFT 7
1064# define R300_FPI2_ARG1A_MASK (31 << 7) 1060# define R300_FPI2_ARG1A_MASK (31 << 7)
1065# define R300_FPI2_ARG1A_NEG (1 << 12) 1061# define R300_FPI2_ARG1A_NEG (1 << 12)
1066# define R300_FPI2_ARG1A_ABS (1 << 13) /* GUESS */ 1062# define R300_FPI2_ARG1A_ABS (1 << 13) /* GUESS */
1067# define R300_FPI2_ARG2A_SHIFT 14 1063# define R300_FPI2_ARG2A_SHIFT 14
1068# define R300_FPI2_ARG2A_MASK (31 << 14) 1064# define R300_FPI2_ARG2A_MASK (31 << 14)
1069# define R300_FPI2_ARG2A_NEG (1 << 19) 1065# define R300_FPI2_ARG2A_NEG (1 << 19)
1070# define R300_FPI2_ARG2A_ABS (1 << 20) /* GUESS */ 1066# define R300_FPI2_ARG2A_ABS (1 << 20) /* GUESS */
1071# define R300_FPI2_SPECIAL_LRP (1 << 21) 1067# define R300_FPI2_SPECIAL_LRP (1 << 21)
1072# define R300_FPI2_OUTA_MAD (0 << 23) 1068# define R300_FPI2_OUTA_MAD (0 << 23)
1073# define R300_FPI2_OUTA_DP4 (1 << 23) 1069# define R300_FPI2_OUTA_DP4 (1 << 23)
@@ -1157,26 +1153,26 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1157 1153
1158/* gap */ 1154/* gap */
1159#define R300_RB3D_COLOROFFSET0 0x4E28 1155#define R300_RB3D_COLOROFFSET0 0x4E28
1160# define R300_COLOROFFSET_MASK 0xFFFFFFF0 /* GUESS */ 1156# define R300_COLOROFFSET_MASK 0xFFFFFFF0 /* GUESS */
1161#define R300_RB3D_COLOROFFSET1 0x4E2C /* GUESS */ 1157#define R300_RB3D_COLOROFFSET1 0x4E2C /* GUESS */
1162#define R300_RB3D_COLOROFFSET2 0x4E30 /* GUESS */ 1158#define R300_RB3D_COLOROFFSET2 0x4E30 /* GUESS */
1163#define R300_RB3D_COLOROFFSET3 0x4E34 /* GUESS */ 1159#define R300_RB3D_COLOROFFSET3 0x4E34 /* GUESS */
1164/* gap */ 1160/* gap */
1165/* Bit 16: Larger tiles 1161/* Bit 16: Larger tiles
1166// Bit 17: 4x2 tiles 1162// Bit 17: 4x2 tiles
1167// Bit 18: Extremely weird tile like, but some pixels duplicated? */ 1163// Bit 18: Extremely weird tile like, but some pixels duplicated? */
1168#define R300_RB3D_COLORPITCH0 0x4E38 1164#define R300_RB3D_COLORPITCH0 0x4E38
1169# define R300_COLORPITCH_MASK 0x00001FF8 /* GUESS */ 1165# define R300_COLORPITCH_MASK 0x00001FF8 /* GUESS */
1170# define R300_COLOR_TILE_ENABLE (1 << 16) /* GUESS */ 1166# define R300_COLOR_TILE_ENABLE (1 << 16) /* GUESS */
1171# define R300_COLOR_MICROTILE_ENABLE (1 << 17) /* GUESS */ 1167# define R300_COLOR_MICROTILE_ENABLE (1 << 17) /* GUESS */
1172# define R300_COLOR_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ 1168# define R300_COLOR_ENDIAN_NO_SWAP (0 << 18) /* GUESS */
1173# define R300_COLOR_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ 1169# define R300_COLOR_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */
1174# define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ 1170# define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */
1175# define R300_COLOR_FORMAT_RGB565 (2 << 22) 1171# define R300_COLOR_FORMAT_RGB565 (2 << 22)
1176# define R300_COLOR_FORMAT_ARGB8888 (3 << 22) 1172# define R300_COLOR_FORMAT_ARGB8888 (3 << 22)
1177#define R300_RB3D_COLORPITCH1 0x4E3C /* GUESS */ 1173#define R300_RB3D_COLORPITCH1 0x4E3C /* GUESS */
1178#define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */ 1174#define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */
1179#define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */ 1175#define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */
1180 1176
1181/* gap */ 1177/* gap */
1182/* Guess by Vladimir. 1178/* Guess by Vladimir.
@@ -1189,8 +1185,8 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1189/* There seems to be no "write only" setting, so use Z-test = ALWAYS for this. */ 1185/* There seems to be no "write only" setting, so use Z-test = ALWAYS for this. */
1190/* Bit (1<<8) is the "test" bit. so plain write is 6 - vd */ 1186/* Bit (1<<8) is the "test" bit. so plain write is 6 - vd */
1191#define R300_RB3D_ZSTENCIL_CNTL_0 0x4F00 1187#define R300_RB3D_ZSTENCIL_CNTL_0 0x4F00
1192# define R300_RB3D_Z_DISABLED_1 0x00000010 /* GUESS */ 1188# define R300_RB3D_Z_DISABLED_1 0x00000010 /* GUESS */
1193# define R300_RB3D_Z_DISABLED_2 0x00000014 /* GUESS */ 1189# define R300_RB3D_Z_DISABLED_2 0x00000014 /* GUESS */
1194# define R300_RB3D_Z_TEST 0x00000012 1190# define R300_RB3D_Z_TEST 0x00000012
1195# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016 1191# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
1196# define R300_RB3D_Z_WRITE_ONLY 0x00000006 1192# define R300_RB3D_Z_WRITE_ONLY 0x00000006
@@ -1233,8 +1229,6 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1233# define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT 21 1229# define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT 21
1234# define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT 24 1230# define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT 24
1235 1231
1236
1237
1238#define R300_RB3D_ZSTENCIL_CNTL_2 0x4F08 1232#define R300_RB3D_ZSTENCIL_CNTL_2 0x4F08
1239# define R300_RB3D_ZS2_STENCIL_REF_SHIFT 0 1233# define R300_RB3D_ZS2_STENCIL_REF_SHIFT 0
1240# define R300_RB3D_ZS2_STENCIL_MASK 0xFF 1234# define R300_RB3D_ZS2_STENCIL_MASK 0xFF
@@ -1250,12 +1244,12 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1250/* gap */ 1244/* gap */
1251#define R300_RB3D_DEPTHOFFSET 0x4F20 1245#define R300_RB3D_DEPTHOFFSET 0x4F20
1252#define R300_RB3D_DEPTHPITCH 0x4F24 1246#define R300_RB3D_DEPTHPITCH 0x4F24
1253# define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */ 1247# define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */
1254# define R300_DEPTH_TILE_ENABLE (1 << 16) /* GUESS */ 1248# define R300_DEPTH_TILE_ENABLE (1 << 16) /* GUESS */
1255# define R300_DEPTH_MICROTILE_ENABLE (1 << 17) /* GUESS */ 1249# define R300_DEPTH_MICROTILE_ENABLE (1 << 17) /* GUESS */
1256# define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ 1250# define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) /* GUESS */
1257# define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ 1251# define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */
1258# define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ 1252# define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */
1259 1253
1260/* BEGIN: Vertex program instruction set 1254/* BEGIN: Vertex program instruction set
1261// Every instruction is four dwords long: 1255// Every instruction is four dwords long:
@@ -1295,26 +1289,26 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1295#define R300_VPI_OUT_OP_MIN (8 << 0) 1289#define R300_VPI_OUT_OP_MIN (8 << 0)
1296#define R300_VPI_OUT_OP_SGE (9 << 0) 1290#define R300_VPI_OUT_OP_SGE (9 << 0)
1297#define R300_VPI_OUT_OP_SLT (10 << 0) 1291#define R300_VPI_OUT_OP_SLT (10 << 0)
1298#define R300_VPI_OUT_OP_UNK12 (12 << 0) /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */ 1292#define R300_VPI_OUT_OP_UNK12 (12 << 0) /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */
1299#define R300_VPI_OUT_OP_EXP (65 << 0) 1293#define R300_VPI_OUT_OP_EXP (65 << 0)
1300#define R300_VPI_OUT_OP_LOG (66 << 0) 1294#define R300_VPI_OUT_OP_LOG (66 << 0)
1301#define R300_VPI_OUT_OP_UNK67 (67 << 0) /* Used in fog computations, scalar(scalar) */ 1295#define R300_VPI_OUT_OP_UNK67 (67 << 0) /* Used in fog computations, scalar(scalar) */
1302#define R300_VPI_OUT_OP_LIT (68 << 0) 1296#define R300_VPI_OUT_OP_LIT (68 << 0)
1303#define R300_VPI_OUT_OP_POW (69 << 0) 1297#define R300_VPI_OUT_OP_POW (69 << 0)
1304#define R300_VPI_OUT_OP_RCP (70 << 0) 1298#define R300_VPI_OUT_OP_RCP (70 << 0)
1305#define R300_VPI_OUT_OP_RSQ (72 << 0) 1299#define R300_VPI_OUT_OP_RSQ (72 << 0)
1306#define R300_VPI_OUT_OP_UNK73 (73 << 0) /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */ 1300#define R300_VPI_OUT_OP_UNK73 (73 << 0) /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */
1307#define R300_VPI_OUT_OP_EX2 (75 << 0) 1301#define R300_VPI_OUT_OP_EX2 (75 << 0)
1308#define R300_VPI_OUT_OP_LG2 (76 << 0) 1302#define R300_VPI_OUT_OP_LG2 (76 << 0)
1309#define R300_VPI_OUT_OP_MAD_2 (128 << 0) 1303#define R300_VPI_OUT_OP_MAD_2 (128 << 0)
1310#define R300_VPI_OUT_OP_UNK129 (129 << 0) /* all temps, vector(scalar, vector, vector) */ 1304#define R300_VPI_OUT_OP_UNK129 (129 << 0) /* all temps, vector(scalar, vector, vector) */
1311 1305
1312#define R300_VPI_OUT_REG_CLASS_TEMPORARY (0 << 8) 1306#define R300_VPI_OUT_REG_CLASS_TEMPORARY (0 << 8)
1313#define R300_VPI_OUT_REG_CLASS_RESULT (2 << 8) 1307#define R300_VPI_OUT_REG_CLASS_RESULT (2 << 8)
1314#define R300_VPI_OUT_REG_CLASS_MASK (31 << 8) 1308#define R300_VPI_OUT_REG_CLASS_MASK (31 << 8)
1315 1309
1316#define R300_VPI_OUT_REG_INDEX_SHIFT 13 1310#define R300_VPI_OUT_REG_INDEX_SHIFT 13
1317#define R300_VPI_OUT_REG_INDEX_MASK (31 << 13) /* GUESS based on fglrx native limits */ 1311#define R300_VPI_OUT_REG_INDEX_MASK (31 << 13) /* GUESS based on fglrx native limits */
1318 1312
1319#define R300_VPI_OUT_WRITE_X (1 << 20) 1313#define R300_VPI_OUT_WRITE_X (1 << 20)
1320#define R300_VPI_OUT_WRITE_Y (1 << 21) 1314#define R300_VPI_OUT_WRITE_Y (1 << 21)
@@ -1325,10 +1319,10 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1325#define R300_VPI_IN_REG_CLASS_ATTRIBUTE (1 << 0) 1319#define R300_VPI_IN_REG_CLASS_ATTRIBUTE (1 << 0)
1326#define R300_VPI_IN_REG_CLASS_PARAMETER (2 << 0) 1320#define R300_VPI_IN_REG_CLASS_PARAMETER (2 << 0)
1327#define R300_VPI_IN_REG_CLASS_NONE (9 << 0) 1321#define R300_VPI_IN_REG_CLASS_NONE (9 << 0)
1328#define R300_VPI_IN_REG_CLASS_MASK (31 << 0) /* GUESS */ 1322#define R300_VPI_IN_REG_CLASS_MASK (31 << 0) /* GUESS */
1329 1323
1330#define R300_VPI_IN_REG_INDEX_SHIFT 5 1324#define R300_VPI_IN_REG_INDEX_SHIFT 5
1331#define R300_VPI_IN_REG_INDEX_MASK (255 << 5) /* GUESS based on fglrx native limits */ 1325#define R300_VPI_IN_REG_INDEX_MASK (255 << 5) /* GUESS based on fglrx native limits */
1332 1326
1333/* The R300 can select components from the input register arbitrarily. 1327/* The R300 can select components from the input register arbitrarily.
1334// Use the following constants, shifted by the component shift you 1328// Use the following constants, shifted by the component shift you
@@ -1366,7 +1360,7 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1366#define R300_PRIM_TYPE_RECT_LIST (8 << 0) 1360#define R300_PRIM_TYPE_RECT_LIST (8 << 0)
1367#define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 1361#define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
1368#define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 1362#define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
1369#define R300_PRIM_TYPE_POINT_SPRITES (11 << 0) // GUESS (based on r200) 1363#define R300_PRIM_TYPE_POINT_SPRITES (11 << 0) // GUESS (based on r200)
1370#define R300_PRIM_TYPE_LINE_LOOP (12 << 0) 1364#define R300_PRIM_TYPE_LINE_LOOP (12 << 0)
1371#define R300_PRIM_TYPE_QUADS (13 << 0) 1365#define R300_PRIM_TYPE_QUADS (13 << 0)
1372#define R300_PRIM_TYPE_QUAD_STRIP (14 << 0) 1366#define R300_PRIM_TYPE_QUAD_STRIP (14 << 0)
@@ -1376,8 +1370,8 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1376#define R300_PRIM_WALK_LIST (2 << 4) 1370#define R300_PRIM_WALK_LIST (2 << 4)
1377#define R300_PRIM_WALK_RING (3 << 4) 1371#define R300_PRIM_WALK_RING (3 << 4)
1378#define R300_PRIM_WALK_MASK (3 << 4) 1372#define R300_PRIM_WALK_MASK (3 << 4)
1379#define R300_PRIM_COLOR_ORDER_BGRA (0 << 6) // GUESS (based on r200) 1373#define R300_PRIM_COLOR_ORDER_BGRA (0 << 6) // GUESS (based on r200)
1380#define R300_PRIM_COLOR_ORDER_RGBA (1 << 6) // GUESS 1374#define R300_PRIM_COLOR_ORDER_RGBA (1 << 6) // GUESS
1381#define R300_PRIM_NUM_VERTICES_SHIFT 16 1375#define R300_PRIM_NUM_VERTICES_SHIFT 16
1382 1376
1383// Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR. 1377// Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR.
@@ -1409,4 +1403,4 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1409 1403
1410//END 1404//END
1411 1405
1412#endif /* _R300_REG_H */ 1406#endif /* _R300_REG_H */
diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c
index 6dff5e43f713..447bfbe0da8a 100644
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@ -36,788 +36,787 @@
36 36
37#define RADEON_FIFO_DEBUG 0 37#define RADEON_FIFO_DEBUG 0
38 38
39static int radeon_do_cleanup_cp( drm_device_t *dev ); 39static int radeon_do_cleanup_cp(drm_device_t * dev);
40 40
41/* CP microcode (from ATI) */ 41/* CP microcode (from ATI) */
42static u32 R200_cp_microcode[][2] = { 42static u32 R200_cp_microcode[][2] = {
43 { 0x21007000, 0000000000 }, 43 {0x21007000, 0000000000},
44 { 0x20007000, 0000000000 }, 44 {0x20007000, 0000000000},
45 { 0x000000ab, 0x00000004 }, 45 {0x000000ab, 0x00000004},
46 { 0x000000af, 0x00000004 }, 46 {0x000000af, 0x00000004},
47 { 0x66544a49, 0000000000 }, 47 {0x66544a49, 0000000000},
48 { 0x49494174, 0000000000 }, 48 {0x49494174, 0000000000},
49 { 0x54517d83, 0000000000 }, 49 {0x54517d83, 0000000000},
50 { 0x498d8b64, 0000000000 }, 50 {0x498d8b64, 0000000000},
51 { 0x49494949, 0000000000 }, 51 {0x49494949, 0000000000},
52 { 0x49da493c, 0000000000 }, 52 {0x49da493c, 0000000000},
53 { 0x49989898, 0000000000 }, 53 {0x49989898, 0000000000},
54 { 0xd34949d5, 0000000000 }, 54 {0xd34949d5, 0000000000},
55 { 0x9dc90e11, 0000000000 }, 55 {0x9dc90e11, 0000000000},
56 { 0xce9b9b9b, 0000000000 }, 56 {0xce9b9b9b, 0000000000},
57 { 0x000f0000, 0x00000016 }, 57 {0x000f0000, 0x00000016},
58 { 0x352e232c, 0000000000 }, 58 {0x352e232c, 0000000000},
59 { 0x00000013, 0x00000004 }, 59 {0x00000013, 0x00000004},
60 { 0x000f0000, 0x00000016 }, 60 {0x000f0000, 0x00000016},
61 { 0x352e272c, 0000000000 }, 61 {0x352e272c, 0000000000},
62 { 0x000f0001, 0x00000016 }, 62 {0x000f0001, 0x00000016},
63 { 0x3239362f, 0000000000 }, 63 {0x3239362f, 0000000000},
64 { 0x000077ef, 0x00000002 }, 64 {0x000077ef, 0x00000002},
65 { 0x00061000, 0x00000002 }, 65 {0x00061000, 0x00000002},
66 { 0x00000020, 0x0000001a }, 66 {0x00000020, 0x0000001a},
67 { 0x00004000, 0x0000001e }, 67 {0x00004000, 0x0000001e},
68 { 0x00061000, 0x00000002 }, 68 {0x00061000, 0x00000002},
69 { 0x00000020, 0x0000001a }, 69 {0x00000020, 0x0000001a},
70 { 0x00004000, 0x0000001e }, 70 {0x00004000, 0x0000001e},
71 { 0x00061000, 0x00000002 }, 71 {0x00061000, 0x00000002},
72 { 0x00000020, 0x0000001a }, 72 {0x00000020, 0x0000001a},
73 { 0x00004000, 0x0000001e }, 73 {0x00004000, 0x0000001e},
74 { 0x00000016, 0x00000004 }, 74 {0x00000016, 0x00000004},
75 { 0x0003802a, 0x00000002 }, 75 {0x0003802a, 0x00000002},
76 { 0x040067e0, 0x00000002 }, 76 {0x040067e0, 0x00000002},
77 { 0x00000016, 0x00000004 }, 77 {0x00000016, 0x00000004},
78 { 0x000077e0, 0x00000002 }, 78 {0x000077e0, 0x00000002},
79 { 0x00065000, 0x00000002 }, 79 {0x00065000, 0x00000002},
80 { 0x000037e1, 0x00000002 }, 80 {0x000037e1, 0x00000002},
81 { 0x040067e1, 0x00000006 }, 81 {0x040067e1, 0x00000006},
82 { 0x000077e0, 0x00000002 }, 82 {0x000077e0, 0x00000002},
83 { 0x000077e1, 0x00000002 }, 83 {0x000077e1, 0x00000002},
84 { 0x000077e1, 0x00000006 }, 84 {0x000077e1, 0x00000006},
85 { 0xffffffff, 0000000000 }, 85 {0xffffffff, 0000000000},
86 { 0x10000000, 0000000000 }, 86 {0x10000000, 0000000000},
87 { 0x0003802a, 0x00000002 }, 87 {0x0003802a, 0x00000002},
88 { 0x040067e0, 0x00000006 }, 88 {0x040067e0, 0x00000006},
89 { 0x00007675, 0x00000002 }, 89 {0x00007675, 0x00000002},
90 { 0x00007676, 0x00000002 }, 90 {0x00007676, 0x00000002},
91 { 0x00007677, 0x00000002 }, 91 {0x00007677, 0x00000002},
92 { 0x00007678, 0x00000006 }, 92 {0x00007678, 0x00000006},
93 { 0x0003802b, 0x00000002 }, 93 {0x0003802b, 0x00000002},
94 { 0x04002676, 0x00000002 }, 94 {0x04002676, 0x00000002},
95 { 0x00007677, 0x00000002 }, 95 {0x00007677, 0x00000002},
96 { 0x00007678, 0x00000006 }, 96 {0x00007678, 0x00000006},
97 { 0x0000002e, 0x00000018 }, 97 {0x0000002e, 0x00000018},
98 { 0x0000002e, 0x00000018 }, 98 {0x0000002e, 0x00000018},
99 { 0000000000, 0x00000006 }, 99 {0000000000, 0x00000006},
100 { 0x0000002f, 0x00000018 }, 100 {0x0000002f, 0x00000018},
101 { 0x0000002f, 0x00000018 }, 101 {0x0000002f, 0x00000018},
102 { 0000000000, 0x00000006 }, 102 {0000000000, 0x00000006},
103 { 0x01605000, 0x00000002 }, 103 {0x01605000, 0x00000002},
104 { 0x00065000, 0x00000002 }, 104 {0x00065000, 0x00000002},
105 { 0x00098000, 0x00000002 }, 105 {0x00098000, 0x00000002},
106 { 0x00061000, 0x00000002 }, 106 {0x00061000, 0x00000002},
107 { 0x64c0603d, 0x00000004 }, 107 {0x64c0603d, 0x00000004},
108 { 0x00080000, 0x00000016 }, 108 {0x00080000, 0x00000016},
109 { 0000000000, 0000000000 }, 109 {0000000000, 0000000000},
110 { 0x0400251d, 0x00000002 }, 110 {0x0400251d, 0x00000002},
111 { 0x00007580, 0x00000002 }, 111 {0x00007580, 0x00000002},
112 { 0x00067581, 0x00000002 }, 112 {0x00067581, 0x00000002},
113 { 0x04002580, 0x00000002 }, 113 {0x04002580, 0x00000002},
114 { 0x00067581, 0x00000002 }, 114 {0x00067581, 0x00000002},
115 { 0x00000046, 0x00000004 }, 115 {0x00000046, 0x00000004},
116 { 0x00005000, 0000000000 }, 116 {0x00005000, 0000000000},
117 { 0x00061000, 0x00000002 }, 117 {0x00061000, 0x00000002},
118 { 0x0000750e, 0x00000002 }, 118 {0x0000750e, 0x00000002},
119 { 0x00019000, 0x00000002 }, 119 {0x00019000, 0x00000002},
120 { 0x00011055, 0x00000014 }, 120 {0x00011055, 0x00000014},
121 { 0x00000055, 0x00000012 }, 121 {0x00000055, 0x00000012},
122 { 0x0400250f, 0x00000002 }, 122 {0x0400250f, 0x00000002},
123 { 0x0000504a, 0x00000004 }, 123 {0x0000504a, 0x00000004},
124 { 0x00007565, 0x00000002 }, 124 {0x00007565, 0x00000002},
125 { 0x00007566, 0x00000002 }, 125 {0x00007566, 0x00000002},
126 { 0x00000051, 0x00000004 }, 126 {0x00000051, 0x00000004},
127 { 0x01e655b4, 0x00000002 }, 127 {0x01e655b4, 0x00000002},
128 { 0x4401b0dc, 0x00000002 }, 128 {0x4401b0dc, 0x00000002},
129 { 0x01c110dc, 0x00000002 }, 129 {0x01c110dc, 0x00000002},
130 { 0x2666705d, 0x00000018 }, 130 {0x2666705d, 0x00000018},
131 { 0x040c2565, 0x00000002 }, 131 {0x040c2565, 0x00000002},
132 { 0x0000005d, 0x00000018 }, 132 {0x0000005d, 0x00000018},
133 { 0x04002564, 0x00000002 }, 133 {0x04002564, 0x00000002},
134 { 0x00007566, 0x00000002 }, 134 {0x00007566, 0x00000002},
135 { 0x00000054, 0x00000004 }, 135 {0x00000054, 0x00000004},
136 { 0x00401060, 0x00000008 }, 136 {0x00401060, 0x00000008},
137 { 0x00101000, 0x00000002 }, 137 {0x00101000, 0x00000002},
138 { 0x000d80ff, 0x00000002 }, 138 {0x000d80ff, 0x00000002},
139 { 0x00800063, 0x00000008 }, 139 {0x00800063, 0x00000008},
140 { 0x000f9000, 0x00000002 }, 140 {0x000f9000, 0x00000002},
141 { 0x000e00ff, 0x00000002 }, 141 {0x000e00ff, 0x00000002},
142 { 0000000000, 0x00000006 }, 142 {0000000000, 0x00000006},
143 { 0x00000080, 0x00000018 }, 143 {0x00000080, 0x00000018},
144 { 0x00000054, 0x00000004 }, 144 {0x00000054, 0x00000004},
145 { 0x00007576, 0x00000002 }, 145 {0x00007576, 0x00000002},
146 { 0x00065000, 0x00000002 }, 146 {0x00065000, 0x00000002},
147 { 0x00009000, 0x00000002 }, 147 {0x00009000, 0x00000002},
148 { 0x00041000, 0x00000002 }, 148 {0x00041000, 0x00000002},
149 { 0x0c00350e, 0x00000002 }, 149 {0x0c00350e, 0x00000002},
150 { 0x00049000, 0x00000002 }, 150 {0x00049000, 0x00000002},
151 { 0x00051000, 0x00000002 }, 151 {0x00051000, 0x00000002},
152 { 0x01e785f8, 0x00000002 }, 152 {0x01e785f8, 0x00000002},
153 { 0x00200000, 0x00000002 }, 153 {0x00200000, 0x00000002},
154 { 0x00600073, 0x0000000c }, 154 {0x00600073, 0x0000000c},
155 { 0x00007563, 0x00000002 }, 155 {0x00007563, 0x00000002},
156 { 0x006075f0, 0x00000021 }, 156 {0x006075f0, 0x00000021},
157 { 0x20007068, 0x00000004 }, 157 {0x20007068, 0x00000004},
158 { 0x00005068, 0x00000004 }, 158 {0x00005068, 0x00000004},
159 { 0x00007576, 0x00000002 }, 159 {0x00007576, 0x00000002},
160 { 0x00007577, 0x00000002 }, 160 {0x00007577, 0x00000002},
161 { 0x0000750e, 0x00000002 }, 161 {0x0000750e, 0x00000002},
162 { 0x0000750f, 0x00000002 }, 162 {0x0000750f, 0x00000002},
163 { 0x00a05000, 0x00000002 }, 163 {0x00a05000, 0x00000002},
164 { 0x00600076, 0x0000000c }, 164 {0x00600076, 0x0000000c},
165 { 0x006075f0, 0x00000021 }, 165 {0x006075f0, 0x00000021},
166 { 0x000075f8, 0x00000002 }, 166 {0x000075f8, 0x00000002},
167 { 0x00000076, 0x00000004 }, 167 {0x00000076, 0x00000004},
168 { 0x000a750e, 0x00000002 }, 168 {0x000a750e, 0x00000002},
169 { 0x0020750f, 0x00000002 }, 169 {0x0020750f, 0x00000002},
170 { 0x00600079, 0x00000004 }, 170 {0x00600079, 0x00000004},
171 { 0x00007570, 0x00000002 }, 171 {0x00007570, 0x00000002},
172 { 0x00007571, 0x00000002 }, 172 {0x00007571, 0x00000002},
173 { 0x00007572, 0x00000006 }, 173 {0x00007572, 0x00000006},
174 { 0x00005000, 0x00000002 }, 174 {0x00005000, 0x00000002},
175 { 0x00a05000, 0x00000002 }, 175 {0x00a05000, 0x00000002},
176 { 0x00007568, 0x00000002 }, 176 {0x00007568, 0x00000002},
177 { 0x00061000, 0x00000002 }, 177 {0x00061000, 0x00000002},
178 { 0x00000084, 0x0000000c }, 178 {0x00000084, 0x0000000c},
179 { 0x00058000, 0x00000002 }, 179 {0x00058000, 0x00000002},
180 { 0x0c607562, 0x00000002 }, 180 {0x0c607562, 0x00000002},
181 { 0x00000086, 0x00000004 }, 181 {0x00000086, 0x00000004},
182 { 0x00600085, 0x00000004 }, 182 {0x00600085, 0x00000004},
183 { 0x400070dd, 0000000000 }, 183 {0x400070dd, 0000000000},
184 { 0x000380dd, 0x00000002 }, 184 {0x000380dd, 0x00000002},
185 { 0x00000093, 0x0000001c }, 185 {0x00000093, 0x0000001c},
186 { 0x00065095, 0x00000018 }, 186 {0x00065095, 0x00000018},
187 { 0x040025bb, 0x00000002 }, 187 {0x040025bb, 0x00000002},
188 { 0x00061096, 0x00000018 }, 188 {0x00061096, 0x00000018},
189 { 0x040075bc, 0000000000 }, 189 {0x040075bc, 0000000000},
190 { 0x000075bb, 0x00000002 }, 190 {0x000075bb, 0x00000002},
191 { 0x000075bc, 0000000000 }, 191 {0x000075bc, 0000000000},
192 { 0x00090000, 0x00000006 }, 192 {0x00090000, 0x00000006},
193 { 0x00090000, 0x00000002 }, 193 {0x00090000, 0x00000002},
194 { 0x000d8002, 0x00000006 }, 194 {0x000d8002, 0x00000006},
195 { 0x00005000, 0x00000002 }, 195 {0x00005000, 0x00000002},
196 { 0x00007821, 0x00000002 }, 196 {0x00007821, 0x00000002},
197 { 0x00007800, 0000000000 }, 197 {0x00007800, 0000000000},
198 { 0x00007821, 0x00000002 }, 198 {0x00007821, 0x00000002},
199 { 0x00007800, 0000000000 }, 199 {0x00007800, 0000000000},
200 { 0x01665000, 0x00000002 }, 200 {0x01665000, 0x00000002},
201 { 0x000a0000, 0x00000002 }, 201 {0x000a0000, 0x00000002},
202 { 0x000671cc, 0x00000002 }, 202 {0x000671cc, 0x00000002},
203 { 0x0286f1cd, 0x00000002 }, 203 {0x0286f1cd, 0x00000002},
204 { 0x000000a3, 0x00000010 }, 204 {0x000000a3, 0x00000010},
205 { 0x21007000, 0000000000 }, 205 {0x21007000, 0000000000},
206 { 0x000000aa, 0x0000001c }, 206 {0x000000aa, 0x0000001c},
207 { 0x00065000, 0x00000002 }, 207 {0x00065000, 0x00000002},
208 { 0x000a0000, 0x00000002 }, 208 {0x000a0000, 0x00000002},
209 { 0x00061000, 0x00000002 }, 209 {0x00061000, 0x00000002},
210 { 0x000b0000, 0x00000002 }, 210 {0x000b0000, 0x00000002},
211 { 0x38067000, 0x00000002 }, 211 {0x38067000, 0x00000002},
212 { 0x000a00a6, 0x00000004 }, 212 {0x000a00a6, 0x00000004},
213 { 0x20007000, 0000000000 }, 213 {0x20007000, 0000000000},
214 { 0x01200000, 0x00000002 }, 214 {0x01200000, 0x00000002},
215 { 0x20077000, 0x00000002 }, 215 {0x20077000, 0x00000002},
216 { 0x01200000, 0x00000002 }, 216 {0x01200000, 0x00000002},
217 { 0x20007000, 0000000000 }, 217 {0x20007000, 0000000000},
218 { 0x00061000, 0x00000002 }, 218 {0x00061000, 0x00000002},
219 { 0x0120751b, 0x00000002 }, 219 {0x0120751b, 0x00000002},
220 { 0x8040750a, 0x00000002 }, 220 {0x8040750a, 0x00000002},
221 { 0x8040750b, 0x00000002 }, 221 {0x8040750b, 0x00000002},
222 { 0x00110000, 0x00000002 }, 222 {0x00110000, 0x00000002},
223 { 0x000380dd, 0x00000002 }, 223 {0x000380dd, 0x00000002},
224 { 0x000000bd, 0x0000001c }, 224 {0x000000bd, 0x0000001c},
225 { 0x00061096, 0x00000018 }, 225 {0x00061096, 0x00000018},
226 { 0x844075bd, 0x00000002 }, 226 {0x844075bd, 0x00000002},
227 { 0x00061095, 0x00000018 }, 227 {0x00061095, 0x00000018},
228 { 0x840075bb, 0x00000002 }, 228 {0x840075bb, 0x00000002},
229 { 0x00061096, 0x00000018 }, 229 {0x00061096, 0x00000018},
230 { 0x844075bc, 0x00000002 }, 230 {0x844075bc, 0x00000002},
231 { 0x000000c0, 0x00000004 }, 231 {0x000000c0, 0x00000004},
232 { 0x804075bd, 0x00000002 }, 232 {0x804075bd, 0x00000002},
233 { 0x800075bb, 0x00000002 }, 233 {0x800075bb, 0x00000002},
234 { 0x804075bc, 0x00000002 }, 234 {0x804075bc, 0x00000002},
235 { 0x00108000, 0x00000002 }, 235 {0x00108000, 0x00000002},
236 { 0x01400000, 0x00000002 }, 236 {0x01400000, 0x00000002},
237 { 0x006000c4, 0x0000000c }, 237 {0x006000c4, 0x0000000c},
238 { 0x20c07000, 0x00000020 }, 238 {0x20c07000, 0x00000020},
239 { 0x000000c6, 0x00000012 }, 239 {0x000000c6, 0x00000012},
240 { 0x00800000, 0x00000006 }, 240 {0x00800000, 0x00000006},
241 { 0x0080751d, 0x00000006 }, 241 {0x0080751d, 0x00000006},
242 { 0x000025bb, 0x00000002 }, 242 {0x000025bb, 0x00000002},
243 { 0x000040c0, 0x00000004 }, 243 {0x000040c0, 0x00000004},
244 { 0x0000775c, 0x00000002 }, 244 {0x0000775c, 0x00000002},
245 { 0x00a05000, 0x00000002 }, 245 {0x00a05000, 0x00000002},
246 { 0x00661000, 0x00000002 }, 246 {0x00661000, 0x00000002},
247 { 0x0460275d, 0x00000020 }, 247 {0x0460275d, 0x00000020},
248 { 0x00004000, 0000000000 }, 248 {0x00004000, 0000000000},
249 { 0x00007999, 0x00000002 }, 249 {0x00007999, 0x00000002},
250 { 0x00a05000, 0x00000002 }, 250 {0x00a05000, 0x00000002},
251 { 0x00661000, 0x00000002 }, 251 {0x00661000, 0x00000002},
252 { 0x0460299b, 0x00000020 }, 252 {0x0460299b, 0x00000020},
253 { 0x00004000, 0000000000 }, 253 {0x00004000, 0000000000},
254 { 0x01e00830, 0x00000002 }, 254 {0x01e00830, 0x00000002},
255 { 0x21007000, 0000000000 }, 255 {0x21007000, 0000000000},
256 { 0x00005000, 0x00000002 }, 256 {0x00005000, 0x00000002},
257 { 0x00038042, 0x00000002 }, 257 {0x00038042, 0x00000002},
258 { 0x040025e0, 0x00000002 }, 258 {0x040025e0, 0x00000002},
259 { 0x000075e1, 0000000000 }, 259 {0x000075e1, 0000000000},
260 { 0x00000001, 0000000000 }, 260 {0x00000001, 0000000000},
261 { 0x000380d9, 0x00000002 }, 261 {0x000380d9, 0x00000002},
262 { 0x04007394, 0000000000 }, 262 {0x04007394, 0000000000},
263 { 0000000000, 0000000000 }, 263 {0000000000, 0000000000},
264 { 0000000000, 0000000000 }, 264 {0000000000, 0000000000},
265 { 0000000000, 0000000000 }, 265 {0000000000, 0000000000},
266 { 0000000000, 0000000000 }, 266 {0000000000, 0000000000},
267 { 0000000000, 0000000000 }, 267 {0000000000, 0000000000},
268 { 0000000000, 0000000000 }, 268 {0000000000, 0000000000},
269 { 0000000000, 0000000000 }, 269 {0000000000, 0000000000},
270 { 0000000000, 0000000000 }, 270 {0000000000, 0000000000},
271 { 0000000000, 0000000000 }, 271 {0000000000, 0000000000},
272 { 0000000000, 0000000000 }, 272 {0000000000, 0000000000},
273 { 0000000000, 0000000000 }, 273 {0000000000, 0000000000},
274 { 0000000000, 0000000000 }, 274 {0000000000, 0000000000},
275 { 0000000000, 0000000000 }, 275 {0000000000, 0000000000},
276 { 0000000000, 0000000000 }, 276 {0000000000, 0000000000},
277 { 0000000000, 0000000000 }, 277 {0000000000, 0000000000},
278 { 0000000000, 0000000000 }, 278 {0000000000, 0000000000},
279 { 0000000000, 0000000000 }, 279 {0000000000, 0000000000},
280 { 0000000000, 0000000000 }, 280 {0000000000, 0000000000},
281 { 0000000000, 0000000000 }, 281 {0000000000, 0000000000},
282 { 0000000000, 0000000000 }, 282 {0000000000, 0000000000},
283 { 0000000000, 0000000000 }, 283 {0000000000, 0000000000},
284 { 0000000000, 0000000000 }, 284 {0000000000, 0000000000},
285 { 0000000000, 0000000000 }, 285 {0000000000, 0000000000},
286 { 0000000000, 0000000000 }, 286 {0000000000, 0000000000},
287 { 0000000000, 0000000000 }, 287 {0000000000, 0000000000},
288 { 0000000000, 0000000000 }, 288 {0000000000, 0000000000},
289 { 0000000000, 0000000000 }, 289 {0000000000, 0000000000},
290 { 0000000000, 0000000000 }, 290 {0000000000, 0000000000},
291 { 0000000000, 0000000000 }, 291 {0000000000, 0000000000},
292 { 0000000000, 0000000000 }, 292 {0000000000, 0000000000},
293 { 0000000000, 0000000000 }, 293 {0000000000, 0000000000},
294 { 0000000000, 0000000000 }, 294 {0000000000, 0000000000},
295 { 0000000000, 0000000000 }, 295 {0000000000, 0000000000},
296 { 0000000000, 0000000000 }, 296 {0000000000, 0000000000},
297 { 0000000000, 0000000000 }, 297 {0000000000, 0000000000},
298 { 0000000000, 0000000000 }, 298 {0000000000, 0000000000},
299}; 299};
300 300
301
302static u32 radeon_cp_microcode[][2] = { 301static u32 radeon_cp_microcode[][2] = {
303 { 0x21007000, 0000000000 }, 302 {0x21007000, 0000000000},
304 { 0x20007000, 0000000000 }, 303 {0x20007000, 0000000000},
305 { 0x000000b4, 0x00000004 }, 304 {0x000000b4, 0x00000004},
306 { 0x000000b8, 0x00000004 }, 305 {0x000000b8, 0x00000004},
307 { 0x6f5b4d4c, 0000000000 }, 306 {0x6f5b4d4c, 0000000000},
308 { 0x4c4c427f, 0000000000 }, 307 {0x4c4c427f, 0000000000},
309 { 0x5b568a92, 0000000000 }, 308 {0x5b568a92, 0000000000},
310 { 0x4ca09c6d, 0000000000 }, 309 {0x4ca09c6d, 0000000000},
311 { 0xad4c4c4c, 0000000000 }, 310 {0xad4c4c4c, 0000000000},
312 { 0x4ce1af3d, 0000000000 }, 311 {0x4ce1af3d, 0000000000},
313 { 0xd8afafaf, 0000000000 }, 312 {0xd8afafaf, 0000000000},
314 { 0xd64c4cdc, 0000000000 }, 313 {0xd64c4cdc, 0000000000},
315 { 0x4cd10d10, 0000000000 }, 314 {0x4cd10d10, 0000000000},
316 { 0x000f0000, 0x00000016 }, 315 {0x000f0000, 0x00000016},
317 { 0x362f242d, 0000000000 }, 316 {0x362f242d, 0000000000},
318 { 0x00000012, 0x00000004 }, 317 {0x00000012, 0x00000004},
319 { 0x000f0000, 0x00000016 }, 318 {0x000f0000, 0x00000016},
320 { 0x362f282d, 0000000000 }, 319 {0x362f282d, 0000000000},
321 { 0x000380e7, 0x00000002 }, 320 {0x000380e7, 0x00000002},
322 { 0x04002c97, 0x00000002 }, 321 {0x04002c97, 0x00000002},
323 { 0x000f0001, 0x00000016 }, 322 {0x000f0001, 0x00000016},
324 { 0x333a3730, 0000000000 }, 323 {0x333a3730, 0000000000},
325 { 0x000077ef, 0x00000002 }, 324 {0x000077ef, 0x00000002},
326 { 0x00061000, 0x00000002 }, 325 {0x00061000, 0x00000002},
327 { 0x00000021, 0x0000001a }, 326 {0x00000021, 0x0000001a},
328 { 0x00004000, 0x0000001e }, 327 {0x00004000, 0x0000001e},
329 { 0x00061000, 0x00000002 }, 328 {0x00061000, 0x00000002},
330 { 0x00000021, 0x0000001a }, 329 {0x00000021, 0x0000001a},
331 { 0x00004000, 0x0000001e }, 330 {0x00004000, 0x0000001e},
332 { 0x00061000, 0x00000002 }, 331 {0x00061000, 0x00000002},
333 { 0x00000021, 0x0000001a }, 332 {0x00000021, 0x0000001a},
334 { 0x00004000, 0x0000001e }, 333 {0x00004000, 0x0000001e},
335 { 0x00000017, 0x00000004 }, 334 {0x00000017, 0x00000004},
336 { 0x0003802b, 0x00000002 }, 335 {0x0003802b, 0x00000002},
337 { 0x040067e0, 0x00000002 }, 336 {0x040067e0, 0x00000002},
338 { 0x00000017, 0x00000004 }, 337 {0x00000017, 0x00000004},
339 { 0x000077e0, 0x00000002 }, 338 {0x000077e0, 0x00000002},
340 { 0x00065000, 0x00000002 }, 339 {0x00065000, 0x00000002},
341 { 0x000037e1, 0x00000002 }, 340 {0x000037e1, 0x00000002},
342 { 0x040067e1, 0x00000006 }, 341 {0x040067e1, 0x00000006},
343 { 0x000077e0, 0x00000002 }, 342 {0x000077e0, 0x00000002},
344 { 0x000077e1, 0x00000002 }, 343 {0x000077e1, 0x00000002},
345 { 0x000077e1, 0x00000006 }, 344 {0x000077e1, 0x00000006},
346 { 0xffffffff, 0000000000 }, 345 {0xffffffff, 0000000000},
347 { 0x10000000, 0000000000 }, 346 {0x10000000, 0000000000},
348 { 0x0003802b, 0x00000002 }, 347 {0x0003802b, 0x00000002},
349 { 0x040067e0, 0x00000006 }, 348 {0x040067e0, 0x00000006},
350 { 0x00007675, 0x00000002 }, 349 {0x00007675, 0x00000002},
351 { 0x00007676, 0x00000002 }, 350 {0x00007676, 0x00000002},
352 { 0x00007677, 0x00000002 }, 351 {0x00007677, 0x00000002},
353 { 0x00007678, 0x00000006 }, 352 {0x00007678, 0x00000006},
354 { 0x0003802c, 0x00000002 }, 353 {0x0003802c, 0x00000002},
355 { 0x04002676, 0x00000002 }, 354 {0x04002676, 0x00000002},
356 { 0x00007677, 0x00000002 }, 355 {0x00007677, 0x00000002},
357 { 0x00007678, 0x00000006 }, 356 {0x00007678, 0x00000006},
358 { 0x0000002f, 0x00000018 }, 357 {0x0000002f, 0x00000018},
359 { 0x0000002f, 0x00000018 }, 358 {0x0000002f, 0x00000018},
360 { 0000000000, 0x00000006 }, 359 {0000000000, 0x00000006},
361 { 0x00000030, 0x00000018 }, 360 {0x00000030, 0x00000018},
362 { 0x00000030, 0x00000018 }, 361 {0x00000030, 0x00000018},
363 { 0000000000, 0x00000006 }, 362 {0000000000, 0x00000006},
364 { 0x01605000, 0x00000002 }, 363 {0x01605000, 0x00000002},
365 { 0x00065000, 0x00000002 }, 364 {0x00065000, 0x00000002},
366 { 0x00098000, 0x00000002 }, 365 {0x00098000, 0x00000002},
367 { 0x00061000, 0x00000002 }, 366 {0x00061000, 0x00000002},
368 { 0x64c0603e, 0x00000004 }, 367 {0x64c0603e, 0x00000004},
369 { 0x000380e6, 0x00000002 }, 368 {0x000380e6, 0x00000002},
370 { 0x040025c5, 0x00000002 }, 369 {0x040025c5, 0x00000002},
371 { 0x00080000, 0x00000016 }, 370 {0x00080000, 0x00000016},
372 { 0000000000, 0000000000 }, 371 {0000000000, 0000000000},
373 { 0x0400251d, 0x00000002 }, 372 {0x0400251d, 0x00000002},
374 { 0x00007580, 0x00000002 }, 373 {0x00007580, 0x00000002},
375 { 0x00067581, 0x00000002 }, 374 {0x00067581, 0x00000002},
376 { 0x04002580, 0x00000002 }, 375 {0x04002580, 0x00000002},
377 { 0x00067581, 0x00000002 }, 376 {0x00067581, 0x00000002},
378 { 0x00000049, 0x00000004 }, 377 {0x00000049, 0x00000004},
379 { 0x00005000, 0000000000 }, 378 {0x00005000, 0000000000},
380 { 0x000380e6, 0x00000002 }, 379 {0x000380e6, 0x00000002},
381 { 0x040025c5, 0x00000002 }, 380 {0x040025c5, 0x00000002},
382 { 0x00061000, 0x00000002 }, 381 {0x00061000, 0x00000002},
383 { 0x0000750e, 0x00000002 }, 382 {0x0000750e, 0x00000002},
384 { 0x00019000, 0x00000002 }, 383 {0x00019000, 0x00000002},
385 { 0x00011055, 0x00000014 }, 384 {0x00011055, 0x00000014},
386 { 0x00000055, 0x00000012 }, 385 {0x00000055, 0x00000012},
387 { 0x0400250f, 0x00000002 }, 386 {0x0400250f, 0x00000002},
388 { 0x0000504f, 0x00000004 }, 387 {0x0000504f, 0x00000004},
389 { 0x000380e6, 0x00000002 }, 388 {0x000380e6, 0x00000002},
390 { 0x040025c5, 0x00000002 }, 389 {0x040025c5, 0x00000002},
391 { 0x00007565, 0x00000002 }, 390 {0x00007565, 0x00000002},
392 { 0x00007566, 0x00000002 }, 391 {0x00007566, 0x00000002},
393 { 0x00000058, 0x00000004 }, 392 {0x00000058, 0x00000004},
394 { 0x000380e6, 0x00000002 }, 393 {0x000380e6, 0x00000002},
395 { 0x040025c5, 0x00000002 }, 394 {0x040025c5, 0x00000002},
396 { 0x01e655b4, 0x00000002 }, 395 {0x01e655b4, 0x00000002},
397 { 0x4401b0e4, 0x00000002 }, 396 {0x4401b0e4, 0x00000002},
398 { 0x01c110e4, 0x00000002 }, 397 {0x01c110e4, 0x00000002},
399 { 0x26667066, 0x00000018 }, 398 {0x26667066, 0x00000018},
400 { 0x040c2565, 0x00000002 }, 399 {0x040c2565, 0x00000002},
401 { 0x00000066, 0x00000018 }, 400 {0x00000066, 0x00000018},
402 { 0x04002564, 0x00000002 }, 401 {0x04002564, 0x00000002},
403 { 0x00007566, 0x00000002 }, 402 {0x00007566, 0x00000002},
404 { 0x0000005d, 0x00000004 }, 403 {0x0000005d, 0x00000004},
405 { 0x00401069, 0x00000008 }, 404 {0x00401069, 0x00000008},
406 { 0x00101000, 0x00000002 }, 405 {0x00101000, 0x00000002},
407 { 0x000d80ff, 0x00000002 }, 406 {0x000d80ff, 0x00000002},
408 { 0x0080006c, 0x00000008 }, 407 {0x0080006c, 0x00000008},
409 { 0x000f9000, 0x00000002 }, 408 {0x000f9000, 0x00000002},
410 { 0x000e00ff, 0x00000002 }, 409 {0x000e00ff, 0x00000002},
411 { 0000000000, 0x00000006 }, 410 {0000000000, 0x00000006},
412 { 0x0000008f, 0x00000018 }, 411 {0x0000008f, 0x00000018},
413 { 0x0000005b, 0x00000004 }, 412 {0x0000005b, 0x00000004},
414 { 0x000380e6, 0x00000002 }, 413 {0x000380e6, 0x00000002},
415 { 0x040025c5, 0x00000002 }, 414 {0x040025c5, 0x00000002},
416 { 0x00007576, 0x00000002 }, 415 {0x00007576, 0x00000002},
417 { 0x00065000, 0x00000002 }, 416 {0x00065000, 0x00000002},
418 { 0x00009000, 0x00000002 }, 417 {0x00009000, 0x00000002},
419 { 0x00041000, 0x00000002 }, 418 {0x00041000, 0x00000002},
420 { 0x0c00350e, 0x00000002 }, 419 {0x0c00350e, 0x00000002},
421 { 0x00049000, 0x00000002 }, 420 {0x00049000, 0x00000002},
422 { 0x00051000, 0x00000002 }, 421 {0x00051000, 0x00000002},
423 { 0x01e785f8, 0x00000002 }, 422 {0x01e785f8, 0x00000002},
424 { 0x00200000, 0x00000002 }, 423 {0x00200000, 0x00000002},
425 { 0x0060007e, 0x0000000c }, 424 {0x0060007e, 0x0000000c},
426 { 0x00007563, 0x00000002 }, 425 {0x00007563, 0x00000002},
427 { 0x006075f0, 0x00000021 }, 426 {0x006075f0, 0x00000021},
428 { 0x20007073, 0x00000004 }, 427 {0x20007073, 0x00000004},
429 { 0x00005073, 0x00000004 }, 428 {0x00005073, 0x00000004},
430 { 0x000380e6, 0x00000002 }, 429 {0x000380e6, 0x00000002},
431 { 0x040025c5, 0x00000002 }, 430 {0x040025c5, 0x00000002},
432 { 0x00007576, 0x00000002 }, 431 {0x00007576, 0x00000002},
433 { 0x00007577, 0x00000002 }, 432 {0x00007577, 0x00000002},
434 { 0x0000750e, 0x00000002 }, 433 {0x0000750e, 0x00000002},
435 { 0x0000750f, 0x00000002 }, 434 {0x0000750f, 0x00000002},
436 { 0x00a05000, 0x00000002 }, 435 {0x00a05000, 0x00000002},
437 { 0x00600083, 0x0000000c }, 436 {0x00600083, 0x0000000c},
438 { 0x006075f0, 0x00000021 }, 437 {0x006075f0, 0x00000021},
439 { 0x000075f8, 0x00000002 }, 438 {0x000075f8, 0x00000002},
440 { 0x00000083, 0x00000004 }, 439 {0x00000083, 0x00000004},
441 { 0x000a750e, 0x00000002 }, 440 {0x000a750e, 0x00000002},
442 { 0x000380e6, 0x00000002 }, 441 {0x000380e6, 0x00000002},
443 { 0x040025c5, 0x00000002 }, 442 {0x040025c5, 0x00000002},
444 { 0x0020750f, 0x00000002 }, 443 {0x0020750f, 0x00000002},
445 { 0x00600086, 0x00000004 }, 444 {0x00600086, 0x00000004},
446 { 0x00007570, 0x00000002 }, 445 {0x00007570, 0x00000002},
447 { 0x00007571, 0x00000002 }, 446 {0x00007571, 0x00000002},
448 { 0x00007572, 0x00000006 }, 447 {0x00007572, 0x00000006},
449 { 0x000380e6, 0x00000002 }, 448 {0x000380e6, 0x00000002},
450 { 0x040025c5, 0x00000002 }, 449 {0x040025c5, 0x00000002},
451 { 0x00005000, 0x00000002 }, 450 {0x00005000, 0x00000002},
452 { 0x00a05000, 0x00000002 }, 451 {0x00a05000, 0x00000002},
453 { 0x00007568, 0x00000002 }, 452 {0x00007568, 0x00000002},
454 { 0x00061000, 0x00000002 }, 453 {0x00061000, 0x00000002},
455 { 0x00000095, 0x0000000c }, 454 {0x00000095, 0x0000000c},
456 { 0x00058000, 0x00000002 }, 455 {0x00058000, 0x00000002},
457 { 0x0c607562, 0x00000002 }, 456 {0x0c607562, 0x00000002},
458 { 0x00000097, 0x00000004 }, 457 {0x00000097, 0x00000004},
459 { 0x000380e6, 0x00000002 }, 458 {0x000380e6, 0x00000002},
460 { 0x040025c5, 0x00000002 }, 459 {0x040025c5, 0x00000002},
461 { 0x00600096, 0x00000004 }, 460 {0x00600096, 0x00000004},
462 { 0x400070e5, 0000000000 }, 461 {0x400070e5, 0000000000},
463 { 0x000380e6, 0x00000002 }, 462 {0x000380e6, 0x00000002},
464 { 0x040025c5, 0x00000002 }, 463 {0x040025c5, 0x00000002},
465 { 0x000380e5, 0x00000002 }, 464 {0x000380e5, 0x00000002},
466 { 0x000000a8, 0x0000001c }, 465 {0x000000a8, 0x0000001c},
467 { 0x000650aa, 0x00000018 }, 466 {0x000650aa, 0x00000018},
468 { 0x040025bb, 0x00000002 }, 467 {0x040025bb, 0x00000002},
469 { 0x000610ab, 0x00000018 }, 468 {0x000610ab, 0x00000018},
470 { 0x040075bc, 0000000000 }, 469 {0x040075bc, 0000000000},
471 { 0x000075bb, 0x00000002 }, 470 {0x000075bb, 0x00000002},
472 { 0x000075bc, 0000000000 }, 471 {0x000075bc, 0000000000},
473 { 0x00090000, 0x00000006 }, 472 {0x00090000, 0x00000006},
474 { 0x00090000, 0x00000002 }, 473 {0x00090000, 0x00000002},
475 { 0x000d8002, 0x00000006 }, 474 {0x000d8002, 0x00000006},
476 { 0x00007832, 0x00000002 }, 475 {0x00007832, 0x00000002},
477 { 0x00005000, 0x00000002 }, 476 {0x00005000, 0x00000002},
478 { 0x000380e7, 0x00000002 }, 477 {0x000380e7, 0x00000002},
479 { 0x04002c97, 0x00000002 }, 478 {0x04002c97, 0x00000002},
480 { 0x00007820, 0x00000002 }, 479 {0x00007820, 0x00000002},
481 { 0x00007821, 0x00000002 }, 480 {0x00007821, 0x00000002},
482 { 0x00007800, 0000000000 }, 481 {0x00007800, 0000000000},
483 { 0x01200000, 0x00000002 }, 482 {0x01200000, 0x00000002},
484 { 0x20077000, 0x00000002 }, 483 {0x20077000, 0x00000002},
485 { 0x01200000, 0x00000002 }, 484 {0x01200000, 0x00000002},
486 { 0x20007000, 0x00000002 }, 485 {0x20007000, 0x00000002},
487 { 0x00061000, 0x00000002 }, 486 {0x00061000, 0x00000002},
488 { 0x0120751b, 0x00000002 }, 487 {0x0120751b, 0x00000002},
489 { 0x8040750a, 0x00000002 }, 488 {0x8040750a, 0x00000002},
490 { 0x8040750b, 0x00000002 }, 489 {0x8040750b, 0x00000002},
491 { 0x00110000, 0x00000002 }, 490 {0x00110000, 0x00000002},
492 { 0x000380e5, 0x00000002 }, 491 {0x000380e5, 0x00000002},
493 { 0x000000c6, 0x0000001c }, 492 {0x000000c6, 0x0000001c},
494 { 0x000610ab, 0x00000018 }, 493 {0x000610ab, 0x00000018},
495 { 0x844075bd, 0x00000002 }, 494 {0x844075bd, 0x00000002},
496 { 0x000610aa, 0x00000018 }, 495 {0x000610aa, 0x00000018},
497 { 0x840075bb, 0x00000002 }, 496 {0x840075bb, 0x00000002},
498 { 0x000610ab, 0x00000018 }, 497 {0x000610ab, 0x00000018},
499 { 0x844075bc, 0x00000002 }, 498 {0x844075bc, 0x00000002},
500 { 0x000000c9, 0x00000004 }, 499 {0x000000c9, 0x00000004},
501 { 0x804075bd, 0x00000002 }, 500 {0x804075bd, 0x00000002},
502 { 0x800075bb, 0x00000002 }, 501 {0x800075bb, 0x00000002},
503 { 0x804075bc, 0x00000002 }, 502 {0x804075bc, 0x00000002},
504 { 0x00108000, 0x00000002 }, 503 {0x00108000, 0x00000002},
505 { 0x01400000, 0x00000002 }, 504 {0x01400000, 0x00000002},
506 { 0x006000cd, 0x0000000c }, 505 {0x006000cd, 0x0000000c},
507 { 0x20c07000, 0x00000020 }, 506 {0x20c07000, 0x00000020},
508 { 0x000000cf, 0x00000012 }, 507 {0x000000cf, 0x00000012},
509 { 0x00800000, 0x00000006 }, 508 {0x00800000, 0x00000006},
510 { 0x0080751d, 0x00000006 }, 509 {0x0080751d, 0x00000006},
511 { 0000000000, 0000000000 }, 510 {0000000000, 0000000000},
512 { 0x0000775c, 0x00000002 }, 511 {0x0000775c, 0x00000002},
513 { 0x00a05000, 0x00000002 }, 512 {0x00a05000, 0x00000002},
514 { 0x00661000, 0x00000002 }, 513 {0x00661000, 0x00000002},
515 { 0x0460275d, 0x00000020 }, 514 {0x0460275d, 0x00000020},
516 { 0x00004000, 0000000000 }, 515 {0x00004000, 0000000000},
517 { 0x01e00830, 0x00000002 }, 516 {0x01e00830, 0x00000002},
518 { 0x21007000, 0000000000 }, 517 {0x21007000, 0000000000},
519 { 0x6464614d, 0000000000 }, 518 {0x6464614d, 0000000000},
520 { 0x69687420, 0000000000 }, 519 {0x69687420, 0000000000},
521 { 0x00000073, 0000000000 }, 520 {0x00000073, 0000000000},
522 { 0000000000, 0000000000 }, 521 {0000000000, 0000000000},
523 { 0x00005000, 0x00000002 }, 522 {0x00005000, 0x00000002},
524 { 0x000380d0, 0x00000002 }, 523 {0x000380d0, 0x00000002},
525 { 0x040025e0, 0x00000002 }, 524 {0x040025e0, 0x00000002},
526 { 0x000075e1, 0000000000 }, 525 {0x000075e1, 0000000000},
527 { 0x00000001, 0000000000 }, 526 {0x00000001, 0000000000},
528 { 0x000380e0, 0x00000002 }, 527 {0x000380e0, 0x00000002},
529 { 0x04002394, 0x00000002 }, 528 {0x04002394, 0x00000002},
530 { 0x00005000, 0000000000 }, 529 {0x00005000, 0000000000},
531 { 0000000000, 0000000000 }, 530 {0000000000, 0000000000},
532 { 0000000000, 0000000000 }, 531 {0000000000, 0000000000},
533 { 0x00000008, 0000000000 }, 532 {0x00000008, 0000000000},
534 { 0x00000004, 0000000000 }, 533 {0x00000004, 0000000000},
535 { 0000000000, 0000000000 }, 534 {0000000000, 0000000000},
536 { 0000000000, 0000000000 }, 535 {0000000000, 0000000000},
537 { 0000000000, 0000000000 }, 536 {0000000000, 0000000000},
538 { 0000000000, 0000000000 }, 537 {0000000000, 0000000000},
539 { 0000000000, 0000000000 }, 538 {0000000000, 0000000000},
540 { 0000000000, 0000000000 }, 539 {0000000000, 0000000000},
541 { 0000000000, 0000000000 }, 540 {0000000000, 0000000000},
542 { 0000000000, 0000000000 }, 541 {0000000000, 0000000000},
543 { 0000000000, 0000000000 }, 542 {0000000000, 0000000000},
544 { 0000000000, 0000000000 }, 543 {0000000000, 0000000000},
545 { 0000000000, 0000000000 }, 544 {0000000000, 0000000000},
546 { 0000000000, 0000000000 }, 545 {0000000000, 0000000000},
547 { 0000000000, 0000000000 }, 546 {0000000000, 0000000000},
548 { 0000000000, 0000000000 }, 547 {0000000000, 0000000000},
549 { 0000000000, 0000000000 }, 548 {0000000000, 0000000000},
550 { 0000000000, 0000000000 }, 549 {0000000000, 0000000000},
551 { 0000000000, 0000000000 }, 550 {0000000000, 0000000000},
552 { 0000000000, 0000000000 }, 551 {0000000000, 0000000000},
553 { 0000000000, 0000000000 }, 552 {0000000000, 0000000000},
554 { 0000000000, 0000000000 }, 553 {0000000000, 0000000000},
555 { 0000000000, 0000000000 }, 554 {0000000000, 0000000000},
556 { 0000000000, 0000000000 }, 555 {0000000000, 0000000000},
557 { 0000000000, 0000000000 }, 556 {0000000000, 0000000000},
558 { 0000000000, 0000000000 }, 557 {0000000000, 0000000000},
559}; 558};
560 559
561static u32 R300_cp_microcode[][2] = { 560static u32 R300_cp_microcode[][2] = {
562 { 0x4200e000, 0000000000 }, 561 {0x4200e000, 0000000000},
563 { 0x4000e000, 0000000000 }, 562 {0x4000e000, 0000000000},
564 { 0x000000af, 0x00000008 }, 563 {0x000000af, 0x00000008},
565 { 0x000000b3, 0x00000008 }, 564 {0x000000b3, 0x00000008},
566 { 0x6c5a504f, 0000000000 }, 565 {0x6c5a504f, 0000000000},
567 { 0x4f4f497a, 0000000000 }, 566 {0x4f4f497a, 0000000000},
568 { 0x5a578288, 0000000000 }, 567 {0x5a578288, 0000000000},
569 { 0x4f91906a, 0000000000 }, 568 {0x4f91906a, 0000000000},
570 { 0x4f4f4f4f, 0000000000 }, 569 {0x4f4f4f4f, 0000000000},
571 { 0x4fe24f44, 0000000000 }, 570 {0x4fe24f44, 0000000000},
572 { 0x4f9c9c9c, 0000000000 }, 571 {0x4f9c9c9c, 0000000000},
573 { 0xdc4f4fde, 0000000000 }, 572 {0xdc4f4fde, 0000000000},
574 { 0xa1cd4f4f, 0000000000 }, 573 {0xa1cd4f4f, 0000000000},
575 { 0xd29d9d9d, 0000000000 }, 574 {0xd29d9d9d, 0000000000},
576 { 0x4f0f9fd7, 0000000000 }, 575 {0x4f0f9fd7, 0000000000},
577 { 0x000ca000, 0x00000004 }, 576 {0x000ca000, 0x00000004},
578 { 0x000d0012, 0x00000038 }, 577 {0x000d0012, 0x00000038},
579 { 0x0000e8b4, 0x00000004 }, 578 {0x0000e8b4, 0x00000004},
580 { 0x000d0014, 0x00000038 }, 579 {0x000d0014, 0x00000038},
581 { 0x0000e8b6, 0x00000004 }, 580 {0x0000e8b6, 0x00000004},
582 { 0x000d0016, 0x00000038 }, 581 {0x000d0016, 0x00000038},
583 { 0x0000e854, 0x00000004 }, 582 {0x0000e854, 0x00000004},
584 { 0x000d0018, 0x00000038 }, 583 {0x000d0018, 0x00000038},
585 { 0x0000e855, 0x00000004 }, 584 {0x0000e855, 0x00000004},
586 { 0x000d001a, 0x00000038 }, 585 {0x000d001a, 0x00000038},
587 { 0x0000e856, 0x00000004 }, 586 {0x0000e856, 0x00000004},
588 { 0x000d001c, 0x00000038 }, 587 {0x000d001c, 0x00000038},
589 { 0x0000e857, 0x00000004 }, 588 {0x0000e857, 0x00000004},
590 { 0x000d001e, 0x00000038 }, 589 {0x000d001e, 0x00000038},
591 { 0x0000e824, 0x00000004 }, 590 {0x0000e824, 0x00000004},
592 { 0x000d0020, 0x00000038 }, 591 {0x000d0020, 0x00000038},
593 { 0x0000e825, 0x00000004 }, 592 {0x0000e825, 0x00000004},
594 { 0x000d0022, 0x00000038 }, 593 {0x000d0022, 0x00000038},
595 { 0x0000e830, 0x00000004 }, 594 {0x0000e830, 0x00000004},
596 { 0x000d0024, 0x00000038 }, 595 {0x000d0024, 0x00000038},
597 { 0x0000f0c0, 0x00000004 }, 596 {0x0000f0c0, 0x00000004},
598 { 0x000d0026, 0x00000038 }, 597 {0x000d0026, 0x00000038},
599 { 0x0000f0c1, 0x00000004 }, 598 {0x0000f0c1, 0x00000004},
600 { 0x000d0028, 0x00000038 }, 599 {0x000d0028, 0x00000038},
601 { 0x0000f041, 0x00000004 }, 600 {0x0000f041, 0x00000004},
602 { 0x000d002a, 0x00000038 }, 601 {0x000d002a, 0x00000038},
603 { 0x0000f184, 0x00000004 }, 602 {0x0000f184, 0x00000004},
604 { 0x000d002c, 0x00000038 }, 603 {0x000d002c, 0x00000038},
605 { 0x0000f185, 0x00000004 }, 604 {0x0000f185, 0x00000004},
606 { 0x000d002e, 0x00000038 }, 605 {0x000d002e, 0x00000038},
607 { 0x0000f186, 0x00000004 }, 606 {0x0000f186, 0x00000004},
608 { 0x000d0030, 0x00000038 }, 607 {0x000d0030, 0x00000038},
609 { 0x0000f187, 0x00000004 }, 608 {0x0000f187, 0x00000004},
610 { 0x000d0032, 0x00000038 }, 609 {0x000d0032, 0x00000038},
611 { 0x0000f180, 0x00000004 }, 610 {0x0000f180, 0x00000004},
612 { 0x000d0034, 0x00000038 }, 611 {0x000d0034, 0x00000038},
613 { 0x0000f393, 0x00000004 }, 612 {0x0000f393, 0x00000004},
614 { 0x000d0036, 0x00000038 }, 613 {0x000d0036, 0x00000038},
615 { 0x0000f38a, 0x00000004 }, 614 {0x0000f38a, 0x00000004},
616 { 0x000d0038, 0x00000038 }, 615 {0x000d0038, 0x00000038},
617 { 0x0000f38e, 0x00000004 }, 616 {0x0000f38e, 0x00000004},
618 { 0x0000e821, 0x00000004 }, 617 {0x0000e821, 0x00000004},
619 { 0x0140a000, 0x00000004 }, 618 {0x0140a000, 0x00000004},
620 { 0x00000043, 0x00000018 }, 619 {0x00000043, 0x00000018},
621 { 0x00cce800, 0x00000004 }, 620 {0x00cce800, 0x00000004},
622 { 0x001b0001, 0x00000004 }, 621 {0x001b0001, 0x00000004},
623 { 0x08004800, 0x00000004 }, 622 {0x08004800, 0x00000004},
624 { 0x001b0001, 0x00000004 }, 623 {0x001b0001, 0x00000004},
625 { 0x08004800, 0x00000004 }, 624 {0x08004800, 0x00000004},
626 { 0x001b0001, 0x00000004 }, 625 {0x001b0001, 0x00000004},
627 { 0x08004800, 0x00000004 }, 626 {0x08004800, 0x00000004},
628 { 0x0000003a, 0x00000008 }, 627 {0x0000003a, 0x00000008},
629 { 0x0000a000, 0000000000 }, 628 {0x0000a000, 0000000000},
630 { 0x02c0a000, 0x00000004 }, 629 {0x02c0a000, 0x00000004},
631 { 0x000ca000, 0x00000004 }, 630 {0x000ca000, 0x00000004},
632 { 0x00130000, 0x00000004 }, 631 {0x00130000, 0x00000004},
633 { 0x000c2000, 0x00000004 }, 632 {0x000c2000, 0x00000004},
634 { 0xc980c045, 0x00000008 }, 633 {0xc980c045, 0x00000008},
635 { 0x2000451d, 0x00000004 }, 634 {0x2000451d, 0x00000004},
636 { 0x0000e580, 0x00000004 }, 635 {0x0000e580, 0x00000004},
637 { 0x000ce581, 0x00000004 }, 636 {0x000ce581, 0x00000004},
638 { 0x08004580, 0x00000004 }, 637 {0x08004580, 0x00000004},
639 { 0x000ce581, 0x00000004 }, 638 {0x000ce581, 0x00000004},
640 { 0x0000004c, 0x00000008 }, 639 {0x0000004c, 0x00000008},
641 { 0x0000a000, 0000000000 }, 640 {0x0000a000, 0000000000},
642 { 0x000c2000, 0x00000004 }, 641 {0x000c2000, 0x00000004},
643 { 0x0000e50e, 0x00000004 }, 642 {0x0000e50e, 0x00000004},
644 { 0x00032000, 0x00000004 }, 643 {0x00032000, 0x00000004},
645 { 0x00022056, 0x00000028 }, 644 {0x00022056, 0x00000028},
646 { 0x00000056, 0x00000024 }, 645 {0x00000056, 0x00000024},
647 { 0x0800450f, 0x00000004 }, 646 {0x0800450f, 0x00000004},
648 { 0x0000a050, 0x00000008 }, 647 {0x0000a050, 0x00000008},
649 { 0x0000e565, 0x00000004 }, 648 {0x0000e565, 0x00000004},
650 { 0x0000e566, 0x00000004 }, 649 {0x0000e566, 0x00000004},
651 { 0x00000057, 0x00000008 }, 650 {0x00000057, 0x00000008},
652 { 0x03cca5b4, 0x00000004 }, 651 {0x03cca5b4, 0x00000004},
653 { 0x05432000, 0x00000004 }, 652 {0x05432000, 0x00000004},
654 { 0x00022000, 0x00000004 }, 653 {0x00022000, 0x00000004},
655 { 0x4ccce063, 0x00000030 }, 654 {0x4ccce063, 0x00000030},
656 { 0x08274565, 0x00000004 }, 655 {0x08274565, 0x00000004},
657 { 0x00000063, 0x00000030 }, 656 {0x00000063, 0x00000030},
658 { 0x08004564, 0x00000004 }, 657 {0x08004564, 0x00000004},
659 { 0x0000e566, 0x00000004 }, 658 {0x0000e566, 0x00000004},
660 { 0x0000005a, 0x00000008 }, 659 {0x0000005a, 0x00000008},
661 { 0x00802066, 0x00000010 }, 660 {0x00802066, 0x00000010},
662 { 0x00202000, 0x00000004 }, 661 {0x00202000, 0x00000004},
663 { 0x001b00ff, 0x00000004 }, 662 {0x001b00ff, 0x00000004},
664 { 0x01000069, 0x00000010 }, 663 {0x01000069, 0x00000010},
665 { 0x001f2000, 0x00000004 }, 664 {0x001f2000, 0x00000004},
666 { 0x001c00ff, 0x00000004 }, 665 {0x001c00ff, 0x00000004},
667 { 0000000000, 0x0000000c }, 666 {0000000000, 0x0000000c},
668 { 0x00000085, 0x00000030 }, 667 {0x00000085, 0x00000030},
669 { 0x0000005a, 0x00000008 }, 668 {0x0000005a, 0x00000008},
670 { 0x0000e576, 0x00000004 }, 669 {0x0000e576, 0x00000004},
671 { 0x000ca000, 0x00000004 }, 670 {0x000ca000, 0x00000004},
672 { 0x00012000, 0x00000004 }, 671 {0x00012000, 0x00000004},
673 { 0x00082000, 0x00000004 }, 672 {0x00082000, 0x00000004},
674 { 0x1800650e, 0x00000004 }, 673 {0x1800650e, 0x00000004},
675 { 0x00092000, 0x00000004 }, 674 {0x00092000, 0x00000004},
676 { 0x000a2000, 0x00000004 }, 675 {0x000a2000, 0x00000004},
677 { 0x000f0000, 0x00000004 }, 676 {0x000f0000, 0x00000004},
678 { 0x00400000, 0x00000004 }, 677 {0x00400000, 0x00000004},
679 { 0x00000079, 0x00000018 }, 678 {0x00000079, 0x00000018},
680 { 0x0000e563, 0x00000004 }, 679 {0x0000e563, 0x00000004},
681 { 0x00c0e5f9, 0x000000c2 }, 680 {0x00c0e5f9, 0x000000c2},
682 { 0x0000006e, 0x00000008 }, 681 {0x0000006e, 0x00000008},
683 { 0x0000a06e, 0x00000008 }, 682 {0x0000a06e, 0x00000008},
684 { 0x0000e576, 0x00000004 }, 683 {0x0000e576, 0x00000004},
685 { 0x0000e577, 0x00000004 }, 684 {0x0000e577, 0x00000004},
686 { 0x0000e50e, 0x00000004 }, 685 {0x0000e50e, 0x00000004},
687 { 0x0000e50f, 0x00000004 }, 686 {0x0000e50f, 0x00000004},
688 { 0x0140a000, 0x00000004 }, 687 {0x0140a000, 0x00000004},
689 { 0x0000007c, 0x00000018 }, 688 {0x0000007c, 0x00000018},
690 { 0x00c0e5f9, 0x000000c2 }, 689 {0x00c0e5f9, 0x000000c2},
691 { 0x0000007c, 0x00000008 }, 690 {0x0000007c, 0x00000008},
692 { 0x0014e50e, 0x00000004 }, 691 {0x0014e50e, 0x00000004},
693 { 0x0040e50f, 0x00000004 }, 692 {0x0040e50f, 0x00000004},
694 { 0x00c0007f, 0x00000008 }, 693 {0x00c0007f, 0x00000008},
695 { 0x0000e570, 0x00000004 }, 694 {0x0000e570, 0x00000004},
696 { 0x0000e571, 0x00000004 }, 695 {0x0000e571, 0x00000004},
697 { 0x0000e572, 0x0000000c }, 696 {0x0000e572, 0x0000000c},
698 { 0x0000a000, 0x00000004 }, 697 {0x0000a000, 0x00000004},
699 { 0x0140a000, 0x00000004 }, 698 {0x0140a000, 0x00000004},
700 { 0x0000e568, 0x00000004 }, 699 {0x0000e568, 0x00000004},
701 { 0x000c2000, 0x00000004 }, 700 {0x000c2000, 0x00000004},
702 { 0x00000089, 0x00000018 }, 701 {0x00000089, 0x00000018},
703 { 0x000b0000, 0x00000004 }, 702 {0x000b0000, 0x00000004},
704 { 0x18c0e562, 0x00000004 }, 703 {0x18c0e562, 0x00000004},
705 { 0x0000008b, 0x00000008 }, 704 {0x0000008b, 0x00000008},
706 { 0x00c0008a, 0x00000008 }, 705 {0x00c0008a, 0x00000008},
707 { 0x000700e4, 0x00000004 }, 706 {0x000700e4, 0x00000004},
708 { 0x00000097, 0x00000038 }, 707 {0x00000097, 0x00000038},
709 { 0x000ca099, 0x00000030 }, 708 {0x000ca099, 0x00000030},
710 { 0x080045bb, 0x00000004 }, 709 {0x080045bb, 0x00000004},
711 { 0x000c209a, 0x00000030 }, 710 {0x000c209a, 0x00000030},
712 { 0x0800e5bc, 0000000000 }, 711 {0x0800e5bc, 0000000000},
713 { 0x0000e5bb, 0x00000004 }, 712 {0x0000e5bb, 0x00000004},
714 { 0x0000e5bc, 0000000000 }, 713 {0x0000e5bc, 0000000000},
715 { 0x00120000, 0x0000000c }, 714 {0x00120000, 0x0000000c},
716 { 0x00120000, 0x00000004 }, 715 {0x00120000, 0x00000004},
717 { 0x001b0002, 0x0000000c }, 716 {0x001b0002, 0x0000000c},
718 { 0x0000a000, 0x00000004 }, 717 {0x0000a000, 0x00000004},
719 { 0x0000e821, 0x00000004 }, 718 {0x0000e821, 0x00000004},
720 { 0x0000e800, 0000000000 }, 719 {0x0000e800, 0000000000},
721 { 0x0000e821, 0x00000004 }, 720 {0x0000e821, 0x00000004},
722 { 0x0000e82e, 0000000000 }, 721 {0x0000e82e, 0000000000},
723 { 0x02cca000, 0x00000004 }, 722 {0x02cca000, 0x00000004},
724 { 0x00140000, 0x00000004 }, 723 {0x00140000, 0x00000004},
725 { 0x000ce1cc, 0x00000004 }, 724 {0x000ce1cc, 0x00000004},
726 { 0x050de1cd, 0x00000004 }, 725 {0x050de1cd, 0x00000004},
727 { 0x000000a7, 0x00000020 }, 726 {0x000000a7, 0x00000020},
728 { 0x4200e000, 0000000000 }, 727 {0x4200e000, 0000000000},
729 { 0x000000ae, 0x00000038 }, 728 {0x000000ae, 0x00000038},
730 { 0x000ca000, 0x00000004 }, 729 {0x000ca000, 0x00000004},
731 { 0x00140000, 0x00000004 }, 730 {0x00140000, 0x00000004},
732 { 0x000c2000, 0x00000004 }, 731 {0x000c2000, 0x00000004},
733 { 0x00160000, 0x00000004 }, 732 {0x00160000, 0x00000004},
734 { 0x700ce000, 0x00000004 }, 733 {0x700ce000, 0x00000004},
735 { 0x001400aa, 0x00000008 }, 734 {0x001400aa, 0x00000008},
736 { 0x4000e000, 0000000000 }, 735 {0x4000e000, 0000000000},
737 { 0x02400000, 0x00000004 }, 736 {0x02400000, 0x00000004},
738 { 0x400ee000, 0x00000004 }, 737 {0x400ee000, 0x00000004},
739 { 0x02400000, 0x00000004 }, 738 {0x02400000, 0x00000004},
740 { 0x4000e000, 0000000000 }, 739 {0x4000e000, 0000000000},
741 { 0x000c2000, 0x00000004 }, 740 {0x000c2000, 0x00000004},
742 { 0x0240e51b, 0x00000004 }, 741 {0x0240e51b, 0x00000004},
743 { 0x0080e50a, 0x00000005 }, 742 {0x0080e50a, 0x00000005},
744 { 0x0080e50b, 0x00000005 }, 743 {0x0080e50b, 0x00000005},
745 { 0x00220000, 0x00000004 }, 744 {0x00220000, 0x00000004},
746 { 0x000700e4, 0x00000004 }, 745 {0x000700e4, 0x00000004},
747 { 0x000000c1, 0x00000038 }, 746 {0x000000c1, 0x00000038},
748 { 0x000c209a, 0x00000030 }, 747 {0x000c209a, 0x00000030},
749 { 0x0880e5bd, 0x00000005 }, 748 {0x0880e5bd, 0x00000005},
750 { 0x000c2099, 0x00000030 }, 749 {0x000c2099, 0x00000030},
751 { 0x0800e5bb, 0x00000005 }, 750 {0x0800e5bb, 0x00000005},
752 { 0x000c209a, 0x00000030 }, 751 {0x000c209a, 0x00000030},
753 { 0x0880e5bc, 0x00000005 }, 752 {0x0880e5bc, 0x00000005},
754 { 0x000000c4, 0x00000008 }, 753 {0x000000c4, 0x00000008},
755 { 0x0080e5bd, 0x00000005 }, 754 {0x0080e5bd, 0x00000005},
756 { 0x0000e5bb, 0x00000005 }, 755 {0x0000e5bb, 0x00000005},
757 { 0x0080e5bc, 0x00000005 }, 756 {0x0080e5bc, 0x00000005},
758 { 0x00210000, 0x00000004 }, 757 {0x00210000, 0x00000004},
759 { 0x02800000, 0x00000004 }, 758 {0x02800000, 0x00000004},
760 { 0x00c000c8, 0x00000018 }, 759 {0x00c000c8, 0x00000018},
761 { 0x4180e000, 0x00000040 }, 760 {0x4180e000, 0x00000040},
762 { 0x000000ca, 0x00000024 }, 761 {0x000000ca, 0x00000024},
763 { 0x01000000, 0x0000000c }, 762 {0x01000000, 0x0000000c},
764 { 0x0100e51d, 0x0000000c }, 763 {0x0100e51d, 0x0000000c},
765 { 0x000045bb, 0x00000004 }, 764 {0x000045bb, 0x00000004},
766 { 0x000080c4, 0x00000008 }, 765 {0x000080c4, 0x00000008},
767 { 0x0000f3ce, 0x00000004 }, 766 {0x0000f3ce, 0x00000004},
768 { 0x0140a000, 0x00000004 }, 767 {0x0140a000, 0x00000004},
769 { 0x00cc2000, 0x00000004 }, 768 {0x00cc2000, 0x00000004},
770 { 0x08c053cf, 0x00000040 }, 769 {0x08c053cf, 0x00000040},
771 { 0x00008000, 0000000000 }, 770 {0x00008000, 0000000000},
772 { 0x0000f3d2, 0x00000004 }, 771 {0x0000f3d2, 0x00000004},
773 { 0x0140a000, 0x00000004 }, 772 {0x0140a000, 0x00000004},
774 { 0x00cc2000, 0x00000004 }, 773 {0x00cc2000, 0x00000004},
775 { 0x08c053d3, 0x00000040 }, 774 {0x08c053d3, 0x00000040},
776 { 0x00008000, 0000000000 }, 775 {0x00008000, 0000000000},
777 { 0x0000f39d, 0x00000004 }, 776 {0x0000f39d, 0x00000004},
778 { 0x0140a000, 0x00000004 }, 777 {0x0140a000, 0x00000004},
779 { 0x00cc2000, 0x00000004 }, 778 {0x00cc2000, 0x00000004},
780 { 0x08c0539e, 0x00000040 }, 779 {0x08c0539e, 0x00000040},
781 { 0x00008000, 0000000000 }, 780 {0x00008000, 0000000000},
782 { 0x03c00830, 0x00000004 }, 781 {0x03c00830, 0x00000004},
783 { 0x4200e000, 0000000000 }, 782 {0x4200e000, 0000000000},
784 { 0x0000a000, 0x00000004 }, 783 {0x0000a000, 0x00000004},
785 { 0x200045e0, 0x00000004 }, 784 {0x200045e0, 0x00000004},
786 { 0x0000e5e1, 0000000000 }, 785 {0x0000e5e1, 0000000000},
787 { 0x00000001, 0000000000 }, 786 {0x00000001, 0000000000},
788 { 0x000700e1, 0x00000004 }, 787 {0x000700e1, 0x00000004},
789 { 0x0800e394, 0000000000 }, 788 {0x0800e394, 0000000000},
790 { 0000000000, 0000000000 }, 789 {0000000000, 0000000000},
791 { 0000000000, 0000000000 }, 790 {0000000000, 0000000000},
792 { 0000000000, 0000000000 }, 791 {0000000000, 0000000000},
793 { 0000000000, 0000000000 }, 792 {0000000000, 0000000000},
794 { 0000000000, 0000000000 }, 793 {0000000000, 0000000000},
795 { 0000000000, 0000000000 }, 794 {0000000000, 0000000000},
796 { 0000000000, 0000000000 }, 795 {0000000000, 0000000000},
797 { 0000000000, 0000000000 }, 796 {0000000000, 0000000000},
798 { 0000000000, 0000000000 }, 797 {0000000000, 0000000000},
799 { 0000000000, 0000000000 }, 798 {0000000000, 0000000000},
800 { 0000000000, 0000000000 }, 799 {0000000000, 0000000000},
801 { 0000000000, 0000000000 }, 800 {0000000000, 0000000000},
802 { 0000000000, 0000000000 }, 801 {0000000000, 0000000000},
803 { 0000000000, 0000000000 }, 802 {0000000000, 0000000000},
804 { 0000000000, 0000000000 }, 803 {0000000000, 0000000000},
805 { 0000000000, 0000000000 }, 804 {0000000000, 0000000000},
806 { 0000000000, 0000000000 }, 805 {0000000000, 0000000000},
807 { 0000000000, 0000000000 }, 806 {0000000000, 0000000000},
808 { 0000000000, 0000000000 }, 807 {0000000000, 0000000000},
809 { 0000000000, 0000000000 }, 808 {0000000000, 0000000000},
810 { 0000000000, 0000000000 }, 809 {0000000000, 0000000000},
811 { 0000000000, 0000000000 }, 810 {0000000000, 0000000000},
812 { 0000000000, 0000000000 }, 811 {0000000000, 0000000000},
813 { 0000000000, 0000000000 }, 812 {0000000000, 0000000000},
814 { 0000000000, 0000000000 }, 813 {0000000000, 0000000000},
815 { 0000000000, 0000000000 }, 814 {0000000000, 0000000000},
816 { 0000000000, 0000000000 }, 815 {0000000000, 0000000000},
817 { 0000000000, 0000000000 }, 816 {0000000000, 0000000000},
818}; 817};
819 818
820static int RADEON_READ_PLL(drm_device_t *dev, int addr) 819static int RADEON_READ_PLL(drm_device_t * dev, int addr)
821{ 820{
822 drm_radeon_private_t *dev_priv = dev->dev_private; 821 drm_radeon_private_t *dev_priv = dev->dev_private;
823 822
@@ -825,151 +824,148 @@ static int RADEON_READ_PLL(drm_device_t *dev, int addr)
825 return RADEON_READ(RADEON_CLOCK_CNTL_DATA); 824 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
826} 825}
827 826
828static int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) 827static int RADEON_READ_PCIE(drm_radeon_private_t * dev_priv, int addr)
829{ 828{
830 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); 829 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
831 return RADEON_READ(RADEON_PCIE_DATA); 830 return RADEON_READ(RADEON_PCIE_DATA);
832} 831}
833 832
834#if RADEON_FIFO_DEBUG 833#if RADEON_FIFO_DEBUG
835static void radeon_status( drm_radeon_private_t *dev_priv ) 834static void radeon_status(drm_radeon_private_t * dev_priv)
836{ 835{
837 printk( "%s:\n", __FUNCTION__ ); 836 printk("%s:\n", __FUNCTION__);
838 printk( "RBBM_STATUS = 0x%08x\n", 837 printk("RBBM_STATUS = 0x%08x\n",
839 (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) ); 838 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
840 printk( "CP_RB_RTPR = 0x%08x\n", 839 printk("CP_RB_RTPR = 0x%08x\n",
841 (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) ); 840 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
842 printk( "CP_RB_WTPR = 0x%08x\n", 841 printk("CP_RB_WTPR = 0x%08x\n",
843 (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) ); 842 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
844 printk( "AIC_CNTL = 0x%08x\n", 843 printk("AIC_CNTL = 0x%08x\n",
845 (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) ); 844 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
846 printk( "AIC_STAT = 0x%08x\n", 845 printk("AIC_STAT = 0x%08x\n",
847 (unsigned int)RADEON_READ( RADEON_AIC_STAT ) ); 846 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
848 printk( "AIC_PT_BASE = 0x%08x\n", 847 printk("AIC_PT_BASE = 0x%08x\n",
849 (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) ); 848 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
850 printk( "TLB_ADDR = 0x%08x\n", 849 printk("TLB_ADDR = 0x%08x\n",
851 (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) ); 850 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
852 printk( "TLB_DATA = 0x%08x\n", 851 printk("TLB_DATA = 0x%08x\n",
853 (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) ); 852 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
854} 853}
855#endif 854#endif
856 855
857
858/* ================================================================ 856/* ================================================================
859 * Engine, FIFO control 857 * Engine, FIFO control
860 */ 858 */
861 859
862static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv ) 860static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
863{ 861{
864 u32 tmp; 862 u32 tmp;
865 int i; 863 int i;
866 864
867 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 865 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
868 866
869 tmp = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT ); 867 tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
870 tmp |= RADEON_RB2D_DC_FLUSH_ALL; 868 tmp |= RADEON_RB2D_DC_FLUSH_ALL;
871 RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp ); 869 RADEON_WRITE(RADEON_RB2D_DSTCACHE_CTLSTAT, tmp);
872 870
873 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 871 for (i = 0; i < dev_priv->usec_timeout; i++) {
874 if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT ) 872 if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
875 & RADEON_RB2D_DC_BUSY) ) { 873 & RADEON_RB2D_DC_BUSY)) {
876 return 0; 874 return 0;
877 } 875 }
878 DRM_UDELAY( 1 ); 876 DRM_UDELAY(1);
879 } 877 }
880 878
881#if RADEON_FIFO_DEBUG 879#if RADEON_FIFO_DEBUG
882 DRM_ERROR( "failed!\n" ); 880 DRM_ERROR("failed!\n");
883 radeon_status( dev_priv ); 881 radeon_status(dev_priv);
884#endif 882#endif
885 return DRM_ERR(EBUSY); 883 return DRM_ERR(EBUSY);
886} 884}
887 885
888static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv, 886static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
889 int entries )
890{ 887{
891 int i; 888 int i;
892 889
893 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 890 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
894 891
895 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 892 for (i = 0; i < dev_priv->usec_timeout; i++) {
896 int slots = ( RADEON_READ( RADEON_RBBM_STATUS ) 893 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
897 & RADEON_RBBM_FIFOCNT_MASK ); 894 & RADEON_RBBM_FIFOCNT_MASK);
898 if ( slots >= entries ) return 0; 895 if (slots >= entries)
899 DRM_UDELAY( 1 ); 896 return 0;
897 DRM_UDELAY(1);
900 } 898 }
901 899
902#if RADEON_FIFO_DEBUG 900#if RADEON_FIFO_DEBUG
903 DRM_ERROR( "failed!\n" ); 901 DRM_ERROR("failed!\n");
904 radeon_status( dev_priv ); 902 radeon_status(dev_priv);
905#endif 903#endif
906 return DRM_ERR(EBUSY); 904 return DRM_ERR(EBUSY);
907} 905}
908 906
909static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv ) 907static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
910{ 908{
911 int i, ret; 909 int i, ret;
912 910
913 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 911 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
914 912
915 ret = radeon_do_wait_for_fifo( dev_priv, 64 ); 913 ret = radeon_do_wait_for_fifo(dev_priv, 64);
916 if ( ret ) return ret; 914 if (ret)
915 return ret;
917 916
918 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 917 for (i = 0; i < dev_priv->usec_timeout; i++) {
919 if ( !(RADEON_READ( RADEON_RBBM_STATUS ) 918 if (!(RADEON_READ(RADEON_RBBM_STATUS)
920 & RADEON_RBBM_ACTIVE) ) { 919 & RADEON_RBBM_ACTIVE)) {
921 radeon_do_pixcache_flush( dev_priv ); 920 radeon_do_pixcache_flush(dev_priv);
922 return 0; 921 return 0;
923 } 922 }
924 DRM_UDELAY( 1 ); 923 DRM_UDELAY(1);
925 } 924 }
926 925
927#if RADEON_FIFO_DEBUG 926#if RADEON_FIFO_DEBUG
928 DRM_ERROR( "failed!\n" ); 927 DRM_ERROR("failed!\n");
929 radeon_status( dev_priv ); 928 radeon_status(dev_priv);
930#endif 929#endif
931 return DRM_ERR(EBUSY); 930 return DRM_ERR(EBUSY);
932} 931}
933 932
934
935/* ================================================================ 933/* ================================================================
936 * CP control, initialization 934 * CP control, initialization
937 */ 935 */
938 936
939/* Load the microcode for the CP */ 937/* Load the microcode for the CP */
940static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv ) 938static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
941{ 939{
942 int i; 940 int i;
943 DRM_DEBUG( "\n" ); 941 DRM_DEBUG("\n");
944 942
945 radeon_do_wait_for_idle( dev_priv ); 943 radeon_do_wait_for_idle(dev_priv);
946 944
947 RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 ); 945 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
948 946
949 if (dev_priv->microcode_version==UCODE_R200) { 947 if (dev_priv->microcode_version == UCODE_R200) {
950 DRM_INFO("Loading R200 Microcode\n"); 948 DRM_INFO("Loading R200 Microcode\n");
951 for ( i = 0 ; i < 256 ; i++ ) 949 for (i = 0; i < 256; i++) {
952 { 950 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
953 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH, 951 R200_cp_microcode[i][1]);
954 R200_cp_microcode[i][1] ); 952 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
955 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL, 953 R200_cp_microcode[i][0]);
956 R200_cp_microcode[i][0] );
957 } 954 }
958 } else if (dev_priv->microcode_version==UCODE_R300) { 955 } else if (dev_priv->microcode_version == UCODE_R300) {
959 DRM_INFO("Loading R300 Microcode\n"); 956 DRM_INFO("Loading R300 Microcode\n");
960 for ( i = 0 ; i < 256 ; i++ ) 957 for (i = 0; i < 256; i++) {
961 { 958 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
962 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH, 959 R300_cp_microcode[i][1]);
963 R300_cp_microcode[i][1] ); 960 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
964 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL, 961 R300_cp_microcode[i][0]);
965 R300_cp_microcode[i][0] );
966 } 962 }
967 } else { 963 } else {
968 for ( i = 0 ; i < 256 ; i++ ) { 964 for (i = 0; i < 256; i++) {
969 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH, 965 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
970 radeon_cp_microcode[i][1] ); 966 radeon_cp_microcode[i][1]);
971 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL, 967 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
972 radeon_cp_microcode[i][0] ); 968 radeon_cp_microcode[i][0]);
973 } 969 }
974 } 970 }
975} 971}
@@ -978,25 +974,25 @@ static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
978 * prior to a wait for idle, as it informs the engine that the command 974 * prior to a wait for idle, as it informs the engine that the command
979 * stream is ending. 975 * stream is ending.
980 */ 976 */
981static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv ) 977static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
982{ 978{
983 DRM_DEBUG( "\n" ); 979 DRM_DEBUG("\n");
984#if 0 980#if 0
985 u32 tmp; 981 u32 tmp;
986 982
987 tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31); 983 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
988 RADEON_WRITE( RADEON_CP_RB_WPTR, tmp ); 984 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
989#endif 985#endif
990} 986}
991 987
992/* Wait for the CP to go idle. 988/* Wait for the CP to go idle.
993 */ 989 */
994int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ) 990int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
995{ 991{
996 RING_LOCALS; 992 RING_LOCALS;
997 DRM_DEBUG( "\n" ); 993 DRM_DEBUG("\n");
998 994
999 BEGIN_RING( 6 ); 995 BEGIN_RING(6);
1000 996
1001 RADEON_PURGE_CACHE(); 997 RADEON_PURGE_CACHE();
1002 RADEON_PURGE_ZCACHE(); 998 RADEON_PURGE_ZCACHE();
@@ -1005,23 +1001,23 @@ int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
1005 ADVANCE_RING(); 1001 ADVANCE_RING();
1006 COMMIT_RING(); 1002 COMMIT_RING();
1007 1003
1008 return radeon_do_wait_for_idle( dev_priv ); 1004 return radeon_do_wait_for_idle(dev_priv);
1009} 1005}
1010 1006
1011/* Start the Command Processor. 1007/* Start the Command Processor.
1012 */ 1008 */
1013static void radeon_do_cp_start( drm_radeon_private_t *dev_priv ) 1009static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
1014{ 1010{
1015 RING_LOCALS; 1011 RING_LOCALS;
1016 DRM_DEBUG( "\n" ); 1012 DRM_DEBUG("\n");
1017 1013
1018 radeon_do_wait_for_idle( dev_priv ); 1014 radeon_do_wait_for_idle(dev_priv);
1019 1015
1020 RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode ); 1016 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1021 1017
1022 dev_priv->cp_running = 1; 1018 dev_priv->cp_running = 1;
1023 1019
1024 BEGIN_RING( 6 ); 1020 BEGIN_RING(6);
1025 1021
1026 RADEON_PURGE_CACHE(); 1022 RADEON_PURGE_CACHE();
1027 RADEON_PURGE_ZCACHE(); 1023 RADEON_PURGE_ZCACHE();
@@ -1035,14 +1031,14 @@ static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
1035 * commands, so you must wait for the CP command stream to complete 1031 * commands, so you must wait for the CP command stream to complete
1036 * before calling this routine. 1032 * before calling this routine.
1037 */ 1033 */
1038static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv ) 1034static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
1039{ 1035{
1040 u32 cur_read_ptr; 1036 u32 cur_read_ptr;
1041 DRM_DEBUG( "\n" ); 1037 DRM_DEBUG("\n");
1042 1038
1043 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR ); 1039 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1044 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr ); 1040 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1045 SET_RING_HEAD( dev_priv, cur_read_ptr ); 1041 SET_RING_HEAD(dev_priv, cur_read_ptr);
1046 dev_priv->ring.tail = cur_read_ptr; 1042 dev_priv->ring.tail = cur_read_ptr;
1047} 1043}
1048 1044
@@ -1050,120 +1046,116 @@ static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
1050 * commands, so you must flush the command stream and wait for the CP 1046 * commands, so you must flush the command stream and wait for the CP
1051 * to go idle before calling this routine. 1047 * to go idle before calling this routine.
1052 */ 1048 */
1053static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv ) 1049static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1054{ 1050{
1055 DRM_DEBUG( "\n" ); 1051 DRM_DEBUG("\n");
1056 1052
1057 RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS ); 1053 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
1058 1054
1059 dev_priv->cp_running = 0; 1055 dev_priv->cp_running = 0;
1060} 1056}
1061 1057
1062/* Reset the engine. This will stop the CP if it is running. 1058/* Reset the engine. This will stop the CP if it is running.
1063 */ 1059 */
1064static int radeon_do_engine_reset( drm_device_t *dev ) 1060static int radeon_do_engine_reset(drm_device_t * dev)
1065{ 1061{
1066 drm_radeon_private_t *dev_priv = dev->dev_private; 1062 drm_radeon_private_t *dev_priv = dev->dev_private;
1067 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; 1063 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
1068 DRM_DEBUG( "\n" ); 1064 DRM_DEBUG("\n");
1069
1070 radeon_do_pixcache_flush( dev_priv );
1071
1072 clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
1073 mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
1074
1075 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
1076 RADEON_FORCEON_MCLKA |
1077 RADEON_FORCEON_MCLKB |
1078 RADEON_FORCEON_YCLKA |
1079 RADEON_FORCEON_YCLKB |
1080 RADEON_FORCEON_MC |
1081 RADEON_FORCEON_AIC ) );
1082
1083 rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
1084 1065
1085 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset | 1066 radeon_do_pixcache_flush(dev_priv);
1086 RADEON_SOFT_RESET_CP | 1067
1068 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
1069 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
1070
1071 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
1072 RADEON_FORCEON_MCLKA |
1073 RADEON_FORCEON_MCLKB |
1074 RADEON_FORCEON_YCLKA |
1075 RADEON_FORCEON_YCLKB |
1076 RADEON_FORCEON_MC |
1077 RADEON_FORCEON_AIC));
1078
1079 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
1080
1081 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
1082 RADEON_SOFT_RESET_CP |
1083 RADEON_SOFT_RESET_HI |
1084 RADEON_SOFT_RESET_SE |
1085 RADEON_SOFT_RESET_RE |
1086 RADEON_SOFT_RESET_PP |
1087 RADEON_SOFT_RESET_E2 |
1088 RADEON_SOFT_RESET_RB));
1089 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1090 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
1091 ~(RADEON_SOFT_RESET_CP |
1087 RADEON_SOFT_RESET_HI | 1092 RADEON_SOFT_RESET_HI |
1088 RADEON_SOFT_RESET_SE | 1093 RADEON_SOFT_RESET_SE |
1089 RADEON_SOFT_RESET_RE | 1094 RADEON_SOFT_RESET_RE |
1090 RADEON_SOFT_RESET_PP | 1095 RADEON_SOFT_RESET_PP |
1091 RADEON_SOFT_RESET_E2 | 1096 RADEON_SOFT_RESET_E2 |
1092 RADEON_SOFT_RESET_RB ) ); 1097 RADEON_SOFT_RESET_RB)));
1093 RADEON_READ( RADEON_RBBM_SOFT_RESET ); 1098 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1094 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset & 1099
1095 ~( RADEON_SOFT_RESET_CP | 1100 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
1096 RADEON_SOFT_RESET_HI | 1101 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
1097 RADEON_SOFT_RESET_SE | 1102 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
1098 RADEON_SOFT_RESET_RE |
1099 RADEON_SOFT_RESET_PP |
1100 RADEON_SOFT_RESET_E2 |
1101 RADEON_SOFT_RESET_RB ) ) );
1102 RADEON_READ( RADEON_RBBM_SOFT_RESET );
1103
1104
1105 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
1106 RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
1107 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, rbbm_soft_reset );
1108 1103
1109 /* Reset the CP ring */ 1104 /* Reset the CP ring */
1110 radeon_do_cp_reset( dev_priv ); 1105 radeon_do_cp_reset(dev_priv);
1111 1106
1112 /* The CP is no longer running after an engine reset */ 1107 /* The CP is no longer running after an engine reset */
1113 dev_priv->cp_running = 0; 1108 dev_priv->cp_running = 0;
1114 1109
1115 /* Reset any pending vertex, indirect buffers */ 1110 /* Reset any pending vertex, indirect buffers */
1116 radeon_freelist_reset( dev ); 1111 radeon_freelist_reset(dev);
1117 1112
1118 return 0; 1113 return 0;
1119} 1114}
1120 1115
1121static void radeon_cp_init_ring_buffer( drm_device_t *dev, 1116static void radeon_cp_init_ring_buffer(drm_device_t * dev,
1122 drm_radeon_private_t *dev_priv ) 1117 drm_radeon_private_t * dev_priv)
1123{ 1118{
1124 u32 ring_start, cur_read_ptr; 1119 u32 ring_start, cur_read_ptr;
1125 u32 tmp; 1120 u32 tmp;
1126 1121
1127 /* Initialize the memory controller */ 1122 /* Initialize the memory controller */
1128 RADEON_WRITE( RADEON_MC_FB_LOCATION, 1123 RADEON_WRITE(RADEON_MC_FB_LOCATION,
1129 ( ( dev_priv->gart_vm_start - 1 ) & 0xffff0000 ) 1124 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
1130 | ( dev_priv->fb_location >> 16 ) ); 1125 | (dev_priv->fb_location >> 16));
1131 1126
1132#if __OS_HAS_AGP 1127#if __OS_HAS_AGP
1133 if ( !dev_priv->is_pci ) { 1128 if (!dev_priv->is_pci) {
1134 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 1129 RADEON_WRITE(RADEON_MC_AGP_LOCATION,
1135 (((dev_priv->gart_vm_start - 1 + 1130 (((dev_priv->gart_vm_start - 1 +
1136 dev_priv->gart_size) & 0xffff0000) | 1131 dev_priv->gart_size) & 0xffff0000) |
1137 (dev_priv->gart_vm_start >> 16)) ); 1132 (dev_priv->gart_vm_start >> 16)));
1138 1133
1139 ring_start = (dev_priv->cp_ring->offset 1134 ring_start = (dev_priv->cp_ring->offset
1140 - dev->agp->base 1135 - dev->agp->base + dev_priv->gart_vm_start);
1141 + dev_priv->gart_vm_start); 1136 } else
1142 } else
1143#endif 1137#endif
1144 ring_start = (dev_priv->cp_ring->offset 1138 ring_start = (dev_priv->cp_ring->offset
1145 - dev->sg->handle 1139 - dev->sg->handle + dev_priv->gart_vm_start);
1146 + dev_priv->gart_vm_start);
1147 1140
1148 RADEON_WRITE( RADEON_CP_RB_BASE, ring_start ); 1141 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
1149 1142
1150 /* Set the write pointer delay */ 1143 /* Set the write pointer delay */
1151 RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 ); 1144 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
1152 1145
1153 /* Initialize the ring buffer's read and write pointers */ 1146 /* Initialize the ring buffer's read and write pointers */
1154 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR ); 1147 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1155 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr ); 1148 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1156 SET_RING_HEAD( dev_priv, cur_read_ptr ); 1149 SET_RING_HEAD(dev_priv, cur_read_ptr);
1157 dev_priv->ring.tail = cur_read_ptr; 1150 dev_priv->ring.tail = cur_read_ptr;
1158 1151
1159#if __OS_HAS_AGP 1152#if __OS_HAS_AGP
1160 if ( !dev_priv->is_pci ) { 1153 if (!dev_priv->is_pci) {
1161 /* set RADEON_AGP_BASE here instead of relying on X from user space */ 1154 /* set RADEON_AGP_BASE here instead of relying on X from user space */
1162 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base); 1155 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
1163 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, 1156 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
1164 dev_priv->ring_rptr->offset 1157 dev_priv->ring_rptr->offset
1165 - dev->agp->base 1158 - dev->agp->base + dev_priv->gart_vm_start);
1166 + dev_priv->gart_vm_start);
1167 } else 1159 } else
1168#endif 1160#endif
1169 { 1161 {
@@ -1173,11 +1165,10 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
1173 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle; 1165 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
1174 page_ofs = tmp_ofs >> PAGE_SHIFT; 1166 page_ofs = tmp_ofs >> PAGE_SHIFT;
1175 1167
1176 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, 1168 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
1177 entry->busaddr[page_ofs]); 1169 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
1178 DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n", 1170 (unsigned long)entry->busaddr[page_ofs],
1179 (unsigned long) entry->busaddr[page_ofs], 1171 entry->handle + tmp_ofs);
1180 entry->handle + tmp_ofs );
1181 } 1172 }
1182 1173
1183 /* Initialize the scratch register pointer. This will cause 1174 /* Initialize the scratch register pointer. This will cause
@@ -1187,64 +1178,64 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
1187 * We simply put this behind the ring read pointer, this works 1178 * We simply put this behind the ring read pointer, this works
1188 * with PCI GART as well as (whatever kind of) AGP GART 1179 * with PCI GART as well as (whatever kind of) AGP GART
1189 */ 1180 */
1190 RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR ) 1181 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
1191 + RADEON_SCRATCH_REG_OFFSET ); 1182 + RADEON_SCRATCH_REG_OFFSET);
1192 1183
1193 dev_priv->scratch = ((__volatile__ u32 *) 1184 dev_priv->scratch = ((__volatile__ u32 *)
1194 dev_priv->ring_rptr->handle + 1185 dev_priv->ring_rptr->handle +
1195 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32))); 1186 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1196 1187
1197 RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 ); 1188 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
1198 1189
1199 /* Writeback doesn't seem to work everywhere, test it first */ 1190 /* Writeback doesn't seem to work everywhere, test it first */
1200 DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 ); 1191 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
1201 RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef ); 1192 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
1202 1193
1203 for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) { 1194 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
1204 if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef ) 1195 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
1196 0xdeadbeef)
1205 break; 1197 break;
1206 DRM_UDELAY( 1 ); 1198 DRM_UDELAY(1);
1207 } 1199 }
1208 1200
1209 if ( tmp < dev_priv->usec_timeout ) { 1201 if (tmp < dev_priv->usec_timeout) {
1210 dev_priv->writeback_works = 1; 1202 dev_priv->writeback_works = 1;
1211 DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp ); 1203 DRM_DEBUG("writeback test succeeded, tmp=%d\n", tmp);
1212 } else { 1204 } else {
1213 dev_priv->writeback_works = 0; 1205 dev_priv->writeback_works = 0;
1214 DRM_DEBUG( "writeback test failed\n" ); 1206 DRM_DEBUG("writeback test failed\n");
1215 } 1207 }
1216 1208
1217 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; 1209 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1218 RADEON_WRITE( RADEON_LAST_FRAME_REG, 1210 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1219 dev_priv->sarea_priv->last_frame );
1220 1211
1221 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0; 1212 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1222 RADEON_WRITE( RADEON_LAST_DISPATCH_REG, 1213 RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
1223 dev_priv->sarea_priv->last_dispatch ); 1214 dev_priv->sarea_priv->last_dispatch);
1224 1215
1225 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0; 1216 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1226 RADEON_WRITE( RADEON_LAST_CLEAR_REG, 1217 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1227 dev_priv->sarea_priv->last_clear );
1228 1218
1229 /* Set ring buffer size */ 1219 /* Set ring buffer size */
1230#ifdef __BIG_ENDIAN 1220#ifdef __BIG_ENDIAN
1231 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT ); 1221 RADEON_WRITE(RADEON_CP_RB_CNTL,
1222 dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT);
1232#else 1223#else
1233 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw ); 1224 RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw);
1234#endif 1225#endif
1235 1226
1236 radeon_do_wait_for_idle( dev_priv ); 1227 radeon_do_wait_for_idle(dev_priv);
1237 1228
1238 /* Turn on bus mastering */ 1229 /* Turn on bus mastering */
1239 tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS; 1230 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
1240 RADEON_WRITE( RADEON_BUS_CNTL, tmp ); 1231 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
1241 1232
1242 /* Sync everything up */ 1233 /* Sync everything up */
1243 RADEON_WRITE( RADEON_ISYNC_CNTL, 1234 RADEON_WRITE(RADEON_ISYNC_CNTL,
1244 (RADEON_ISYNC_ANY2D_IDLE3D | 1235 (RADEON_ISYNC_ANY2D_IDLE3D |
1245 RADEON_ISYNC_ANY3D_IDLE2D | 1236 RADEON_ISYNC_ANY3D_IDLE2D |
1246 RADEON_ISYNC_WAIT_IDLEGUI | 1237 RADEON_ISYNC_WAIT_IDLEGUI |
1247 RADEON_ISYNC_CPSCRATCH_IDLEGUI) ); 1238 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
1248} 1239}
1249 1240
1250/* Enable or disable PCI-E GART on the chip */ 1241/* Enable or disable PCI-E GART on the chip */
@@ -1254,35 +1245,42 @@ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1254 if (on) { 1245 if (on) {
1255 1246
1256 DRM_DEBUG("programming pcie %08X %08lX %08X\n", 1247 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1257 dev_priv->gart_vm_start, (long)dev_priv->gart_info.bus_addr, 1248 dev_priv->gart_vm_start,
1249 (long)dev_priv->gart_info.bus_addr,
1258 dev_priv->gart_size); 1250 dev_priv->gart_size);
1259 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, dev_priv->gart_vm_start); 1251 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1260 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, dev_priv->gart_info.bus_addr); 1252 dev_priv->gart_vm_start);
1261 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, dev_priv->gart_vm_start); 1253 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1262 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, dev_priv->gart_vm_start 1254 dev_priv->gart_info.bus_addr);
1263 + dev_priv->gart_size - 1); 1255 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1264 1256 dev_priv->gart_vm_start);
1257 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1258 dev_priv->gart_vm_start +
1259 dev_priv->gart_size - 1);
1260
1265 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */ 1261 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */
1266 1262
1267 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, RADEON_PCIE_TX_GART_EN); 1263 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1264 RADEON_PCIE_TX_GART_EN);
1268 } else { 1265 } else {
1269 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); 1266 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1267 tmp & ~RADEON_PCIE_TX_GART_EN);
1270 } 1268 }
1271} 1269}
1272 1270
1273/* Enable or disable PCI GART on the chip */ 1271/* Enable or disable PCI GART on the chip */
1274static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on ) 1272static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1275{ 1273{
1276 u32 tmp = RADEON_READ( RADEON_AIC_CNTL ); 1274 u32 tmp = RADEON_READ(RADEON_AIC_CNTL);
1277 1275
1278 if (dev_priv->flags & CHIP_IS_PCIE) 1276 if (dev_priv->flags & CHIP_IS_PCIE) {
1279 {
1280 radeon_set_pciegart(dev_priv, on); 1277 radeon_set_pciegart(dev_priv, on);
1281 return; 1278 return;
1282 } 1279 }
1283 1280
1284 if ( on ) { 1281 if (on) {
1285 RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN ); 1282 RADEON_WRITE(RADEON_AIC_CNTL,
1283 tmp | RADEON_PCIGART_TRANSLATE_EN);
1286 1284
1287 /* set PCI GART page-table base address 1285 /* set PCI GART page-table base address
1288 */ 1286 */
@@ -1290,53 +1288,54 @@ static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on )
1290 1288
1291 /* set address range for PCI address translate 1289 /* set address range for PCI address translate
1292 */ 1290 */
1293 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start ); 1291 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1294 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start 1292 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1295 + dev_priv->gart_size - 1); 1293 + dev_priv->gart_size - 1);
1296 1294
1297 /* Turn off AGP aperture -- is this required for PCI GART? 1295 /* Turn off AGP aperture -- is this required for PCI GART?
1298 */ 1296 */
1299 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */ 1297 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */
1300 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */ 1298 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1301 } else { 1299 } else {
1302 RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN ); 1300 RADEON_WRITE(RADEON_AIC_CNTL,
1301 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1303 } 1302 }
1304} 1303}
1305 1304
1306static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) 1305static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1307{ 1306{
1308 drm_radeon_private_t *dev_priv = dev->dev_private;; 1307 drm_radeon_private_t *dev_priv = dev->dev_private;;
1309 DRM_DEBUG( "\n" ); 1308 DRM_DEBUG("\n");
1310 1309
1311 dev_priv->is_pci = init->is_pci; 1310 dev_priv->is_pci = init->is_pci;
1312 1311
1313 if ( dev_priv->is_pci && !dev->sg ) { 1312 if (dev_priv->is_pci && !dev->sg) {
1314 DRM_ERROR( "PCI GART memory not allocated!\n" ); 1313 DRM_ERROR("PCI GART memory not allocated!\n");
1315 dev->dev_private = (void *)dev_priv; 1314 dev->dev_private = (void *)dev_priv;
1316 radeon_do_cleanup_cp(dev); 1315 radeon_do_cleanup_cp(dev);
1317 return DRM_ERR(EINVAL); 1316 return DRM_ERR(EINVAL);
1318 } 1317 }
1319 1318
1320 dev_priv->usec_timeout = init->usec_timeout; 1319 dev_priv->usec_timeout = init->usec_timeout;
1321 if ( dev_priv->usec_timeout < 1 || 1320 if (dev_priv->usec_timeout < 1 ||
1322 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) { 1321 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1323 DRM_DEBUG( "TIMEOUT problem!\n" ); 1322 DRM_DEBUG("TIMEOUT problem!\n");
1324 dev->dev_private = (void *)dev_priv; 1323 dev->dev_private = (void *)dev_priv;
1325 radeon_do_cleanup_cp(dev); 1324 radeon_do_cleanup_cp(dev);
1326 return DRM_ERR(EINVAL); 1325 return DRM_ERR(EINVAL);
1327 } 1326 }
1328 1327
1329 switch(init->func) { 1328 switch (init->func) {
1330 case RADEON_INIT_R200_CP: 1329 case RADEON_INIT_R200_CP:
1331 dev_priv->microcode_version=UCODE_R200; 1330 dev_priv->microcode_version = UCODE_R200;
1332 break; 1331 break;
1333 case RADEON_INIT_R300_CP: 1332 case RADEON_INIT_R300_CP:
1334 dev_priv->microcode_version=UCODE_R300; 1333 dev_priv->microcode_version = UCODE_R300;
1335 break; 1334 break;
1336 default: 1335 default:
1337 dev_priv->microcode_version=UCODE_R100; 1336 dev_priv->microcode_version = UCODE_R100;
1338 } 1337 }
1339 1338
1340 dev_priv->do_boxes = 0; 1339 dev_priv->do_boxes = 0;
1341 dev_priv->cp_mode = init->cp_mode; 1340 dev_priv->cp_mode = init->cp_mode;
1342 1341
@@ -1344,15 +1343,15 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1344 * but the ring can be in either AGP or PCI space for the ring 1343 * but the ring can be in either AGP or PCI space for the ring
1345 * read pointer. 1344 * read pointer.
1346 */ 1345 */
1347 if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) && 1346 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1348 ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) { 1347 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1349 DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode ); 1348 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1350 dev->dev_private = (void *)dev_priv; 1349 dev->dev_private = (void *)dev_priv;
1351 radeon_do_cleanup_cp(dev); 1350 radeon_do_cleanup_cp(dev);
1352 return DRM_ERR(EINVAL); 1351 return DRM_ERR(EINVAL);
1353 } 1352 }
1354 1353
1355 switch ( init->fb_bpp ) { 1354 switch (init->fb_bpp) {
1356 case 16: 1355 case 16:
1357 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; 1356 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1358 break; 1357 break;
@@ -1361,12 +1360,12 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1361 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 1360 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1362 break; 1361 break;
1363 } 1362 }
1364 dev_priv->front_offset = init->front_offset; 1363 dev_priv->front_offset = init->front_offset;
1365 dev_priv->front_pitch = init->front_pitch; 1364 dev_priv->front_pitch = init->front_pitch;
1366 dev_priv->back_offset = init->back_offset; 1365 dev_priv->back_offset = init->back_offset;
1367 dev_priv->back_pitch = init->back_pitch; 1366 dev_priv->back_pitch = init->back_pitch;
1368 1367
1369 switch ( init->depth_bpp ) { 1368 switch (init->depth_bpp) {
1370 case 16: 1369 case 16:
1371 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; 1370 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1372 break; 1371 break;
@@ -1375,8 +1374,8 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1375 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; 1374 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1376 break; 1375 break;
1377 } 1376 }
1378 dev_priv->depth_offset = init->depth_offset; 1377 dev_priv->depth_offset = init->depth_offset;
1379 dev_priv->depth_pitch = init->depth_pitch; 1378 dev_priv->depth_pitch = init->depth_pitch;
1380 1379
1381 /* Hardware state for depth clears. Remove this if/when we no 1380 /* Hardware state for depth clears. Remove this if/when we no
1382 * longer clear the depth buffer with a 3D rectangle. Hard-code 1381 * longer clear the depth buffer with a 3D rectangle. Hard-code
@@ -1385,16 +1384,16 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1385 */ 1384 */
1386 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | 1385 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1387 (dev_priv->color_fmt << 10) | 1386 (dev_priv->color_fmt << 10) |
1388 (dev_priv->microcode_version == UCODE_R100 ? RADEON_ZBLOCK16 : 0)); 1387 (dev_priv->microcode_version ==
1388 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1389 1389
1390 dev_priv->depth_clear.rb3d_zstencilcntl = 1390 dev_priv->depth_clear.rb3d_zstencilcntl =
1391 (dev_priv->depth_fmt | 1391 (dev_priv->depth_fmt |
1392 RADEON_Z_TEST_ALWAYS | 1392 RADEON_Z_TEST_ALWAYS |
1393 RADEON_STENCIL_TEST_ALWAYS | 1393 RADEON_STENCIL_TEST_ALWAYS |
1394 RADEON_STENCIL_S_FAIL_REPLACE | 1394 RADEON_STENCIL_S_FAIL_REPLACE |
1395 RADEON_STENCIL_ZPASS_REPLACE | 1395 RADEON_STENCIL_ZPASS_REPLACE |
1396 RADEON_STENCIL_ZFAIL_REPLACE | 1396 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1397 RADEON_Z_WRITE_ENABLE);
1398 1397
1399 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | 1398 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1400 RADEON_BFACE_SOLID | 1399 RADEON_BFACE_SOLID |
@@ -1416,8 +1415,8 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1416 dev_priv->ring_rptr_offset = init->ring_rptr_offset; 1415 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1417 dev_priv->buffers_offset = init->buffers_offset; 1416 dev_priv->buffers_offset = init->buffers_offset;
1418 dev_priv->gart_textures_offset = init->gart_textures_offset; 1417 dev_priv->gart_textures_offset = init->gart_textures_offset;
1419 1418
1420 if(!dev_priv->sarea) { 1419 if (!dev_priv->sarea) {
1421 DRM_ERROR("could not find sarea!\n"); 1420 DRM_ERROR("could not find sarea!\n");
1422 dev->dev_private = (void *)dev_priv; 1421 dev->dev_private = (void *)dev_priv;
1423 radeon_do_cleanup_cp(dev); 1422 radeon_do_cleanup_cp(dev);
@@ -1425,21 +1424,21 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1425 } 1424 }
1426 1425
1427 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); 1426 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
1428 if(!dev_priv->mmio) { 1427 if (!dev_priv->mmio) {
1429 DRM_ERROR("could not find mmio region!\n"); 1428 DRM_ERROR("could not find mmio region!\n");
1430 dev->dev_private = (void *)dev_priv; 1429 dev->dev_private = (void *)dev_priv;
1431 radeon_do_cleanup_cp(dev); 1430 radeon_do_cleanup_cp(dev);
1432 return DRM_ERR(EINVAL); 1431 return DRM_ERR(EINVAL);
1433 } 1432 }
1434 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); 1433 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1435 if(!dev_priv->cp_ring) { 1434 if (!dev_priv->cp_ring) {
1436 DRM_ERROR("could not find cp ring region!\n"); 1435 DRM_ERROR("could not find cp ring region!\n");
1437 dev->dev_private = (void *)dev_priv; 1436 dev->dev_private = (void *)dev_priv;
1438 radeon_do_cleanup_cp(dev); 1437 radeon_do_cleanup_cp(dev);
1439 return DRM_ERR(EINVAL); 1438 return DRM_ERR(EINVAL);
1440 } 1439 }
1441 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 1440 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1442 if(!dev_priv->ring_rptr) { 1441 if (!dev_priv->ring_rptr) {
1443 DRM_ERROR("could not find ring read pointer!\n"); 1442 DRM_ERROR("could not find ring read pointer!\n");
1444 dev->dev_private = (void *)dev_priv; 1443 dev->dev_private = (void *)dev_priv;
1445 radeon_do_cleanup_cp(dev); 1444 radeon_do_cleanup_cp(dev);
@@ -1447,16 +1446,17 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1447 } 1446 }
1448 dev->agp_buffer_token = init->buffers_offset; 1447 dev->agp_buffer_token = init->buffers_offset;
1449 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 1448 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1450 if(!dev->agp_buffer_map) { 1449 if (!dev->agp_buffer_map) {
1451 DRM_ERROR("could not find dma buffer region!\n"); 1450 DRM_ERROR("could not find dma buffer region!\n");
1452 dev->dev_private = (void *)dev_priv; 1451 dev->dev_private = (void *)dev_priv;
1453 radeon_do_cleanup_cp(dev); 1452 radeon_do_cleanup_cp(dev);
1454 return DRM_ERR(EINVAL); 1453 return DRM_ERR(EINVAL);
1455 } 1454 }
1456 1455
1457 if ( init->gart_textures_offset ) { 1456 if (init->gart_textures_offset) {
1458 dev_priv->gart_textures = drm_core_findmap(dev, init->gart_textures_offset); 1457 dev_priv->gart_textures =
1459 if ( !dev_priv->gart_textures ) { 1458 drm_core_findmap(dev, init->gart_textures_offset);
1459 if (!dev_priv->gart_textures) {
1460 DRM_ERROR("could not find GART texture region!\n"); 1460 DRM_ERROR("could not find GART texture region!\n");
1461 dev->dev_private = (void *)dev_priv; 1461 dev->dev_private = (void *)dev_priv;
1462 radeon_do_cleanup_cp(dev); 1462 radeon_do_cleanup_cp(dev);
@@ -1465,17 +1465,17 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1465 } 1465 }
1466 1466
1467 dev_priv->sarea_priv = 1467 dev_priv->sarea_priv =
1468 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle + 1468 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1469 init->sarea_priv_offset); 1469 init->sarea_priv_offset);
1470 1470
1471#if __OS_HAS_AGP 1471#if __OS_HAS_AGP
1472 if ( !dev_priv->is_pci ) { 1472 if (!dev_priv->is_pci) {
1473 drm_core_ioremap( dev_priv->cp_ring, dev ); 1473 drm_core_ioremap(dev_priv->cp_ring, dev);
1474 drm_core_ioremap( dev_priv->ring_rptr, dev ); 1474 drm_core_ioremap(dev_priv->ring_rptr, dev);
1475 drm_core_ioremap( dev->agp_buffer_map, dev ); 1475 drm_core_ioremap(dev->agp_buffer_map, dev);
1476 if(!dev_priv->cp_ring->handle || 1476 if (!dev_priv->cp_ring->handle ||
1477 !dev_priv->ring_rptr->handle || 1477 !dev_priv->ring_rptr->handle ||
1478 !dev->agp_buffer_map->handle) { 1478 !dev->agp_buffer_map->handle) {
1479 DRM_ERROR("could not find ioremap agp regions!\n"); 1479 DRM_ERROR("could not find ioremap agp regions!\n");
1480 dev->dev_private = (void *)dev_priv; 1480 dev->dev_private = (void *)dev_priv;
1481 radeon_do_cleanup_cp(dev); 1481 radeon_do_cleanup_cp(dev);
@@ -1484,140 +1484,146 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1484 } else 1484 } else
1485#endif 1485#endif
1486 { 1486 {
1487 dev_priv->cp_ring->handle = 1487 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1488 (void *)dev_priv->cp_ring->offset;
1489 dev_priv->ring_rptr->handle = 1488 dev_priv->ring_rptr->handle =
1490 (void *)dev_priv->ring_rptr->offset; 1489 (void *)dev_priv->ring_rptr->offset;
1491 dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset; 1490 dev->agp_buffer_map->handle =
1492 1491 (void *)dev->agp_buffer_map->offset;
1493 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n", 1492
1494 dev_priv->cp_ring->handle ); 1493 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1495 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n", 1494 dev_priv->cp_ring->handle);
1496 dev_priv->ring_rptr->handle ); 1495 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1497 DRM_DEBUG( "dev->agp_buffer_map->handle %p\n", 1496 dev_priv->ring_rptr->handle);
1498 dev->agp_buffer_map->handle ); 1497 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1498 dev->agp_buffer_map->handle);
1499 } 1499 }
1500 1500
1501 dev_priv->fb_location = ( RADEON_READ( RADEON_MC_FB_LOCATION ) 1501 dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
1502 & 0xffff ) << 16; 1502 & 0xffff) << 16;
1503 1503
1504 dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) | 1504 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1505 ( ( dev_priv->front_offset 1505 ((dev_priv->front_offset
1506 + dev_priv->fb_location ) >> 10 ) ); 1506 + dev_priv->fb_location) >> 10));
1507 1507
1508 dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) | 1508 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1509 ( ( dev_priv->back_offset 1509 ((dev_priv->back_offset
1510 + dev_priv->fb_location ) >> 10 ) ); 1510 + dev_priv->fb_location) >> 10));
1511
1512 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
1513 ( ( dev_priv->depth_offset
1514 + dev_priv->fb_location ) >> 10 ) );
1515 1511
1512 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1513 ((dev_priv->depth_offset
1514 + dev_priv->fb_location) >> 10));
1516 1515
1517 dev_priv->gart_size = init->gart_size; 1516 dev_priv->gart_size = init->gart_size;
1518 dev_priv->gart_vm_start = dev_priv->fb_location 1517 dev_priv->gart_vm_start = dev_priv->fb_location
1519 + RADEON_READ( RADEON_CONFIG_APER_SIZE ); 1518 + RADEON_READ(RADEON_CONFIG_APER_SIZE);
1520 1519
1521#if __OS_HAS_AGP 1520#if __OS_HAS_AGP
1522 if ( !dev_priv->is_pci ) 1521 if (!dev_priv->is_pci)
1523 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 1522 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1524 - dev->agp->base 1523 - dev->agp->base
1525 + dev_priv->gart_vm_start); 1524 + dev_priv->gart_vm_start);
1526 else 1525 else
1527#endif 1526#endif
1528 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 1527 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1529 - dev->sg->handle 1528 - dev->sg->handle
1530 + dev_priv->gart_vm_start); 1529 + dev_priv->gart_vm_start);
1531 1530
1532 DRM_DEBUG( "dev_priv->gart_size %d\n", 1531 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1533 dev_priv->gart_size ); 1532 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1534 DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n", 1533 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1535 dev_priv->gart_vm_start ); 1534 dev_priv->gart_buffers_offset);
1536 DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n", 1535
1537 dev_priv->gart_buffers_offset ); 1536 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1538 1537 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1539 dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
1540 dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
1541 + init->ring_size / sizeof(u32)); 1538 + init->ring_size / sizeof(u32));
1542 dev_priv->ring.size = init->ring_size; 1539 dev_priv->ring.size = init->ring_size;
1543 dev_priv->ring.size_l2qw = drm_order( init->ring_size / 8 ); 1540 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1544 1541
1545 dev_priv->ring.tail_mask = 1542 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1546 (dev_priv->ring.size / sizeof(u32)) - 1;
1547 1543
1548 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 1544 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1549 1545
1550#if __OS_HAS_AGP 1546#if __OS_HAS_AGP
1551 if ( !dev_priv->is_pci ) { 1547 if (!dev_priv->is_pci) {
1552 /* Turn off PCI GART */ 1548 /* Turn off PCI GART */
1553 radeon_set_pcigart( dev_priv, 0 ); 1549 radeon_set_pcigart(dev_priv, 0);
1554 } else 1550 } else
1555#endif 1551#endif
1556 { 1552 {
1557 /* if we have an offset set from userspace */ 1553 /* if we have an offset set from userspace */
1558 if (dev_priv->pcigart_offset) { 1554 if (dev_priv->pcigart_offset) {
1559 dev_priv->gart_info.bus_addr = dev_priv->pcigart_offset + dev_priv->fb_location; 1555 dev_priv->gart_info.bus_addr =
1560 dev_priv->gart_info.addr = (unsigned long)drm_ioremap(dev_priv->gart_info.bus_addr, RADEON_PCIGART_TABLE_SIZE, dev); 1556 dev_priv->pcigart_offset + dev_priv->fb_location;
1561 1557 dev_priv->gart_info.addr =
1562 dev_priv->gart_info.is_pcie = !!(dev_priv->flags & CHIP_IS_PCIE); 1558 (unsigned long)drm_ioremap(dev_priv->gart_info.
1563 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_FB; 1559 bus_addr,
1564 1560 RADEON_PCIGART_TABLE_SIZE,
1565 DRM_DEBUG("Setting phys_pci_gart to %08lX %08lX\n", dev_priv->gart_info.addr, dev_priv->pcigart_offset); 1561 dev);
1566 } 1562
1567 else { 1563 dev_priv->gart_info.is_pcie =
1568 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN; 1564 !!(dev_priv->flags & CHIP_IS_PCIE);
1569 dev_priv->gart_info.addr = dev_priv->gart_info.bus_addr= 0; 1565 dev_priv->gart_info.gart_table_location =
1570 if (dev_priv->flags & CHIP_IS_PCIE) 1566 DRM_ATI_GART_FB;
1571 { 1567
1572 DRM_ERROR("Cannot use PCI Express without GART in FB memory\n"); 1568 DRM_DEBUG("Setting phys_pci_gart to %08lX %08lX\n",
1569 dev_priv->gart_info.addr,
1570 dev_priv->pcigart_offset);
1571 } else {
1572 dev_priv->gart_info.gart_table_location =
1573 DRM_ATI_GART_MAIN;
1574 dev_priv->gart_info.addr =
1575 dev_priv->gart_info.bus_addr = 0;
1576 if (dev_priv->flags & CHIP_IS_PCIE) {
1577 DRM_ERROR
1578 ("Cannot use PCI Express without GART in FB memory\n");
1573 radeon_do_cleanup_cp(dev); 1579 radeon_do_cleanup_cp(dev);
1574 return DRM_ERR(EINVAL); 1580 return DRM_ERR(EINVAL);
1575 } 1581 }
1576 } 1582 }
1577 1583
1578 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) { 1584 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1579 DRM_ERROR( "failed to init PCI GART!\n" ); 1585 DRM_ERROR("failed to init PCI GART!\n");
1580 dev->dev_private = (void *)dev_priv; 1586 dev->dev_private = (void *)dev_priv;
1581 radeon_do_cleanup_cp(dev); 1587 radeon_do_cleanup_cp(dev);
1582 return DRM_ERR(ENOMEM); 1588 return DRM_ERR(ENOMEM);
1583 } 1589 }
1584 1590
1585 /* Turn on PCI GART */ 1591 /* Turn on PCI GART */
1586 radeon_set_pcigart( dev_priv, 1 ); 1592 radeon_set_pcigart(dev_priv, 1);
1587 } 1593 }
1588 1594
1589 radeon_cp_load_microcode( dev_priv ); 1595 radeon_cp_load_microcode(dev_priv);
1590 radeon_cp_init_ring_buffer( dev, dev_priv ); 1596 radeon_cp_init_ring_buffer(dev, dev_priv);
1591 1597
1592 dev_priv->last_buf = 0; 1598 dev_priv->last_buf = 0;
1593 1599
1594 dev->dev_private = (void *)dev_priv; 1600 dev->dev_private = (void *)dev_priv;
1595 1601
1596 radeon_do_engine_reset( dev ); 1602 radeon_do_engine_reset(dev);
1597 1603
1598 return 0; 1604 return 0;
1599} 1605}
1600 1606
1601static int radeon_do_cleanup_cp( drm_device_t *dev ) 1607static int radeon_do_cleanup_cp(drm_device_t * dev)
1602{ 1608{
1603 drm_radeon_private_t *dev_priv = dev->dev_private; 1609 drm_radeon_private_t *dev_priv = dev->dev_private;
1604 DRM_DEBUG( "\n" ); 1610 DRM_DEBUG("\n");
1605 1611
1606 /* Make sure interrupts are disabled here because the uninstall ioctl 1612 /* Make sure interrupts are disabled here because the uninstall ioctl
1607 * may not have been called from userspace and after dev_private 1613 * may not have been called from userspace and after dev_private
1608 * is freed, it's too late. 1614 * is freed, it's too late.
1609 */ 1615 */
1610 if ( dev->irq_enabled ) drm_irq_uninstall(dev); 1616 if (dev->irq_enabled)
1617 drm_irq_uninstall(dev);
1611 1618
1612#if __OS_HAS_AGP 1619#if __OS_HAS_AGP
1613 if ( !dev_priv->is_pci ) { 1620 if (!dev_priv->is_pci) {
1614 if ( dev_priv->cp_ring != NULL ) 1621 if (dev_priv->cp_ring != NULL)
1615 drm_core_ioremapfree( dev_priv->cp_ring, dev ); 1622 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1616 if ( dev_priv->ring_rptr != NULL ) 1623 if (dev_priv->ring_rptr != NULL)
1617 drm_core_ioremapfree( dev_priv->ring_rptr, dev ); 1624 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1618 if ( dev->agp_buffer_map != NULL ) 1625 if (dev->agp_buffer_map != NULL) {
1619 { 1626 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1620 drm_core_ioremapfree( dev->agp_buffer_map, dev );
1621 dev->agp_buffer_map = NULL; 1627 dev->agp_buffer_map = NULL;
1622 } 1628 }
1623 } else 1629 } else
@@ -1626,103 +1632,103 @@ static int radeon_do_cleanup_cp( drm_device_t *dev )
1626 if (dev_priv->gart_info.bus_addr) 1632 if (dev_priv->gart_info.bus_addr)
1627 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) 1633 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1628 DRM_ERROR("failed to cleanup PCI GART!\n"); 1634 DRM_ERROR("failed to cleanup PCI GART!\n");
1629 1635
1630 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) 1636 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
1631 { 1637 drm_ioremapfree((void *)dev_priv->gart_info.addr,
1632 drm_ioremapfree((void *)dev_priv->gart_info.addr, RADEON_PCIGART_TABLE_SIZE, dev); 1638 RADEON_PCIGART_TABLE_SIZE, dev);
1633 dev_priv->gart_info.addr = 0; 1639 dev_priv->gart_info.addr = 0;
1634 } 1640 }
1635 } 1641 }
1636 1642
1637 /* only clear to the start of flags */ 1643 /* only clear to the start of flags */
1638 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); 1644 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1639 1645
1640 return 0; 1646 return 0;
1641} 1647}
1642 1648
1643/* This code will reinit the Radeon CP hardware after a resume from disc. 1649/* This code will reinit the Radeon CP hardware after a resume from disc.
1644 * AFAIK, it would be very difficult to pickle the state at suspend time, so 1650 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1645 * here we make sure that all Radeon hardware initialisation is re-done without 1651 * here we make sure that all Radeon hardware initialisation is re-done without
1646 * affecting running applications. 1652 * affecting running applications.
1647 * 1653 *
1648 * Charl P. Botha <http://cpbotha.net> 1654 * Charl P. Botha <http://cpbotha.net>
1649 */ 1655 */
1650static int radeon_do_resume_cp( drm_device_t *dev ) 1656static int radeon_do_resume_cp(drm_device_t * dev)
1651{ 1657{
1652 drm_radeon_private_t *dev_priv = dev->dev_private; 1658 drm_radeon_private_t *dev_priv = dev->dev_private;
1653 1659
1654 if ( !dev_priv ) { 1660 if (!dev_priv) {
1655 DRM_ERROR( "Called with no initialization\n" ); 1661 DRM_ERROR("Called with no initialization\n");
1656 return DRM_ERR( EINVAL ); 1662 return DRM_ERR(EINVAL);
1657 } 1663 }
1658 1664
1659 DRM_DEBUG("Starting radeon_do_resume_cp()\n"); 1665 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1660 1666
1661#if __OS_HAS_AGP 1667#if __OS_HAS_AGP
1662 if ( !dev_priv->is_pci ) { 1668 if (!dev_priv->is_pci) {
1663 /* Turn off PCI GART */ 1669 /* Turn off PCI GART */
1664 radeon_set_pcigart( dev_priv, 0 ); 1670 radeon_set_pcigart(dev_priv, 0);
1665 } else 1671 } else
1666#endif 1672#endif
1667 { 1673 {
1668 /* Turn on PCI GART */ 1674 /* Turn on PCI GART */
1669 radeon_set_pcigart( dev_priv, 1 ); 1675 radeon_set_pcigart(dev_priv, 1);
1670 } 1676 }
1671 1677
1672 radeon_cp_load_microcode( dev_priv ); 1678 radeon_cp_load_microcode(dev_priv);
1673 radeon_cp_init_ring_buffer( dev, dev_priv ); 1679 radeon_cp_init_ring_buffer(dev, dev_priv);
1674 1680
1675 radeon_do_engine_reset( dev ); 1681 radeon_do_engine_reset(dev);
1676 1682
1677 DRM_DEBUG("radeon_do_resume_cp() complete\n"); 1683 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1678 1684
1679 return 0; 1685 return 0;
1680} 1686}
1681 1687
1682 1688int radeon_cp_init(DRM_IOCTL_ARGS)
1683int radeon_cp_init( DRM_IOCTL_ARGS )
1684{ 1689{
1685 DRM_DEVICE; 1690 DRM_DEVICE;
1686 drm_radeon_init_t init; 1691 drm_radeon_init_t init;
1687 1692
1688 LOCK_TEST_WITH_RETURN( dev, filp ); 1693 LOCK_TEST_WITH_RETURN(dev, filp);
1689 1694
1690 DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t __user *)data, sizeof(init) ); 1695 DRM_COPY_FROM_USER_IOCTL(init, (drm_radeon_init_t __user *) data,
1696 sizeof(init));
1691 1697
1692 if(init.func == RADEON_INIT_R300_CP) 1698 if (init.func == RADEON_INIT_R300_CP)
1693 r300_init_reg_flags(); 1699 r300_init_reg_flags();
1694 1700
1695 switch ( init.func ) { 1701 switch (init.func) {
1696 case RADEON_INIT_CP: 1702 case RADEON_INIT_CP:
1697 case RADEON_INIT_R200_CP: 1703 case RADEON_INIT_R200_CP:
1698 case RADEON_INIT_R300_CP: 1704 case RADEON_INIT_R300_CP:
1699 return radeon_do_init_cp( dev, &init ); 1705 return radeon_do_init_cp(dev, &init);
1700 case RADEON_CLEANUP_CP: 1706 case RADEON_CLEANUP_CP:
1701 return radeon_do_cleanup_cp( dev ); 1707 return radeon_do_cleanup_cp(dev);
1702 } 1708 }
1703 1709
1704 return DRM_ERR(EINVAL); 1710 return DRM_ERR(EINVAL);
1705} 1711}
1706 1712
1707int radeon_cp_start( DRM_IOCTL_ARGS ) 1713int radeon_cp_start(DRM_IOCTL_ARGS)
1708{ 1714{
1709 DRM_DEVICE; 1715 DRM_DEVICE;
1710 drm_radeon_private_t *dev_priv = dev->dev_private; 1716 drm_radeon_private_t *dev_priv = dev->dev_private;
1711 DRM_DEBUG( "\n" ); 1717 DRM_DEBUG("\n");
1712 1718
1713 LOCK_TEST_WITH_RETURN( dev, filp ); 1719 LOCK_TEST_WITH_RETURN(dev, filp);
1714 1720
1715 if ( dev_priv->cp_running ) { 1721 if (dev_priv->cp_running) {
1716 DRM_DEBUG( "%s while CP running\n", __FUNCTION__ ); 1722 DRM_DEBUG("%s while CP running\n", __FUNCTION__);
1717 return 0; 1723 return 0;
1718 } 1724 }
1719 if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) { 1725 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1720 DRM_DEBUG( "%s called with bogus CP mode (%d)\n", 1726 DRM_DEBUG("%s called with bogus CP mode (%d)\n",
1721 __FUNCTION__, dev_priv->cp_mode ); 1727 __FUNCTION__, dev_priv->cp_mode);
1722 return 0; 1728 return 0;
1723 } 1729 }
1724 1730
1725 radeon_do_cp_start( dev_priv ); 1731 radeon_do_cp_start(dev_priv);
1726 1732
1727 return 0; 1733 return 0;
1728} 1734}
@@ -1730,17 +1736,18 @@ int radeon_cp_start( DRM_IOCTL_ARGS )
1730/* Stop the CP. The engine must have been idled before calling this 1736/* Stop the CP. The engine must have been idled before calling this
1731 * routine. 1737 * routine.
1732 */ 1738 */
1733int radeon_cp_stop( DRM_IOCTL_ARGS ) 1739int radeon_cp_stop(DRM_IOCTL_ARGS)
1734{ 1740{
1735 DRM_DEVICE; 1741 DRM_DEVICE;
1736 drm_radeon_private_t *dev_priv = dev->dev_private; 1742 drm_radeon_private_t *dev_priv = dev->dev_private;
1737 drm_radeon_cp_stop_t stop; 1743 drm_radeon_cp_stop_t stop;
1738 int ret; 1744 int ret;
1739 DRM_DEBUG( "\n" ); 1745 DRM_DEBUG("\n");
1740 1746
1741 LOCK_TEST_WITH_RETURN( dev, filp ); 1747 LOCK_TEST_WITH_RETURN(dev, filp);
1742 1748
1743 DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t __user *)data, sizeof(stop) ); 1749 DRM_COPY_FROM_USER_IOCTL(stop, (drm_radeon_cp_stop_t __user *) data,
1750 sizeof(stop));
1744 1751
1745 if (!dev_priv->cp_running) 1752 if (!dev_priv->cp_running)
1746 return 0; 1753 return 0;
@@ -1748,32 +1755,32 @@ int radeon_cp_stop( DRM_IOCTL_ARGS )
1748 /* Flush any pending CP commands. This ensures any outstanding 1755 /* Flush any pending CP commands. This ensures any outstanding
1749 * commands are exectuted by the engine before we turn it off. 1756 * commands are exectuted by the engine before we turn it off.
1750 */ 1757 */
1751 if ( stop.flush ) { 1758 if (stop.flush) {
1752 radeon_do_cp_flush( dev_priv ); 1759 radeon_do_cp_flush(dev_priv);
1753 } 1760 }
1754 1761
1755 /* If we fail to make the engine go idle, we return an error 1762 /* If we fail to make the engine go idle, we return an error
1756 * code so that the DRM ioctl wrapper can try again. 1763 * code so that the DRM ioctl wrapper can try again.
1757 */ 1764 */
1758 if ( stop.idle ) { 1765 if (stop.idle) {
1759 ret = radeon_do_cp_idle( dev_priv ); 1766 ret = radeon_do_cp_idle(dev_priv);
1760 if ( ret ) return ret; 1767 if (ret)
1768 return ret;
1761 } 1769 }
1762 1770
1763 /* Finally, we can turn off the CP. If the engine isn't idle, 1771 /* Finally, we can turn off the CP. If the engine isn't idle,
1764 * we will get some dropped triangles as they won't be fully 1772 * we will get some dropped triangles as they won't be fully
1765 * rendered before the CP is shut down. 1773 * rendered before the CP is shut down.
1766 */ 1774 */
1767 radeon_do_cp_stop( dev_priv ); 1775 radeon_do_cp_stop(dev_priv);
1768 1776
1769 /* Reset the engine */ 1777 /* Reset the engine */
1770 radeon_do_engine_reset( dev ); 1778 radeon_do_engine_reset(dev);
1771 1779
1772 return 0; 1780 return 0;
1773} 1781}
1774 1782
1775 1783void radeon_do_release(drm_device_t * dev)
1776void radeon_do_release( drm_device_t *dev )
1777{ 1784{
1778 drm_radeon_private_t *dev_priv = dev->dev_private; 1785 drm_radeon_private_t *dev_priv = dev->dev_private;
1779 int i, ret; 1786 int i, ret;
@@ -1781,7 +1788,7 @@ void radeon_do_release( drm_device_t *dev )
1781 if (dev_priv) { 1788 if (dev_priv) {
1782 if (dev_priv->cp_running) { 1789 if (dev_priv->cp_running) {
1783 /* Stop the cp */ 1790 /* Stop the cp */
1784 while ((ret = radeon_do_cp_idle( dev_priv )) != 0) { 1791 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1785 DRM_DEBUG("radeon_do_cp_idle %d\n", ret); 1792 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1786#ifdef __linux__ 1793#ifdef __linux__
1787 schedule(); 1794 schedule();
@@ -1789,47 +1796,49 @@ void radeon_do_release( drm_device_t *dev )
1789 tsleep(&ret, PZERO, "rdnrel", 1); 1796 tsleep(&ret, PZERO, "rdnrel", 1);
1790#endif 1797#endif
1791 } 1798 }
1792 radeon_do_cp_stop( dev_priv ); 1799 radeon_do_cp_stop(dev_priv);
1793 radeon_do_engine_reset( dev ); 1800 radeon_do_engine_reset(dev);
1794 } 1801 }
1795 1802
1796 /* Disable *all* interrupts */ 1803 /* Disable *all* interrupts */
1797 if (dev_priv->mmio) /* remove this after permanent addmaps */ 1804 if (dev_priv->mmio) /* remove this after permanent addmaps */
1798 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 ); 1805 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1799 1806
1800 if (dev_priv->mmio) {/* remove all surfaces */ 1807 if (dev_priv->mmio) { /* remove all surfaces */
1801 for (i = 0; i < RADEON_MAX_SURFACES; i++) { 1808 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1802 RADEON_WRITE(RADEON_SURFACE0_INFO + 16*i, 0); 1809 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1803 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*i, 0); 1810 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1804 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*i, 0); 1811 16 * i, 0);
1812 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1813 16 * i, 0);
1805 } 1814 }
1806 } 1815 }
1807 1816
1808 /* Free memory heap structures */ 1817 /* Free memory heap structures */
1809 radeon_mem_takedown( &(dev_priv->gart_heap) ); 1818 radeon_mem_takedown(&(dev_priv->gart_heap));
1810 radeon_mem_takedown( &(dev_priv->fb_heap) ); 1819 radeon_mem_takedown(&(dev_priv->fb_heap));
1811 1820
1812 /* deallocate kernel resources */ 1821 /* deallocate kernel resources */
1813 radeon_do_cleanup_cp( dev ); 1822 radeon_do_cleanup_cp(dev);
1814 } 1823 }
1815} 1824}
1816 1825
1817/* Just reset the CP ring. Called as part of an X Server engine reset. 1826/* Just reset the CP ring. Called as part of an X Server engine reset.
1818 */ 1827 */
1819int radeon_cp_reset( DRM_IOCTL_ARGS ) 1828int radeon_cp_reset(DRM_IOCTL_ARGS)
1820{ 1829{
1821 DRM_DEVICE; 1830 DRM_DEVICE;
1822 drm_radeon_private_t *dev_priv = dev->dev_private; 1831 drm_radeon_private_t *dev_priv = dev->dev_private;
1823 DRM_DEBUG( "\n" ); 1832 DRM_DEBUG("\n");
1824 1833
1825 LOCK_TEST_WITH_RETURN( dev, filp ); 1834 LOCK_TEST_WITH_RETURN(dev, filp);
1826 1835
1827 if ( !dev_priv ) { 1836 if (!dev_priv) {
1828 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ ); 1837 DRM_DEBUG("%s called before init done\n", __FUNCTION__);
1829 return DRM_ERR(EINVAL); 1838 return DRM_ERR(EINVAL);
1830 } 1839 }
1831 1840
1832 radeon_do_cp_reset( dev_priv ); 1841 radeon_do_cp_reset(dev_priv);
1833 1842
1834 /* The CP is no longer running after an engine reset */ 1843 /* The CP is no longer running after an engine reset */
1835 dev_priv->cp_running = 0; 1844 dev_priv->cp_running = 0;
@@ -1837,50 +1846,47 @@ int radeon_cp_reset( DRM_IOCTL_ARGS )
1837 return 0; 1846 return 0;
1838} 1847}
1839 1848
1840int radeon_cp_idle( DRM_IOCTL_ARGS ) 1849int radeon_cp_idle(DRM_IOCTL_ARGS)
1841{ 1850{
1842 DRM_DEVICE; 1851 DRM_DEVICE;
1843 drm_radeon_private_t *dev_priv = dev->dev_private; 1852 drm_radeon_private_t *dev_priv = dev->dev_private;
1844 DRM_DEBUG( "\n" ); 1853 DRM_DEBUG("\n");
1845 1854
1846 LOCK_TEST_WITH_RETURN( dev, filp ); 1855 LOCK_TEST_WITH_RETURN(dev, filp);
1847 1856
1848 return radeon_do_cp_idle( dev_priv ); 1857 return radeon_do_cp_idle(dev_priv);
1849} 1858}
1850 1859
1851/* Added by Charl P. Botha to call radeon_do_resume_cp(). 1860/* Added by Charl P. Botha to call radeon_do_resume_cp().
1852 */ 1861 */
1853int radeon_cp_resume( DRM_IOCTL_ARGS ) 1862int radeon_cp_resume(DRM_IOCTL_ARGS)
1854{ 1863{
1855 DRM_DEVICE; 1864 DRM_DEVICE;
1856 1865
1857 return radeon_do_resume_cp(dev); 1866 return radeon_do_resume_cp(dev);
1858} 1867}
1859 1868
1860 1869int radeon_engine_reset(DRM_IOCTL_ARGS)
1861int radeon_engine_reset( DRM_IOCTL_ARGS )
1862{ 1870{
1863 DRM_DEVICE; 1871 DRM_DEVICE;
1864 DRM_DEBUG( "\n" ); 1872 DRM_DEBUG("\n");
1865 1873
1866 LOCK_TEST_WITH_RETURN( dev, filp ); 1874 LOCK_TEST_WITH_RETURN(dev, filp);
1867 1875
1868 return radeon_do_engine_reset( dev ); 1876 return radeon_do_engine_reset(dev);
1869} 1877}
1870 1878
1871
1872/* ================================================================ 1879/* ================================================================
1873 * Fullscreen mode 1880 * Fullscreen mode
1874 */ 1881 */
1875 1882
1876/* KW: Deprecated to say the least: 1883/* KW: Deprecated to say the least:
1877 */ 1884 */
1878int radeon_fullscreen( DRM_IOCTL_ARGS ) 1885int radeon_fullscreen(DRM_IOCTL_ARGS)
1879{ 1886{
1880 return 0; 1887 return 0;
1881} 1888}
1882 1889
1883
1884/* ================================================================ 1890/* ================================================================
1885 * Freelist management 1891 * Freelist management
1886 */ 1892 */
@@ -1889,20 +1895,20 @@ int radeon_fullscreen( DRM_IOCTL_ARGS )
1889 * bufs until freelist code is used. Note this hides a problem with 1895 * bufs until freelist code is used. Note this hides a problem with
1890 * the scratch register * (used to keep track of last buffer 1896 * the scratch register * (used to keep track of last buffer
1891 * completed) being written to before * the last buffer has actually 1897 * completed) being written to before * the last buffer has actually
1892 * completed rendering. 1898 * completed rendering.
1893 * 1899 *
1894 * KW: It's also a good way to find free buffers quickly. 1900 * KW: It's also a good way to find free buffers quickly.
1895 * 1901 *
1896 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't 1902 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1897 * sleep. However, bugs in older versions of radeon_accel.c mean that 1903 * sleep. However, bugs in older versions of radeon_accel.c mean that
1898 * we essentially have to do this, else old clients will break. 1904 * we essentially have to do this, else old clients will break.
1899 * 1905 *
1900 * However, it does leave open a potential deadlock where all the 1906 * However, it does leave open a potential deadlock where all the
1901 * buffers are held by other clients, which can't release them because 1907 * buffers are held by other clients, which can't release them because
1902 * they can't get the lock. 1908 * they can't get the lock.
1903 */ 1909 */
1904 1910
1905drm_buf_t *radeon_freelist_get( drm_device_t *dev ) 1911drm_buf_t *radeon_freelist_get(drm_device_t * dev)
1906{ 1912{
1907 drm_device_dma_t *dma = dev->dma; 1913 drm_device_dma_t *dma = dev->dma;
1908 drm_radeon_private_t *dev_priv = dev->dev_private; 1914 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -1911,19 +1917,19 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1911 int i, t; 1917 int i, t;
1912 int start; 1918 int start;
1913 1919
1914 if ( ++dev_priv->last_buf >= dma->buf_count ) 1920 if (++dev_priv->last_buf >= dma->buf_count)
1915 dev_priv->last_buf = 0; 1921 dev_priv->last_buf = 0;
1916 1922
1917 start = dev_priv->last_buf; 1923 start = dev_priv->last_buf;
1918 1924
1919 for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) { 1925 for (t = 0; t < dev_priv->usec_timeout; t++) {
1920 u32 done_age = GET_SCRATCH( 1 ); 1926 u32 done_age = GET_SCRATCH(1);
1921 DRM_DEBUG("done_age = %d\n",done_age); 1927 DRM_DEBUG("done_age = %d\n", done_age);
1922 for ( i = start ; i < dma->buf_count ; i++ ) { 1928 for (i = start; i < dma->buf_count; i++) {
1923 buf = dma->buflist[i]; 1929 buf = dma->buflist[i];
1924 buf_priv = buf->dev_private; 1930 buf_priv = buf->dev_private;
1925 if ( buf->filp == 0 || (buf->pending && 1931 if (buf->filp == 0 || (buf->pending &&
1926 buf_priv->age <= done_age) ) { 1932 buf_priv->age <= done_age)) {
1927 dev_priv->stats.requested_bufs++; 1933 dev_priv->stats.requested_bufs++;
1928 buf->pending = 0; 1934 buf->pending = 0;
1929 return buf; 1935 return buf;
@@ -1932,16 +1938,17 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1932 } 1938 }
1933 1939
1934 if (t) { 1940 if (t) {
1935 DRM_UDELAY( 1 ); 1941 DRM_UDELAY(1);
1936 dev_priv->stats.freelist_loops++; 1942 dev_priv->stats.freelist_loops++;
1937 } 1943 }
1938 } 1944 }
1939 1945
1940 DRM_DEBUG( "returning NULL!\n" ); 1946 DRM_DEBUG("returning NULL!\n");
1941 return NULL; 1947 return NULL;
1942} 1948}
1949
1943#if 0 1950#if 0
1944drm_buf_t *radeon_freelist_get( drm_device_t *dev ) 1951drm_buf_t *radeon_freelist_get(drm_device_t * dev)
1945{ 1952{
1946 drm_device_dma_t *dma = dev->dma; 1953 drm_device_dma_t *dma = dev->dma;
1947 drm_radeon_private_t *dev_priv = dev->dev_private; 1954 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -1951,18 +1958,18 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1951 int start; 1958 int start;
1952 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); 1959 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1953 1960
1954 if ( ++dev_priv->last_buf >= dma->buf_count ) 1961 if (++dev_priv->last_buf >= dma->buf_count)
1955 dev_priv->last_buf = 0; 1962 dev_priv->last_buf = 0;
1956 1963
1957 start = dev_priv->last_buf; 1964 start = dev_priv->last_buf;
1958 dev_priv->stats.freelist_loops++; 1965 dev_priv->stats.freelist_loops++;
1959 1966
1960 for ( t = 0 ; t < 2 ; t++ ) { 1967 for (t = 0; t < 2; t++) {
1961 for ( i = start ; i < dma->buf_count ; i++ ) { 1968 for (i = start; i < dma->buf_count; i++) {
1962 buf = dma->buflist[i]; 1969 buf = dma->buflist[i];
1963 buf_priv = buf->dev_private; 1970 buf_priv = buf->dev_private;
1964 if ( buf->filp == 0 || (buf->pending && 1971 if (buf->filp == 0 || (buf->pending &&
1965 buf_priv->age <= done_age) ) { 1972 buf_priv->age <= done_age)) {
1966 dev_priv->stats.requested_bufs++; 1973 dev_priv->stats.requested_bufs++;
1967 buf->pending = 0; 1974 buf->pending = 0;
1968 return buf; 1975 return buf;
@@ -1975,73 +1982,74 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1975} 1982}
1976#endif 1983#endif
1977 1984
1978void radeon_freelist_reset( drm_device_t *dev ) 1985void radeon_freelist_reset(drm_device_t * dev)
1979{ 1986{
1980 drm_device_dma_t *dma = dev->dma; 1987 drm_device_dma_t *dma = dev->dma;
1981 drm_radeon_private_t *dev_priv = dev->dev_private; 1988 drm_radeon_private_t *dev_priv = dev->dev_private;
1982 int i; 1989 int i;
1983 1990
1984 dev_priv->last_buf = 0; 1991 dev_priv->last_buf = 0;
1985 for ( i = 0 ; i < dma->buf_count ; i++ ) { 1992 for (i = 0; i < dma->buf_count; i++) {
1986 drm_buf_t *buf = dma->buflist[i]; 1993 drm_buf_t *buf = dma->buflist[i];
1987 drm_radeon_buf_priv_t *buf_priv = buf->dev_private; 1994 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1988 buf_priv->age = 0; 1995 buf_priv->age = 0;
1989 } 1996 }
1990} 1997}
1991 1998
1992
1993/* ================================================================ 1999/* ================================================================
1994 * CP command submission 2000 * CP command submission
1995 */ 2001 */
1996 2002
1997int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n ) 2003int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1998{ 2004{
1999 drm_radeon_ring_buffer_t *ring = &dev_priv->ring; 2005 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
2000 int i; 2006 int i;
2001 u32 last_head = GET_RING_HEAD( dev_priv ); 2007 u32 last_head = GET_RING_HEAD(dev_priv);
2002 2008
2003 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 2009 for (i = 0; i < dev_priv->usec_timeout; i++) {
2004 u32 head = GET_RING_HEAD( dev_priv ); 2010 u32 head = GET_RING_HEAD(dev_priv);
2005 2011
2006 ring->space = (head - ring->tail) * sizeof(u32); 2012 ring->space = (head - ring->tail) * sizeof(u32);
2007 if ( ring->space <= 0 ) 2013 if (ring->space <= 0)
2008 ring->space += ring->size; 2014 ring->space += ring->size;
2009 if ( ring->space > n ) 2015 if (ring->space > n)
2010 return 0; 2016 return 0;
2011 2017
2012 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 2018 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2013 2019
2014 if (head != last_head) 2020 if (head != last_head)
2015 i = 0; 2021 i = 0;
2016 last_head = head; 2022 last_head = head;
2017 2023
2018 DRM_UDELAY( 1 ); 2024 DRM_UDELAY(1);
2019 } 2025 }
2020 2026
2021 /* FIXME: This return value is ignored in the BEGIN_RING macro! */ 2027 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2022#if RADEON_FIFO_DEBUG 2028#if RADEON_FIFO_DEBUG
2023 radeon_status( dev_priv ); 2029 radeon_status(dev_priv);
2024 DRM_ERROR( "failed!\n" ); 2030 DRM_ERROR("failed!\n");
2025#endif 2031#endif
2026 return DRM_ERR(EBUSY); 2032 return DRM_ERR(EBUSY);
2027} 2033}
2028 2034
2029static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d ) 2035static int radeon_cp_get_buffers(DRMFILE filp, drm_device_t * dev,
2036 drm_dma_t * d)
2030{ 2037{
2031 int i; 2038 int i;
2032 drm_buf_t *buf; 2039 drm_buf_t *buf;
2033 2040
2034 for ( i = d->granted_count ; i < d->request_count ; i++ ) { 2041 for (i = d->granted_count; i < d->request_count; i++) {
2035 buf = radeon_freelist_get( dev ); 2042 buf = radeon_freelist_get(dev);
2036 if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */ 2043 if (!buf)
2044 return DRM_ERR(EBUSY); /* NOTE: broken client */
2037 2045
2038 buf->filp = filp; 2046 buf->filp = filp;
2039 2047
2040 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx, 2048 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2041 sizeof(buf->idx) ) ) 2049 sizeof(buf->idx)))
2042 return DRM_ERR(EFAULT); 2050 return DRM_ERR(EFAULT);
2043 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total, 2051 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2044 sizeof(buf->total) ) ) 2052 sizeof(buf->total)))
2045 return DRM_ERR(EFAULT); 2053 return DRM_ERR(EFAULT);
2046 2054
2047 d->granted_count++; 2055 d->granted_count++;
@@ -2049,7 +2057,7 @@ static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d
2049 return 0; 2057 return 0;
2050} 2058}
2051 2059
2052int radeon_cp_buffers( DRM_IOCTL_ARGS ) 2060int radeon_cp_buffers(DRM_IOCTL_ARGS)
2053{ 2061{
2054 DRM_DEVICE; 2062 DRM_DEVICE;
2055 drm_device_dma_t *dma = dev->dma; 2063 drm_device_dma_t *dma = dev->dma;
@@ -2057,33 +2065,33 @@ int radeon_cp_buffers( DRM_IOCTL_ARGS )
2057 drm_dma_t __user *argp = (void __user *)data; 2065 drm_dma_t __user *argp = (void __user *)data;
2058 drm_dma_t d; 2066 drm_dma_t d;
2059 2067
2060 LOCK_TEST_WITH_RETURN( dev, filp ); 2068 LOCK_TEST_WITH_RETURN(dev, filp);
2061 2069
2062 DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) ); 2070 DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
2063 2071
2064 /* Please don't send us buffers. 2072 /* Please don't send us buffers.
2065 */ 2073 */
2066 if ( d.send_count != 0 ) { 2074 if (d.send_count != 0) {
2067 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", 2075 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2068 DRM_CURRENTPID, d.send_count ); 2076 DRM_CURRENTPID, d.send_count);
2069 return DRM_ERR(EINVAL); 2077 return DRM_ERR(EINVAL);
2070 } 2078 }
2071 2079
2072 /* We'll send you buffers. 2080 /* We'll send you buffers.
2073 */ 2081 */
2074 if ( d.request_count < 0 || d.request_count > dma->buf_count ) { 2082 if (d.request_count < 0 || d.request_count > dma->buf_count) {
2075 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", 2083 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2076 DRM_CURRENTPID, d.request_count, dma->buf_count ); 2084 DRM_CURRENTPID, d.request_count, dma->buf_count);
2077 return DRM_ERR(EINVAL); 2085 return DRM_ERR(EINVAL);
2078 } 2086 }
2079 2087
2080 d.granted_count = 0; 2088 d.granted_count = 0;
2081 2089
2082 if ( d.request_count ) { 2090 if (d.request_count) {
2083 ret = radeon_cp_get_buffers( filp, dev, &d ); 2091 ret = radeon_cp_get_buffers(filp, dev, &d);
2084 } 2092 }
2085 2093
2086 DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) ); 2094 DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
2087 2095
2088 return ret; 2096 return ret;
2089} 2097}
@@ -2110,13 +2118,13 @@ int radeon_driver_preinit(struct drm_device *dev, unsigned long flags)
2110 dev_priv->flags |= CHIP_HAS_HIERZ; 2118 dev_priv->flags |= CHIP_HAS_HIERZ;
2111 break; 2119 break;
2112 default: 2120 default:
2113 /* all other chips have no hierarchical z buffer */ 2121 /* all other chips have no hierarchical z buffer */
2114 break; 2122 break;
2115 } 2123 }
2116 2124
2117 if (drm_device_is_agp(dev)) 2125 if (drm_device_is_agp(dev))
2118 dev_priv->flags |= CHIP_IS_AGP; 2126 dev_priv->flags |= CHIP_IS_AGP;
2119 2127
2120 if (drm_device_is_pcie(dev)) 2128 if (drm_device_is_pcie(dev))
2121 dev_priv->flags |= CHIP_IS_PCIE; 2129 dev_priv->flags |= CHIP_IS_PCIE;
2122 2130
diff --git a/drivers/char/drm/radeon_drm.h b/drivers/char/drm/radeon_drm.h
index dd526617faec..1cd81a671a36 100644
--- a/drivers/char/drm/radeon_drm.h
+++ b/drivers/char/drm/radeon_drm.h
@@ -57,78 +57,77 @@
57#define RADEON_UPLOAD_TEX0IMAGES 0x00001000 57#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
58#define RADEON_UPLOAD_TEX1IMAGES 0x00002000 58#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
59#define RADEON_UPLOAD_TEX2IMAGES 0x00004000 59#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
60#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ 60#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
61#define RADEON_REQUIRE_QUIESCENCE 0x00010000 61#define RADEON_REQUIRE_QUIESCENCE 0x00010000
62#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ 62#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */
63#define RADEON_UPLOAD_ALL 0x003effff 63#define RADEON_UPLOAD_ALL 0x003effff
64#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff 64#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
65 65
66
67/* New style per-packet identifiers for use in cmd_buffer ioctl with 66/* New style per-packet identifiers for use in cmd_buffer ioctl with
68 * the RADEON_EMIT_PACKET command. Comments relate new packets to old 67 * the RADEON_EMIT_PACKET command. Comments relate new packets to old
69 * state bits and the packet size: 68 * state bits and the packet size:
70 */ 69 */
71#define RADEON_EMIT_PP_MISC 0 /* context/7 */ 70#define RADEON_EMIT_PP_MISC 0 /* context/7 */
72#define RADEON_EMIT_PP_CNTL 1 /* context/3 */ 71#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
73#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ 72#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
74#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ 73#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
75#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ 74#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
76#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ 75#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
77#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ 76#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
78#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ 77#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
79#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ 78#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
80#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ 79#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
81#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ 80#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
82#define RADEON_EMIT_RE_MISC 11 /* misc/1 */ 81#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
83#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ 82#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
84#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ 83#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
85#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ 84#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
86#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ 85#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
87#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ 86#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
88#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ 87#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
89#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ 88#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
90#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ 89#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
91#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ 90#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
92#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ 91#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
93#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ 92#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
94#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ 93#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
95#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ 94#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
96#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ 95#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
97#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ 96#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
98#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ 97#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
99#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ 98#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
100#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ 99#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */
101#define R200_EMIT_TFACTOR_0 30 /* tf/7 */ 100#define R200_EMIT_TFACTOR_0 30 /* tf/7 */
102#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ 101#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */
103#define R200_EMIT_VAP_CTL 32 /* vap/1 */ 102#define R200_EMIT_VAP_CTL 32 /* vap/1 */
104#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ 103#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
105#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ 104#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
106#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ 105#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
107#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ 106#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
108#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ 107#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
109#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ 108#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
110#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ 109#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
111#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ 110#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
112#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ 111#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
113#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ 112#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
114#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ 113#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
115#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ 114#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
116#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ 115#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
117#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ 116#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
118#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ 117#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
119#define R200_EMIT_VTE_CNTL 48 /* vte/1 */ 118#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
120#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ 119#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
121#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ 120#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
122#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ 121#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
123#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ 122#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
124#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ 123#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
125#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ 124#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
126#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ 125#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
127#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ 126#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
128#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ 127#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
129#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ 128#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
130#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ 129#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
131#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ 130#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
132#define R200_EMIT_PP_CUBIC_FACES_0 61 131#define R200_EMIT_PP_CUBIC_FACES_0 61
133#define R200_EMIT_PP_CUBIC_OFFSETS_0 62 132#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
134#define R200_EMIT_PP_CUBIC_FACES_1 63 133#define R200_EMIT_PP_CUBIC_FACES_1 63
@@ -167,37 +166,36 @@
167/* Commands understood by cmd_buffer ioctl. More can be added but 166/* Commands understood by cmd_buffer ioctl. More can be added but
168 * obviously these can't be removed or changed: 167 * obviously these can't be removed or changed:
169 */ 168 */
170#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ 169#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
171#define RADEON_CMD_SCALARS 2 /* emit scalar data */ 170#define RADEON_CMD_SCALARS 2 /* emit scalar data */
172#define RADEON_CMD_VECTORS 3 /* emit vector data */ 171#define RADEON_CMD_VECTORS 3 /* emit vector data */
173#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ 172#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
174#define RADEON_CMD_PACKET3 5 /* emit hw packet */ 173#define RADEON_CMD_PACKET3 5 /* emit hw packet */
175#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ 174#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
176#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ 175#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */
177#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: 176#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
178 * doesn't make the cpu wait, just 177 * doesn't make the cpu wait, just
179 * the graphics hardware */ 178 * the graphics hardware */
180
181 179
182typedef union { 180typedef union {
183 int i; 181 int i;
184 struct { 182 struct {
185 unsigned char cmd_type, pad0, pad1, pad2; 183 unsigned char cmd_type, pad0, pad1, pad2;
186 } header; 184 } header;
187 struct { 185 struct {
188 unsigned char cmd_type, packet_id, pad0, pad1; 186 unsigned char cmd_type, packet_id, pad0, pad1;
189 } packet; 187 } packet;
190 struct { 188 struct {
191 unsigned char cmd_type, offset, stride, count; 189 unsigned char cmd_type, offset, stride, count;
192 } scalars; 190 } scalars;
193 struct { 191 struct {
194 unsigned char cmd_type, offset, stride, count; 192 unsigned char cmd_type, offset, stride, count;
195 } vectors; 193 } vectors;
196 struct { 194 struct {
197 unsigned char cmd_type, buf_idx, pad0, pad1; 195 unsigned char cmd_type, buf_idx, pad0, pad1;
198 } dma; 196 } dma;
199 struct { 197 struct {
200 unsigned char cmd_type, flags, pad0, pad1; 198 unsigned char cmd_type, flags, pad0, pad1;
201 } wait; 199 } wait;
202} drm_radeon_cmd_header_t; 200} drm_radeon_cmd_header_t;
203 201
@@ -213,10 +211,10 @@ typedef union {
213 * The interface has not been stabilized, so some of these may be removed 211 * The interface has not been stabilized, so some of these may be removed
214 * and eventually reordered before stabilization. 212 * and eventually reordered before stabilization.
215 */ 213 */
216#define R300_CMD_PACKET0 1 214#define R300_CMD_PACKET0 1
217#define R300_CMD_VPU 2 /* emit vertex program upload */ 215#define R300_CMD_VPU 2 /* emit vertex program upload */
218#define R300_CMD_PACKET3 3 /* emit a packet3 */ 216#define R300_CMD_PACKET3 3 /* emit a packet3 */
219#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */ 217#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */
220#define R300_CMD_CP_DELAY 5 218#define R300_CMD_CP_DELAY 5
221#define R300_CMD_DMA_DISCARD 6 219#define R300_CMD_DMA_DISCARD 6
222#define R300_CMD_WAIT 7 220#define R300_CMD_WAIT 7
@@ -241,13 +239,13 @@ typedef union {
241 } packet3; 239 } packet3;
242 struct { 240 struct {
243 unsigned char cmd_type, packet; 241 unsigned char cmd_type, packet;
244 unsigned short count; /* amount of packet2 to emit */ 242 unsigned short count; /* amount of packet2 to emit */
245 } delay; 243 } delay;
246 struct { 244 struct {
247 unsigned char cmd_type, buf_idx, pad0, pad1; 245 unsigned char cmd_type, buf_idx, pad0, pad1;
248 } dma; 246 } dma;
249 struct { 247 struct {
250 unsigned char cmd_type, flags, pad0, pad1; 248 unsigned char cmd_type, flags, pad0, pad1;
251 } wait; 249 } wait;
252} drm_r300_cmd_header_t; 250} drm_r300_cmd_header_t;
253 251
@@ -301,7 +299,7 @@ typedef union {
301#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) 299#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
302#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) 300#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
303 301
304#endif /* __RADEON_SAREA_DEFINES__ */ 302#endif /* __RADEON_SAREA_DEFINES__ */
305 303
306typedef struct { 304typedef struct {
307 unsigned int red; 305 unsigned int red;
@@ -312,7 +310,7 @@ typedef struct {
312 310
313typedef struct { 311typedef struct {
314 /* Context state */ 312 /* Context state */
315 unsigned int pp_misc; /* 0x1c14 */ 313 unsigned int pp_misc; /* 0x1c14 */
316 unsigned int pp_fog_color; 314 unsigned int pp_fog_color;
317 unsigned int re_solid_color; 315 unsigned int re_solid_color;
318 unsigned int rb3d_blendcntl; 316 unsigned int rb3d_blendcntl;
@@ -320,7 +318,7 @@ typedef struct {
320 unsigned int rb3d_depthpitch; 318 unsigned int rb3d_depthpitch;
321 unsigned int rb3d_zstencilcntl; 319 unsigned int rb3d_zstencilcntl;
322 320
323 unsigned int pp_cntl; /* 0x1c38 */ 321 unsigned int pp_cntl; /* 0x1c38 */
324 unsigned int rb3d_cntl; 322 unsigned int rb3d_cntl;
325 unsigned int rb3d_coloroffset; 323 unsigned int rb3d_coloroffset;
326 unsigned int re_width_height; 324 unsigned int re_width_height;
@@ -328,27 +326,27 @@ typedef struct {
328 unsigned int se_cntl; 326 unsigned int se_cntl;
329 327
330 /* Vertex format state */ 328 /* Vertex format state */
331 unsigned int se_coord_fmt; /* 0x1c50 */ 329 unsigned int se_coord_fmt; /* 0x1c50 */
332 330
333 /* Line state */ 331 /* Line state */
334 unsigned int re_line_pattern; /* 0x1cd0 */ 332 unsigned int re_line_pattern; /* 0x1cd0 */
335 unsigned int re_line_state; 333 unsigned int re_line_state;
336 334
337 unsigned int se_line_width; /* 0x1db8 */ 335 unsigned int se_line_width; /* 0x1db8 */
338 336
339 /* Bumpmap state */ 337 /* Bumpmap state */
340 unsigned int pp_lum_matrix; /* 0x1d00 */ 338 unsigned int pp_lum_matrix; /* 0x1d00 */
341 339
342 unsigned int pp_rot_matrix_0; /* 0x1d58 */ 340 unsigned int pp_rot_matrix_0; /* 0x1d58 */
343 unsigned int pp_rot_matrix_1; 341 unsigned int pp_rot_matrix_1;
344 342
345 /* Mask state */ 343 /* Mask state */
346 unsigned int rb3d_stencilrefmask; /* 0x1d7c */ 344 unsigned int rb3d_stencilrefmask; /* 0x1d7c */
347 unsigned int rb3d_ropcntl; 345 unsigned int rb3d_ropcntl;
348 unsigned int rb3d_planemask; 346 unsigned int rb3d_planemask;
349 347
350 /* Viewport state */ 348 /* Viewport state */
351 unsigned int se_vport_xscale; /* 0x1d98 */ 349 unsigned int se_vport_xscale; /* 0x1d98 */
352 unsigned int se_vport_xoffset; 350 unsigned int se_vport_xoffset;
353 unsigned int se_vport_yscale; 351 unsigned int se_vport_yscale;
354 unsigned int se_vport_yoffset; 352 unsigned int se_vport_yoffset;
@@ -356,20 +354,19 @@ typedef struct {
356 unsigned int se_vport_zoffset; 354 unsigned int se_vport_zoffset;
357 355
358 /* Setup state */ 356 /* Setup state */
359 unsigned int se_cntl_status; /* 0x2140 */ 357 unsigned int se_cntl_status; /* 0x2140 */
360 358
361 /* Misc state */ 359 /* Misc state */
362 unsigned int re_top_left; /* 0x26c0 */ 360 unsigned int re_top_left; /* 0x26c0 */
363 unsigned int re_misc; 361 unsigned int re_misc;
364} drm_radeon_context_regs_t; 362} drm_radeon_context_regs_t;
365 363
366typedef struct { 364typedef struct {
367 /* Zbias state */ 365 /* Zbias state */
368 unsigned int se_zbias_factor; /* 0x1dac */ 366 unsigned int se_zbias_factor; /* 0x1dac */
369 unsigned int se_zbias_constant; 367 unsigned int se_zbias_constant;
370} drm_radeon_context2_regs_t; 368} drm_radeon_context2_regs_t;
371 369
372
373/* Setup registers for each texture unit 370/* Setup registers for each texture unit
374 */ 371 */
375typedef struct { 372typedef struct {
@@ -387,11 +384,10 @@ typedef struct {
387 unsigned int finish; 384 unsigned int finish;
388 unsigned int prim:8; 385 unsigned int prim:8;
389 unsigned int stateidx:8; 386 unsigned int stateidx:8;
390 unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ 387 unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
391 unsigned int vc_format; /* vertex format */ 388 unsigned int vc_format; /* vertex format */
392} drm_radeon_prim_t; 389} drm_radeon_prim_t;
393 390
394
395typedef struct { 391typedef struct {
396 drm_radeon_context_regs_t context; 392 drm_radeon_context_regs_t context;
397 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; 393 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
@@ -399,7 +395,6 @@ typedef struct {
399 unsigned int dirty; 395 unsigned int dirty;
400} drm_radeon_state_t; 396} drm_radeon_state_t;
401 397
402
403typedef struct { 398typedef struct {
404 /* The channel for communication of state information to the 399 /* The channel for communication of state information to the
405 * kernel on firing a vertex buffer with either of the 400 * kernel on firing a vertex buffer with either of the
@@ -422,16 +417,16 @@ typedef struct {
422 unsigned int last_dispatch; 417 unsigned int last_dispatch;
423 unsigned int last_clear; 418 unsigned int last_clear;
424 419
425 drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1]; 420 drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
421 1];
426 unsigned int tex_age[RADEON_NR_TEX_HEAPS]; 422 unsigned int tex_age[RADEON_NR_TEX_HEAPS];
427 int ctx_owner; 423 int ctx_owner;
428 int pfState; /* number of 3d windows (0,1,2ormore) */ 424 int pfState; /* number of 3d windows (0,1,2ormore) */
429 int pfCurrentPage; /* which buffer is being displayed? */ 425 int pfCurrentPage; /* which buffer is being displayed? */
430 int crtc2_base; /* CRTC2 frame offset */ 426 int crtc2_base; /* CRTC2 frame offset */
431 int tiling_enabled; /* set by drm, read by 2d + 3d clients */ 427 int tiling_enabled; /* set by drm, read by 2d + 3d clients */
432} drm_radeon_sarea_t; 428} drm_radeon_sarea_t;
433 429
434
435/* WARNING: If you change any of these defines, make sure to change the 430/* WARNING: If you change any of these defines, make sure to change the
436 * defines in the Xserver file (xf86drmRadeon.h) 431 * defines in the Xserver file (xf86drmRadeon.h)
437 * 432 *
@@ -441,15 +436,15 @@ typedef struct {
441/* Radeon specific ioctls 436/* Radeon specific ioctls
442 * The device specific ioctl range is 0x40 to 0x79. 437 * The device specific ioctl range is 0x40 to 0x79.
443 */ 438 */
444#define DRM_RADEON_CP_INIT 0x00 439#define DRM_RADEON_CP_INIT 0x00
445#define DRM_RADEON_CP_START 0x01 440#define DRM_RADEON_CP_START 0x01
446#define DRM_RADEON_CP_STOP 0x02 441#define DRM_RADEON_CP_STOP 0x02
447#define DRM_RADEON_CP_RESET 0x03 442#define DRM_RADEON_CP_RESET 0x03
448#define DRM_RADEON_CP_IDLE 0x04 443#define DRM_RADEON_CP_IDLE 0x04
449#define DRM_RADEON_RESET 0x05 444#define DRM_RADEON_RESET 0x05
450#define DRM_RADEON_FULLSCREEN 0x06 445#define DRM_RADEON_FULLSCREEN 0x06
451#define DRM_RADEON_SWAP 0x07 446#define DRM_RADEON_SWAP 0x07
452#define DRM_RADEON_CLEAR 0x08 447#define DRM_RADEON_CLEAR 0x08
453#define DRM_RADEON_VERTEX 0x09 448#define DRM_RADEON_VERTEX 0x09
454#define DRM_RADEON_INDICES 0x0A 449#define DRM_RADEON_INDICES 0x0A
455#define DRM_RADEON_NOT_USED 450#define DRM_RADEON_NOT_USED
@@ -500,7 +495,7 @@ typedef struct {
500 495
501typedef struct drm_radeon_init { 496typedef struct drm_radeon_init {
502 enum { 497 enum {
503 RADEON_INIT_CP = 0x01, 498 RADEON_INIT_CP = 0x01,
504 RADEON_CLEANUP_CP = 0x02, 499 RADEON_CLEANUP_CP = 0x02,
505 RADEON_INIT_R200_CP = 0x03, 500 RADEON_INIT_R200_CP = 0x03,
506 RADEON_INIT_R300_CP = 0x04 501 RADEON_INIT_R300_CP = 0x04
@@ -533,7 +528,7 @@ typedef struct drm_radeon_cp_stop {
533 528
534typedef struct drm_radeon_fullscreen { 529typedef struct drm_radeon_fullscreen {
535 enum { 530 enum {
536 RADEON_INIT_FULLSCREEN = 0x01, 531 RADEON_INIT_FULLSCREEN = 0x01,
537 RADEON_CLEANUP_FULLSCREEN = 0x02 532 RADEON_CLEANUP_FULLSCREEN = 0x02
538 } func; 533 } func;
539} drm_radeon_fullscreen_t; 534} drm_radeon_fullscreen_t;
@@ -554,15 +549,15 @@ typedef struct drm_radeon_clear {
554 unsigned int clear_color; 549 unsigned int clear_color;
555 unsigned int clear_depth; 550 unsigned int clear_depth;
556 unsigned int color_mask; 551 unsigned int color_mask;
557 unsigned int depth_mask; /* misnamed field: should be stencil */ 552 unsigned int depth_mask; /* misnamed field: should be stencil */
558 drm_radeon_clear_rect_t __user *depth_boxes; 553 drm_radeon_clear_rect_t __user *depth_boxes;
559} drm_radeon_clear_t; 554} drm_radeon_clear_t;
560 555
561typedef struct drm_radeon_vertex { 556typedef struct drm_radeon_vertex {
562 int prim; 557 int prim;
563 int idx; /* Index of vertex buffer */ 558 int idx; /* Index of vertex buffer */
564 int count; /* Number of vertices in buffer */ 559 int count; /* Number of vertices in buffer */
565 int discard; /* Client finished with buffer? */ 560 int discard; /* Client finished with buffer? */
566} drm_radeon_vertex_t; 561} drm_radeon_vertex_t;
567 562
568typedef struct drm_radeon_indices { 563typedef struct drm_radeon_indices {
@@ -570,7 +565,7 @@ typedef struct drm_radeon_indices {
570 int idx; 565 int idx;
571 int start; 566 int start;
572 int end; 567 int end;
573 int discard; /* Client finished with buffer? */ 568 int discard; /* Client finished with buffer? */
574} drm_radeon_indices_t; 569} drm_radeon_indices_t;
575 570
576/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices 571/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
@@ -578,8 +573,8 @@ typedef struct drm_radeon_indices {
578 * - supports driver change to emit native primitives 573 * - supports driver change to emit native primitives
579 */ 574 */
580typedef struct drm_radeon_vertex2 { 575typedef struct drm_radeon_vertex2 {
581 int idx; /* Index of vertex buffer */ 576 int idx; /* Index of vertex buffer */
582 int discard; /* Client finished with buffer? */ 577 int discard; /* Client finished with buffer? */
583 int nr_states; 578 int nr_states;
584 drm_radeon_state_t __user *state; 579 drm_radeon_state_t __user *state;
585 int nr_prims; 580 int nr_prims;
@@ -587,10 +582,10 @@ typedef struct drm_radeon_vertex2 {
587} drm_radeon_vertex2_t; 582} drm_radeon_vertex2_t;
588 583
589/* v1.3 - obsoletes drm_radeon_vertex2 584/* v1.3 - obsoletes drm_radeon_vertex2
590 * - allows arbitarily large cliprect list 585 * - allows arbitarily large cliprect list
591 * - allows updating of tcl packet, vector and scalar state 586 * - allows updating of tcl packet, vector and scalar state
592 * - allows memory-efficient description of state updates 587 * - allows memory-efficient description of state updates
593 * - allows state to be emitted without a primitive 588 * - allows state to be emitted without a primitive
594 * (for clears, ctx switches) 589 * (for clears, ctx switches)
595 * - allows more than one dma buffer to be referenced per ioctl 590 * - allows more than one dma buffer to be referenced per ioctl
596 * - supports tcl driver 591 * - supports tcl driver
@@ -604,7 +599,7 @@ typedef struct drm_radeon_cmd_buffer {
604} drm_radeon_cmd_buffer_t; 599} drm_radeon_cmd_buffer_t;
605 600
606typedef struct drm_radeon_tex_image { 601typedef struct drm_radeon_tex_image {
607 unsigned int x, y; /* Blit coordinates */ 602 unsigned int x, y; /* Blit coordinates */
608 unsigned int width, height; 603 unsigned int width, height;
609 const void __user *data; 604 const void __user *data;
610} drm_radeon_tex_image_t; 605} drm_radeon_tex_image_t;
@@ -613,7 +608,7 @@ typedef struct drm_radeon_texture {
613 unsigned int offset; 608 unsigned int offset;
614 int pitch; 609 int pitch;
615 int format; 610 int format;
616 int width; /* Texture image coordinates */ 611 int width; /* Texture image coordinates */
617 int height; 612 int height;
618 drm_radeon_tex_image_t __user *image; 613 drm_radeon_tex_image_t __user *image;
619} drm_radeon_texture_t; 614} drm_radeon_texture_t;
@@ -629,19 +624,18 @@ typedef struct drm_radeon_indirect {
629 int discard; 624 int discard;
630} drm_radeon_indirect_t; 625} drm_radeon_indirect_t;
631 626
632
633/* 1.3: An ioctl to get parameters that aren't available to the 3d 627/* 1.3: An ioctl to get parameters that aren't available to the 3d
634 * client any other way. 628 * client any other way.
635 */ 629 */
636#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ 630#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
637#define RADEON_PARAM_LAST_FRAME 2 631#define RADEON_PARAM_LAST_FRAME 2
638#define RADEON_PARAM_LAST_DISPATCH 3 632#define RADEON_PARAM_LAST_DISPATCH 3
639#define RADEON_PARAM_LAST_CLEAR 4 633#define RADEON_PARAM_LAST_CLEAR 4
640/* Added with DRM version 1.6. */ 634/* Added with DRM version 1.6. */
641#define RADEON_PARAM_IRQ_NR 5 635#define RADEON_PARAM_IRQ_NR 5
642#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ 636#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
643/* Added with DRM version 1.8. */ 637/* Added with DRM version 1.8. */
644#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ 638#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
645#define RADEON_PARAM_STATUS_HANDLE 8 639#define RADEON_PARAM_STATUS_HANDLE 8
646#define RADEON_PARAM_SAREA_HANDLE 9 640#define RADEON_PARAM_SAREA_HANDLE 9
647#define RADEON_PARAM_GART_TEX_HANDLE 10 641#define RADEON_PARAM_GART_TEX_HANDLE 10
@@ -672,10 +666,9 @@ typedef struct drm_radeon_mem_free {
672typedef struct drm_radeon_mem_init_heap { 666typedef struct drm_radeon_mem_init_heap {
673 int region; 667 int region;
674 int size; 668 int size;
675 int start; 669 int start;
676} drm_radeon_mem_init_heap_t; 670} drm_radeon_mem_init_heap_t;
677 671
678
679/* 1.6: Userspace can request & wait on irq's: 672/* 1.6: Userspace can request & wait on irq's:
680 */ 673 */
681typedef struct drm_radeon_irq_emit { 674typedef struct drm_radeon_irq_emit {
@@ -686,19 +679,18 @@ typedef struct drm_radeon_irq_wait {
686 int irq_seq; 679 int irq_seq;
687} drm_radeon_irq_wait_t; 680} drm_radeon_irq_wait_t;
688 681
689
690/* 1.10: Clients tell the DRM where they think the framebuffer is located in 682/* 1.10: Clients tell the DRM where they think the framebuffer is located in
691 * the card's address space, via a new generic ioctl to set parameters 683 * the card's address space, via a new generic ioctl to set parameters
692 */ 684 */
693 685
694typedef struct drm_radeon_setparam { 686typedef struct drm_radeon_setparam {
695 unsigned int param; 687 unsigned int param;
696 int64_t value; 688 int64_t value;
697} drm_radeon_setparam_t; 689} drm_radeon_setparam_t;
698 690
699#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ 691#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */
700#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ 692#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
701#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */ 693#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
702 694
703/* 1.14: Clients can allocate/free a surface 695/* 1.14: Clients can allocate/free a surface
704 */ 696 */
diff --git a/drivers/char/drm/radeon_drv.c b/drivers/char/drm/radeon_drv.c
index e0682f64b400..6c1766120c10 100644
--- a/drivers/char/drm/radeon_drv.c
+++ b/drivers/char/drm/radeon_drv.c
@@ -29,7 +29,6 @@
29 * OTHER DEALINGS IN THE SOFTWARE. 29 * OTHER DEALINGS IN THE SOFTWARE.
30 */ 30 */
31 31
32
33#include <linux/config.h> 32#include <linux/config.h>
34#include "drmP.h" 33#include "drmP.h"
35#include "drm.h" 34#include "drm.h"
@@ -38,30 +37,28 @@
38 37
39#include "drm_pciids.h" 38#include "drm_pciids.h"
40 39
41static int postinit( struct drm_device *dev, unsigned long flags ) 40static int postinit(struct drm_device *dev, unsigned long flags)
42{ 41{
43 DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", 42 DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n",
44 DRIVER_NAME, 43 DRIVER_NAME,
45 DRIVER_MAJOR, 44 DRIVER_MAJOR,
46 DRIVER_MINOR, 45 DRIVER_MINOR,
47 DRIVER_PATCHLEVEL, 46 DRIVER_PATCHLEVEL,
48 DRIVER_DATE, 47 DRIVER_DATE, dev->primary.minor, pci_pretty_name(dev->pdev)
49 dev->primary.minor, 48 );
50 pci_pretty_name(dev->pdev)
51 );
52 return 0; 49 return 0;
53} 50}
54 51
55static int version( drm_version_t *version ) 52static int version(drm_version_t * version)
56{ 53{
57 int len; 54 int len;
58 55
59 version->version_major = DRIVER_MAJOR; 56 version->version_major = DRIVER_MAJOR;
60 version->version_minor = DRIVER_MINOR; 57 version->version_minor = DRIVER_MINOR;
61 version->version_patchlevel = DRIVER_PATCHLEVEL; 58 version->version_patchlevel = DRIVER_PATCHLEVEL;
62 DRM_COPY( version->name, DRIVER_NAME ); 59 DRM_COPY(version->name, DRIVER_NAME);
63 DRM_COPY( version->date, DRIVER_DATE ); 60 DRM_COPY(version->date, DRIVER_DATE);
64 DRM_COPY( version->desc, DRIVER_DESC ); 61 DRM_COPY(version->desc, DRIVER_DESC);
65 return 0; 62 return 0;
66} 63}
67 64
@@ -73,7 +70,10 @@ extern drm_ioctl_desc_t radeon_ioctls[];
73extern int radeon_max_ioctl; 70extern int radeon_max_ioctl;
74 71
75static struct drm_driver driver = { 72static struct drm_driver driver = {
76 .driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL, 73 .driver_features =
74 DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG |
75 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED |
76 DRIVER_IRQ_VBL,
77 .dev_priv_size = sizeof(drm_radeon_buf_priv_t), 77 .dev_priv_size = sizeof(drm_radeon_buf_priv_t),
78 .preinit = radeon_driver_preinit, 78 .preinit = radeon_driver_preinit,
79 .presetup = radeon_presetup, 79 .presetup = radeon_presetup,
@@ -95,21 +95,22 @@ static struct drm_driver driver = {
95 .ioctls = radeon_ioctls, 95 .ioctls = radeon_ioctls,
96 .dma_ioctl = radeon_cp_buffers, 96 .dma_ioctl = radeon_cp_buffers,
97 .fops = { 97 .fops = {
98 .owner = THIS_MODULE, 98 .owner = THIS_MODULE,
99 .open = drm_open, 99 .open = drm_open,
100 .release = drm_release, 100 .release = drm_release,
101 .ioctl = drm_ioctl, 101 .ioctl = drm_ioctl,
102 .mmap = drm_mmap, 102 .mmap = drm_mmap,
103 .poll = drm_poll, 103 .poll = drm_poll,
104 .fasync = drm_fasync, 104 .fasync = drm_fasync,
105#ifdef CONFIG_COMPAT 105#ifdef CONFIG_COMPAT
106 .compat_ioctl = radeon_compat_ioctl, 106 .compat_ioctl = radeon_compat_ioctl,
107#endif 107#endif
108 }, 108 }
109 ,
109 .pci_driver = { 110 .pci_driver = {
110 .name = DRIVER_NAME, 111 .name = DRIVER_NAME,
111 .id_table = pciidlist, 112 .id_table = pciidlist,
112 } 113 }
113}; 114};
114 115
115static int __init radeon_init(void) 116static int __init radeon_init(void)
@@ -126,6 +127,6 @@ static void __exit radeon_exit(void)
126module_init(radeon_init); 127module_init(radeon_init);
127module_exit(radeon_exit); 128module_exit(radeon_exit);
128 129
129MODULE_AUTHOR( DRIVER_AUTHOR ); 130MODULE_AUTHOR(DRIVER_AUTHOR);
130MODULE_DESCRIPTION( DRIVER_DESC ); 131MODULE_DESCRIPTION(DRIVER_DESC);
131MODULE_LICENSE("GPL and additional rights"); 132MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index 9c10141845e7..e36076981d1a 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -68,7 +68,7 @@
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. 68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100. 69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which 70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
71 * clients use to tell the DRM where they think the framebuffer is 71 * clients use to tell the DRM where they think the framebuffer is
72 * located in the card's address space 72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color 73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200 74 * and GL_EXT_blend_[func|equation]_separate on r200
@@ -134,15 +134,15 @@ enum radeon_chip_flags {
134 CHIP_IS_IGP = 0x00020000UL, 134 CHIP_IS_IGP = 0x00020000UL,
135 CHIP_SINGLE_CRTC = 0x00040000UL, 135 CHIP_SINGLE_CRTC = 0x00040000UL,
136 CHIP_IS_AGP = 0x00080000UL, 136 CHIP_IS_AGP = 0x00080000UL,
137 CHIP_HAS_HIERZ = 0x00100000UL, 137 CHIP_HAS_HIERZ = 0x00100000UL,
138 CHIP_IS_PCIE = 0x00200000UL, 138 CHIP_IS_PCIE = 0x00200000UL,
139}; 139};
140 140
141typedef struct drm_radeon_freelist { 141typedef struct drm_radeon_freelist {
142 unsigned int age; 142 unsigned int age;
143 drm_buf_t *buf; 143 drm_buf_t *buf;
144 struct drm_radeon_freelist *next; 144 struct drm_radeon_freelist *next;
145 struct drm_radeon_freelist *prev; 145 struct drm_radeon_freelist *prev;
146} drm_radeon_freelist_t; 146} drm_radeon_freelist_t;
147 147
148typedef struct drm_radeon_ring_buffer { 148typedef struct drm_radeon_ring_buffer {
@@ -204,8 +204,8 @@ typedef struct drm_radeon_private {
204 int cp_mode; 204 int cp_mode;
205 int cp_running; 205 int cp_running;
206 206
207 drm_radeon_freelist_t *head; 207 drm_radeon_freelist_t *head;
208 drm_radeon_freelist_t *tail; 208 drm_radeon_freelist_t *tail;
209 int last_buf; 209 int last_buf;
210 volatile u32 *scratch; 210 volatile u32 *scratch;
211 int writeback_works; 211 int writeback_works;
@@ -246,7 +246,7 @@ typedef struct drm_radeon_private {
246 u32 depth_pitch_offset; 246 u32 depth_pitch_offset;
247 247
248 drm_radeon_depth_clear_t depth_clear; 248 drm_radeon_depth_clear_t depth_clear;
249 249
250 unsigned long fb_offset; 250 unsigned long fb_offset;
251 unsigned long mmio_offset; 251 unsigned long mmio_offset;
252 unsigned long ring_offset; 252 unsigned long ring_offset;
@@ -264,14 +264,14 @@ typedef struct drm_radeon_private {
264 struct mem_block *fb_heap; 264 struct mem_block *fb_heap;
265 265
266 /* SW interrupt */ 266 /* SW interrupt */
267 wait_queue_head_t swi_queue; 267 wait_queue_head_t swi_queue;
268 atomic_t swi_emitted; 268 atomic_t swi_emitted;
269 269
270 struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 270 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
271 struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES]; 271 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
272 272
273 unsigned long pcigart_offset; 273 unsigned long pcigart_offset;
274 drm_ati_pcigart_info gart_info; 274 drm_ati_pcigart_info gart_info;
275 275
276 /* starting from here on, data is preserved accross an open */ 276 /* starting from here on, data is preserved accross an open */
277 uint32_t flags; /* see radeon_chip_flags */ 277 uint32_t flags; /* see radeon_chip_flags */
@@ -282,62 +282,64 @@ typedef struct drm_radeon_buf_priv {
282} drm_radeon_buf_priv_t; 282} drm_radeon_buf_priv_t;
283 283
284 /* radeon_cp.c */ 284 /* radeon_cp.c */
285extern int radeon_cp_init( DRM_IOCTL_ARGS ); 285extern int radeon_cp_init(DRM_IOCTL_ARGS);
286extern int radeon_cp_start( DRM_IOCTL_ARGS ); 286extern int radeon_cp_start(DRM_IOCTL_ARGS);
287extern int radeon_cp_stop( DRM_IOCTL_ARGS ); 287extern int radeon_cp_stop(DRM_IOCTL_ARGS);
288extern int radeon_cp_reset( DRM_IOCTL_ARGS ); 288extern int radeon_cp_reset(DRM_IOCTL_ARGS);
289extern int radeon_cp_idle( DRM_IOCTL_ARGS ); 289extern int radeon_cp_idle(DRM_IOCTL_ARGS);
290extern int radeon_cp_resume( DRM_IOCTL_ARGS ); 290extern int radeon_cp_resume(DRM_IOCTL_ARGS);
291extern int radeon_engine_reset( DRM_IOCTL_ARGS ); 291extern int radeon_engine_reset(DRM_IOCTL_ARGS);
292extern int radeon_fullscreen( DRM_IOCTL_ARGS ); 292extern int radeon_fullscreen(DRM_IOCTL_ARGS);
293extern int radeon_cp_buffers( DRM_IOCTL_ARGS ); 293extern int radeon_cp_buffers(DRM_IOCTL_ARGS);
294 294
295extern void radeon_freelist_reset( drm_device_t *dev ); 295extern void radeon_freelist_reset(drm_device_t * dev);
296extern drm_buf_t *radeon_freelist_get( drm_device_t *dev ); 296extern drm_buf_t *radeon_freelist_get(drm_device_t * dev);
297 297
298extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n ); 298extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
299 299
300extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ); 300extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
301 301
302extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags); 302extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
303extern int radeon_presetup(struct drm_device *dev); 303extern int radeon_presetup(struct drm_device *dev);
304extern int radeon_driver_postcleanup(struct drm_device *dev); 304extern int radeon_driver_postcleanup(struct drm_device *dev);
305 305
306extern int radeon_mem_alloc( DRM_IOCTL_ARGS ); 306extern int radeon_mem_alloc(DRM_IOCTL_ARGS);
307extern int radeon_mem_free( DRM_IOCTL_ARGS ); 307extern int radeon_mem_free(DRM_IOCTL_ARGS);
308extern int radeon_mem_init_heap( DRM_IOCTL_ARGS ); 308extern int radeon_mem_init_heap(DRM_IOCTL_ARGS);
309extern void radeon_mem_takedown( struct mem_block **heap ); 309extern void radeon_mem_takedown(struct mem_block **heap);
310extern void radeon_mem_release( DRMFILE filp, struct mem_block *heap ); 310extern void radeon_mem_release(DRMFILE filp, struct mem_block *heap);
311 311
312 /* radeon_irq.c */ 312 /* radeon_irq.c */
313extern int radeon_irq_emit( DRM_IOCTL_ARGS ); 313extern int radeon_irq_emit(DRM_IOCTL_ARGS);
314extern int radeon_irq_wait( DRM_IOCTL_ARGS ); 314extern int radeon_irq_wait(DRM_IOCTL_ARGS);
315 315
316extern void radeon_do_release(drm_device_t *dev); 316extern void radeon_do_release(drm_device_t * dev);
317extern int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence); 317extern int radeon_driver_vblank_wait(drm_device_t * dev,
318extern irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS ); 318 unsigned int *sequence);
319extern void radeon_driver_irq_preinstall( drm_device_t *dev ); 319extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
320extern void radeon_driver_irq_postinstall( drm_device_t *dev ); 320extern void radeon_driver_irq_preinstall(drm_device_t * dev);
321extern void radeon_driver_irq_uninstall( drm_device_t *dev ); 321extern void radeon_driver_irq_postinstall(drm_device_t * dev);
322extern void radeon_driver_prerelease(drm_device_t *dev, DRMFILE filp); 322extern void radeon_driver_irq_uninstall(drm_device_t * dev);
323extern void radeon_driver_pretakedown(drm_device_t *dev); 323extern void radeon_driver_prerelease(drm_device_t * dev, DRMFILE filp);
324extern int radeon_driver_open_helper(drm_device_t *dev, drm_file_t *filp_priv); 324extern void radeon_driver_pretakedown(drm_device_t * dev);
325extern void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_priv); 325extern int radeon_driver_open_helper(drm_device_t * dev,
326 326 drm_file_t * filp_priv);
327extern int radeon_preinit( struct drm_device *dev, unsigned long flags ); 327extern void radeon_driver_free_filp_priv(drm_device_t * dev,
328extern int radeon_postinit( struct drm_device *dev, unsigned long flags ); 328 drm_file_t * filp_priv);
329extern int radeon_postcleanup( struct drm_device *dev ); 329
330extern int radeon_preinit(struct drm_device *dev, unsigned long flags);
331extern int radeon_postinit(struct drm_device *dev, unsigned long flags);
332extern int radeon_postcleanup(struct drm_device *dev);
330 333
331extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 334extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
332 unsigned long arg); 335 unsigned long arg);
333 336
334
335/* r300_cmdbuf.c */ 337/* r300_cmdbuf.c */
336extern void r300_init_reg_flags(void); 338extern void r300_init_reg_flags(void);
337 339
338extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp, 340extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
339 drm_file_t* filp_priv, 341 drm_file_t * filp_priv,
340 drm_radeon_cmd_buffer_t* cmdbuf); 342 drm_radeon_cmd_buffer_t * cmdbuf);
341 343
342/* Flags for stats.boxes 344/* Flags for stats.boxes
343 */ 345 */
@@ -347,8 +349,6 @@ extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp,
347#define RADEON_BOX_WAIT_IDLE 0x8 349#define RADEON_BOX_WAIT_IDLE 0x8
348#define RADEON_BOX_TEXTURE_LOAD 0x10 350#define RADEON_BOX_TEXTURE_LOAD 0x10
349 351
350
351
352/* Register definitions, register access macros and drmAddMap constants 352/* Register definitions, register access macros and drmAddMap constants
353 * for Radeon kernel driver. 353 * for Radeon kernel driver.
354 */ 354 */
@@ -442,7 +442,6 @@ extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp,
442 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ 442 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
443 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) 443 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
444 444
445
446#define RADEON_GEN_INT_CNTL 0x0040 445#define RADEON_GEN_INT_CNTL 0x0040
447# define RADEON_CRTC_VBLANK_MASK (1 << 0) 446# define RADEON_CRTC_VBLANK_MASK (1 << 0)
448# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) 447# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
@@ -650,7 +649,6 @@ extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp,
650# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 649# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
651# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 650# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
652 651
653
654/* CP registers */ 652/* CP registers */
655#define RADEON_CP_ME_RAM_ADDR 0x07d4 653#define RADEON_CP_ME_RAM_ADDR 0x07d4
656#define RADEON_CP_ME_RAM_RADDR 0x07d8 654#define RADEON_CP_ME_RAM_RADDR 0x07d8
@@ -698,7 +696,7 @@ extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp,
698# define RADEON_CP_NEXT_CHAR 0x00001900 696# define RADEON_CP_NEXT_CHAR 0x00001900
699# define RADEON_CP_PLY_NEXTSCAN 0x00001D00 697# define RADEON_CP_PLY_NEXTSCAN 0x00001D00
700# define RADEON_CP_SET_SCISSORS 0x00001E00 698# define RADEON_CP_SET_SCISSORS 0x00001E00
701 /* GEN_INDX_PRIM is unsupported starting with R300 */ 699 /* GEN_INDX_PRIM is unsupported starting with R300 */
702# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 700# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
703# define RADEON_WAIT_FOR_IDLE 0x00002600 701# define RADEON_WAIT_FOR_IDLE 0x00002600
704# define RADEON_3D_DRAW_VBUF 0x00002800 702# define RADEON_3D_DRAW_VBUF 0x00002800
@@ -782,19 +780,19 @@ extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp,
782#define R200_PP_TXCBLEND_5 0x2f50 780#define R200_PP_TXCBLEND_5 0x2f50
783#define R200_PP_TXCBLEND_6 0x2f60 781#define R200_PP_TXCBLEND_6 0x2f60
784#define R200_PP_TXCBLEND_7 0x2f70 782#define R200_PP_TXCBLEND_7 0x2f70
785#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 783#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
786#define R200_PP_TFACTOR_0 0x2ee0 784#define R200_PP_TFACTOR_0 0x2ee0
787#define R200_SE_VTX_FMT_0 0x2088 785#define R200_SE_VTX_FMT_0 0x2088
788#define R200_SE_VAP_CNTL 0x2080 786#define R200_SE_VAP_CNTL 0x2080
789#define R200_SE_TCL_MATRIX_SEL_0 0x2230 787#define R200_SE_TCL_MATRIX_SEL_0 0x2230
790#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 788#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
791#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 789#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
792#define R200_PP_TXFILTER_5 0x2ca0 790#define R200_PP_TXFILTER_5 0x2ca0
793#define R200_PP_TXFILTER_4 0x2c80 791#define R200_PP_TXFILTER_4 0x2c80
794#define R200_PP_TXFILTER_3 0x2c60 792#define R200_PP_TXFILTER_3 0x2c60
795#define R200_PP_TXFILTER_2 0x2c40 793#define R200_PP_TXFILTER_2 0x2c40
796#define R200_PP_TXFILTER_1 0x2c20 794#define R200_PP_TXFILTER_1 0x2c20
797#define R200_PP_TXFILTER_0 0x2c00 795#define R200_PP_TXFILTER_0 0x2c00
798#define R200_PP_TXOFFSET_5 0x2d78 796#define R200_PP_TXOFFSET_5 0x2d78
799#define R200_PP_TXOFFSET_4 0x2d60 797#define R200_PP_TXOFFSET_4 0x2d60
800#define R200_PP_TXOFFSET_3 0x2d48 798#define R200_PP_TXOFFSET_3 0x2d48
@@ -848,13 +846,13 @@ extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp,
848#define R200_RE_SCISSOR_TL_0 0x1cd8 846#define R200_RE_SCISSOR_TL_0 0x1cd8
849#define R200_RE_SCISSOR_TL_1 0x1ce0 847#define R200_RE_SCISSOR_TL_1 0x1ce0
850#define R200_RE_SCISSOR_TL_2 0x1ce8 848#define R200_RE_SCISSOR_TL_2 0x1ce8
851#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 849#define R200_RB3D_DEPTHXY_OFFSET 0x1d60
852#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 850#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
853#define R200_SE_VTX_STATE_CNTL 0x2180 851#define R200_SE_VTX_STATE_CNTL 0x2180
854#define R200_RE_POINTSIZE 0x2648 852#define R200_RE_POINTSIZE 0x2648
855#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 853#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
856 854
857#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 855#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
858#define RADEON_PP_TEX_SIZE_1 0x1d0c 856#define RADEON_PP_TEX_SIZE_1 0x1d0c
859#define RADEON_PP_TEX_SIZE_2 0x1d14 857#define RADEON_PP_TEX_SIZE_2 0x1d14
860 858
@@ -875,7 +873,7 @@ extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp,
875#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b 873#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
876#define R200_3D_DRAW_IMMD_2 0xC0003500 874#define R200_3D_DRAW_IMMD_2 0xC0003500
877#define R200_SE_VTX_FMT_1 0x208c 875#define R200_SE_VTX_FMT_1 0x208c
878#define R200_RE_CNTL 0x1c50 876#define R200_RE_CNTL 0x1c50
879 877
880#define R200_RB3D_BLENDCOLOR 0x3218 878#define R200_RB3D_BLENDCOLOR 0x3218
881 879
@@ -884,7 +882,7 @@ extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp,
884#define R200_PP_TRI_PERF 0x2cf8 882#define R200_PP_TRI_PERF 0x2cf8
885 883
886#define R200_PP_AFS_0 0x2f80 884#define R200_PP_AFS_0 0x2f80
887#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ 885#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
888 886
889/* Constants */ 887/* Constants */
890#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 888#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
@@ -932,7 +930,6 @@ do { \
932#define CP_PACKET3( pkt, n ) \ 930#define CP_PACKET3( pkt, n ) \
933 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 931 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
934 932
935
936/* ================================================================ 933/* ================================================================
937 * Engine control helper macros 934 * Engine control helper macros
938 */ 935 */
@@ -981,12 +978,11 @@ do { \
981 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \ 978 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
982} while (0) 979} while (0)
983 980
984
985/* ================================================================ 981/* ================================================================
986 * Misc helper macros 982 * Misc helper macros
987 */ 983 */
988 984
989/* Perfbox functionality only. 985/* Perfbox functionality only.
990 */ 986 */
991#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 987#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
992do { \ 988do { \
@@ -1023,7 +1019,6 @@ do { \
1023 OUT_RING( age ); \ 1019 OUT_RING( age ); \
1024} while (0) 1020} while (0)
1025 1021
1026
1027/* ================================================================ 1022/* ================================================================
1028 * Ring control 1023 * Ring control
1029 */ 1024 */
@@ -1084,7 +1079,6 @@ do { \
1084 OUT_RING( val ); \ 1079 OUT_RING( val ); \
1085} while (0) 1080} while (0)
1086 1081
1087
1088#define OUT_RING_TABLE( tab, sz ) do { \ 1082#define OUT_RING_TABLE( tab, sz ) do { \
1089 int _size = (sz); \ 1083 int _size = (sz); \
1090 int *_tab = (int *)(tab); \ 1084 int *_tab = (int *)(tab); \
@@ -1109,5 +1103,4 @@ do { \
1109 write &= mask; \ 1103 write &= mask; \
1110} while (0) 1104} while (0)
1111 1105
1112 1106#endif /* __RADEON_DRV_H__ */
1113#endif /* __RADEON_DRV_H__ */
diff --git a/drivers/char/drm/radeon_ioc32.c b/drivers/char/drm/radeon_ioc32.c
index bfe612215fb3..fef4a2b84c1e 100644
--- a/drivers/char/drm/radeon_ioc32.c
+++ b/drivers/char/drm/radeon_ioc32.c
@@ -94,7 +94,7 @@ static int compat_radeon_cp_init(struct file *file, unsigned int cmd,
94 return -EFAULT; 94 return -EFAULT;
95 95
96 return drm_ioctl(file->f_dentry->d_inode, file, 96 return drm_ioctl(file->f_dentry->d_inode, file,
97 DRM_IOCTL_RADEON_CP_INIT, (unsigned long) init); 97 DRM_IOCTL_RADEON_CP_INIT, (unsigned long)init);
98} 98}
99 99
100typedef struct drm_radeon_clear32 { 100typedef struct drm_radeon_clear32 {
@@ -102,8 +102,8 @@ typedef struct drm_radeon_clear32 {
102 unsigned int clear_color; 102 unsigned int clear_color;
103 unsigned int clear_depth; 103 unsigned int clear_depth;
104 unsigned int color_mask; 104 unsigned int color_mask;
105 unsigned int depth_mask; /* misnamed field: should be stencil */ 105 unsigned int depth_mask; /* misnamed field: should be stencil */
106 u32 depth_boxes; 106 u32 depth_boxes;
107} drm_radeon_clear32_t; 107} drm_radeon_clear32_t;
108 108
109static int compat_radeon_cp_clear(struct file *file, unsigned int cmd, 109static int compat_radeon_cp_clear(struct file *file, unsigned int cmd,
@@ -127,7 +127,7 @@ static int compat_radeon_cp_clear(struct file *file, unsigned int cmd,
127 return -EFAULT; 127 return -EFAULT;
128 128
129 return drm_ioctl(file->f_dentry->d_inode, file, 129 return drm_ioctl(file->f_dentry->d_inode, file,
130 DRM_IOCTL_RADEON_CLEAR, (unsigned long) clr); 130 DRM_IOCTL_RADEON_CLEAR, (unsigned long)clr);
131} 131}
132 132
133typedef struct drm_radeon_stipple32 { 133typedef struct drm_radeon_stipple32 {
@@ -137,7 +137,7 @@ typedef struct drm_radeon_stipple32 {
137static int compat_radeon_cp_stipple(struct file *file, unsigned int cmd, 137static int compat_radeon_cp_stipple(struct file *file, unsigned int cmd,
138 unsigned long arg) 138 unsigned long arg)
139{ 139{
140 drm_radeon_stipple32_t __user *argp = (void __user *) arg; 140 drm_radeon_stipple32_t __user *argp = (void __user *)arg;
141 drm_radeon_stipple_t __user *request; 141 drm_radeon_stipple_t __user *request;
142 u32 mask; 142 u32 mask;
143 143
@@ -146,16 +146,16 @@ static int compat_radeon_cp_stipple(struct file *file, unsigned int cmd,
146 146
147 request = compat_alloc_user_space(sizeof(*request)); 147 request = compat_alloc_user_space(sizeof(*request));
148 if (!access_ok(VERIFY_WRITE, request, sizeof(*request)) 148 if (!access_ok(VERIFY_WRITE, request, sizeof(*request))
149 || __put_user((unsigned int __user *)(unsigned long) mask, 149 || __put_user((unsigned int __user *)(unsigned long)mask,
150 &request->mask)) 150 &request->mask))
151 return -EFAULT; 151 return -EFAULT;
152 152
153 return drm_ioctl(file->f_dentry->d_inode, file, 153 return drm_ioctl(file->f_dentry->d_inode, file,
154 DRM_IOCTL_RADEON_STIPPLE, (unsigned long) request); 154 DRM_IOCTL_RADEON_STIPPLE, (unsigned long)request);
155} 155}
156 156
157typedef struct drm_radeon_tex_image32 { 157typedef struct drm_radeon_tex_image32 {
158 unsigned int x, y; /* Blit coordinates */ 158 unsigned int x, y; /* Blit coordinates */
159 unsigned int width, height; 159 unsigned int width, height;
160 u32 data; 160 u32 data;
161} drm_radeon_tex_image32_t; 161} drm_radeon_tex_image32_t;
@@ -164,7 +164,7 @@ typedef struct drm_radeon_texture32 {
164 unsigned int offset; 164 unsigned int offset;
165 int pitch; 165 int pitch;
166 int format; 166 int format;
167 int width; /* Texture image coordinates */ 167 int width; /* Texture image coordinates */
168 int height; 168 int height;
169 u32 image; 169 u32 image;
170} drm_radeon_texture32_t; 170} drm_radeon_texture32_t;
@@ -177,7 +177,7 @@ static int compat_radeon_cp_texture(struct file *file, unsigned int cmd,
177 drm_radeon_tex_image32_t img32; 177 drm_radeon_tex_image32_t img32;
178 drm_radeon_tex_image_t __user *image; 178 drm_radeon_tex_image_t __user *image;
179 179
180 if (copy_from_user(&req32, (void __user *) arg, sizeof(req32))) 180 if (copy_from_user(&req32, (void __user *)arg, sizeof(req32)))
181 return -EFAULT; 181 return -EFAULT;
182 if (req32.image == 0) 182 if (req32.image == 0)
183 return -EINVAL; 183 return -EINVAL;
@@ -206,12 +206,12 @@ static int compat_radeon_cp_texture(struct file *file, unsigned int cmd,
206 return -EFAULT; 206 return -EFAULT;
207 207
208 return drm_ioctl(file->f_dentry->d_inode, file, 208 return drm_ioctl(file->f_dentry->d_inode, file,
209 DRM_IOCTL_RADEON_TEXTURE, (unsigned long) request); 209 DRM_IOCTL_RADEON_TEXTURE, (unsigned long)request);
210} 210}
211 211
212typedef struct drm_radeon_vertex2_32 { 212typedef struct drm_radeon_vertex2_32 {
213 int idx; /* Index of vertex buffer */ 213 int idx; /* Index of vertex buffer */
214 int discard; /* Client finished with buffer? */ 214 int discard; /* Client finished with buffer? */
215 int nr_states; 215 int nr_states;
216 u32 state; 216 u32 state;
217 int nr_prims; 217 int nr_prims;
@@ -224,7 +224,7 @@ static int compat_radeon_cp_vertex2(struct file *file, unsigned int cmd,
224 drm_radeon_vertex2_32_t req32; 224 drm_radeon_vertex2_32_t req32;
225 drm_radeon_vertex2_t __user *request; 225 drm_radeon_vertex2_t __user *request;
226 226
227 if (copy_from_user(&req32, (void __user *) arg, sizeof(req32))) 227 if (copy_from_user(&req32, (void __user *)arg, sizeof(req32)))
228 return -EFAULT; 228 return -EFAULT;
229 229
230 request = compat_alloc_user_space(sizeof(*request)); 230 request = compat_alloc_user_space(sizeof(*request));
@@ -240,7 +240,7 @@ static int compat_radeon_cp_vertex2(struct file *file, unsigned int cmd,
240 return -EFAULT; 240 return -EFAULT;
241 241
242 return drm_ioctl(file->f_dentry->d_inode, file, 242 return drm_ioctl(file->f_dentry->d_inode, file,
243 DRM_IOCTL_RADEON_VERTEX2, (unsigned long) request); 243 DRM_IOCTL_RADEON_VERTEX2, (unsigned long)request);
244} 244}
245 245
246typedef struct drm_radeon_cmd_buffer32 { 246typedef struct drm_radeon_cmd_buffer32 {
@@ -256,7 +256,7 @@ static int compat_radeon_cp_cmdbuf(struct file *file, unsigned int cmd,
256 drm_radeon_cmd_buffer32_t req32; 256 drm_radeon_cmd_buffer32_t req32;
257 drm_radeon_cmd_buffer_t __user *request; 257 drm_radeon_cmd_buffer_t __user *request;
258 258
259 if (copy_from_user(&req32, (void __user *) arg, sizeof(req32))) 259 if (copy_from_user(&req32, (void __user *)arg, sizeof(req32)))
260 return -EFAULT; 260 return -EFAULT;
261 261
262 request = compat_alloc_user_space(sizeof(*request)); 262 request = compat_alloc_user_space(sizeof(*request));
@@ -270,7 +270,7 @@ static int compat_radeon_cp_cmdbuf(struct file *file, unsigned int cmd,
270 return -EFAULT; 270 return -EFAULT;
271 271
272 return drm_ioctl(file->f_dentry->d_inode, file, 272 return drm_ioctl(file->f_dentry->d_inode, file,
273 DRM_IOCTL_RADEON_CMDBUF, (unsigned long) request); 273 DRM_IOCTL_RADEON_CMDBUF, (unsigned long)request);
274} 274}
275 275
276typedef struct drm_radeon_getparam32 { 276typedef struct drm_radeon_getparam32 {
@@ -284,7 +284,7 @@ static int compat_radeon_cp_getparam(struct file *file, unsigned int cmd,
284 drm_radeon_getparam32_t req32; 284 drm_radeon_getparam32_t req32;
285 drm_radeon_getparam_t __user *request; 285 drm_radeon_getparam_t __user *request;
286 286
287 if (copy_from_user(&req32, (void __user *) arg, sizeof(req32))) 287 if (copy_from_user(&req32, (void __user *)arg, sizeof(req32)))
288 return -EFAULT; 288 return -EFAULT;
289 289
290 request = compat_alloc_user_space(sizeof(*request)); 290 request = compat_alloc_user_space(sizeof(*request));
@@ -295,7 +295,7 @@ static int compat_radeon_cp_getparam(struct file *file, unsigned int cmd,
295 return -EFAULT; 295 return -EFAULT;
296 296
297 return drm_ioctl(file->f_dentry->d_inode, file, 297 return drm_ioctl(file->f_dentry->d_inode, file,
298 DRM_IOCTL_RADEON_GETPARAM, (unsigned long) request); 298 DRM_IOCTL_RADEON_GETPARAM, (unsigned long)request);
299} 299}
300 300
301typedef struct drm_radeon_mem_alloc32 { 301typedef struct drm_radeon_mem_alloc32 {
@@ -311,7 +311,7 @@ static int compat_radeon_mem_alloc(struct file *file, unsigned int cmd,
311 drm_radeon_mem_alloc32_t req32; 311 drm_radeon_mem_alloc32_t req32;
312 drm_radeon_mem_alloc_t __user *request; 312 drm_radeon_mem_alloc_t __user *request;
313 313
314 if (copy_from_user(&req32, (void __user *) arg, sizeof(req32))) 314 if (copy_from_user(&req32, (void __user *)arg, sizeof(req32)))
315 return -EFAULT; 315 return -EFAULT;
316 316
317 request = compat_alloc_user_space(sizeof(*request)); 317 request = compat_alloc_user_space(sizeof(*request));
@@ -324,7 +324,7 @@ static int compat_radeon_mem_alloc(struct file *file, unsigned int cmd,
324 return -EFAULT; 324 return -EFAULT;
325 325
326 return drm_ioctl(file->f_dentry->d_inode, file, 326 return drm_ioctl(file->f_dentry->d_inode, file,
327 DRM_IOCTL_RADEON_ALLOC, (unsigned long) request); 327 DRM_IOCTL_RADEON_ALLOC, (unsigned long)request);
328} 328}
329 329
330typedef struct drm_radeon_irq_emit32 { 330typedef struct drm_radeon_irq_emit32 {
@@ -337,7 +337,7 @@ static int compat_radeon_irq_emit(struct file *file, unsigned int cmd,
337 drm_radeon_irq_emit32_t req32; 337 drm_radeon_irq_emit32_t req32;
338 drm_radeon_irq_emit_t __user *request; 338 drm_radeon_irq_emit_t __user *request;
339 339
340 if (copy_from_user(&req32, (void __user *) arg, sizeof(req32))) 340 if (copy_from_user(&req32, (void __user *)arg, sizeof(req32)))
341 return -EFAULT; 341 return -EFAULT;
342 342
343 request = compat_alloc_user_space(sizeof(*request)); 343 request = compat_alloc_user_space(sizeof(*request));
@@ -347,7 +347,7 @@ static int compat_radeon_irq_emit(struct file *file, unsigned int cmd,
347 return -EFAULT; 347 return -EFAULT;
348 348
349 return drm_ioctl(file->f_dentry->d_inode, file, 349 return drm_ioctl(file->f_dentry->d_inode, file,
350 DRM_IOCTL_RADEON_IRQ_EMIT, (unsigned long) request); 350 DRM_IOCTL_RADEON_IRQ_EMIT, (unsigned long)request);
351} 351}
352 352
353drm_ioctl_compat_t *radeon_compat_ioctls[] = { 353drm_ioctl_compat_t *radeon_compat_ioctls[] = {
@@ -371,8 +371,7 @@ drm_ioctl_compat_t *radeon_compat_ioctls[] = {
371 * \param arg user argument. 371 * \param arg user argument.
372 * \return zero on success or negative number on failure. 372 * \return zero on success or negative number on failure.
373 */ 373 */
374long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 374long radeon_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
375 unsigned long arg)
376{ 375{
377 unsigned int nr = DRM_IOCTL_NR(cmd); 376 unsigned int nr = DRM_IOCTL_NR(cmd);
378 drm_ioctl_compat_t *fn = NULL; 377 drm_ioctl_compat_t *fn = NULL;
@@ -386,7 +385,7 @@ long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
386 385
387 lock_kernel(); /* XXX for now */ 386 lock_kernel(); /* XXX for now */
388 if (fn != NULL) 387 if (fn != NULL)
389 ret = (*fn)(filp, cmd, arg); 388 ret = (*fn) (filp, cmd, arg);
390 else 389 else
391 ret = drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg); 390 ret = drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg);
392 unlock_kernel(); 391 unlock_kernel();
diff --git a/drivers/char/drm/radeon_irq.c b/drivers/char/drm/radeon_irq.c
index 40474a65f56d..d60519de887b 100644
--- a/drivers/char/drm/radeon_irq.c
+++ b/drivers/char/drm/radeon_irq.c
@@ -1,7 +1,7 @@
1/* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- 1/* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*-
2 * 2 *
3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 * 4 *
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the 5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license. 6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved. 7 * This notice must be preserved.
@@ -35,7 +35,8 @@
35#include "radeon_drm.h" 35#include "radeon_drm.h"
36#include "radeon_drv.h" 36#include "radeon_drv.h"
37 37
38static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u32 mask) 38static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv,
39 u32 mask)
39{ 40{
40 u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS) & mask; 41 u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS) & mask;
41 if (irqs) 42 if (irqs)
@@ -61,37 +62,37 @@ static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u3
61 * tied to dma at all, this is just a hangover from dri prehistory. 62 * tied to dma at all, this is just a hangover from dri prehistory.
62 */ 63 */
63 64
64irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS ) 65irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
65{ 66{
66 drm_device_t *dev = (drm_device_t *) arg; 67 drm_device_t *dev = (drm_device_t *) arg;
67 drm_radeon_private_t *dev_priv = 68 drm_radeon_private_t *dev_priv =
68 (drm_radeon_private_t *)dev->dev_private; 69 (drm_radeon_private_t *) dev->dev_private;
69 u32 stat; 70 u32 stat;
70 71
71 /* Only consider the bits we're interested in - others could be used 72 /* Only consider the bits we're interested in - others could be used
72 * outside the DRM 73 * outside the DRM
73 */ 74 */
74 stat = radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK | 75 stat = radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
75 RADEON_CRTC_VBLANK_STAT)); 76 RADEON_CRTC_VBLANK_STAT));
76 if (!stat) 77 if (!stat)
77 return IRQ_NONE; 78 return IRQ_NONE;
78 79
79 /* SW interrupt */ 80 /* SW interrupt */
80 if (stat & RADEON_SW_INT_TEST) { 81 if (stat & RADEON_SW_INT_TEST) {
81 DRM_WAKEUP( &dev_priv->swi_queue ); 82 DRM_WAKEUP(&dev_priv->swi_queue);
82 } 83 }
83 84
84 /* VBLANK interrupt */ 85 /* VBLANK interrupt */
85 if (stat & RADEON_CRTC_VBLANK_STAT) { 86 if (stat & RADEON_CRTC_VBLANK_STAT) {
86 atomic_inc(&dev->vbl_received); 87 atomic_inc(&dev->vbl_received);
87 DRM_WAKEUP(&dev->vbl_queue); 88 DRM_WAKEUP(&dev->vbl_queue);
88 drm_vbl_send_signals( dev ); 89 drm_vbl_send_signals(dev);
89 } 90 }
90 91
91 return IRQ_HANDLED; 92 return IRQ_HANDLED;
92} 93}
93 94
94static int radeon_emit_irq(drm_device_t *dev) 95static int radeon_emit_irq(drm_device_t * dev)
95{ 96{
96 drm_radeon_private_t *dev_priv = dev->dev_private; 97 drm_radeon_private_t *dev_priv = dev->dev_private;
97 unsigned int ret; 98 unsigned int ret;
@@ -100,42 +101,41 @@ static int radeon_emit_irq(drm_device_t *dev)
100 atomic_inc(&dev_priv->swi_emitted); 101 atomic_inc(&dev_priv->swi_emitted);
101 ret = atomic_read(&dev_priv->swi_emitted); 102 ret = atomic_read(&dev_priv->swi_emitted);
102 103
103 BEGIN_RING( 4 ); 104 BEGIN_RING(4);
104 OUT_RING_REG( RADEON_LAST_SWI_REG, ret ); 105 OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
105 OUT_RING_REG( RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE ); 106 OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
106 ADVANCE_RING(); 107 ADVANCE_RING();
107 COMMIT_RING(); 108 COMMIT_RING();
108 109
109 return ret; 110 return ret;
110} 111}
111 112
112 113static int radeon_wait_irq(drm_device_t * dev, int swi_nr)
113static int radeon_wait_irq(drm_device_t *dev, int swi_nr)
114{ 114{
115 drm_radeon_private_t *dev_priv = 115 drm_radeon_private_t *dev_priv =
116 (drm_radeon_private_t *)dev->dev_private; 116 (drm_radeon_private_t *) dev->dev_private;
117 int ret = 0; 117 int ret = 0;
118 118
119 if (RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr) 119 if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
120 return 0; 120 return 0;
121 121
122 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 122 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
123 123
124 DRM_WAIT_ON( ret, dev_priv->swi_queue, 3 * DRM_HZ, 124 DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
125 RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr ); 125 RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
126 126
127 return ret; 127 return ret;
128} 128}
129 129
130int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence) 130int radeon_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence)
131{ 131{
132 drm_radeon_private_t *dev_priv = 132 drm_radeon_private_t *dev_priv =
133 (drm_radeon_private_t *)dev->dev_private; 133 (drm_radeon_private_t *) dev->dev_private;
134 unsigned int cur_vblank; 134 unsigned int cur_vblank;
135 int ret = 0; 135 int ret = 0;
136 136
137 if ( !dev_priv ) { 137 if (!dev_priv) {
138 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 138 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
139 return DRM_ERR(EINVAL); 139 return DRM_ERR(EINVAL);
140 } 140 }
141 141
@@ -145,101 +145,100 @@ int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence)
145 145
146 /* Assume that the user has missed the current sequence number 146 /* Assume that the user has missed the current sequence number
147 * by about a day rather than she wants to wait for years 147 * by about a day rather than she wants to wait for years
148 * using vertical blanks... 148 * using vertical blanks...
149 */ 149 */
150 DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, 150 DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
151 ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) ) 151 (((cur_vblank = atomic_read(&dev->vbl_received))
152 - *sequence ) <= (1<<23) ) ); 152 - *sequence) <= (1 << 23)));
153 153
154 *sequence = cur_vblank; 154 *sequence = cur_vblank;
155 155
156 return ret; 156 return ret;
157} 157}
158 158
159
160/* Needs the lock as it touches the ring. 159/* Needs the lock as it touches the ring.
161 */ 160 */
162int radeon_irq_emit( DRM_IOCTL_ARGS ) 161int radeon_irq_emit(DRM_IOCTL_ARGS)
163{ 162{
164 DRM_DEVICE; 163 DRM_DEVICE;
165 drm_radeon_private_t *dev_priv = dev->dev_private; 164 drm_radeon_private_t *dev_priv = dev->dev_private;
166 drm_radeon_irq_emit_t emit; 165 drm_radeon_irq_emit_t emit;
167 int result; 166 int result;
168 167
169 LOCK_TEST_WITH_RETURN( dev, filp ); 168 LOCK_TEST_WITH_RETURN(dev, filp);
170 169
171 if ( !dev_priv ) { 170 if (!dev_priv) {
172 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 171 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
173 return DRM_ERR(EINVAL); 172 return DRM_ERR(EINVAL);
174 } 173 }
175 174
176 DRM_COPY_FROM_USER_IOCTL( emit, (drm_radeon_irq_emit_t __user *)data, 175 DRM_COPY_FROM_USER_IOCTL(emit, (drm_radeon_irq_emit_t __user *) data,
177 sizeof(emit) ); 176 sizeof(emit));
178 177
179 result = radeon_emit_irq( dev ); 178 result = radeon_emit_irq(dev);
180 179
181 if ( DRM_COPY_TO_USER( emit.irq_seq, &result, sizeof(int) ) ) { 180 if (DRM_COPY_TO_USER(emit.irq_seq, &result, sizeof(int))) {
182 DRM_ERROR( "copy_to_user\n" ); 181 DRM_ERROR("copy_to_user\n");
183 return DRM_ERR(EFAULT); 182 return DRM_ERR(EFAULT);
184 } 183 }
185 184
186 return 0; 185 return 0;
187} 186}
188 187
189
190/* Doesn't need the hardware lock. 188/* Doesn't need the hardware lock.
191 */ 189 */
192int radeon_irq_wait( DRM_IOCTL_ARGS ) 190int radeon_irq_wait(DRM_IOCTL_ARGS)
193{ 191{
194 DRM_DEVICE; 192 DRM_DEVICE;
195 drm_radeon_private_t *dev_priv = dev->dev_private; 193 drm_radeon_private_t *dev_priv = dev->dev_private;
196 drm_radeon_irq_wait_t irqwait; 194 drm_radeon_irq_wait_t irqwait;
197 195
198 if ( !dev_priv ) { 196 if (!dev_priv) {
199 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 197 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
200 return DRM_ERR(EINVAL); 198 return DRM_ERR(EINVAL);
201 } 199 }
202 200
203 DRM_COPY_FROM_USER_IOCTL( irqwait, (drm_radeon_irq_wait_t __user*)data, 201 DRM_COPY_FROM_USER_IOCTL(irqwait, (drm_radeon_irq_wait_t __user *) data,
204 sizeof(irqwait) ); 202 sizeof(irqwait));
205 203
206 return radeon_wait_irq( dev, irqwait.irq_seq ); 204 return radeon_wait_irq(dev, irqwait.irq_seq);
207} 205}
208 206
209
210/* drm_dma.h hooks 207/* drm_dma.h hooks
211*/ 208*/
212void radeon_driver_irq_preinstall( drm_device_t *dev ) { 209void radeon_driver_irq_preinstall(drm_device_t * dev)
210{
213 drm_radeon_private_t *dev_priv = 211 drm_radeon_private_t *dev_priv =
214 (drm_radeon_private_t *)dev->dev_private; 212 (drm_radeon_private_t *) dev->dev_private;
215 213
216 /* Disable *all* interrupts */ 214 /* Disable *all* interrupts */
217 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 ); 215 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
218 216
219 /* Clear bits if they're already high */ 217 /* Clear bits if they're already high */
220 radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK | 218 radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
221 RADEON_CRTC_VBLANK_STAT)); 219 RADEON_CRTC_VBLANK_STAT));
222} 220}
223 221
224void radeon_driver_irq_postinstall( drm_device_t *dev ) { 222void radeon_driver_irq_postinstall(drm_device_t * dev)
223{
225 drm_radeon_private_t *dev_priv = 224 drm_radeon_private_t *dev_priv =
226 (drm_radeon_private_t *)dev->dev_private; 225 (drm_radeon_private_t *) dev->dev_private;
227 226
228 atomic_set(&dev_priv->swi_emitted, 0); 227 atomic_set(&dev_priv->swi_emitted, 0);
229 DRM_INIT_WAITQUEUE( &dev_priv->swi_queue ); 228 DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
230 229
231 /* Turn on SW and VBL ints */ 230 /* Turn on SW and VBL ints */
232 RADEON_WRITE( RADEON_GEN_INT_CNTL, 231 RADEON_WRITE(RADEON_GEN_INT_CNTL,
233 RADEON_CRTC_VBLANK_MASK | 232 RADEON_CRTC_VBLANK_MASK | RADEON_SW_INT_ENABLE);
234 RADEON_SW_INT_ENABLE );
235} 233}
236 234
237void radeon_driver_irq_uninstall( drm_device_t *dev ) { 235void radeon_driver_irq_uninstall(drm_device_t * dev)
236{
238 drm_radeon_private_t *dev_priv = 237 drm_radeon_private_t *dev_priv =
239 (drm_radeon_private_t *)dev->dev_private; 238 (drm_radeon_private_t *) dev->dev_private;
240 if (!dev_priv) 239 if (!dev_priv)
241 return; 240 return;
242 241
243 /* Disable *all* interrupts */ 242 /* Disable *all* interrupts */
244 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 ); 243 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
245} 244}
diff --git a/drivers/char/drm/radeon_mem.c b/drivers/char/drm/radeon_mem.c
index 134f894e6e4b..030a6fad0d86 100644
--- a/drivers/char/drm/radeon_mem.c
+++ b/drivers/char/drm/radeon_mem.c
@@ -1,7 +1,7 @@
1/* radeon_mem.c -- Simple GART/fb memory manager for radeon -*- linux-c -*- 1/* radeon_mem.c -- Simple GART/fb memory manager for radeon -*- linux-c -*-
2 * 2 *
3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 * 4 *
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the 5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license. 6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved. 7 * This notice must be preserved.
@@ -35,16 +35,17 @@
35#include "radeon_drv.h" 35#include "radeon_drv.h"
36 36
37/* Very simple allocator for GART memory, working on a static range 37/* Very simple allocator for GART memory, working on a static range
38 * already mapped into each client's address space. 38 * already mapped into each client's address space.
39 */ 39 */
40 40
41static struct mem_block *split_block(struct mem_block *p, int start, int size, 41static struct mem_block *split_block(struct mem_block *p, int start, int size,
42 DRMFILE filp ) 42 DRMFILE filp)
43{ 43{
44 /* Maybe cut off the start of an existing block */ 44 /* Maybe cut off the start of an existing block */
45 if (start > p->start) { 45 if (start > p->start) {
46 struct mem_block *newblock = drm_alloc(sizeof(*newblock), DRM_MEM_BUFS ); 46 struct mem_block *newblock =
47 if (!newblock) 47 drm_alloc(sizeof(*newblock), DRM_MEM_BUFS);
48 if (!newblock)
48 goto out; 49 goto out;
49 newblock->start = start; 50 newblock->start = start;
50 newblock->size = p->size - (start - p->start); 51 newblock->size = p->size - (start - p->start);
@@ -56,10 +57,11 @@ static struct mem_block *split_block(struct mem_block *p, int start, int size,
56 p->size -= newblock->size; 57 p->size -= newblock->size;
57 p = newblock; 58 p = newblock;
58 } 59 }
59 60
60 /* Maybe cut off the end of an existing block */ 61 /* Maybe cut off the end of an existing block */
61 if (size < p->size) { 62 if (size < p->size) {
62 struct mem_block *newblock = drm_alloc(sizeof(*newblock), DRM_MEM_BUFS ); 63 struct mem_block *newblock =
64 drm_alloc(sizeof(*newblock), DRM_MEM_BUFS);
63 if (!newblock) 65 if (!newblock)
64 goto out; 66 goto out;
65 newblock->start = start + size; 67 newblock->start = start + size;
@@ -72,40 +74,39 @@ static struct mem_block *split_block(struct mem_block *p, int start, int size,
72 p->size = size; 74 p->size = size;
73 } 75 }
74 76
75 out: 77 out:
76 /* Our block is in the middle */ 78 /* Our block is in the middle */
77 p->filp = filp; 79 p->filp = filp;
78 return p; 80 return p;
79} 81}
80 82
81static struct mem_block *alloc_block( struct mem_block *heap, int size, 83static struct mem_block *alloc_block(struct mem_block *heap, int size,
82 int align2, DRMFILE filp ) 84 int align2, DRMFILE filp)
83{ 85{
84 struct mem_block *p; 86 struct mem_block *p;
85 int mask = (1 << align2)-1; 87 int mask = (1 << align2) - 1;
86 88
87 list_for_each(p, heap) { 89 list_for_each(p, heap) {
88 int start = (p->start + mask) & ~mask; 90 int start = (p->start + mask) & ~mask;
89 if (p->filp == 0 && start + size <= p->start + p->size) 91 if (p->filp == 0 && start + size <= p->start + p->size)
90 return split_block( p, start, size, filp ); 92 return split_block(p, start, size, filp);
91 } 93 }
92 94
93 return NULL; 95 return NULL;
94} 96}
95 97
96static struct mem_block *find_block( struct mem_block *heap, int start ) 98static struct mem_block *find_block(struct mem_block *heap, int start)
97{ 99{
98 struct mem_block *p; 100 struct mem_block *p;
99 101
100 list_for_each(p, heap) 102 list_for_each(p, heap)
101 if (p->start == start) 103 if (p->start == start)
102 return p; 104 return p;
103 105
104 return NULL; 106 return NULL;
105} 107}
106 108
107 109static void free_block(struct mem_block *p)
108static void free_block( struct mem_block *p )
109{ 110{
110 p->filp = NULL; 111 p->filp = NULL;
111 112
@@ -117,7 +118,7 @@ static void free_block( struct mem_block *p )
117 p->size += q->size; 118 p->size += q->size;
118 p->next = q->next; 119 p->next = q->next;
119 p->next->prev = p; 120 p->next->prev = p;
120 drm_free(q, sizeof(*q), DRM_MEM_BUFS ); 121 drm_free(q, sizeof(*q), DRM_MEM_BUFS);
121 } 122 }
122 123
123 if (p->prev->filp == 0) { 124 if (p->prev->filp == 0) {
@@ -125,7 +126,7 @@ static void free_block( struct mem_block *p )
125 q->size += p->size; 126 q->size += p->size;
126 q->next = p->next; 127 q->next = p->next;
127 q->next->prev = q; 128 q->next->prev = q;
128 drm_free(p, sizeof(*q), DRM_MEM_BUFS ); 129 drm_free(p, sizeof(*q), DRM_MEM_BUFS);
129 } 130 }
130} 131}
131 132
@@ -133,14 +134,14 @@ static void free_block( struct mem_block *p )
133 */ 134 */
134static int init_heap(struct mem_block **heap, int start, int size) 135static int init_heap(struct mem_block **heap, int start, int size)
135{ 136{
136 struct mem_block *blocks = drm_alloc(sizeof(*blocks), DRM_MEM_BUFS ); 137 struct mem_block *blocks = drm_alloc(sizeof(*blocks), DRM_MEM_BUFS);
137 138
138 if (!blocks) 139 if (!blocks)
139 return DRM_ERR(ENOMEM); 140 return DRM_ERR(ENOMEM);
140 141
141 *heap = drm_alloc(sizeof(**heap), DRM_MEM_BUFS ); 142 *heap = drm_alloc(sizeof(**heap), DRM_MEM_BUFS);
142 if (!*heap) { 143 if (!*heap) {
143 drm_free( blocks, sizeof(*blocks), DRM_MEM_BUFS ); 144 drm_free(blocks, sizeof(*blocks), DRM_MEM_BUFS);
144 return DRM_ERR(ENOMEM); 145 return DRM_ERR(ENOMEM);
145 } 146 }
146 147
@@ -149,16 +150,15 @@ static int init_heap(struct mem_block **heap, int start, int size)
149 blocks->filp = NULL; 150 blocks->filp = NULL;
150 blocks->next = blocks->prev = *heap; 151 blocks->next = blocks->prev = *heap;
151 152
152 memset( *heap, 0, sizeof(**heap) ); 153 memset(*heap, 0, sizeof(**heap));
153 (*heap)->filp = (DRMFILE) -1; 154 (*heap)->filp = (DRMFILE) - 1;
154 (*heap)->next = (*heap)->prev = blocks; 155 (*heap)->next = (*heap)->prev = blocks;
155 return 0; 156 return 0;
156} 157}
157 158
158
159/* Free all blocks associated with the releasing file. 159/* Free all blocks associated with the releasing file.
160 */ 160 */
161void radeon_mem_release( DRMFILE filp, struct mem_block *heap ) 161void radeon_mem_release(DRMFILE filp, struct mem_block *heap)
162{ 162{
163 struct mem_block *p; 163 struct mem_block *p;
164 164
@@ -166,7 +166,7 @@ void radeon_mem_release( DRMFILE filp, struct mem_block *heap )
166 return; 166 return;
167 167
168 list_for_each(p, heap) { 168 list_for_each(p, heap) {
169 if (p->filp == filp) 169 if (p->filp == filp)
170 p->filp = NULL; 170 p->filp = NULL;
171 } 171 }
172 172
@@ -179,40 +179,37 @@ void radeon_mem_release( DRMFILE filp, struct mem_block *heap )
179 p->size += q->size; 179 p->size += q->size;
180 p->next = q->next; 180 p->next = q->next;
181 p->next->prev = p; 181 p->next->prev = p;
182 drm_free(q, sizeof(*q),DRM_MEM_DRIVER); 182 drm_free(q, sizeof(*q), DRM_MEM_DRIVER);
183 } 183 }
184 } 184 }
185} 185}
186 186
187/* Shutdown. 187/* Shutdown.
188 */ 188 */
189void radeon_mem_takedown( struct mem_block **heap ) 189void radeon_mem_takedown(struct mem_block **heap)
190{ 190{
191 struct mem_block *p; 191 struct mem_block *p;
192 192
193 if (!*heap) 193 if (!*heap)
194 return; 194 return;
195 195
196 for (p = (*heap)->next ; p != *heap ; ) { 196 for (p = (*heap)->next; p != *heap;) {
197 struct mem_block *q = p; 197 struct mem_block *q = p;
198 p = p->next; 198 p = p->next;
199 drm_free(q, sizeof(*q),DRM_MEM_DRIVER); 199 drm_free(q, sizeof(*q), DRM_MEM_DRIVER);
200 } 200 }
201 201
202 drm_free( *heap, sizeof(**heap),DRM_MEM_DRIVER ); 202 drm_free(*heap, sizeof(**heap), DRM_MEM_DRIVER);
203 *heap = NULL; 203 *heap = NULL;
204} 204}
205 205
206
207
208/* IOCTL HANDLERS */ 206/* IOCTL HANDLERS */
209 207
210static struct mem_block **get_heap( drm_radeon_private_t *dev_priv, 208static struct mem_block **get_heap(drm_radeon_private_t * dev_priv, int region)
211 int region )
212{ 209{
213 switch( region ) { 210 switch (region) {
214 case RADEON_MEM_REGION_GART: 211 case RADEON_MEM_REGION_GART:
215 return &dev_priv->gart_heap; 212 return &dev_priv->gart_heap;
216 case RADEON_MEM_REGION_FB: 213 case RADEON_MEM_REGION_FB:
217 return &dev_priv->fb_heap; 214 return &dev_priv->fb_heap;
218 default: 215 default:
@@ -220,103 +217,98 @@ static struct mem_block **get_heap( drm_radeon_private_t *dev_priv,
220 } 217 }
221} 218}
222 219
223int radeon_mem_alloc( DRM_IOCTL_ARGS ) 220int radeon_mem_alloc(DRM_IOCTL_ARGS)
224{ 221{
225 DRM_DEVICE; 222 DRM_DEVICE;
226 drm_radeon_private_t *dev_priv = dev->dev_private; 223 drm_radeon_private_t *dev_priv = dev->dev_private;
227 drm_radeon_mem_alloc_t alloc; 224 drm_radeon_mem_alloc_t alloc;
228 struct mem_block *block, **heap; 225 struct mem_block *block, **heap;
229 226
230 if ( !dev_priv ) { 227 if (!dev_priv) {
231 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 228 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
232 return DRM_ERR(EINVAL); 229 return DRM_ERR(EINVAL);
233 } 230 }
234 231
235 DRM_COPY_FROM_USER_IOCTL( alloc, (drm_radeon_mem_alloc_t __user *)data, 232 DRM_COPY_FROM_USER_IOCTL(alloc, (drm_radeon_mem_alloc_t __user *) data,
236 sizeof(alloc) ); 233 sizeof(alloc));
237 234
238 heap = get_heap( dev_priv, alloc.region ); 235 heap = get_heap(dev_priv, alloc.region);
239 if (!heap || !*heap) 236 if (!heap || !*heap)
240 return DRM_ERR(EFAULT); 237 return DRM_ERR(EFAULT);
241 238
242 /* Make things easier on ourselves: all allocations at least 239 /* Make things easier on ourselves: all allocations at least
243 * 4k aligned. 240 * 4k aligned.
244 */ 241 */
245 if (alloc.alignment < 12) 242 if (alloc.alignment < 12)
246 alloc.alignment = 12; 243 alloc.alignment = 12;
247 244
248 block = alloc_block( *heap, alloc.size, alloc.alignment, 245 block = alloc_block(*heap, alloc.size, alloc.alignment, filp);
249 filp );
250 246
251 if (!block) 247 if (!block)
252 return DRM_ERR(ENOMEM); 248 return DRM_ERR(ENOMEM);
253 249
254 if ( DRM_COPY_TO_USER( alloc.region_offset, &block->start, 250 if (DRM_COPY_TO_USER(alloc.region_offset, &block->start, sizeof(int))) {
255 sizeof(int) ) ) { 251 DRM_ERROR("copy_to_user\n");
256 DRM_ERROR( "copy_to_user\n" );
257 return DRM_ERR(EFAULT); 252 return DRM_ERR(EFAULT);
258 } 253 }
259 254
260 return 0; 255 return 0;
261} 256}
262 257
263 258int radeon_mem_free(DRM_IOCTL_ARGS)
264
265int radeon_mem_free( DRM_IOCTL_ARGS )
266{ 259{
267 DRM_DEVICE; 260 DRM_DEVICE;
268 drm_radeon_private_t *dev_priv = dev->dev_private; 261 drm_radeon_private_t *dev_priv = dev->dev_private;
269 drm_radeon_mem_free_t memfree; 262 drm_radeon_mem_free_t memfree;
270 struct mem_block *block, **heap; 263 struct mem_block *block, **heap;
271 264
272 if ( !dev_priv ) { 265 if (!dev_priv) {
273 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 266 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
274 return DRM_ERR(EINVAL); 267 return DRM_ERR(EINVAL);
275 } 268 }
276 269
277 DRM_COPY_FROM_USER_IOCTL( memfree, (drm_radeon_mem_free_t __user *)data, 270 DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_mem_free_t __user *) data,
278 sizeof(memfree) ); 271 sizeof(memfree));
279 272
280 heap = get_heap( dev_priv, memfree.region ); 273 heap = get_heap(dev_priv, memfree.region);
281 if (!heap || !*heap) 274 if (!heap || !*heap)
282 return DRM_ERR(EFAULT); 275 return DRM_ERR(EFAULT);
283 276
284 block = find_block( *heap, memfree.region_offset ); 277 block = find_block(*heap, memfree.region_offset);
285 if (!block) 278 if (!block)
286 return DRM_ERR(EFAULT); 279 return DRM_ERR(EFAULT);
287 280
288 if (block->filp != filp) 281 if (block->filp != filp)
289 return DRM_ERR(EPERM); 282 return DRM_ERR(EPERM);
290 283
291 free_block( block ); 284 free_block(block);
292 return 0; 285 return 0;
293} 286}
294 287
295int radeon_mem_init_heap( DRM_IOCTL_ARGS ) 288int radeon_mem_init_heap(DRM_IOCTL_ARGS)
296{ 289{
297 DRM_DEVICE; 290 DRM_DEVICE;
298 drm_radeon_private_t *dev_priv = dev->dev_private; 291 drm_radeon_private_t *dev_priv = dev->dev_private;
299 drm_radeon_mem_init_heap_t initheap; 292 drm_radeon_mem_init_heap_t initheap;
300 struct mem_block **heap; 293 struct mem_block **heap;
301 294
302 if ( !dev_priv ) { 295 if (!dev_priv) {
303 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 296 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
304 return DRM_ERR(EINVAL); 297 return DRM_ERR(EINVAL);
305 } 298 }
306 299
307 DRM_COPY_FROM_USER_IOCTL( initheap, (drm_radeon_mem_init_heap_t __user *)data, 300 DRM_COPY_FROM_USER_IOCTL(initheap,
308 sizeof(initheap) ); 301 (drm_radeon_mem_init_heap_t __user *) data,
302 sizeof(initheap));
309 303
310 heap = get_heap( dev_priv, initheap.region ); 304 heap = get_heap(dev_priv, initheap.region);
311 if (!heap) 305 if (!heap)
312 return DRM_ERR(EFAULT); 306 return DRM_ERR(EFAULT);
313 307
314 if (*heap) { 308 if (*heap) {
315 DRM_ERROR("heap already initialized?"); 309 DRM_ERROR("heap already initialized?");
316 return DRM_ERR(EFAULT); 310 return DRM_ERR(EFAULT);
317 } 311 }
318
319 return init_heap( heap, initheap.start, initheap.size );
320}
321
322 312
313 return init_heap(heap, initheap.start, initheap.size);
314}
diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c
index 74c2fe8033c2..42e8ce4dbe99 100644
--- a/drivers/char/drm/radeon_state.c
+++ b/drivers/char/drm/radeon_state.c
@@ -37,51 +37,58 @@
37 * Helper functions for client state checking and fixup 37 * Helper functions for client state checking and fixup
38 */ 38 */
39 39
40static __inline__ int radeon_check_and_fixup_offset( drm_radeon_private_t *dev_priv, 40static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t *
41 drm_file_t *filp_priv, 41 dev_priv,
42 u32 *offset ) { 42 drm_file_t * filp_priv,
43 u32 * offset)
44{
43 u32 off = *offset; 45 u32 off = *offset;
44 struct drm_radeon_driver_file_fields *radeon_priv; 46 struct drm_radeon_driver_file_fields *radeon_priv;
45 47
46 if ( off >= dev_priv->fb_location && 48 if (off >= dev_priv->fb_location &&
47 off < ( dev_priv->gart_vm_start + dev_priv->gart_size ) ) 49 off < (dev_priv->gart_vm_start + dev_priv->gart_size))
48 return 0; 50 return 0;
49 51
50 radeon_priv = filp_priv->driver_priv; 52 radeon_priv = filp_priv->driver_priv;
51 off += radeon_priv->radeon_fb_delta; 53 off += radeon_priv->radeon_fb_delta;
52 54
53 DRM_DEBUG( "offset fixed up to 0x%x\n", off ); 55 DRM_DEBUG("offset fixed up to 0x%x\n", off);
54 56
55 if ( off < dev_priv->fb_location || 57 if (off < dev_priv->fb_location ||
56 off >= ( dev_priv->gart_vm_start + dev_priv->gart_size ) ) 58 off >= (dev_priv->gart_vm_start + dev_priv->gart_size))
57 return DRM_ERR( EINVAL ); 59 return DRM_ERR(EINVAL);
58 60
59 *offset = off; 61 *offset = off;
60 62
61 return 0; 63 return 0;
62} 64}
63 65
64static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_priv, 66static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
65 drm_file_t *filp_priv, 67 dev_priv,
66 int id, 68 drm_file_t * filp_priv,
67 u32 __user *data ) { 69 int id, u32 __user * data)
68 switch ( id ) { 70{
71 switch (id) {
69 72
70 case RADEON_EMIT_PP_MISC: 73 case RADEON_EMIT_PP_MISC:
71 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 74 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
72 &data[( RADEON_RB3D_DEPTHOFFSET 75 &data[(RADEON_RB3D_DEPTHOFFSET
73 - RADEON_PP_MISC ) / 4] ) ) { 76 -
74 DRM_ERROR( "Invalid depth buffer offset\n" ); 77 RADEON_PP_MISC) /
75 return DRM_ERR( EINVAL ); 78 4])) {
79 DRM_ERROR("Invalid depth buffer offset\n");
80 return DRM_ERR(EINVAL);
76 } 81 }
77 break; 82 break;
78 83
79 case RADEON_EMIT_PP_CNTL: 84 case RADEON_EMIT_PP_CNTL:
80 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 85 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
81 &data[( RADEON_RB3D_COLOROFFSET 86 &data[(RADEON_RB3D_COLOROFFSET
82 - RADEON_PP_CNTL ) / 4] ) ) { 87 -
83 DRM_ERROR( "Invalid colour buffer offset\n" ); 88 RADEON_PP_CNTL) /
84 return DRM_ERR( EINVAL ); 89 4])) {
90 DRM_ERROR("Invalid colour buffer offset\n");
91 return DRM_ERR(EINVAL);
85 } 92 }
86 break; 93 break;
87 94
@@ -91,21 +98,23 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
91 case R200_EMIT_PP_TXOFFSET_3: 98 case R200_EMIT_PP_TXOFFSET_3:
92 case R200_EMIT_PP_TXOFFSET_4: 99 case R200_EMIT_PP_TXOFFSET_4:
93 case R200_EMIT_PP_TXOFFSET_5: 100 case R200_EMIT_PP_TXOFFSET_5:
94 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 101 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
95 &data[0] ) ) { 102 &data[0])) {
96 DRM_ERROR( "Invalid R200 texture offset\n" ); 103 DRM_ERROR("Invalid R200 texture offset\n");
97 return DRM_ERR( EINVAL ); 104 return DRM_ERR(EINVAL);
98 } 105 }
99 break; 106 break;
100 107
101 case RADEON_EMIT_PP_TXFILTER_0: 108 case RADEON_EMIT_PP_TXFILTER_0:
102 case RADEON_EMIT_PP_TXFILTER_1: 109 case RADEON_EMIT_PP_TXFILTER_1:
103 case RADEON_EMIT_PP_TXFILTER_2: 110 case RADEON_EMIT_PP_TXFILTER_2:
104 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 111 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
105 &data[( RADEON_PP_TXOFFSET_0 112 &data[(RADEON_PP_TXOFFSET_0
106 - RADEON_PP_TXFILTER_0 ) / 4] ) ) { 113 -
107 DRM_ERROR( "Invalid R100 texture offset\n" ); 114 RADEON_PP_TXFILTER_0) /
108 return DRM_ERR( EINVAL ); 115 4])) {
116 DRM_ERROR("Invalid R100 texture offset\n");
117 return DRM_ERR(EINVAL);
109 } 118 }
110 break; 119 break;
111 120
@@ -114,17 +123,18 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
114 case R200_EMIT_PP_CUBIC_OFFSETS_2: 123 case R200_EMIT_PP_CUBIC_OFFSETS_2:
115 case R200_EMIT_PP_CUBIC_OFFSETS_3: 124 case R200_EMIT_PP_CUBIC_OFFSETS_3:
116 case R200_EMIT_PP_CUBIC_OFFSETS_4: 125 case R200_EMIT_PP_CUBIC_OFFSETS_4:
117 case R200_EMIT_PP_CUBIC_OFFSETS_5: { 126 case R200_EMIT_PP_CUBIC_OFFSETS_5:{
118 int i; 127 int i;
119 for ( i = 0; i < 5; i++ ) { 128 for (i = 0; i < 5; i++) {
120 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 129 if (radeon_check_and_fixup_offset
121 &data[i] ) ) { 130 (dev_priv, filp_priv, &data[i])) {
122 DRM_ERROR( "Invalid R200 cubic texture offset\n" ); 131 DRM_ERROR
123 return DRM_ERR( EINVAL ); 132 ("Invalid R200 cubic texture offset\n");
133 return DRM_ERR(EINVAL);
134 }
124 } 135 }
136 break;
125 } 137 }
126 break;
127 }
128 138
129 case RADEON_EMIT_PP_CUBIC_OFFSETS_T0: 139 case RADEON_EMIT_PP_CUBIC_OFFSETS_T0:
130 case RADEON_EMIT_PP_CUBIC_OFFSETS_T1: 140 case RADEON_EMIT_PP_CUBIC_OFFSETS_T1:
@@ -220,243 +230,247 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
220 break; 230 break;
221 231
222 default: 232 default:
223 DRM_ERROR( "Unknown state packet ID %d\n", id ); 233 DRM_ERROR("Unknown state packet ID %d\n", id);
224 return DRM_ERR( EINVAL ); 234 return DRM_ERR(EINVAL);
225 } 235 }
226 236
227 return 0; 237 return 0;
228} 238}
229 239
230static __inline__ int radeon_check_and_fixup_packet3( drm_radeon_private_t *dev_priv, 240static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
231 drm_file_t *filp_priv, 241 dev_priv,
232 drm_radeon_cmd_buffer_t *cmdbuf, 242 drm_file_t * filp_priv,
233 unsigned int *cmdsz ) { 243 drm_radeon_cmd_buffer_t *
244 cmdbuf,
245 unsigned int *cmdsz)
246{
234 u32 *cmd = (u32 *) cmdbuf->buf; 247 u32 *cmd = (u32 *) cmdbuf->buf;
235 248
236 *cmdsz = 2 + ( ( cmd[0] & RADEON_CP_PACKET_COUNT_MASK ) >> 16 ); 249 *cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16);
237 250
238 if ( ( cmd[0] & 0xc0000000 ) != RADEON_CP_PACKET3 ) { 251 if ((cmd[0] & 0xc0000000) != RADEON_CP_PACKET3) {
239 DRM_ERROR( "Not a type 3 packet\n" ); 252 DRM_ERROR("Not a type 3 packet\n");
240 return DRM_ERR( EINVAL ); 253 return DRM_ERR(EINVAL);
241 } 254 }
242 255
243 if ( 4 * *cmdsz > cmdbuf->bufsz ) { 256 if (4 * *cmdsz > cmdbuf->bufsz) {
244 DRM_ERROR( "Packet size larger than size of data provided\n" ); 257 DRM_ERROR("Packet size larger than size of data provided\n");
245 return DRM_ERR( EINVAL ); 258 return DRM_ERR(EINVAL);
246 } 259 }
247 260
248 /* Check client state and fix it up if necessary */ 261 /* Check client state and fix it up if necessary */
249 if ( cmd[0] & 0x8000 ) { /* MSB of opcode: next DWORD GUI_CNTL */ 262 if (cmd[0] & 0x8000) { /* MSB of opcode: next DWORD GUI_CNTL */
250 u32 offset; 263 u32 offset;
251 264
252 if ( cmd[1] & ( RADEON_GMC_SRC_PITCH_OFFSET_CNTL 265 if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
253 | RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) { 266 | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
254 offset = cmd[2] << 10; 267 offset = cmd[2] << 10;
255 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) { 268 if (radeon_check_and_fixup_offset
256 DRM_ERROR( "Invalid first packet offset\n" ); 269 (dev_priv, filp_priv, &offset)) {
257 return DRM_ERR( EINVAL ); 270 DRM_ERROR("Invalid first packet offset\n");
271 return DRM_ERR(EINVAL);
258 } 272 }
259 cmd[2] = ( cmd[2] & 0xffc00000 ) | offset >> 10; 273 cmd[2] = (cmd[2] & 0xffc00000) | offset >> 10;
260 } 274 }
261 275
262 if ( ( cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL ) && 276 if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
263 ( cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) { 277 (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
264 offset = cmd[3] << 10; 278 offset = cmd[3] << 10;
265 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) { 279 if (radeon_check_and_fixup_offset
266 DRM_ERROR( "Invalid second packet offset\n" ); 280 (dev_priv, filp_priv, &offset)) {
267 return DRM_ERR( EINVAL ); 281 DRM_ERROR("Invalid second packet offset\n");
282 return DRM_ERR(EINVAL);
268 } 283 }
269 cmd[3] = ( cmd[3] & 0xffc00000 ) | offset >> 10; 284 cmd[3] = (cmd[3] & 0xffc00000) | offset >> 10;
270 } 285 }
271 } 286 }
272 287
273 return 0; 288 return 0;
274} 289}
275 290
276
277/* ================================================================ 291/* ================================================================
278 * CP hardware state programming functions 292 * CP hardware state programming functions
279 */ 293 */
280 294
281static __inline__ void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv, 295static __inline__ void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv,
282 drm_clip_rect_t *box ) 296 drm_clip_rect_t * box)
283{ 297{
284 RING_LOCALS; 298 RING_LOCALS;
285 299
286 DRM_DEBUG( " box: x1=%d y1=%d x2=%d y2=%d\n", 300 DRM_DEBUG(" box: x1=%d y1=%d x2=%d y2=%d\n",
287 box->x1, box->y1, box->x2, box->y2 ); 301 box->x1, box->y1, box->x2, box->y2);
288 302
289 BEGIN_RING( 4 ); 303 BEGIN_RING(4);
290 OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) ); 304 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
291 OUT_RING( (box->y1 << 16) | box->x1 ); 305 OUT_RING((box->y1 << 16) | box->x1);
292 OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) ); 306 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
293 OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) ); 307 OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1));
294 ADVANCE_RING(); 308 ADVANCE_RING();
295} 309}
296 310
297/* Emit 1.1 state 311/* Emit 1.1 state
298 */ 312 */
299static int radeon_emit_state( drm_radeon_private_t *dev_priv, 313static int radeon_emit_state(drm_radeon_private_t * dev_priv,
300 drm_file_t *filp_priv, 314 drm_file_t * filp_priv,
301 drm_radeon_context_regs_t *ctx, 315 drm_radeon_context_regs_t * ctx,
302 drm_radeon_texture_regs_t *tex, 316 drm_radeon_texture_regs_t * tex,
303 unsigned int dirty ) 317 unsigned int dirty)
304{ 318{
305 RING_LOCALS; 319 RING_LOCALS;
306 DRM_DEBUG( "dirty=0x%08x\n", dirty ); 320 DRM_DEBUG("dirty=0x%08x\n", dirty);
307 321
308 if ( dirty & RADEON_UPLOAD_CONTEXT ) { 322 if (dirty & RADEON_UPLOAD_CONTEXT) {
309 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 323 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
310 &ctx->rb3d_depthoffset ) ) { 324 &ctx->rb3d_depthoffset)) {
311 DRM_ERROR( "Invalid depth buffer offset\n" ); 325 DRM_ERROR("Invalid depth buffer offset\n");
312 return DRM_ERR( EINVAL ); 326 return DRM_ERR(EINVAL);
313 } 327 }
314 328
315 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 329 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
316 &ctx->rb3d_coloroffset ) ) { 330 &ctx->rb3d_coloroffset)) {
317 DRM_ERROR( "Invalid depth buffer offset\n" ); 331 DRM_ERROR("Invalid depth buffer offset\n");
318 return DRM_ERR( EINVAL ); 332 return DRM_ERR(EINVAL);
319 } 333 }
320 334
321 BEGIN_RING( 14 ); 335 BEGIN_RING(14);
322 OUT_RING( CP_PACKET0( RADEON_PP_MISC, 6 ) ); 336 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6));
323 OUT_RING( ctx->pp_misc ); 337 OUT_RING(ctx->pp_misc);
324 OUT_RING( ctx->pp_fog_color ); 338 OUT_RING(ctx->pp_fog_color);
325 OUT_RING( ctx->re_solid_color ); 339 OUT_RING(ctx->re_solid_color);
326 OUT_RING( ctx->rb3d_blendcntl ); 340 OUT_RING(ctx->rb3d_blendcntl);
327 OUT_RING( ctx->rb3d_depthoffset ); 341 OUT_RING(ctx->rb3d_depthoffset);
328 OUT_RING( ctx->rb3d_depthpitch ); 342 OUT_RING(ctx->rb3d_depthpitch);
329 OUT_RING( ctx->rb3d_zstencilcntl ); 343 OUT_RING(ctx->rb3d_zstencilcntl);
330 OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 2 ) ); 344 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2));
331 OUT_RING( ctx->pp_cntl ); 345 OUT_RING(ctx->pp_cntl);
332 OUT_RING( ctx->rb3d_cntl ); 346 OUT_RING(ctx->rb3d_cntl);
333 OUT_RING( ctx->rb3d_coloroffset ); 347 OUT_RING(ctx->rb3d_coloroffset);
334 OUT_RING( CP_PACKET0( RADEON_RB3D_COLORPITCH, 0 ) ); 348 OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
335 OUT_RING( ctx->rb3d_colorpitch ); 349 OUT_RING(ctx->rb3d_colorpitch);
336 ADVANCE_RING(); 350 ADVANCE_RING();
337 } 351 }
338 352
339 if ( dirty & RADEON_UPLOAD_VERTFMT ) { 353 if (dirty & RADEON_UPLOAD_VERTFMT) {
340 BEGIN_RING( 2 ); 354 BEGIN_RING(2);
341 OUT_RING( CP_PACKET0( RADEON_SE_COORD_FMT, 0 ) ); 355 OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0));
342 OUT_RING( ctx->se_coord_fmt ); 356 OUT_RING(ctx->se_coord_fmt);
343 ADVANCE_RING(); 357 ADVANCE_RING();
344 } 358 }
345 359
346 if ( dirty & RADEON_UPLOAD_LINE ) { 360 if (dirty & RADEON_UPLOAD_LINE) {
347 BEGIN_RING( 5 ); 361 BEGIN_RING(5);
348 OUT_RING( CP_PACKET0( RADEON_RE_LINE_PATTERN, 1 ) ); 362 OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1));
349 OUT_RING( ctx->re_line_pattern ); 363 OUT_RING(ctx->re_line_pattern);
350 OUT_RING( ctx->re_line_state ); 364 OUT_RING(ctx->re_line_state);
351 OUT_RING( CP_PACKET0( RADEON_SE_LINE_WIDTH, 0 ) ); 365 OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0));
352 OUT_RING( ctx->se_line_width ); 366 OUT_RING(ctx->se_line_width);
353 ADVANCE_RING(); 367 ADVANCE_RING();
354 } 368 }
355 369
356 if ( dirty & RADEON_UPLOAD_BUMPMAP ) { 370 if (dirty & RADEON_UPLOAD_BUMPMAP) {
357 BEGIN_RING( 5 ); 371 BEGIN_RING(5);
358 OUT_RING( CP_PACKET0( RADEON_PP_LUM_MATRIX, 0 ) ); 372 OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0));
359 OUT_RING( ctx->pp_lum_matrix ); 373 OUT_RING(ctx->pp_lum_matrix);
360 OUT_RING( CP_PACKET0( RADEON_PP_ROT_MATRIX_0, 1 ) ); 374 OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_0, 1));
361 OUT_RING( ctx->pp_rot_matrix_0 ); 375 OUT_RING(ctx->pp_rot_matrix_0);
362 OUT_RING( ctx->pp_rot_matrix_1 ); 376 OUT_RING(ctx->pp_rot_matrix_1);
363 ADVANCE_RING(); 377 ADVANCE_RING();
364 } 378 }
365 379
366 if ( dirty & RADEON_UPLOAD_MASKS ) { 380 if (dirty & RADEON_UPLOAD_MASKS) {
367 BEGIN_RING( 4 ); 381 BEGIN_RING(4);
368 OUT_RING( CP_PACKET0( RADEON_RB3D_STENCILREFMASK, 2 ) ); 382 OUT_RING(CP_PACKET0(RADEON_RB3D_STENCILREFMASK, 2));
369 OUT_RING( ctx->rb3d_stencilrefmask ); 383 OUT_RING(ctx->rb3d_stencilrefmask);
370 OUT_RING( ctx->rb3d_ropcntl ); 384 OUT_RING(ctx->rb3d_ropcntl);
371 OUT_RING( ctx->rb3d_planemask ); 385 OUT_RING(ctx->rb3d_planemask);
372 ADVANCE_RING(); 386 ADVANCE_RING();
373 } 387 }
374 388
375 if ( dirty & RADEON_UPLOAD_VIEWPORT ) { 389 if (dirty & RADEON_UPLOAD_VIEWPORT) {
376 BEGIN_RING( 7 ); 390 BEGIN_RING(7);
377 OUT_RING( CP_PACKET0( RADEON_SE_VPORT_XSCALE, 5 ) ); 391 OUT_RING(CP_PACKET0(RADEON_SE_VPORT_XSCALE, 5));
378 OUT_RING( ctx->se_vport_xscale ); 392 OUT_RING(ctx->se_vport_xscale);
379 OUT_RING( ctx->se_vport_xoffset ); 393 OUT_RING(ctx->se_vport_xoffset);
380 OUT_RING( ctx->se_vport_yscale ); 394 OUT_RING(ctx->se_vport_yscale);
381 OUT_RING( ctx->se_vport_yoffset ); 395 OUT_RING(ctx->se_vport_yoffset);
382 OUT_RING( ctx->se_vport_zscale ); 396 OUT_RING(ctx->se_vport_zscale);
383 OUT_RING( ctx->se_vport_zoffset ); 397 OUT_RING(ctx->se_vport_zoffset);
384 ADVANCE_RING(); 398 ADVANCE_RING();
385 } 399 }
386 400
387 if ( dirty & RADEON_UPLOAD_SETUP ) { 401 if (dirty & RADEON_UPLOAD_SETUP) {
388 BEGIN_RING( 4 ); 402 BEGIN_RING(4);
389 OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) ); 403 OUT_RING(CP_PACKET0(RADEON_SE_CNTL, 0));
390 OUT_RING( ctx->se_cntl ); 404 OUT_RING(ctx->se_cntl);
391 OUT_RING( CP_PACKET0( RADEON_SE_CNTL_STATUS, 0 ) ); 405 OUT_RING(CP_PACKET0(RADEON_SE_CNTL_STATUS, 0));
392 OUT_RING( ctx->se_cntl_status ); 406 OUT_RING(ctx->se_cntl_status);
393 ADVANCE_RING(); 407 ADVANCE_RING();
394 } 408 }
395 409
396 if ( dirty & RADEON_UPLOAD_MISC ) { 410 if (dirty & RADEON_UPLOAD_MISC) {
397 BEGIN_RING( 2 ); 411 BEGIN_RING(2);
398 OUT_RING( CP_PACKET0( RADEON_RE_MISC, 0 ) ); 412 OUT_RING(CP_PACKET0(RADEON_RE_MISC, 0));
399 OUT_RING( ctx->re_misc ); 413 OUT_RING(ctx->re_misc);
400 ADVANCE_RING(); 414 ADVANCE_RING();
401 } 415 }
402 416
403 if ( dirty & RADEON_UPLOAD_TEX0 ) { 417 if (dirty & RADEON_UPLOAD_TEX0) {
404 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 418 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
405 &tex[0].pp_txoffset ) ) { 419 &tex[0].pp_txoffset)) {
406 DRM_ERROR( "Invalid texture offset for unit 0\n" ); 420 DRM_ERROR("Invalid texture offset for unit 0\n");
407 return DRM_ERR( EINVAL ); 421 return DRM_ERR(EINVAL);
408 } 422 }
409 423
410 BEGIN_RING( 9 ); 424 BEGIN_RING(9);
411 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) ); 425 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_0, 5));
412 OUT_RING( tex[0].pp_txfilter ); 426 OUT_RING(tex[0].pp_txfilter);
413 OUT_RING( tex[0].pp_txformat ); 427 OUT_RING(tex[0].pp_txformat);
414 OUT_RING( tex[0].pp_txoffset ); 428 OUT_RING(tex[0].pp_txoffset);
415 OUT_RING( tex[0].pp_txcblend ); 429 OUT_RING(tex[0].pp_txcblend);
416 OUT_RING( tex[0].pp_txablend ); 430 OUT_RING(tex[0].pp_txablend);
417 OUT_RING( tex[0].pp_tfactor ); 431 OUT_RING(tex[0].pp_tfactor);
418 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) ); 432 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_0, 0));
419 OUT_RING( tex[0].pp_border_color ); 433 OUT_RING(tex[0].pp_border_color);
420 ADVANCE_RING(); 434 ADVANCE_RING();
421 } 435 }
422 436
423 if ( dirty & RADEON_UPLOAD_TEX1 ) { 437 if (dirty & RADEON_UPLOAD_TEX1) {
424 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 438 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
425 &tex[1].pp_txoffset ) ) { 439 &tex[1].pp_txoffset)) {
426 DRM_ERROR( "Invalid texture offset for unit 1\n" ); 440 DRM_ERROR("Invalid texture offset for unit 1\n");
427 return DRM_ERR( EINVAL ); 441 return DRM_ERR(EINVAL);
428 } 442 }
429 443
430 BEGIN_RING( 9 ); 444 BEGIN_RING(9);
431 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) ); 445 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_1, 5));
432 OUT_RING( tex[1].pp_txfilter ); 446 OUT_RING(tex[1].pp_txfilter);
433 OUT_RING( tex[1].pp_txformat ); 447 OUT_RING(tex[1].pp_txformat);
434 OUT_RING( tex[1].pp_txoffset ); 448 OUT_RING(tex[1].pp_txoffset);
435 OUT_RING( tex[1].pp_txcblend ); 449 OUT_RING(tex[1].pp_txcblend);
436 OUT_RING( tex[1].pp_txablend ); 450 OUT_RING(tex[1].pp_txablend);
437 OUT_RING( tex[1].pp_tfactor ); 451 OUT_RING(tex[1].pp_tfactor);
438 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) ); 452 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_1, 0));
439 OUT_RING( tex[1].pp_border_color ); 453 OUT_RING(tex[1].pp_border_color);
440 ADVANCE_RING(); 454 ADVANCE_RING();
441 } 455 }
442 456
443 if ( dirty & RADEON_UPLOAD_TEX2 ) { 457 if (dirty & RADEON_UPLOAD_TEX2) {
444 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, 458 if (radeon_check_and_fixup_offset(dev_priv, filp_priv,
445 &tex[2].pp_txoffset ) ) { 459 &tex[2].pp_txoffset)) {
446 DRM_ERROR( "Invalid texture offset for unit 2\n" ); 460 DRM_ERROR("Invalid texture offset for unit 2\n");
447 return DRM_ERR( EINVAL ); 461 return DRM_ERR(EINVAL);
448 } 462 }
449 463
450 BEGIN_RING( 9 ); 464 BEGIN_RING(9);
451 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) ); 465 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_2, 5));
452 OUT_RING( tex[2].pp_txfilter ); 466 OUT_RING(tex[2].pp_txfilter);
453 OUT_RING( tex[2].pp_txformat ); 467 OUT_RING(tex[2].pp_txformat);
454 OUT_RING( tex[2].pp_txoffset ); 468 OUT_RING(tex[2].pp_txoffset);
455 OUT_RING( tex[2].pp_txcblend ); 469 OUT_RING(tex[2].pp_txcblend);
456 OUT_RING( tex[2].pp_txablend ); 470 OUT_RING(tex[2].pp_txablend);
457 OUT_RING( tex[2].pp_tfactor ); 471 OUT_RING(tex[2].pp_tfactor);
458 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) ); 472 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_2, 0));
459 OUT_RING( tex[2].pp_border_color ); 473 OUT_RING(tex[2].pp_border_color);
460 ADVANCE_RING(); 474 ADVANCE_RING();
461 } 475 }
462 476
@@ -465,138 +479,137 @@ static int radeon_emit_state( drm_radeon_private_t *dev_priv,
465 479
466/* Emit 1.2 state 480/* Emit 1.2 state
467 */ 481 */
468static int radeon_emit_state2( drm_radeon_private_t *dev_priv, 482static int radeon_emit_state2(drm_radeon_private_t * dev_priv,
469 drm_file_t *filp_priv, 483 drm_file_t * filp_priv,
470 drm_radeon_state_t *state ) 484 drm_radeon_state_t * state)
471{ 485{
472 RING_LOCALS; 486 RING_LOCALS;
473 487
474 if (state->dirty & RADEON_UPLOAD_ZBIAS) { 488 if (state->dirty & RADEON_UPLOAD_ZBIAS) {
475 BEGIN_RING( 3 ); 489 BEGIN_RING(3);
476 OUT_RING( CP_PACKET0( RADEON_SE_ZBIAS_FACTOR, 1 ) ); 490 OUT_RING(CP_PACKET0(RADEON_SE_ZBIAS_FACTOR, 1));
477 OUT_RING( state->context2.se_zbias_factor ); 491 OUT_RING(state->context2.se_zbias_factor);
478 OUT_RING( state->context2.se_zbias_constant ); 492 OUT_RING(state->context2.se_zbias_constant);
479 ADVANCE_RING(); 493 ADVANCE_RING();
480 } 494 }
481 495
482 return radeon_emit_state( dev_priv, filp_priv, &state->context, 496 return radeon_emit_state(dev_priv, filp_priv, &state->context,
483 state->tex, state->dirty ); 497 state->tex, state->dirty);
484} 498}
485 499
486/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in 500/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
487 * 1.3 cmdbuffers allow all previous state to be updated as well as 501 * 1.3 cmdbuffers allow all previous state to be updated as well as
488 * the tcl scalar and vector areas. 502 * the tcl scalar and vector areas.
489 */ 503 */
490static struct { 504static struct {
491 int start; 505 int start;
492 int len; 506 int len;
493 const char *name; 507 const char *name;
494} packet[RADEON_MAX_STATE_PACKETS] = { 508} packet[RADEON_MAX_STATE_PACKETS] = {
495 { RADEON_PP_MISC,7,"RADEON_PP_MISC" }, 509 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
496 { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" }, 510 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
497 { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" }, 511 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
498 { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" }, 512 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
499 { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" }, 513 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
500 { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" }, 514 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
501 { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" }, 515 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
502 { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" }, 516 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
503 { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" }, 517 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
504 { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" }, 518 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
505 { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" }, 519 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
506 { RADEON_RE_MISC,1,"RADEON_RE_MISC" }, 520 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
507 { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" }, 521 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
508 { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" }, 522 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
509 { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" }, 523 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
510 { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" }, 524 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
511 { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" }, 525 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
512 { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" }, 526 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
513 { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" }, 527 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
514 { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" }, 528 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
515 { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" }, 529 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
516 { R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0" }, 530 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
517 { R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1" }, 531 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
518 { R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2" }, 532 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
519 { R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3" }, 533 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
520 { R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4" }, 534 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
521 { R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5" }, 535 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
522 { R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6" }, 536 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
523 { R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7" }, 537 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
524 { R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" }, 538 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
525 { R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0" }, 539 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
526 { R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0" }, 540 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
527 { R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL" }, 541 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
528 { R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0" }, 542 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
529 { R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2" }, 543 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
530 { R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" }, 544 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
531 { R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0" }, 545 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
532 { R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1" }, 546 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
533 { R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2" }, 547 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
534 { R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3" }, 548 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
535 { R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4" }, 549 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
536 { R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5" }, 550 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
537 { R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" }, 551 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
538 { R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1" }, 552 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
539 { R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2" }, 553 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
540 { R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3" }, 554 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
541 { R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" }, 555 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
542 { R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" }, 556 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
543 { R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" }, 557 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
544 { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" }, 558 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
545 { R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" }, 559 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
546 { R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" }, 560 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
547 { R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" }, 561 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
548 { R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" }, 562 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
549 { R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" }, 563 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
550 { R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" }, 564 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
551 { R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" }, 565 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
552 { R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" }, 566 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
553 { R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" }, 567 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
554 { R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" }, 568 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
555 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" }, 569 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
556 { R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */ 570 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
557 { R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */ 571 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
558 { R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1" }, 572 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
559 { R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1" }, 573 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
560 { R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2" }, 574 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
561 { R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2" }, 575 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
562 { R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3" }, 576 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
563 { R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3" }, 577 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
564 { R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4" }, 578 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
565 { R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" }, 579 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
566 { R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" }, 580 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
567 { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" }, 581 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
568 { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" }, 582 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
569 { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" }, 583 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
570 { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" }, 584 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
571 { R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" }, 585 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
572 { R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL" }, 586 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
573 { RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"}, 587 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
574 { RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"}, 588 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
575 { RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, 589 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
576 { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, 590 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
577 { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, 591 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
578 { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, 592 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
579 { R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, 593 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
580 { R200_PP_AFS_0, 32, "R200_PP_AFS_0"}, /* 85 */ 594 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
581 { R200_PP_AFS_1, 32, "R200_PP_AFS_1"}, 595 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
582 { R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, 596 {R200_PP_AFS_0, 32, "R200_PP_AFS_0"}, /* 85 */
583 { R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, 597 {R200_PP_AFS_1, 32, "R200_PP_AFS_1"},
584 { R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, 598 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
585 { R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, 599 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
586 { R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, 600 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
587 { R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, 601 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
588 { R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, 602 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
603 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
604 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
589}; 605};
590 606
591
592
593/* ================================================================ 607/* ================================================================
594 * Performance monitoring functions 608 * Performance monitoring functions
595 */ 609 */
596 610
597static void radeon_clear_box( drm_radeon_private_t *dev_priv, 611static void radeon_clear_box(drm_radeon_private_t * dev_priv,
598 int x, int y, int w, int h, 612 int x, int y, int w, int h, int r, int g, int b)
599 int r, int g, int b )
600{ 613{
601 u32 color; 614 u32 color;
602 RING_LOCALS; 615 RING_LOCALS;
@@ -604,49 +617,47 @@ static void radeon_clear_box( drm_radeon_private_t *dev_priv,
604 x += dev_priv->sarea_priv->boxes[0].x1; 617 x += dev_priv->sarea_priv->boxes[0].x1;
605 y += dev_priv->sarea_priv->boxes[0].y1; 618 y += dev_priv->sarea_priv->boxes[0].y1;
606 619
607 switch ( dev_priv->color_fmt ) { 620 switch (dev_priv->color_fmt) {
608 case RADEON_COLOR_FORMAT_RGB565: 621 case RADEON_COLOR_FORMAT_RGB565:
609 color = (((r & 0xf8) << 8) | 622 color = (((r & 0xf8) << 8) |
610 ((g & 0xfc) << 3) | 623 ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
611 ((b & 0xf8) >> 3));
612 break; 624 break;
613 case RADEON_COLOR_FORMAT_ARGB8888: 625 case RADEON_COLOR_FORMAT_ARGB8888:
614 default: 626 default:
615 color = (((0xff) << 24) | (r << 16) | (g << 8) | b); 627 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
616 break; 628 break;
617 } 629 }
618 630
619 BEGIN_RING( 4 ); 631 BEGIN_RING(4);
620 RADEON_WAIT_UNTIL_3D_IDLE(); 632 RADEON_WAIT_UNTIL_3D_IDLE();
621 OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) ); 633 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
622 OUT_RING( 0xffffffff ); 634 OUT_RING(0xffffffff);
623 ADVANCE_RING(); 635 ADVANCE_RING();
624 636
625 BEGIN_RING( 6 ); 637 BEGIN_RING(6);
626 638
627 OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); 639 OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4));
628 OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | 640 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
629 RADEON_GMC_BRUSH_SOLID_COLOR | 641 RADEON_GMC_BRUSH_SOLID_COLOR |
630 (dev_priv->color_fmt << 8) | 642 (dev_priv->color_fmt << 8) |
631 RADEON_GMC_SRC_DATATYPE_COLOR | 643 RADEON_GMC_SRC_DATATYPE_COLOR |
632 RADEON_ROP3_P | 644 RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS);
633 RADEON_GMC_CLR_CMP_CNTL_DIS );
634 645
635 if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { 646 if (dev_priv->page_flipping && dev_priv->current_page == 1) {
636 OUT_RING( dev_priv->front_pitch_offset ); 647 OUT_RING(dev_priv->front_pitch_offset);
637 } else { 648 } else {
638 OUT_RING( dev_priv->back_pitch_offset ); 649 OUT_RING(dev_priv->back_pitch_offset);
639 } 650 }
640 651
641 OUT_RING( color ); 652 OUT_RING(color);
642 653
643 OUT_RING( (x << 16) | y ); 654 OUT_RING((x << 16) | y);
644 OUT_RING( (w << 16) | h ); 655 OUT_RING((w << 16) | h);
645 656
646 ADVANCE_RING(); 657 ADVANCE_RING();
647} 658}
648 659
649static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv ) 660static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv)
650{ 661{
651 /* Collapse various things into a wait flag -- trying to 662 /* Collapse various things into a wait flag -- trying to
652 * guess if userspase slept -- better just to have them tell us. 663 * guess if userspase slept -- better just to have them tell us.
@@ -662,50 +673,50 @@ static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv )
662 673
663 /* Purple box for page flipping 674 /* Purple box for page flipping
664 */ 675 */
665 if ( dev_priv->stats.boxes & RADEON_BOX_FLIP ) 676 if (dev_priv->stats.boxes & RADEON_BOX_FLIP)
666 radeon_clear_box( dev_priv, 4, 4, 8, 8, 255, 0, 255 ); 677 radeon_clear_box(dev_priv, 4, 4, 8, 8, 255, 0, 255);
667 678
668 /* Red box if we have to wait for idle at any point 679 /* Red box if we have to wait for idle at any point
669 */ 680 */
670 if ( dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE ) 681 if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE)
671 radeon_clear_box( dev_priv, 16, 4, 8, 8, 255, 0, 0 ); 682 radeon_clear_box(dev_priv, 16, 4, 8, 8, 255, 0, 0);
672 683
673 /* Blue box: lost context? 684 /* Blue box: lost context?
674 */ 685 */
675 686
676 /* Yellow box for texture swaps 687 /* Yellow box for texture swaps
677 */ 688 */
678 if ( dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD ) 689 if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD)
679 radeon_clear_box( dev_priv, 40, 4, 8, 8, 255, 255, 0 ); 690 radeon_clear_box(dev_priv, 40, 4, 8, 8, 255, 255, 0);
680 691
681 /* Green box if hardware never idles (as far as we can tell) 692 /* Green box if hardware never idles (as far as we can tell)
682 */ 693 */
683 if ( !(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE) ) 694 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE))
684 radeon_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 ); 695 radeon_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0);
685
686 696
687 /* Draw bars indicating number of buffers allocated 697 /* Draw bars indicating number of buffers allocated
688 * (not a great measure, easily confused) 698 * (not a great measure, easily confused)
689 */ 699 */
690 if (dev_priv->stats.requested_bufs) { 700 if (dev_priv->stats.requested_bufs) {
691 if (dev_priv->stats.requested_bufs > 100) 701 if (dev_priv->stats.requested_bufs > 100)
692 dev_priv->stats.requested_bufs = 100; 702 dev_priv->stats.requested_bufs = 100;
693 703
694 radeon_clear_box( dev_priv, 4, 16, 704 radeon_clear_box(dev_priv, 4, 16,
695 dev_priv->stats.requested_bufs, 4, 705 dev_priv->stats.requested_bufs, 4,
696 196, 128, 128 ); 706 196, 128, 128);
697 } 707 }
698 708
699 memset( &dev_priv->stats, 0, sizeof(dev_priv->stats) ); 709 memset(&dev_priv->stats, 0, sizeof(dev_priv->stats));
700 710
701} 711}
712
702/* ================================================================ 713/* ================================================================
703 * CP command dispatch functions 714 * CP command dispatch functions
704 */ 715 */
705 716
706static void radeon_cp_dispatch_clear( drm_device_t *dev, 717static void radeon_cp_dispatch_clear(drm_device_t * dev,
707 drm_radeon_clear_t *clear, 718 drm_radeon_clear_t * clear,
708 drm_radeon_clear_rect_t *depth_boxes ) 719 drm_radeon_clear_rect_t * depth_boxes)
709{ 720{
710 drm_radeon_private_t *dev_priv = dev->dev_private; 721 drm_radeon_private_t *dev_priv = dev->dev_private;
711 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; 722 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -713,32 +724,34 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
713 int nbox = sarea_priv->nbox; 724 int nbox = sarea_priv->nbox;
714 drm_clip_rect_t *pbox = sarea_priv->boxes; 725 drm_clip_rect_t *pbox = sarea_priv->boxes;
715 unsigned int flags = clear->flags; 726 unsigned int flags = clear->flags;
716 u32 rb3d_cntl = 0, rb3d_stencilrefmask= 0; 727 u32 rb3d_cntl = 0, rb3d_stencilrefmask = 0;
717 int i; 728 int i;
718 RING_LOCALS; 729 RING_LOCALS;
719 DRM_DEBUG( "flags = 0x%x\n", flags ); 730 DRM_DEBUG("flags = 0x%x\n", flags);
720 731
721 dev_priv->stats.clears++; 732 dev_priv->stats.clears++;
722 733
723 if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { 734 if (dev_priv->page_flipping && dev_priv->current_page == 1) {
724 unsigned int tmp = flags; 735 unsigned int tmp = flags;
725 736
726 flags &= ~(RADEON_FRONT | RADEON_BACK); 737 flags &= ~(RADEON_FRONT | RADEON_BACK);
727 if ( tmp & RADEON_FRONT ) flags |= RADEON_BACK; 738 if (tmp & RADEON_FRONT)
728 if ( tmp & RADEON_BACK ) flags |= RADEON_FRONT; 739 flags |= RADEON_BACK;
740 if (tmp & RADEON_BACK)
741 flags |= RADEON_FRONT;
729 } 742 }
730 743
731 if ( flags & (RADEON_FRONT | RADEON_BACK) ) { 744 if (flags & (RADEON_FRONT | RADEON_BACK)) {
732 745
733 BEGIN_RING( 4 ); 746 BEGIN_RING(4);
734 747
735 /* Ensure the 3D stream is idle before doing a 748 /* Ensure the 3D stream is idle before doing a
736 * 2D fill to clear the front or back buffer. 749 * 2D fill to clear the front or back buffer.
737 */ 750 */
738 RADEON_WAIT_UNTIL_3D_IDLE(); 751 RADEON_WAIT_UNTIL_3D_IDLE();
739 752
740 OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) ); 753 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
741 OUT_RING( clear->color_mask ); 754 OUT_RING(clear->color_mask);
742 755
743 ADVANCE_RING(); 756 ADVANCE_RING();
744 757
@@ -746,121 +759,130 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
746 */ 759 */
747 dev_priv->sarea_priv->ctx_owner = 0; 760 dev_priv->sarea_priv->ctx_owner = 0;
748 761
749 for ( i = 0 ; i < nbox ; i++ ) { 762 for (i = 0; i < nbox; i++) {
750 int x = pbox[i].x1; 763 int x = pbox[i].x1;
751 int y = pbox[i].y1; 764 int y = pbox[i].y1;
752 int w = pbox[i].x2 - x; 765 int w = pbox[i].x2 - x;
753 int h = pbox[i].y2 - y; 766 int h = pbox[i].y2 - y;
754 767
755 DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n", 768 DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n",
756 x, y, w, h, flags ); 769 x, y, w, h, flags);
757 770
758 if ( flags & RADEON_FRONT ) { 771 if (flags & RADEON_FRONT) {
759 BEGIN_RING( 6 ); 772 BEGIN_RING(6);
760 773
761 OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); 774 OUT_RING(CP_PACKET3
762 OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | 775 (RADEON_CNTL_PAINT_MULTI, 4));
763 RADEON_GMC_BRUSH_SOLID_COLOR | 776 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
764 (dev_priv->color_fmt << 8) | 777 RADEON_GMC_BRUSH_SOLID_COLOR |
765 RADEON_GMC_SRC_DATATYPE_COLOR | 778 (dev_priv->
766 RADEON_ROP3_P | 779 color_fmt << 8) |
767 RADEON_GMC_CLR_CMP_CNTL_DIS ); 780 RADEON_GMC_SRC_DATATYPE_COLOR |
768 781 RADEON_ROP3_P |
769 OUT_RING( dev_priv->front_pitch_offset ); 782 RADEON_GMC_CLR_CMP_CNTL_DIS);
770 OUT_RING( clear->clear_color ); 783
771 784 OUT_RING(dev_priv->front_pitch_offset);
772 OUT_RING( (x << 16) | y ); 785 OUT_RING(clear->clear_color);
773 OUT_RING( (w << 16) | h ); 786
774 787 OUT_RING((x << 16) | y);
788 OUT_RING((w << 16) | h);
789
775 ADVANCE_RING(); 790 ADVANCE_RING();
776 } 791 }
777 792
778 if ( flags & RADEON_BACK ) { 793 if (flags & RADEON_BACK) {
779 BEGIN_RING( 6 ); 794 BEGIN_RING(6);
780 795
781 OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); 796 OUT_RING(CP_PACKET3
782 OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | 797 (RADEON_CNTL_PAINT_MULTI, 4));
783 RADEON_GMC_BRUSH_SOLID_COLOR | 798 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
784 (dev_priv->color_fmt << 8) | 799 RADEON_GMC_BRUSH_SOLID_COLOR |
785 RADEON_GMC_SRC_DATATYPE_COLOR | 800 (dev_priv->
786 RADEON_ROP3_P | 801 color_fmt << 8) |
787 RADEON_GMC_CLR_CMP_CNTL_DIS ); 802 RADEON_GMC_SRC_DATATYPE_COLOR |
788 803 RADEON_ROP3_P |
789 OUT_RING( dev_priv->back_pitch_offset ); 804 RADEON_GMC_CLR_CMP_CNTL_DIS);
790 OUT_RING( clear->clear_color ); 805
791 806 OUT_RING(dev_priv->back_pitch_offset);
792 OUT_RING( (x << 16) | y ); 807 OUT_RING(clear->clear_color);
793 OUT_RING( (w << 16) | h ); 808
809 OUT_RING((x << 16) | y);
810 OUT_RING((w << 16) | h);
794 811
795 ADVANCE_RING(); 812 ADVANCE_RING();
796 } 813 }
797 } 814 }
798 } 815 }
799 816
800 /* hyper z clear */ 817 /* hyper z clear */
801 /* no docs available, based on reverse engeneering by Stephane Marchesin */ 818 /* no docs available, based on reverse engeneering by Stephane Marchesin */
802 if ((flags & (RADEON_DEPTH | RADEON_STENCIL)) && (flags & RADEON_CLEAR_FASTZ)) { 819 if ((flags & (RADEON_DEPTH | RADEON_STENCIL))
820 && (flags & RADEON_CLEAR_FASTZ)) {
803 821
804 int i; 822 int i;
805 int depthpixperline = dev_priv->depth_fmt==RADEON_DEPTH_FORMAT_16BIT_INT_Z? 823 int depthpixperline =
806 (dev_priv->depth_pitch / 2): (dev_priv->depth_pitch / 4); 824 dev_priv->depth_fmt ==
807 825 RADEON_DEPTH_FORMAT_16BIT_INT_Z ? (dev_priv->depth_pitch /
826 2) : (dev_priv->
827 depth_pitch / 4);
828
808 u32 clearmask; 829 u32 clearmask;
809 830
810 u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth | 831 u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth |
811 ((clear->depth_mask & 0xff) << 24); 832 ((clear->depth_mask & 0xff) << 24);
812 833
813
814 /* Make sure we restore the 3D state next time. 834 /* Make sure we restore the 3D state next time.
815 * we haven't touched any "normal" state - still need this? 835 * we haven't touched any "normal" state - still need this?
816 */ 836 */
817 dev_priv->sarea_priv->ctx_owner = 0; 837 dev_priv->sarea_priv->ctx_owner = 0;
818 838
819 if ((dev_priv->flags & CHIP_HAS_HIERZ) && (flags & RADEON_USE_HIERZ)) { 839 if ((dev_priv->flags & CHIP_HAS_HIERZ)
820 /* FIXME : reverse engineer that for Rx00 cards */ 840 && (flags & RADEON_USE_HIERZ)) {
821 /* FIXME : the mask supposedly contains low-res z values. So can't set 841 /* FIXME : reverse engineer that for Rx00 cards */
822 just to the max (0xff? or actually 0x3fff?), need to take z clear 842 /* FIXME : the mask supposedly contains low-res z values. So can't set
823 value into account? */ 843 just to the max (0xff? or actually 0x3fff?), need to take z clear
824 /* pattern seems to work for r100, though get slight 844 value into account? */
825 rendering errors with glxgears. If hierz is not enabled for r100, 845 /* pattern seems to work for r100, though get slight
826 only 4 bits which indicate clear (15,16,31,32, all zero) matter, the 846 rendering errors with glxgears. If hierz is not enabled for r100,
827 other ones are ignored, and the same clear mask can be used. That's 847 only 4 bits which indicate clear (15,16,31,32, all zero) matter, the
828 very different behaviour than R200 which needs different clear mask 848 other ones are ignored, and the same clear mask can be used. That's
829 and different number of tiles to clear if hierz is enabled or not !?! 849 very different behaviour than R200 which needs different clear mask
830 */ 850 and different number of tiles to clear if hierz is enabled or not !?!
831 clearmask = (0xff<<22)|(0xff<<6)| 0x003f003f; 851 */
832 } 852 clearmask = (0xff << 22) | (0xff << 6) | 0x003f003f;
833 else { 853 } else {
834 /* clear mask : chooses the clearing pattern. 854 /* clear mask : chooses the clearing pattern.
835 rv250: could be used to clear only parts of macrotiles 855 rv250: could be used to clear only parts of macrotiles
836 (but that would get really complicated...)? 856 (but that would get really complicated...)?
837 bit 0 and 1 (either or both of them ?!?!) are used to 857 bit 0 and 1 (either or both of them ?!?!) are used to
838 not clear tile (or maybe one of the bits indicates if the tile is 858 not clear tile (or maybe one of the bits indicates if the tile is
839 compressed or not), bit 2 and 3 to not clear tile 1,...,. 859 compressed or not), bit 2 and 3 to not clear tile 1,...,.
840 Pattern is as follows: 860 Pattern is as follows:
841 | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29| 861 | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29|
842 bits ------------------------------------------------- 862 bits -------------------------------------------------
843 | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31| 863 | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31|
844 rv100: clearmask covers 2x8 4x1 tiles, but one clear still 864 rv100: clearmask covers 2x8 4x1 tiles, but one clear still
845 covers 256 pixels ?!? 865 covers 256 pixels ?!?
846 */ 866 */
847 clearmask = 0x0; 867 clearmask = 0x0;
848 } 868 }
849 869
850 BEGIN_RING( 8 ); 870 BEGIN_RING(8);
851 RADEON_WAIT_UNTIL_2D_IDLE(); 871 RADEON_WAIT_UNTIL_2D_IDLE();
852 OUT_RING_REG( RADEON_RB3D_DEPTHCLEARVALUE, 872 OUT_RING_REG(RADEON_RB3D_DEPTHCLEARVALUE,
853 tempRB3D_DEPTHCLEARVALUE); 873 tempRB3D_DEPTHCLEARVALUE);
854 /* what offset is this exactly ? */ 874 /* what offset is this exactly ? */
855 OUT_RING_REG( RADEON_RB3D_ZMASKOFFSET, 0 ); 875 OUT_RING_REG(RADEON_RB3D_ZMASKOFFSET, 0);
856 /* need ctlstat, otherwise get some strange black flickering */ 876 /* need ctlstat, otherwise get some strange black flickering */
857 OUT_RING_REG( RADEON_RB3D_ZCACHE_CTLSTAT, RADEON_RB3D_ZC_FLUSH_ALL ); 877 OUT_RING_REG(RADEON_RB3D_ZCACHE_CTLSTAT,
878 RADEON_RB3D_ZC_FLUSH_ALL);
858 ADVANCE_RING(); 879 ADVANCE_RING();
859 880
860 for (i = 0; i < nbox; i++) { 881 for (i = 0; i < nbox; i++) {
861 int tileoffset, nrtilesx, nrtilesy, j; 882 int tileoffset, nrtilesx, nrtilesy, j;
862 /* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */ 883 /* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */
863 if ((dev_priv->flags&CHIP_HAS_HIERZ) && !(dev_priv->microcode_version==UCODE_R200)) { 884 if ((dev_priv->flags & CHIP_HAS_HIERZ)
885 && !(dev_priv->microcode_version == UCODE_R200)) {
864 /* FIXME : figure this out for r200 (when hierz is enabled). Or 886 /* FIXME : figure this out for r200 (when hierz is enabled). Or
865 maybe r200 actually doesn't need to put the low-res z value into 887 maybe r200 actually doesn't need to put the low-res z value into
866 the tile cache like r100, but just needs to clear the hi-level z-buffer? 888 the tile cache like r100, but just needs to clear the hi-level z-buffer?
@@ -868,59 +890,74 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
868 R100 seems to operate on 2x1 8x8 tiles, but... 890 R100 seems to operate on 2x1 8x8 tiles, but...
869 odd: offset/nrtiles need to be 64 pix (4 block) aligned? Potentially 891 odd: offset/nrtiles need to be 64 pix (4 block) aligned? Potentially
870 problematic with resolutions which are not 64 pix aligned? */ 892 problematic with resolutions which are not 64 pix aligned? */
871 tileoffset = ((pbox[i].y1 >> 3) * depthpixperline + pbox[i].x1) >> 6; 893 tileoffset =
872 nrtilesx = ((pbox[i].x2 & ~63) - (pbox[i].x1 & ~63)) >> 4; 894 ((pbox[i].y1 >> 3) * depthpixperline +
873 nrtilesy = (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3); 895 pbox[i].x1) >> 6;
896 nrtilesx =
897 ((pbox[i].x2 & ~63) -
898 (pbox[i].x1 & ~63)) >> 4;
899 nrtilesy =
900 (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
874 for (j = 0; j <= nrtilesy; j++) { 901 for (j = 0; j <= nrtilesy; j++) {
875 BEGIN_RING( 4 ); 902 BEGIN_RING(4);
876 OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) ); 903 OUT_RING(CP_PACKET3
904 (RADEON_3D_CLEAR_ZMASK, 2));
877 /* first tile */ 905 /* first tile */
878 OUT_RING( tileoffset * 8 ); 906 OUT_RING(tileoffset * 8);
879 /* the number of tiles to clear */ 907 /* the number of tiles to clear */
880 OUT_RING( nrtilesx + 4 ); 908 OUT_RING(nrtilesx + 4);
881 /* clear mask : chooses the clearing pattern. */ 909 /* clear mask : chooses the clearing pattern. */
882 OUT_RING( clearmask ); 910 OUT_RING(clearmask);
883 ADVANCE_RING(); 911 ADVANCE_RING();
884 tileoffset += depthpixperline >> 6; 912 tileoffset += depthpixperline >> 6;
885 } 913 }
886 } 914 } else if (dev_priv->microcode_version == UCODE_R200) {
887 else if (dev_priv->microcode_version==UCODE_R200) {
888 /* works for rv250. */ 915 /* works for rv250. */
889 /* find first macro tile (8x2 4x4 z-pixels on rv250) */ 916 /* find first macro tile (8x2 4x4 z-pixels on rv250) */
890 tileoffset = ((pbox[i].y1 >> 3) * depthpixperline + pbox[i].x1) >> 5; 917 tileoffset =
891 nrtilesx = (pbox[i].x2 >> 5) - (pbox[i].x1 >> 5); 918 ((pbox[i].y1 >> 3) * depthpixperline +
892 nrtilesy = (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3); 919 pbox[i].x1) >> 5;
920 nrtilesx =
921 (pbox[i].x2 >> 5) - (pbox[i].x1 >> 5);
922 nrtilesy =
923 (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
893 for (j = 0; j <= nrtilesy; j++) { 924 for (j = 0; j <= nrtilesy; j++) {
894 BEGIN_RING( 4 ); 925 BEGIN_RING(4);
895 OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) ); 926 OUT_RING(CP_PACKET3
927 (RADEON_3D_CLEAR_ZMASK, 2));
896 /* first tile */ 928 /* first tile */
897 /* judging by the first tile offset needed, could possibly 929 /* judging by the first tile offset needed, could possibly
898 directly address/clear 4x4 tiles instead of 8x2 * 4x4 930 directly address/clear 4x4 tiles instead of 8x2 * 4x4
899 macro tiles, though would still need clear mask for 931 macro tiles, though would still need clear mask for
900 right/bottom if truely 4x4 granularity is desired ? */ 932 right/bottom if truely 4x4 granularity is desired ? */
901 OUT_RING( tileoffset * 16 ); 933 OUT_RING(tileoffset * 16);
902 /* the number of tiles to clear */ 934 /* the number of tiles to clear */
903 OUT_RING( nrtilesx + 1 ); 935 OUT_RING(nrtilesx + 1);
904 /* clear mask : chooses the clearing pattern. */ 936 /* clear mask : chooses the clearing pattern. */
905 OUT_RING( clearmask ); 937 OUT_RING(clearmask);
906 ADVANCE_RING(); 938 ADVANCE_RING();
907 tileoffset += depthpixperline >> 5; 939 tileoffset += depthpixperline >> 5;
908 } 940 }
909 } 941 } else { /* rv 100 */
910 else { /* rv 100 */
911 /* rv100 might not need 64 pix alignment, who knows */ 942 /* rv100 might not need 64 pix alignment, who knows */
912 /* offsets are, hmm, weird */ 943 /* offsets are, hmm, weird */
913 tileoffset = ((pbox[i].y1 >> 4) * depthpixperline + pbox[i].x1) >> 6; 944 tileoffset =
914 nrtilesx = ((pbox[i].x2 & ~63) - (pbox[i].x1 & ~63)) >> 4; 945 ((pbox[i].y1 >> 4) * depthpixperline +
915 nrtilesy = (pbox[i].y2 >> 4) - (pbox[i].y1 >> 4); 946 pbox[i].x1) >> 6;
947 nrtilesx =
948 ((pbox[i].x2 & ~63) -
949 (pbox[i].x1 & ~63)) >> 4;
950 nrtilesy =
951 (pbox[i].y2 >> 4) - (pbox[i].y1 >> 4);
916 for (j = 0; j <= nrtilesy; j++) { 952 for (j = 0; j <= nrtilesy; j++) {
917 BEGIN_RING( 4 ); 953 BEGIN_RING(4);
918 OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) ); 954 OUT_RING(CP_PACKET3
919 OUT_RING( tileoffset * 128 ); 955 (RADEON_3D_CLEAR_ZMASK, 2));
956 OUT_RING(tileoffset * 128);
920 /* the number of tiles to clear */ 957 /* the number of tiles to clear */
921 OUT_RING( nrtilesx + 4 ); 958 OUT_RING(nrtilesx + 4);
922 /* clear mask : chooses the clearing pattern. */ 959 /* clear mask : chooses the clearing pattern. */
923 OUT_RING( clearmask ); 960 OUT_RING(clearmask);
924 ADVANCE_RING(); 961 ADVANCE_RING();
925 tileoffset += depthpixperline >> 6; 962 tileoffset += depthpixperline >> 6;
926 } 963 }
@@ -928,18 +965,19 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
928 } 965 }
929 966
930 /* TODO don't always clear all hi-level z tiles */ 967 /* TODO don't always clear all hi-level z tiles */
931 if ((dev_priv->flags & CHIP_HAS_HIERZ) && (dev_priv->microcode_version==UCODE_R200) 968 if ((dev_priv->flags & CHIP_HAS_HIERZ)
932 && (flags & RADEON_USE_HIERZ)) 969 && (dev_priv->microcode_version == UCODE_R200)
933 /* r100 and cards without hierarchical z-buffer have no high-level z-buffer */ 970 && (flags & RADEON_USE_HIERZ))
934 /* FIXME : the mask supposedly contains low-res z values. So can't set 971 /* r100 and cards without hierarchical z-buffer have no high-level z-buffer */
935 just to the max (0xff? or actually 0x3fff?), need to take z clear 972 /* FIXME : the mask supposedly contains low-res z values. So can't set
936 value into account? */ 973 just to the max (0xff? or actually 0x3fff?), need to take z clear
974 value into account? */
937 { 975 {
938 BEGIN_RING( 4 ); 976 BEGIN_RING(4);
939 OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_HIZ, 2 ) ); 977 OUT_RING(CP_PACKET3(RADEON_3D_CLEAR_HIZ, 2));
940 OUT_RING( 0x0 ); /* First tile */ 978 OUT_RING(0x0); /* First tile */
941 OUT_RING( 0x3cc0 ); 979 OUT_RING(0x3cc0);
942 OUT_RING( (0xff<<22)|(0xff<<6)| 0x003f003f); 980 OUT_RING((0xff << 22) | (0xff << 6) | 0x003f003f);
943 ADVANCE_RING(); 981 ADVANCE_RING();
944 } 982 }
945 } 983 }
@@ -974,30 +1012,27 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
974 1012
975 tempSE_CNTL = depth_clear->se_cntl; 1013 tempSE_CNTL = depth_clear->se_cntl;
976 1014
977
978
979 /* Disable TCL */ 1015 /* Disable TCL */
980 1016
981 tempSE_VAP_CNTL = (/* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */ 1017 tempSE_VAP_CNTL = ( /* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */
982 (0x9 << SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT)); 1018 (0x9 <<
1019 SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT));
983 1020
984 tempRB3D_PLANEMASK = 0x0; 1021 tempRB3D_PLANEMASK = 0x0;
985 1022
986 tempRE_AUX_SCISSOR_CNTL = 0x0; 1023 tempRE_AUX_SCISSOR_CNTL = 0x0;
987 1024
988 tempSE_VTE_CNTL = 1025 tempSE_VTE_CNTL =
989 SE_VTE_CNTL__VTX_XY_FMT_MASK | 1026 SE_VTE_CNTL__VTX_XY_FMT_MASK | SE_VTE_CNTL__VTX_Z_FMT_MASK;
990 SE_VTE_CNTL__VTX_Z_FMT_MASK;
991 1027
992 /* Vertex format (X, Y, Z, W)*/ 1028 /* Vertex format (X, Y, Z, W) */
993 tempSE_VTX_FMT_0 = 1029 tempSE_VTX_FMT_0 =
994 SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK | 1030 SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK |
995 SE_VTX_FMT_0__VTX_W0_PRESENT_MASK; 1031 SE_VTX_FMT_0__VTX_W0_PRESENT_MASK;
996 tempSE_VTX_FMT_1 = 0x0; 1032 tempSE_VTX_FMT_1 = 0x0;
997 1033
998 1034 /*
999 /* 1035 * Depth buffer specific enables
1000 * Depth buffer specific enables
1001 */ 1036 */
1002 if (flags & RADEON_DEPTH) { 1037 if (flags & RADEON_DEPTH) {
1003 /* Enable depth buffer */ 1038 /* Enable depth buffer */
@@ -1007,12 +1042,12 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
1007 tempRB3D_CNTL &= ~RADEON_Z_ENABLE; 1042 tempRB3D_CNTL &= ~RADEON_Z_ENABLE;
1008 } 1043 }
1009 1044
1010 /* 1045 /*
1011 * Stencil buffer specific enables 1046 * Stencil buffer specific enables
1012 */ 1047 */
1013 if ( flags & RADEON_STENCIL ) { 1048 if (flags & RADEON_STENCIL) {
1014 tempRB3D_CNTL |= RADEON_STENCIL_ENABLE; 1049 tempRB3D_CNTL |= RADEON_STENCIL_ENABLE;
1015 tempRB3D_STENCILREFMASK = clear->depth_mask; 1050 tempRB3D_STENCILREFMASK = clear->depth_mask;
1016 } else { 1051 } else {
1017 tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE; 1052 tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE;
1018 tempRB3D_STENCILREFMASK = 0x00000000; 1053 tempRB3D_STENCILREFMASK = 0x00000000;
@@ -1020,79 +1055,75 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
1020 1055
1021 if (flags & RADEON_USE_COMP_ZBUF) { 1056 if (flags & RADEON_USE_COMP_ZBUF) {
1022 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE | 1057 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
1023 RADEON_Z_DECOMPRESSION_ENABLE; 1058 RADEON_Z_DECOMPRESSION_ENABLE;
1024 } 1059 }
1025 if (flags & RADEON_USE_HIERZ) { 1060 if (flags & RADEON_USE_HIERZ) {
1026 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE; 1061 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
1027 } 1062 }
1028 1063
1029 BEGIN_RING( 26 ); 1064 BEGIN_RING(26);
1030 RADEON_WAIT_UNTIL_2D_IDLE(); 1065 RADEON_WAIT_UNTIL_2D_IDLE();
1031 1066
1032 OUT_RING_REG( RADEON_PP_CNTL, tempPP_CNTL ); 1067 OUT_RING_REG(RADEON_PP_CNTL, tempPP_CNTL);
1033 OUT_RING_REG( R200_RE_CNTL, tempRE_CNTL ); 1068 OUT_RING_REG(R200_RE_CNTL, tempRE_CNTL);
1034 OUT_RING_REG( RADEON_RB3D_CNTL, tempRB3D_CNTL ); 1069 OUT_RING_REG(RADEON_RB3D_CNTL, tempRB3D_CNTL);
1035 OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL, 1070 OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
1036 tempRB3D_ZSTENCILCNTL ); 1071 OUT_RING_REG(RADEON_RB3D_STENCILREFMASK,
1037 OUT_RING_REG( RADEON_RB3D_STENCILREFMASK, 1072 tempRB3D_STENCILREFMASK);
1038 tempRB3D_STENCILREFMASK ); 1073 OUT_RING_REG(RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK);
1039 OUT_RING_REG( RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK ); 1074 OUT_RING_REG(RADEON_SE_CNTL, tempSE_CNTL);
1040 OUT_RING_REG( RADEON_SE_CNTL, tempSE_CNTL ); 1075 OUT_RING_REG(R200_SE_VTE_CNTL, tempSE_VTE_CNTL);
1041 OUT_RING_REG( R200_SE_VTE_CNTL, tempSE_VTE_CNTL ); 1076 OUT_RING_REG(R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0);
1042 OUT_RING_REG( R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0 ); 1077 OUT_RING_REG(R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1);
1043 OUT_RING_REG( R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1 ); 1078 OUT_RING_REG(R200_SE_VAP_CNTL, tempSE_VAP_CNTL);
1044 OUT_RING_REG( R200_SE_VAP_CNTL, tempSE_VAP_CNTL ); 1079 OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, tempRE_AUX_SCISSOR_CNTL);
1045 OUT_RING_REG( R200_RE_AUX_SCISSOR_CNTL,
1046 tempRE_AUX_SCISSOR_CNTL );
1047 ADVANCE_RING(); 1080 ADVANCE_RING();
1048 1081
1049 /* Make sure we restore the 3D state next time. 1082 /* Make sure we restore the 3D state next time.
1050 */ 1083 */
1051 dev_priv->sarea_priv->ctx_owner = 0; 1084 dev_priv->sarea_priv->ctx_owner = 0;
1052 1085
1053 for ( i = 0 ; i < nbox ; i++ ) { 1086 for (i = 0; i < nbox; i++) {
1054 1087
1055 /* Funny that this should be required -- 1088 /* Funny that this should be required --
1056 * sets top-left? 1089 * sets top-left?
1057 */ 1090 */
1058 radeon_emit_clip_rect( dev_priv, 1091 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1059 &sarea_priv->boxes[i] ); 1092
1060 1093 BEGIN_RING(14);
1061 BEGIN_RING( 14 ); 1094 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12));
1062 OUT_RING( CP_PACKET3( R200_3D_DRAW_IMMD_2, 12 ) ); 1095 OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
1063 OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST | 1096 RADEON_PRIM_WALK_RING |
1064 RADEON_PRIM_WALK_RING | 1097 (3 << RADEON_NUM_VERTICES_SHIFT)));
1065 (3 << RADEON_NUM_VERTICES_SHIFT)) ); 1098 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1066 OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); 1099 OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
1067 OUT_RING( depth_boxes[i].ui[CLEAR_Y1] ); 1100 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1068 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); 1101 OUT_RING(0x3f800000);
1069 OUT_RING( 0x3f800000 ); 1102 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1070 OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); 1103 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1071 OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); 1104 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1072 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); 1105 OUT_RING(0x3f800000);
1073 OUT_RING( 0x3f800000 ); 1106 OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
1074 OUT_RING( depth_boxes[i].ui[CLEAR_X2] ); 1107 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1075 OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); 1108 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1076 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); 1109 OUT_RING(0x3f800000);
1077 OUT_RING( 0x3f800000 );
1078 ADVANCE_RING(); 1110 ADVANCE_RING();
1079 } 1111 }
1080 } 1112 } else if ((flags & (RADEON_DEPTH | RADEON_STENCIL))) {
1081 else if ( (flags & (RADEON_DEPTH | RADEON_STENCIL)) ) {
1082 1113
1083 int tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl; 1114 int tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
1084 1115
1085 rb3d_cntl = depth_clear->rb3d_cntl; 1116 rb3d_cntl = depth_clear->rb3d_cntl;
1086 1117
1087 if ( flags & RADEON_DEPTH ) { 1118 if (flags & RADEON_DEPTH) {
1088 rb3d_cntl |= RADEON_Z_ENABLE; 1119 rb3d_cntl |= RADEON_Z_ENABLE;
1089 } else { 1120 } else {
1090 rb3d_cntl &= ~RADEON_Z_ENABLE; 1121 rb3d_cntl &= ~RADEON_Z_ENABLE;
1091 } 1122 }
1092 1123
1093 if ( flags & RADEON_STENCIL ) { 1124 if (flags & RADEON_STENCIL) {
1094 rb3d_cntl |= RADEON_STENCIL_ENABLE; 1125 rb3d_cntl |= RADEON_STENCIL_ENABLE;
1095 rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */ 1126 rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */
1096 } else { 1127 } else {
1097 rb3d_cntl &= ~RADEON_STENCIL_ENABLE; 1128 rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
1098 rb3d_stencilrefmask = 0x00000000; 1129 rb3d_stencilrefmask = 0x00000000;
@@ -1100,66 +1131,61 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
1100 1131
1101 if (flags & RADEON_USE_COMP_ZBUF) { 1132 if (flags & RADEON_USE_COMP_ZBUF) {
1102 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE | 1133 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
1103 RADEON_Z_DECOMPRESSION_ENABLE; 1134 RADEON_Z_DECOMPRESSION_ENABLE;
1104 } 1135 }
1105 if (flags & RADEON_USE_HIERZ) { 1136 if (flags & RADEON_USE_HIERZ) {
1106 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE; 1137 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
1107 } 1138 }
1108 1139
1109 BEGIN_RING( 13 ); 1140 BEGIN_RING(13);
1110 RADEON_WAIT_UNTIL_2D_IDLE(); 1141 RADEON_WAIT_UNTIL_2D_IDLE();
1111 1142
1112 OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) ); 1143 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 1));
1113 OUT_RING( 0x00000000 ); 1144 OUT_RING(0x00000000);
1114 OUT_RING( rb3d_cntl ); 1145 OUT_RING(rb3d_cntl);
1115 1146
1116 OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL ); 1147 OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
1117 OUT_RING_REG( RADEON_RB3D_STENCILREFMASK, 1148 OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, rb3d_stencilrefmask);
1118 rb3d_stencilrefmask ); 1149 OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0x00000000);
1119 OUT_RING_REG( RADEON_RB3D_PLANEMASK, 1150 OUT_RING_REG(RADEON_SE_CNTL, depth_clear->se_cntl);
1120 0x00000000 );
1121 OUT_RING_REG( RADEON_SE_CNTL,
1122 depth_clear->se_cntl );
1123 ADVANCE_RING(); 1151 ADVANCE_RING();
1124 1152
1125 /* Make sure we restore the 3D state next time. 1153 /* Make sure we restore the 3D state next time.
1126 */ 1154 */
1127 dev_priv->sarea_priv->ctx_owner = 0; 1155 dev_priv->sarea_priv->ctx_owner = 0;
1128 1156
1129 for ( i = 0 ; i < nbox ; i++ ) { 1157 for (i = 0; i < nbox; i++) {
1130 1158
1131 /* Funny that this should be required -- 1159 /* Funny that this should be required --
1132 * sets top-left? 1160 * sets top-left?
1133 */ 1161 */
1134 radeon_emit_clip_rect( dev_priv, 1162 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1135 &sarea_priv->boxes[i] ); 1163
1136 1164 BEGIN_RING(15);
1137 BEGIN_RING( 15 ); 1165
1138 1166 OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13));
1139 OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 13 ) ); 1167 OUT_RING(RADEON_VTX_Z_PRESENT |
1140 OUT_RING( RADEON_VTX_Z_PRESENT | 1168 RADEON_VTX_PKCOLOR_PRESENT);
1141 RADEON_VTX_PKCOLOR_PRESENT); 1169 OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
1142 OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST | 1170 RADEON_PRIM_WALK_RING |
1143 RADEON_PRIM_WALK_RING | 1171 RADEON_MAOS_ENABLE |
1144 RADEON_MAOS_ENABLE | 1172 RADEON_VTX_FMT_RADEON_MODE |
1145 RADEON_VTX_FMT_RADEON_MODE | 1173 (3 << RADEON_NUM_VERTICES_SHIFT)));
1146 (3 << RADEON_NUM_VERTICES_SHIFT)) ); 1174
1147 1175 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1148 1176 OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
1149 OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); 1177 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1150 OUT_RING( depth_boxes[i].ui[CLEAR_Y1] ); 1178 OUT_RING(0x0);
1151 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); 1179
1152 OUT_RING( 0x0 ); 1180 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1153 1181 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1154 OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); 1182 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1155 OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); 1183 OUT_RING(0x0);
1156 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); 1184
1157 OUT_RING( 0x0 ); 1185 OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
1158 1186 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1159 OUT_RING( depth_boxes[i].ui[CLEAR_X2] ); 1187 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1160 OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); 1188 OUT_RING(0x0);
1161 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
1162 OUT_RING( 0x0 );
1163 1189
1164 ADVANCE_RING(); 1190 ADVANCE_RING();
1165 } 1191 }
@@ -1171,15 +1197,15 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev,
1171 */ 1197 */
1172 dev_priv->sarea_priv->last_clear++; 1198 dev_priv->sarea_priv->last_clear++;
1173 1199
1174 BEGIN_RING( 4 ); 1200 BEGIN_RING(4);
1175 1201
1176 RADEON_CLEAR_AGE( dev_priv->sarea_priv->last_clear ); 1202 RADEON_CLEAR_AGE(dev_priv->sarea_priv->last_clear);
1177 RADEON_WAIT_UNTIL_IDLE(); 1203 RADEON_WAIT_UNTIL_IDLE();
1178 1204
1179 ADVANCE_RING(); 1205 ADVANCE_RING();
1180} 1206}
1181 1207
1182static void radeon_cp_dispatch_swap( drm_device_t *dev ) 1208static void radeon_cp_dispatch_swap(drm_device_t * dev)
1183{ 1209{
1184 drm_radeon_private_t *dev_priv = dev->dev_private; 1210 drm_radeon_private_t *dev_priv = dev->dev_private;
1185 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; 1211 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -1187,59 +1213,55 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev )
1187 drm_clip_rect_t *pbox = sarea_priv->boxes; 1213 drm_clip_rect_t *pbox = sarea_priv->boxes;
1188 int i; 1214 int i;
1189 RING_LOCALS; 1215 RING_LOCALS;
1190 DRM_DEBUG( "\n" ); 1216 DRM_DEBUG("\n");
1191 1217
1192 /* Do some trivial performance monitoring... 1218 /* Do some trivial performance monitoring...
1193 */ 1219 */
1194 if (dev_priv->do_boxes) 1220 if (dev_priv->do_boxes)
1195 radeon_cp_performance_boxes( dev_priv ); 1221 radeon_cp_performance_boxes(dev_priv);
1196
1197 1222
1198 /* Wait for the 3D stream to idle before dispatching the bitblt. 1223 /* Wait for the 3D stream to idle before dispatching the bitblt.
1199 * This will prevent data corruption between the two streams. 1224 * This will prevent data corruption between the two streams.
1200 */ 1225 */
1201 BEGIN_RING( 2 ); 1226 BEGIN_RING(2);
1202 1227
1203 RADEON_WAIT_UNTIL_3D_IDLE(); 1228 RADEON_WAIT_UNTIL_3D_IDLE();
1204 1229
1205 ADVANCE_RING(); 1230 ADVANCE_RING();
1206 1231
1207 for ( i = 0 ; i < nbox ; i++ ) { 1232 for (i = 0; i < nbox; i++) {
1208 int x = pbox[i].x1; 1233 int x = pbox[i].x1;
1209 int y = pbox[i].y1; 1234 int y = pbox[i].y1;
1210 int w = pbox[i].x2 - x; 1235 int w = pbox[i].x2 - x;
1211 int h = pbox[i].y2 - y; 1236 int h = pbox[i].y2 - y;
1212 1237
1213 DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n", 1238 DRM_DEBUG("dispatch swap %d,%d-%d,%d\n", x, y, w, h);
1214 x, y, w, h ); 1239
1215 1240 BEGIN_RING(7);
1216 BEGIN_RING( 7 ); 1241
1217 1242 OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5));
1218 OUT_RING( CP_PACKET3( RADEON_CNTL_BITBLT_MULTI, 5 ) ); 1243 OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
1219 OUT_RING( RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 1244 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1220 RADEON_GMC_DST_PITCH_OFFSET_CNTL | 1245 RADEON_GMC_BRUSH_NONE |
1221 RADEON_GMC_BRUSH_NONE | 1246 (dev_priv->color_fmt << 8) |
1222 (dev_priv->color_fmt << 8) | 1247 RADEON_GMC_SRC_DATATYPE_COLOR |
1223 RADEON_GMC_SRC_DATATYPE_COLOR | 1248 RADEON_ROP3_S |
1224 RADEON_ROP3_S | 1249 RADEON_DP_SRC_SOURCE_MEMORY |
1225 RADEON_DP_SRC_SOURCE_MEMORY | 1250 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
1226 RADEON_GMC_CLR_CMP_CNTL_DIS | 1251
1227 RADEON_GMC_WR_MSK_DIS );
1228
1229 /* Make this work even if front & back are flipped: 1252 /* Make this work even if front & back are flipped:
1230 */ 1253 */
1231 if (dev_priv->current_page == 0) { 1254 if (dev_priv->current_page == 0) {
1232 OUT_RING( dev_priv->back_pitch_offset ); 1255 OUT_RING(dev_priv->back_pitch_offset);
1233 OUT_RING( dev_priv->front_pitch_offset ); 1256 OUT_RING(dev_priv->front_pitch_offset);
1234 } 1257 } else {
1235 else { 1258 OUT_RING(dev_priv->front_pitch_offset);
1236 OUT_RING( dev_priv->front_pitch_offset ); 1259 OUT_RING(dev_priv->back_pitch_offset);
1237 OUT_RING( dev_priv->back_pitch_offset );
1238 } 1260 }
1239 1261
1240 OUT_RING( (x << 16) | y ); 1262 OUT_RING((x << 16) | y);
1241 OUT_RING( (x << 16) | y ); 1263 OUT_RING((x << 16) | y);
1242 OUT_RING( (w << 16) | h ); 1264 OUT_RING((w << 16) | h);
1243 1265
1244 ADVANCE_RING(); 1266 ADVANCE_RING();
1245 } 1267 }
@@ -1250,44 +1272,43 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev )
1250 */ 1272 */
1251 dev_priv->sarea_priv->last_frame++; 1273 dev_priv->sarea_priv->last_frame++;
1252 1274
1253 BEGIN_RING( 4 ); 1275 BEGIN_RING(4);
1254 1276
1255 RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame ); 1277 RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
1256 RADEON_WAIT_UNTIL_2D_IDLE(); 1278 RADEON_WAIT_UNTIL_2D_IDLE();
1257 1279
1258 ADVANCE_RING(); 1280 ADVANCE_RING();
1259} 1281}
1260 1282
1261static void radeon_cp_dispatch_flip( drm_device_t *dev ) 1283static void radeon_cp_dispatch_flip(drm_device_t * dev)
1262{ 1284{
1263 drm_radeon_private_t *dev_priv = dev->dev_private; 1285 drm_radeon_private_t *dev_priv = dev->dev_private;
1264 drm_sarea_t *sarea = (drm_sarea_t *)dev_priv->sarea->handle; 1286 drm_sarea_t *sarea = (drm_sarea_t *) dev_priv->sarea->handle;
1265 int offset = (dev_priv->current_page == 1) 1287 int offset = (dev_priv->current_page == 1)
1266 ? dev_priv->front_offset : dev_priv->back_offset; 1288 ? dev_priv->front_offset : dev_priv->back_offset;
1267 RING_LOCALS; 1289 RING_LOCALS;
1268 DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n", 1290 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
1269 __FUNCTION__, 1291 __FUNCTION__,
1270 dev_priv->current_page, 1292 dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage);
1271 dev_priv->sarea_priv->pfCurrentPage);
1272 1293
1273 /* Do some trivial performance monitoring... 1294 /* Do some trivial performance monitoring...
1274 */ 1295 */
1275 if (dev_priv->do_boxes) { 1296 if (dev_priv->do_boxes) {
1276 dev_priv->stats.boxes |= RADEON_BOX_FLIP; 1297 dev_priv->stats.boxes |= RADEON_BOX_FLIP;
1277 radeon_cp_performance_boxes( dev_priv ); 1298 radeon_cp_performance_boxes(dev_priv);
1278 } 1299 }
1279 1300
1280 /* Update the frame offsets for both CRTCs 1301 /* Update the frame offsets for both CRTCs
1281 */ 1302 */
1282 BEGIN_RING( 6 ); 1303 BEGIN_RING(6);
1283 1304
1284 RADEON_WAIT_UNTIL_3D_IDLE(); 1305 RADEON_WAIT_UNTIL_3D_IDLE();
1285 OUT_RING_REG( RADEON_CRTC_OFFSET, ( ( sarea->frame.y * dev_priv->front_pitch 1306 OUT_RING_REG(RADEON_CRTC_OFFSET,
1286 + sarea->frame.x 1307 ((sarea->frame.y * dev_priv->front_pitch +
1287 * ( dev_priv->color_fmt - 2 ) ) & ~7 ) 1308 sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7)
1288 + offset ); 1309 + offset);
1289 OUT_RING_REG( RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base 1310 OUT_RING_REG(RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base
1290 + offset ); 1311 + offset);
1291 1312
1292 ADVANCE_RING(); 1313 ADVANCE_RING();
1293 1314
@@ -1297,16 +1318,16 @@ static void radeon_cp_dispatch_flip( drm_device_t *dev )
1297 */ 1318 */
1298 dev_priv->sarea_priv->last_frame++; 1319 dev_priv->sarea_priv->last_frame++;
1299 dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page = 1320 dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
1300 1 - dev_priv->current_page; 1321 1 - dev_priv->current_page;
1301 1322
1302 BEGIN_RING( 2 ); 1323 BEGIN_RING(2);
1303 1324
1304 RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame ); 1325 RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
1305 1326
1306 ADVANCE_RING(); 1327 ADVANCE_RING();
1307} 1328}
1308 1329
1309static int bad_prim_vertex_nr( int primitive, int nr ) 1330static int bad_prim_vertex_nr(int primitive, int nr)
1310{ 1331{
1311 switch (primitive & RADEON_PRIM_TYPE_MASK) { 1332 switch (primitive & RADEON_PRIM_TYPE_MASK) {
1312 case RADEON_PRIM_TYPE_NONE: 1333 case RADEON_PRIM_TYPE_NONE:
@@ -1326,24 +1347,21 @@ static int bad_prim_vertex_nr( int primitive, int nr )
1326 return nr < 3; 1347 return nr < 3;
1327 default: 1348 default:
1328 return 1; 1349 return 1;
1329 } 1350 }
1330} 1351}
1331 1352
1332
1333
1334typedef struct { 1353typedef struct {
1335 unsigned int start; 1354 unsigned int start;
1336 unsigned int finish; 1355 unsigned int finish;
1337 unsigned int prim; 1356 unsigned int prim;
1338 unsigned int numverts; 1357 unsigned int numverts;
1339 unsigned int offset; 1358 unsigned int offset;
1340 unsigned int vc_format; 1359 unsigned int vc_format;
1341} drm_radeon_tcl_prim_t; 1360} drm_radeon_tcl_prim_t;
1342 1361
1343static void radeon_cp_dispatch_vertex( drm_device_t *dev, 1362static void radeon_cp_dispatch_vertex(drm_device_t * dev,
1344 drm_buf_t *buf, 1363 drm_buf_t * buf,
1345 drm_radeon_tcl_prim_t *prim ) 1364 drm_radeon_tcl_prim_t * prim)
1346
1347{ 1365{
1348 drm_radeon_private_t *dev_priv = dev->dev_private; 1366 drm_radeon_private_t *dev_priv = dev->dev_private;
1349 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; 1367 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -1355,45 +1373,39 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
1355 1373
1356 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n", 1374 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n",
1357 prim->prim, 1375 prim->prim,
1358 prim->vc_format, 1376 prim->vc_format, prim->start, prim->finish, prim->numverts);
1359 prim->start,
1360 prim->finish,
1361 prim->numverts);
1362 1377
1363 if (bad_prim_vertex_nr( prim->prim, prim->numverts )) { 1378 if (bad_prim_vertex_nr(prim->prim, prim->numverts)) {
1364 DRM_ERROR( "bad prim %x numverts %d\n", 1379 DRM_ERROR("bad prim %x numverts %d\n",
1365 prim->prim, prim->numverts ); 1380 prim->prim, prim->numverts);
1366 return; 1381 return;
1367 } 1382 }
1368 1383
1369 do { 1384 do {
1370 /* Emit the next cliprect */ 1385 /* Emit the next cliprect */
1371 if ( i < nbox ) { 1386 if (i < nbox) {
1372 radeon_emit_clip_rect( dev_priv, 1387 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1373 &sarea_priv->boxes[i] );
1374 } 1388 }
1375 1389
1376 /* Emit the vertex buffer rendering commands */ 1390 /* Emit the vertex buffer rendering commands */
1377 BEGIN_RING( 5 ); 1391 BEGIN_RING(5);
1378 1392
1379 OUT_RING( CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, 3 ) ); 1393 OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, 3));
1380 OUT_RING( offset ); 1394 OUT_RING(offset);
1381 OUT_RING( numverts ); 1395 OUT_RING(numverts);
1382 OUT_RING( prim->vc_format ); 1396 OUT_RING(prim->vc_format);
1383 OUT_RING( prim->prim | RADEON_PRIM_WALK_LIST | 1397 OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST |
1384 RADEON_COLOR_ORDER_RGBA | 1398 RADEON_COLOR_ORDER_RGBA |
1385 RADEON_VTX_FMT_RADEON_MODE | 1399 RADEON_VTX_FMT_RADEON_MODE |
1386 (numverts << RADEON_NUM_VERTICES_SHIFT) ); 1400 (numverts << RADEON_NUM_VERTICES_SHIFT));
1387 1401
1388 ADVANCE_RING(); 1402 ADVANCE_RING();
1389 1403
1390 i++; 1404 i++;
1391 } while ( i < nbox ); 1405 } while (i < nbox);
1392} 1406}
1393 1407
1394 1408static void radeon_cp_discard_buffer(drm_device_t * dev, drm_buf_t * buf)
1395
1396static void radeon_cp_discard_buffer( drm_device_t *dev, drm_buf_t *buf )
1397{ 1409{
1398 drm_radeon_private_t *dev_priv = dev->dev_private; 1410 drm_radeon_private_t *dev_priv = dev->dev_private;
1399 drm_radeon_buf_priv_t *buf_priv = buf->dev_private; 1411 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
@@ -1402,24 +1414,22 @@ static void radeon_cp_discard_buffer( drm_device_t *dev, drm_buf_t *buf )
1402 buf_priv->age = ++dev_priv->sarea_priv->last_dispatch; 1414 buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
1403 1415
1404 /* Emit the vertex buffer age */ 1416 /* Emit the vertex buffer age */
1405 BEGIN_RING( 2 ); 1417 BEGIN_RING(2);
1406 RADEON_DISPATCH_AGE( buf_priv->age ); 1418 RADEON_DISPATCH_AGE(buf_priv->age);
1407 ADVANCE_RING(); 1419 ADVANCE_RING();
1408 1420
1409 buf->pending = 1; 1421 buf->pending = 1;
1410 buf->used = 0; 1422 buf->used = 0;
1411} 1423}
1412 1424
1413static void radeon_cp_dispatch_indirect( drm_device_t *dev, 1425static void radeon_cp_dispatch_indirect(drm_device_t * dev,
1414 drm_buf_t *buf, 1426 drm_buf_t * buf, int start, int end)
1415 int start, int end )
1416{ 1427{
1417 drm_radeon_private_t *dev_priv = dev->dev_private; 1428 drm_radeon_private_t *dev_priv = dev->dev_private;
1418 RING_LOCALS; 1429 RING_LOCALS;
1419 DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n", 1430 DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end);
1420 buf->idx, start, end );
1421 1431
1422 if ( start != end ) { 1432 if (start != end) {
1423 int offset = (dev_priv->gart_buffers_offset 1433 int offset = (dev_priv->gart_buffers_offset
1424 + buf->offset + start); 1434 + buf->offset + start);
1425 int dwords = (end - start + 3) / sizeof(u32); 1435 int dwords = (end - start + 3) / sizeof(u32);
@@ -1428,28 +1438,27 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev,
1428 * dwords, so if we've been given an odd number we must 1438 * dwords, so if we've been given an odd number we must
1429 * pad the data with a Type-2 CP packet. 1439 * pad the data with a Type-2 CP packet.
1430 */ 1440 */
1431 if ( dwords & 1 ) { 1441 if (dwords & 1) {
1432 u32 *data = (u32 *) 1442 u32 *data = (u32 *)
1433 ((char *)dev->agp_buffer_map->handle 1443 ((char *)dev->agp_buffer_map->handle
1434 + buf->offset + start); 1444 + buf->offset + start);
1435 data[dwords++] = RADEON_CP_PACKET2; 1445 data[dwords++] = RADEON_CP_PACKET2;
1436 } 1446 }
1437 1447
1438 /* Fire off the indirect buffer */ 1448 /* Fire off the indirect buffer */
1439 BEGIN_RING( 3 ); 1449 BEGIN_RING(3);
1440 1450
1441 OUT_RING( CP_PACKET0( RADEON_CP_IB_BASE, 1 ) ); 1451 OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
1442 OUT_RING( offset ); 1452 OUT_RING(offset);
1443 OUT_RING( dwords ); 1453 OUT_RING(dwords);
1444 1454
1445 ADVANCE_RING(); 1455 ADVANCE_RING();
1446 } 1456 }
1447} 1457}
1448 1458
1449 1459static void radeon_cp_dispatch_indices(drm_device_t * dev,
1450static void radeon_cp_dispatch_indices( drm_device_t *dev, 1460 drm_buf_t * elt_buf,
1451 drm_buf_t *elt_buf, 1461 drm_radeon_tcl_prim_t * prim)
1452 drm_radeon_tcl_prim_t *prim )
1453{ 1462{
1454 drm_radeon_private_t *dev_priv = dev->dev_private; 1463 drm_radeon_private_t *dev_priv = dev->dev_private;
1455 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; 1464 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -1464,30 +1473,24 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
1464 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n", 1473 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
1465 prim->prim, 1474 prim->prim,
1466 prim->vc_format, 1475 prim->vc_format,
1467 prim->start, 1476 prim->start, prim->finish, prim->offset, prim->numverts);
1468 prim->finish, 1477
1469 prim->offset, 1478 if (bad_prim_vertex_nr(prim->prim, count)) {
1470 prim->numverts); 1479 DRM_ERROR("bad prim %x count %d\n", prim->prim, count);
1471
1472 if (bad_prim_vertex_nr( prim->prim, count )) {
1473 DRM_ERROR( "bad prim %x count %d\n",
1474 prim->prim, count );
1475 return; 1480 return;
1476 } 1481 }
1477 1482
1478 1483 if (start >= prim->finish || (prim->start & 0x7)) {
1479 if ( start >= prim->finish || 1484 DRM_ERROR("buffer prim %d\n", prim->prim);
1480 (prim->start & 0x7) ) {
1481 DRM_ERROR( "buffer prim %d\n", prim->prim );
1482 return; 1485 return;
1483 } 1486 }
1484 1487
1485 dwords = (prim->finish - prim->start + 3) / sizeof(u32); 1488 dwords = (prim->finish - prim->start + 3) / sizeof(u32);
1486 1489
1487 data = (u32 *)((char *)dev->agp_buffer_map->handle + 1490 data = (u32 *) ((char *)dev->agp_buffer_map->handle +
1488 elt_buf->offset + prim->start); 1491 elt_buf->offset + prim->start);
1489 1492
1490 data[0] = CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 ); 1493 data[0] = CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, dwords - 2);
1491 data[1] = offset; 1494 data[1] = offset;
1492 data[2] = prim->numverts; 1495 data[2] = prim->numverts;
1493 data[3] = prim->vc_format; 1496 data[3] = prim->vc_format;
@@ -1495,28 +1498,26 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
1495 RADEON_PRIM_WALK_IND | 1498 RADEON_PRIM_WALK_IND |
1496 RADEON_COLOR_ORDER_RGBA | 1499 RADEON_COLOR_ORDER_RGBA |
1497 RADEON_VTX_FMT_RADEON_MODE | 1500 RADEON_VTX_FMT_RADEON_MODE |
1498 (count << RADEON_NUM_VERTICES_SHIFT) ); 1501 (count << RADEON_NUM_VERTICES_SHIFT));
1499 1502
1500 do { 1503 do {
1501 if ( i < nbox ) 1504 if (i < nbox)
1502 radeon_emit_clip_rect( dev_priv, 1505 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1503 &sarea_priv->boxes[i] );
1504 1506
1505 radeon_cp_dispatch_indirect( dev, elt_buf, 1507 radeon_cp_dispatch_indirect(dev, elt_buf,
1506 prim->start, 1508 prim->start, prim->finish);
1507 prim->finish );
1508 1509
1509 i++; 1510 i++;
1510 } while ( i < nbox ); 1511 } while (i < nbox);
1511 1512
1512} 1513}
1513 1514
1514#define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE 1515#define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE
1515 1516
1516static int radeon_cp_dispatch_texture( DRMFILE filp, 1517static int radeon_cp_dispatch_texture(DRMFILE filp,
1517 drm_device_t *dev, 1518 drm_device_t * dev,
1518 drm_radeon_texture_t *tex, 1519 drm_radeon_texture_t * tex,
1519 drm_radeon_tex_image_t *image ) 1520 drm_radeon_tex_image_t * image)
1520{ 1521{
1521 drm_radeon_private_t *dev_priv = dev->dev_private; 1522 drm_radeon_private_t *dev_priv = dev->dev_private;
1522 drm_file_t *filp_priv; 1523 drm_file_t *filp_priv;
@@ -1531,11 +1532,11 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1531 u32 offset; 1532 u32 offset;
1532 RING_LOCALS; 1533 RING_LOCALS;
1533 1534
1534 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); 1535 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
1535 1536
1536 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &tex->offset ) ) { 1537 if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &tex->offset)) {
1537 DRM_ERROR( "Invalid destination offset\n" ); 1538 DRM_ERROR("Invalid destination offset\n");
1538 return DRM_ERR( EINVAL ); 1539 return DRM_ERR(EINVAL);
1539 } 1540 }
1540 1541
1541 dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD; 1542 dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD;
@@ -1544,7 +1545,7 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1544 * up with the texture data from the host data blit, otherwise 1545 * up with the texture data from the host data blit, otherwise
1545 * part of the texture image may be corrupted. 1546 * part of the texture image may be corrupted.
1546 */ 1547 */
1547 BEGIN_RING( 4 ); 1548 BEGIN_RING(4);
1548 RADEON_FLUSH_CACHE(); 1549 RADEON_FLUSH_CACHE();
1549 RADEON_WAIT_UNTIL_IDLE(); 1550 RADEON_WAIT_UNTIL_IDLE();
1550 ADVANCE_RING(); 1551 ADVANCE_RING();
@@ -1553,7 +1554,7 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1553 * even if the only legal values are powers of two. Thus, we'll 1554 * even if the only legal values are powers of two. Thus, we'll
1554 * use a shift instead. 1555 * use a shift instead.
1555 */ 1556 */
1556 switch ( tex->format ) { 1557 switch (tex->format) {
1557 case RADEON_TXFORMAT_ARGB8888: 1558 case RADEON_TXFORMAT_ARGB8888:
1558 case RADEON_TXFORMAT_RGBA8888: 1559 case RADEON_TXFORMAT_RGBA8888:
1559 format = RADEON_COLOR_FORMAT_ARGB8888; 1560 format = RADEON_COLOR_FORMAT_ARGB8888;
@@ -1577,7 +1578,7 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1577 blit_width = image->width * 1; 1578 blit_width = image->width * 1;
1578 break; 1579 break;
1579 default: 1580 default:
1580 DRM_ERROR( "invalid texture format %d\n", tex->format ); 1581 DRM_ERROR("invalid texture format %d\n", tex->format);
1581 return DRM_ERR(EINVAL); 1582 return DRM_ERR(EINVAL);
1582 } 1583 }
1583 spitch = blit_width >> 6; 1584 spitch = blit_width >> 6;
@@ -1592,49 +1593,49 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1592 /* we got tiled coordinates, untile them */ 1593 /* we got tiled coordinates, untile them */
1593 image->x *= 2; 1594 image->x *= 2;
1594 } 1595 }
1595 } 1596 } else
1596 else microtile = 0; 1597 microtile = 0;
1597 1598
1598 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width ); 1599 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
1599 1600
1600 do { 1601 do {
1601 DRM_DEBUG( "tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n", 1602 DRM_DEBUG("tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
1602 tex->offset >> 10, tex->pitch, tex->format, 1603 tex->offset >> 10, tex->pitch, tex->format,
1603 image->x, image->y, image->width, image->height ); 1604 image->x, image->y, image->width, image->height);
1604 1605
1605 /* Make a copy of some parameters in case we have to 1606 /* Make a copy of some parameters in case we have to
1606 * update them for a multi-pass texture blit. 1607 * update them for a multi-pass texture blit.
1607 */ 1608 */
1608 height = image->height; 1609 height = image->height;
1609 data = (const u8 __user *)image->data; 1610 data = (const u8 __user *)image->data;
1610 1611
1611 size = height * blit_width; 1612 size = height * blit_width;
1612 1613
1613 if ( size > RADEON_MAX_TEXTURE_SIZE ) { 1614 if (size > RADEON_MAX_TEXTURE_SIZE) {
1614 height = RADEON_MAX_TEXTURE_SIZE / blit_width; 1615 height = RADEON_MAX_TEXTURE_SIZE / blit_width;
1615 size = height * blit_width; 1616 size = height * blit_width;
1616 } else if ( size < 4 && size > 0 ) { 1617 } else if (size < 4 && size > 0) {
1617 size = 4; 1618 size = 4;
1618 } else if ( size == 0 ) { 1619 } else if (size == 0) {
1619 return 0; 1620 return 0;
1620 } 1621 }
1621 1622
1622 buf = radeon_freelist_get( dev ); 1623 buf = radeon_freelist_get(dev);
1623 if ( 0 && !buf ) { 1624 if (0 && !buf) {
1624 radeon_do_cp_idle( dev_priv ); 1625 radeon_do_cp_idle(dev_priv);
1625 buf = radeon_freelist_get( dev ); 1626 buf = radeon_freelist_get(dev);
1626 } 1627 }
1627 if ( !buf ) { 1628 if (!buf) {
1628 DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n"); 1629 DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n");
1629 if (DRM_COPY_TO_USER( tex->image, image, sizeof(*image) )) 1630 if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image)))
1630 return DRM_ERR(EFAULT); 1631 return DRM_ERR(EFAULT);
1631 return DRM_ERR(EAGAIN); 1632 return DRM_ERR(EAGAIN);
1632 } 1633 }
1633 1634
1634
1635 /* Dispatch the indirect buffer. 1635 /* Dispatch the indirect buffer.
1636 */ 1636 */
1637 buffer = (u32*)((char*)dev->agp_buffer_map->handle + buf->offset); 1637 buffer =
1638 (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
1638 dwords = size / 4; 1639 dwords = size / 4;
1639 1640
1640 if (microtile) { 1641 if (microtile) {
@@ -1649,20 +1650,26 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1649 if (tex->height == 1) { 1650 if (tex->height == 1) {
1650 if (tex_width >= 64 || tex_width <= 16) { 1651 if (tex_width >= 64 || tex_width <= 16) {
1651 if (DRM_COPY_FROM_USER(buffer, data, 1652 if (DRM_COPY_FROM_USER(buffer, data,
1652 tex_width * sizeof(u32))) { 1653 tex_width *
1653 DRM_ERROR("EFAULT on pad, %d bytes\n", 1654 sizeof(u32))) {
1654 tex_width); 1655 DRM_ERROR
1656 ("EFAULT on pad, %d bytes\n",
1657 tex_width);
1655 return DRM_ERR(EFAULT); 1658 return DRM_ERR(EFAULT);
1656 } 1659 }
1657 } else if (tex_width == 32) { 1660 } else if (tex_width == 32) {
1658 if (DRM_COPY_FROM_USER(buffer, data, 16)) { 1661 if (DRM_COPY_FROM_USER
1659 DRM_ERROR("EFAULT on pad, %d bytes\n", 1662 (buffer, data, 16)) {
1660 tex_width); 1663 DRM_ERROR
1664 ("EFAULT on pad, %d bytes\n",
1665 tex_width);
1661 return DRM_ERR(EFAULT); 1666 return DRM_ERR(EFAULT);
1662 } 1667 }
1663 if (DRM_COPY_FROM_USER(buffer + 8, data + 16, 16)) { 1668 if (DRM_COPY_FROM_USER
1664 DRM_ERROR("EFAULT on pad, %d bytes\n", 1669 (buffer + 8, data + 16, 16)) {
1665 tex_width); 1670 DRM_ERROR
1671 ("EFAULT on pad, %d bytes\n",
1672 tex_width);
1666 return DRM_ERR(EFAULT); 1673 return DRM_ERR(EFAULT);
1667 } 1674 }
1668 } 1675 }
@@ -1675,9 +1682,11 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1675 } 1682 }
1676 } else if (tex_width < 16) { 1683 } else if (tex_width < 16) {
1677 for (i = 0; i < tex->height; i++) { 1684 for (i = 0; i < tex->height; i++) {
1678 if (DRM_COPY_FROM_USER(buffer, data, tex_width)) { 1685 if (DRM_COPY_FROM_USER
1679 DRM_ERROR("EFAULT on pad, %d bytes\n", 1686 (buffer, data, tex_width)) {
1680 tex_width); 1687 DRM_ERROR
1688 ("EFAULT on pad, %d bytes\n",
1689 tex_width);
1681 return DRM_ERR(EFAULT); 1690 return DRM_ERR(EFAULT);
1682 } 1691 }
1683 buffer += 4; 1692 buffer += 4;
@@ -1687,35 +1696,42 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1687 /* TODO: make sure this works when not fitting in one buffer 1696 /* TODO: make sure this works when not fitting in one buffer
1688 (i.e. 32bytes x 2048...) */ 1697 (i.e. 32bytes x 2048...) */
1689 for (i = 0; i < tex->height; i += 2) { 1698 for (i = 0; i < tex->height; i += 2) {
1690 if (DRM_COPY_FROM_USER(buffer, data, 16)) { 1699 if (DRM_COPY_FROM_USER
1691 DRM_ERROR("EFAULT on pad, %d bytes\n", 1700 (buffer, data, 16)) {
1692 tex_width); 1701 DRM_ERROR
1702 ("EFAULT on pad, %d bytes\n",
1703 tex_width);
1693 return DRM_ERR(EFAULT); 1704 return DRM_ERR(EFAULT);
1694 } 1705 }
1695 data += 16; 1706 data += 16;
1696 if (DRM_COPY_FROM_USER(buffer + 8, data, 16)) { 1707 if (DRM_COPY_FROM_USER
1697 DRM_ERROR("EFAULT on pad, %d bytes\n", 1708 (buffer + 8, data, 16)) {
1698 tex_width); 1709 DRM_ERROR
1710 ("EFAULT on pad, %d bytes\n",
1711 tex_width);
1699 return DRM_ERR(EFAULT); 1712 return DRM_ERR(EFAULT);
1700 } 1713 }
1701 data += 16; 1714 data += 16;
1702 if (DRM_COPY_FROM_USER(buffer + 4, data, 16)) { 1715 if (DRM_COPY_FROM_USER
1703 DRM_ERROR("EFAULT on pad, %d bytes\n", 1716 (buffer + 4, data, 16)) {
1704 tex_width); 1717 DRM_ERROR
1718 ("EFAULT on pad, %d bytes\n",
1719 tex_width);
1705 return DRM_ERR(EFAULT); 1720 return DRM_ERR(EFAULT);
1706 } 1721 }
1707 data += 16; 1722 data += 16;
1708 if (DRM_COPY_FROM_USER(buffer + 12, data, 16)) { 1723 if (DRM_COPY_FROM_USER
1709 DRM_ERROR("EFAULT on pad, %d bytes\n", 1724 (buffer + 12, data, 16)) {
1710 tex_width); 1725 DRM_ERROR
1726 ("EFAULT on pad, %d bytes\n",
1727 tex_width);
1711 return DRM_ERR(EFAULT); 1728 return DRM_ERR(EFAULT);
1712 } 1729 }
1713 data += 16; 1730 data += 16;
1714 buffer += 16; 1731 buffer += 16;
1715 } 1732 }
1716 } 1733 }
1717 } 1734 } else {
1718 else {
1719 if (tex_width >= 32) { 1735 if (tex_width >= 32) {
1720 /* Texture image width is larger than the minimum, so we 1736 /* Texture image width is larger than the minimum, so we
1721 * can upload it directly. 1737 * can upload it directly.
@@ -1731,9 +1747,12 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1731 * need to pad out each image scanline to the minimum 1747 * need to pad out each image scanline to the minimum
1732 * width. 1748 * width.
1733 */ 1749 */
1734 for (i = 0 ; i < tex->height ; i++) { 1750 for (i = 0; i < tex->height; i++) {
1735 if (DRM_COPY_FROM_USER(buffer, data, tex_width )) { 1751 if (DRM_COPY_FROM_USER
1736 DRM_ERROR("EFAULT on pad, %d bytes\n", tex_width); 1752 (buffer, data, tex_width)) {
1753 DRM_ERROR
1754 ("EFAULT on pad, %d bytes\n",
1755 tex_width);
1737 return DRM_ERR(EFAULT); 1756 return DRM_ERR(EFAULT);
1738 } 1757 }
1739 buffer += 8; 1758 buffer += 8;
@@ -1754,8 +1773,7 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1754 RADEON_GMC_SRC_DATATYPE_COLOR | 1773 RADEON_GMC_SRC_DATATYPE_COLOR |
1755 RADEON_ROP3_S | 1774 RADEON_ROP3_S |
1756 RADEON_DP_SRC_SOURCE_MEMORY | 1775 RADEON_DP_SRC_SOURCE_MEMORY |
1757 RADEON_GMC_CLR_CMP_CNTL_DIS | 1776 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
1758 RADEON_GMC_WR_MSK_DIS );
1759 OUT_RING((spitch << 22) | (offset >> 10)); 1777 OUT_RING((spitch << 22) | (offset >> 10));
1760 OUT_RING((texpitch << 22) | (tex->offset >> 10)); 1778 OUT_RING((texpitch << 22) | (tex->offset >> 10));
1761 OUT_RING(0); 1779 OUT_RING(0);
@@ -1776,62 +1794,62 @@ static int radeon_cp_dispatch_texture( DRMFILE filp,
1776 * the texture data is written out to memory before rendering 1794 * the texture data is written out to memory before rendering
1777 * continues. 1795 * continues.
1778 */ 1796 */
1779 BEGIN_RING( 4 ); 1797 BEGIN_RING(4);
1780 RADEON_FLUSH_CACHE(); 1798 RADEON_FLUSH_CACHE();
1781 RADEON_WAIT_UNTIL_2D_IDLE(); 1799 RADEON_WAIT_UNTIL_2D_IDLE();
1782 ADVANCE_RING(); 1800 ADVANCE_RING();
1783 return 0; 1801 return 0;
1784} 1802}
1785 1803
1786 1804static void radeon_cp_dispatch_stipple(drm_device_t * dev, u32 * stipple)
1787static void radeon_cp_dispatch_stipple( drm_device_t *dev, u32 *stipple )
1788{ 1805{
1789 drm_radeon_private_t *dev_priv = dev->dev_private; 1806 drm_radeon_private_t *dev_priv = dev->dev_private;
1790 int i; 1807 int i;
1791 RING_LOCALS; 1808 RING_LOCALS;
1792 DRM_DEBUG( "\n" ); 1809 DRM_DEBUG("\n");
1793 1810
1794 BEGIN_RING( 35 ); 1811 BEGIN_RING(35);
1795 1812
1796 OUT_RING( CP_PACKET0( RADEON_RE_STIPPLE_ADDR, 0 ) ); 1813 OUT_RING(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0));
1797 OUT_RING( 0x00000000 ); 1814 OUT_RING(0x00000000);
1798 1815
1799 OUT_RING( CP_PACKET0_TABLE( RADEON_RE_STIPPLE_DATA, 31 ) ); 1816 OUT_RING(CP_PACKET0_TABLE(RADEON_RE_STIPPLE_DATA, 31));
1800 for ( i = 0 ; i < 32 ; i++ ) { 1817 for (i = 0; i < 32; i++) {
1801 OUT_RING( stipple[i] ); 1818 OUT_RING(stipple[i]);
1802 } 1819 }
1803 1820
1804 ADVANCE_RING(); 1821 ADVANCE_RING();
1805} 1822}
1806 1823
1807static void radeon_apply_surface_regs(int surf_index, drm_radeon_private_t *dev_priv) 1824static void radeon_apply_surface_regs(int surf_index,
1825 drm_radeon_private_t * dev_priv)
1808{ 1826{
1809 if (!dev_priv->mmio) 1827 if (!dev_priv->mmio)
1810 return; 1828 return;
1811 1829
1812 radeon_do_cp_idle(dev_priv); 1830 radeon_do_cp_idle(dev_priv);
1813 1831
1814 RADEON_WRITE(RADEON_SURFACE0_INFO + 16*surf_index, 1832 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * surf_index,
1815 dev_priv->surfaces[surf_index].flags); 1833 dev_priv->surfaces[surf_index].flags);
1816 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*surf_index, 1834 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * surf_index,
1817 dev_priv->surfaces[surf_index].lower); 1835 dev_priv->surfaces[surf_index].lower);
1818 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*surf_index, 1836 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * surf_index,
1819 dev_priv->surfaces[surf_index].upper); 1837 dev_priv->surfaces[surf_index].upper);
1820} 1838}
1821 1839
1822
1823/* Allocates a virtual surface 1840/* Allocates a virtual surface
1824 * doesn't always allocate a real surface, will stretch an existing 1841 * doesn't always allocate a real surface, will stretch an existing
1825 * surface when possible. 1842 * surface when possible.
1826 * 1843 *
1827 * Note that refcount can be at most 2, since during a free refcount=3 1844 * Note that refcount can be at most 2, since during a free refcount=3
1828 * might mean we have to allocate a new surface which might not always 1845 * might mean we have to allocate a new surface which might not always
1829 * be available. 1846 * be available.
1830 * For example : we allocate three contigous surfaces ABC. If B is 1847 * For example : we allocate three contigous surfaces ABC. If B is
1831 * freed, we suddenly need two surfaces to store A and C, which might 1848 * freed, we suddenly need two surfaces to store A and C, which might
1832 * not always be available. 1849 * not always be available.
1833 */ 1850 */
1834static int alloc_surface(drm_radeon_surface_alloc_t* new, drm_radeon_private_t *dev_priv, DRMFILE filp) 1851static int alloc_surface(drm_radeon_surface_alloc_t * new,
1852 drm_radeon_private_t * dev_priv, DRMFILE filp)
1835{ 1853{
1836 struct radeon_virt_surface *s; 1854 struct radeon_virt_surface *s;
1837 int i; 1855 int i;
@@ -1843,34 +1861,37 @@ static int alloc_surface(drm_radeon_surface_alloc_t* new, drm_radeon_private_t *
1843 1861
1844 /* sanity check */ 1862 /* sanity check */
1845 if ((new_lower >= new_upper) || (new->flags == 0) || (new->size == 0) || 1863 if ((new_lower >= new_upper) || (new->flags == 0) || (new->size == 0) ||
1846 ((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) != RADEON_SURF_ADDRESS_FIXED_MASK) || 1864 ((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) !=
1847 ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0)) 1865 RADEON_SURF_ADDRESS_FIXED_MASK)
1866 || ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0))
1848 return -1; 1867 return -1;
1849 1868
1850 /* make sure there is no overlap with existing surfaces */ 1869 /* make sure there is no overlap with existing surfaces */
1851 for (i = 0; i < RADEON_MAX_SURFACES; i++) { 1870 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1852 if ((dev_priv->surfaces[i].refcount != 0) && 1871 if ((dev_priv->surfaces[i].refcount != 0) &&
1853 (( (new_lower >= dev_priv->surfaces[i].lower) && 1872 (((new_lower >= dev_priv->surfaces[i].lower) &&
1854 (new_lower < dev_priv->surfaces[i].upper) ) || 1873 (new_lower < dev_priv->surfaces[i].upper)) ||
1855 ( (new_lower < dev_priv->surfaces[i].lower) && 1874 ((new_lower < dev_priv->surfaces[i].lower) &&
1856 (new_upper > dev_priv->surfaces[i].lower) )) ){ 1875 (new_upper > dev_priv->surfaces[i].lower)))) {
1857 return -1;} 1876 return -1;
1877 }
1858 } 1878 }
1859 1879
1860 /* find a virtual surface */ 1880 /* find a virtual surface */
1861 for (i = 0; i < 2*RADEON_MAX_SURFACES; i++) 1881 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++)
1862 if (dev_priv->virt_surfaces[i].filp == 0) 1882 if (dev_priv->virt_surfaces[i].filp == 0)
1863 break; 1883 break;
1864 if (i == 2*RADEON_MAX_SURFACES) { 1884 if (i == 2 * RADEON_MAX_SURFACES) {
1865 return -1;} 1885 return -1;
1886 }
1866 virt_surface_index = i; 1887 virt_surface_index = i;
1867 1888
1868 /* try to reuse an existing surface */ 1889 /* try to reuse an existing surface */
1869 for (i = 0; i < RADEON_MAX_SURFACES; i++) { 1890 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1870 /* extend before */ 1891 /* extend before */
1871 if ((dev_priv->surfaces[i].refcount == 1) && 1892 if ((dev_priv->surfaces[i].refcount == 1) &&
1872 (new->flags == dev_priv->surfaces[i].flags) && 1893 (new->flags == dev_priv->surfaces[i].flags) &&
1873 (new_upper + 1 == dev_priv->surfaces[i].lower)) { 1894 (new_upper + 1 == dev_priv->surfaces[i].lower)) {
1874 s = &(dev_priv->virt_surfaces[virt_surface_index]); 1895 s = &(dev_priv->virt_surfaces[virt_surface_index]);
1875 s->surface_index = i; 1896 s->surface_index = i;
1876 s->lower = new_lower; 1897 s->lower = new_lower;
@@ -1885,8 +1906,8 @@ static int alloc_surface(drm_radeon_surface_alloc_t* new, drm_radeon_private_t *
1885 1906
1886 /* extend after */ 1907 /* extend after */
1887 if ((dev_priv->surfaces[i].refcount == 1) && 1908 if ((dev_priv->surfaces[i].refcount == 1) &&
1888 (new->flags == dev_priv->surfaces[i].flags) && 1909 (new->flags == dev_priv->surfaces[i].flags) &&
1889 (new_lower == dev_priv->surfaces[i].upper + 1)) { 1910 (new_lower == dev_priv->surfaces[i].upper + 1)) {
1890 s = &(dev_priv->virt_surfaces[virt_surface_index]); 1911 s = &(dev_priv->virt_surfaces[virt_surface_index]);
1891 s->surface_index = i; 1912 s->surface_index = i;
1892 s->lower = new_lower; 1913 s->lower = new_lower;
@@ -1922,26 +1943,34 @@ static int alloc_surface(drm_radeon_surface_alloc_t* new, drm_radeon_private_t *
1922 return -1; 1943 return -1;
1923} 1944}
1924 1945
1925static int free_surface(DRMFILE filp, drm_radeon_private_t *dev_priv, int lower) 1946static int free_surface(DRMFILE filp, drm_radeon_private_t * dev_priv,
1947 int lower)
1926{ 1948{
1927 struct radeon_virt_surface *s; 1949 struct radeon_virt_surface *s;
1928 int i; 1950 int i;
1929 /* find the virtual surface */ 1951 /* find the virtual surface */
1930 for(i = 0; i < 2*RADEON_MAX_SURFACES; i++) { 1952 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
1931 s = &(dev_priv->virt_surfaces[i]); 1953 s = &(dev_priv->virt_surfaces[i]);
1932 if (s->filp) { 1954 if (s->filp) {
1933 if ((lower == s->lower) && (filp == s->filp)) { 1955 if ((lower == s->lower) && (filp == s->filp)) {
1934 if (dev_priv->surfaces[s->surface_index].lower == s->lower) 1956 if (dev_priv->surfaces[s->surface_index].
1935 dev_priv->surfaces[s->surface_index].lower = s->upper; 1957 lower == s->lower)
1958 dev_priv->surfaces[s->surface_index].
1959 lower = s->upper;
1936 1960
1937 if (dev_priv->surfaces[s->surface_index].upper == s->upper) 1961 if (dev_priv->surfaces[s->surface_index].
1938 dev_priv->surfaces[s->surface_index].upper = s->lower; 1962 upper == s->upper)
1963 dev_priv->surfaces[s->surface_index].
1964 upper = s->lower;
1939 1965
1940 dev_priv->surfaces[s->surface_index].refcount--; 1966 dev_priv->surfaces[s->surface_index].refcount--;
1941 if (dev_priv->surfaces[s->surface_index].refcount == 0) 1967 if (dev_priv->surfaces[s->surface_index].
1942 dev_priv->surfaces[s->surface_index].flags = 0; 1968 refcount == 0)
1969 dev_priv->surfaces[s->surface_index].
1970 flags = 0;
1943 s->filp = NULL; 1971 s->filp = NULL;
1944 radeon_apply_surface_regs(s->surface_index, dev_priv); 1972 radeon_apply_surface_regs(s->surface_index,
1973 dev_priv);
1945 return 0; 1974 return 0;
1946 } 1975 }
1947 } 1976 }
@@ -1949,13 +1978,14 @@ static int free_surface(DRMFILE filp, drm_radeon_private_t *dev_priv, int lower)
1949 return 1; 1978 return 1;
1950} 1979}
1951 1980
1952static void radeon_surfaces_release(DRMFILE filp, drm_radeon_private_t *dev_priv) 1981static void radeon_surfaces_release(DRMFILE filp,
1982 drm_radeon_private_t * dev_priv)
1953{ 1983{
1954 int i; 1984 int i;
1955 for( i = 0; i < 2*RADEON_MAX_SURFACES; i++) 1985 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
1956 {
1957 if (dev_priv->virt_surfaces[i].filp == filp) 1986 if (dev_priv->virt_surfaces[i].filp == filp)
1958 free_surface(filp, dev_priv, dev_priv->virt_surfaces[i].lower); 1987 free_surface(filp, dev_priv,
1988 dev_priv->virt_surfaces[i].lower);
1959 } 1989 }
1960} 1990}
1961 1991
@@ -1969,12 +1999,13 @@ static int radeon_surface_alloc(DRM_IOCTL_ARGS)
1969 drm_radeon_surface_alloc_t alloc; 1999 drm_radeon_surface_alloc_t alloc;
1970 2000
1971 if (!dev_priv) { 2001 if (!dev_priv) {
1972 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 2002 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1973 return DRM_ERR(EINVAL); 2003 return DRM_ERR(EINVAL);
1974 } 2004 }
1975 2005
1976 DRM_COPY_FROM_USER_IOCTL(alloc, (drm_radeon_surface_alloc_t __user *)data, 2006 DRM_COPY_FROM_USER_IOCTL(alloc,
1977 sizeof(alloc)); 2007 (drm_radeon_surface_alloc_t __user *) data,
2008 sizeof(alloc));
1978 2009
1979 if (alloc_surface(&alloc, dev_priv, filp) == -1) 2010 if (alloc_surface(&alloc, dev_priv, filp) == -1)
1980 return DRM_ERR(EINVAL); 2011 return DRM_ERR(EINVAL);
@@ -1989,12 +2020,12 @@ static int radeon_surface_free(DRM_IOCTL_ARGS)
1989 drm_radeon_surface_free_t memfree; 2020 drm_radeon_surface_free_t memfree;
1990 2021
1991 if (!dev_priv) { 2022 if (!dev_priv) {
1992 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 2023 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1993 return DRM_ERR(EINVAL); 2024 return DRM_ERR(EINVAL);
1994 } 2025 }
1995 2026
1996 DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_mem_free_t __user *)data, 2027 DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_mem_free_t __user *) data,
1997 sizeof(memfree) ); 2028 sizeof(memfree));
1998 2029
1999 if (free_surface(filp, dev_priv, memfree.address)) 2030 if (free_surface(filp, dev_priv, memfree.address))
2000 return DRM_ERR(EINVAL); 2031 return DRM_ERR(EINVAL);
@@ -2002,51 +2033,52 @@ static int radeon_surface_free(DRM_IOCTL_ARGS)
2002 return 0; 2033 return 0;
2003} 2034}
2004 2035
2005static int radeon_cp_clear( DRM_IOCTL_ARGS ) 2036static int radeon_cp_clear(DRM_IOCTL_ARGS)
2006{ 2037{
2007 DRM_DEVICE; 2038 DRM_DEVICE;
2008 drm_radeon_private_t *dev_priv = dev->dev_private; 2039 drm_radeon_private_t *dev_priv = dev->dev_private;
2009 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; 2040 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2010 drm_radeon_clear_t clear; 2041 drm_radeon_clear_t clear;
2011 drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; 2042 drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
2012 DRM_DEBUG( "\n" ); 2043 DRM_DEBUG("\n");
2013 2044
2014 LOCK_TEST_WITH_RETURN( dev, filp ); 2045 LOCK_TEST_WITH_RETURN(dev, filp);
2015 2046
2016 DRM_COPY_FROM_USER_IOCTL( clear, (drm_radeon_clear_t __user *)data, 2047 DRM_COPY_FROM_USER_IOCTL(clear, (drm_radeon_clear_t __user *) data,
2017 sizeof(clear) ); 2048 sizeof(clear));
2018 2049
2019 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2050 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2020 2051
2021 if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS ) 2052 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2022 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; 2053 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2023 2054
2024 if ( DRM_COPY_FROM_USER( &depth_boxes, clear.depth_boxes, 2055 if (DRM_COPY_FROM_USER(&depth_boxes, clear.depth_boxes,
2025 sarea_priv->nbox * sizeof(depth_boxes[0]) ) ) 2056 sarea_priv->nbox * sizeof(depth_boxes[0])))
2026 return DRM_ERR(EFAULT); 2057 return DRM_ERR(EFAULT);
2027 2058
2028 radeon_cp_dispatch_clear( dev, &clear, depth_boxes ); 2059 radeon_cp_dispatch_clear(dev, &clear, depth_boxes);
2029 2060
2030 COMMIT_RING(); 2061 COMMIT_RING();
2031 return 0; 2062 return 0;
2032} 2063}
2033 2064
2034
2035/* Not sure why this isn't set all the time: 2065/* Not sure why this isn't set all the time:
2036 */ 2066 */
2037static int radeon_do_init_pageflip( drm_device_t *dev ) 2067static int radeon_do_init_pageflip(drm_device_t * dev)
2038{ 2068{
2039 drm_radeon_private_t *dev_priv = dev->dev_private; 2069 drm_radeon_private_t *dev_priv = dev->dev_private;
2040 RING_LOCALS; 2070 RING_LOCALS;
2041 2071
2042 DRM_DEBUG( "\n" ); 2072 DRM_DEBUG("\n");
2043 2073
2044 BEGIN_RING( 6 ); 2074 BEGIN_RING(6);
2045 RADEON_WAIT_UNTIL_3D_IDLE(); 2075 RADEON_WAIT_UNTIL_3D_IDLE();
2046 OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET_CNTL, 0 ) ); 2076 OUT_RING(CP_PACKET0(RADEON_CRTC_OFFSET_CNTL, 0));
2047 OUT_RING( RADEON_READ( RADEON_CRTC_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL ); 2077 OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) |
2048 OUT_RING( CP_PACKET0( RADEON_CRTC2_OFFSET_CNTL, 0 ) ); 2078 RADEON_CRTC_OFFSET_FLIP_CNTL);
2049 OUT_RING( RADEON_READ( RADEON_CRTC2_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL ); 2079 OUT_RING(CP_PACKET0(RADEON_CRTC2_OFFSET_CNTL, 0));
2080 OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) |
2081 RADEON_CRTC_OFFSET_FLIP_CNTL);
2050 ADVANCE_RING(); 2082 ADVANCE_RING();
2051 2083
2052 dev_priv->page_flipping = 1; 2084 dev_priv->page_flipping = 1;
@@ -2059,62 +2091,62 @@ static int radeon_do_init_pageflip( drm_device_t *dev )
2059/* Called whenever a client dies, from drm_release. 2091/* Called whenever a client dies, from drm_release.
2060 * NOTE: Lock isn't necessarily held when this is called! 2092 * NOTE: Lock isn't necessarily held when this is called!
2061 */ 2093 */
2062static int radeon_do_cleanup_pageflip( drm_device_t *dev ) 2094static int radeon_do_cleanup_pageflip(drm_device_t * dev)
2063{ 2095{
2064 drm_radeon_private_t *dev_priv = dev->dev_private; 2096 drm_radeon_private_t *dev_priv = dev->dev_private;
2065 DRM_DEBUG( "\n" ); 2097 DRM_DEBUG("\n");
2066 2098
2067 if (dev_priv->current_page != 0) 2099 if (dev_priv->current_page != 0)
2068 radeon_cp_dispatch_flip( dev ); 2100 radeon_cp_dispatch_flip(dev);
2069 2101
2070 dev_priv->page_flipping = 0; 2102 dev_priv->page_flipping = 0;
2071 return 0; 2103 return 0;
2072} 2104}
2073 2105
2074/* Swapping and flipping are different operations, need different ioctls. 2106/* Swapping and flipping are different operations, need different ioctls.
2075 * They can & should be intermixed to support multiple 3d windows. 2107 * They can & should be intermixed to support multiple 3d windows.
2076 */ 2108 */
2077static int radeon_cp_flip( DRM_IOCTL_ARGS ) 2109static int radeon_cp_flip(DRM_IOCTL_ARGS)
2078{ 2110{
2079 DRM_DEVICE; 2111 DRM_DEVICE;
2080 drm_radeon_private_t *dev_priv = dev->dev_private; 2112 drm_radeon_private_t *dev_priv = dev->dev_private;
2081 DRM_DEBUG( "\n" ); 2113 DRM_DEBUG("\n");
2114
2115 LOCK_TEST_WITH_RETURN(dev, filp);
2082 2116
2083 LOCK_TEST_WITH_RETURN( dev, filp ); 2117 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2084 2118
2085 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2119 if (!dev_priv->page_flipping)
2120 radeon_do_init_pageflip(dev);
2086 2121
2087 if (!dev_priv->page_flipping) 2122 radeon_cp_dispatch_flip(dev);
2088 radeon_do_init_pageflip( dev );
2089
2090 radeon_cp_dispatch_flip( dev );
2091 2123
2092 COMMIT_RING(); 2124 COMMIT_RING();
2093 return 0; 2125 return 0;
2094} 2126}
2095 2127
2096static int radeon_cp_swap( DRM_IOCTL_ARGS ) 2128static int radeon_cp_swap(DRM_IOCTL_ARGS)
2097{ 2129{
2098 DRM_DEVICE; 2130 DRM_DEVICE;
2099 drm_radeon_private_t *dev_priv = dev->dev_private; 2131 drm_radeon_private_t *dev_priv = dev->dev_private;
2100 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; 2132 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2101 DRM_DEBUG( "\n" ); 2133 DRM_DEBUG("\n");
2102 2134
2103 LOCK_TEST_WITH_RETURN( dev, filp ); 2135 LOCK_TEST_WITH_RETURN(dev, filp);
2104 2136
2105 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2137 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2106 2138
2107 if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS ) 2139 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2108 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; 2140 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2109 2141
2110 radeon_cp_dispatch_swap( dev ); 2142 radeon_cp_dispatch_swap(dev);
2111 dev_priv->sarea_priv->ctx_owner = 0; 2143 dev_priv->sarea_priv->ctx_owner = 0;
2112 2144
2113 COMMIT_RING(); 2145 COMMIT_RING();
2114 return 0; 2146 return 0;
2115} 2147}
2116 2148
2117static int radeon_cp_vertex( DRM_IOCTL_ARGS ) 2149static int radeon_cp_vertex(DRM_IOCTL_ARGS)
2118{ 2150{
2119 DRM_DEVICE; 2151 DRM_DEVICE;
2120 drm_radeon_private_t *dev_priv = dev->dev_private; 2152 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -2125,55 +2157,53 @@ static int radeon_cp_vertex( DRM_IOCTL_ARGS )
2125 drm_radeon_vertex_t vertex; 2157 drm_radeon_vertex_t vertex;
2126 drm_radeon_tcl_prim_t prim; 2158 drm_radeon_tcl_prim_t prim;
2127 2159
2128 LOCK_TEST_WITH_RETURN( dev, filp ); 2160 LOCK_TEST_WITH_RETURN(dev, filp);
2129 2161
2130 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); 2162 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2131 2163
2132 DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex_t __user *)data, 2164 DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex_t __user *) data,
2133 sizeof(vertex) ); 2165 sizeof(vertex));
2134 2166
2135 DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n", 2167 DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
2136 DRM_CURRENTPID, 2168 DRM_CURRENTPID, vertex.idx, vertex.count, vertex.discard);
2137 vertex.idx, vertex.count, vertex.discard );
2138 2169
2139 if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { 2170 if (vertex.idx < 0 || vertex.idx >= dma->buf_count) {
2140 DRM_ERROR( "buffer index %d (of %d max)\n", 2171 DRM_ERROR("buffer index %d (of %d max)\n",
2141 vertex.idx, dma->buf_count - 1 ); 2172 vertex.idx, dma->buf_count - 1);
2142 return DRM_ERR(EINVAL); 2173 return DRM_ERR(EINVAL);
2143 } 2174 }
2144 if ( vertex.prim < 0 || 2175 if (vertex.prim < 0 || vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
2145 vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) { 2176 DRM_ERROR("buffer prim %d\n", vertex.prim);
2146 DRM_ERROR( "buffer prim %d\n", vertex.prim );
2147 return DRM_ERR(EINVAL); 2177 return DRM_ERR(EINVAL);
2148 } 2178 }
2149 2179
2150 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2180 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2151 VB_AGE_TEST_WITH_RETURN( dev_priv ); 2181 VB_AGE_TEST_WITH_RETURN(dev_priv);
2152 2182
2153 buf = dma->buflist[vertex.idx]; 2183 buf = dma->buflist[vertex.idx];
2154 2184
2155 if ( buf->filp != filp ) { 2185 if (buf->filp != filp) {
2156 DRM_ERROR( "process %d using buffer owned by %p\n", 2186 DRM_ERROR("process %d using buffer owned by %p\n",
2157 DRM_CURRENTPID, buf->filp ); 2187 DRM_CURRENTPID, buf->filp);
2158 return DRM_ERR(EINVAL); 2188 return DRM_ERR(EINVAL);
2159 } 2189 }
2160 if ( buf->pending ) { 2190 if (buf->pending) {
2161 DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); 2191 DRM_ERROR("sending pending buffer %d\n", vertex.idx);
2162 return DRM_ERR(EINVAL); 2192 return DRM_ERR(EINVAL);
2163 } 2193 }
2164 2194
2165 /* Build up a prim_t record: 2195 /* Build up a prim_t record:
2166 */ 2196 */
2167 if (vertex.count) { 2197 if (vertex.count) {
2168 buf->used = vertex.count; /* not used? */ 2198 buf->used = vertex.count; /* not used? */
2169 2199
2170 if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) { 2200 if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2171 if ( radeon_emit_state( dev_priv, filp_priv, 2201 if (radeon_emit_state(dev_priv, filp_priv,
2172 &sarea_priv->context_state, 2202 &sarea_priv->context_state,
2173 sarea_priv->tex_state, 2203 sarea_priv->tex_state,
2174 sarea_priv->dirty ) ) { 2204 sarea_priv->dirty)) {
2175 DRM_ERROR( "radeon_emit_state failed\n" ); 2205 DRM_ERROR("radeon_emit_state failed\n");
2176 return DRM_ERR( EINVAL ); 2206 return DRM_ERR(EINVAL);
2177 } 2207 }
2178 2208
2179 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | 2209 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
@@ -2183,23 +2213,23 @@ static int radeon_cp_vertex( DRM_IOCTL_ARGS )
2183 } 2213 }
2184 2214
2185 prim.start = 0; 2215 prim.start = 0;
2186 prim.finish = vertex.count; /* unused */ 2216 prim.finish = vertex.count; /* unused */
2187 prim.prim = vertex.prim; 2217 prim.prim = vertex.prim;
2188 prim.numverts = vertex.count; 2218 prim.numverts = vertex.count;
2189 prim.vc_format = dev_priv->sarea_priv->vc_format; 2219 prim.vc_format = dev_priv->sarea_priv->vc_format;
2190 2220
2191 radeon_cp_dispatch_vertex( dev, buf, &prim ); 2221 radeon_cp_dispatch_vertex(dev, buf, &prim);
2192 } 2222 }
2193 2223
2194 if (vertex.discard) { 2224 if (vertex.discard) {
2195 radeon_cp_discard_buffer( dev, buf ); 2225 radeon_cp_discard_buffer(dev, buf);
2196 } 2226 }
2197 2227
2198 COMMIT_RING(); 2228 COMMIT_RING();
2199 return 0; 2229 return 0;
2200} 2230}
2201 2231
2202static int radeon_cp_indices( DRM_IOCTL_ARGS ) 2232static int radeon_cp_indices(DRM_IOCTL_ARGS)
2203{ 2233{
2204 DRM_DEVICE; 2234 DRM_DEVICE;
2205 drm_radeon_private_t *dev_priv = dev->dev_private; 2235 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -2211,69 +2241,67 @@ static int radeon_cp_indices( DRM_IOCTL_ARGS )
2211 drm_radeon_tcl_prim_t prim; 2241 drm_radeon_tcl_prim_t prim;
2212 int count; 2242 int count;
2213 2243
2214 LOCK_TEST_WITH_RETURN( dev, filp ); 2244 LOCK_TEST_WITH_RETURN(dev, filp);
2215 2245
2216 if ( !dev_priv ) { 2246 if (!dev_priv) {
2217 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 2247 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2218 return DRM_ERR(EINVAL); 2248 return DRM_ERR(EINVAL);
2219 } 2249 }
2220 2250
2221 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); 2251 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2222 2252
2223 DRM_COPY_FROM_USER_IOCTL( elts, (drm_radeon_indices_t __user *)data, 2253 DRM_COPY_FROM_USER_IOCTL(elts, (drm_radeon_indices_t __user *) data,
2224 sizeof(elts) ); 2254 sizeof(elts));
2225 2255
2226 DRM_DEBUG( "pid=%d index=%d start=%d end=%d discard=%d\n", 2256 DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n",
2227 DRM_CURRENTPID, 2257 DRM_CURRENTPID, elts.idx, elts.start, elts.end, elts.discard);
2228 elts.idx, elts.start, elts.end, elts.discard );
2229 2258
2230 if ( elts.idx < 0 || elts.idx >= dma->buf_count ) { 2259 if (elts.idx < 0 || elts.idx >= dma->buf_count) {
2231 DRM_ERROR( "buffer index %d (of %d max)\n", 2260 DRM_ERROR("buffer index %d (of %d max)\n",
2232 elts.idx, dma->buf_count - 1 ); 2261 elts.idx, dma->buf_count - 1);
2233 return DRM_ERR(EINVAL); 2262 return DRM_ERR(EINVAL);
2234 } 2263 }
2235 if ( elts.prim < 0 || 2264 if (elts.prim < 0 || elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
2236 elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) { 2265 DRM_ERROR("buffer prim %d\n", elts.prim);
2237 DRM_ERROR( "buffer prim %d\n", elts.prim );
2238 return DRM_ERR(EINVAL); 2266 return DRM_ERR(EINVAL);
2239 } 2267 }
2240 2268
2241 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2269 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2242 VB_AGE_TEST_WITH_RETURN( dev_priv ); 2270 VB_AGE_TEST_WITH_RETURN(dev_priv);
2243 2271
2244 buf = dma->buflist[elts.idx]; 2272 buf = dma->buflist[elts.idx];
2245 2273
2246 if ( buf->filp != filp ) { 2274 if (buf->filp != filp) {
2247 DRM_ERROR( "process %d using buffer owned by %p\n", 2275 DRM_ERROR("process %d using buffer owned by %p\n",
2248 DRM_CURRENTPID, buf->filp ); 2276 DRM_CURRENTPID, buf->filp);
2249 return DRM_ERR(EINVAL); 2277 return DRM_ERR(EINVAL);
2250 } 2278 }
2251 if ( buf->pending ) { 2279 if (buf->pending) {
2252 DRM_ERROR( "sending pending buffer %d\n", elts.idx ); 2280 DRM_ERROR("sending pending buffer %d\n", elts.idx);
2253 return DRM_ERR(EINVAL); 2281 return DRM_ERR(EINVAL);
2254 } 2282 }
2255 2283
2256 count = (elts.end - elts.start) / sizeof(u16); 2284 count = (elts.end - elts.start) / sizeof(u16);
2257 elts.start -= RADEON_INDEX_PRIM_OFFSET; 2285 elts.start -= RADEON_INDEX_PRIM_OFFSET;
2258 2286
2259 if ( elts.start & 0x7 ) { 2287 if (elts.start & 0x7) {
2260 DRM_ERROR( "misaligned buffer 0x%x\n", elts.start ); 2288 DRM_ERROR("misaligned buffer 0x%x\n", elts.start);
2261 return DRM_ERR(EINVAL); 2289 return DRM_ERR(EINVAL);
2262 } 2290 }
2263 if ( elts.start < buf->used ) { 2291 if (elts.start < buf->used) {
2264 DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used ); 2292 DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used);
2265 return DRM_ERR(EINVAL); 2293 return DRM_ERR(EINVAL);
2266 } 2294 }
2267 2295
2268 buf->used = elts.end; 2296 buf->used = elts.end;
2269 2297
2270 if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) { 2298 if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2271 if ( radeon_emit_state( dev_priv, filp_priv, 2299 if (radeon_emit_state(dev_priv, filp_priv,
2272 &sarea_priv->context_state, 2300 &sarea_priv->context_state,
2273 sarea_priv->tex_state, 2301 sarea_priv->tex_state,
2274 sarea_priv->dirty ) ) { 2302 sarea_priv->dirty)) {
2275 DRM_ERROR( "radeon_emit_state failed\n" ); 2303 DRM_ERROR("radeon_emit_state failed\n");
2276 return DRM_ERR( EINVAL ); 2304 return DRM_ERR(EINVAL);
2277 } 2305 }
2278 2306
2279 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | 2307 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
@@ -2282,26 +2310,25 @@ static int radeon_cp_indices( DRM_IOCTL_ARGS )
2282 RADEON_REQUIRE_QUIESCENCE); 2310 RADEON_REQUIRE_QUIESCENCE);
2283 } 2311 }
2284 2312
2285
2286 /* Build up a prim_t record: 2313 /* Build up a prim_t record:
2287 */ 2314 */
2288 prim.start = elts.start; 2315 prim.start = elts.start;
2289 prim.finish = elts.end; 2316 prim.finish = elts.end;
2290 prim.prim = elts.prim; 2317 prim.prim = elts.prim;
2291 prim.offset = 0; /* offset from start of dma buffers */ 2318 prim.offset = 0; /* offset from start of dma buffers */
2292 prim.numverts = RADEON_MAX_VB_VERTS; /* duh */ 2319 prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
2293 prim.vc_format = dev_priv->sarea_priv->vc_format; 2320 prim.vc_format = dev_priv->sarea_priv->vc_format;
2294 2321
2295 radeon_cp_dispatch_indices( dev, buf, &prim ); 2322 radeon_cp_dispatch_indices(dev, buf, &prim);
2296 if (elts.discard) { 2323 if (elts.discard) {
2297 radeon_cp_discard_buffer( dev, buf ); 2324 radeon_cp_discard_buffer(dev, buf);
2298 } 2325 }
2299 2326
2300 COMMIT_RING(); 2327 COMMIT_RING();
2301 return 0; 2328 return 0;
2302} 2329}
2303 2330
2304static int radeon_cp_texture( DRM_IOCTL_ARGS ) 2331static int radeon_cp_texture(DRM_IOCTL_ARGS)
2305{ 2332{
2306 DRM_DEVICE; 2333 DRM_DEVICE;
2307 drm_radeon_private_t *dev_priv = dev->dev_private; 2334 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -2309,53 +2336,54 @@ static int radeon_cp_texture( DRM_IOCTL_ARGS )
2309 drm_radeon_tex_image_t image; 2336 drm_radeon_tex_image_t image;
2310 int ret; 2337 int ret;
2311 2338
2312 LOCK_TEST_WITH_RETURN( dev, filp ); 2339 LOCK_TEST_WITH_RETURN(dev, filp);
2313 2340
2314 DRM_COPY_FROM_USER_IOCTL( tex, (drm_radeon_texture_t __user *)data, sizeof(tex) ); 2341 DRM_COPY_FROM_USER_IOCTL(tex, (drm_radeon_texture_t __user *) data,
2342 sizeof(tex));
2315 2343
2316 if ( tex.image == NULL ) { 2344 if (tex.image == NULL) {
2317 DRM_ERROR( "null texture image!\n" ); 2345 DRM_ERROR("null texture image!\n");
2318 return DRM_ERR(EINVAL); 2346 return DRM_ERR(EINVAL);
2319 } 2347 }
2320 2348
2321 if ( DRM_COPY_FROM_USER( &image, 2349 if (DRM_COPY_FROM_USER(&image,
2322 (drm_radeon_tex_image_t __user *)tex.image, 2350 (drm_radeon_tex_image_t __user *) tex.image,
2323 sizeof(image) ) ) 2351 sizeof(image)))
2324 return DRM_ERR(EFAULT); 2352 return DRM_ERR(EFAULT);
2325 2353
2326 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2354 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2327 VB_AGE_TEST_WITH_RETURN( dev_priv ); 2355 VB_AGE_TEST_WITH_RETURN(dev_priv);
2328 2356
2329 ret = radeon_cp_dispatch_texture( filp, dev, &tex, &image ); 2357 ret = radeon_cp_dispatch_texture(filp, dev, &tex, &image);
2330 2358
2331 COMMIT_RING(); 2359 COMMIT_RING();
2332 return ret; 2360 return ret;
2333} 2361}
2334 2362
2335static int radeon_cp_stipple( DRM_IOCTL_ARGS ) 2363static int radeon_cp_stipple(DRM_IOCTL_ARGS)
2336{ 2364{
2337 DRM_DEVICE; 2365 DRM_DEVICE;
2338 drm_radeon_private_t *dev_priv = dev->dev_private; 2366 drm_radeon_private_t *dev_priv = dev->dev_private;
2339 drm_radeon_stipple_t stipple; 2367 drm_radeon_stipple_t stipple;
2340 u32 mask[32]; 2368 u32 mask[32];
2341 2369
2342 LOCK_TEST_WITH_RETURN( dev, filp ); 2370 LOCK_TEST_WITH_RETURN(dev, filp);
2343 2371
2344 DRM_COPY_FROM_USER_IOCTL( stipple, (drm_radeon_stipple_t __user *)data, 2372 DRM_COPY_FROM_USER_IOCTL(stipple, (drm_radeon_stipple_t __user *) data,
2345 sizeof(stipple) ); 2373 sizeof(stipple));
2346 2374
2347 if ( DRM_COPY_FROM_USER( &mask, stipple.mask, 32 * sizeof(u32) ) ) 2375 if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32)))
2348 return DRM_ERR(EFAULT); 2376 return DRM_ERR(EFAULT);
2349 2377
2350 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2378 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2351 2379
2352 radeon_cp_dispatch_stipple( dev, mask ); 2380 radeon_cp_dispatch_stipple(dev, mask);
2353 2381
2354 COMMIT_RING(); 2382 COMMIT_RING();
2355 return 0; 2383 return 0;
2356} 2384}
2357 2385
2358static int radeon_cp_indirect( DRM_IOCTL_ARGS ) 2386static int radeon_cp_indirect(DRM_IOCTL_ARGS)
2359{ 2387{
2360 DRM_DEVICE; 2388 DRM_DEVICE;
2361 drm_radeon_private_t *dev_priv = dev->dev_private; 2389 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -2364,53 +2392,53 @@ static int radeon_cp_indirect( DRM_IOCTL_ARGS )
2364 drm_radeon_indirect_t indirect; 2392 drm_radeon_indirect_t indirect;
2365 RING_LOCALS; 2393 RING_LOCALS;
2366 2394
2367 LOCK_TEST_WITH_RETURN( dev, filp ); 2395 LOCK_TEST_WITH_RETURN(dev, filp);
2368 2396
2369 if ( !dev_priv ) { 2397 if (!dev_priv) {
2370 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 2398 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2371 return DRM_ERR(EINVAL); 2399 return DRM_ERR(EINVAL);
2372 } 2400 }
2373 2401
2374 DRM_COPY_FROM_USER_IOCTL( indirect, (drm_radeon_indirect_t __user *)data, 2402 DRM_COPY_FROM_USER_IOCTL(indirect,
2375 sizeof(indirect) ); 2403 (drm_radeon_indirect_t __user *) data,
2404 sizeof(indirect));
2376 2405
2377 DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n", 2406 DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n",
2378 indirect.idx, indirect.start, 2407 indirect.idx, indirect.start, indirect.end, indirect.discard);
2379 indirect.end, indirect.discard );
2380 2408
2381 if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) { 2409 if (indirect.idx < 0 || indirect.idx >= dma->buf_count) {
2382 DRM_ERROR( "buffer index %d (of %d max)\n", 2410 DRM_ERROR("buffer index %d (of %d max)\n",
2383 indirect.idx, dma->buf_count - 1 ); 2411 indirect.idx, dma->buf_count - 1);
2384 return DRM_ERR(EINVAL); 2412 return DRM_ERR(EINVAL);
2385 } 2413 }
2386 2414
2387 buf = dma->buflist[indirect.idx]; 2415 buf = dma->buflist[indirect.idx];
2388 2416
2389 if ( buf->filp != filp ) { 2417 if (buf->filp != filp) {
2390 DRM_ERROR( "process %d using buffer owned by %p\n", 2418 DRM_ERROR("process %d using buffer owned by %p\n",
2391 DRM_CURRENTPID, buf->filp ); 2419 DRM_CURRENTPID, buf->filp);
2392 return DRM_ERR(EINVAL); 2420 return DRM_ERR(EINVAL);
2393 } 2421 }
2394 if ( buf->pending ) { 2422 if (buf->pending) {
2395 DRM_ERROR( "sending pending buffer %d\n", indirect.idx ); 2423 DRM_ERROR("sending pending buffer %d\n", indirect.idx);
2396 return DRM_ERR(EINVAL); 2424 return DRM_ERR(EINVAL);
2397 } 2425 }
2398 2426
2399 if ( indirect.start < buf->used ) { 2427 if (indirect.start < buf->used) {
2400 DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n", 2428 DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n",
2401 indirect.start, buf->used ); 2429 indirect.start, buf->used);
2402 return DRM_ERR(EINVAL); 2430 return DRM_ERR(EINVAL);
2403 } 2431 }
2404 2432
2405 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2433 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2406 VB_AGE_TEST_WITH_RETURN( dev_priv ); 2434 VB_AGE_TEST_WITH_RETURN(dev_priv);
2407 2435
2408 buf->used = indirect.end; 2436 buf->used = indirect.end;
2409 2437
2410 /* Wait for the 3D stream to idle before the indirect buffer 2438 /* Wait for the 3D stream to idle before the indirect buffer
2411 * containing 2D acceleration commands is processed. 2439 * containing 2D acceleration commands is processed.
2412 */ 2440 */
2413 BEGIN_RING( 2 ); 2441 BEGIN_RING(2);
2414 2442
2415 RADEON_WAIT_UNTIL_3D_IDLE(); 2443 RADEON_WAIT_UNTIL_3D_IDLE();
2416 2444
@@ -2420,17 +2448,16 @@ static int radeon_cp_indirect( DRM_IOCTL_ARGS )
2420 * X server. This is insecure and is thus only available to 2448 * X server. This is insecure and is thus only available to
2421 * privileged clients. 2449 * privileged clients.
2422 */ 2450 */
2423 radeon_cp_dispatch_indirect( dev, buf, indirect.start, indirect.end ); 2451 radeon_cp_dispatch_indirect(dev, buf, indirect.start, indirect.end);
2424 if (indirect.discard) { 2452 if (indirect.discard) {
2425 radeon_cp_discard_buffer( dev, buf ); 2453 radeon_cp_discard_buffer(dev, buf);
2426 } 2454 }
2427 2455
2428
2429 COMMIT_RING(); 2456 COMMIT_RING();
2430 return 0; 2457 return 0;
2431} 2458}
2432 2459
2433static int radeon_cp_vertex2( DRM_IOCTL_ARGS ) 2460static int radeon_cp_vertex2(DRM_IOCTL_ARGS)
2434{ 2461{
2435 DRM_DEVICE; 2462 DRM_DEVICE;
2436 drm_radeon_private_t *dev_priv = dev->dev_private; 2463 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -2442,65 +2469,64 @@ static int radeon_cp_vertex2( DRM_IOCTL_ARGS )
2442 int i; 2469 int i;
2443 unsigned char laststate; 2470 unsigned char laststate;
2444 2471
2445 LOCK_TEST_WITH_RETURN( dev, filp ); 2472 LOCK_TEST_WITH_RETURN(dev, filp);
2446 2473
2447 if ( !dev_priv ) { 2474 if (!dev_priv) {
2448 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 2475 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2449 return DRM_ERR(EINVAL); 2476 return DRM_ERR(EINVAL);
2450 } 2477 }
2451 2478
2452 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); 2479 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2453 2480
2454 DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex2_t __user *)data, 2481 DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex2_t __user *) data,
2455 sizeof(vertex) ); 2482 sizeof(vertex));
2456 2483
2457 DRM_DEBUG( "pid=%d index=%d discard=%d\n", 2484 DRM_DEBUG("pid=%d index=%d discard=%d\n",
2458 DRM_CURRENTPID, 2485 DRM_CURRENTPID, vertex.idx, vertex.discard);
2459 vertex.idx, vertex.discard );
2460 2486
2461 if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { 2487 if (vertex.idx < 0 || vertex.idx >= dma->buf_count) {
2462 DRM_ERROR( "buffer index %d (of %d max)\n", 2488 DRM_ERROR("buffer index %d (of %d max)\n",
2463 vertex.idx, dma->buf_count - 1 ); 2489 vertex.idx, dma->buf_count - 1);
2464 return DRM_ERR(EINVAL); 2490 return DRM_ERR(EINVAL);
2465 } 2491 }
2466 2492
2467 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2493 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2468 VB_AGE_TEST_WITH_RETURN( dev_priv ); 2494 VB_AGE_TEST_WITH_RETURN(dev_priv);
2469 2495
2470 buf = dma->buflist[vertex.idx]; 2496 buf = dma->buflist[vertex.idx];
2471 2497
2472 if ( buf->filp != filp ) { 2498 if (buf->filp != filp) {
2473 DRM_ERROR( "process %d using buffer owned by %p\n", 2499 DRM_ERROR("process %d using buffer owned by %p\n",
2474 DRM_CURRENTPID, buf->filp ); 2500 DRM_CURRENTPID, buf->filp);
2475 return DRM_ERR(EINVAL); 2501 return DRM_ERR(EINVAL);
2476 } 2502 }
2477 2503
2478 if ( buf->pending ) { 2504 if (buf->pending) {
2479 DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); 2505 DRM_ERROR("sending pending buffer %d\n", vertex.idx);
2480 return DRM_ERR(EINVAL); 2506 return DRM_ERR(EINVAL);
2481 } 2507 }
2482 2508
2483 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) 2509 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2484 return DRM_ERR(EINVAL); 2510 return DRM_ERR(EINVAL);
2485 2511
2486 for (laststate = 0xff, i = 0 ; i < vertex.nr_prims ; i++) { 2512 for (laststate = 0xff, i = 0; i < vertex.nr_prims; i++) {
2487 drm_radeon_prim_t prim; 2513 drm_radeon_prim_t prim;
2488 drm_radeon_tcl_prim_t tclprim; 2514 drm_radeon_tcl_prim_t tclprim;
2489 2515
2490 if ( DRM_COPY_FROM_USER( &prim, &vertex.prim[i], sizeof(prim) ) ) 2516 if (DRM_COPY_FROM_USER(&prim, &vertex.prim[i], sizeof(prim)))
2491 return DRM_ERR(EFAULT); 2517 return DRM_ERR(EFAULT);
2492 2518
2493 if ( prim.stateidx != laststate ) { 2519 if (prim.stateidx != laststate) {
2494 drm_radeon_state_t state; 2520 drm_radeon_state_t state;
2495 2521
2496 if ( DRM_COPY_FROM_USER( &state, 2522 if (DRM_COPY_FROM_USER(&state,
2497 &vertex.state[prim.stateidx], 2523 &vertex.state[prim.stateidx],
2498 sizeof(state) ) ) 2524 sizeof(state)))
2499 return DRM_ERR(EFAULT); 2525 return DRM_ERR(EFAULT);
2500 2526
2501 if ( radeon_emit_state2( dev_priv, filp_priv, &state ) ) { 2527 if (radeon_emit_state2(dev_priv, filp_priv, &state)) {
2502 DRM_ERROR( "radeon_emit_state2 failed\n" ); 2528 DRM_ERROR("radeon_emit_state2 failed\n");
2503 return DRM_ERR( EINVAL ); 2529 return DRM_ERR(EINVAL);
2504 } 2530 }
2505 2531
2506 laststate = prim.stateidx; 2532 laststate = prim.stateidx;
@@ -2511,42 +2537,40 @@ static int radeon_cp_vertex2( DRM_IOCTL_ARGS )
2511 tclprim.prim = prim.prim; 2537 tclprim.prim = prim.prim;
2512 tclprim.vc_format = prim.vc_format; 2538 tclprim.vc_format = prim.vc_format;
2513 2539
2514 if ( prim.prim & RADEON_PRIM_WALK_IND ) { 2540 if (prim.prim & RADEON_PRIM_WALK_IND) {
2515 tclprim.offset = prim.numverts * 64; 2541 tclprim.offset = prim.numverts * 64;
2516 tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */ 2542 tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */
2517 2543
2518 radeon_cp_dispatch_indices( dev, buf, &tclprim ); 2544 radeon_cp_dispatch_indices(dev, buf, &tclprim);
2519 } else { 2545 } else {
2520 tclprim.numverts = prim.numverts; 2546 tclprim.numverts = prim.numverts;
2521 tclprim.offset = 0; /* not used */ 2547 tclprim.offset = 0; /* not used */
2522 2548
2523 radeon_cp_dispatch_vertex( dev, buf, &tclprim ); 2549 radeon_cp_dispatch_vertex(dev, buf, &tclprim);
2524 } 2550 }
2525 2551
2526 if (sarea_priv->nbox == 1) 2552 if (sarea_priv->nbox == 1)
2527 sarea_priv->nbox = 0; 2553 sarea_priv->nbox = 0;
2528 } 2554 }
2529 2555
2530 if ( vertex.discard ) { 2556 if (vertex.discard) {
2531 radeon_cp_discard_buffer( dev, buf ); 2557 radeon_cp_discard_buffer(dev, buf);
2532 } 2558 }
2533 2559
2534 COMMIT_RING(); 2560 COMMIT_RING();
2535 return 0; 2561 return 0;
2536} 2562}
2537 2563
2538 2564static int radeon_emit_packets(drm_radeon_private_t * dev_priv,
2539static int radeon_emit_packets( 2565 drm_file_t * filp_priv,
2540 drm_radeon_private_t *dev_priv, 2566 drm_radeon_cmd_header_t header,
2541 drm_file_t *filp_priv, 2567 drm_radeon_cmd_buffer_t * cmdbuf)
2542 drm_radeon_cmd_header_t header,
2543 drm_radeon_cmd_buffer_t *cmdbuf )
2544{ 2568{
2545 int id = (int)header.packet.packet_id; 2569 int id = (int)header.packet.packet_id;
2546 int sz, reg; 2570 int sz, reg;
2547 int *data = (int *)cmdbuf->buf; 2571 int *data = (int *)cmdbuf->buf;
2548 RING_LOCALS; 2572 RING_LOCALS;
2549 2573
2550 if (id >= RADEON_MAX_STATE_PACKETS) 2574 if (id >= RADEON_MAX_STATE_PACKETS)
2551 return DRM_ERR(EINVAL); 2575 return DRM_ERR(EINVAL);
2552 2576
@@ -2554,18 +2578,18 @@ static int radeon_emit_packets(
2554 reg = packet[id].start; 2578 reg = packet[id].start;
2555 2579
2556 if (sz * sizeof(int) > cmdbuf->bufsz) { 2580 if (sz * sizeof(int) > cmdbuf->bufsz) {
2557 DRM_ERROR( "Packet size provided larger than data provided\n" ); 2581 DRM_ERROR("Packet size provided larger than data provided\n");
2558 return DRM_ERR(EINVAL); 2582 return DRM_ERR(EINVAL);
2559 } 2583 }
2560 2584
2561 if ( radeon_check_and_fixup_packets( dev_priv, filp_priv, id, data ) ) { 2585 if (radeon_check_and_fixup_packets(dev_priv, filp_priv, id, data)) {
2562 DRM_ERROR( "Packet verification failed\n" ); 2586 DRM_ERROR("Packet verification failed\n");
2563 return DRM_ERR( EINVAL ); 2587 return DRM_ERR(EINVAL);
2564 } 2588 }
2565 2589
2566 BEGIN_RING(sz+1); 2590 BEGIN_RING(sz + 1);
2567 OUT_RING( CP_PACKET0( reg, (sz-1) ) ); 2591 OUT_RING(CP_PACKET0(reg, (sz - 1)));
2568 OUT_RING_TABLE( data, sz ); 2592 OUT_RING_TABLE(data, sz);
2569 ADVANCE_RING(); 2593 ADVANCE_RING();
2570 2594
2571 cmdbuf->buf += sz * sizeof(int); 2595 cmdbuf->buf += sz * sizeof(int);
@@ -2573,21 +2597,20 @@ static int radeon_emit_packets(
2573 return 0; 2597 return 0;
2574} 2598}
2575 2599
2576static __inline__ int radeon_emit_scalars( 2600static __inline__ int radeon_emit_scalars(drm_radeon_private_t * dev_priv,
2577 drm_radeon_private_t *dev_priv, 2601 drm_radeon_cmd_header_t header,
2578 drm_radeon_cmd_header_t header, 2602 drm_radeon_cmd_buffer_t * cmdbuf)
2579 drm_radeon_cmd_buffer_t *cmdbuf )
2580{ 2603{
2581 int sz = header.scalars.count; 2604 int sz = header.scalars.count;
2582 int start = header.scalars.offset; 2605 int start = header.scalars.offset;
2583 int stride = header.scalars.stride; 2606 int stride = header.scalars.stride;
2584 RING_LOCALS; 2607 RING_LOCALS;
2585 2608
2586 BEGIN_RING( 3+sz ); 2609 BEGIN_RING(3 + sz);
2587 OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) ); 2610 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
2588 OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); 2611 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2589 OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) ); 2612 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
2590 OUT_RING_TABLE( cmdbuf->buf, sz ); 2613 OUT_RING_TABLE(cmdbuf->buf, sz);
2591 ADVANCE_RING(); 2614 ADVANCE_RING();
2592 cmdbuf->buf += sz * sizeof(int); 2615 cmdbuf->buf += sz * sizeof(int);
2593 cmdbuf->bufsz -= sz * sizeof(int); 2616 cmdbuf->bufsz -= sz * sizeof(int);
@@ -2596,42 +2619,40 @@ static __inline__ int radeon_emit_scalars(
2596 2619
2597/* God this is ugly 2620/* God this is ugly
2598 */ 2621 */
2599static __inline__ int radeon_emit_scalars2( 2622static __inline__ int radeon_emit_scalars2(drm_radeon_private_t * dev_priv,
2600 drm_radeon_private_t *dev_priv, 2623 drm_radeon_cmd_header_t header,
2601 drm_radeon_cmd_header_t header, 2624 drm_radeon_cmd_buffer_t * cmdbuf)
2602 drm_radeon_cmd_buffer_t *cmdbuf )
2603{ 2625{
2604 int sz = header.scalars.count; 2626 int sz = header.scalars.count;
2605 int start = ((unsigned int)header.scalars.offset) + 0x100; 2627 int start = ((unsigned int)header.scalars.offset) + 0x100;
2606 int stride = header.scalars.stride; 2628 int stride = header.scalars.stride;
2607 RING_LOCALS; 2629 RING_LOCALS;
2608 2630
2609 BEGIN_RING( 3+sz ); 2631 BEGIN_RING(3 + sz);
2610 OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) ); 2632 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
2611 OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); 2633 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2612 OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) ); 2634 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
2613 OUT_RING_TABLE( cmdbuf->buf, sz ); 2635 OUT_RING_TABLE(cmdbuf->buf, sz);
2614 ADVANCE_RING(); 2636 ADVANCE_RING();
2615 cmdbuf->buf += sz * sizeof(int); 2637 cmdbuf->buf += sz * sizeof(int);
2616 cmdbuf->bufsz -= sz * sizeof(int); 2638 cmdbuf->bufsz -= sz * sizeof(int);
2617 return 0; 2639 return 0;
2618} 2640}
2619 2641
2620static __inline__ int radeon_emit_vectors( 2642static __inline__ int radeon_emit_vectors(drm_radeon_private_t * dev_priv,
2621 drm_radeon_private_t *dev_priv, 2643 drm_radeon_cmd_header_t header,
2622 drm_radeon_cmd_header_t header, 2644 drm_radeon_cmd_buffer_t * cmdbuf)
2623 drm_radeon_cmd_buffer_t *cmdbuf )
2624{ 2645{
2625 int sz = header.vectors.count; 2646 int sz = header.vectors.count;
2626 int start = header.vectors.offset; 2647 int start = header.vectors.offset;
2627 int stride = header.vectors.stride; 2648 int stride = header.vectors.stride;
2628 RING_LOCALS; 2649 RING_LOCALS;
2629 2650
2630 BEGIN_RING( 3+sz ); 2651 BEGIN_RING(3 + sz);
2631 OUT_RING( CP_PACKET0( RADEON_SE_TCL_VECTOR_INDX_REG, 0 ) ); 2652 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
2632 OUT_RING( start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); 2653 OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
2633 OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_VECTOR_DATA_REG, (sz-1) ) ); 2654 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
2634 OUT_RING_TABLE( cmdbuf->buf, sz ); 2655 OUT_RING_TABLE(cmdbuf->buf, sz);
2635 ADVANCE_RING(); 2656 ADVANCE_RING();
2636 2657
2637 cmdbuf->buf += sz * sizeof(int); 2658 cmdbuf->buf += sz * sizeof(int);
@@ -2639,10 +2660,9 @@ static __inline__ int radeon_emit_vectors(
2639 return 0; 2660 return 0;
2640} 2661}
2641 2662
2642 2663static int radeon_emit_packet3(drm_device_t * dev,
2643static int radeon_emit_packet3( drm_device_t *dev, 2664 drm_file_t * filp_priv,
2644 drm_file_t *filp_priv, 2665 drm_radeon_cmd_buffer_t * cmdbuf)
2645 drm_radeon_cmd_buffer_t *cmdbuf )
2646{ 2666{
2647 drm_radeon_private_t *dev_priv = dev->dev_private; 2667 drm_radeon_private_t *dev_priv = dev->dev_private;
2648 unsigned int cmdsz; 2668 unsigned int cmdsz;
@@ -2651,14 +2671,14 @@ static int radeon_emit_packet3( drm_device_t *dev,
2651 2671
2652 DRM_DEBUG("\n"); 2672 DRM_DEBUG("\n");
2653 2673
2654 if ( ( ret = radeon_check_and_fixup_packet3( dev_priv, filp_priv, 2674 if ((ret = radeon_check_and_fixup_packet3(dev_priv, filp_priv,
2655 cmdbuf, &cmdsz ) ) ) { 2675 cmdbuf, &cmdsz))) {
2656 DRM_ERROR( "Packet verification failed\n" ); 2676 DRM_ERROR("Packet verification failed\n");
2657 return ret; 2677 return ret;
2658 } 2678 }
2659 2679
2660 BEGIN_RING( cmdsz ); 2680 BEGIN_RING(cmdsz);
2661 OUT_RING_TABLE( cmdbuf->buf, cmdsz ); 2681 OUT_RING_TABLE(cmdbuf->buf, cmdsz);
2662 ADVANCE_RING(); 2682 ADVANCE_RING();
2663 2683
2664 cmdbuf->buf += cmdsz * 4; 2684 cmdbuf->buf += cmdsz * 4;
@@ -2666,11 +2686,10 @@ static int radeon_emit_packet3( drm_device_t *dev,
2666 return 0; 2686 return 0;
2667} 2687}
2668 2688
2669 2689static int radeon_emit_packet3_cliprect(drm_device_t * dev,
2670static int radeon_emit_packet3_cliprect( drm_device_t *dev, 2690 drm_file_t * filp_priv,
2671 drm_file_t *filp_priv, 2691 drm_radeon_cmd_buffer_t * cmdbuf,
2672 drm_radeon_cmd_buffer_t *cmdbuf, 2692 int orig_nbox)
2673 int orig_nbox )
2674{ 2693{
2675 drm_radeon_private_t *dev_priv = dev->dev_private; 2694 drm_radeon_private_t *dev_priv = dev->dev_private;
2676 drm_clip_rect_t box; 2695 drm_clip_rect_t box;
@@ -2682,9 +2701,9 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev,
2682 2701
2683 DRM_DEBUG("\n"); 2702 DRM_DEBUG("\n");
2684 2703
2685 if ( ( ret = radeon_check_and_fixup_packet3( dev_priv, filp_priv, 2704 if ((ret = radeon_check_and_fixup_packet3(dev_priv, filp_priv,
2686 cmdbuf, &cmdsz ) ) ) { 2705 cmdbuf, &cmdsz))) {
2687 DRM_ERROR( "Packet verification failed\n" ); 2706 DRM_ERROR("Packet verification failed\n");
2688 return ret; 2707 return ret;
2689 } 2708 }
2690 2709
@@ -2692,8 +2711,8 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev,
2692 goto out; 2711 goto out;
2693 2712
2694 do { 2713 do {
2695 if ( i < cmdbuf->nbox ) { 2714 if (i < cmdbuf->nbox) {
2696 if (DRM_COPY_FROM_USER( &box, &boxes[i], sizeof(box) )) 2715 if (DRM_COPY_FROM_USER(&box, &boxes[i], sizeof(box)))
2697 return DRM_ERR(EFAULT); 2716 return DRM_ERR(EFAULT);
2698 /* FIXME The second and subsequent times round 2717 /* FIXME The second and subsequent times round
2699 * this loop, send a WAIT_UNTIL_3D_IDLE before 2718 * this loop, send a WAIT_UNTIL_3D_IDLE before
@@ -2707,30 +2726,29 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev,
2707 * the correct place to fix it but this works 2726 * the correct place to fix it but this works
2708 * around it until I can figure that out - Tim 2727 * around it until I can figure that out - Tim
2709 * Smith */ 2728 * Smith */
2710 if ( i ) { 2729 if (i) {
2711 BEGIN_RING( 2 ); 2730 BEGIN_RING(2);
2712 RADEON_WAIT_UNTIL_3D_IDLE(); 2731 RADEON_WAIT_UNTIL_3D_IDLE();
2713 ADVANCE_RING(); 2732 ADVANCE_RING();
2714 } 2733 }
2715 radeon_emit_clip_rect( dev_priv, &box ); 2734 radeon_emit_clip_rect(dev_priv, &box);
2716 } 2735 }
2717 2736
2718 BEGIN_RING( cmdsz ); 2737 BEGIN_RING(cmdsz);
2719 OUT_RING_TABLE( cmdbuf->buf, cmdsz ); 2738 OUT_RING_TABLE(cmdbuf->buf, cmdsz);
2720 ADVANCE_RING(); 2739 ADVANCE_RING();
2721 2740
2722 } while ( ++i < cmdbuf->nbox ); 2741 } while (++i < cmdbuf->nbox);
2723 if (cmdbuf->nbox == 1) 2742 if (cmdbuf->nbox == 1)
2724 cmdbuf->nbox = 0; 2743 cmdbuf->nbox = 0;
2725 2744
2726 out: 2745 out:
2727 cmdbuf->buf += cmdsz * 4; 2746 cmdbuf->buf += cmdsz * 4;
2728 cmdbuf->bufsz -= cmdsz * 4; 2747 cmdbuf->bufsz -= cmdsz * 4;
2729 return 0; 2748 return 0;
2730} 2749}
2731 2750
2732 2751static int radeon_emit_wait(drm_device_t * dev, int flags)
2733static int radeon_emit_wait( drm_device_t *dev, int flags )
2734{ 2752{
2735 drm_radeon_private_t *dev_priv = dev->dev_private; 2753 drm_radeon_private_t *dev_priv = dev->dev_private;
2736 RING_LOCALS; 2754 RING_LOCALS;
@@ -2738,18 +2756,18 @@ static int radeon_emit_wait( drm_device_t *dev, int flags )
2738 DRM_DEBUG("%s: %x\n", __FUNCTION__, flags); 2756 DRM_DEBUG("%s: %x\n", __FUNCTION__, flags);
2739 switch (flags) { 2757 switch (flags) {
2740 case RADEON_WAIT_2D: 2758 case RADEON_WAIT_2D:
2741 BEGIN_RING( 2 ); 2759 BEGIN_RING(2);
2742 RADEON_WAIT_UNTIL_2D_IDLE(); 2760 RADEON_WAIT_UNTIL_2D_IDLE();
2743 ADVANCE_RING(); 2761 ADVANCE_RING();
2744 break; 2762 break;
2745 case RADEON_WAIT_3D: 2763 case RADEON_WAIT_3D:
2746 BEGIN_RING( 2 ); 2764 BEGIN_RING(2);
2747 RADEON_WAIT_UNTIL_3D_IDLE(); 2765 RADEON_WAIT_UNTIL_3D_IDLE();
2748 ADVANCE_RING(); 2766 ADVANCE_RING();
2749 break; 2767 break;
2750 case RADEON_WAIT_2D|RADEON_WAIT_3D: 2768 case RADEON_WAIT_2D | RADEON_WAIT_3D:
2751 BEGIN_RING( 2 ); 2769 BEGIN_RING(2);
2752 RADEON_WAIT_UNTIL_IDLE(); 2770 RADEON_WAIT_UNTIL_IDLE();
2753 ADVANCE_RING(); 2771 ADVANCE_RING();
2754 break; 2772 break;
2755 default: 2773 default:
@@ -2759,7 +2777,7 @@ static int radeon_emit_wait( drm_device_t *dev, int flags )
2759 return 0; 2777 return 0;
2760} 2778}
2761 2779
2762static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) 2780static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS)
2763{ 2781{
2764 DRM_DEVICE; 2782 DRM_DEVICE;
2765 drm_radeon_private_t *dev_priv = dev->dev_private; 2783 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -2770,24 +2788,25 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2770 drm_radeon_cmd_buffer_t cmdbuf; 2788 drm_radeon_cmd_buffer_t cmdbuf;
2771 drm_radeon_cmd_header_t header; 2789 drm_radeon_cmd_header_t header;
2772 int orig_nbox, orig_bufsz; 2790 int orig_nbox, orig_bufsz;
2773 char *kbuf=NULL; 2791 char *kbuf = NULL;
2774 2792
2775 LOCK_TEST_WITH_RETURN( dev, filp ); 2793 LOCK_TEST_WITH_RETURN(dev, filp);
2776 2794
2777 if ( !dev_priv ) { 2795 if (!dev_priv) {
2778 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 2796 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2779 return DRM_ERR(EINVAL); 2797 return DRM_ERR(EINVAL);
2780 } 2798 }
2781 2799
2782 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); 2800 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
2783 2801
2784 DRM_COPY_FROM_USER_IOCTL( cmdbuf, (drm_radeon_cmd_buffer_t __user *)data, 2802 DRM_COPY_FROM_USER_IOCTL(cmdbuf,
2785 sizeof(cmdbuf) ); 2803 (drm_radeon_cmd_buffer_t __user *) data,
2804 sizeof(cmdbuf));
2786 2805
2787 RING_SPACE_TEST_WITH_RETURN( dev_priv ); 2806 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2788 VB_AGE_TEST_WITH_RETURN( dev_priv ); 2807 VB_AGE_TEST_WITH_RETURN(dev_priv);
2789 2808
2790 if (cmdbuf.bufsz > 64*1024 || cmdbuf.bufsz<0) { 2809 if (cmdbuf.bufsz > 64 * 1024 || cmdbuf.bufsz < 0) {
2791 return DRM_ERR(EINVAL); 2810 return DRM_ERR(EINVAL);
2792 } 2811 }
2793 2812
@@ -2809,27 +2828,28 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2809 2828
2810 orig_nbox = cmdbuf.nbox; 2829 orig_nbox = cmdbuf.nbox;
2811 2830
2812 if(dev_priv->microcode_version == UCODE_R300) { 2831 if (dev_priv->microcode_version == UCODE_R300) {
2813 int temp; 2832 int temp;
2814 temp=r300_do_cp_cmdbuf(dev, filp, filp_priv, &cmdbuf); 2833 temp = r300_do_cp_cmdbuf(dev, filp, filp_priv, &cmdbuf);
2815 2834
2816 if (orig_bufsz != 0) 2835 if (orig_bufsz != 0)
2817 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); 2836 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
2818 2837
2819 return temp; 2838 return temp;
2820 } 2839 }
2821 2840
2822 /* microcode_version != r300 */ 2841 /* microcode_version != r300 */
2823 while ( cmdbuf.bufsz >= sizeof(header) ) { 2842 while (cmdbuf.bufsz >= sizeof(header)) {
2824 2843
2825 header.i = *(int *)cmdbuf.buf; 2844 header.i = *(int *)cmdbuf.buf;
2826 cmdbuf.buf += sizeof(header); 2845 cmdbuf.buf += sizeof(header);
2827 cmdbuf.bufsz -= sizeof(header); 2846 cmdbuf.bufsz -= sizeof(header);
2828 2847
2829 switch (header.header.cmd_type) { 2848 switch (header.header.cmd_type) {
2830 case RADEON_CMD_PACKET: 2849 case RADEON_CMD_PACKET:
2831 DRM_DEBUG("RADEON_CMD_PACKET\n"); 2850 DRM_DEBUG("RADEON_CMD_PACKET\n");
2832 if (radeon_emit_packets( dev_priv, filp_priv, header, &cmdbuf )) { 2851 if (radeon_emit_packets
2852 (dev_priv, filp_priv, header, &cmdbuf)) {
2833 DRM_ERROR("radeon_emit_packets failed\n"); 2853 DRM_ERROR("radeon_emit_packets failed\n");
2834 goto err; 2854 goto err;
2835 } 2855 }
@@ -2837,7 +2857,7 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2837 2857
2838 case RADEON_CMD_SCALARS: 2858 case RADEON_CMD_SCALARS:
2839 DRM_DEBUG("RADEON_CMD_SCALARS\n"); 2859 DRM_DEBUG("RADEON_CMD_SCALARS\n");
2840 if (radeon_emit_scalars( dev_priv, header, &cmdbuf )) { 2860 if (radeon_emit_scalars(dev_priv, header, &cmdbuf)) {
2841 DRM_ERROR("radeon_emit_scalars failed\n"); 2861 DRM_ERROR("radeon_emit_scalars failed\n");
2842 goto err; 2862 goto err;
2843 } 2863 }
@@ -2845,7 +2865,7 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2845 2865
2846 case RADEON_CMD_VECTORS: 2866 case RADEON_CMD_VECTORS:
2847 DRM_DEBUG("RADEON_CMD_VECTORS\n"); 2867 DRM_DEBUG("RADEON_CMD_VECTORS\n");
2848 if (radeon_emit_vectors( dev_priv, header, &cmdbuf )) { 2868 if (radeon_emit_vectors(dev_priv, header, &cmdbuf)) {
2849 DRM_ERROR("radeon_emit_vectors failed\n"); 2869 DRM_ERROR("radeon_emit_vectors failed\n");
2850 goto err; 2870 goto err;
2851 } 2871 }
@@ -2854,25 +2874,25 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2854 case RADEON_CMD_DMA_DISCARD: 2874 case RADEON_CMD_DMA_DISCARD:
2855 DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n"); 2875 DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
2856 idx = header.dma.buf_idx; 2876 idx = header.dma.buf_idx;
2857 if ( idx < 0 || idx >= dma->buf_count ) { 2877 if (idx < 0 || idx >= dma->buf_count) {
2858 DRM_ERROR( "buffer index %d (of %d max)\n", 2878 DRM_ERROR("buffer index %d (of %d max)\n",
2859 idx, dma->buf_count - 1 ); 2879 idx, dma->buf_count - 1);
2860 goto err; 2880 goto err;
2861 } 2881 }
2862 2882
2863 buf = dma->buflist[idx]; 2883 buf = dma->buflist[idx];
2864 if ( buf->filp != filp || buf->pending ) { 2884 if (buf->filp != filp || buf->pending) {
2865 DRM_ERROR( "bad buffer %p %p %d\n", 2885 DRM_ERROR("bad buffer %p %p %d\n",
2866 buf->filp, filp, buf->pending); 2886 buf->filp, filp, buf->pending);
2867 goto err; 2887 goto err;
2868 } 2888 }
2869 2889
2870 radeon_cp_discard_buffer( dev, buf ); 2890 radeon_cp_discard_buffer(dev, buf);
2871 break; 2891 break;
2872 2892
2873 case RADEON_CMD_PACKET3: 2893 case RADEON_CMD_PACKET3:
2874 DRM_DEBUG("RADEON_CMD_PACKET3\n"); 2894 DRM_DEBUG("RADEON_CMD_PACKET3\n");
2875 if (radeon_emit_packet3( dev, filp_priv, &cmdbuf )) { 2895 if (radeon_emit_packet3(dev, filp_priv, &cmdbuf)) {
2876 DRM_ERROR("radeon_emit_packet3 failed\n"); 2896 DRM_ERROR("radeon_emit_packet3 failed\n");
2877 goto err; 2897 goto err;
2878 } 2898 }
@@ -2880,7 +2900,8 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2880 2900
2881 case RADEON_CMD_PACKET3_CLIP: 2901 case RADEON_CMD_PACKET3_CLIP:
2882 DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n"); 2902 DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n");
2883 if (radeon_emit_packet3_cliprect( dev, filp_priv, &cmdbuf, orig_nbox )) { 2903 if (radeon_emit_packet3_cliprect
2904 (dev, filp_priv, &cmdbuf, orig_nbox)) {
2884 DRM_ERROR("radeon_emit_packet3_clip failed\n"); 2905 DRM_ERROR("radeon_emit_packet3_clip failed\n");
2885 goto err; 2906 goto err;
2886 } 2907 }
@@ -2888,7 +2909,7 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2888 2909
2889 case RADEON_CMD_SCALARS2: 2910 case RADEON_CMD_SCALARS2:
2890 DRM_DEBUG("RADEON_CMD_SCALARS2\n"); 2911 DRM_DEBUG("RADEON_CMD_SCALARS2\n");
2891 if (radeon_emit_scalars2( dev_priv, header, &cmdbuf )) { 2912 if (radeon_emit_scalars2(dev_priv, header, &cmdbuf)) {
2892 DRM_ERROR("radeon_emit_scalars2 failed\n"); 2913 DRM_ERROR("radeon_emit_scalars2 failed\n");
2893 goto err; 2914 goto err;
2894 } 2915 }
@@ -2896,13 +2917,13 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2896 2917
2897 case RADEON_CMD_WAIT: 2918 case RADEON_CMD_WAIT:
2898 DRM_DEBUG("RADEON_CMD_WAIT\n"); 2919 DRM_DEBUG("RADEON_CMD_WAIT\n");
2899 if (radeon_emit_wait( dev, header.wait.flags )) { 2920 if (radeon_emit_wait(dev, header.wait.flags)) {
2900 DRM_ERROR("radeon_emit_wait failed\n"); 2921 DRM_ERROR("radeon_emit_wait failed\n");
2901 goto err; 2922 goto err;
2902 } 2923 }
2903 break; 2924 break;
2904 default: 2925 default:
2905 DRM_ERROR("bad cmd_type %d at %p\n", 2926 DRM_ERROR("bad cmd_type %d at %p\n",
2906 header.header.cmd_type, 2927 header.header.cmd_type,
2907 cmdbuf.buf - sizeof(header)); 2928 cmdbuf.buf - sizeof(header));
2908 goto err; 2929 goto err;
@@ -2916,45 +2937,43 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2916 COMMIT_RING(); 2937 COMMIT_RING();
2917 return 0; 2938 return 0;
2918 2939
2919err: 2940 err:
2920 if (orig_bufsz != 0) 2941 if (orig_bufsz != 0)
2921 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); 2942 drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER);
2922 return DRM_ERR(EINVAL); 2943 return DRM_ERR(EINVAL);
2923} 2944}
2924 2945
2925 2946static int radeon_cp_getparam(DRM_IOCTL_ARGS)
2926
2927static int radeon_cp_getparam( DRM_IOCTL_ARGS )
2928{ 2947{
2929 DRM_DEVICE; 2948 DRM_DEVICE;
2930 drm_radeon_private_t *dev_priv = dev->dev_private; 2949 drm_radeon_private_t *dev_priv = dev->dev_private;
2931 drm_radeon_getparam_t param; 2950 drm_radeon_getparam_t param;
2932 int value; 2951 int value;
2933 2952
2934 if ( !dev_priv ) { 2953 if (!dev_priv) {
2935 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 2954 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
2936 return DRM_ERR(EINVAL); 2955 return DRM_ERR(EINVAL);
2937 } 2956 }
2938 2957
2939 DRM_COPY_FROM_USER_IOCTL( param, (drm_radeon_getparam_t __user *)data, 2958 DRM_COPY_FROM_USER_IOCTL(param, (drm_radeon_getparam_t __user *) data,
2940 sizeof(param) ); 2959 sizeof(param));
2941 2960
2942 DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); 2961 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
2943 2962
2944 switch( param.param ) { 2963 switch (param.param) {
2945 case RADEON_PARAM_GART_BUFFER_OFFSET: 2964 case RADEON_PARAM_GART_BUFFER_OFFSET:
2946 value = dev_priv->gart_buffers_offset; 2965 value = dev_priv->gart_buffers_offset;
2947 break; 2966 break;
2948 case RADEON_PARAM_LAST_FRAME: 2967 case RADEON_PARAM_LAST_FRAME:
2949 dev_priv->stats.last_frame_reads++; 2968 dev_priv->stats.last_frame_reads++;
2950 value = GET_SCRATCH( 0 ); 2969 value = GET_SCRATCH(0);
2951 break; 2970 break;
2952 case RADEON_PARAM_LAST_DISPATCH: 2971 case RADEON_PARAM_LAST_DISPATCH:
2953 value = GET_SCRATCH( 1 ); 2972 value = GET_SCRATCH(1);
2954 break; 2973 break;
2955 case RADEON_PARAM_LAST_CLEAR: 2974 case RADEON_PARAM_LAST_CLEAR:
2956 dev_priv->stats.last_clear_reads++; 2975 dev_priv->stats.last_clear_reads++;
2957 value = GET_SCRATCH( 2 ); 2976 value = GET_SCRATCH(2);
2958 break; 2977 break;
2959 case RADEON_PARAM_IRQ_NR: 2978 case RADEON_PARAM_IRQ_NR:
2960 value = dev->irq; 2979 value = dev->irq;
@@ -2969,15 +2988,15 @@ static int radeon_cp_getparam( DRM_IOCTL_ARGS )
2969 value = dev_priv->ring_rptr_offset; 2988 value = dev_priv->ring_rptr_offset;
2970 break; 2989 break;
2971#if BITS_PER_LONG == 32 2990#if BITS_PER_LONG == 32
2972 /* 2991 /*
2973 * This ioctl() doesn't work on 64-bit platforms because hw_lock is a 2992 * This ioctl() doesn't work on 64-bit platforms because hw_lock is a
2974 * pointer which can't fit into an int-sized variable. According to 2993 * pointer which can't fit into an int-sized variable. According to
2975 * Michel Dänzer, the ioctl() is only used on embedded platforms, so 2994 * Michel Dänzer, the ioctl() is only used on embedded platforms, so
2976 * not supporting it shouldn't be a problem. If the same functionality 2995 * not supporting it shouldn't be a problem. If the same functionality
2977 * is needed on 64-bit platforms, a new ioctl() would have to be added, 2996 * is needed on 64-bit platforms, a new ioctl() would have to be added,
2978 * so backwards-compatibility for the embedded platforms can be 2997 * so backwards-compatibility for the embedded platforms can be
2979 * maintained. --davidm 4-Feb-2004. 2998 * maintained. --davidm 4-Feb-2004.
2980 */ 2999 */
2981 case RADEON_PARAM_SAREA_HANDLE: 3000 case RADEON_PARAM_SAREA_HANDLE:
2982 /* The lock is the first dword in the sarea. */ 3001 /* The lock is the first dword in the sarea. */
2983 value = (long)dev->lock.hw_lock; 3002 value = (long)dev->lock.hw_lock;
@@ -2990,56 +3009,56 @@ static int radeon_cp_getparam( DRM_IOCTL_ARGS )
2990 return DRM_ERR(EINVAL); 3009 return DRM_ERR(EINVAL);
2991 } 3010 }
2992 3011
2993 if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { 3012 if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
2994 DRM_ERROR( "copy_to_user\n" ); 3013 DRM_ERROR("copy_to_user\n");
2995 return DRM_ERR(EFAULT); 3014 return DRM_ERR(EFAULT);
2996 } 3015 }
2997 3016
2998 return 0; 3017 return 0;
2999} 3018}
3000 3019
3001static int radeon_cp_setparam( DRM_IOCTL_ARGS ) { 3020static int radeon_cp_setparam(DRM_IOCTL_ARGS)
3021{
3002 DRM_DEVICE; 3022 DRM_DEVICE;
3003 drm_radeon_private_t *dev_priv = dev->dev_private; 3023 drm_radeon_private_t *dev_priv = dev->dev_private;
3004 drm_file_t *filp_priv; 3024 drm_file_t *filp_priv;
3005 drm_radeon_setparam_t sp; 3025 drm_radeon_setparam_t sp;
3006 struct drm_radeon_driver_file_fields *radeon_priv; 3026 struct drm_radeon_driver_file_fields *radeon_priv;
3007 3027
3008 if ( !dev_priv ) { 3028 if (!dev_priv) {
3009 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); 3029 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
3010 return DRM_ERR( EINVAL ); 3030 return DRM_ERR(EINVAL);
3011 } 3031 }
3012 3032
3013 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); 3033 DRM_GET_PRIV_WITH_RETURN(filp_priv, filp);
3014 3034
3015 DRM_COPY_FROM_USER_IOCTL( sp, ( drm_radeon_setparam_t __user * )data, 3035 DRM_COPY_FROM_USER_IOCTL(sp, (drm_radeon_setparam_t __user *) data,
3016 sizeof( sp ) ); 3036 sizeof(sp));
3017 3037
3018 switch( sp.param ) { 3038 switch (sp.param) {
3019 case RADEON_SETPARAM_FB_LOCATION: 3039 case RADEON_SETPARAM_FB_LOCATION:
3020 radeon_priv = filp_priv->driver_priv; 3040 radeon_priv = filp_priv->driver_priv;
3021 radeon_priv->radeon_fb_delta = dev_priv->fb_location - sp.value; 3041 radeon_priv->radeon_fb_delta = dev_priv->fb_location - sp.value;
3022 break; 3042 break;
3023 case RADEON_SETPARAM_SWITCH_TILING: 3043 case RADEON_SETPARAM_SWITCH_TILING:
3024 if (sp.value == 0) { 3044 if (sp.value == 0) {
3025 DRM_DEBUG( "color tiling disabled\n" ); 3045 DRM_DEBUG("color tiling disabled\n");
3026 dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO; 3046 dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO;
3027 dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO; 3047 dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO;
3028 dev_priv->sarea_priv->tiling_enabled = 0; 3048 dev_priv->sarea_priv->tiling_enabled = 0;
3029 } 3049 } else if (sp.value == 1) {
3030 else if (sp.value == 1) { 3050 DRM_DEBUG("color tiling enabled\n");
3031 DRM_DEBUG( "color tiling enabled\n" );
3032 dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO; 3051 dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO;
3033 dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO; 3052 dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO;
3034 dev_priv->sarea_priv->tiling_enabled = 1; 3053 dev_priv->sarea_priv->tiling_enabled = 1;
3035 } 3054 }
3036 break; 3055 break;
3037 case RADEON_SETPARAM_PCIGART_LOCATION: 3056 case RADEON_SETPARAM_PCIGART_LOCATION:
3038 dev_priv->pcigart_offset = sp.value; 3057 dev_priv->pcigart_offset = sp.value;
3039 break; 3058 break;
3040 default: 3059 default:
3041 DRM_DEBUG( "Invalid parameter %d\n", sp.param ); 3060 DRM_DEBUG("Invalid parameter %d\n", sp.param);
3042 return DRM_ERR( EINVAL ); 3061 return DRM_ERR(EINVAL);
3043 } 3062 }
3044 3063
3045 return 0; 3064 return 0;
@@ -3051,78 +3070,106 @@ static int radeon_cp_setparam( DRM_IOCTL_ARGS ) {
3051 * 3070 *
3052 * DRM infrastructure takes care of reclaiming dma buffers. 3071 * DRM infrastructure takes care of reclaiming dma buffers.
3053 */ 3072 */
3054void radeon_driver_prerelease(drm_device_t *dev, DRMFILE filp) 3073void radeon_driver_prerelease(drm_device_t * dev, DRMFILE filp)
3055{ 3074{
3056 if ( dev->dev_private ) { 3075 if (dev->dev_private) {
3057 drm_radeon_private_t *dev_priv = dev->dev_private; 3076 drm_radeon_private_t *dev_priv = dev->dev_private;
3058 if ( dev_priv->page_flipping ) { 3077 if (dev_priv->page_flipping) {
3059 radeon_do_cleanup_pageflip( dev ); 3078 radeon_do_cleanup_pageflip(dev);
3060 } 3079 }
3061 radeon_mem_release( filp, dev_priv->gart_heap ); 3080 radeon_mem_release(filp, dev_priv->gart_heap);
3062 radeon_mem_release( filp, dev_priv->fb_heap ); 3081 radeon_mem_release(filp, dev_priv->fb_heap);
3063 radeon_surfaces_release(filp, dev_priv); 3082 radeon_surfaces_release(filp, dev_priv);
3064 } 3083 }
3065} 3084}
3066 3085
3067void radeon_driver_pretakedown(drm_device_t *dev) 3086void radeon_driver_pretakedown(drm_device_t * dev)
3068{ 3087{
3069 radeon_do_release(dev); 3088 radeon_do_release(dev);
3070} 3089}
3071 3090
3072int radeon_driver_open_helper(drm_device_t *dev, drm_file_t *filp_priv) 3091int radeon_driver_open_helper(drm_device_t * dev, drm_file_t * filp_priv)
3073{ 3092{
3074 drm_radeon_private_t *dev_priv = dev->dev_private; 3093 drm_radeon_private_t *dev_priv = dev->dev_private;
3075 struct drm_radeon_driver_file_fields *radeon_priv; 3094 struct drm_radeon_driver_file_fields *radeon_priv;
3076 3095
3077 radeon_priv = (struct drm_radeon_driver_file_fields *)drm_alloc(sizeof(*radeon_priv), DRM_MEM_FILES); 3096 radeon_priv =
3078 3097 (struct drm_radeon_driver_file_fields *)
3098 drm_alloc(sizeof(*radeon_priv), DRM_MEM_FILES);
3099
3079 if (!radeon_priv) 3100 if (!radeon_priv)
3080 return -ENOMEM; 3101 return -ENOMEM;
3081 3102
3082 filp_priv->driver_priv = radeon_priv; 3103 filp_priv->driver_priv = radeon_priv;
3083 if ( dev_priv ) 3104 if (dev_priv)
3084 radeon_priv->radeon_fb_delta = dev_priv->fb_location; 3105 radeon_priv->radeon_fb_delta = dev_priv->fb_location;
3085 else 3106 else
3086 radeon_priv->radeon_fb_delta = 0; 3107 radeon_priv->radeon_fb_delta = 0;
3087 return 0; 3108 return 0;
3088} 3109}
3089 3110
3090 3111void radeon_driver_free_filp_priv(drm_device_t * dev, drm_file_t * filp_priv)
3091void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_priv)
3092{ 3112{
3093 struct drm_radeon_driver_file_fields *radeon_priv = filp_priv->driver_priv; 3113 struct drm_radeon_driver_file_fields *radeon_priv =
3094 3114 filp_priv->driver_priv;
3095 drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES); 3115
3116 drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES);
3096} 3117}
3097 3118
3098drm_ioctl_desc_t radeon_ioctls[] = { 3119drm_ioctl_desc_t radeon_ioctls[] = {
3099 [DRM_IOCTL_NR(DRM_RADEON_CP_INIT)] = { radeon_cp_init, 1, 1 }, 3120 [DRM_IOCTL_NR(DRM_RADEON_CP_INIT)] = {radeon_cp_init, 1, 1}
3100 [DRM_IOCTL_NR(DRM_RADEON_CP_START)] = { radeon_cp_start, 1, 1 }, 3121 ,
3101 [DRM_IOCTL_NR(DRM_RADEON_CP_STOP)] = { radeon_cp_stop, 1, 1 }, 3122 [DRM_IOCTL_NR(DRM_RADEON_CP_START)] = {radeon_cp_start, 1, 1}
3102 [DRM_IOCTL_NR(DRM_RADEON_CP_RESET)] = { radeon_cp_reset, 1, 1 }, 3123 ,
3103 [DRM_IOCTL_NR(DRM_RADEON_CP_IDLE)] = { radeon_cp_idle, 1, 0 }, 3124 [DRM_IOCTL_NR(DRM_RADEON_CP_STOP)] = {radeon_cp_stop, 1, 1}
3104 [DRM_IOCTL_NR(DRM_RADEON_CP_RESUME)] = { radeon_cp_resume, 1, 0 }, 3125 ,
3105 [DRM_IOCTL_NR(DRM_RADEON_RESET)] = { radeon_engine_reset, 1, 0 }, 3126 [DRM_IOCTL_NR(DRM_RADEON_CP_RESET)] = {radeon_cp_reset, 1, 1}
3106 [DRM_IOCTL_NR(DRM_RADEON_FULLSCREEN)] = { radeon_fullscreen, 1, 0 }, 3127 ,
3107 [DRM_IOCTL_NR(DRM_RADEON_SWAP)] = { radeon_cp_swap, 1, 0 }, 3128 [DRM_IOCTL_NR(DRM_RADEON_CP_IDLE)] = {radeon_cp_idle, 1, 0}
3108 [DRM_IOCTL_NR(DRM_RADEON_CLEAR)] = { radeon_cp_clear, 1, 0 }, 3129 ,
3109 [DRM_IOCTL_NR(DRM_RADEON_VERTEX)] = { radeon_cp_vertex, 1, 0 }, 3130 [DRM_IOCTL_NR(DRM_RADEON_CP_RESUME)] = {radeon_cp_resume, 1, 0}
3110 [DRM_IOCTL_NR(DRM_RADEON_INDICES)] = { radeon_cp_indices, 1, 0 }, 3131 ,
3111 [DRM_IOCTL_NR(DRM_RADEON_TEXTURE)] = { radeon_cp_texture, 1, 0 }, 3132 [DRM_IOCTL_NR(DRM_RADEON_RESET)] = {radeon_engine_reset, 1, 0}
3112 [DRM_IOCTL_NR(DRM_RADEON_STIPPLE)] = { radeon_cp_stipple, 1, 0 }, 3133 ,
3113 [DRM_IOCTL_NR(DRM_RADEON_INDIRECT)] = { radeon_cp_indirect, 1, 1 }, 3134 [DRM_IOCTL_NR(DRM_RADEON_FULLSCREEN)] = {radeon_fullscreen, 1, 0}
3114 [DRM_IOCTL_NR(DRM_RADEON_VERTEX2)] = { radeon_cp_vertex2, 1, 0 }, 3135 ,
3115 [DRM_IOCTL_NR(DRM_RADEON_CMDBUF)] = { radeon_cp_cmdbuf, 1, 0 }, 3136 [DRM_IOCTL_NR(DRM_RADEON_SWAP)] = {radeon_cp_swap, 1, 0}
3116 [DRM_IOCTL_NR(DRM_RADEON_GETPARAM)] = { radeon_cp_getparam, 1, 0 }, 3137 ,
3117 [DRM_IOCTL_NR(DRM_RADEON_FLIP)] = { radeon_cp_flip, 1, 0 }, 3138 [DRM_IOCTL_NR(DRM_RADEON_CLEAR)] = {radeon_cp_clear, 1, 0}
3118 [DRM_IOCTL_NR(DRM_RADEON_ALLOC)] = { radeon_mem_alloc, 1, 0 }, 3139 ,
3119 [DRM_IOCTL_NR(DRM_RADEON_FREE)] = { radeon_mem_free, 1, 0 }, 3140 [DRM_IOCTL_NR(DRM_RADEON_VERTEX)] = {radeon_cp_vertex, 1, 0}
3120 [DRM_IOCTL_NR(DRM_RADEON_INIT_HEAP)] = { radeon_mem_init_heap,1, 1 }, 3141 ,
3121 [DRM_IOCTL_NR(DRM_RADEON_IRQ_EMIT)] = { radeon_irq_emit, 1, 0 }, 3142 [DRM_IOCTL_NR(DRM_RADEON_INDICES)] = {radeon_cp_indices, 1, 0}
3122 [DRM_IOCTL_NR(DRM_RADEON_IRQ_WAIT)] = { radeon_irq_wait, 1, 0 }, 3143 ,
3123 [DRM_IOCTL_NR(DRM_RADEON_SETPARAM)] = { radeon_cp_setparam, 1, 0 }, 3144 [DRM_IOCTL_NR(DRM_RADEON_TEXTURE)] = {radeon_cp_texture, 1, 0}
3124 [DRM_IOCTL_NR(DRM_RADEON_SURF_ALLOC)] = { radeon_surface_alloc,1, 0 }, 3145 ,
3125 [DRM_IOCTL_NR(DRM_RADEON_SURF_FREE)] = { radeon_surface_free, 1, 0 } 3146 [DRM_IOCTL_NR(DRM_RADEON_STIPPLE)] = {radeon_cp_stipple, 1, 0}
3147 ,
3148 [DRM_IOCTL_NR(DRM_RADEON_INDIRECT)] = {radeon_cp_indirect, 1, 1}
3149 ,
3150 [DRM_IOCTL_NR(DRM_RADEON_VERTEX2)] = {radeon_cp_vertex2, 1, 0}
3151 ,
3152 [DRM_IOCTL_NR(DRM_RADEON_CMDBUF)] = {radeon_cp_cmdbuf, 1, 0}
3153 ,
3154 [DRM_IOCTL_NR(DRM_RADEON_GETPARAM)] = {radeon_cp_getparam, 1, 0}
3155 ,
3156 [DRM_IOCTL_NR(DRM_RADEON_FLIP)] = {radeon_cp_flip, 1, 0}
3157 ,
3158 [DRM_IOCTL_NR(DRM_RADEON_ALLOC)] = {radeon_mem_alloc, 1, 0}
3159 ,
3160 [DRM_IOCTL_NR(DRM_RADEON_FREE)] = {radeon_mem_free, 1, 0}
3161 ,
3162 [DRM_IOCTL_NR(DRM_RADEON_INIT_HEAP)] = {radeon_mem_init_heap, 1, 1}
3163 ,
3164 [DRM_IOCTL_NR(DRM_RADEON_IRQ_EMIT)] = {radeon_irq_emit, 1, 0}
3165 ,
3166 [DRM_IOCTL_NR(DRM_RADEON_IRQ_WAIT)] = {radeon_irq_wait, 1, 0}
3167 ,
3168 [DRM_IOCTL_NR(DRM_RADEON_SETPARAM)] = {radeon_cp_setparam, 1, 0}
3169 ,
3170 [DRM_IOCTL_NR(DRM_RADEON_SURF_ALLOC)] = {radeon_surface_alloc, 1, 0}
3171 ,
3172 [DRM_IOCTL_NR(DRM_RADEON_SURF_FREE)] = {radeon_surface_free, 1, 0}
3126}; 3173};
3127 3174
3128int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls); 3175int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls);
diff --git a/drivers/char/drm/savage_bci.c b/drivers/char/drm/savage_bci.c
index 2fd40bac7c97..0ad9201af8bd 100644
--- a/drivers/char/drm/savage_bci.c
+++ b/drivers/char/drm/savage_bci.c
@@ -28,12 +28,12 @@
28 28
29/* Need a long timeout for shadow status updates can take a while 29/* Need a long timeout for shadow status updates can take a while
30 * and so can waiting for events when the queue is full. */ 30 * and so can waiting for events when the queue is full. */
31#define SAVAGE_DEFAULT_USEC_TIMEOUT 1000000 /* 1s */ 31#define SAVAGE_DEFAULT_USEC_TIMEOUT 1000000 /* 1s */
32#define SAVAGE_EVENT_USEC_TIMEOUT 5000000 /* 5s */ 32#define SAVAGE_EVENT_USEC_TIMEOUT 5000000 /* 5s */
33#define SAVAGE_FREELIST_DEBUG 0 33#define SAVAGE_FREELIST_DEBUG 0
34 34
35static int 35static int
36savage_bci_wait_fifo_shadow(drm_savage_private_t *dev_priv, unsigned int n) 36savage_bci_wait_fifo_shadow(drm_savage_private_t * dev_priv, unsigned int n)
37{ 37{
38 uint32_t mask = dev_priv->status_used_mask; 38 uint32_t mask = dev_priv->status_used_mask;
39 uint32_t threshold = dev_priv->bci_threshold_hi; 39 uint32_t threshold = dev_priv->bci_threshold_hi;
@@ -62,7 +62,7 @@ savage_bci_wait_fifo_shadow(drm_savage_private_t *dev_priv, unsigned int n)
62} 62}
63 63
64static int 64static int
65savage_bci_wait_fifo_s3d(drm_savage_private_t *dev_priv, unsigned int n) 65savage_bci_wait_fifo_s3d(drm_savage_private_t * dev_priv, unsigned int n)
66{ 66{
67 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; 67 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n;
68 uint32_t status; 68 uint32_t status;
@@ -83,7 +83,7 @@ savage_bci_wait_fifo_s3d(drm_savage_private_t *dev_priv, unsigned int n)
83} 83}
84 84
85static int 85static int
86savage_bci_wait_fifo_s4(drm_savage_private_t *dev_priv, unsigned int n) 86savage_bci_wait_fifo_s4(drm_savage_private_t * dev_priv, unsigned int n)
87{ 87{
88 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; 88 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n;
89 uint32_t status; 89 uint32_t status;
@@ -115,7 +115,7 @@ savage_bci_wait_fifo_s4(drm_savage_private_t *dev_priv, unsigned int n)
115 * rule. Otherwise there may be glitches every 2^16 events. 115 * rule. Otherwise there may be glitches every 2^16 events.
116 */ 116 */
117static int 117static int
118savage_bci_wait_event_shadow(drm_savage_private_t *dev_priv, uint16_t e) 118savage_bci_wait_event_shadow(drm_savage_private_t * dev_priv, uint16_t e)
119{ 119{
120 uint32_t status; 120 uint32_t status;
121 int i; 121 int i;
@@ -138,7 +138,7 @@ savage_bci_wait_event_shadow(drm_savage_private_t *dev_priv, uint16_t e)
138} 138}
139 139
140static int 140static int
141savage_bci_wait_event_reg(drm_savage_private_t *dev_priv, uint16_t e) 141savage_bci_wait_event_reg(drm_savage_private_t * dev_priv, uint16_t e)
142{ 142{
143 uint32_t status; 143 uint32_t status;
144 int i; 144 int i;
@@ -159,7 +159,7 @@ savage_bci_wait_event_reg(drm_savage_private_t *dev_priv, uint16_t e)
159 return DRM_ERR(EBUSY); 159 return DRM_ERR(EBUSY);
160} 160}
161 161
162uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv, 162uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv,
163 unsigned int flags) 163 unsigned int flags)
164{ 164{
165 uint16_t count; 165 uint16_t count;
@@ -175,12 +175,12 @@ uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv,
175 } 175 }
176 count = (count + 1) & 0xffff; 176 count = (count + 1) & 0xffff;
177 if (count == 0) { 177 if (count == 0) {
178 count++; /* See the comment above savage_wait_event_*. */ 178 count++; /* See the comment above savage_wait_event_*. */
179 dev_priv->event_wrap++; 179 dev_priv->event_wrap++;
180 } 180 }
181 dev_priv->event_counter = count; 181 dev_priv->event_counter = count;
182 if (dev_priv->status_ptr) 182 if (dev_priv->status_ptr)
183 dev_priv->status_ptr[1023] = (uint32_t)count; 183 dev_priv->status_ptr[1023] = (uint32_t) count;
184 184
185 if ((flags & (SAVAGE_WAIT_2D | SAVAGE_WAIT_3D))) { 185 if ((flags & (SAVAGE_WAIT_2D | SAVAGE_WAIT_3D))) {
186 unsigned int wait_cmd = BCI_CMD_WAIT; 186 unsigned int wait_cmd = BCI_CMD_WAIT;
@@ -193,7 +193,7 @@ uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv,
193 } else { 193 } else {
194 BEGIN_BCI(1); 194 BEGIN_BCI(1);
195 } 195 }
196 BCI_WRITE(BCI_CMD_UPDATE_EVENT_TAG | (uint32_t)count); 196 BCI_WRITE(BCI_CMD_UPDATE_EVENT_TAG | (uint32_t) count);
197 197
198 return count; 198 return count;
199} 199}
@@ -201,7 +201,7 @@ uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv,
201/* 201/*
202 * Freelist management 202 * Freelist management
203 */ 203 */
204static int savage_freelist_init(drm_device_t *dev) 204static int savage_freelist_init(drm_device_t * dev)
205{ 205{
206 drm_savage_private_t *dev_priv = dev->dev_private; 206 drm_savage_private_t *dev_priv = dev->dev_private;
207 drm_device_dma_t *dma = dev->dma; 207 drm_device_dma_t *dma = dev->dma;
@@ -234,7 +234,7 @@ static int savage_freelist_init(drm_device_t *dev)
234 return 0; 234 return 0;
235} 235}
236 236
237static drm_buf_t *savage_freelist_get(drm_device_t *dev) 237static drm_buf_t *savage_freelist_get(drm_device_t * dev)
238{ 238{
239 drm_savage_private_t *dev_priv = dev->dev_private; 239 drm_savage_private_t *dev_priv = dev->dev_private;
240 drm_savage_buf_priv_t *tail = dev_priv->tail.prev; 240 drm_savage_buf_priv_t *tail = dev_priv->tail.prev;
@@ -249,7 +249,7 @@ static drm_buf_t *savage_freelist_get(drm_device_t *dev)
249 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; 249 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
250 wrap = dev_priv->event_wrap; 250 wrap = dev_priv->event_wrap;
251 if (event > dev_priv->event_counter) 251 if (event > dev_priv->event_counter)
252 wrap--; /* hardware hasn't passed the last wrap yet */ 252 wrap--; /* hardware hasn't passed the last wrap yet */
253 253
254 DRM_DEBUG(" tail=0x%04x %d\n", tail->age.event, tail->age.wrap); 254 DRM_DEBUG(" tail=0x%04x %d\n", tail->age.event, tail->age.wrap);
255 DRM_DEBUG(" head=0x%04x %d\n", event, wrap); 255 DRM_DEBUG(" head=0x%04x %d\n", event, wrap);
@@ -267,7 +267,7 @@ static drm_buf_t *savage_freelist_get(drm_device_t *dev)
267 return NULL; 267 return NULL;
268} 268}
269 269
270void savage_freelist_put(drm_device_t *dev, drm_buf_t *buf) 270void savage_freelist_put(drm_device_t * dev, drm_buf_t * buf)
271{ 271{
272 drm_savage_private_t *dev_priv = dev->dev_private; 272 drm_savage_private_t *dev_priv = dev->dev_private;
273 drm_savage_buf_priv_t *entry = buf->dev_private, *prev, *next; 273 drm_savage_buf_priv_t *entry = buf->dev_private, *prev, *next;
@@ -290,15 +290,14 @@ void savage_freelist_put(drm_device_t *dev, drm_buf_t *buf)
290/* 290/*
291 * Command DMA 291 * Command DMA
292 */ 292 */
293static int savage_dma_init(drm_savage_private_t *dev_priv) 293static int savage_dma_init(drm_savage_private_t * dev_priv)
294{ 294{
295 unsigned int i; 295 unsigned int i;
296 296
297 dev_priv->nr_dma_pages = dev_priv->cmd_dma->size / 297 dev_priv->nr_dma_pages = dev_priv->cmd_dma->size /
298 (SAVAGE_DMA_PAGE_SIZE*4); 298 (SAVAGE_DMA_PAGE_SIZE * 4);
299 dev_priv->dma_pages = drm_alloc(sizeof(drm_savage_dma_page_t) * 299 dev_priv->dma_pages = drm_alloc(sizeof(drm_savage_dma_page_t) *
300 dev_priv->nr_dma_pages, 300 dev_priv->nr_dma_pages, DRM_MEM_DRIVER);
301 DRM_MEM_DRIVER);
302 if (dev_priv->dma_pages == NULL) 301 if (dev_priv->dma_pages == NULL)
303 return DRM_ERR(ENOMEM); 302 return DRM_ERR(ENOMEM);
304 303
@@ -315,7 +314,7 @@ static int savage_dma_init(drm_savage_private_t *dev_priv)
315 return 0; 314 return 0;
316} 315}
317 316
318void savage_dma_reset(drm_savage_private_t *dev_priv) 317void savage_dma_reset(drm_savage_private_t * dev_priv)
319{ 318{
320 uint16_t event; 319 uint16_t event;
321 unsigned int wrap, i; 320 unsigned int wrap, i;
@@ -330,7 +329,7 @@ void savage_dma_reset(drm_savage_private_t *dev_priv)
330 dev_priv->first_dma_page = dev_priv->current_dma_page = 0; 329 dev_priv->first_dma_page = dev_priv->current_dma_page = 0;
331} 330}
332 331
333void savage_dma_wait(drm_savage_private_t *dev_priv, unsigned int page) 332void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page)
334{ 333{
335 uint16_t event; 334 uint16_t event;
336 unsigned int wrap; 335 unsigned int wrap;
@@ -346,7 +345,7 @@ void savage_dma_wait(drm_savage_private_t *dev_priv, unsigned int page)
346 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; 345 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
347 wrap = dev_priv->event_wrap; 346 wrap = dev_priv->event_wrap;
348 if (event > dev_priv->event_counter) 347 if (event > dev_priv->event_counter)
349 wrap--; /* hardware hasn't passed the last wrap yet */ 348 wrap--; /* hardware hasn't passed the last wrap yet */
350 349
351 if (dev_priv->dma_pages[page].age.wrap > wrap || 350 if (dev_priv->dma_pages[page].age.wrap > wrap ||
352 (dev_priv->dma_pages[page].age.wrap == wrap && 351 (dev_priv->dma_pages[page].age.wrap == wrap &&
@@ -358,13 +357,13 @@ void savage_dma_wait(drm_savage_private_t *dev_priv, unsigned int page)
358 } 357 }
359} 358}
360 359
361uint32_t *savage_dma_alloc(drm_savage_private_t *dev_priv, unsigned int n) 360uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv, unsigned int n)
362{ 361{
363 unsigned int cur = dev_priv->current_dma_page; 362 unsigned int cur = dev_priv->current_dma_page;
364 unsigned int rest = SAVAGE_DMA_PAGE_SIZE - 363 unsigned int rest = SAVAGE_DMA_PAGE_SIZE -
365 dev_priv->dma_pages[cur].used; 364 dev_priv->dma_pages[cur].used;
366 unsigned int nr_pages = (n - rest + SAVAGE_DMA_PAGE_SIZE-1) / 365 unsigned int nr_pages = (n - rest + SAVAGE_DMA_PAGE_SIZE - 1) /
367 SAVAGE_DMA_PAGE_SIZE; 366 SAVAGE_DMA_PAGE_SIZE;
368 uint32_t *dma_ptr; 367 uint32_t *dma_ptr;
369 unsigned int i; 368 unsigned int i;
370 369
@@ -372,9 +371,8 @@ uint32_t *savage_dma_alloc(drm_savage_private_t *dev_priv, unsigned int n)
372 cur, dev_priv->dma_pages[cur].used, n, rest, nr_pages); 371 cur, dev_priv->dma_pages[cur].used, n, rest, nr_pages);
373 372
374 if (cur + nr_pages < dev_priv->nr_dma_pages) { 373 if (cur + nr_pages < dev_priv->nr_dma_pages) {
375 dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + 374 dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle +
376 cur*SAVAGE_DMA_PAGE_SIZE + 375 cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used;
377 dev_priv->dma_pages[cur].used;
378 if (n < rest) 376 if (n < rest)
379 rest = n; 377 rest = n;
380 dev_priv->dma_pages[cur].used += rest; 378 dev_priv->dma_pages[cur].used += rest;
@@ -382,13 +380,14 @@ uint32_t *savage_dma_alloc(drm_savage_private_t *dev_priv, unsigned int n)
382 cur++; 380 cur++;
383 } else { 381 } else {
384 dev_priv->dma_flush(dev_priv); 382 dev_priv->dma_flush(dev_priv);
385 nr_pages = (n + SAVAGE_DMA_PAGE_SIZE-1) / SAVAGE_DMA_PAGE_SIZE; 383 nr_pages =
384 (n + SAVAGE_DMA_PAGE_SIZE - 1) / SAVAGE_DMA_PAGE_SIZE;
386 for (i = cur; i < dev_priv->nr_dma_pages; ++i) { 385 for (i = cur; i < dev_priv->nr_dma_pages; ++i) {
387 dev_priv->dma_pages[i].age = dev_priv->last_dma_age; 386 dev_priv->dma_pages[i].age = dev_priv->last_dma_age;
388 dev_priv->dma_pages[i].used = 0; 387 dev_priv->dma_pages[i].used = 0;
389 dev_priv->dma_pages[i].flushed = 0; 388 dev_priv->dma_pages[i].flushed = 0;
390 } 389 }
391 dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle; 390 dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle;
392 dev_priv->first_dma_page = cur = 0; 391 dev_priv->first_dma_page = cur = 0;
393 } 392 }
394 for (i = cur; nr_pages > 0; ++i, --nr_pages) { 393 for (i = cur; nr_pages > 0; ++i, --nr_pages) {
@@ -414,7 +413,7 @@ uint32_t *savage_dma_alloc(drm_savage_private_t *dev_priv, unsigned int n)
414 return dma_ptr; 413 return dma_ptr;
415} 414}
416 415
417static void savage_dma_flush(drm_savage_private_t *dev_priv) 416static void savage_dma_flush(drm_savage_private_t * dev_priv)
418{ 417{
419 unsigned int first = dev_priv->first_dma_page; 418 unsigned int first = dev_priv->first_dma_page;
420 unsigned int cur = dev_priv->current_dma_page; 419 unsigned int cur = dev_priv->current_dma_page;
@@ -439,11 +438,10 @@ static void savage_dma_flush(drm_savage_private_t *dev_priv)
439 438
440 /* pad with noops */ 439 /* pad with noops */
441 if (pad) { 440 if (pad) {
442 uint32_t *dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + 441 uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle +
443 cur * SAVAGE_DMA_PAGE_SIZE + 442 cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used;
444 dev_priv->dma_pages[cur].used;
445 dev_priv->dma_pages[cur].used += pad; 443 dev_priv->dma_pages[cur].used += pad;
446 while(pad != 0) { 444 while (pad != 0) {
447 *dma_ptr++ = BCI_CMD_WAIT; 445 *dma_ptr++ = BCI_CMD_WAIT;
448 pad--; 446 pad--;
449 } 447 }
@@ -453,11 +451,10 @@ static void savage_dma_flush(drm_savage_private_t *dev_priv)
453 451
454 /* do flush ... */ 452 /* do flush ... */
455 phys_addr = dev_priv->cmd_dma->offset + 453 phys_addr = dev_priv->cmd_dma->offset +
456 (first * SAVAGE_DMA_PAGE_SIZE + 454 (first * SAVAGE_DMA_PAGE_SIZE +
457 dev_priv->dma_pages[first].flushed) * 4; 455 dev_priv->dma_pages[first].flushed) * 4;
458 len = (cur - first) * SAVAGE_DMA_PAGE_SIZE + 456 len = (cur - first) * SAVAGE_DMA_PAGE_SIZE +
459 dev_priv->dma_pages[cur].used - 457 dev_priv->dma_pages[cur].used - dev_priv->dma_pages[first].flushed;
460 dev_priv->dma_pages[first].flushed;
461 458
462 DRM_DEBUG("phys_addr=%lx, len=%u\n", 459 DRM_DEBUG("phys_addr=%lx, len=%u\n",
463 phys_addr | dev_priv->dma_type, len); 460 phys_addr | dev_priv->dma_type, len);
@@ -499,7 +496,7 @@ static void savage_dma_flush(drm_savage_private_t *dev_priv)
499 dev_priv->dma_pages[cur].flushed); 496 dev_priv->dma_pages[cur].flushed);
500} 497}
501 498
502static void savage_fake_dma_flush(drm_savage_private_t *dev_priv) 499static void savage_fake_dma_flush(drm_savage_private_t * dev_priv)
503{ 500{
504 unsigned int i, j; 501 unsigned int i, j;
505 BCI_LOCALS; 502 BCI_LOCALS;
@@ -515,8 +512,8 @@ static void savage_fake_dma_flush(drm_savage_private_t *dev_priv)
515 for (i = dev_priv->first_dma_page; 512 for (i = dev_priv->first_dma_page;
516 i <= dev_priv->current_dma_page && dev_priv->dma_pages[i].used; 513 i <= dev_priv->current_dma_page && dev_priv->dma_pages[i].used;
517 ++i) { 514 ++i) {
518 uint32_t *dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + 515 uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle +
519 i * SAVAGE_DMA_PAGE_SIZE; 516 i * SAVAGE_DMA_PAGE_SIZE;
520#if SAVAGE_DMA_DEBUG 517#if SAVAGE_DMA_DEBUG
521 /* Sanity check: all pages except the last one must be full. */ 518 /* Sanity check: all pages except the last one must be full. */
522 if (i < dev_priv->current_dma_page && 519 if (i < dev_priv->current_dma_page &&
@@ -543,7 +540,7 @@ static void savage_fake_dma_flush(drm_savage_private_t *dev_priv)
543 * initialized. We also need to take care of deleting the MTRRs in 540 * initialized. We also need to take care of deleting the MTRRs in
544 * postcleanup. 541 * postcleanup.
545 */ 542 */
546int savage_preinit(drm_device_t *dev, unsigned long chipset) 543int savage_preinit(drm_device_t * dev, unsigned long chipset)
547{ 544{
548 drm_savage_private_t *dev_priv; 545 drm_savage_private_t *dev_priv;
549 unsigned long mmio_base, fb_base, fb_size, aperture_base; 546 unsigned long mmio_base, fb_base, fb_size, aperture_base;
@@ -578,19 +575,22 @@ int savage_preinit(drm_device_t *dev, unsigned long chipset)
578 * MTRRs. */ 575 * MTRRs. */
579 dev_priv->mtrr[0].base = fb_base; 576 dev_priv->mtrr[0].base = fb_base;
580 dev_priv->mtrr[0].size = 0x01000000; 577 dev_priv->mtrr[0].size = 0x01000000;
581 dev_priv->mtrr[0].handle = mtrr_add( 578 dev_priv->mtrr[0].handle =
582 dev_priv->mtrr[0].base, dev_priv->mtrr[0].size, 579 mtrr_add(dev_priv->mtrr[0].base,
583 MTRR_TYPE_WRCOMB, 1); 580 dev_priv->mtrr[0].size, MTRR_TYPE_WRCOMB,
584 dev_priv->mtrr[1].base = fb_base+0x02000000; 581 1);
582 dev_priv->mtrr[1].base = fb_base + 0x02000000;
585 dev_priv->mtrr[1].size = 0x02000000; 583 dev_priv->mtrr[1].size = 0x02000000;
586 dev_priv->mtrr[1].handle = mtrr_add( 584 dev_priv->mtrr[1].handle =
587 dev_priv->mtrr[1].base, dev_priv->mtrr[1].size, 585 mtrr_add(dev_priv->mtrr[1].base,
588 MTRR_TYPE_WRCOMB, 1); 586 dev_priv->mtrr[1].size, MTRR_TYPE_WRCOMB,
589 dev_priv->mtrr[2].base = fb_base+0x04000000; 587 1);
588 dev_priv->mtrr[2].base = fb_base + 0x04000000;
590 dev_priv->mtrr[2].size = 0x04000000; 589 dev_priv->mtrr[2].size = 0x04000000;
591 dev_priv->mtrr[2].handle = mtrr_add( 590 dev_priv->mtrr[2].handle =
592 dev_priv->mtrr[2].base, dev_priv->mtrr[2].size, 591 mtrr_add(dev_priv->mtrr[2].base,
593 MTRR_TYPE_WRCOMB, 1); 592 dev_priv->mtrr[2].size, MTRR_TYPE_WRCOMB,
593 1);
594 } else { 594 } else {
595 DRM_ERROR("strange pci_resource_len %08lx\n", 595 DRM_ERROR("strange pci_resource_len %08lx\n",
596 drm_get_resource_len(dev, 0)); 596 drm_get_resource_len(dev, 0));
@@ -608,9 +608,10 @@ int savage_preinit(drm_device_t *dev, unsigned long chipset)
608 * aperture. */ 608 * aperture. */
609 dev_priv->mtrr[0].base = fb_base; 609 dev_priv->mtrr[0].base = fb_base;
610 dev_priv->mtrr[0].size = 0x08000000; 610 dev_priv->mtrr[0].size = 0x08000000;
611 dev_priv->mtrr[0].handle = mtrr_add( 611 dev_priv->mtrr[0].handle =
612 dev_priv->mtrr[0].base, dev_priv->mtrr[0].size, 612 mtrr_add(dev_priv->mtrr[0].base,
613 MTRR_TYPE_WRCOMB, 1); 613 dev_priv->mtrr[0].size, MTRR_TYPE_WRCOMB,
614 1);
614 } else { 615 } else {
615 DRM_ERROR("strange pci_resource_len %08lx\n", 616 DRM_ERROR("strange pci_resource_len %08lx\n",
616 drm_get_resource_len(dev, 1)); 617 drm_get_resource_len(dev, 1));
@@ -647,7 +648,7 @@ int savage_preinit(drm_device_t *dev, unsigned long chipset)
647/* 648/*
648 * Delete MTRRs and free device-private data. 649 * Delete MTRRs and free device-private data.
649 */ 650 */
650int savage_postcleanup(drm_device_t *dev) 651int savage_postcleanup(drm_device_t * dev)
651{ 652{
652 drm_savage_private_t *dev_priv = dev->dev_private; 653 drm_savage_private_t *dev_priv = dev->dev_private;
653 int i; 654 int i;
@@ -663,7 +664,7 @@ int savage_postcleanup(drm_device_t *dev)
663 return 0; 664 return 0;
664} 665}
665 666
666static int savage_do_init_bci(drm_device_t *dev, drm_savage_init_t *init) 667static int savage_do_init_bci(drm_device_t * dev, drm_savage_init_t * init)
667{ 668{
668 drm_savage_private_t *dev_priv = dev->dev_private; 669 drm_savage_private_t *dev_priv = dev->dev_private;
669 670
@@ -731,7 +732,7 @@ static int savage_do_init_bci(drm_device_t *dev, drm_savage_init_t *init)
731 } 732 }
732 if (init->agp_textures_offset) { 733 if (init->agp_textures_offset) {
733 dev_priv->agp_textures = 734 dev_priv->agp_textures =
734 drm_core_findmap(dev, init->agp_textures_offset); 735 drm_core_findmap(dev, init->agp_textures_offset);
735 if (!dev_priv->agp_textures) { 736 if (!dev_priv->agp_textures) {
736 DRM_ERROR("could not find agp texture region!\n"); 737 DRM_ERROR("could not find agp texture region!\n");
737 savage_do_cleanup_bci(dev); 738 savage_do_cleanup_bci(dev);
@@ -802,8 +803,8 @@ static int savage_do_init_bci(drm_device_t *dev, drm_savage_init_t *init)
802 } 803 }
803 804
804 dev_priv->sarea_priv = 805 dev_priv->sarea_priv =
805 (drm_savage_sarea_t *)((uint8_t *)dev_priv->sarea->handle + 806 (drm_savage_sarea_t *) ((uint8_t *) dev_priv->sarea->handle +
806 init->sarea_priv_offset); 807 init->sarea_priv_offset);
807 808
808 /* setup bitmap descriptors */ 809 /* setup bitmap descriptors */
809 { 810 {
@@ -812,35 +813,36 @@ static int savage_do_init_bci(drm_device_t *dev, drm_savage_init_t *init)
812 unsigned int front_stride, back_stride, depth_stride; 813 unsigned int front_stride, back_stride, depth_stride;
813 if (dev_priv->chipset <= S3_SAVAGE4) { 814 if (dev_priv->chipset <= S3_SAVAGE4) {
814 color_tile_format = dev_priv->fb_bpp == 16 ? 815 color_tile_format = dev_priv->fb_bpp == 16 ?
815 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP; 816 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP;
816 depth_tile_format = dev_priv->depth_bpp == 16 ? 817 depth_tile_format = dev_priv->depth_bpp == 16 ?
817 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP; 818 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP;
818 } else { 819 } else {
819 color_tile_format = SAVAGE_BD_TILE_DEST; 820 color_tile_format = SAVAGE_BD_TILE_DEST;
820 depth_tile_format = SAVAGE_BD_TILE_DEST; 821 depth_tile_format = SAVAGE_BD_TILE_DEST;
821 } 822 }
822 front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp/8); 823 front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp / 8);
823 back_stride = dev_priv-> back_pitch / (dev_priv->fb_bpp/8); 824 back_stride = dev_priv->back_pitch / (dev_priv->fb_bpp / 8);
824 depth_stride = dev_priv->depth_pitch / (dev_priv->depth_bpp/8); 825 depth_stride =
826 dev_priv->depth_pitch / (dev_priv->depth_bpp / 8);
825 827
826 dev_priv->front_bd = front_stride | SAVAGE_BD_BW_DISABLE | 828 dev_priv->front_bd = front_stride | SAVAGE_BD_BW_DISABLE |
827 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) | 829 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) |
828 (color_tile_format << SAVAGE_BD_TILE_SHIFT); 830 (color_tile_format << SAVAGE_BD_TILE_SHIFT);
829 831
830 dev_priv-> back_bd = back_stride | SAVAGE_BD_BW_DISABLE | 832 dev_priv->back_bd = back_stride | SAVAGE_BD_BW_DISABLE |
831 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) | 833 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) |
832 (color_tile_format << SAVAGE_BD_TILE_SHIFT); 834 (color_tile_format << SAVAGE_BD_TILE_SHIFT);
833 835
834 dev_priv->depth_bd = depth_stride | SAVAGE_BD_BW_DISABLE | 836 dev_priv->depth_bd = depth_stride | SAVAGE_BD_BW_DISABLE |
835 (dev_priv->depth_bpp << SAVAGE_BD_BPP_SHIFT) | 837 (dev_priv->depth_bpp << SAVAGE_BD_BPP_SHIFT) |
836 (depth_tile_format << SAVAGE_BD_TILE_SHIFT); 838 (depth_tile_format << SAVAGE_BD_TILE_SHIFT);
837 } 839 }
838 840
839 /* setup status and bci ptr */ 841 /* setup status and bci ptr */
840 dev_priv->event_counter = 0; 842 dev_priv->event_counter = 0;
841 dev_priv->event_wrap = 0; 843 dev_priv->event_wrap = 0;
842 dev_priv->bci_ptr = (volatile uint32_t *) 844 dev_priv->bci_ptr = (volatile uint32_t *)
843 ((uint8_t *)dev_priv->mmio->handle + SAVAGE_BCI_OFFSET); 845 ((uint8_t *) dev_priv->mmio->handle + SAVAGE_BCI_OFFSET);
844 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 846 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
845 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S3D; 847 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S3D;
846 } else { 848 } else {
@@ -848,7 +850,7 @@ static int savage_do_init_bci(drm_device_t *dev, drm_savage_init_t *init)
848 } 850 }
849 if (dev_priv->status != NULL) { 851 if (dev_priv->status != NULL) {
850 dev_priv->status_ptr = 852 dev_priv->status_ptr =
851 (volatile uint32_t *)dev_priv->status->handle; 853 (volatile uint32_t *)dev_priv->status->handle;
852 dev_priv->wait_fifo = savage_bci_wait_fifo_shadow; 854 dev_priv->wait_fifo = savage_bci_wait_fifo_shadow;
853 dev_priv->wait_evnt = savage_bci_wait_event_shadow; 855 dev_priv->wait_evnt = savage_bci_wait_event_shadow;
854 dev_priv->status_ptr[1023] = dev_priv->event_counter; 856 dev_priv->status_ptr[1023] = dev_priv->event_counter;
@@ -874,7 +876,7 @@ static int savage_do_init_bci(drm_device_t *dev, drm_savage_init_t *init)
874 return DRM_ERR(ENOMEM); 876 return DRM_ERR(ENOMEM);
875 } 877 }
876 878
877 if (savage_dma_init(dev_priv) < 0) { 879 if (savage_dma_init(dev_priv) < 0) {
878 DRM_ERROR("could not initialize command DMA\n"); 880 DRM_ERROR("could not initialize command DMA\n");
879 savage_do_cleanup_bci(dev); 881 savage_do_cleanup_bci(dev);
880 return DRM_ERR(ENOMEM); 882 return DRM_ERR(ENOMEM);
@@ -883,7 +885,7 @@ static int savage_do_init_bci(drm_device_t *dev, drm_savage_init_t *init)
883 return 0; 885 return 0;
884} 886}
885 887
886int savage_do_cleanup_bci(drm_device_t *dev) 888int savage_do_cleanup_bci(drm_device_t * dev)
887{ 889{
888 drm_savage_private_t *dev_priv = dev->dev_private; 890 drm_savage_private_t *dev_priv = dev->dev_private;
889 891
@@ -907,7 +909,7 @@ int savage_do_cleanup_bci(drm_device_t *dev)
907 909
908 if (dev_priv->dma_pages) 910 if (dev_priv->dma_pages)
909 drm_free(dev_priv->dma_pages, 911 drm_free(dev_priv->dma_pages,
910 sizeof(drm_savage_dma_page_t)*dev_priv->nr_dma_pages, 912 sizeof(drm_savage_dma_page_t) * dev_priv->nr_dma_pages,
911 DRM_MEM_DRIVER); 913 DRM_MEM_DRIVER);
912 914
913 return 0; 915 return 0;
@@ -920,7 +922,7 @@ static int savage_bci_init(DRM_IOCTL_ARGS)
920 922
921 LOCK_TEST_WITH_RETURN(dev, filp); 923 LOCK_TEST_WITH_RETURN(dev, filp);
922 924
923 DRM_COPY_FROM_USER_IOCTL(init, (drm_savage_init_t __user *)data, 925 DRM_COPY_FROM_USER_IOCTL(init, (drm_savage_init_t __user *) data,
924 sizeof(init)); 926 sizeof(init));
925 927
926 switch (init.func) { 928 switch (init.func) {
@@ -943,13 +945,13 @@ static int savage_bci_event_emit(DRM_IOCTL_ARGS)
943 945
944 LOCK_TEST_WITH_RETURN(dev, filp); 946 LOCK_TEST_WITH_RETURN(dev, filp);
945 947
946 DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_emit_t __user *)data, 948 DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_emit_t __user *) data,
947 sizeof(event)); 949 sizeof(event));
948 950
949 event.count = savage_bci_emit_event(dev_priv, event.flags); 951 event.count = savage_bci_emit_event(dev_priv, event.flags);
950 event.count |= dev_priv->event_wrap << 16; 952 event.count |= dev_priv->event_wrap << 16;
951 DRM_COPY_TO_USER_IOCTL(&((drm_savage_event_emit_t __user *)data)->count, 953 DRM_COPY_TO_USER_IOCTL(&((drm_savage_event_emit_t __user *) data)->
952 event.count, sizeof(event.count)); 954 count, event.count, sizeof(event.count));
953 return 0; 955 return 0;
954} 956}
955 957
@@ -963,7 +965,7 @@ static int savage_bci_event_wait(DRM_IOCTL_ARGS)
963 965
964 DRM_DEBUG("\n"); 966 DRM_DEBUG("\n");
965 967
966 DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_wait_t __user *)data, 968 DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_wait_t __user *) data,
967 sizeof(event)); 969 sizeof(event));
968 970
969 UPDATE_EVENT_COUNTER(); 971 UPDATE_EVENT_COUNTER();
@@ -973,7 +975,7 @@ static int savage_bci_event_wait(DRM_IOCTL_ARGS)
973 hw_e = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; 975 hw_e = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
974 hw_w = dev_priv->event_wrap; 976 hw_w = dev_priv->event_wrap;
975 if (hw_e > dev_priv->event_counter) 977 if (hw_e > dev_priv->event_counter)
976 hw_w--; /* hardware hasn't passed the last wrap yet */ 978 hw_w--; /* hardware hasn't passed the last wrap yet */
977 979
978 event_e = event.count & 0xffff; 980 event_e = event.count & 0xffff;
979 event_w = event.count >> 16; 981 event_w = event.count >> 16;
@@ -982,7 +984,7 @@ static int savage_bci_event_wait(DRM_IOCTL_ARGS)
982 * - event counter wrapped since the event was emitted or 984 * - event counter wrapped since the event was emitted or
983 * - the hardware has advanced up to or over the event to wait for. 985 * - the hardware has advanced up to or over the event to wait for.
984 */ 986 */
985 if (event_w < hw_w || (event_w == hw_w && event_e <= hw_e) ) 987 if (event_w < hw_w || (event_w == hw_w && event_e <= hw_e))
986 return 0; 988 return 0;
987 else 989 else
988 return dev_priv->wait_evnt(dev_priv, event_e); 990 return dev_priv->wait_evnt(dev_priv, event_e);
@@ -992,7 +994,8 @@ static int savage_bci_event_wait(DRM_IOCTL_ARGS)
992 * DMA buffer management 994 * DMA buffer management
993 */ 995 */
994 996
995static int savage_bci_get_buffers(DRMFILE filp, drm_device_t *dev, drm_dma_t *d) 997static int savage_bci_get_buffers(DRMFILE filp, drm_device_t * dev,
998 drm_dma_t * d)
996{ 999{
997 drm_buf_t *buf; 1000 drm_buf_t *buf;
998 int i; 1001 int i;
@@ -1025,7 +1028,7 @@ int savage_bci_buffers(DRM_IOCTL_ARGS)
1025 1028
1026 LOCK_TEST_WITH_RETURN(dev, filp); 1029 LOCK_TEST_WITH_RETURN(dev, filp);
1027 1030
1028 DRM_COPY_FROM_USER_IOCTL(d, (drm_dma_t __user *)data, sizeof(d)); 1031 DRM_COPY_FROM_USER_IOCTL(d, (drm_dma_t __user *) data, sizeof(d));
1029 1032
1030 /* Please don't send us buffers. 1033 /* Please don't send us buffers.
1031 */ 1034 */
@@ -1049,12 +1052,13 @@ int savage_bci_buffers(DRM_IOCTL_ARGS)
1049 ret = savage_bci_get_buffers(filp, dev, &d); 1052 ret = savage_bci_get_buffers(filp, dev, &d);
1050 } 1053 }
1051 1054
1052 DRM_COPY_TO_USER_IOCTL((drm_dma_t __user *)data, d, sizeof(d)); 1055 DRM_COPY_TO_USER_IOCTL((drm_dma_t __user *) data, d, sizeof(d));
1053 1056
1054 return ret; 1057 return ret;
1055} 1058}
1056 1059
1057void savage_reclaim_buffers(drm_device_t *dev, DRMFILE filp) { 1060void savage_reclaim_buffers(drm_device_t * dev, DRMFILE filp)
1061{
1058 drm_device_dma_t *dma = dev->dma; 1062 drm_device_dma_t *dma = dev->dma;
1059 drm_savage_private_t *dev_priv = dev->dev_private; 1063 drm_savage_private_t *dev_priv = dev->dev_private;
1060 int i; 1064 int i;
@@ -1066,7 +1070,7 @@ void savage_reclaim_buffers(drm_device_t *dev, DRMFILE filp) {
1066 if (!dma->buflist) 1070 if (!dma->buflist)
1067 return; 1071 return;
1068 1072
1069 /*i830_flush_queue(dev);*/ 1073 /*i830_flush_queue(dev); */
1070 1074
1071 for (i = 0; i < dma->buf_count; i++) { 1075 for (i = 0; i < dma->buf_count; i++) {
1072 drm_buf_t *buf = dma->buflist[i]; 1076 drm_buf_t *buf = dma->buflist[i];
@@ -1085,12 +1089,15 @@ void savage_reclaim_buffers(drm_device_t *dev, DRMFILE filp) {
1085 drm_core_reclaim_buffers(dev, filp); 1089 drm_core_reclaim_buffers(dev, filp);
1086} 1090}
1087 1091
1088
1089drm_ioctl_desc_t savage_ioctls[] = { 1092drm_ioctl_desc_t savage_ioctls[] = {
1090 [DRM_IOCTL_NR(DRM_SAVAGE_BCI_INIT)] = {savage_bci_init, 1, 1}, 1093 [DRM_IOCTL_NR(DRM_SAVAGE_BCI_INIT)] = {savage_bci_init, 1, 1}
1091 [DRM_IOCTL_NR(DRM_SAVAGE_BCI_CMDBUF)] = {savage_bci_cmdbuf, 1, 0}, 1094 ,
1092 [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_EMIT)] = {savage_bci_event_emit, 1, 0}, 1095 [DRM_IOCTL_NR(DRM_SAVAGE_BCI_CMDBUF)] = {savage_bci_cmdbuf, 1, 0}
1093 [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_WAIT)] = {savage_bci_event_wait, 1, 0}, 1096 ,
1097 [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_EMIT)] = {savage_bci_event_emit, 1, 0}
1098 ,
1099 [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_WAIT)] = {savage_bci_event_wait, 1, 0}
1100 ,
1094}; 1101};
1095 1102
1096int savage_max_ioctl = DRM_ARRAY_SIZE(savage_ioctls); 1103int savage_max_ioctl = DRM_ARRAY_SIZE(savage_ioctls);
diff --git a/drivers/char/drm/savage_drm.h b/drivers/char/drm/savage_drm.h
index 6526c9aa7589..e1148e8e7994 100644
--- a/drivers/char/drm/savage_drm.h
+++ b/drivers/char/drm/savage_drm.h
@@ -42,12 +42,13 @@
42#define SAVAGE_NR_TEX_REGIONS 16 42#define SAVAGE_NR_TEX_REGIONS 16
43#define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16 43#define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16
44 44
45#endif /* __SAVAGE_SAREA_DEFINES__ */ 45#endif /* __SAVAGE_SAREA_DEFINES__ */
46 46
47typedef struct _drm_savage_sarea { 47typedef struct _drm_savage_sarea {
48 /* LRU lists for texture memory in agp space and on the card. 48 /* LRU lists for texture memory in agp space and on the card.
49 */ 49 */
50 drm_tex_region_t texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS+1]; 50 drm_tex_region_t texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS +
51 1];
51 unsigned int texAge[SAVAGE_NR_TEX_HEAPS]; 52 unsigned int texAge[SAVAGE_NR_TEX_HEAPS];
52 53
53 /* Mechanism to validate card state. 54 /* Mechanism to validate card state.
@@ -101,24 +102,24 @@ typedef struct drm_savage_init {
101 102
102typedef union drm_savage_cmd_header drm_savage_cmd_header_t; 103typedef union drm_savage_cmd_header drm_savage_cmd_header_t;
103typedef struct drm_savage_cmdbuf { 104typedef struct drm_savage_cmdbuf {
104 /* command buffer in client's address space */ 105 /* command buffer in client's address space */
105 drm_savage_cmd_header_t __user *cmd_addr; 106 drm_savage_cmd_header_t __user *cmd_addr;
106 unsigned int size; /* size of the command buffer in 64bit units */ 107 unsigned int size; /* size of the command buffer in 64bit units */
107 108
108 unsigned int dma_idx; /* DMA buffer index to use */ 109 unsigned int dma_idx; /* DMA buffer index to use */
109 int discard; /* discard DMA buffer when done */ 110 int discard; /* discard DMA buffer when done */
110 /* vertex buffer in client's address space */ 111 /* vertex buffer in client's address space */
111 unsigned int __user *vb_addr; 112 unsigned int __user *vb_addr;
112 unsigned int vb_size; /* size of client vertex buffer in bytes */ 113 unsigned int vb_size; /* size of client vertex buffer in bytes */
113 unsigned int vb_stride; /* stride of vertices in 32bit words */ 114 unsigned int vb_stride; /* stride of vertices in 32bit words */
114 /* boxes in client's address space */ 115 /* boxes in client's address space */
115 drm_clip_rect_t __user *box_addr; 116 drm_clip_rect_t __user *box_addr;
116 unsigned int nbox; /* number of clipping boxes */ 117 unsigned int nbox; /* number of clipping boxes */
117} drm_savage_cmdbuf_t; 118} drm_savage_cmdbuf_t;
118 119
119#define SAVAGE_WAIT_2D 0x1 /* wait for 2D idle before updating event tag */ 120#define SAVAGE_WAIT_2D 0x1 /* wait for 2D idle before updating event tag */
120#define SAVAGE_WAIT_3D 0x2 /* wait for 3D idle before updating event tag */ 121#define SAVAGE_WAIT_3D 0x2 /* wait for 3D idle before updating event tag */
121#define SAVAGE_WAIT_IRQ 0x4 /* emit or wait for IRQ, not implemented yet */ 122#define SAVAGE_WAIT_IRQ 0x4 /* emit or wait for IRQ, not implemented yet */
122typedef struct drm_savage_event { 123typedef struct drm_savage_event {
123 unsigned int count; 124 unsigned int count;
124 unsigned int flags; 125 unsigned int flags;
@@ -126,21 +127,21 @@ typedef struct drm_savage_event {
126 127
127/* Commands for the cmdbuf ioctl 128/* Commands for the cmdbuf ioctl
128 */ 129 */
129#define SAVAGE_CMD_STATE 0 /* a range of state registers */ 130#define SAVAGE_CMD_STATE 0 /* a range of state registers */
130#define SAVAGE_CMD_DMA_PRIM 1 /* vertices from DMA buffer */ 131#define SAVAGE_CMD_DMA_PRIM 1 /* vertices from DMA buffer */
131#define SAVAGE_CMD_VB_PRIM 2 /* vertices from client vertex buffer */ 132#define SAVAGE_CMD_VB_PRIM 2 /* vertices from client vertex buffer */
132#define SAVAGE_CMD_DMA_IDX 3 /* indexed vertices from DMA buffer */ 133#define SAVAGE_CMD_DMA_IDX 3 /* indexed vertices from DMA buffer */
133#define SAVAGE_CMD_VB_IDX 4 /* indexed vertices client vertex buffer */ 134#define SAVAGE_CMD_VB_IDX 4 /* indexed vertices client vertex buffer */
134#define SAVAGE_CMD_CLEAR 5 /* clear buffers */ 135#define SAVAGE_CMD_CLEAR 5 /* clear buffers */
135#define SAVAGE_CMD_SWAP 6 /* swap buffers */ 136#define SAVAGE_CMD_SWAP 6 /* swap buffers */
136 137
137/* Primitive types 138/* Primitive types
138*/ 139*/
139#define SAVAGE_PRIM_TRILIST 0 /* triangle list */ 140#define SAVAGE_PRIM_TRILIST 0 /* triangle list */
140#define SAVAGE_PRIM_TRISTRIP 1 /* triangle strip */ 141#define SAVAGE_PRIM_TRISTRIP 1 /* triangle strip */
141#define SAVAGE_PRIM_TRIFAN 2 /* triangle fan */ 142#define SAVAGE_PRIM_TRIFAN 2 /* triangle fan */
142#define SAVAGE_PRIM_TRILIST_201 3 /* reorder verts for correct flat 143#define SAVAGE_PRIM_TRILIST_201 3 /* reorder verts for correct flat
143 * shading on s3d */ 144 * shading on s3d */
144 145
145/* Skip flags (vertex format) 146/* Skip flags (vertex format)
146 */ 147 */
@@ -172,38 +173,38 @@ union drm_savage_cmd_header {
172 unsigned short pad1; 173 unsigned short pad1;
173 unsigned short pad2; 174 unsigned short pad2;
174 unsigned short pad3; 175 unsigned short pad3;
175 } cmd; /* generic */ 176 } cmd; /* generic */
176 struct { 177 struct {
177 unsigned char cmd; 178 unsigned char cmd;
178 unsigned char global; /* need idle engine? */ 179 unsigned char global; /* need idle engine? */
179 unsigned short count; /* number of consecutive registers */ 180 unsigned short count; /* number of consecutive registers */
180 unsigned short start; /* first register */ 181 unsigned short start; /* first register */
181 unsigned short pad3; 182 unsigned short pad3;
182 } state; /* SAVAGE_CMD_STATE */ 183 } state; /* SAVAGE_CMD_STATE */
183 struct { 184 struct {
184 unsigned char cmd; 185 unsigned char cmd;
185 unsigned char prim; /* primitive type */ 186 unsigned char prim; /* primitive type */
186 unsigned short skip; /* vertex format (skip flags) */ 187 unsigned short skip; /* vertex format (skip flags) */
187 unsigned short count; /* number of vertices */ 188 unsigned short count; /* number of vertices */
188 unsigned short start; /* first vertex in DMA/vertex buffer */ 189 unsigned short start; /* first vertex in DMA/vertex buffer */
189 } prim; /* SAVAGE_CMD_DMA_PRIM, SAVAGE_CMD_VB_PRIM */ 190 } prim; /* SAVAGE_CMD_DMA_PRIM, SAVAGE_CMD_VB_PRIM */
190 struct { 191 struct {
191 unsigned char cmd; 192 unsigned char cmd;
192 unsigned char prim; 193 unsigned char prim;
193 unsigned short skip; 194 unsigned short skip;
194 unsigned short count; /* number of indices that follow */ 195 unsigned short count; /* number of indices that follow */
195 unsigned short pad3; 196 unsigned short pad3;
196 } idx; /* SAVAGE_CMD_DMA_IDX, SAVAGE_CMD_VB_IDX */ 197 } idx; /* SAVAGE_CMD_DMA_IDX, SAVAGE_CMD_VB_IDX */
197 struct { 198 struct {
198 unsigned char cmd; 199 unsigned char cmd;
199 unsigned char pad0; 200 unsigned char pad0;
200 unsigned short pad1; 201 unsigned short pad1;
201 unsigned int flags; 202 unsigned int flags;
202 } clear0; /* SAVAGE_CMD_CLEAR */ 203 } clear0; /* SAVAGE_CMD_CLEAR */
203 struct { 204 struct {
204 unsigned int mask; 205 unsigned int mask;
205 unsigned int value; 206 unsigned int value;
206 } clear1; /* SAVAGE_CMD_CLEAR data */ 207 } clear1; /* SAVAGE_CMD_CLEAR data */
207}; 208};
208 209
209#endif 210#endif
diff --git a/drivers/char/drm/savage_drv.c b/drivers/char/drm/savage_drv.c
index ac8d270427ca..0906f9a5d8f9 100644
--- a/drivers/char/drm/savage_drv.c
+++ b/drivers/char/drm/savage_drv.c
@@ -30,30 +30,28 @@
30 30
31#include "drm_pciids.h" 31#include "drm_pciids.h"
32 32
33static int postinit( struct drm_device *dev, unsigned long flags ) 33static int postinit(struct drm_device *dev, unsigned long flags)
34{ 34{
35 DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", 35 DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n",
36 DRIVER_NAME, 36 DRIVER_NAME,
37 DRIVER_MAJOR, 37 DRIVER_MAJOR,
38 DRIVER_MINOR, 38 DRIVER_MINOR,
39 DRIVER_PATCHLEVEL, 39 DRIVER_PATCHLEVEL,
40 DRIVER_DATE, 40 DRIVER_DATE, dev->primary.minor, pci_pretty_name(dev->pdev)
41 dev->primary.minor, 41 );
42 pci_pretty_name(dev->pdev)
43 );
44 return 0; 42 return 0;
45} 43}
46 44
47static int version( drm_version_t *version ) 45static int version(drm_version_t * version)
48{ 46{
49 int len; 47 int len;
50 48
51 version->version_major = DRIVER_MAJOR; 49 version->version_major = DRIVER_MAJOR;
52 version->version_minor = DRIVER_MINOR; 50 version->version_minor = DRIVER_MINOR;
53 version->version_patchlevel = DRIVER_PATCHLEVEL; 51 version->version_patchlevel = DRIVER_PATCHLEVEL;
54 DRM_COPY( version->name, DRIVER_NAME ); 52 DRM_COPY(version->name, DRIVER_NAME);
55 DRM_COPY( version->date, DRIVER_DATE ); 53 DRM_COPY(version->date, DRIVER_DATE);
56 DRM_COPY( version->desc, DRIVER_DESC ); 54 DRM_COPY(version->desc, DRIVER_DESC);
57 return 0; 55 return 0;
58} 56}
59 57
@@ -66,8 +64,7 @@ extern int savage_max_ioctl;
66 64
67static struct drm_driver driver = { 65static struct drm_driver driver = {
68 .driver_features = 66 .driver_features =
69 DRIVER_USE_AGP | DRIVER_USE_MTRR | 67 DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_DMA | DRIVER_PCI_DMA,
70 DRIVER_HAVE_DMA | DRIVER_PCI_DMA,
71 .dev_priv_size = sizeof(drm_savage_buf_priv_t), 68 .dev_priv_size = sizeof(drm_savage_buf_priv_t),
72 .preinit = savage_preinit, 69 .preinit = savage_preinit,
73 .postinit = postinit, 70 .postinit = postinit,
@@ -79,18 +76,19 @@ static struct drm_driver driver = {
79 .ioctls = savage_ioctls, 76 .ioctls = savage_ioctls,
80 .dma_ioctl = savage_bci_buffers, 77 .dma_ioctl = savage_bci_buffers,
81 .fops = { 78 .fops = {
82 .owner = THIS_MODULE, 79 .owner = THIS_MODULE,
83 .open = drm_open, 80 .open = drm_open,
84 .release = drm_release, 81 .release = drm_release,
85 .ioctl = drm_ioctl, 82 .ioctl = drm_ioctl,
86 .mmap = drm_mmap, 83 .mmap = drm_mmap,
87 .poll = drm_poll, 84 .poll = drm_poll,
88 .fasync = drm_fasync, 85 .fasync = drm_fasync,
89 }, 86 }
87 ,
90 .pci_driver = { 88 .pci_driver = {
91 .name = DRIVER_NAME, 89 .name = DRIVER_NAME,
92 .id_table = pciidlist, 90 .id_table = pciidlist,
93 } 91 }
94}; 92};
95 93
96static int __init savage_init(void) 94static int __init savage_init(void)
@@ -107,6 +105,6 @@ static void __exit savage_exit(void)
107module_init(savage_init); 105module_init(savage_init);
108module_exit(savage_exit); 106module_exit(savage_exit);
109 107
110MODULE_AUTHOR( DRIVER_AUTHOR ); 108MODULE_AUTHOR(DRIVER_AUTHOR);
111MODULE_DESCRIPTION( DRIVER_DESC ); 109MODULE_DESCRIPTION(DRIVER_DESC);
112MODULE_LICENSE("GPL and additional rights"); 110MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/char/drm/savage_drv.h b/drivers/char/drm/savage_drv.h
index a45434944658..358f4fb2712a 100644
--- a/drivers/char/drm/savage_drv.h
+++ b/drivers/char/drm/savage_drv.h
@@ -65,7 +65,7 @@ typedef struct drm_savage_dma_page {
65 drm_savage_age_t age; 65 drm_savage_age_t age;
66 unsigned int used, flushed; 66 unsigned int used, flushed;
67} drm_savage_dma_page_t; 67} drm_savage_dma_page_t;
68#define SAVAGE_DMA_PAGE_SIZE 1024 /* in dwords */ 68#define SAVAGE_DMA_PAGE_SIZE 1024 /* in dwords */
69/* Fake DMA buffer size in bytes. 4 pages. Allows a maximum command 69/* Fake DMA buffer size in bytes. 4 pages. Allows a maximum command
70 * size of 16kbytes or 4k entries. Minimum requirement would be 70 * size of 16kbytes or 4k entries. Minimum requirement would be
71 * 10kbytes for 255 40-byte vertices in one drawing command. */ 71 * 10kbytes for 255 40-byte vertices in one drawing command. */
@@ -184,13 +184,13 @@ typedef struct drm_savage_private {
184 unsigned int waiting; 184 unsigned int waiting;
185 185
186 /* config/hardware-dependent function pointers */ 186 /* config/hardware-dependent function pointers */
187 int (*wait_fifo)(struct drm_savage_private *dev_priv, unsigned int n); 187 int (*wait_fifo) (struct drm_savage_private * dev_priv, unsigned int n);
188 int (*wait_evnt)(struct drm_savage_private *dev_priv, uint16_t e); 188 int (*wait_evnt) (struct drm_savage_private * dev_priv, uint16_t e);
189 /* Err, there is a macro wait_event in include/linux/wait.h. 189 /* Err, there is a macro wait_event in include/linux/wait.h.
190 * Avoid unwanted macro expansion. */ 190 * Avoid unwanted macro expansion. */
191 void (*emit_clip_rect)(struct drm_savage_private *dev_priv, 191 void (*emit_clip_rect) (struct drm_savage_private * dev_priv,
192 drm_clip_rect_t *pbox); 192 drm_clip_rect_t * pbox);
193 void (*dma_flush)(struct drm_savage_private *dev_priv); 193 void (*dma_flush) (struct drm_savage_private * dev_priv);
194} drm_savage_private_t; 194} drm_savage_private_t;
195 195
196/* ioctls */ 196/* ioctls */
@@ -198,23 +198,23 @@ extern int savage_bci_cmdbuf(DRM_IOCTL_ARGS);
198extern int savage_bci_buffers(DRM_IOCTL_ARGS); 198extern int savage_bci_buffers(DRM_IOCTL_ARGS);
199 199
200/* BCI functions */ 200/* BCI functions */
201extern uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv, 201extern uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv,
202 unsigned int flags); 202 unsigned int flags);
203extern void savage_freelist_put(drm_device_t *dev, drm_buf_t *buf); 203extern void savage_freelist_put(drm_device_t * dev, drm_buf_t * buf);
204extern void savage_dma_reset(drm_savage_private_t *dev_priv); 204extern void savage_dma_reset(drm_savage_private_t * dev_priv);
205extern void savage_dma_wait(drm_savage_private_t *dev_priv, unsigned int page); 205extern void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page);
206extern uint32_t *savage_dma_alloc(drm_savage_private_t *dev_priv, 206extern uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv,
207 unsigned int n); 207 unsigned int n);
208extern int savage_preinit(drm_device_t *dev, unsigned long chipset); 208extern int savage_preinit(drm_device_t * dev, unsigned long chipset);
209extern int savage_postcleanup(drm_device_t *dev); 209extern int savage_postcleanup(drm_device_t * dev);
210extern int savage_do_cleanup_bci(drm_device_t *dev); 210extern int savage_do_cleanup_bci(drm_device_t * dev);
211extern void savage_reclaim_buffers(drm_device_t *dev, DRMFILE filp); 211extern void savage_reclaim_buffers(drm_device_t * dev, DRMFILE filp);
212 212
213/* state functions */ 213/* state functions */
214extern void savage_emit_clip_rect_s3d(drm_savage_private_t *dev_priv, 214extern void savage_emit_clip_rect_s3d(drm_savage_private_t * dev_priv,
215 drm_clip_rect_t *pbox); 215 drm_clip_rect_t * pbox);
216extern void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv, 216extern void savage_emit_clip_rect_s4(drm_savage_private_t * dev_priv,
217 drm_clip_rect_t *pbox); 217 drm_clip_rect_t * pbox);
218 218
219#define SAVAGE_FB_SIZE_S3 0x01000000 /* 16MB */ 219#define SAVAGE_FB_SIZE_S3 0x01000000 /* 16MB */
220#define SAVAGE_FB_SIZE_S4 0x02000000 /* 32MB */ 220#define SAVAGE_FB_SIZE_S4 0x02000000 /* 32MB */
@@ -222,10 +222,10 @@ extern void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv,
222#define SAVAGE_APERTURE_OFFSET 0x02000000 /* 32MB */ 222#define SAVAGE_APERTURE_OFFSET 0x02000000 /* 32MB */
223#define SAVAGE_APERTURE_SIZE 0x05000000 /* 5 tiled surfaces, 16MB each */ 223#define SAVAGE_APERTURE_SIZE 0x05000000 /* 5 tiled surfaces, 16MB each */
224 224
225#define SAVAGE_BCI_OFFSET 0x00010000 /* offset of the BCI region 225#define SAVAGE_BCI_OFFSET 0x00010000 /* offset of the BCI region
226 * inside the MMIO region */ 226 * inside the MMIO region */
227#define SAVAGE_BCI_FIFO_SIZE 32 /* number of entries in on-chip 227#define SAVAGE_BCI_FIFO_SIZE 32 /* number of entries in on-chip
228 * BCI FIFO */ 228 * BCI FIFO */
229 229
230/* 230/*
231 * MMIO registers 231 * MMIO registers
@@ -278,7 +278,7 @@ extern void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv,
278#define SAVAGE_TEXADDR1_S4 0x23 278#define SAVAGE_TEXADDR1_S4 0x23
279#define SAVAGE_TEXBLEND0_S4 0x24 279#define SAVAGE_TEXBLEND0_S4 0x24
280#define SAVAGE_TEXBLEND1_S4 0x25 280#define SAVAGE_TEXBLEND1_S4 0x25
281#define SAVAGE_TEXXPRCLR_S4 0x26 /* never used */ 281#define SAVAGE_TEXXPRCLR_S4 0x26 /* never used */
282#define SAVAGE_TEXDESCR_S4 0x27 282#define SAVAGE_TEXDESCR_S4 0x27
283#define SAVAGE_FOGTABLE_S4 0x28 283#define SAVAGE_FOGTABLE_S4 0x28
284#define SAVAGE_FOGCTRL_S4 0x30 284#define SAVAGE_FOGCTRL_S4 0x30
@@ -293,7 +293,7 @@ extern void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv,
293#define SAVAGE_TEXBLENDCOLOR_S4 0x39 293#define SAVAGE_TEXBLENDCOLOR_S4 0x39
294/* Savage3D/MX/IX 3D registers */ 294/* Savage3D/MX/IX 3D registers */
295#define SAVAGE_TEXPALADDR_S3D 0x18 295#define SAVAGE_TEXPALADDR_S3D 0x18
296#define SAVAGE_TEXXPRCLR_S3D 0x19 /* never used */ 296#define SAVAGE_TEXXPRCLR_S3D 0x19 /* never used */
297#define SAVAGE_TEXADDR_S3D 0x1A 297#define SAVAGE_TEXADDR_S3D 0x1A
298#define SAVAGE_TEXDESCR_S3D 0x1B 298#define SAVAGE_TEXDESCR_S3D 0x1B
299#define SAVAGE_TEXCTRL_S3D 0x1C 299#define SAVAGE_TEXCTRL_S3D 0x1C
@@ -305,7 +305,7 @@ extern void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv,
305#define SAVAGE_DESTCTRL_S3D 0x34 305#define SAVAGE_DESTCTRL_S3D 0x34
306#define SAVAGE_SCSTART_S3D 0x35 306#define SAVAGE_SCSTART_S3D 0x35
307#define SAVAGE_SCEND_S3D 0x36 307#define SAVAGE_SCEND_S3D 0x36
308#define SAVAGE_ZWATERMARK_S3D 0x37 308#define SAVAGE_ZWATERMARK_S3D 0x37
309#define SAVAGE_DESTTEXRWWATERMARK_S3D 0x38 309#define SAVAGE_DESTTEXRWWATERMARK_S3D 0x38
310/* common stuff */ 310/* common stuff */
311#define SAVAGE_VERTBUFADDR 0x3e 311#define SAVAGE_VERTBUFADDR 0x3e
@@ -313,9 +313,9 @@ extern void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv,
313#define SAVAGE_DMABUFADDR 0x51 313#define SAVAGE_DMABUFADDR 0x51
314 314
315/* texture enable bits (needed for tex addr checking) */ 315/* texture enable bits (needed for tex addr checking) */
316#define SAVAGE_TEXCTRL_TEXEN_MASK 0x00010000 /* S3D */ 316#define SAVAGE_TEXCTRL_TEXEN_MASK 0x00010000 /* S3D */
317#define SAVAGE_TEXDESCR_TEX0EN_MASK 0x02000000 /* S4 */ 317#define SAVAGE_TEXDESCR_TEX0EN_MASK 0x02000000 /* S4 */
318#define SAVAGE_TEXDESCR_TEX1EN_MASK 0x04000000 /* S4 */ 318#define SAVAGE_TEXDESCR_TEX1EN_MASK 0x04000000 /* S4 */
319 319
320/* Global fields in Savage4/Twister/ProSavage 3D registers: 320/* Global fields in Savage4/Twister/ProSavage 3D registers:
321 * 321 *
@@ -576,4 +576,4 @@ extern void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv,
576#define TEST_AGE( age, e, w ) \ 576#define TEST_AGE( age, e, w ) \
577 ( (age)->wrap < (w) || ( (age)->wrap == (w) && (age)->event <= (e) ) ) 577 ( (age)->wrap < (w) || ( (age)->wrap == (w) && (age)->event <= (e) ) )
578 578
579#endif /* __SAVAGE_DRV_H__ */ 579#endif /* __SAVAGE_DRV_H__ */
diff --git a/drivers/char/drm/savage_state.c b/drivers/char/drm/savage_state.c
index 475695a00083..39654cb5d570 100644
--- a/drivers/char/drm/savage_state.c
+++ b/drivers/char/drm/savage_state.c
@@ -26,48 +26,48 @@
26#include "savage_drm.h" 26#include "savage_drm.h"
27#include "savage_drv.h" 27#include "savage_drv.h"
28 28
29void savage_emit_clip_rect_s3d(drm_savage_private_t *dev_priv, 29void savage_emit_clip_rect_s3d(drm_savage_private_t * dev_priv,
30 drm_clip_rect_t *pbox) 30 drm_clip_rect_t * pbox)
31{ 31{
32 uint32_t scstart = dev_priv->state.s3d.new_scstart; 32 uint32_t scstart = dev_priv->state.s3d.new_scstart;
33 uint32_t scend = dev_priv->state.s3d.new_scend; 33 uint32_t scend = dev_priv->state.s3d.new_scend;
34 scstart = (scstart & ~SAVAGE_SCISSOR_MASK_S3D) | 34 scstart = (scstart & ~SAVAGE_SCISSOR_MASK_S3D) |
35 ((uint32_t)pbox->x1 & 0x000007ff) | 35 ((uint32_t) pbox->x1 & 0x000007ff) |
36 (((uint32_t)pbox->y1 << 16) & 0x07ff0000); 36 (((uint32_t) pbox->y1 << 16) & 0x07ff0000);
37 scend = (scend & ~SAVAGE_SCISSOR_MASK_S3D) | 37 scend = (scend & ~SAVAGE_SCISSOR_MASK_S3D) |
38 (((uint32_t)pbox->x2-1) & 0x000007ff) | 38 (((uint32_t) pbox->x2 - 1) & 0x000007ff) |
39 ((((uint32_t)pbox->y2-1) << 16) & 0x07ff0000); 39 ((((uint32_t) pbox->y2 - 1) << 16) & 0x07ff0000);
40 if (scstart != dev_priv->state.s3d.scstart || 40 if (scstart != dev_priv->state.s3d.scstart ||
41 scend != dev_priv->state.s3d.scend) { 41 scend != dev_priv->state.s3d.scend) {
42 DMA_LOCALS; 42 DMA_LOCALS;
43 BEGIN_DMA(4); 43 BEGIN_DMA(4);
44 DMA_WRITE(BCI_CMD_WAIT|BCI_CMD_WAIT_3D); 44 DMA_WRITE(BCI_CMD_WAIT | BCI_CMD_WAIT_3D);
45 DMA_SET_REGISTERS(SAVAGE_SCSTART_S3D, 2); 45 DMA_SET_REGISTERS(SAVAGE_SCSTART_S3D, 2);
46 DMA_WRITE(scstart); 46 DMA_WRITE(scstart);
47 DMA_WRITE(scend); 47 DMA_WRITE(scend);
48 dev_priv->state.s3d.scstart = scstart; 48 dev_priv->state.s3d.scstart = scstart;
49 dev_priv->state.s3d.scend = scend; 49 dev_priv->state.s3d.scend = scend;
50 dev_priv->waiting = 1; 50 dev_priv->waiting = 1;
51 DMA_COMMIT(); 51 DMA_COMMIT();
52 } 52 }
53} 53}
54 54
55void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv, 55void savage_emit_clip_rect_s4(drm_savage_private_t * dev_priv,
56 drm_clip_rect_t *pbox) 56 drm_clip_rect_t * pbox)
57{ 57{
58 uint32_t drawctrl0 = dev_priv->state.s4.new_drawctrl0; 58 uint32_t drawctrl0 = dev_priv->state.s4.new_drawctrl0;
59 uint32_t drawctrl1 = dev_priv->state.s4.new_drawctrl1; 59 uint32_t drawctrl1 = dev_priv->state.s4.new_drawctrl1;
60 drawctrl0 = (drawctrl0 & ~SAVAGE_SCISSOR_MASK_S4) | 60 drawctrl0 = (drawctrl0 & ~SAVAGE_SCISSOR_MASK_S4) |
61 ((uint32_t)pbox->x1 & 0x000007ff) | 61 ((uint32_t) pbox->x1 & 0x000007ff) |
62 (((uint32_t)pbox->y1 << 12) & 0x00fff000); 62 (((uint32_t) pbox->y1 << 12) & 0x00fff000);
63 drawctrl1 = (drawctrl1 & ~SAVAGE_SCISSOR_MASK_S4) | 63 drawctrl1 = (drawctrl1 & ~SAVAGE_SCISSOR_MASK_S4) |
64 (((uint32_t)pbox->x2-1) & 0x000007ff) | 64 (((uint32_t) pbox->x2 - 1) & 0x000007ff) |
65 ((((uint32_t)pbox->y2-1) << 12) & 0x00fff000); 65 ((((uint32_t) pbox->y2 - 1) << 12) & 0x00fff000);
66 if (drawctrl0 != dev_priv->state.s4.drawctrl0 || 66 if (drawctrl0 != dev_priv->state.s4.drawctrl0 ||
67 drawctrl1 != dev_priv->state.s4.drawctrl1) { 67 drawctrl1 != dev_priv->state.s4.drawctrl1) {
68 DMA_LOCALS; 68 DMA_LOCALS;
69 BEGIN_DMA(4); 69 BEGIN_DMA(4);
70 DMA_WRITE(BCI_CMD_WAIT|BCI_CMD_WAIT_3D); 70 DMA_WRITE(BCI_CMD_WAIT | BCI_CMD_WAIT_3D);
71 DMA_SET_REGISTERS(SAVAGE_DRAWCTRL0_S4, 2); 71 DMA_SET_REGISTERS(SAVAGE_DRAWCTRL0_S4, 2);
72 DMA_WRITE(drawctrl0); 72 DMA_WRITE(drawctrl0);
73 DMA_WRITE(drawctrl1); 73 DMA_WRITE(drawctrl1);
@@ -78,22 +78,23 @@ void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv,
78 } 78 }
79} 79}
80 80
81static int savage_verify_texaddr(drm_savage_private_t *dev_priv, int unit, 81static int savage_verify_texaddr(drm_savage_private_t * dev_priv, int unit,
82 uint32_t addr) 82 uint32_t addr)
83{ 83{
84 if ((addr & 6) != 2) { /* reserved bits */ 84 if ((addr & 6) != 2) { /* reserved bits */
85 DRM_ERROR("bad texAddr%d %08x (reserved bits)\n", unit, addr); 85 DRM_ERROR("bad texAddr%d %08x (reserved bits)\n", unit, addr);
86 return DRM_ERR(EINVAL); 86 return DRM_ERR(EINVAL);
87 } 87 }
88 if (!(addr & 1)) { /* local */ 88 if (!(addr & 1)) { /* local */
89 addr &= ~7; 89 addr &= ~7;
90 if (addr < dev_priv->texture_offset || 90 if (addr < dev_priv->texture_offset ||
91 addr >= dev_priv->texture_offset+dev_priv->texture_size) { 91 addr >= dev_priv->texture_offset + dev_priv->texture_size) {
92 DRM_ERROR("bad texAddr%d %08x (local addr out of range)\n", 92 DRM_ERROR
93 unit, addr); 93 ("bad texAddr%d %08x (local addr out of range)\n",
94 unit, addr);
94 return DRM_ERR(EINVAL); 95 return DRM_ERR(EINVAL);
95 } 96 }
96 } else { /* AGP */ 97 } else { /* AGP */
97 if (!dev_priv->agp_textures) { 98 if (!dev_priv->agp_textures) {
98 DRM_ERROR("bad texAddr%d %08x (AGP not available)\n", 99 DRM_ERROR("bad texAddr%d %08x (AGP not available)\n",
99 unit, addr); 100 unit, addr);
@@ -103,8 +104,9 @@ static int savage_verify_texaddr(drm_savage_private_t *dev_priv, int unit,
103 if (addr < dev_priv->agp_textures->offset || 104 if (addr < dev_priv->agp_textures->offset ||
104 addr >= (dev_priv->agp_textures->offset + 105 addr >= (dev_priv->agp_textures->offset +
105 dev_priv->agp_textures->size)) { 106 dev_priv->agp_textures->size)) {
106 DRM_ERROR("bad texAddr%d %08x (AGP addr out of range)\n", 107 DRM_ERROR
107 unit, addr); 108 ("bad texAddr%d %08x (AGP addr out of range)\n",
109 unit, addr);
108 return DRM_ERR(EINVAL); 110 return DRM_ERR(EINVAL);
109 } 111 }
110 } 112 }
@@ -122,14 +124,14 @@ static int savage_verify_texaddr(drm_savage_private_t *dev_priv, int unit,
122 (dev_priv->state.where & ~(mask)); \ 124 (dev_priv->state.where & ~(mask)); \
123 } \ 125 } \
124} while (0) 126} while (0)
125static int savage_verify_state_s3d(drm_savage_private_t *dev_priv, 127static int savage_verify_state_s3d(drm_savage_private_t * dev_priv,
126 unsigned int start, unsigned int count, 128 unsigned int start, unsigned int count,
127 const uint32_t __user *regs) 129 const uint32_t __user * regs)
128{ 130{
129 if (start < SAVAGE_TEXPALADDR_S3D || 131 if (start < SAVAGE_TEXPALADDR_S3D ||
130 start+count-1 > SAVAGE_DESTTEXRWWATERMARK_S3D) { 132 start + count - 1 > SAVAGE_DESTTEXRWWATERMARK_S3D) {
131 DRM_ERROR("invalid register range (0x%04x-0x%04x)\n", 133 DRM_ERROR("invalid register range (0x%04x-0x%04x)\n",
132 start, start+count-1); 134 start, start + count - 1);
133 return DRM_ERR(EINVAL); 135 return DRM_ERR(EINVAL);
134 } 136 }
135 137
@@ -140,28 +142,29 @@ static int savage_verify_state_s3d(drm_savage_private_t *dev_priv,
140 142
141 /* if any texture regs were changed ... */ 143 /* if any texture regs were changed ... */
142 if (start <= SAVAGE_TEXCTRL_S3D && 144 if (start <= SAVAGE_TEXCTRL_S3D &&
143 start+count > SAVAGE_TEXPALADDR_S3D) { 145 start + count > SAVAGE_TEXPALADDR_S3D) {
144 /* ... check texture state */ 146 /* ... check texture state */
145 SAVE_STATE(SAVAGE_TEXCTRL_S3D, s3d.texctrl); 147 SAVE_STATE(SAVAGE_TEXCTRL_S3D, s3d.texctrl);
146 SAVE_STATE(SAVAGE_TEXADDR_S3D, s3d.texaddr); 148 SAVE_STATE(SAVAGE_TEXADDR_S3D, s3d.texaddr);
147 if (dev_priv->state.s3d.texctrl & SAVAGE_TEXCTRL_TEXEN_MASK) 149 if (dev_priv->state.s3d.texctrl & SAVAGE_TEXCTRL_TEXEN_MASK)
148 return savage_verify_texaddr( 150 return savage_verify_texaddr(dev_priv, 0,
149 dev_priv, 0, dev_priv->state.s3d.texaddr); 151 dev_priv->state.s3d.
152 texaddr);
150 } 153 }
151 154
152 return 0; 155 return 0;
153} 156}
154 157
155static int savage_verify_state_s4(drm_savage_private_t *dev_priv, 158static int savage_verify_state_s4(drm_savage_private_t * dev_priv,
156 unsigned int start, unsigned int count, 159 unsigned int start, unsigned int count,
157 const uint32_t __user *regs) 160 const uint32_t __user * regs)
158{ 161{
159 int ret = 0; 162 int ret = 0;
160 163
161 if (start < SAVAGE_DRAWLOCALCTRL_S4 || 164 if (start < SAVAGE_DRAWLOCALCTRL_S4 ||
162 start+count-1 > SAVAGE_TEXBLENDCOLOR_S4) { 165 start + count - 1 > SAVAGE_TEXBLENDCOLOR_S4) {
163 DRM_ERROR("invalid register range (0x%04x-0x%04x)\n", 166 DRM_ERROR("invalid register range (0x%04x-0x%04x)\n",
164 start, start+count-1); 167 start, start + count - 1);
165 return DRM_ERR(EINVAL); 168 return DRM_ERR(EINVAL);
166 } 169 }
167 170
@@ -171,28 +174,30 @@ static int savage_verify_state_s4(drm_savage_private_t *dev_priv,
171 ~SAVAGE_SCISSOR_MASK_S4); 174 ~SAVAGE_SCISSOR_MASK_S4);
172 175
173 /* if any texture regs were changed ... */ 176 /* if any texture regs were changed ... */
174 if (start <= SAVAGE_TEXDESCR_S4 && 177 if (start <= SAVAGE_TEXDESCR_S4 && start + count > SAVAGE_TEXPALADDR_S4) {
175 start+count > SAVAGE_TEXPALADDR_S4) {
176 /* ... check texture state */ 178 /* ... check texture state */
177 SAVE_STATE(SAVAGE_TEXDESCR_S4, s4.texdescr); 179 SAVE_STATE(SAVAGE_TEXDESCR_S4, s4.texdescr);
178 SAVE_STATE(SAVAGE_TEXADDR0_S4, s4.texaddr0); 180 SAVE_STATE(SAVAGE_TEXADDR0_S4, s4.texaddr0);
179 SAVE_STATE(SAVAGE_TEXADDR1_S4, s4.texaddr1); 181 SAVE_STATE(SAVAGE_TEXADDR1_S4, s4.texaddr1);
180 if (dev_priv->state.s4.texdescr & SAVAGE_TEXDESCR_TEX0EN_MASK) 182 if (dev_priv->state.s4.texdescr & SAVAGE_TEXDESCR_TEX0EN_MASK)
181 ret |= savage_verify_texaddr( 183 ret |=
182 dev_priv, 0, dev_priv->state.s4.texaddr0); 184 savage_verify_texaddr(dev_priv, 0,
185 dev_priv->state.s4.texaddr0);
183 if (dev_priv->state.s4.texdescr & SAVAGE_TEXDESCR_TEX1EN_MASK) 186 if (dev_priv->state.s4.texdescr & SAVAGE_TEXDESCR_TEX1EN_MASK)
184 ret |= savage_verify_texaddr( 187 ret |=
185 dev_priv, 1, dev_priv->state.s4.texaddr1); 188 savage_verify_texaddr(dev_priv, 1,
189 dev_priv->state.s4.texaddr1);
186 } 190 }
187 191
188 return ret; 192 return ret;
189} 193}
194
190#undef SAVE_STATE 195#undef SAVE_STATE
191#undef SAVE_STATE_MASK 196#undef SAVE_STATE_MASK
192 197
193static int savage_dispatch_state(drm_savage_private_t *dev_priv, 198static int savage_dispatch_state(drm_savage_private_t * dev_priv,
194 const drm_savage_cmd_header_t *cmd_header, 199 const drm_savage_cmd_header_t * cmd_header,
195 const uint32_t __user *regs) 200 const uint32_t __user * regs)
196{ 201{
197 unsigned int count = cmd_header->state.count; 202 unsigned int count = cmd_header->state.count;
198 unsigned int start = cmd_header->state.start; 203 unsigned int start = cmd_header->state.start;
@@ -204,7 +209,7 @@ static int savage_dispatch_state(drm_savage_private_t *dev_priv,
204 if (!count) 209 if (!count)
205 return 0; 210 return 0;
206 211
207 if (DRM_VERIFYAREA_READ(regs, count*4)) 212 if (DRM_VERIFYAREA_READ(regs, count * 4))
208 return DRM_ERR(EFAULT); 213 return DRM_ERR(EFAULT);
209 214
210 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 215 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
@@ -213,14 +218,14 @@ static int savage_dispatch_state(drm_savage_private_t *dev_priv,
213 return ret; 218 return ret;
214 /* scissor regs are emitted in savage_dispatch_draw */ 219 /* scissor regs are emitted in savage_dispatch_draw */
215 if (start < SAVAGE_SCSTART_S3D) { 220 if (start < SAVAGE_SCSTART_S3D) {
216 if (start+count > SAVAGE_SCEND_S3D+1) 221 if (start + count > SAVAGE_SCEND_S3D + 1)
217 count2 = count - (SAVAGE_SCEND_S3D+1 - start); 222 count2 = count - (SAVAGE_SCEND_S3D + 1 - start);
218 if (start+count > SAVAGE_SCSTART_S3D) 223 if (start + count > SAVAGE_SCSTART_S3D)
219 count = SAVAGE_SCSTART_S3D - start; 224 count = SAVAGE_SCSTART_S3D - start;
220 } else if (start <= SAVAGE_SCEND_S3D) { 225 } else if (start <= SAVAGE_SCEND_S3D) {
221 if (start+count > SAVAGE_SCEND_S3D+1) { 226 if (start + count > SAVAGE_SCEND_S3D + 1) {
222 count -= SAVAGE_SCEND_S3D+1 - start; 227 count -= SAVAGE_SCEND_S3D + 1 - start;
223 start = SAVAGE_SCEND_S3D+1; 228 start = SAVAGE_SCEND_S3D + 1;
224 } else 229 } else
225 return 0; 230 return 0;
226 } 231 }
@@ -230,23 +235,24 @@ static int savage_dispatch_state(drm_savage_private_t *dev_priv,
230 return ret; 235 return ret;
231 /* scissor regs are emitted in savage_dispatch_draw */ 236 /* scissor regs are emitted in savage_dispatch_draw */
232 if (start < SAVAGE_DRAWCTRL0_S4) { 237 if (start < SAVAGE_DRAWCTRL0_S4) {
233 if (start+count > SAVAGE_DRAWCTRL1_S4+1) 238 if (start + count > SAVAGE_DRAWCTRL1_S4 + 1)
234 count2 = count - (SAVAGE_DRAWCTRL1_S4+1 - start); 239 count2 =
235 if (start+count > SAVAGE_DRAWCTRL0_S4) 240 count - (SAVAGE_DRAWCTRL1_S4 + 1 - start);
241 if (start + count > SAVAGE_DRAWCTRL0_S4)
236 count = SAVAGE_DRAWCTRL0_S4 - start; 242 count = SAVAGE_DRAWCTRL0_S4 - start;
237 } else if (start <= SAVAGE_DRAWCTRL1_S4) { 243 } else if (start <= SAVAGE_DRAWCTRL1_S4) {
238 if (start+count > SAVAGE_DRAWCTRL1_S4+1) { 244 if (start + count > SAVAGE_DRAWCTRL1_S4 + 1) {
239 count -= SAVAGE_DRAWCTRL1_S4+1 - start; 245 count -= SAVAGE_DRAWCTRL1_S4 + 1 - start;
240 start = SAVAGE_DRAWCTRL1_S4+1; 246 start = SAVAGE_DRAWCTRL1_S4 + 1;
241 } else 247 } else
242 return 0; 248 return 0;
243 } 249 }
244 } 250 }
245 251
246 bci_size = count + (count+254)/255 + count2 + (count2+254)/255; 252 bci_size = count + (count + 254) / 255 + count2 + (count2 + 254) / 255;
247 253
248 if (cmd_header->state.global) { 254 if (cmd_header->state.global) {
249 BEGIN_DMA(bci_size+1); 255 BEGIN_DMA(bci_size + 1);
250 DMA_WRITE(BCI_CMD_WAIT | BCI_CMD_WAIT_3D); 256 DMA_WRITE(BCI_CMD_WAIT | BCI_CMD_WAIT_3D);
251 dev_priv->waiting = 1; 257 dev_priv->waiting = 1;
252 } else { 258 } else {
@@ -273,9 +279,9 @@ static int savage_dispatch_state(drm_savage_private_t *dev_priv,
273 return 0; 279 return 0;
274} 280}
275 281
276static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv, 282static int savage_dispatch_dma_prim(drm_savage_private_t * dev_priv,
277 const drm_savage_cmd_header_t *cmd_header, 283 const drm_savage_cmd_header_t * cmd_header,
278 const drm_buf_t *dmabuf) 284 const drm_buf_t * dmabuf)
279{ 285{
280 unsigned char reorder = 0; 286 unsigned char reorder = 0;
281 unsigned int prim = cmd_header->prim.prim; 287 unsigned int prim = cmd_header->prim.prim;
@@ -286,8 +292,8 @@ static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv,
286 BCI_LOCALS; 292 BCI_LOCALS;
287 293
288 if (!dmabuf) { 294 if (!dmabuf) {
289 DRM_ERROR("called without dma buffers!\n"); 295 DRM_ERROR("called without dma buffers!\n");
290 return DRM_ERR(EINVAL); 296 return DRM_ERR(EINVAL);
291 } 297 }
292 298
293 if (!n) 299 if (!n)
@@ -307,8 +313,9 @@ static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv,
307 case SAVAGE_PRIM_TRISTRIP: 313 case SAVAGE_PRIM_TRISTRIP:
308 case SAVAGE_PRIM_TRIFAN: 314 case SAVAGE_PRIM_TRIFAN:
309 if (n < 3) { 315 if (n < 3) {
310 DRM_ERROR("wrong number of vertices %u in TRIFAN/STRIP\n", 316 DRM_ERROR
311 n); 317 ("wrong number of vertices %u in TRIFAN/STRIP\n",
318 n);
312 return DRM_ERR(EINVAL); 319 return DRM_ERR(EINVAL);
313 } 320 }
314 break; 321 break;
@@ -319,17 +326,15 @@ static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv,
319 326
320 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 327 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
321 if (skip != 0) { 328 if (skip != 0) {
322 DRM_ERROR("invalid skip flags 0x%04x for DMA\n", 329 DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip);
323 skip);
324 return DRM_ERR(EINVAL); 330 return DRM_ERR(EINVAL);
325 } 331 }
326 } else { 332 } else {
327 unsigned int size = 10 - (skip & 1) - (skip >> 1 & 1) - 333 unsigned int size = 10 - (skip & 1) - (skip >> 1 & 1) -
328 (skip >> 2 & 1) - (skip >> 3 & 1) - (skip >> 4 & 1) - 334 (skip >> 2 & 1) - (skip >> 3 & 1) - (skip >> 4 & 1) -
329 (skip >> 5 & 1) - (skip >> 6 & 1) - (skip >> 7 & 1); 335 (skip >> 5 & 1) - (skip >> 6 & 1) - (skip >> 7 & 1);
330 if (skip > SAVAGE_SKIP_ALL_S4 || size != 8) { 336 if (skip > SAVAGE_SKIP_ALL_S4 || size != 8) {
331 DRM_ERROR("invalid skip flags 0x%04x for DMA\n", 337 DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip);
332 skip);
333 return DRM_ERR(EINVAL); 338 return DRM_ERR(EINVAL);
334 } 339 }
335 if (reorder) { 340 if (reorder) {
@@ -338,9 +343,9 @@ static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv,
338 } 343 }
339 } 344 }
340 345
341 if (start + n > dmabuf->total/32) { 346 if (start + n > dmabuf->total / 32) {
342 DRM_ERROR("vertex indices (%u-%u) out of range (0-%u)\n", 347 DRM_ERROR("vertex indices (%u-%u) out of range (0-%u)\n",
343 start, start + n - 1, dmabuf->total/32); 348 start, start + n - 1, dmabuf->total / 32);
344 return DRM_ERR(EINVAL); 349 return DRM_ERR(EINVAL);
345 } 350 }
346 351
@@ -375,32 +380,33 @@ static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv,
375 /* Need to reorder indices for correct flat 380 /* Need to reorder indices for correct flat
376 * shading while preserving the clock sense 381 * shading while preserving the clock sense
377 * for correct culling. Only on Savage3D. */ 382 * for correct culling. Only on Savage3D. */
378 int reorder[3] = {-1, -1, -1}; 383 int reorder[3] = { -1, -1, -1 };
379 reorder[start%3] = 2; 384 reorder[start % 3] = 2;
380 385
381 BEGIN_BCI((count+1+1)/2); 386 BEGIN_BCI((count + 1 + 1) / 2);
382 BCI_DRAW_INDICES_S3D(count, prim, start+2); 387 BCI_DRAW_INDICES_S3D(count, prim, start + 2);
383 388
384 for (i = start+1; i+1 < start+count; i += 2) 389 for (i = start + 1; i + 1 < start + count; i += 2)
385 BCI_WRITE((i + reorder[i % 3]) | 390 BCI_WRITE((i + reorder[i % 3]) |
386 ((i+1 + reorder[(i+1) % 3]) << 16)); 391 ((i + 1 +
387 if (i < start+count) 392 reorder[(i + 1) % 3]) << 16));
388 BCI_WRITE(i + reorder[i%3]); 393 if (i < start + count)
394 BCI_WRITE(i + reorder[i % 3]);
389 } else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 395 } else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
390 BEGIN_BCI((count+1+1)/2); 396 BEGIN_BCI((count + 1 + 1) / 2);
391 BCI_DRAW_INDICES_S3D(count, prim, start); 397 BCI_DRAW_INDICES_S3D(count, prim, start);
392 398
393 for (i = start+1; i+1 < start+count; i += 2) 399 for (i = start + 1; i + 1 < start + count; i += 2)
394 BCI_WRITE(i | ((i+1) << 16)); 400 BCI_WRITE(i | ((i + 1) << 16));
395 if (i < start+count) 401 if (i < start + count)
396 BCI_WRITE(i); 402 BCI_WRITE(i);
397 } else { 403 } else {
398 BEGIN_BCI((count+2+1)/2); 404 BEGIN_BCI((count + 2 + 1) / 2);
399 BCI_DRAW_INDICES_S4(count, prim, skip); 405 BCI_DRAW_INDICES_S4(count, prim, skip);
400 406
401 for (i = start; i+1 < start+count; i += 2) 407 for (i = start; i + 1 < start + count; i += 2)
402 BCI_WRITE(i | ((i+1) << 16)); 408 BCI_WRITE(i | ((i + 1) << 16));
403 if (i < start+count) 409 if (i < start + count)
404 BCI_WRITE(i); 410 BCI_WRITE(i);
405 } 411 }
406 412
@@ -413,11 +419,10 @@ static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv,
413 return 0; 419 return 0;
414} 420}
415 421
416static int savage_dispatch_vb_prim(drm_savage_private_t *dev_priv, 422static int savage_dispatch_vb_prim(drm_savage_private_t * dev_priv,
417 const drm_savage_cmd_header_t *cmd_header, 423 const drm_savage_cmd_header_t * cmd_header,
418 const uint32_t __user *vtxbuf, 424 const uint32_t __user * vtxbuf,
419 unsigned int vb_size, 425 unsigned int vb_size, unsigned int vb_stride)
420 unsigned int vb_stride)
421{ 426{
422 unsigned char reorder = 0; 427 unsigned char reorder = 0;
423 unsigned int prim = cmd_header->prim.prim; 428 unsigned int prim = cmd_header->prim.prim;
@@ -445,8 +450,9 @@ static int savage_dispatch_vb_prim(drm_savage_private_t *dev_priv,
445 case SAVAGE_PRIM_TRISTRIP: 450 case SAVAGE_PRIM_TRISTRIP:
446 case SAVAGE_PRIM_TRIFAN: 451 case SAVAGE_PRIM_TRIFAN:
447 if (n < 3) { 452 if (n < 3) {
448 DRM_ERROR("wrong number of vertices %u in TRIFAN/STRIP\n", 453 DRM_ERROR
449 n); 454 ("wrong number of vertices %u in TRIFAN/STRIP\n",
455 n);
450 return DRM_ERR(EINVAL); 456 return DRM_ERR(EINVAL);
451 } 457 }
452 break; 458 break;
@@ -460,18 +466,18 @@ static int savage_dispatch_vb_prim(drm_savage_private_t *dev_priv,
460 DRM_ERROR("invalid skip flags 0x%04x\n", skip); 466 DRM_ERROR("invalid skip flags 0x%04x\n", skip);
461 return DRM_ERR(EINVAL); 467 return DRM_ERR(EINVAL);
462 } 468 }
463 vtx_size = 8; /* full vertex */ 469 vtx_size = 8; /* full vertex */
464 } else { 470 } else {
465 if (skip > SAVAGE_SKIP_ALL_S4) { 471 if (skip > SAVAGE_SKIP_ALL_S4) {
466 DRM_ERROR("invalid skip flags 0x%04x\n", skip); 472 DRM_ERROR("invalid skip flags 0x%04x\n", skip);
467 return DRM_ERR(EINVAL); 473 return DRM_ERR(EINVAL);
468 } 474 }
469 vtx_size = 10; /* full vertex */ 475 vtx_size = 10; /* full vertex */
470 } 476 }
471 477
472 vtx_size -= (skip & 1) + (skip >> 1 & 1) + 478 vtx_size -= (skip & 1) + (skip >> 1 & 1) +
473 (skip >> 2 & 1) + (skip >> 3 & 1) + (skip >> 4 & 1) + 479 (skip >> 2 & 1) + (skip >> 3 & 1) + (skip >> 4 & 1) +
474 (skip >> 5 & 1) + (skip >> 6 & 1) + (skip >> 7 & 1); 480 (skip >> 5 & 1) + (skip >> 6 & 1) + (skip >> 7 & 1);
475 481
476 if (vtx_size > vb_stride) { 482 if (vtx_size > vb_stride) {
477 DRM_ERROR("vertex size greater than vb stride (%u > %u)\n", 483 DRM_ERROR("vertex size greater than vb stride (%u > %u)\n",
@@ -479,9 +485,9 @@ static int savage_dispatch_vb_prim(drm_savage_private_t *dev_priv,
479 return DRM_ERR(EINVAL); 485 return DRM_ERR(EINVAL);
480 } 486 }
481 487
482 if (start + n > vb_size / (vb_stride*4)) { 488 if (start + n > vb_size / (vb_stride * 4)) {
483 DRM_ERROR("vertex indices (%u-%u) out of range (0-%u)\n", 489 DRM_ERROR("vertex indices (%u-%u) out of range (0-%u)\n",
484 start, start + n - 1, vb_size / (vb_stride*4)); 490 start, start + n - 1, vb_size / (vb_stride * 4));
485 return DRM_ERR(EINVAL); 491 return DRM_ERR(EINVAL);
486 } 492 }
487 493
@@ -493,31 +499,31 @@ static int savage_dispatch_vb_prim(drm_savage_private_t *dev_priv,
493 /* Need to reorder vertices for correct flat 499 /* Need to reorder vertices for correct flat
494 * shading while preserving the clock sense 500 * shading while preserving the clock sense
495 * for correct culling. Only on Savage3D. */ 501 * for correct culling. Only on Savage3D. */
496 int reorder[3] = {-1, -1, -1}; 502 int reorder[3] = { -1, -1, -1 };
497 reorder[start%3] = 2; 503 reorder[start % 3] = 2;
498 504
499 BEGIN_DMA(count*vtx_size+1); 505 BEGIN_DMA(count * vtx_size + 1);
500 DMA_DRAW_PRIMITIVE(count, prim, skip); 506 DMA_DRAW_PRIMITIVE(count, prim, skip);
501 507
502 for (i = start; i < start+count; ++i) { 508 for (i = start; i < start + count; ++i) {
503 unsigned int j = i + reorder[i % 3]; 509 unsigned int j = i + reorder[i % 3];
504 DMA_COPY_FROM_USER(&vtxbuf[vb_stride*j], 510 DMA_COPY_FROM_USER(&vtxbuf[vb_stride * j],
505 vtx_size); 511 vtx_size);
506 } 512 }
507 513
508 DMA_COMMIT(); 514 DMA_COMMIT();
509 } else { 515 } else {
510 BEGIN_DMA(count*vtx_size+1); 516 BEGIN_DMA(count * vtx_size + 1);
511 DMA_DRAW_PRIMITIVE(count, prim, skip); 517 DMA_DRAW_PRIMITIVE(count, prim, skip);
512 518
513 if (vb_stride == vtx_size) { 519 if (vb_stride == vtx_size) {
514 DMA_COPY_FROM_USER(&vtxbuf[vb_stride*start], 520 DMA_COPY_FROM_USER(&vtxbuf[vb_stride * start],
515 vtx_size*count); 521 vtx_size * count);
516 } else { 522 } else {
517 for (i = start; i < start+count; ++i) { 523 for (i = start; i < start + count; ++i) {
518 DMA_COPY_FROM_USER( 524 DMA_COPY_FROM_USER(&vtxbuf
519 &vtxbuf[vb_stride*i], 525 [vb_stride * i],
520 vtx_size); 526 vtx_size);
521 } 527 }
522 } 528 }
523 529
@@ -533,10 +539,10 @@ static int savage_dispatch_vb_prim(drm_savage_private_t *dev_priv,
533 return 0; 539 return 0;
534} 540}
535 541
536static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv, 542static int savage_dispatch_dma_idx(drm_savage_private_t * dev_priv,
537 const drm_savage_cmd_header_t *cmd_header, 543 const drm_savage_cmd_header_t * cmd_header,
538 const uint16_t __user *usr_idx, 544 const uint16_t __user * usr_idx,
539 const drm_buf_t *dmabuf) 545 const drm_buf_t * dmabuf)
540{ 546{
541 unsigned char reorder = 0; 547 unsigned char reorder = 0;
542 unsigned int prim = cmd_header->idx.prim; 548 unsigned int prim = cmd_header->idx.prim;
@@ -546,8 +552,8 @@ static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv,
546 BCI_LOCALS; 552 BCI_LOCALS;
547 553
548 if (!dmabuf) { 554 if (!dmabuf) {
549 DRM_ERROR("called without dma buffers!\n"); 555 DRM_ERROR("called without dma buffers!\n");
550 return DRM_ERR(EINVAL); 556 return DRM_ERR(EINVAL);
551 } 557 }
552 558
553 if (!n) 559 if (!n)
@@ -559,16 +565,15 @@ static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv,
559 prim = SAVAGE_PRIM_TRILIST; 565 prim = SAVAGE_PRIM_TRILIST;
560 case SAVAGE_PRIM_TRILIST: 566 case SAVAGE_PRIM_TRILIST:
561 if (n % 3 != 0) { 567 if (n % 3 != 0) {
562 DRM_ERROR("wrong number of indices %u in TRILIST\n", 568 DRM_ERROR("wrong number of indices %u in TRILIST\n", n);
563 n);
564 return DRM_ERR(EINVAL); 569 return DRM_ERR(EINVAL);
565 } 570 }
566 break; 571 break;
567 case SAVAGE_PRIM_TRISTRIP: 572 case SAVAGE_PRIM_TRISTRIP:
568 case SAVAGE_PRIM_TRIFAN: 573 case SAVAGE_PRIM_TRIFAN:
569 if (n < 3) { 574 if (n < 3) {
570 DRM_ERROR("wrong number of indices %u in TRIFAN/STRIP\n", 575 DRM_ERROR
571 n); 576 ("wrong number of indices %u in TRIFAN/STRIP\n", n);
572 return DRM_ERR(EINVAL); 577 return DRM_ERR(EINVAL);
573 } 578 }
574 break; 579 break;
@@ -579,17 +584,15 @@ static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv,
579 584
580 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 585 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
581 if (skip != 0) { 586 if (skip != 0) {
582 DRM_ERROR("invalid skip flags 0x%04x for DMA\n", 587 DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip);
583 skip);
584 return DRM_ERR(EINVAL); 588 return DRM_ERR(EINVAL);
585 } 589 }
586 } else { 590 } else {
587 unsigned int size = 10 - (skip & 1) - (skip >> 1 & 1) - 591 unsigned int size = 10 - (skip & 1) - (skip >> 1 & 1) -
588 (skip >> 2 & 1) - (skip >> 3 & 1) - (skip >> 4 & 1) - 592 (skip >> 2 & 1) - (skip >> 3 & 1) - (skip >> 4 & 1) -
589 (skip >> 5 & 1) - (skip >> 6 & 1) - (skip >> 7 & 1); 593 (skip >> 5 & 1) - (skip >> 6 & 1) - (skip >> 7 & 1);
590 if (skip > SAVAGE_SKIP_ALL_S4 || size != 8) { 594 if (skip > SAVAGE_SKIP_ALL_S4 || size != 8) {
591 DRM_ERROR("invalid skip flags 0x%04x for DMA\n", 595 DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip);
592 skip);
593 return DRM_ERR(EINVAL); 596 return DRM_ERR(EINVAL);
594 } 597 }
595 if (reorder) { 598 if (reorder) {
@@ -629,11 +632,11 @@ static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv,
629 uint16_t idx[255]; 632 uint16_t idx[255];
630 633
631 /* Copy and check indices */ 634 /* Copy and check indices */
632 DRM_COPY_FROM_USER_UNCHECKED(idx, usr_idx, count*2); 635 DRM_COPY_FROM_USER_UNCHECKED(idx, usr_idx, count * 2);
633 for (i = 0; i < count; ++i) { 636 for (i = 0; i < count; ++i) {
634 if (idx[i] > dmabuf->total/32) { 637 if (idx[i] > dmabuf->total / 32) {
635 DRM_ERROR("idx[%u]=%u out of range (0-%u)\n", 638 DRM_ERROR("idx[%u]=%u out of range (0-%u)\n",
636 i, idx[i], dmabuf->total/32); 639 i, idx[i], dmabuf->total / 32);
637 return DRM_ERR(EINVAL); 640 return DRM_ERR(EINVAL);
638 } 641 }
639 } 642 }
@@ -642,30 +645,31 @@ static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv,
642 /* Need to reorder indices for correct flat 645 /* Need to reorder indices for correct flat
643 * shading while preserving the clock sense 646 * shading while preserving the clock sense
644 * for correct culling. Only on Savage3D. */ 647 * for correct culling. Only on Savage3D. */
645 int reorder[3] = {2, -1, -1}; 648 int reorder[3] = { 2, -1, -1 };
646 649
647 BEGIN_BCI((count+1+1)/2); 650 BEGIN_BCI((count + 1 + 1) / 2);
648 BCI_DRAW_INDICES_S3D(count, prim, idx[2]); 651 BCI_DRAW_INDICES_S3D(count, prim, idx[2]);
649 652
650 for (i = 1; i+1 < count; i += 2) 653 for (i = 1; i + 1 < count; i += 2)
651 BCI_WRITE(idx[i + reorder[i % 3]] | 654 BCI_WRITE(idx[i + reorder[i % 3]] |
652 (idx[i+1 + reorder[(i+1) % 3]] << 16)); 655 (idx[i + 1 + reorder[(i + 1) % 3]] <<
656 16));
653 if (i < count) 657 if (i < count)
654 BCI_WRITE(idx[i + reorder[i%3]]); 658 BCI_WRITE(idx[i + reorder[i % 3]]);
655 } else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 659 } else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
656 BEGIN_BCI((count+1+1)/2); 660 BEGIN_BCI((count + 1 + 1) / 2);
657 BCI_DRAW_INDICES_S3D(count, prim, idx[0]); 661 BCI_DRAW_INDICES_S3D(count, prim, idx[0]);
658 662
659 for (i = 1; i+1 < count; i += 2) 663 for (i = 1; i + 1 < count; i += 2)
660 BCI_WRITE(idx[i] | (idx[i+1] << 16)); 664 BCI_WRITE(idx[i] | (idx[i + 1] << 16));
661 if (i < count) 665 if (i < count)
662 BCI_WRITE(idx[i]); 666 BCI_WRITE(idx[i]);
663 } else { 667 } else {
664 BEGIN_BCI((count+2+1)/2); 668 BEGIN_BCI((count + 2 + 1) / 2);
665 BCI_DRAW_INDICES_S4(count, prim, skip); 669 BCI_DRAW_INDICES_S4(count, prim, skip);
666 670
667 for (i = 0; i+1 < count; i += 2) 671 for (i = 0; i + 1 < count; i += 2)
668 BCI_WRITE(idx[i] | (idx[i+1] << 16)); 672 BCI_WRITE(idx[i] | (idx[i + 1] << 16));
669 if (i < count) 673 if (i < count)
670 BCI_WRITE(idx[i]); 674 BCI_WRITE(idx[i]);
671 } 675 }
@@ -679,12 +683,11 @@ static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv,
679 return 0; 683 return 0;
680} 684}
681 685
682static int savage_dispatch_vb_idx(drm_savage_private_t *dev_priv, 686static int savage_dispatch_vb_idx(drm_savage_private_t * dev_priv,
683 const drm_savage_cmd_header_t *cmd_header, 687 const drm_savage_cmd_header_t * cmd_header,
684 const uint16_t __user *usr_idx, 688 const uint16_t __user * usr_idx,
685 const uint32_t __user *vtxbuf, 689 const uint32_t __user * vtxbuf,
686 unsigned int vb_size, 690 unsigned int vb_size, unsigned int vb_stride)
687 unsigned int vb_stride)
688{ 691{
689 unsigned char reorder = 0; 692 unsigned char reorder = 0;
690 unsigned int prim = cmd_header->idx.prim; 693 unsigned int prim = cmd_header->idx.prim;
@@ -703,16 +706,15 @@ static int savage_dispatch_vb_idx(drm_savage_private_t *dev_priv,
703 prim = SAVAGE_PRIM_TRILIST; 706 prim = SAVAGE_PRIM_TRILIST;
704 case SAVAGE_PRIM_TRILIST: 707 case SAVAGE_PRIM_TRILIST:
705 if (n % 3 != 0) { 708 if (n % 3 != 0) {
706 DRM_ERROR("wrong number of indices %u in TRILIST\n", 709 DRM_ERROR("wrong number of indices %u in TRILIST\n", n);
707 n);
708 return DRM_ERR(EINVAL); 710 return DRM_ERR(EINVAL);
709 } 711 }
710 break; 712 break;
711 case SAVAGE_PRIM_TRISTRIP: 713 case SAVAGE_PRIM_TRISTRIP:
712 case SAVAGE_PRIM_TRIFAN: 714 case SAVAGE_PRIM_TRIFAN:
713 if (n < 3) { 715 if (n < 3) {
714 DRM_ERROR("wrong number of indices %u in TRIFAN/STRIP\n", 716 DRM_ERROR
715 n); 717 ("wrong number of indices %u in TRIFAN/STRIP\n", n);
716 return DRM_ERR(EINVAL); 718 return DRM_ERR(EINVAL);
717 } 719 }
718 break; 720 break;
@@ -726,18 +728,18 @@ static int savage_dispatch_vb_idx(drm_savage_private_t *dev_priv,
726 DRM_ERROR("invalid skip flags 0x%04x\n", skip); 728 DRM_ERROR("invalid skip flags 0x%04x\n", skip);
727 return DRM_ERR(EINVAL); 729 return DRM_ERR(EINVAL);
728 } 730 }
729 vtx_size = 8; /* full vertex */ 731 vtx_size = 8; /* full vertex */
730 } else { 732 } else {
731 if (skip > SAVAGE_SKIP_ALL_S4) { 733 if (skip > SAVAGE_SKIP_ALL_S4) {
732 DRM_ERROR("invalid skip flags 0x%04x\n", skip); 734 DRM_ERROR("invalid skip flags 0x%04x\n", skip);
733 return DRM_ERR(EINVAL); 735 return DRM_ERR(EINVAL);
734 } 736 }
735 vtx_size = 10; /* full vertex */ 737 vtx_size = 10; /* full vertex */
736 } 738 }
737 739
738 vtx_size -= (skip & 1) + (skip >> 1 & 1) + 740 vtx_size -= (skip & 1) + (skip >> 1 & 1) +
739 (skip >> 2 & 1) + (skip >> 3 & 1) + (skip >> 4 & 1) + 741 (skip >> 2 & 1) + (skip >> 3 & 1) + (skip >> 4 & 1) +
740 (skip >> 5 & 1) + (skip >> 6 & 1) + (skip >> 7 & 1); 742 (skip >> 5 & 1) + (skip >> 6 & 1) + (skip >> 7 & 1);
741 743
742 if (vtx_size > vb_stride) { 744 if (vtx_size > vb_stride) {
743 DRM_ERROR("vertex size greater than vb stride (%u > %u)\n", 745 DRM_ERROR("vertex size greater than vb stride (%u > %u)\n",
@@ -753,11 +755,11 @@ static int savage_dispatch_vb_idx(drm_savage_private_t *dev_priv,
753 uint16_t idx[255]; 755 uint16_t idx[255];
754 756
755 /* Copy and check indices */ 757 /* Copy and check indices */
756 DRM_COPY_FROM_USER_UNCHECKED(idx, usr_idx, count*2); 758 DRM_COPY_FROM_USER_UNCHECKED(idx, usr_idx, count * 2);
757 for (i = 0; i < count; ++i) { 759 for (i = 0; i < count; ++i) {
758 if (idx[i] > vb_size / (vb_stride*4)) { 760 if (idx[i] > vb_size / (vb_stride * 4)) {
759 DRM_ERROR("idx[%u]=%u out of range (0-%u)\n", 761 DRM_ERROR("idx[%u]=%u out of range (0-%u)\n",
760 i, idx[i], vb_size / (vb_stride*4)); 762 i, idx[i], vb_size / (vb_stride * 4));
761 return DRM_ERR(EINVAL); 763 return DRM_ERR(EINVAL);
762 } 764 }
763 } 765 }
@@ -766,25 +768,25 @@ static int savage_dispatch_vb_idx(drm_savage_private_t *dev_priv,
766 /* Need to reorder vertices for correct flat 768 /* Need to reorder vertices for correct flat
767 * shading while preserving the clock sense 769 * shading while preserving the clock sense
768 * for correct culling. Only on Savage3D. */ 770 * for correct culling. Only on Savage3D. */
769 int reorder[3] = {2, -1, -1}; 771 int reorder[3] = { 2, -1, -1 };
770 772
771 BEGIN_DMA(count*vtx_size+1); 773 BEGIN_DMA(count * vtx_size + 1);
772 DMA_DRAW_PRIMITIVE(count, prim, skip); 774 DMA_DRAW_PRIMITIVE(count, prim, skip);
773 775
774 for (i = 0; i < count; ++i) { 776 for (i = 0; i < count; ++i) {
775 unsigned int j = idx[i + reorder[i % 3]]; 777 unsigned int j = idx[i + reorder[i % 3]];
776 DMA_COPY_FROM_USER(&vtxbuf[vb_stride*j], 778 DMA_COPY_FROM_USER(&vtxbuf[vb_stride * j],
777 vtx_size); 779 vtx_size);
778 } 780 }
779 781
780 DMA_COMMIT(); 782 DMA_COMMIT();
781 } else { 783 } else {
782 BEGIN_DMA(count*vtx_size+1); 784 BEGIN_DMA(count * vtx_size + 1);
783 DMA_DRAW_PRIMITIVE(count, prim, skip); 785 DMA_DRAW_PRIMITIVE(count, prim, skip);
784 786
785 for (i = 0; i < count; ++i) { 787 for (i = 0; i < count; ++i) {
786 unsigned int j = idx[i]; 788 unsigned int j = idx[i];
787 DMA_COPY_FROM_USER(&vtxbuf[vb_stride*j], 789 DMA_COPY_FROM_USER(&vtxbuf[vb_stride * j],
788 vtx_size); 790 vtx_size);
789 } 791 }
790 792
@@ -800,11 +802,11 @@ static int savage_dispatch_vb_idx(drm_savage_private_t *dev_priv,
800 return 0; 802 return 0;
801} 803}
802 804
803static int savage_dispatch_clear(drm_savage_private_t *dev_priv, 805static int savage_dispatch_clear(drm_savage_private_t * dev_priv,
804 const drm_savage_cmd_header_t *cmd_header, 806 const drm_savage_cmd_header_t * cmd_header,
805 const drm_savage_cmd_header_t __user *data, 807 const drm_savage_cmd_header_t __user * data,
806 unsigned int nbox, 808 unsigned int nbox,
807 const drm_clip_rect_t __user *usr_boxes) 809 const drm_clip_rect_t __user * usr_boxes)
808{ 810{
809 unsigned int flags = cmd_header->clear0.flags, mask, value; 811 unsigned int flags = cmd_header->clear0.flags, mask, value;
810 unsigned int clear_cmd; 812 unsigned int clear_cmd;
@@ -814,18 +816,17 @@ static int savage_dispatch_clear(drm_savage_private_t *dev_priv,
814 if (nbox == 0) 816 if (nbox == 0)
815 return 0; 817 return 0;
816 818
817 DRM_GET_USER_UNCHECKED(mask, &((const drm_savage_cmd_header_t*)data) 819 DRM_GET_USER_UNCHECKED(mask, &((const drm_savage_cmd_header_t *)data)
818 ->clear1.mask); 820 ->clear1.mask);
819 DRM_GET_USER_UNCHECKED(value, &((const drm_savage_cmd_header_t*)data) 821 DRM_GET_USER_UNCHECKED(value, &((const drm_savage_cmd_header_t *)data)
820 ->clear1.value); 822 ->clear1.value);
821 823
822 clear_cmd = BCI_CMD_RECT | BCI_CMD_RECT_XP | BCI_CMD_RECT_YP | 824 clear_cmd = BCI_CMD_RECT | BCI_CMD_RECT_XP | BCI_CMD_RECT_YP |
823 BCI_CMD_SEND_COLOR | BCI_CMD_DEST_PBD_NEW; 825 BCI_CMD_SEND_COLOR | BCI_CMD_DEST_PBD_NEW;
824 BCI_CMD_SET_ROP(clear_cmd,0xCC); 826 BCI_CMD_SET_ROP(clear_cmd, 0xCC);
825 827
826 nbufs = ((flags & SAVAGE_FRONT) ? 1 : 0) + 828 nbufs = ((flags & SAVAGE_FRONT) ? 1 : 0) +
827 ((flags & SAVAGE_BACK) ? 1 : 0) + 829 ((flags & SAVAGE_BACK) ? 1 : 0) + ((flags & SAVAGE_DEPTH) ? 1 : 0);
828 ((flags & SAVAGE_DEPTH) ? 1 : 0);
829 if (nbufs == 0) 830 if (nbufs == 0)
830 return 0; 831 return 0;
831 832
@@ -844,12 +845,12 @@ static int savage_dispatch_clear(drm_savage_private_t *dev_priv,
844 x = box.x1, y = box.y1; 845 x = box.x1, y = box.y1;
845 w = box.x2 - box.x1; 846 w = box.x2 - box.x1;
846 h = box.y2 - box.y1; 847 h = box.y2 - box.y1;
847 BEGIN_DMA(nbufs*6); 848 BEGIN_DMA(nbufs * 6);
848 for (buf = SAVAGE_FRONT; buf <= SAVAGE_DEPTH; buf <<= 1) { 849 for (buf = SAVAGE_FRONT; buf <= SAVAGE_DEPTH; buf <<= 1) {
849 if (!(flags & buf)) 850 if (!(flags & buf))
850 continue; 851 continue;
851 DMA_WRITE(clear_cmd); 852 DMA_WRITE(clear_cmd);
852 switch(buf) { 853 switch (buf) {
853 case SAVAGE_FRONT: 854 case SAVAGE_FRONT:
854 DMA_WRITE(dev_priv->front_offset); 855 DMA_WRITE(dev_priv->front_offset);
855 DMA_WRITE(dev_priv->front_bd); 856 DMA_WRITE(dev_priv->front_bd);
@@ -880,9 +881,9 @@ static int savage_dispatch_clear(drm_savage_private_t *dev_priv,
880 return 0; 881 return 0;
881} 882}
882 883
883static int savage_dispatch_swap(drm_savage_private_t *dev_priv, 884static int savage_dispatch_swap(drm_savage_private_t * dev_priv,
884 unsigned int nbox, 885 unsigned int nbox,
885 const drm_clip_rect_t __user *usr_boxes) 886 const drm_clip_rect_t __user * usr_boxes)
886{ 887{
887 unsigned int swap_cmd; 888 unsigned int swap_cmd;
888 unsigned int i; 889 unsigned int i;
@@ -892,8 +893,8 @@ static int savage_dispatch_swap(drm_savage_private_t *dev_priv,
892 return 0; 893 return 0;
893 894
894 swap_cmd = BCI_CMD_RECT | BCI_CMD_RECT_XP | BCI_CMD_RECT_YP | 895 swap_cmd = BCI_CMD_RECT | BCI_CMD_RECT_XP | BCI_CMD_RECT_YP |
895 BCI_CMD_SRC_PBD_COLOR_NEW | BCI_CMD_DEST_GBD; 896 BCI_CMD_SRC_PBD_COLOR_NEW | BCI_CMD_DEST_GBD;
896 BCI_CMD_SET_ROP(swap_cmd,0xCC); 897 BCI_CMD_SET_ROP(swap_cmd, 0xCC);
897 898
898 for (i = 0; i < nbox; ++i) { 899 for (i = 0; i < nbox; ++i) {
899 drm_clip_rect_t box; 900 drm_clip_rect_t box;
@@ -905,21 +906,21 @@ static int savage_dispatch_swap(drm_savage_private_t *dev_priv,
905 DMA_WRITE(dev_priv->back_bd); 906 DMA_WRITE(dev_priv->back_bd);
906 DMA_WRITE(BCI_X_Y(box.x1, box.y1)); 907 DMA_WRITE(BCI_X_Y(box.x1, box.y1));
907 DMA_WRITE(BCI_X_Y(box.x1, box.y1)); 908 DMA_WRITE(BCI_X_Y(box.x1, box.y1));
908 DMA_WRITE(BCI_W_H(box.x2-box.x1, box.y2-box.y1)); 909 DMA_WRITE(BCI_W_H(box.x2 - box.x1, box.y2 - box.y1));
909 DMA_COMMIT(); 910 DMA_COMMIT();
910 } 911 }
911 912
912 return 0; 913 return 0;
913} 914}
914 915
915static int savage_dispatch_draw(drm_savage_private_t *dev_priv, 916static int savage_dispatch_draw(drm_savage_private_t * dev_priv,
916 const drm_savage_cmd_header_t __user *start, 917 const drm_savage_cmd_header_t __user * start,
917 const drm_savage_cmd_header_t __user *end, 918 const drm_savage_cmd_header_t __user * end,
918 const drm_buf_t *dmabuf, 919 const drm_buf_t * dmabuf,
919 const unsigned int __user *usr_vtxbuf, 920 const unsigned int __user * usr_vtxbuf,
920 unsigned int vb_size, unsigned int vb_stride, 921 unsigned int vb_size, unsigned int vb_stride,
921 unsigned int nbox, 922 unsigned int nbox,
922 const drm_clip_rect_t __user *usr_boxes) 923 const drm_clip_rect_t __user * usr_boxes)
923{ 924{
924 unsigned int i, j; 925 unsigned int i, j;
925 int ret; 926 int ret;
@@ -938,32 +939,42 @@ static int savage_dispatch_draw(drm_savage_private_t *dev_priv,
938 usr_cmdbuf++; 939 usr_cmdbuf++;
939 switch (cmd_header.cmd.cmd) { 940 switch (cmd_header.cmd.cmd) {
940 case SAVAGE_CMD_DMA_PRIM: 941 case SAVAGE_CMD_DMA_PRIM:
941 ret = savage_dispatch_dma_prim( 942 ret =
942 dev_priv, &cmd_header, dmabuf); 943 savage_dispatch_dma_prim(dev_priv,
944 &cmd_header,
945 dmabuf);
943 break; 946 break;
944 case SAVAGE_CMD_VB_PRIM: 947 case SAVAGE_CMD_VB_PRIM:
945 ret = savage_dispatch_vb_prim( 948 ret =
946 dev_priv, &cmd_header, 949 savage_dispatch_vb_prim(dev_priv,
947 (const uint32_t __user *)usr_vtxbuf, 950 &cmd_header,
948 vb_size, vb_stride); 951 (const uint32_t
952 __user *)
953 usr_vtxbuf, vb_size,
954 vb_stride);
949 break; 955 break;
950 case SAVAGE_CMD_DMA_IDX: 956 case SAVAGE_CMD_DMA_IDX:
951 j = (cmd_header.idx.count + 3) / 4; 957 j = (cmd_header.idx.count + 3) / 4;
952 /* j was check in savage_bci_cmdbuf */ 958 /* j was check in savage_bci_cmdbuf */
953 ret = savage_dispatch_dma_idx( 959 ret =
954 dev_priv, &cmd_header, 960 savage_dispatch_dma_idx(dev_priv,
955 (const uint16_t __user *)usr_cmdbuf, 961 &cmd_header,
956 dmabuf); 962 (const uint16_t
963 __user *)
964 usr_cmdbuf, dmabuf);
957 usr_cmdbuf += j; 965 usr_cmdbuf += j;
958 break; 966 break;
959 case SAVAGE_CMD_VB_IDX: 967 case SAVAGE_CMD_VB_IDX:
960 j = (cmd_header.idx.count + 3) / 4; 968 j = (cmd_header.idx.count + 3) / 4;
961 /* j was check in savage_bci_cmdbuf */ 969 /* j was check in savage_bci_cmdbuf */
962 ret = savage_dispatch_vb_idx( 970 ret =
963 dev_priv, &cmd_header, 971 savage_dispatch_vb_idx(dev_priv,
964 (const uint16_t __user *)usr_cmdbuf, 972 &cmd_header,
965 (const uint32_t __user *)usr_vtxbuf, 973 (const uint16_t
966 vb_size, vb_stride); 974 __user *)usr_cmdbuf,
975 (const uint32_t
976 __user *)usr_vtxbuf,
977 vb_size, vb_stride);
967 usr_cmdbuf += j; 978 usr_cmdbuf += j;
968 break; 979 break;
969 default: 980 default:
@@ -997,16 +1008,17 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS)
997 int ret = 0; 1008 int ret = 0;
998 1009
999 DRM_DEBUG("\n"); 1010 DRM_DEBUG("\n");
1000 1011
1001 LOCK_TEST_WITH_RETURN(dev, filp); 1012 LOCK_TEST_WITH_RETURN(dev, filp);
1002 1013
1003 DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_savage_cmdbuf_t __user *)data, 1014 DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_savage_cmdbuf_t __user *) data,
1004 sizeof(cmdbuf)); 1015 sizeof(cmdbuf));
1005 1016
1006 if (dma && dma->buflist) { 1017 if (dma && dma->buflist) {
1007 if (cmdbuf.dma_idx > dma->buf_count) { 1018 if (cmdbuf.dma_idx > dma->buf_count) {
1008 DRM_ERROR("vertex buffer index %u out of range (0-%u)\n", 1019 DRM_ERROR
1009 cmdbuf.dma_idx, dma->buf_count-1); 1020 ("vertex buffer index %u out of range (0-%u)\n",
1021 cmdbuf.dma_idx, dma->buf_count - 1);
1010 return DRM_ERR(EINVAL); 1022 return DRM_ERR(EINVAL);
1011 } 1023 }
1012 dmabuf = dma->buflist[cmdbuf.dma_idx]; 1024 dmabuf = dma->buflist[cmdbuf.dma_idx];
@@ -1014,14 +1026,14 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS)
1014 dmabuf = NULL; 1026 dmabuf = NULL;
1015 } 1027 }
1016 1028
1017 usr_cmdbuf = (drm_savage_cmd_header_t __user *)cmdbuf.cmd_addr; 1029 usr_cmdbuf = (drm_savage_cmd_header_t __user *) cmdbuf.cmd_addr;
1018 usr_vtxbuf = (unsigned int __user *)cmdbuf.vb_addr; 1030 usr_vtxbuf = (unsigned int __user *)cmdbuf.vb_addr;
1019 usr_boxes = (drm_clip_rect_t __user *)cmdbuf.box_addr; 1031 usr_boxes = (drm_clip_rect_t __user *) cmdbuf.box_addr;
1020 if ((cmdbuf.size && DRM_VERIFYAREA_READ(usr_cmdbuf, cmdbuf.size*8)) || 1032 if ((cmdbuf.size && DRM_VERIFYAREA_READ(usr_cmdbuf, cmdbuf.size * 8)) ||
1021 (cmdbuf.vb_size && DRM_VERIFYAREA_READ( 1033 (cmdbuf.vb_size && DRM_VERIFYAREA_READ(usr_vtxbuf, cmdbuf.vb_size))
1022 usr_vtxbuf, cmdbuf.vb_size)) || 1034 || (cmdbuf.nbox
1023 (cmdbuf.nbox && DRM_VERIFYAREA_READ( 1035 && DRM_VERIFYAREA_READ(usr_boxes,
1024 usr_boxes, cmdbuf.nbox*sizeof(drm_clip_rect_t)))) 1036 cmdbuf.nbox * sizeof(drm_clip_rect_t))))
1025 return DRM_ERR(EFAULT); 1037 return DRM_ERR(EFAULT);
1026 1038
1027 /* Make sure writes to DMA buffers are finished before sending 1039 /* Make sure writes to DMA buffers are finished before sending
@@ -1058,17 +1070,21 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS)
1058 case SAVAGE_CMD_DMA_PRIM: 1070 case SAVAGE_CMD_DMA_PRIM:
1059 case SAVAGE_CMD_VB_PRIM: 1071 case SAVAGE_CMD_VB_PRIM:
1060 if (!first_draw_cmd) 1072 if (!first_draw_cmd)
1061 first_draw_cmd = usr_cmdbuf-1; 1073 first_draw_cmd = usr_cmdbuf - 1;
1062 usr_cmdbuf += j; 1074 usr_cmdbuf += j;
1063 i += j; 1075 i += j;
1064 break; 1076 break;
1065 default: 1077 default:
1066 if (first_draw_cmd) { 1078 if (first_draw_cmd) {
1067 ret = savage_dispatch_draw ( 1079 ret =
1068 dev_priv, first_draw_cmd, usr_cmdbuf-1, 1080 savage_dispatch_draw(dev_priv,
1069 dmabuf, usr_vtxbuf, cmdbuf.vb_size, 1081 first_draw_cmd,
1070 cmdbuf.vb_stride, 1082 usr_cmdbuf - 1, dmabuf,
1071 cmdbuf.nbox, usr_boxes); 1083 usr_vtxbuf,
1084 cmdbuf.vb_size,
1085 cmdbuf.vb_stride,
1086 cmdbuf.nbox,
1087 usr_boxes);
1072 if (ret != 0) 1088 if (ret != 0)
1073 return ret; 1089 return ret;
1074 first_draw_cmd = NULL; 1090 first_draw_cmd = NULL;
@@ -1086,9 +1102,9 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS)
1086 DMA_FLUSH(); 1102 DMA_FLUSH();
1087 return DRM_ERR(EINVAL); 1103 return DRM_ERR(EINVAL);
1088 } 1104 }
1089 ret = savage_dispatch_state( 1105 ret = savage_dispatch_state(dev_priv, &cmd_header,
1090 dev_priv, &cmd_header, 1106 (uint32_t __user *)
1091 (uint32_t __user *)usr_cmdbuf); 1107 usr_cmdbuf);
1092 usr_cmdbuf += j; 1108 usr_cmdbuf += j;
1093 i += j; 1109 i += j;
1094 break; 1110 break;
@@ -1122,10 +1138,11 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS)
1122 } 1138 }
1123 1139
1124 if (first_draw_cmd) { 1140 if (first_draw_cmd) {
1125 ret = savage_dispatch_draw ( 1141 ret =
1126 dev_priv, first_draw_cmd, usr_cmdbuf, dmabuf, 1142 savage_dispatch_draw(dev_priv, first_draw_cmd, usr_cmdbuf,
1127 usr_vtxbuf, cmdbuf.vb_size, cmdbuf.vb_stride, 1143 dmabuf, usr_vtxbuf, cmdbuf.vb_size,
1128 cmdbuf.nbox, usr_boxes); 1144 cmdbuf.vb_stride, cmdbuf.nbox,
1145 usr_boxes);
1129 if (ret != 0) { 1146 if (ret != 0) {
1130 DMA_FLUSH(); 1147 DMA_FLUSH();
1131 return ret; 1148 return ret;
diff --git a/drivers/char/drm/sis_drm.h b/drivers/char/drm/sis_drm.h
index e99c3a43abbc..8f273da76ddb 100644
--- a/drivers/char/drm/sis_drm.h
+++ b/drivers/char/drm/sis_drm.h
@@ -39,4 +39,4 @@ typedef struct {
39 unsigned int offset, size; 39 unsigned int offset, size;
40} drm_sis_fb_t; 40} drm_sis_fb_t;
41 41
42#endif /* __SIS_DRM_H__ */ 42#endif /* __SIS_DRM_H__ */
diff --git a/drivers/char/drm/sis_drv.c b/drivers/char/drm/sis_drv.c
index f441714faae3..6d0cb2226005 100644
--- a/drivers/char/drm/sis_drv.c
+++ b/drivers/char/drm/sis_drv.c
@@ -10,11 +10,11 @@
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the 11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions: 12 * Software is furnished to do so, subject to the following conditions:
13 * 13 *
14 * The above copyright notice and this permission notice (including the next 14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the 15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software. 16 * Software.
17 * 17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -31,31 +31,29 @@
31#include "sis_drv.h" 31#include "sis_drv.h"
32 32
33#include "drm_pciids.h" 33#include "drm_pciids.h"
34 34
35static int postinit( struct drm_device *dev, unsigned long flags ) 35static int postinit(struct drm_device *dev, unsigned long flags)
36{ 36{
37 DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", 37 DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n",
38 DRIVER_NAME, 38 DRIVER_NAME,
39 DRIVER_MAJOR, 39 DRIVER_MAJOR,
40 DRIVER_MINOR, 40 DRIVER_MINOR,
41 DRIVER_PATCHLEVEL, 41 DRIVER_PATCHLEVEL,
42 DRIVER_DATE, 42 DRIVER_DATE, dev->primary.minor, pci_pretty_name(dev->pdev)
43 dev->primary.minor, 43 );
44 pci_pretty_name(dev->pdev)
45 );
46 return 0; 44 return 0;
47} 45}
48 46
49static int version( drm_version_t *version ) 47static int version(drm_version_t * version)
50{ 48{
51 int len; 49 int len;
52 50
53 version->version_major = DRIVER_MAJOR; 51 version->version_major = DRIVER_MAJOR;
54 version->version_minor = DRIVER_MINOR; 52 version->version_minor = DRIVER_MINOR;
55 version->version_patchlevel = DRIVER_PATCHLEVEL; 53 version->version_patchlevel = DRIVER_PATCHLEVEL;
56 DRM_COPY( version->name, DRIVER_NAME ); 54 DRM_COPY(version->name, DRIVER_NAME);
57 DRM_COPY( version->date, DRIVER_DATE ); 55 DRM_COPY(version->date, DRIVER_DATE);
58 DRM_COPY( version->desc, DRIVER_DESC ); 56 DRM_COPY(version->desc, DRIVER_DESC);
59 return 0; 57 return 0;
60} 58}
61 59
@@ -77,18 +75,18 @@ static struct drm_driver driver = {
77 .version = version, 75 .version = version,
78 .ioctls = sis_ioctls, 76 .ioctls = sis_ioctls,
79 .fops = { 77 .fops = {
80 .owner = THIS_MODULE, 78 .owner = THIS_MODULE,
81 .open = drm_open, 79 .open = drm_open,
82 .release = drm_release, 80 .release = drm_release,
83 .ioctl = drm_ioctl, 81 .ioctl = drm_ioctl,
84 .mmap = drm_mmap, 82 .mmap = drm_mmap,
85 .poll = drm_poll, 83 .poll = drm_poll,
86 .fasync = drm_fasync, 84 .fasync = drm_fasync,
87 }, 85 },
88 .pci_driver = { 86 .pci_driver = {
89 .name = DRIVER_NAME, 87 .name = DRIVER_NAME,
90 .id_table = pciidlist, 88 .id_table = pciidlist,
91 } 89 }
92}; 90};
93 91
94static int __init sis_init(void) 92static int __init sis_init(void)
@@ -105,6 +103,6 @@ static void __exit sis_exit(void)
105module_init(sis_init); 103module_init(sis_init);
106module_exit(sis_exit); 104module_exit(sis_exit);
107 105
108MODULE_AUTHOR( DRIVER_AUTHOR ); 106MODULE_AUTHOR(DRIVER_AUTHOR);
109MODULE_DESCRIPTION( DRIVER_DESC ); 107MODULE_DESCRIPTION(DRIVER_DESC);
110MODULE_LICENSE("GPL and additional rights"); 108MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/char/drm/sis_drv.h b/drivers/char/drm/sis_drv.h
index 5be36b5caec9..4ef3d6226418 100644
--- a/drivers/char/drm/sis_drv.h
+++ b/drivers/char/drm/sis_drv.h
@@ -10,11 +10,11 @@
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the 11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions: 12 * Software is furnished to do so, subject to the following conditions:
13 * 13 *
14 * The above copyright notice and this permission notice (including the next 14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the 15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software. 16 * Software.
17 * 17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -22,7 +22,7 @@
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE. 24 * DEALINGS IN THE SOFTWARE.
25 * 25 *
26 */ 26 */
27 27
28#ifndef _SIS_DRV_H_ 28#ifndef _SIS_DRV_H_
@@ -46,7 +46,7 @@ typedef struct drm_sis_private {
46 memHeap_t *FBHeap; 46 memHeap_t *FBHeap;
47} drm_sis_private_t; 47} drm_sis_private_t;
48 48
49extern int sis_init_context(drm_device_t *dev, int context); 49extern int sis_init_context(drm_device_t * dev, int context);
50extern int sis_final_context(drm_device_t *dev, int context); 50extern int sis_final_context(drm_device_t * dev, int context);
51 51
52#endif 52#endif
diff --git a/drivers/char/drm/sis_ds.c b/drivers/char/drm/sis_ds.c
index e37ed8ce48df..2e485d482943 100644
--- a/drivers/char/drm/sis_ds.c
+++ b/drivers/char/drm/sis_ds.c
@@ -10,11 +10,11 @@
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the 11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions: 12 * Software is furnished to do so, subject to the following conditions:
13 * 13 *
14 * The above copyright notice and this permission notice (including the next 14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the 15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software. 16 * Software.
17 * 17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -22,10 +22,10 @@
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE. 24 * DEALINGS IN THE SOFTWARE.
25 * 25 *
26 * Authors: 26 * Authors:
27 * Sung-Ching Lin <sclin@sis.com.tw> 27 * Sung-Ching Lin <sclin@sis.com.tw>
28 * 28 *
29 */ 29 */
30 30
31#include "drmP.h" 31#include "drmP.h"
@@ -41,13 +41,13 @@ set_t *setInit(void)
41 int i; 41 int i;
42 set_t *set; 42 set_t *set;
43 43
44 set = (set_t *)drm_alloc(sizeof(set_t), DRM_MEM_DRIVER); 44 set = (set_t *) drm_alloc(sizeof(set_t), DRM_MEM_DRIVER);
45 if (set != NULL) { 45 if (set != NULL) {
46 for (i = 0; i < SET_SIZE; i++) { 46 for (i = 0; i < SET_SIZE; i++) {
47 set->list[i].free_next = i + 1; 47 set->list[i].free_next = i + 1;
48 set->list[i].alloc_next = -1; 48 set->list[i].alloc_next = -1;
49 } 49 }
50 set->list[SET_SIZE-1].free_next = -1; 50 set->list[SET_SIZE - 1].free_next = -1;
51 set->free = 0; 51 set->free = 0;
52 set->alloc = -1; 52 set->alloc = -1;
53 set->trace = -1; 53 set->trace = -1;
@@ -55,10 +55,10 @@ set_t *setInit(void)
55 return set; 55 return set;
56} 56}
57 57
58int setAdd(set_t *set, ITEM_TYPE item) 58int setAdd(set_t * set, ITEM_TYPE item)
59{ 59{
60 int free = set->free; 60 int free = set->free;
61 61
62 if (free != -1) { 62 if (free != -1) {
63 set->list[free].val = item; 63 set->list[free].val = item;
64 set->free = set->list[free].free_next; 64 set->free = set->list[free].free_next;
@@ -67,16 +67,16 @@ int setAdd(set_t *set, ITEM_TYPE item)
67 } 67 }
68 68
69 set->list[free].alloc_next = set->alloc; 69 set->list[free].alloc_next = set->alloc;
70 set->alloc = free; 70 set->alloc = free;
71 set->list[free].free_next = -1; 71 set->list[free].free_next = -1;
72 72
73 return 1; 73 return 1;
74} 74}
75 75
76int setDel(set_t *set, ITEM_TYPE item) 76int setDel(set_t * set, ITEM_TYPE item)
77{ 77{
78 int alloc = set->alloc; 78 int alloc = set->alloc;
79 int prev = -1; 79 int prev = -1;
80 80
81 while (alloc != -1) { 81 while (alloc != -1) {
82 if (set->list[alloc].val == item) { 82 if (set->list[alloc].val == item) {
@@ -103,7 +103,7 @@ int setDel(set_t *set, ITEM_TYPE item)
103 103
104/* setFirst -> setAdd -> setNext is wrong */ 104/* setFirst -> setAdd -> setNext is wrong */
105 105
106int setFirst(set_t *set, ITEM_TYPE *item) 106int setFirst(set_t * set, ITEM_TYPE * item)
107{ 107{
108 if (set->alloc == -1) 108 if (set->alloc == -1)
109 return 0; 109 return 0;
@@ -114,7 +114,7 @@ int setFirst(set_t *set, ITEM_TYPE *item)
114 return 1; 114 return 1;
115} 115}
116 116
117int setNext(set_t *set, ITEM_TYPE *item) 117int setNext(set_t * set, ITEM_TYPE * item)
118{ 118{
119 if (set->trace == -1) 119 if (set->trace == -1)
120 return 0; 120 return 0;
@@ -125,7 +125,7 @@ int setNext(set_t *set, ITEM_TYPE *item)
125 return 1; 125 return 1;
126} 126}
127 127
128int setDestroy(set_t *set) 128int setDestroy(set_t * set)
129{ 129{
130 drm_free(set, sizeof(set_t), DRM_MEM_DRIVER); 130 drm_free(set, sizeof(set_t), DRM_MEM_DRIVER);
131 131
@@ -149,35 +149,34 @@ int setDestroy(set_t *set)
149 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 149 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
150 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 150 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
151 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 151 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
152 * WITTAWAT YAMWONG, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, 152 * WITTAWAT YAMWONG, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
153 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 153 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
154 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE 154 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
155 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 155 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
156 * 156 *
157 */ 157 */
158 158
159#define ISFREE(bptr) ((bptr)->free) 159#define ISFREE(bptr) ((bptr)->free)
160 160
161memHeap_t *mmInit(int ofs, 161memHeap_t *mmInit(int ofs, int size)
162 int size)
163{ 162{
164 PMemBlock blocks; 163 PMemBlock blocks;
165 164
166 if (size <= 0) 165 if (size <= 0)
167 return NULL; 166 return NULL;
168 167
169 blocks = (TMemBlock *)drm_calloc(1, sizeof(TMemBlock), DRM_MEM_DRIVER); 168 blocks = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock), DRM_MEM_DRIVER);
170 if (blocks != NULL) { 169 if (blocks != NULL) {
171 blocks->ofs = ofs; 170 blocks->ofs = ofs;
172 blocks->size = size; 171 blocks->size = size;
173 blocks->free = 1; 172 blocks->free = 1;
174 return (memHeap_t *)blocks; 173 return (memHeap_t *) blocks;
175 } else 174 } else
176 return NULL; 175 return NULL;
177} 176}
178 177
179/* Checks if a pointer 'b' is part of the heap 'heap' */ 178/* Checks if a pointer 'b' is part of the heap 'heap' */
180int mmBlockInHeap(memHeap_t *heap, PMemBlock b) 179int mmBlockInHeap(memHeap_t * heap, PMemBlock b)
181{ 180{
182 TMemBlock *p; 181 TMemBlock *p;
183 182
@@ -194,16 +193,16 @@ int mmBlockInHeap(memHeap_t *heap, PMemBlock b)
194 return 0; 193 return 0;
195} 194}
196 195
197static TMemBlock* SliceBlock(TMemBlock *p, 196static TMemBlock *SliceBlock(TMemBlock * p,
198 int startofs, int size, 197 int startofs, int size,
199 int reserved, int alignment) 198 int reserved, int alignment)
200{ 199{
201 TMemBlock *newblock; 200 TMemBlock *newblock;
202 201
203 /* break left */ 202 /* break left */
204 if (startofs > p->ofs) { 203 if (startofs > p->ofs) {
205 newblock = (TMemBlock*) drm_calloc(1, sizeof(TMemBlock), 204 newblock = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock),
206 DRM_MEM_DRIVER); 205 DRM_MEM_DRIVER);
207 newblock->ofs = startofs; 206 newblock->ofs = startofs;
208 newblock->size = p->size - (startofs - p->ofs); 207 newblock->size = p->size - (startofs - p->ofs);
209 newblock->free = 1; 208 newblock->free = 1;
@@ -215,8 +214,8 @@ static TMemBlock* SliceBlock(TMemBlock *p,
215 214
216 /* break right */ 215 /* break right */
217 if (size < p->size) { 216 if (size < p->size) {
218 newblock = (TMemBlock*) drm_calloc(1, sizeof(TMemBlock), 217 newblock = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock),
219 DRM_MEM_DRIVER); 218 DRM_MEM_DRIVER);
220 newblock->ofs = startofs + size; 219 newblock->ofs = startofs + size;
221 newblock->size = p->size - size; 220 newblock->size = p->size - size;
222 newblock->free = 1; 221 newblock->free = 1;
@@ -232,37 +231,37 @@ static TMemBlock* SliceBlock(TMemBlock *p,
232 return p; 231 return p;
233} 232}
234 233
235PMemBlock mmAllocMem( memHeap_t *heap, int size, int align2, int startSearch) 234PMemBlock mmAllocMem(memHeap_t * heap, int size, int align2, int startSearch)
236{ 235{
237 int mask,startofs, endofs; 236 int mask, startofs, endofs;
238 TMemBlock *p; 237 TMemBlock *p;
239 238
240 if (heap == NULL || align2 < 0 || size <= 0) 239 if (heap == NULL || align2 < 0 || size <= 0)
241 return NULL; 240 return NULL;
242 241
243 mask = (1 << align2)-1; 242 mask = (1 << align2) - 1;
244 startofs = 0; 243 startofs = 0;
245 p = (TMemBlock *)heap; 244 p = (TMemBlock *) heap;
246 while (p != NULL) { 245 while (p != NULL) {
247 if (ISFREE(p)) { 246 if (ISFREE(p)) {
248 startofs = (p->ofs + mask) & ~mask; 247 startofs = (p->ofs + mask) & ~mask;
249 if ( startofs < startSearch ) { 248 if (startofs < startSearch) {
250 startofs = startSearch; 249 startofs = startSearch;
251 } 250 }
252 endofs = startofs+size; 251 endofs = startofs + size;
253 if (endofs <= (p->ofs+p->size)) 252 if (endofs <= (p->ofs + p->size))
254 break; 253 break;
255 } 254 }
256 p = p->next; 255 p = p->next;
257 } 256 }
258 if (p == NULL) 257 if (p == NULL)
259 return NULL; 258 return NULL;
260 p = SliceBlock(p,startofs,size,0,mask+1); 259 p = SliceBlock(p, startofs, size, 0, mask + 1);
261 p->heap = heap; 260 p->heap = heap;
262 return p; 261 return p;
263} 262}
264 263
265static __inline__ int Join2Blocks(TMemBlock *p) 264static __inline__ int Join2Blocks(TMemBlock * p)
266{ 265{
267 if (p->free && p->next && p->next->free) { 266 if (p->free && p->next && p->next->free) {
268 TMemBlock *q = p->next; 267 TMemBlock *q = p->next;
@@ -295,7 +294,6 @@ int mmFreeMem(PMemBlock b)
295 p->free = 1; 294 p->free = 1;
296 Join2Blocks(p); 295 Join2Blocks(p);
297 if (prev) 296 if (prev)
298 Join2Blocks(prev); 297 Join2Blocks(prev);
299 return 0; 298 return 0;
300} 299}
301
diff --git a/drivers/char/drm/sis_ds.h b/drivers/char/drm/sis_ds.h
index 171ee75afa57..da850b4f5440 100644
--- a/drivers/char/drm/sis_ds.h
+++ b/drivers/char/drm/sis_ds.h
@@ -10,11 +10,11 @@
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the 11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions: 12 * Software is furnished to do so, subject to the following conditions:
13 * 13 *
14 * The above copyright notice and this permission notice (including the next 14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the 15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software. 16 * Software.
17 * 17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -22,10 +22,10 @@
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE. 24 * DEALINGS IN THE SOFTWARE.
25 * 25 *
26 * Authors: 26 * Authors:
27 * Sung-Ching Lin <sclin@sis.com.tw> 27 * Sung-Ching Lin <sclin@sis.com.tw>
28 * 28 *
29 */ 29 */
30 30
31#ifndef __SIS_DS_H__ 31#ifndef __SIS_DS_H__
@@ -50,11 +50,11 @@ typedef struct {
50} set_t; 50} set_t;
51 51
52set_t *setInit(void); 52set_t *setInit(void);
53int setAdd(set_t *set, ITEM_TYPE item); 53int setAdd(set_t * set, ITEM_TYPE item);
54int setDel(set_t *set, ITEM_TYPE item); 54int setDel(set_t * set, ITEM_TYPE item);
55int setFirst(set_t *set, ITEM_TYPE *item); 55int setFirst(set_t * set, ITEM_TYPE * item);
56int setNext(set_t *set, ITEM_TYPE *item); 56int setNext(set_t * set, ITEM_TYPE * item);
57int setDestroy(set_t *set); 57int setDestroy(set_t * set);
58 58
59/* 59/*
60 * GLX Hardware Device Driver common code 60 * GLX Hardware Device Driver common code
@@ -73,9 +73,9 @@ int setDestroy(set_t *set);
73 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 73 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
74 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 74 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
75 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 75 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
76 * WITTAWAT YAMWONG, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, 76 * WITTAWAT YAMWONG, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
77 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 77 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
78 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE 78 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
79 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 79 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
80 * 80 *
81 */ 81 */
@@ -83,7 +83,7 @@ int setDestroy(set_t *set);
83struct mem_block_t { 83struct mem_block_t {
84 struct mem_block_t *next; 84 struct mem_block_t *next;
85 struct mem_block_t *heap; 85 struct mem_block_t *heap;
86 int ofs,size; 86 int ofs, size;
87 int align; 87 int align;
88 unsigned int free:1; 88 unsigned int free:1;
89 unsigned int reserved:1; 89 unsigned int reserved:1;
@@ -109,11 +109,11 @@ static __inline__ void mmMarkReserved(PMemBlock b)
109 b->reserved = 1; 109 b->reserved = 1;
110} 110}
111 111
112/* 112/*
113 * input: total size in bytes 113 * input: total size in bytes
114 * return: a heap pointer if OK, NULL if error 114 * return: a heap pointer if OK, NULL if error
115 */ 115 */
116memHeap_t *mmInit( int ofs, int size ); 116memHeap_t *mmInit(int ofs, int size);
117 117
118/* 118/*
119 * Allocate 'size' bytes with 2^align2 bytes alignment, 119 * Allocate 'size' bytes with 2^align2 bytes alignment,
@@ -125,21 +125,21 @@ memHeap_t *mmInit( int ofs, int size );
125 * startSearch = linear offset from start of heap to begin search 125 * startSearch = linear offset from start of heap to begin search
126 * return: pointer to the allocated block, 0 if error 126 * return: pointer to the allocated block, 0 if error
127 */ 127 */
128PMemBlock mmAllocMem( memHeap_t *heap, int size, int align2, int startSearch ); 128PMemBlock mmAllocMem(memHeap_t * heap, int size, int align2, int startSearch);
129 129
130/* 130/*
131 * Returns 1 if the block 'b' is part of the heap 'heap' 131 * Returns 1 if the block 'b' is part of the heap 'heap'
132 */ 132 */
133int mmBlockInHeap( PMemBlock heap, PMemBlock b ); 133int mmBlockInHeap(PMemBlock heap, PMemBlock b);
134 134
135/* 135/*
136 * Free block starts at offset 136 * Free block starts at offset
137 * input: pointer to a block 137 * input: pointer to a block
138 * return: 0 if OK, -1 if error 138 * return: 0 if OK, -1 if error
139 */ 139 */
140int mmFreeMem( PMemBlock b ); 140int mmFreeMem(PMemBlock b);
141 141
142/* For debuging purpose. */ 142/* For debuging purpose. */
143void mmDumpMemInfo( memHeap_t *mmInit ); 143void mmDumpMemInfo(memHeap_t * mmInit);
144 144
145#endif /* __SIS_DS_H__ */ 145#endif /* __SIS_DS_H__ */
diff --git a/drivers/char/drm/sis_mm.c b/drivers/char/drm/sis_mm.c
index 6610c5576d22..50e32384ad93 100644
--- a/drivers/char/drm/sis_mm.c
+++ b/drivers/char/drm/sis_mm.c
@@ -10,11 +10,11 @@
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the 11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions: 12 * Software is furnished to do so, subject to the following conditions:
13 * 13 *
14 * The above copyright notice and this permission notice (including the next 14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the 15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software. 16 * Software.
17 * 17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -22,10 +22,10 @@
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE. 24 * DEALINGS IN THE SOFTWARE.
25 * 25 *
26 * Authors: 26 * Authors:
27 * Sung-Ching Lin <sclin@sis.com.tw> 27 * Sung-Ching Lin <sclin@sis.com.tw>
28 * 28 *
29 */ 29 */
30 30
31#include "drmP.h" 31#include "drmP.h"
@@ -37,25 +37,23 @@
37#endif 37#endif
38 38
39#define MAX_CONTEXT 100 39#define MAX_CONTEXT 100
40#define VIDEO_TYPE 0 40#define VIDEO_TYPE 0
41#define AGP_TYPE 1 41#define AGP_TYPE 1
42 42
43typedef struct { 43typedef struct {
44 int used; 44 int used;
45 int context; 45 int context;
46 set_t *sets[2]; /* 0 for video, 1 for AGP */ 46 set_t *sets[2]; /* 0 for video, 1 for AGP */
47} sis_context_t; 47} sis_context_t;
48 48
49static sis_context_t global_ppriv[MAX_CONTEXT]; 49static sis_context_t global_ppriv[MAX_CONTEXT];
50 50
51
52static int add_alloc_set(int context, int type, unsigned int val) 51static int add_alloc_set(int context, int type, unsigned int val)
53{ 52{
54 int i, retval = 0; 53 int i, retval = 0;
55 54
56 for (i = 0; i < MAX_CONTEXT; i++) { 55 for (i = 0; i < MAX_CONTEXT; i++) {
57 if (global_ppriv[i].used && global_ppriv[i].context == context) 56 if (global_ppriv[i].used && global_ppriv[i].context == context) {
58 {
59 retval = setAdd(global_ppriv[i].sets[type], val); 57 retval = setAdd(global_ppriv[i].sets[type], val);
60 break; 58 break;
61 } 59 }
@@ -64,12 +62,11 @@ static int add_alloc_set(int context, int type, unsigned int val)
64} 62}
65 63
66static int del_alloc_set(int context, int type, unsigned int val) 64static int del_alloc_set(int context, int type, unsigned int val)
67{ 65{
68 int i, retval = 0; 66 int i, retval = 0;
69 67
70 for (i = 0; i < MAX_CONTEXT; i++) { 68 for (i = 0; i < MAX_CONTEXT; i++) {
71 if (global_ppriv[i].used && global_ppriv[i].context == context) 69 if (global_ppriv[i].used && global_ppriv[i].context == context) {
72 {
73 retval = setDel(global_ppriv[i].sets[type], val); 70 retval = setDel(global_ppriv[i].sets[type], val);
74 break; 71 break;
75 } 72 }
@@ -77,15 +74,15 @@ static int del_alloc_set(int context, int type, unsigned int val)
77 return retval; 74 return retval;
78} 75}
79 76
80/* fb management via fb device */ 77/* fb management via fb device */
81#if defined(__linux__) && defined(CONFIG_FB_SIS) 78#if defined(__linux__) && defined(CONFIG_FB_SIS)
82 79
83static int sis_fb_init( DRM_IOCTL_ARGS ) 80static int sis_fb_init(DRM_IOCTL_ARGS)
84{ 81{
85 return 0; 82 return 0;
86} 83}
87 84
88static int sis_fb_alloc( DRM_IOCTL_ARGS ) 85static int sis_fb_alloc(DRM_IOCTL_ARGS)
89{ 86{
90 drm_sis_mem_t fb; 87 drm_sis_mem_t fb;
91 struct sis_memreq req; 88 struct sis_memreq req;
@@ -105,7 +102,7 @@ static int sis_fb_alloc( DRM_IOCTL_ARGS )
105 sis_free(req.offset); 102 sis_free(req.offset);
106 retval = DRM_ERR(EINVAL); 103 retval = DRM_ERR(EINVAL);
107 } 104 }
108 } else { 105 } else {
109 fb.offset = 0; 106 fb.offset = 0;
110 fb.size = 0; 107 fb.size = 0;
111 fb.free = 0; 108 fb.free = 0;
@@ -118,19 +115,19 @@ static int sis_fb_alloc( DRM_IOCTL_ARGS )
118 return retval; 115 return retval;
119} 116}
120 117
121static int sis_fb_free( DRM_IOCTL_ARGS ) 118static int sis_fb_free(DRM_IOCTL_ARGS)
122{ 119{
123 drm_sis_mem_t fb; 120 drm_sis_mem_t fb;
124 int retval = 0; 121 int retval = 0;
125 122
126 DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_mem_t __user *)data, sizeof(fb)); 123 DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_mem_t __user *) data, sizeof(fb));
127 124
128 if (!fb.free) 125 if (!fb.free)
129 return DRM_ERR(EINVAL); 126 return DRM_ERR(EINVAL);
130 127
131 if (!del_alloc_set(fb.context, VIDEO_TYPE, fb.free)) 128 if (!del_alloc_set(fb.context, VIDEO_TYPE, fb.free))
132 retval = DRM_ERR(EINVAL); 129 retval = DRM_ERR(EINVAL);
133 sis_free((u32)fb.free); 130 sis_free((u32) fb.free);
134 131
135 DRM_DEBUG("free fb, offset = %lu\n", fb.free); 132 DRM_DEBUG("free fb, offset = %lu\n", fb.free);
136 133
@@ -149,17 +146,17 @@ static int sis_fb_free( DRM_IOCTL_ARGS )
149 * X driver/sisfb HW- Command- 146 * X driver/sisfb HW- Command-
150 * framebuffer memory DRI heap Cursor queue 147 * framebuffer memory DRI heap Cursor queue
151 */ 148 */
152static int sis_fb_init( DRM_IOCTL_ARGS ) 149static int sis_fb_init(DRM_IOCTL_ARGS)
153{ 150{
154 DRM_DEVICE; 151 DRM_DEVICE;
155 drm_sis_private_t *dev_priv = dev->dev_private; 152 drm_sis_private_t *dev_priv = dev->dev_private;
156 drm_sis_fb_t fb; 153 drm_sis_fb_t fb;
157 154
158 DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_fb_t __user *)data, sizeof(fb)); 155 DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_fb_t __user *) data, sizeof(fb));
159 156
160 if (dev_priv == NULL) { 157 if (dev_priv == NULL) {
161 dev->dev_private = drm_calloc(1, sizeof(drm_sis_private_t), 158 dev->dev_private = drm_calloc(1, sizeof(drm_sis_private_t),
162 DRM_MEM_DRIVER); 159 DRM_MEM_DRIVER);
163 dev_priv = dev->dev_private; 160 dev_priv = dev->dev_private;
164 if (dev_priv == NULL) 161 if (dev_priv == NULL)
165 return ENOMEM; 162 return ENOMEM;
@@ -175,7 +172,7 @@ static int sis_fb_init( DRM_IOCTL_ARGS )
175 return 0; 172 return 0;
176} 173}
177 174
178static int sis_fb_alloc( DRM_IOCTL_ARGS ) 175static int sis_fb_alloc(DRM_IOCTL_ARGS)
179{ 176{
180 DRM_DEVICE; 177 DRM_DEVICE;
181 drm_sis_private_t *dev_priv = dev->dev_private; 178 drm_sis_private_t *dev_priv = dev->dev_private;
@@ -186,9 +183,9 @@ static int sis_fb_alloc( DRM_IOCTL_ARGS )
186 183
187 if (dev_priv == NULL || dev_priv->FBHeap == NULL) 184 if (dev_priv == NULL || dev_priv->FBHeap == NULL)
188 return DRM_ERR(EINVAL); 185 return DRM_ERR(EINVAL);
189 186
190 DRM_COPY_FROM_USER_IOCTL(fb, argp, sizeof(fb)); 187 DRM_COPY_FROM_USER_IOCTL(fb, argp, sizeof(fb));
191 188
192 block = mmAllocMem(dev_priv->FBHeap, fb.size, 0, 0); 189 block = mmAllocMem(dev_priv->FBHeap, fb.size, 0, 0);
193 if (block) { 190 if (block) {
194 /* TODO */ 191 /* TODO */
@@ -196,7 +193,7 @@ static int sis_fb_alloc( DRM_IOCTL_ARGS )
196 fb.free = (unsigned long)block; 193 fb.free = (unsigned long)block;
197 if (!add_alloc_set(fb.context, VIDEO_TYPE, fb.free)) { 194 if (!add_alloc_set(fb.context, VIDEO_TYPE, fb.free)) {
198 DRM_DEBUG("adding to allocation set fails\n"); 195 DRM_DEBUG("adding to allocation set fails\n");
199 mmFreeMem((PMemBlock)fb.free); 196 mmFreeMem((PMemBlock) fb.free);
200 retval = DRM_ERR(EINVAL); 197 retval = DRM_ERR(EINVAL);
201 } 198 }
202 } else { 199 } else {
@@ -212,7 +209,7 @@ static int sis_fb_alloc( DRM_IOCTL_ARGS )
212 return retval; 209 return retval;
213} 210}
214 211
215static int sis_fb_free( DRM_IOCTL_ARGS ) 212static int sis_fb_free(DRM_IOCTL_ARGS)
216{ 213{
217 DRM_DEVICE; 214 DRM_DEVICE;
218 drm_sis_private_t *dev_priv = dev->dev_private; 215 drm_sis_private_t *dev_priv = dev->dev_private;
@@ -221,14 +218,14 @@ static int sis_fb_free( DRM_IOCTL_ARGS )
221 if (dev_priv == NULL || dev_priv->FBHeap == NULL) 218 if (dev_priv == NULL || dev_priv->FBHeap == NULL)
222 return DRM_ERR(EINVAL); 219 return DRM_ERR(EINVAL);
223 220
224 DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_mem_t __user *)data, sizeof(fb)); 221 DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_mem_t __user *) data, sizeof(fb));
225 222
226 if (!mmBlockInHeap(dev_priv->FBHeap, (PMemBlock)fb.free)) 223 if (!mmBlockInHeap(dev_priv->FBHeap, (PMemBlock) fb.free))
227 return DRM_ERR(EINVAL); 224 return DRM_ERR(EINVAL);
228 225
229 if (!del_alloc_set(fb.context, VIDEO_TYPE, fb.free)) 226 if (!del_alloc_set(fb.context, VIDEO_TYPE, fb.free))
230 return DRM_ERR(EINVAL); 227 return DRM_ERR(EINVAL);
231 mmFreeMem((PMemBlock)fb.free); 228 mmFreeMem((PMemBlock) fb.free);
232 229
233 DRM_DEBUG("free fb, free = 0x%lx\n", fb.free); 230 DRM_DEBUG("free fb, free = 0x%lx\n", fb.free);
234 231
@@ -237,9 +234,9 @@ static int sis_fb_free( DRM_IOCTL_ARGS )
237 234
238#endif 235#endif
239 236
240/* agp memory management */ 237/* agp memory management */
241 238
242static int sis_ioctl_agp_init( DRM_IOCTL_ARGS ) 239static int sis_ioctl_agp_init(DRM_IOCTL_ARGS)
243{ 240{
244 DRM_DEVICE; 241 DRM_DEVICE;
245 drm_sis_private_t *dev_priv = dev->dev_private; 242 drm_sis_private_t *dev_priv = dev->dev_private;
@@ -247,7 +244,7 @@ static int sis_ioctl_agp_init( DRM_IOCTL_ARGS )
247 244
248 if (dev_priv == NULL) { 245 if (dev_priv == NULL) {
249 dev->dev_private = drm_calloc(1, sizeof(drm_sis_private_t), 246 dev->dev_private = drm_calloc(1, sizeof(drm_sis_private_t),
250 DRM_MEM_DRIVER); 247 DRM_MEM_DRIVER);
251 dev_priv = dev->dev_private; 248 dev_priv = dev->dev_private;
252 if (dev_priv == NULL) 249 if (dev_priv == NULL)
253 return ENOMEM; 250 return ENOMEM;
@@ -256,16 +253,17 @@ static int sis_ioctl_agp_init( DRM_IOCTL_ARGS )
256 if (dev_priv->AGPHeap != NULL) 253 if (dev_priv->AGPHeap != NULL)
257 return DRM_ERR(EINVAL); 254 return DRM_ERR(EINVAL);
258 255
259 DRM_COPY_FROM_USER_IOCTL(agp, (drm_sis_agp_t __user *)data, sizeof(agp)); 256 DRM_COPY_FROM_USER_IOCTL(agp, (drm_sis_agp_t __user *) data,
257 sizeof(agp));
260 258
261 dev_priv->AGPHeap = mmInit(agp.offset, agp.size); 259 dev_priv->AGPHeap = mmInit(agp.offset, agp.size);
262 260
263 DRM_DEBUG("offset = %u, size = %u", agp.offset, agp.size); 261 DRM_DEBUG("offset = %u, size = %u", agp.offset, agp.size);
264 262
265 return 0; 263 return 0;
266} 264}
267 265
268static int sis_ioctl_agp_alloc( DRM_IOCTL_ARGS ) 266static int sis_ioctl_agp_alloc(DRM_IOCTL_ARGS)
269{ 267{
270 DRM_DEVICE; 268 DRM_DEVICE;
271 drm_sis_private_t *dev_priv = dev->dev_private; 269 drm_sis_private_t *dev_priv = dev->dev_private;
@@ -273,12 +271,12 @@ static int sis_ioctl_agp_alloc( DRM_IOCTL_ARGS )
273 drm_sis_mem_t agp; 271 drm_sis_mem_t agp;
274 PMemBlock block; 272 PMemBlock block;
275 int retval = 0; 273 int retval = 0;
276 274
277 if (dev_priv == NULL || dev_priv->AGPHeap == NULL) 275 if (dev_priv == NULL || dev_priv->AGPHeap == NULL)
278 return DRM_ERR(EINVAL); 276 return DRM_ERR(EINVAL);
279 277
280 DRM_COPY_FROM_USER_IOCTL(agp, argp, sizeof(agp)); 278 DRM_COPY_FROM_USER_IOCTL(agp, argp, sizeof(agp));
281 279
282 block = mmAllocMem(dev_priv->AGPHeap, agp.size, 0, 0); 280 block = mmAllocMem(dev_priv->AGPHeap, agp.size, 0, 0);
283 if (block) { 281 if (block) {
284 /* TODO */ 282 /* TODO */
@@ -286,10 +284,10 @@ static int sis_ioctl_agp_alloc( DRM_IOCTL_ARGS )
286 agp.free = (unsigned long)block; 284 agp.free = (unsigned long)block;
287 if (!add_alloc_set(agp.context, AGP_TYPE, agp.free)) { 285 if (!add_alloc_set(agp.context, AGP_TYPE, agp.free)) {
288 DRM_DEBUG("adding to allocation set fails\n"); 286 DRM_DEBUG("adding to allocation set fails\n");
289 mmFreeMem((PMemBlock)agp.free); 287 mmFreeMem((PMemBlock) agp.free);
290 retval = -1; 288 retval = -1;
291 } 289 }
292 } else { 290 } else {
293 agp.offset = 0; 291 agp.offset = 0;
294 agp.size = 0; 292 agp.size = 0;
295 agp.free = 0; 293 agp.free = 0;
@@ -302,7 +300,7 @@ static int sis_ioctl_agp_alloc( DRM_IOCTL_ARGS )
302 return retval; 300 return retval;
303} 301}
304 302
305static int sis_ioctl_agp_free( DRM_IOCTL_ARGS ) 303static int sis_ioctl_agp_free(DRM_IOCTL_ARGS)
306{ 304{
307 DRM_DEVICE; 305 DRM_DEVICE;
308 drm_sis_private_t *dev_priv = dev->dev_private; 306 drm_sis_private_t *dev_priv = dev->dev_private;
@@ -311,12 +309,13 @@ static int sis_ioctl_agp_free( DRM_IOCTL_ARGS )
311 if (dev_priv == NULL || dev_priv->AGPHeap == NULL) 309 if (dev_priv == NULL || dev_priv->AGPHeap == NULL)
312 return DRM_ERR(EINVAL); 310 return DRM_ERR(EINVAL);
313 311
314 DRM_COPY_FROM_USER_IOCTL(agp, (drm_sis_mem_t __user *)data, sizeof(agp)); 312 DRM_COPY_FROM_USER_IOCTL(agp, (drm_sis_mem_t __user *) data,
313 sizeof(agp));
315 314
316 if (!mmBlockInHeap(dev_priv->AGPHeap, (PMemBlock)agp.free)) 315 if (!mmBlockInHeap(dev_priv->AGPHeap, (PMemBlock) agp.free))
317 return DRM_ERR(EINVAL); 316 return DRM_ERR(EINVAL);
318 317
319 mmFreeMem((PMemBlock)agp.free); 318 mmFreeMem((PMemBlock) agp.free);
320 if (!del_alloc_set(agp.context, AGP_TYPE, agp.free)) 319 if (!del_alloc_set(agp.context, AGP_TYPE, agp.free))
321 return DRM_ERR(EINVAL); 320 return DRM_ERR(EINVAL);
322 321
@@ -329,31 +328,30 @@ int sis_init_context(struct drm_device *dev, int context)
329{ 328{
330 int i; 329 int i;
331 330
332 for (i = 0; i < MAX_CONTEXT ; i++) { 331 for (i = 0; i < MAX_CONTEXT; i++) {
333 if (global_ppriv[i].used && 332 if (global_ppriv[i].used &&
334 (global_ppriv[i].context == context)) 333 (global_ppriv[i].context == context))
335 break; 334 break;
336 } 335 }
337 336
338 if (i >= MAX_CONTEXT) { 337 if (i >= MAX_CONTEXT) {
339 for (i = 0; i < MAX_CONTEXT ; i++) { 338 for (i = 0; i < MAX_CONTEXT; i++) {
340 if (!global_ppriv[i].used) { 339 if (!global_ppriv[i].used) {
341 global_ppriv[i].context = context; 340 global_ppriv[i].context = context;
342 global_ppriv[i].used = 1; 341 global_ppriv[i].used = 1;
343 global_ppriv[i].sets[0] = setInit(); 342 global_ppriv[i].sets[0] = setInit();
344 global_ppriv[i].sets[1] = setInit(); 343 global_ppriv[i].sets[1] = setInit();
345 DRM_DEBUG("init allocation set, socket=%d, " 344 DRM_DEBUG("init allocation set, socket=%d, "
346 "context = %d\n", i, context); 345 "context = %d\n", i, context);
347 break; 346 break;
348 } 347 }
349 } 348 }
350 if ((i >= MAX_CONTEXT) || (global_ppriv[i].sets[0] == NULL) || 349 if ((i >= MAX_CONTEXT) || (global_ppriv[i].sets[0] == NULL) ||
351 (global_ppriv[i].sets[1] == NULL)) 350 (global_ppriv[i].sets[1] == NULL)) {
352 {
353 return 0; 351 return 0;
354 } 352 }
355 } 353 }
356 354
357 return 1; 355 return 1;
358} 356}
359 357
@@ -361,7 +359,7 @@ int sis_final_context(struct drm_device *dev, int context)
361{ 359{
362 int i; 360 int i;
363 361
364 for (i=0; i<MAX_CONTEXT; i++) { 362 for (i = 0; i < MAX_CONTEXT; i++) {
365 if (global_ppriv[i].used && 363 if (global_ppriv[i].used &&
366 (global_ppriv[i].context == context)) 364 (global_ppriv[i].context == context))
367 break; 365 break;
@@ -382,7 +380,7 @@ int sis_final_context(struct drm_device *dev, int context)
382#if defined(__linux__) && defined(CONFIG_FB_SIS) 380#if defined(__linux__) && defined(CONFIG_FB_SIS)
383 sis_free(item); 381 sis_free(item);
384#else 382#else
385 mmFreeMem((PMemBlock)item); 383 mmFreeMem((PMemBlock) item);
386#endif 384#endif
387 retval = setNext(set, &item); 385 retval = setNext(set, &item);
388 } 386 }
@@ -393,25 +391,29 @@ int sis_final_context(struct drm_device *dev, int context)
393 retval = setFirst(set, &item); 391 retval = setFirst(set, &item);
394 while (retval) { 392 while (retval) {
395 DRM_DEBUG("free agp memory 0x%x\n", item); 393 DRM_DEBUG("free agp memory 0x%x\n", item);
396 mmFreeMem((PMemBlock)item); 394 mmFreeMem((PMemBlock) item);
397 retval = setNext(set, &item); 395 retval = setNext(set, &item);
398 } 396 }
399 setDestroy(set); 397 setDestroy(set);
400 398
401 global_ppriv[i].used = 0; 399 global_ppriv[i].used = 0;
402 } 400 }
403 401
404 return 1; 402 return 1;
405} 403}
406 404
407drm_ioctl_desc_t sis_ioctls[] = { 405drm_ioctl_desc_t sis_ioctls[] = {
408 [DRM_IOCTL_NR(DRM_SIS_FB_ALLOC)] = { sis_fb_alloc, 1, 0 }, 406 [DRM_IOCTL_NR(DRM_SIS_FB_ALLOC)] = {sis_fb_alloc, 1, 0}
409 [DRM_IOCTL_NR(DRM_SIS_FB_FREE)] = { sis_fb_free, 1, 0 }, 407 ,
410 [DRM_IOCTL_NR(DRM_SIS_AGP_INIT)] = { sis_ioctl_agp_init, 1, 1 }, 408 [DRM_IOCTL_NR(DRM_SIS_FB_FREE)] = {sis_fb_free, 1, 0}
411 [DRM_IOCTL_NR(DRM_SIS_AGP_ALLOC)] = { sis_ioctl_agp_alloc, 1, 0 }, 409 ,
412 [DRM_IOCTL_NR(DRM_SIS_AGP_FREE)] = { sis_ioctl_agp_free, 1, 0 }, 410 [DRM_IOCTL_NR(DRM_SIS_AGP_INIT)] = {sis_ioctl_agp_init, 1, 1}
413 [DRM_IOCTL_NR(DRM_SIS_FB_INIT)] = { sis_fb_init, 1, 1 } 411 ,
412 [DRM_IOCTL_NR(DRM_SIS_AGP_ALLOC)] = {sis_ioctl_agp_alloc, 1, 0}
413 ,
414 [DRM_IOCTL_NR(DRM_SIS_AGP_FREE)] = {sis_ioctl_agp_free, 1, 0}
415 ,
416 [DRM_IOCTL_NR(DRM_SIS_FB_INIT)] = {sis_fb_init, 1, 1}
414}; 417};
415 418
416int sis_max_ioctl = DRM_ARRAY_SIZE(sis_ioctls); 419int sis_max_ioctl = DRM_ARRAY_SIZE(sis_ioctls);
417
diff --git a/drivers/char/drm/tdfx_drv.c b/drivers/char/drm/tdfx_drv.c
index 0e7943e6efea..c275cbb6e9ce 100644
--- a/drivers/char/drm/tdfx_drv.c
+++ b/drivers/char/drm/tdfx_drv.c
@@ -36,30 +36,28 @@
36 36
37#include "drm_pciids.h" 37#include "drm_pciids.h"
38 38
39static int postinit( struct drm_device *dev, unsigned long flags ) 39static int postinit(struct drm_device *dev, unsigned long flags)
40{ 40{
41 DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", 41 DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n",
42 DRIVER_NAME, 42 DRIVER_NAME,
43 DRIVER_MAJOR, 43 DRIVER_MAJOR,
44 DRIVER_MINOR, 44 DRIVER_MINOR,
45 DRIVER_PATCHLEVEL, 45 DRIVER_PATCHLEVEL,
46 DRIVER_DATE, 46 DRIVER_DATE, dev->primary.minor, pci_pretty_name(dev->pdev)
47 dev->primary.minor, 47 );
48 pci_pretty_name(dev->pdev)
49 );
50 return 0; 48 return 0;
51} 49}
52 50
53static int version( drm_version_t *version ) 51static int version(drm_version_t * version)
54{ 52{
55 int len; 53 int len;
56 54
57 version->version_major = DRIVER_MAJOR; 55 version->version_major = DRIVER_MAJOR;
58 version->version_minor = DRIVER_MINOR; 56 version->version_minor = DRIVER_MINOR;
59 version->version_patchlevel = DRIVER_PATCHLEVEL; 57 version->version_patchlevel = DRIVER_PATCHLEVEL;
60 DRM_COPY( version->name, DRIVER_NAME ); 58 DRM_COPY(version->name, DRIVER_NAME);
61 DRM_COPY( version->date, DRIVER_DATE ); 59 DRM_COPY(version->date, DRIVER_DATE);
62 DRM_COPY( version->desc, DRIVER_DESC ); 60 DRM_COPY(version->desc, DRIVER_DESC);
63 return 0; 61 return 0;
64} 62}
65 63
@@ -75,18 +73,18 @@ static struct drm_driver driver = {
75 .postinit = postinit, 73 .postinit = postinit,
76 .version = version, 74 .version = version,
77 .fops = { 75 .fops = {
78 .owner = THIS_MODULE, 76 .owner = THIS_MODULE,
79 .open = drm_open, 77 .open = drm_open,
80 .release = drm_release, 78 .release = drm_release,
81 .ioctl = drm_ioctl, 79 .ioctl = drm_ioctl,
82 .mmap = drm_mmap, 80 .mmap = drm_mmap,
83 .poll = drm_poll, 81 .poll = drm_poll,
84 .fasync = drm_fasync, 82 .fasync = drm_fasync,
85 }, 83 },
86 .pci_driver = { 84 .pci_driver = {
87 .name = DRIVER_NAME, 85 .name = DRIVER_NAME,
88 .id_table = pciidlist, 86 .id_table = pciidlist,
89 } 87 }
90}; 88};
91 89
92static int __init tdfx_init(void) 90static int __init tdfx_init(void)
@@ -102,6 +100,6 @@ static void __exit tdfx_exit(void)
102module_init(tdfx_init); 100module_init(tdfx_init);
103module_exit(tdfx_exit); 101module_exit(tdfx_exit);
104 102
105MODULE_AUTHOR( DRIVER_AUTHOR ); 103MODULE_AUTHOR(DRIVER_AUTHOR);
106MODULE_DESCRIPTION( DRIVER_DESC ); 104MODULE_DESCRIPTION(DRIVER_DESC);
107MODULE_LICENSE("GPL and additional rights"); 105MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/char/drm/via_3d_reg.h b/drivers/char/drm/via_3d_reg.h
index cf61bb514db1..462375d543b9 100644
--- a/drivers/char/drm/via_3d_reg.h
+++ b/drivers/char/drm/via_3d_reg.h
@@ -1643,7 +1643,6 @@
1643#define HC_HAGPBpID_STOP 0x00000002 1643#define HC_HAGPBpID_STOP 0x00000002
1644#define HC_HAGPBpH_MASK 0x00ffffff 1644#define HC_HAGPBpH_MASK 0x00ffffff
1645 1645
1646
1647#define VIA_VIDEO_HEADER5 0xFE040000 1646#define VIA_VIDEO_HEADER5 0xFE040000
1648#define VIA_VIDEO_HEADER6 0xFE050000 1647#define VIA_VIDEO_HEADER6 0xFE050000
1649#define VIA_VIDEO_HEADER7 0xFE060000 1648#define VIA_VIDEO_HEADER7 0xFE060000
diff --git a/drivers/char/drm/via_dma.c b/drivers/char/drm/via_dma.c
index 4f60f7f4193d..d4b1766608b0 100644
--- a/drivers/char/drm/via_dma.c
+++ b/drivers/char/drm/via_dma.c
@@ -1,11 +1,11 @@
1/* via_dma.c -- DMA support for the VIA Unichrome/Pro 1/* via_dma.c -- DMA support for the VIA Unichrome/Pro
2 * 2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved. 4 * All Rights Reserved.
5 * 5 *
6 * Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A. 6 * Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A.
7 * All Rights Reserved. 7 * All Rights Reserved.
8 * 8 *
9 * Copyright 2004 The Unichrome project. 9 * Copyright 2004 The Unichrome project.
10 * All Rights Reserved. 10 * All Rights Reserved.
11 * 11 *
@@ -23,14 +23,14 @@
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
26 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 26 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
27 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 27 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
28 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 28 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
29 * USE OR OTHER DEALINGS IN THE SOFTWARE. 29 * USE OR OTHER DEALINGS IN THE SOFTWARE.
30 * 30 *
31 * Authors: 31 * Authors:
32 * Tungsten Graphics, 32 * Tungsten Graphics,
33 * Erdi Chen, 33 * Erdi Chen,
34 * Thomas Hellstrom. 34 * Thomas Hellstrom.
35 */ 35 */
36 36
@@ -61,34 +61,31 @@
61 dev_priv->dma_low +=8; \ 61 dev_priv->dma_low +=8; \
62} 62}
63 63
64#define via_flush_write_combine() DRM_MEMORYBARRIER() 64#define via_flush_write_combine() DRM_MEMORYBARRIER()
65 65
66#define VIA_OUT_RING_QW(w1,w2) \ 66#define VIA_OUT_RING_QW(w1,w2) \
67 *vb++ = (w1); \ 67 *vb++ = (w1); \
68 *vb++ = (w2); \ 68 *vb++ = (w2); \
69 dev_priv->dma_low += 8; 69 dev_priv->dma_low += 8;
70 70
71static void via_cmdbuf_start(drm_via_private_t * dev_priv); 71static void via_cmdbuf_start(drm_via_private_t * dev_priv);
72static void via_cmdbuf_pause(drm_via_private_t * dev_priv); 72static void via_cmdbuf_pause(drm_via_private_t * dev_priv);
73static void via_cmdbuf_reset(drm_via_private_t * dev_priv); 73static void via_cmdbuf_reset(drm_via_private_t * dev_priv);
74static void via_cmdbuf_rewind(drm_via_private_t * dev_priv); 74static void via_cmdbuf_rewind(drm_via_private_t * dev_priv);
75static int via_wait_idle(drm_via_private_t * dev_priv); 75static int via_wait_idle(drm_via_private_t * dev_priv);
76static void via_pad_cache(drm_via_private_t *dev_priv, int qwords); 76static void via_pad_cache(drm_via_private_t * dev_priv, int qwords);
77
78 77
79/* 78/*
80 * Free space in command buffer. 79 * Free space in command buffer.
81 */ 80 */
82 81
83static uint32_t 82static uint32_t via_cmdbuf_space(drm_via_private_t * dev_priv)
84via_cmdbuf_space(drm_via_private_t *dev_priv)
85{ 83{
86 uint32_t agp_base = dev_priv->dma_offset + 84 uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
87 (uint32_t) dev_priv->agpAddr;
88 uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base; 85 uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
89 86
90 return ((hw_addr <= dev_priv->dma_low) ? 87 return ((hw_addr <= dev_priv->dma_low) ?
91 (dev_priv->dma_high + hw_addr - dev_priv->dma_low) : 88 (dev_priv->dma_high + hw_addr - dev_priv->dma_low) :
92 (hw_addr - dev_priv->dma_low)); 89 (hw_addr - dev_priv->dma_low));
93} 90}
94 91
@@ -96,15 +93,13 @@ via_cmdbuf_space(drm_via_private_t *dev_priv)
96 * How much does the command regulator lag behind? 93 * How much does the command regulator lag behind?
97 */ 94 */
98 95
99static uint32_t 96static uint32_t via_cmdbuf_lag(drm_via_private_t * dev_priv)
100via_cmdbuf_lag(drm_via_private_t *dev_priv)
101{ 97{
102 uint32_t agp_base = dev_priv->dma_offset + 98 uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
103 (uint32_t) dev_priv->agpAddr;
104 uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base; 99 uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
105 100
106 return ((hw_addr <= dev_priv->dma_low) ? 101 return ((hw_addr <= dev_priv->dma_low) ?
107 (dev_priv->dma_low - hw_addr) : 102 (dev_priv->dma_low - hw_addr) :
108 (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr)); 103 (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr));
109} 104}
110 105
@@ -121,20 +116,20 @@ via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)
121 uint32_t count; 116 uint32_t count;
122 hw_addr_ptr = dev_priv->hw_addr_ptr; 117 hw_addr_ptr = dev_priv->hw_addr_ptr;
123 cur_addr = dev_priv->dma_low; 118 cur_addr = dev_priv->dma_low;
124 next_addr = cur_addr + size + 512*1024; 119 next_addr = cur_addr + size + 512 * 1024;
125 count = 1000000; 120 count = 1000000;
126 do { 121 do {
127 hw_addr = *hw_addr_ptr - agp_base; 122 hw_addr = *hw_addr_ptr - agp_base;
128 if (count-- == 0) { 123 if (count-- == 0) {
129 DRM_ERROR("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n", 124 DRM_ERROR
130 hw_addr, cur_addr, next_addr); 125 ("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n",
126 hw_addr, cur_addr, next_addr);
131 return -1; 127 return -1;
132 } 128 }
133 } while ((cur_addr < hw_addr) && (next_addr >= hw_addr)); 129 } while ((cur_addr < hw_addr) && (next_addr >= hw_addr));
134 return 0; 130 return 0;
135} 131}
136 132
137
138/* 133/*
139 * Checks whether buffer head has reach the end. Rewind the ring buffer 134 * Checks whether buffer head has reach the end. Rewind the ring buffer
140 * when necessary. 135 * when necessary.
@@ -145,7 +140,8 @@ via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)
145static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv, 140static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv,
146 unsigned int size) 141 unsigned int size)
147{ 142{
148 if ((dev_priv->dma_low + size + 4*CMDBUF_ALIGNMENT_SIZE) > dev_priv->dma_high) { 143 if ((dev_priv->dma_low + size + 4 * CMDBUF_ALIGNMENT_SIZE) >
144 dev_priv->dma_high) {
149 via_cmdbuf_rewind(dev_priv); 145 via_cmdbuf_rewind(dev_priv);
150 } 146 }
151 if (via_cmdbuf_wait(dev_priv, size) != 0) { 147 if (via_cmdbuf_wait(dev_priv, size) != 0) {
@@ -159,7 +155,7 @@ int via_dma_cleanup(drm_device_t * dev)
159{ 155{
160 if (dev->dev_private) { 156 if (dev->dev_private) {
161 drm_via_private_t *dev_priv = 157 drm_via_private_t *dev_priv =
162 (drm_via_private_t *) dev->dev_private; 158 (drm_via_private_t *) dev->dev_private;
163 159
164 if (dev_priv->ring.virtual_start) { 160 if (dev_priv->ring.virtual_start) {
165 via_cmdbuf_reset(dev_priv); 161 via_cmdbuf_reset(dev_priv);
@@ -189,7 +185,7 @@ static int via_initialize(drm_device_t * dev,
189 } 185 }
190 186
191 if (!dev->agp || !dev->agp->base) { 187 if (!dev->agp || !dev->agp->base) {
192 DRM_ERROR("%s called with no agp memory available\n", 188 DRM_ERROR("%s called with no agp memory available\n",
193 __FUNCTION__); 189 __FUNCTION__);
194 return DRM_ERR(EFAULT); 190 return DRM_ERR(EFAULT);
195 } 191 }
@@ -247,10 +243,10 @@ int via_dma_init(DRM_IOCTL_ARGS)
247 else 243 else
248 retcode = via_dma_cleanup(dev); 244 retcode = via_dma_cleanup(dev);
249 break; 245 break;
250 case VIA_DMA_INITIALIZED: 246 case VIA_DMA_INITIALIZED:
251 retcode = (dev_priv->ring.virtual_start != NULL) ? 247 retcode = (dev_priv->ring.virtual_start != NULL) ?
252 0: DRM_ERR( EFAULT ); 248 0 : DRM_ERR(EFAULT);
253 break; 249 break;
254 default: 250 default:
255 retcode = DRM_ERR(EINVAL); 251 retcode = DRM_ERR(EINVAL);
256 break; 252 break;
@@ -259,8 +255,6 @@ int via_dma_init(DRM_IOCTL_ARGS)
259 return retcode; 255 return retcode;
260} 256}
261 257
262
263
264static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd) 258static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd)
265{ 259{
266 drm_via_private_t *dev_priv; 260 drm_via_private_t *dev_priv;
@@ -277,8 +271,7 @@ static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd)
277 271
278 if (cmd->size > VIA_PCI_BUF_SIZE) { 272 if (cmd->size > VIA_PCI_BUF_SIZE) {
279 return DRM_ERR(ENOMEM); 273 return DRM_ERR(ENOMEM);
280 } 274 }
281
282 275
283 if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size)) 276 if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
284 return DRM_ERR(EFAULT); 277 return DRM_ERR(EFAULT);
@@ -289,19 +282,19 @@ static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd)
289 * copy it to AGP memory when ready. 282 * copy it to AGP memory when ready.
290 */ 283 */
291 284
292 285 if ((ret =
293 if ((ret = via_verify_command_stream((uint32_t *)dev_priv->pci_buf, cmd->size, dev, 1))) { 286 via_verify_command_stream((uint32_t *) dev_priv->pci_buf,
287 cmd->size, dev, 1))) {
294 return ret; 288 return ret;
295 } 289 }
296 290
297
298 vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size); 291 vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size);
299 if (vb == NULL) { 292 if (vb == NULL) {
300 return DRM_ERR(EAGAIN); 293 return DRM_ERR(EAGAIN);
301 } 294 }
302 295
303 memcpy(vb, dev_priv->pci_buf, cmd->size); 296 memcpy(vb, dev_priv->pci_buf, cmd->size);
304 297
305 dev_priv->dma_low += cmd->size; 298 dev_priv->dma_low += cmd->size;
306 299
307 /* 300 /*
@@ -310,7 +303,7 @@ static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd)
310 */ 303 */
311 304
312 if (cmd->size < 0x100) 305 if (cmd->size < 0x100)
313 via_pad_cache(dev_priv,(0x100 - cmd->size) >> 3); 306 via_pad_cache(dev_priv, (0x100 - cmd->size) >> 3);
314 via_cmdbuf_pause(dev_priv); 307 via_cmdbuf_pause(dev_priv);
315 308
316 return 0; 309 return 0;
@@ -330,7 +323,7 @@ int via_flush_ioctl(DRM_IOCTL_ARGS)
330{ 323{
331 DRM_DEVICE; 324 DRM_DEVICE;
332 325
333 LOCK_TEST_WITH_RETURN( dev, filp ); 326 LOCK_TEST_WITH_RETURN(dev, filp);
334 327
335 return via_driver_dma_quiescent(dev); 328 return via_driver_dma_quiescent(dev);
336} 329}
@@ -341,7 +334,7 @@ int via_cmdbuffer(DRM_IOCTL_ARGS)
341 drm_via_cmdbuffer_t cmdbuf; 334 drm_via_cmdbuffer_t cmdbuf;
342 int ret; 335 int ret;
343 336
344 LOCK_TEST_WITH_RETURN( dev, filp ); 337 LOCK_TEST_WITH_RETURN(dev, filp);
345 338
346 DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data, 339 DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data,
347 sizeof(cmdbuf)); 340 sizeof(cmdbuf));
@@ -356,8 +349,9 @@ int via_cmdbuffer(DRM_IOCTL_ARGS)
356 return 0; 349 return 0;
357} 350}
358 351
359extern int 352extern int
360via_parse_command_stream(drm_device_t *dev, const uint32_t * buf, unsigned int size); 353via_parse_command_stream(drm_device_t * dev, const uint32_t * buf,
354 unsigned int size);
361static int via_dispatch_pci_cmdbuffer(drm_device_t * dev, 355static int via_dispatch_pci_cmdbuffer(drm_device_t * dev,
362 drm_via_cmdbuffer_t * cmd) 356 drm_via_cmdbuffer_t * cmd)
363{ 357{
@@ -366,15 +360,19 @@ static int via_dispatch_pci_cmdbuffer(drm_device_t * dev,
366 360
367 if (cmd->size > VIA_PCI_BUF_SIZE) { 361 if (cmd->size > VIA_PCI_BUF_SIZE) {
368 return DRM_ERR(ENOMEM); 362 return DRM_ERR(ENOMEM);
369 } 363 }
370 if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size)) 364 if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
371 return DRM_ERR(EFAULT); 365 return DRM_ERR(EFAULT);
372 366
373 if ((ret = via_verify_command_stream((uint32_t *)dev_priv->pci_buf, cmd->size, dev, 0))) { 367 if ((ret =
368 via_verify_command_stream((uint32_t *) dev_priv->pci_buf,
369 cmd->size, dev, 0))) {
374 return ret; 370 return ret;
375 } 371 }
376 372
377 ret = via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf, cmd->size); 373 ret =
374 via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf,
375 cmd->size);
378 return ret; 376 return ret;
379} 377}
380 378
@@ -384,7 +382,7 @@ int via_pci_cmdbuffer(DRM_IOCTL_ARGS)
384 drm_via_cmdbuffer_t cmdbuf; 382 drm_via_cmdbuffer_t cmdbuf;
385 int ret; 383 int ret;
386 384
387 LOCK_TEST_WITH_RETURN( dev, filp ); 385 LOCK_TEST_WITH_RETURN(dev, filp);
388 386
389 DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data, 387 DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data,
390 sizeof(cmdbuf)); 388 sizeof(cmdbuf));
@@ -400,17 +398,15 @@ int via_pci_cmdbuffer(DRM_IOCTL_ARGS)
400 return 0; 398 return 0;
401} 399}
402 400
403
404static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv, 401static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv,
405 uint32_t * vb, int qw_count) 402 uint32_t * vb, int qw_count)
406{ 403{
407 for (; qw_count > 0; --qw_count) { 404 for (; qw_count > 0; --qw_count) {
408 VIA_OUT_RING_QW(HC_DUMMY, HC_DUMMY); 405 VIA_OUT_RING_QW(HC_DUMMY, HC_DUMMY);
409 } 406 }
410 return vb; 407 return vb;
411} 408}
412 409
413
414/* 410/*
415 * This function is used internally by ring buffer mangement code. 411 * This function is used internally by ring buffer mangement code.
416 * 412 *
@@ -426,7 +422,7 @@ static inline uint32_t *via_get_dma(drm_via_private_t * dev_priv)
426 * modifying the pause address stored in the buffer itself. If 422 * modifying the pause address stored in the buffer itself. If
427 * the regulator has already paused, restart it. 423 * the regulator has already paused, restart it.
428 */ 424 */
429static int via_hook_segment(drm_via_private_t *dev_priv, 425static int via_hook_segment(drm_via_private_t * dev_priv,
430 uint32_t pause_addr_hi, uint32_t pause_addr_lo, 426 uint32_t pause_addr_hi, uint32_t pause_addr_lo,
431 int no_pci_fire) 427 int no_pci_fire)
432{ 428{
@@ -434,7 +430,7 @@ static int via_hook_segment(drm_via_private_t *dev_priv,
434 volatile uint32_t *paused_at = dev_priv->last_pause_ptr; 430 volatile uint32_t *paused_at = dev_priv->last_pause_ptr;
435 431
436 via_flush_write_combine(); 432 via_flush_write_combine();
437 while(! *(via_get_dma(dev_priv)-1)); 433 while (!*(via_get_dma(dev_priv) - 1)) ;
438 *dev_priv->last_pause_ptr = pause_addr_lo; 434 *dev_priv->last_pause_ptr = pause_addr_lo;
439 via_flush_write_combine(); 435 via_flush_write_combine();
440 436
@@ -443,55 +439,53 @@ static int via_hook_segment(drm_via_private_t *dev_priv,
443 * Not sure it is needed. 439 * Not sure it is needed.
444 */ 440 */
445 441
446 while(! *dev_priv->last_pause_ptr); 442 while (!*dev_priv->last_pause_ptr) ;
447 dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1; 443 dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1;
448 while(! *dev_priv->last_pause_ptr); 444 while (!*dev_priv->last_pause_ptr) ;
449
450 445
451 paused = 0; 446 paused = 0;
452 count = 20; 447 count = 20;
453 448
454 while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--); 449 while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--) ;
455 if ((count <= 8) && (count >= 0)) { 450 if ((count <= 8) && (count >= 0)) {
456 uint32_t rgtr, ptr; 451 uint32_t rgtr, ptr;
457 rgtr = *(dev_priv->hw_addr_ptr); 452 rgtr = *(dev_priv->hw_addr_ptr);
458 ptr = ((char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) + 453 ptr = ((char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) +
459 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4 - 454 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4 -
460 CMDBUF_ALIGNMENT_SIZE; 455 CMDBUF_ALIGNMENT_SIZE;
461 if (rgtr <= ptr) { 456 if (rgtr <= ptr) {
462 DRM_ERROR("Command regulator\npaused at count %d, address %x, " 457 DRM_ERROR
463 "while current pause address is %x.\n" 458 ("Command regulator\npaused at count %d, address %x, "
464 "Please mail this message to " 459 "while current pause address is %x.\n"
465 "<unichrome-devel@lists.sourceforge.net>\n", 460 "Please mail this message to "
466 count, rgtr, ptr); 461 "<unichrome-devel@lists.sourceforge.net>\n", count,
462 rgtr, ptr);
467 } 463 }
468 } 464 }
469 465
470 if (paused && !no_pci_fire) { 466 if (paused && !no_pci_fire) {
471 uint32_t rgtr,ptr; 467 uint32_t rgtr, ptr;
472 uint32_t ptr_low; 468 uint32_t ptr_low;
473 469
474 count = 1000000; 470 count = 1000000;
475 while ((VIA_READ(VIA_REG_STATUS) & VIA_CMD_RGTR_BUSY) && count--); 471 while ((VIA_READ(VIA_REG_STATUS) & VIA_CMD_RGTR_BUSY)
476 472 && count--) ;
473
477 rgtr = *(dev_priv->hw_addr_ptr); 474 rgtr = *(dev_priv->hw_addr_ptr);
478 ptr = ((char *)paused_at - dev_priv->dma_ptr) + 475 ptr = ((char *)paused_at - dev_priv->dma_ptr) +
479 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4; 476 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
480
481 477
482 ptr_low = (ptr > 3*CMDBUF_ALIGNMENT_SIZE) ? 478 ptr_low = (ptr > 3 * CMDBUF_ALIGNMENT_SIZE) ?
483 ptr - 3*CMDBUF_ALIGNMENT_SIZE : 0; 479 ptr - 3 * CMDBUF_ALIGNMENT_SIZE : 0;
484 if (rgtr <= ptr && rgtr >= ptr_low) { 480 if (rgtr <= ptr && rgtr >= ptr_low) {
485 VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16)); 481 VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
486 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi); 482 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
487 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo); 483 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
488 } 484 }
489 } 485 }
490 return paused; 486 return paused;
491} 487}
492 488
493
494
495static int via_wait_idle(drm_via_private_t * dev_priv) 489static int via_wait_idle(drm_via_private_t * dev_priv)
496{ 490{
497 int count = 10000000; 491 int count = 10000000;
@@ -502,9 +496,8 @@ static int via_wait_idle(drm_via_private_t * dev_priv)
502} 496}
503 497
504static uint32_t *via_align_cmd(drm_via_private_t * dev_priv, uint32_t cmd_type, 498static uint32_t *via_align_cmd(drm_via_private_t * dev_priv, uint32_t cmd_type,
505 uint32_t addr, uint32_t *cmd_addr_hi, 499 uint32_t addr, uint32_t * cmd_addr_hi,
506 uint32_t *cmd_addr_lo, 500 uint32_t * cmd_addr_lo, int skip_wait)
507 int skip_wait)
508{ 501{
509 uint32_t agp_base; 502 uint32_t agp_base;
510 uint32_t cmd_addr, addr_lo, addr_hi; 503 uint32_t cmd_addr, addr_lo, addr_hi;
@@ -512,31 +505,26 @@ static uint32_t *via_align_cmd(drm_via_private_t * dev_priv, uint32_t cmd_type,
512 uint32_t qw_pad_count; 505 uint32_t qw_pad_count;
513 506
514 if (!skip_wait) 507 if (!skip_wait)
515 via_cmdbuf_wait(dev_priv, 2*CMDBUF_ALIGNMENT_SIZE); 508 via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE);
516 509
517 vb = via_get_dma(dev_priv); 510 vb = via_get_dma(dev_priv);
518 VIA_OUT_RING_QW( HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) | 511 VIA_OUT_RING_QW(HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
519 (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16); 512 (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16);
520 agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; 513 agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
521 qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) - 514 qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
522 ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3); 515 ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
523 516
524 517 cmd_addr = (addr) ? addr :
525 cmd_addr = (addr) ? addr : 518 agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
526 agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
527 addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) | 519 addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) |
528 (cmd_addr & HC_HAGPBpL_MASK)); 520 (cmd_addr & HC_HAGPBpL_MASK));
529 addr_hi = ((HC_SubA_HAGPBpH << 24) | (cmd_addr >> 24)); 521 addr_hi = ((HC_SubA_HAGPBpH << 24) | (cmd_addr >> 24));
530 522
531 vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1); 523 vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);
532 VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi, 524 VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi, *cmd_addr_lo = addr_lo);
533 *cmd_addr_lo = addr_lo);
534 return vb; 525 return vb;
535} 526}
536 527
537
538
539
540static void via_cmdbuf_start(drm_via_private_t * dev_priv) 528static void via_cmdbuf_start(drm_via_private_t * dev_priv)
541{ 529{
542 uint32_t pause_addr_lo, pause_addr_hi; 530 uint32_t pause_addr_lo, pause_addr_hi;
@@ -545,7 +533,6 @@ static void via_cmdbuf_start(drm_via_private_t * dev_priv)
545 uint32_t command; 533 uint32_t command;
546 uint32_t agp_base; 534 uint32_t agp_base;
547 535
548
549 dev_priv->dma_low = 0; 536 dev_priv->dma_low = 0;
550 537
551 agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; 538 agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
@@ -557,12 +544,12 @@ static void via_cmdbuf_start(drm_via_private_t * dev_priv)
557 command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) | 544 command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
558 ((end_addr & 0xff000000) >> 16)); 545 ((end_addr & 0xff000000) >> 16));
559 546
560 dev_priv->last_pause_ptr = 547 dev_priv->last_pause_ptr =
561 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, 548 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0,
562 &pause_addr_hi, & pause_addr_lo, 1) - 1; 549 &pause_addr_hi, &pause_addr_lo, 1) - 1;
563 550
564 via_flush_write_combine(); 551 via_flush_write_combine();
565 while(! *dev_priv->last_pause_ptr); 552 while (!*dev_priv->last_pause_ptr) ;
566 553
567 VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16)); 554 VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
568 VIA_WRITE(VIA_REG_TRANSPACE, command); 555 VIA_WRITE(VIA_REG_TRANSPACE, command);
@@ -575,14 +562,14 @@ static void via_cmdbuf_start(drm_via_private_t * dev_priv)
575 VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK); 562 VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);
576} 563}
577 564
578static void via_pad_cache(drm_via_private_t *dev_priv, int qwords) 565static void via_pad_cache(drm_via_private_t * dev_priv, int qwords)
579{ 566{
580 uint32_t *vb; 567 uint32_t *vb;
581 568
582 via_cmdbuf_wait(dev_priv, qwords + 2); 569 via_cmdbuf_wait(dev_priv, qwords + 2);
583 vb = via_get_dma(dev_priv); 570 vb = via_get_dma(dev_priv);
584 VIA_OUT_RING_QW( HC_HEADER2, HC_ParaType_NotTex << 16); 571 VIA_OUT_RING_QW(HC_HEADER2, HC_ParaType_NotTex << 16);
585 via_align_buffer(dev_priv,vb,qwords); 572 via_align_buffer(dev_priv, vb, qwords);
586} 573}
587 574
588static inline void via_dummy_bitblt(drm_via_private_t * dev_priv) 575static inline void via_dummy_bitblt(drm_via_private_t * dev_priv)
@@ -590,10 +577,9 @@ static inline void via_dummy_bitblt(drm_via_private_t * dev_priv)
590 uint32_t *vb = via_get_dma(dev_priv); 577 uint32_t *vb = via_get_dma(dev_priv);
591 SetReg2DAGP(0x0C, (0 | (0 << 16))); 578 SetReg2DAGP(0x0C, (0 | (0 << 16)));
592 SetReg2DAGP(0x10, 0 | (0 << 16)); 579 SetReg2DAGP(0x10, 0 | (0 << 16));
593 SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000); 580 SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);
594} 581}
595 582
596
597static void via_cmdbuf_jump(drm_via_private_t * dev_priv) 583static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
598{ 584{
599 uint32_t agp_base; 585 uint32_t agp_base;
@@ -603,11 +589,10 @@ static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
603 uint32_t dma_low_save1, dma_low_save2; 589 uint32_t dma_low_save1, dma_low_save2;
604 590
605 agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; 591 agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
606 via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi, 592 via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
607 &jump_addr_lo, 0); 593 &jump_addr_lo, 0);
608
609 dev_priv->dma_wrap = dev_priv->dma_low;
610 594
595 dev_priv->dma_wrap = dev_priv->dma_low;
611 596
612 /* 597 /*
613 * Wrap command buffer to the beginning. 598 * Wrap command buffer to the beginning.
@@ -619,11 +604,12 @@ static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
619 } 604 }
620 605
621 via_dummy_bitblt(dev_priv); 606 via_dummy_bitblt(dev_priv);
622 via_dummy_bitblt(dev_priv); 607 via_dummy_bitblt(dev_priv);
623 608
624 last_pause_ptr = via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, 609 last_pause_ptr =
625 &pause_addr_lo, 0) -1; 610 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
626 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, 611 &pause_addr_lo, 0) - 1;
612 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
627 &pause_addr_lo, 0); 613 &pause_addr_lo, 0);
628 614
629 *last_pause_ptr = pause_addr_lo; 615 *last_pause_ptr = pause_addr_lo;
@@ -638,23 +624,23 @@ static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
638 * does not seem to get updated immediately when a jump occurs. 624 * does not seem to get updated immediately when a jump occurs.
639 */ 625 */
640 626
641 last_pause_ptr = via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, 627 last_pause_ptr =
642 &pause_addr_lo, 0) -1; 628 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
643 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, 629 &pause_addr_lo, 0) - 1;
630 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
644 &pause_addr_lo, 0); 631 &pause_addr_lo, 0);
645 *last_pause_ptr = pause_addr_lo; 632 *last_pause_ptr = pause_addr_lo;
646 633
647 dma_low_save2 = dev_priv->dma_low; 634 dma_low_save2 = dev_priv->dma_low;
648 dev_priv->dma_low = dma_low_save1; 635 dev_priv->dma_low = dma_low_save1;
649 via_hook_segment( dev_priv, jump_addr_hi, jump_addr_lo, 0); 636 via_hook_segment(dev_priv, jump_addr_hi, jump_addr_lo, 0);
650 dev_priv->dma_low = dma_low_save2; 637 dev_priv->dma_low = dma_low_save2;
651 via_hook_segment( dev_priv, pause_addr_hi, pause_addr_lo, 0); 638 via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0);
652} 639}
653 640
654
655static void via_cmdbuf_rewind(drm_via_private_t * dev_priv) 641static void via_cmdbuf_rewind(drm_via_private_t * dev_priv)
656{ 642{
657 via_cmdbuf_jump(dev_priv); 643 via_cmdbuf_jump(dev_priv);
658} 644}
659 645
660static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type) 646static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type)
@@ -662,10 +648,9 @@ static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type)
662 uint32_t pause_addr_lo, pause_addr_hi; 648 uint32_t pause_addr_lo, pause_addr_hi;
663 649
664 via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0); 650 via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0);
665 via_hook_segment( dev_priv, pause_addr_hi, pause_addr_lo, 0); 651 via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0);
666} 652}
667 653
668
669static void via_cmdbuf_pause(drm_via_private_t * dev_priv) 654static void via_cmdbuf_pause(drm_via_private_t * dev_priv)
670{ 655{
671 via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE); 656 via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE);
@@ -681,8 +666,7 @@ static void via_cmdbuf_reset(drm_via_private_t * dev_priv)
681 * User interface to the space and lag functions. 666 * User interface to the space and lag functions.
682 */ 667 */
683 668
684int 669int via_cmdbuf_size(DRM_IOCTL_ARGS)
685via_cmdbuf_size(DRM_IOCTL_ARGS)
686{ 670{
687 DRM_DEVICE; 671 DRM_DEVICE;
688 drm_via_cmdbuf_size_t d_siz; 672 drm_via_cmdbuf_size_t d_siz;
@@ -691,7 +675,7 @@ via_cmdbuf_size(DRM_IOCTL_ARGS)
691 drm_via_private_t *dev_priv; 675 drm_via_private_t *dev_priv;
692 676
693 DRM_DEBUG("via cmdbuf_size\n"); 677 DRM_DEBUG("via cmdbuf_size\n");
694 LOCK_TEST_WITH_RETURN( dev, filp ); 678 LOCK_TEST_WITH_RETURN(dev, filp);
695 679
696 dev_priv = (drm_via_private_t *) dev->dev_private; 680 dev_priv = (drm_via_private_t *) dev->dev_private;
697 681
@@ -704,12 +688,12 @@ via_cmdbuf_size(DRM_IOCTL_ARGS)
704 DRM_COPY_FROM_USER_IOCTL(d_siz, (drm_via_cmdbuf_size_t __user *) data, 688 DRM_COPY_FROM_USER_IOCTL(d_siz, (drm_via_cmdbuf_size_t __user *) data,
705 sizeof(d_siz)); 689 sizeof(d_siz));
706 690
707
708 count = 1000000; 691 count = 1000000;
709 tmp_size = d_siz.size; 692 tmp_size = d_siz.size;
710 switch(d_siz.func) { 693 switch (d_siz.func) {
711 case VIA_CMDBUF_SPACE: 694 case VIA_CMDBUF_SPACE:
712 while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz.size) && count--) { 695 while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz.size)
696 && count--) {
713 if (!d_siz.wait) { 697 if (!d_siz.wait) {
714 break; 698 break;
715 } 699 }
@@ -720,7 +704,8 @@ via_cmdbuf_size(DRM_IOCTL_ARGS)
720 } 704 }
721 break; 705 break;
722 case VIA_CMDBUF_LAG: 706 case VIA_CMDBUF_LAG:
723 while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz.size) && count--) { 707 while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz.size)
708 && count--) {
724 if (!d_siz.wait) { 709 if (!d_siz.wait) {
725 break; 710 break;
726 } 711 }
diff --git a/drivers/char/drm/via_drm.h b/drivers/char/drm/via_drm.h
index be346bb0a26a..ebde9206115e 100644
--- a/drivers/char/drm/via_drm.h
+++ b/drivers/char/drm/via_drm.h
@@ -149,7 +149,7 @@ typedef struct _drm_via_dma_init {
149 enum { 149 enum {
150 VIA_INIT_DMA = 0x01, 150 VIA_INIT_DMA = 0x01,
151 VIA_CLEANUP_DMA = 0x02, 151 VIA_CLEANUP_DMA = 0x02,
152 VIA_DMA_INITIALIZED = 0x03 152 VIA_DMA_INITIALIZED = 0x03
153 } func; 153 } func;
154 154
155 unsigned long offset; 155 unsigned long offset;
@@ -212,7 +212,7 @@ typedef enum {
212 212
213#define VIA_IRQ_FLAGS_MASK 0xF0000000 213#define VIA_IRQ_FLAGS_MASK 0xF0000000
214 214
215struct drm_via_wait_irq_request{ 215struct drm_via_wait_irq_request {
216 unsigned irq; 216 unsigned irq;
217 via_irq_seq_type_t type; 217 via_irq_seq_type_t type;
218 uint32_t sequence; 218 uint32_t sequence;
diff --git a/drivers/char/drm/via_drv.c b/drivers/char/drm/via_drv.c
index 275eefc79221..016665e0c69f 100644
--- a/drivers/char/drm/via_drv.c
+++ b/drivers/char/drm/via_drv.c
@@ -93,18 +93,18 @@ static struct drm_driver driver = {
93 .ioctls = ioctls, 93 .ioctls = ioctls,
94 .num_ioctls = DRM_ARRAY_SIZE(ioctls), 94 .num_ioctls = DRM_ARRAY_SIZE(ioctls),
95 .fops = { 95 .fops = {
96 .owner = THIS_MODULE, 96 .owner = THIS_MODULE,
97 .open = drm_open, 97 .open = drm_open,
98 .release = drm_release, 98 .release = drm_release,
99 .ioctl = drm_ioctl, 99 .ioctl = drm_ioctl,
100 .mmap = drm_mmap, 100 .mmap = drm_mmap,
101 .poll = drm_poll, 101 .poll = drm_poll,
102 .fasync = drm_fasync, 102 .fasync = drm_fasync,
103 }, 103 },
104 .pci_driver = { 104 .pci_driver = {
105 .name = DRIVER_NAME, 105 .name = DRIVER_NAME,
106 .id_table = pciidlist, 106 .id_table = pciidlist,
107 } 107 }
108}; 108};
109 109
110static int __init via_init(void) 110static int __init via_init(void)
diff --git a/drivers/char/drm/via_drv.h b/drivers/char/drm/via_drv.h
index 4eaa8b7c4c96..d902dc2f4fae 100644
--- a/drivers/char/drm/via_drv.h
+++ b/drivers/char/drm/via_drv.h
@@ -40,8 +40,6 @@
40#define VIA_FIRE_BUF_SIZE 1024 40#define VIA_FIRE_BUF_SIZE 1024
41#define VIA_NUM_IRQS 2 41#define VIA_NUM_IRQS 2
42 42
43
44
45typedef struct drm_via_ring_buffer { 43typedef struct drm_via_ring_buffer {
46 drm_map_t map; 44 drm_map_t map;
47 char *virtual_start; 45 char *virtual_start;
@@ -55,7 +53,7 @@ typedef struct drm_via_irq {
55 uint32_t enable_mask; 53 uint32_t enable_mask;
56 wait_queue_head_t irq_queue; 54 wait_queue_head_t irq_queue;
57} drm_via_irq_t; 55} drm_via_irq_t;
58 56
59typedef struct drm_via_private { 57typedef struct drm_via_private {
60 drm_via_sarea_t *sarea_priv; 58 drm_via_sarea_t *sarea_priv;
61 drm_map_t *sarea; 59 drm_map_t *sarea;
@@ -71,9 +69,9 @@ typedef struct drm_via_private {
71 volatile uint32_t *last_pause_ptr; 69 volatile uint32_t *last_pause_ptr;
72 volatile uint32_t *hw_addr_ptr; 70 volatile uint32_t *hw_addr_ptr;
73 drm_via_ring_buffer_t ring; 71 drm_via_ring_buffer_t ring;
74 struct timeval last_vblank; 72 struct timeval last_vblank;
75 int last_vblank_valid; 73 int last_vblank_valid;
76 unsigned usec_per_vblank; 74 unsigned usec_per_vblank;
77 drm_via_state_t hc_state; 75 drm_via_state_t hc_state;
78 char pci_buf[VIA_PCI_BUF_SIZE]; 76 char pci_buf[VIA_PCI_BUF_SIZE];
79 const uint32_t *fire_offsets[VIA_FIRE_BUF_SIZE]; 77 const uint32_t *fire_offsets[VIA_FIRE_BUF_SIZE];
@@ -82,8 +80,8 @@ typedef struct drm_via_private {
82 drm_via_irq_t via_irqs[VIA_NUM_IRQS]; 80 drm_via_irq_t via_irqs[VIA_NUM_IRQS];
83 unsigned num_irqs; 81 unsigned num_irqs;
84 maskarray_t *irq_masks; 82 maskarray_t *irq_masks;
85 uint32_t irq_enable_mask; 83 uint32_t irq_enable_mask;
86 uint32_t irq_pending_mask; 84 uint32_t irq_pending_mask;
87} drm_via_private_t; 85} drm_via_private_t;
88 86
89/* VIA MMIO register access */ 87/* VIA MMIO register access */
@@ -110,9 +108,8 @@ extern void via_driver_irq_uninstall(drm_device_t * dev);
110extern int via_dma_cleanup(drm_device_t * dev); 108extern int via_dma_cleanup(drm_device_t * dev);
111extern void via_init_command_verifier(void); 109extern void via_init_command_verifier(void);
112extern int via_driver_dma_quiescent(drm_device_t * dev); 110extern int via_driver_dma_quiescent(drm_device_t * dev);
113extern void via_init_futex(drm_via_private_t *dev_priv); 111extern void via_init_futex(drm_via_private_t * dev_priv);
114extern void via_cleanup_futex(drm_via_private_t *dev_priv); 112extern void via_cleanup_futex(drm_via_private_t * dev_priv);
115extern void via_release_futex(drm_via_private_t *dev_priv, int context); 113extern void via_release_futex(drm_via_private_t * dev_priv, int context);
116
117 114
118#endif 115#endif
diff --git a/drivers/char/drm/via_irq.c b/drivers/char/drm/via_irq.c
index e8027f3a93b0..d023add1929b 100644
--- a/drivers/char/drm/via_irq.c
+++ b/drivers/char/drm/via_irq.c
@@ -54,23 +54,26 @@
54/* 54/*
55 * Device-specific IRQs go here. This type might need to be extended with 55 * Device-specific IRQs go here. This type might need to be extended with
56 * the register if there are multiple IRQ control registers. 56 * the register if there are multiple IRQ control registers.
57 * Currently we activate the HQV interrupts of Unichrome Pro group A. 57 * Currently we activate the HQV interrupts of Unichrome Pro group A.
58 */ 58 */
59 59
60static maskarray_t via_pro_group_a_irqs[] = { 60static maskarray_t via_pro_group_a_irqs[] = {
61 {VIA_IRQ_HQV0_ENABLE, VIA_IRQ_HQV0_PENDING, 0x000003D0, 0x00008010, 0x00000000 }, 61 {VIA_IRQ_HQV0_ENABLE, VIA_IRQ_HQV0_PENDING, 0x000003D0, 0x00008010,
62 {VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x000013D0, 0x00008010, 0x00000000 }}; 62 0x00000000},
63static int via_num_pro_group_a = sizeof(via_pro_group_a_irqs)/sizeof(maskarray_t); 63 {VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x000013D0, 0x00008010,
64 64 0x00000000}
65static maskarray_t via_unichrome_irqs[] = {}; 65};
66static int via_num_unichrome = sizeof(via_unichrome_irqs)/sizeof(maskarray_t); 66static int via_num_pro_group_a =
67 67 sizeof(via_pro_group_a_irqs) / sizeof(maskarray_t);
68 68
69static unsigned time_diff(struct timeval *now,struct timeval *then) 69static maskarray_t via_unichrome_irqs[] = { };
70static int via_num_unichrome = sizeof(via_unichrome_irqs) / sizeof(maskarray_t);
71
72static unsigned time_diff(struct timeval *now, struct timeval *then)
70{ 73{
71 return (now->tv_usec >= then->tv_usec) ? 74 return (now->tv_usec >= then->tv_usec) ?
72 now->tv_usec - then->tv_usec : 75 now->tv_usec - then->tv_usec :
73 1000000 - (then->tv_usec - now->tv_usec); 76 1000000 - (then->tv_usec - now->tv_usec);
74} 77}
75 78
76irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS) 79irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS)
@@ -86,38 +89,37 @@ irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS)
86 status = VIA_READ(VIA_REG_INTERRUPT); 89 status = VIA_READ(VIA_REG_INTERRUPT);
87 if (status & VIA_IRQ_VBLANK_PENDING) { 90 if (status & VIA_IRQ_VBLANK_PENDING) {
88 atomic_inc(&dev->vbl_received); 91 atomic_inc(&dev->vbl_received);
89 if (!(atomic_read(&dev->vbl_received) & 0x0F)) { 92 if (!(atomic_read(&dev->vbl_received) & 0x0F)) {
90 do_gettimeofday(&cur_vblank); 93 do_gettimeofday(&cur_vblank);
91 if (dev_priv->last_vblank_valid) { 94 if (dev_priv->last_vblank_valid) {
92 dev_priv->usec_per_vblank = 95 dev_priv->usec_per_vblank =
93 time_diff( &cur_vblank,&dev_priv->last_vblank) >> 4; 96 time_diff(&cur_vblank,
97 &dev_priv->last_vblank) >> 4;
94 } 98 }
95 dev_priv->last_vblank = cur_vblank; 99 dev_priv->last_vblank = cur_vblank;
96 dev_priv->last_vblank_valid = 1; 100 dev_priv->last_vblank_valid = 1;
97 } 101 }
98 if (!(atomic_read(&dev->vbl_received) & 0xFF)) { 102 if (!(atomic_read(&dev->vbl_received) & 0xFF)) {
99 DRM_DEBUG("US per vblank is: %u\n", 103 DRM_DEBUG("US per vblank is: %u\n",
100 dev_priv->usec_per_vblank); 104 dev_priv->usec_per_vblank);
101 } 105 }
102 DRM_WAKEUP(&dev->vbl_queue); 106 DRM_WAKEUP(&dev->vbl_queue);
103 drm_vbl_send_signals(dev); 107 drm_vbl_send_signals(dev);
104 handled = 1; 108 handled = 1;
105 } 109 }
106
107 110
108 for (i=0; i<dev_priv->num_irqs; ++i) { 111 for (i = 0; i < dev_priv->num_irqs; ++i) {
109 if (status & cur_irq->pending_mask) { 112 if (status & cur_irq->pending_mask) {
110 atomic_inc( &cur_irq->irq_received ); 113 atomic_inc(&cur_irq->irq_received);
111 DRM_WAKEUP( &cur_irq->irq_queue ); 114 DRM_WAKEUP(&cur_irq->irq_queue);
112 handled = 1; 115 handled = 1;
113 } 116 }
114 cur_irq++; 117 cur_irq++;
115 } 118 }
116 119
117 /* Acknowlege interrupts */ 120 /* Acknowlege interrupts */
118 VIA_WRITE(VIA_REG_INTERRUPT, status); 121 VIA_WRITE(VIA_REG_INTERRUPT, status);
119 122
120
121 if (handled) 123 if (handled)
122 return IRQ_HANDLED; 124 return IRQ_HANDLED;
123 else 125 else
@@ -131,7 +133,7 @@ static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t * dev_priv)
131 if (dev_priv) { 133 if (dev_priv) {
132 /* Acknowlege interrupts */ 134 /* Acknowlege interrupts */
133 status = VIA_READ(VIA_REG_INTERRUPT); 135 status = VIA_READ(VIA_REG_INTERRUPT);
134 VIA_WRITE(VIA_REG_INTERRUPT, status | 136 VIA_WRITE(VIA_REG_INTERRUPT, status |
135 dev_priv->irq_pending_mask); 137 dev_priv->irq_pending_mask);
136 } 138 }
137} 139}
@@ -158,12 +160,12 @@ int via_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence)
158 DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ, 160 DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
159 (((cur_vblank = atomic_read(&dev->vbl_received)) - 161 (((cur_vblank = atomic_read(&dev->vbl_received)) -
160 *sequence) <= (1 << 23))); 162 *sequence) <= (1 << 23)));
161 163
162 *sequence = cur_vblank; 164 *sequence = cur_vblank;
163 return ret; 165 return ret;
164} 166}
165 167
166static int 168static int
167via_driver_irq_wait(drm_device_t * dev, unsigned int irq, int force_sequence, 169via_driver_irq_wait(drm_device_t * dev, unsigned int irq, int force_sequence,
168 unsigned int *sequence) 170 unsigned int *sequence)
169{ 171{
@@ -180,27 +182,29 @@ via_driver_irq_wait(drm_device_t * dev, unsigned int irq, int force_sequence,
180 return DRM_ERR(EINVAL); 182 return DRM_ERR(EINVAL);
181 } 183 }
182 184
183 if (irq >= dev_priv->num_irqs ) { 185 if (irq >= dev_priv->num_irqs) {
184 DRM_ERROR("%s Trying to wait on unknown irq %d\n", __FUNCTION__, irq); 186 DRM_ERROR("%s Trying to wait on unknown irq %d\n", __FUNCTION__,
187 irq);
185 return DRM_ERR(EINVAL); 188 return DRM_ERR(EINVAL);
186 } 189 }
187 190
188 cur_irq += irq; 191 cur_irq += irq;
189 192
190 if (masks[irq][2] && !force_sequence) { 193 if (masks[irq][2] && !force_sequence) {
191 DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ, 194 DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,
192 ((VIA_READ(masks[irq][2]) & masks[irq][3]) == masks[irq][4])); 195 ((VIA_READ(masks[irq][2]) & masks[irq][3]) ==
196 masks[irq][4]));
193 cur_irq_sequence = atomic_read(&cur_irq->irq_received); 197 cur_irq_sequence = atomic_read(&cur_irq->irq_received);
194 } else { 198 } else {
195 DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ, 199 DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,
196 (((cur_irq_sequence = atomic_read(&cur_irq->irq_received)) - 200 (((cur_irq_sequence =
197 *sequence) <= (1 << 23))); 201 atomic_read(&cur_irq->irq_received)) -
202 *sequence) <= (1 << 23)));
198 } 203 }
199 *sequence = cur_irq_sequence; 204 *sequence = cur_irq_sequence;
200 return ret; 205 return ret;
201} 206}
202 207
203
204/* 208/*
205 * drm_dma.h hooks 209 * drm_dma.h hooks
206 */ 210 */
@@ -219,29 +223,29 @@ void via_driver_irq_preinstall(drm_device_t * dev)
219 dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING; 223 dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING;
220 224
221 dev_priv->irq_masks = (dev_priv->pro_group_a) ? 225 dev_priv->irq_masks = (dev_priv->pro_group_a) ?
222 via_pro_group_a_irqs : via_unichrome_irqs; 226 via_pro_group_a_irqs : via_unichrome_irqs;
223 dev_priv->num_irqs = (dev_priv->pro_group_a) ? 227 dev_priv->num_irqs = (dev_priv->pro_group_a) ?
224 via_num_pro_group_a : via_num_unichrome; 228 via_num_pro_group_a : via_num_unichrome;
225 229
226 for(i=0; i < dev_priv->num_irqs; ++i) { 230 for (i = 0; i < dev_priv->num_irqs; ++i) {
227 atomic_set(&cur_irq->irq_received, 0); 231 atomic_set(&cur_irq->irq_received, 0);
228 cur_irq->enable_mask = dev_priv->irq_masks[i][0]; 232 cur_irq->enable_mask = dev_priv->irq_masks[i][0];
229 cur_irq->pending_mask = dev_priv->irq_masks[i][1]; 233 cur_irq->pending_mask = dev_priv->irq_masks[i][1];
230 DRM_INIT_WAITQUEUE( &cur_irq->irq_queue ); 234 DRM_INIT_WAITQUEUE(&cur_irq->irq_queue);
231 dev_priv->irq_enable_mask |= cur_irq->enable_mask; 235 dev_priv->irq_enable_mask |= cur_irq->enable_mask;
232 dev_priv->irq_pending_mask |= cur_irq->pending_mask; 236 dev_priv->irq_pending_mask |= cur_irq->pending_mask;
233 cur_irq++; 237 cur_irq++;
234 238
235 DRM_DEBUG("Initializing IRQ %d\n", i); 239 DRM_DEBUG("Initializing IRQ %d\n", i);
236 } 240 }
237 241
238 dev_priv->last_vblank_valid = 0; 242 dev_priv->last_vblank_valid = 0;
239 243
240 // Clear VSync interrupt regs 244 // Clear VSync interrupt regs
241 status = VIA_READ(VIA_REG_INTERRUPT); 245 status = VIA_READ(VIA_REG_INTERRUPT);
242 VIA_WRITE(VIA_REG_INTERRUPT, status & 246 VIA_WRITE(VIA_REG_INTERRUPT, status &
243 ~(dev_priv->irq_enable_mask)); 247 ~(dev_priv->irq_enable_mask));
244 248
245 /* Clear bits if they're already high */ 249 /* Clear bits if they're already high */
246 viadrv_acknowledge_irqs(dev_priv); 250 viadrv_acknowledge_irqs(dev_priv);
247 } 251 }
@@ -262,7 +266,7 @@ void via_driver_irq_postinstall(drm_device_t * dev)
262 266
263 VIA_WRITE8(0x83d4, 0x11); 267 VIA_WRITE8(0x83d4, 0x11);
264 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30); 268 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
265 269
266 } 270 }
267} 271}
268 272
@@ -280,7 +284,7 @@ void via_driver_irq_uninstall(drm_device_t * dev)
280 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30); 284 VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
281 285
282 status = VIA_READ(VIA_REG_INTERRUPT); 286 status = VIA_READ(VIA_REG_INTERRUPT);
283 VIA_WRITE(VIA_REG_INTERRUPT, status & 287 VIA_WRITE(VIA_REG_INTERRUPT, status &
284 ~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask)); 288 ~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask));
285 } 289 }
286} 290}
@@ -302,7 +306,7 @@ int via_wait_irq(DRM_IOCTL_ARGS)
302 306
303 DRM_COPY_FROM_USER_IOCTL(irqwait, argp, sizeof(irqwait)); 307 DRM_COPY_FROM_USER_IOCTL(irqwait, argp, sizeof(irqwait));
304 if (irqwait.request.irq >= dev_priv->num_irqs) { 308 if (irqwait.request.irq >= dev_priv->num_irqs) {
305 DRM_ERROR("%s Trying to wait on unknown irq %d\n", __FUNCTION__, 309 DRM_ERROR("%s Trying to wait on unknown irq %d\n", __FUNCTION__,
306 irqwait.request.irq); 310 irqwait.request.irq);
307 return DRM_ERR(EINVAL); 311 return DRM_ERR(EINVAL);
308 } 312 }
@@ -320,7 +324,7 @@ int via_wait_irq(DRM_IOCTL_ARGS)
320 } 324 }
321 325
322 if (irqwait.request.type & VIA_IRQ_SIGNAL) { 326 if (irqwait.request.type & VIA_IRQ_SIGNAL) {
323 DRM_ERROR("%s Signals on Via IRQs not implemented yet.\n", 327 DRM_ERROR("%s Signals on Via IRQs not implemented yet.\n",
324 __FUNCTION__); 328 __FUNCTION__);
325 return DRM_ERR(EINVAL); 329 return DRM_ERR(EINVAL);
326 } 330 }
diff --git a/drivers/char/drm/via_map.c b/drivers/char/drm/via_map.c
index bb171139e737..6bd6ac52ad1b 100644
--- a/drivers/char/drm/via_map.c
+++ b/drivers/char/drm/via_map.c
@@ -66,7 +66,7 @@ static int via_do_init_map(drm_device_t * dev, drm_via_init_t * init)
66 66
67 dev_priv->agpAddr = init->agpAddr; 67 dev_priv->agpAddr = init->agpAddr;
68 68
69 via_init_futex( dev_priv ); 69 via_init_futex(dev_priv);
70 dev_priv->pro_group_a = (dev->pdev->device == 0x3118); 70 dev_priv->pro_group_a = (dev->pdev->device == 0x3118);
71 71
72 dev->dev_private = (void *)dev_priv; 72 dev->dev_private = (void *)dev_priv;
@@ -107,5 +107,3 @@ int via_map_init(DRM_IOCTL_ARGS)
107 107
108 return -EINVAL; 108 return -EINVAL;
109} 109}
110
111
diff --git a/drivers/char/drm/via_mm.c b/drivers/char/drm/via_mm.c
index 13921f3c0ec2..3baddacdff26 100644
--- a/drivers/char/drm/via_mm.c
+++ b/drivers/char/drm/via_mm.c
@@ -81,7 +81,8 @@ int via_agp_init(DRM_IOCTL_ARGS)
81 81
82 AgpHeap = via_mmInit(agp.offset, agp.size); 82 AgpHeap = via_mmInit(agp.offset, agp.size);
83 83
84 DRM_DEBUG("offset = %lu, size = %lu", (unsigned long)agp.offset, (unsigned long)agp.size); 84 DRM_DEBUG("offset = %lu, size = %lu", (unsigned long)agp.offset,
85 (unsigned long)agp.size);
85 86
86 return 0; 87 return 0;
87} 88}
@@ -97,7 +98,8 @@ int via_fb_init(DRM_IOCTL_ARGS)
97 98
98 FBHeap = via_mmInit(fb.offset, fb.size); 99 FBHeap = via_mmInit(fb.offset, fb.size);
99 100
100 DRM_DEBUG("offset = %lu, size = %lu", (unsigned long)fb.offset, (unsigned long)fb.size); 101 DRM_DEBUG("offset = %lu, size = %lu", (unsigned long)fb.offset,
102 (unsigned long)fb.size);
101 103
102 return 0; 104 return 0;
103} 105}
@@ -134,8 +136,8 @@ int via_init_context(struct drm_device *dev, int context)
134} 136}
135 137
136int via_final_context(struct drm_device *dev, int context) 138int via_final_context(struct drm_device *dev, int context)
137{ 139{
138 int i; 140 int i;
139 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; 141 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
140 142
141 for (i = 0; i < MAX_CONTEXT; i++) 143 for (i = 0; i < MAX_CONTEXT; i++)
@@ -171,14 +173,13 @@ int via_final_context(struct drm_device *dev, int context)
171 via_setDestroy(set); 173 via_setDestroy(set);
172 global_ppriv[i].used = 0; 174 global_ppriv[i].used = 0;
173 } 175 }
174 via_release_futex(dev_priv, context); 176 via_release_futex(dev_priv, context);
175 177
176
177#if defined(__linux__) 178#if defined(__linux__)
178 /* Linux specific until context tracking code gets ported to BSD */ 179 /* Linux specific until context tracking code gets ported to BSD */
179 /* Last context, perform cleanup */ 180 /* Last context, perform cleanup */
180 if (dev->ctx_count == 1 && dev->dev_private) { 181 if (dev->ctx_count == 1 && dev->dev_private) {
181 DRM_DEBUG("Last Context\n"); 182 DRM_DEBUG("Last Context\n");
182 if (dev->irq) 183 if (dev->irq)
183 drm_irq_uninstall(dev); 184 drm_irq_uninstall(dev);
184 185
diff --git a/drivers/char/drm/via_verifier.c b/drivers/char/drm/via_verifier.c
index 07923b0c7a97..4ac495f297f7 100644
--- a/drivers/char/drm/via_verifier.c
+++ b/drivers/char/drm/via_verifier.c
@@ -28,7 +28,6 @@
28 * be very slow. 28 * be very slow.
29 */ 29 */
30 30
31
32#include "via_3d_reg.h" 31#include "via_3d_reg.h"
33#include "drmP.h" 32#include "drmP.h"
34#include "drm.h" 33#include "drm.h"
@@ -36,7 +35,7 @@
36#include "via_verifier.h" 35#include "via_verifier.h"
37#include "via_drv.h" 36#include "via_drv.h"
38 37
39typedef enum{ 38typedef enum {
40 state_command, 39 state_command,
41 state_header2, 40 state_header2,
42 state_header1, 41 state_header1,
@@ -45,8 +44,7 @@ typedef enum{
45 state_error 44 state_error
46} verifier_state_t; 45} verifier_state_t;
47 46
48 47typedef enum {
49typedef enum{
50 no_check = 0, 48 no_check = 0,
51 check_for_header2, 49 check_for_header2,
52 check_for_header1, 50 check_for_header1,
@@ -74,16 +72,16 @@ typedef enum{
74 check_for_vertex_count, 72 check_for_vertex_count,
75 check_number_texunits, 73 check_number_texunits,
76 forbidden_command 74 forbidden_command
77}hazard_t; 75} hazard_t;
78 76
79/* 77/*
80 * Associates each hazard above with a possible multi-command 78 * Associates each hazard above with a possible multi-command
81 * sequence. For example an address that is split over multiple 79 * sequence. For example an address that is split over multiple
82 * commands and that needs to be checked at the first command 80 * commands and that needs to be checked at the first command
83 * that does not include any part of the address. 81 * that does not include any part of the address.
84 */ 82 */
85 83
86static drm_via_sequence_t seqs[] = { 84static drm_via_sequence_t seqs[] = {
87 no_sequence, 85 no_sequence,
88 no_sequence, 86 no_sequence,
89 no_sequence, 87 no_sequence,
@@ -110,14 +108,12 @@ static drm_via_sequence_t seqs[] = {
110 tex_address, 108 tex_address,
111 no_sequence 109 no_sequence
112}; 110};
113 111
114typedef struct{ 112typedef struct {
115 unsigned int code; 113 unsigned int code;
116 hazard_t hz; 114 hazard_t hz;
117} hz_init_t; 115} hz_init_t;
118 116
119
120
121static hz_init_t init_table1[] = { 117static hz_init_t init_table1[] = {
122 {0xf2, check_for_header2_err}, 118 {0xf2, check_for_header2_err},
123 {0xf0, check_for_header1_err}, 119 {0xf0, check_for_header1_err},
@@ -169,8 +165,6 @@ static hz_init_t init_table1[] = {
169 {0x7D, check_for_vertex_count} 165 {0x7D, check_for_vertex_count}
170}; 166};
171 167
172
173
174static hz_init_t init_table2[] = { 168static hz_init_t init_table2[] = {
175 {0xf2, check_for_header2_err}, 169 {0xf2, check_for_header2_err},
176 {0xf0, check_for_header1_err}, 170 {0xf0, check_for_header1_err},
@@ -235,49 +229,49 @@ static hz_init_t init_table3[] = {
235 {0xcc, check_for_dummy}, 229 {0xcc, check_for_dummy},
236 {0x00, check_number_texunits} 230 {0x00, check_number_texunits}
237}; 231};
238
239
240static hazard_t table1[256];
241static hazard_t table2[256];
242static hazard_t table3[256];
243
244 232
233static hazard_t table1[256];
234static hazard_t table2[256];
235static hazard_t table3[256];
245 236
246static __inline__ int 237static __inline__ int
247eat_words(const uint32_t **buf, const uint32_t *buf_end, unsigned num_words) 238eat_words(const uint32_t ** buf, const uint32_t * buf_end, unsigned num_words)
248{ 239{
249 if ((*buf - buf_end) >= num_words) { 240 if ((*buf - buf_end) >= num_words) {
250 *buf += num_words; 241 *buf += num_words;
251 return 0; 242 return 0;
252 } 243 }
253 DRM_ERROR("Illegal termination of DMA command buffer\n"); 244 DRM_ERROR("Illegal termination of DMA command buffer\n");
254 return 1; 245 return 1;
255} 246}
256 247
257
258/* 248/*
259 * Partially stolen from drm_memory.h 249 * Partially stolen from drm_memory.h
260 */ 250 */
261 251
262static __inline__ drm_map_t * 252static __inline__ drm_map_t *via_drm_lookup_agp_map(drm_via_state_t * seq,
263via_drm_lookup_agp_map (drm_via_state_t *seq, unsigned long offset, unsigned long size, 253 unsigned long offset,
264 drm_device_t *dev) 254 unsigned long size,
255 drm_device_t * dev)
265{ 256{
266 struct list_head *list; 257 struct list_head *list;
267 drm_map_list_t *r_list; 258 drm_map_list_t *r_list;
268 drm_map_t *map = seq->map_cache; 259 drm_map_t *map = seq->map_cache;
269 260
270 if (map && map->offset <= offset && (offset + size) <= (map->offset + map->size)) { 261 if (map && map->offset <= offset
262 && (offset + size) <= (map->offset + map->size)) {
271 return map; 263 return map;
272 } 264 }
273 265
274 list_for_each(list, &dev->maplist->head) { 266 list_for_each(list, &dev->maplist->head) {
275 r_list = (drm_map_list_t *) list; 267 r_list = (drm_map_list_t *) list;
276 map = r_list->map; 268 map = r_list->map;
277 if (!map) 269 if (!map)
278 continue; 270 continue;
279 if (map->offset <= offset && (offset + size) <= (map->offset + map->size) && 271 if (map->offset <= offset
280 !(map->flags & _DRM_RESTRICTED) && (map->type == _DRM_AGP)) { 272 && (offset + size) <= (map->offset + map->size)
273 && !(map->flags & _DRM_RESTRICTED)
274 && (map->type == _DRM_AGP)) {
281 seq->map_cache = map; 275 seq->map_cache = map;
282 return map; 276 return map;
283 } 277 }
@@ -285,54 +279,60 @@ via_drm_lookup_agp_map (drm_via_state_t *seq, unsigned long offset, unsigned lon
285 return NULL; 279 return NULL;
286} 280}
287 281
288
289/* 282/*
290 * Require that all AGP texture levels reside in the same AGP map which should 283 * Require that all AGP texture levels reside in the same AGP map which should
291 * be mappable by the client. This is not a big restriction. 284 * be mappable by the client. This is not a big restriction.
292 * FIXME: To actually enforce this security policy strictly, drm_rmmap 285 * FIXME: To actually enforce this security policy strictly, drm_rmmap
293 * would have to wait for dma quiescent before removing an AGP map. 286 * would have to wait for dma quiescent before removing an AGP map.
294 * The via_drm_lookup_agp_map call in reality seems to take 287 * The via_drm_lookup_agp_map call in reality seems to take
295 * very little CPU time. 288 * very little CPU time.
296 */ 289 */
297 290
298 291static __inline__ int finish_current_sequence(drm_via_state_t * cur_seq)
299static __inline__ int
300finish_current_sequence(drm_via_state_t *cur_seq)
301{ 292{
302 switch(cur_seq->unfinished) { 293 switch (cur_seq->unfinished) {
303 case z_address: 294 case z_address:
304 DRM_DEBUG("Z Buffer start address is 0x%x\n", cur_seq->z_addr); 295 DRM_DEBUG("Z Buffer start address is 0x%x\n", cur_seq->z_addr);
305 break; 296 break;
306 case dest_address: 297 case dest_address:
307 DRM_DEBUG("Destination start address is 0x%x\n", cur_seq->d_addr); 298 DRM_DEBUG("Destination start address is 0x%x\n",
299 cur_seq->d_addr);
308 break; 300 break;
309 case tex_address: 301 case tex_address:
310 if (cur_seq->agp_texture) { 302 if (cur_seq->agp_texture) {
311 unsigned start = cur_seq->tex_level_lo[cur_seq->texture]; 303 unsigned start =
304 cur_seq->tex_level_lo[cur_seq->texture];
312 unsigned end = cur_seq->tex_level_hi[cur_seq->texture]; 305 unsigned end = cur_seq->tex_level_hi[cur_seq->texture];
313 unsigned long lo=~0, hi=0, tmp; 306 unsigned long lo = ~0, hi = 0, tmp;
314 uint32_t *addr, *pitch, *height, tex; 307 uint32_t *addr, *pitch, *height, tex;
315 unsigned i; 308 unsigned i;
316 309
317 if (end > 9) end = 9; 310 if (end > 9)
318 if (start > 9) start = 9; 311 end = 9;
312 if (start > 9)
313 start = 9;
319 314
320 addr =&(cur_seq->t_addr[tex = cur_seq->texture][start]); 315 addr =
316 &(cur_seq->t_addr[tex = cur_seq->texture][start]);
321 pitch = &(cur_seq->pitch[tex][start]); 317 pitch = &(cur_seq->pitch[tex][start]);
322 height = &(cur_seq->height[tex][start]); 318 height = &(cur_seq->height[tex][start]);
323 319
324 for (i=start; i<= end; ++i) { 320 for (i = start; i <= end; ++i) {
325 tmp = *addr++; 321 tmp = *addr++;
326 if (tmp < lo) lo = tmp; 322 if (tmp < lo)
323 lo = tmp;
327 tmp += (*height++ << *pitch++); 324 tmp += (*height++ << *pitch++);
328 if (tmp > hi) hi = tmp; 325 if (tmp > hi)
326 hi = tmp;
329 } 327 }
330 328
331 if (! via_drm_lookup_agp_map (cur_seq, lo, hi - lo, cur_seq->dev)) { 329 if (!via_drm_lookup_agp_map
332 DRM_ERROR("AGP texture is not in allowed map\n"); 330 (cur_seq, lo, hi - lo, cur_seq->dev)) {
331 DRM_ERROR
332 ("AGP texture is not in allowed map\n");
333 return 2; 333 return 2;
334 } 334 }
335 } 335 }
336 break; 336 break;
337 default: 337 default:
338 break; 338 break;
@@ -341,73 +341,84 @@ finish_current_sequence(drm_via_state_t *cur_seq)
341 return 0; 341 return 0;
342} 342}
343 343
344static __inline__ int 344static __inline__ int
345investigate_hazard( uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq) 345investigate_hazard(uint32_t cmd, hazard_t hz, drm_via_state_t * cur_seq)
346{ 346{
347 register uint32_t tmp, *tmp_addr; 347 register uint32_t tmp, *tmp_addr;
348 348
349 if (cur_seq->unfinished && (cur_seq->unfinished != seqs[hz])) { 349 if (cur_seq->unfinished && (cur_seq->unfinished != seqs[hz])) {
350 int ret; 350 int ret;
351 if ((ret = finish_current_sequence(cur_seq))) return ret; 351 if ((ret = finish_current_sequence(cur_seq)))
352 return ret;
352 } 353 }
353 354
354 switch(hz) { 355 switch (hz) {
355 case check_for_header2: 356 case check_for_header2:
356 if (cmd == HALCYON_HEADER2) return 1; 357 if (cmd == HALCYON_HEADER2)
358 return 1;
357 return 0; 359 return 0;
358 case check_for_header1: 360 case check_for_header1:
359 if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) return 1; 361 if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
362 return 1;
360 return 0; 363 return 0;
361 case check_for_header2_err: 364 case check_for_header2_err:
362 if (cmd == HALCYON_HEADER2) return 1; 365 if (cmd == HALCYON_HEADER2)
366 return 1;
363 DRM_ERROR("Illegal DMA HALCYON_HEADER2 command\n"); 367 DRM_ERROR("Illegal DMA HALCYON_HEADER2 command\n");
364 break; 368 break;
365 case check_for_header1_err: 369 case check_for_header1_err:
366 if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) return 1; 370 if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
371 return 1;
367 DRM_ERROR("Illegal DMA HALCYON_HEADER1 command\n"); 372 DRM_ERROR("Illegal DMA HALCYON_HEADER1 command\n");
368 break; 373 break;
369 case check_for_fire: 374 case check_for_fire:
370 if ((cmd & HALCYON_FIREMASK) == HALCYON_FIRECMD) return 1; 375 if ((cmd & HALCYON_FIREMASK) == HALCYON_FIRECMD)
376 return 1;
371 DRM_ERROR("Illegal DMA HALCYON_FIRECMD command\n"); 377 DRM_ERROR("Illegal DMA HALCYON_FIRECMD command\n");
372 break; 378 break;
373 case check_for_dummy: 379 case check_for_dummy:
374 if (HC_DUMMY == cmd) return 0; 380 if (HC_DUMMY == cmd)
381 return 0;
375 DRM_ERROR("Illegal DMA HC_DUMMY command\n"); 382 DRM_ERROR("Illegal DMA HC_DUMMY command\n");
376 break; 383 break;
377 case check_for_dd: 384 case check_for_dd:
378 if (0xdddddddd == cmd) return 0; 385 if (0xdddddddd == cmd)
386 return 0;
379 DRM_ERROR("Illegal DMA 0xdddddddd command\n"); 387 DRM_ERROR("Illegal DMA 0xdddddddd command\n");
380 break; 388 break;
381 case check_z_buffer_addr0: 389 case check_z_buffer_addr0:
382 cur_seq->unfinished = z_address; 390 cur_seq->unfinished = z_address;
383 cur_seq->z_addr = (cur_seq->z_addr & 0xFF000000) | 391 cur_seq->z_addr = (cur_seq->z_addr & 0xFF000000) |
384 (cmd & 0x00FFFFFF); 392 (cmd & 0x00FFFFFF);
385 return 0; 393 return 0;
386 case check_z_buffer_addr1: 394 case check_z_buffer_addr1:
387 cur_seq->unfinished = z_address; 395 cur_seq->unfinished = z_address;
388 cur_seq->z_addr = (cur_seq->z_addr & 0x00FFFFFF) | 396 cur_seq->z_addr = (cur_seq->z_addr & 0x00FFFFFF) |
389 ((cmd & 0xFF) << 24); 397 ((cmd & 0xFF) << 24);
390 return 0; 398 return 0;
391 case check_z_buffer_addr_mode: 399 case check_z_buffer_addr_mode:
392 cur_seq->unfinished = z_address; 400 cur_seq->unfinished = z_address;
393 if ((cmd & 0x0000C000) == 0) return 0; 401 if ((cmd & 0x0000C000) == 0)
402 return 0;
394 DRM_ERROR("Attempt to place Z buffer in system memory\n"); 403 DRM_ERROR("Attempt to place Z buffer in system memory\n");
395 return 2; 404 return 2;
396 case check_destination_addr0: 405 case check_destination_addr0:
397 cur_seq->unfinished = dest_address; 406 cur_seq->unfinished = dest_address;
398 cur_seq->d_addr = (cur_seq->d_addr & 0xFF000000) | 407 cur_seq->d_addr = (cur_seq->d_addr & 0xFF000000) |
399 (cmd & 0x00FFFFFF); 408 (cmd & 0x00FFFFFF);
400 return 0; 409 return 0;
401 case check_destination_addr1: 410 case check_destination_addr1:
402 cur_seq->unfinished = dest_address; 411 cur_seq->unfinished = dest_address;
403 cur_seq->d_addr = (cur_seq->d_addr & 0x00FFFFFF) | 412 cur_seq->d_addr = (cur_seq->d_addr & 0x00FFFFFF) |
404 ((cmd & 0xFF) << 24); 413 ((cmd & 0xFF) << 24);
405 return 0; 414 return 0;
406 case check_destination_addr_mode: 415 case check_destination_addr_mode:
407 cur_seq->unfinished = dest_address; 416 cur_seq->unfinished = dest_address;
408 if ((cmd & 0x0000C000) == 0) return 0; 417 if ((cmd & 0x0000C000) == 0)
409 DRM_ERROR("Attempt to place 3D drawing buffer in system memory\n"); 418 return 0;
410 return 2; 419 DRM_ERROR
420 ("Attempt to place 3D drawing buffer in system memory\n");
421 return 2;
411 case check_texture_addr0: 422 case check_texture_addr0:
412 cur_seq->unfinished = tex_address; 423 cur_seq->unfinished = tex_address;
413 tmp = (cmd >> 24); 424 tmp = (cmd >> 24);
@@ -433,9 +444,11 @@ investigate_hazard( uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq)
433 case check_texture_addr3: 444 case check_texture_addr3:
434 cur_seq->unfinished = tex_address; 445 cur_seq->unfinished = tex_address;
435 tmp = ((cmd >> 24) - 0x2B); 446 tmp = ((cmd >> 24) - 0x2B);
436 cur_seq->pitch[cur_seq->texture][tmp] = (cmd & 0x00F00000) >> 20; 447 cur_seq->pitch[cur_seq->texture][tmp] =
448 (cmd & 0x00F00000) >> 20;
437 if (!tmp && (cmd & 0x000FFFFF)) { 449 if (!tmp && (cmd & 0x000FFFFF)) {
438 DRM_ERROR("Unimplemented texture level 0 pitch mode.\n"); 450 DRM_ERROR
451 ("Unimplemented texture level 0 pitch mode.\n");
439 return 2; 452 return 2;
440 } 453 }
441 return 0; 454 return 0;
@@ -449,7 +462,7 @@ investigate_hazard( uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq)
449 cur_seq->unfinished = tex_address; 462 cur_seq->unfinished = tex_address;
450 /* 463 /*
451 * Texture width. We don't care since we have the pitch. 464 * Texture width. We don't care since we have the pitch.
452 */ 465 */
453 return 0; 466 return 0;
454 case check_texture_addr7: 467 case check_texture_addr7:
455 cur_seq->unfinished = tex_address; 468 cur_seq->unfinished = tex_address;
@@ -465,25 +478,26 @@ investigate_hazard( uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq)
465 cur_seq->unfinished = tex_address; 478 cur_seq->unfinished = tex_address;
466 tmp_addr = &(cur_seq->height[cur_seq->texture][0]); 479 tmp_addr = &(cur_seq->height[cur_seq->texture][0]);
467 tmp_addr[9] = 1 << ((cmd & 0x0000F000) >> 12); 480 tmp_addr[9] = 1 << ((cmd & 0x0000F000) >> 12);
468 tmp_addr[8] = 1 << ((cmd & 0x00000F00) >> 8); 481 tmp_addr[8] = 1 << ((cmd & 0x00000F00) >> 8);
469 tmp_addr[7] = 1 << ((cmd & 0x000000F0) >> 4); 482 tmp_addr[7] = 1 << ((cmd & 0x000000F0) >> 4);
470 tmp_addr[6] = 1 << (cmd & 0x0000000F); 483 tmp_addr[6] = 1 << (cmd & 0x0000000F);
471 return 0; 484 return 0;
472 case check_texture_addr_mode: 485 case check_texture_addr_mode:
473 cur_seq->unfinished = tex_address; 486 cur_seq->unfinished = tex_address;
474 if ( 2 == (tmp = cmd & 0x00000003)) { 487 if (2 == (tmp = cmd & 0x00000003)) {
475 DRM_ERROR("Attempt to fetch texture from system memory.\n"); 488 DRM_ERROR
489 ("Attempt to fetch texture from system memory.\n");
476 return 2; 490 return 2;
477 } 491 }
478 cur_seq->agp_texture = (tmp == 3); 492 cur_seq->agp_texture = (tmp == 3);
479 cur_seq->tex_palette_size[cur_seq->texture] = 493 cur_seq->tex_palette_size[cur_seq->texture] =
480 (cmd >> 16) & 0x000000007; 494 (cmd >> 16) & 0x000000007;
481 return 0; 495 return 0;
482 case check_for_vertex_count: 496 case check_for_vertex_count:
483 cur_seq->vertex_count = cmd & 0x0000FFFF; 497 cur_seq->vertex_count = cmd & 0x0000FFFF;
484 return 0; 498 return 0;
485 case check_number_texunits: 499 case check_number_texunits:
486 cur_seq->multitex = (cmd >> 3) & 1; 500 cur_seq->multitex = (cmd >> 3) & 1;
487 return 0; 501 return 0;
488 default: 502 default:
489 DRM_ERROR("Illegal DMA data: 0x%x\n", cmd); 503 DRM_ERROR("Illegal DMA data: 0x%x\n", cmd);
@@ -492,25 +506,27 @@ investigate_hazard( uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq)
492 return 2; 506 return 2;
493} 507}
494 508
495
496static __inline__ int 509static __inline__ int
497via_check_prim_list(uint32_t const **buffer, const uint32_t *buf_end, 510via_check_prim_list(uint32_t const **buffer, const uint32_t * buf_end,
498 drm_via_state_t *cur_seq) 511 drm_via_state_t * cur_seq)
499{ 512{
500 drm_via_private_t *dev_priv = (drm_via_private_t *) cur_seq->dev->dev_private; 513 drm_via_private_t *dev_priv =
501 uint32_t a_fire, bcmd , dw_count; 514 (drm_via_private_t *) cur_seq->dev->dev_private;
515 uint32_t a_fire, bcmd, dw_count;
502 int ret = 0; 516 int ret = 0;
503 int have_fire; 517 int have_fire;
504 const uint32_t *buf = *buffer; 518 const uint32_t *buf = *buffer;
505 519
506 while(buf < buf_end) { 520 while (buf < buf_end) {
507 have_fire = 0; 521 have_fire = 0;
508 if ((buf_end - buf) < 2) { 522 if ((buf_end - buf) < 2) {
509 DRM_ERROR("Unexpected termination of primitive list.\n"); 523 DRM_ERROR
524 ("Unexpected termination of primitive list.\n");
510 ret = 1; 525 ret = 1;
511 break; 526 break;
512 } 527 }
513 if ((*buf & HC_ACMD_MASK) != HC_ACMD_HCmdB) break; 528 if ((*buf & HC_ACMD_MASK) != HC_ACMD_HCmdB)
529 break;
514 bcmd = *buf++; 530 bcmd = *buf++;
515 if ((*buf & HC_ACMD_MASK) != HC_ACMD_HCmdA) { 531 if ((*buf & HC_ACMD_MASK) != HC_ACMD_HCmdA) {
516 DRM_ERROR("Expected Vertex List A command, got 0x%x\n", 532 DRM_ERROR("Expected Vertex List A command, got 0x%x\n",
@@ -518,43 +534,56 @@ via_check_prim_list(uint32_t const **buffer, const uint32_t *buf_end,
518 ret = 1; 534 ret = 1;
519 break; 535 break;
520 } 536 }
521 a_fire = *buf++ | HC_HPLEND_MASK | HC_HPMValidN_MASK | HC_HE3Fire_MASK; 537 a_fire =
522 538 *buf++ | HC_HPLEND_MASK | HC_HPMValidN_MASK |
539 HC_HE3Fire_MASK;
540
523 /* 541 /*
524 * How many dwords per vertex ? 542 * How many dwords per vertex ?
525 */ 543 */
526 544
527 if (cur_seq->agp && ((bcmd & (0xF << 11)) == 0)) { 545 if (cur_seq->agp && ((bcmd & (0xF << 11)) == 0)) {
528 DRM_ERROR("Illegal B command vertex data for AGP.\n"); 546 DRM_ERROR("Illegal B command vertex data for AGP.\n");
529 ret = 1; 547 ret = 1;
530 break; 548 break;
531 } 549 }
532 550
533 dw_count = 0; 551 dw_count = 0;
534 if (bcmd & (1 << 7)) dw_count += (cur_seq->multitex) ? 2:1; 552 if (bcmd & (1 << 7))
535 if (bcmd & (1 << 8)) dw_count += (cur_seq->multitex) ? 2:1; 553 dw_count += (cur_seq->multitex) ? 2 : 1;
536 if (bcmd & (1 << 9)) dw_count++; 554 if (bcmd & (1 << 8))
537 if (bcmd & (1 << 10)) dw_count++; 555 dw_count += (cur_seq->multitex) ? 2 : 1;
538 if (bcmd & (1 << 11)) dw_count++; 556 if (bcmd & (1 << 9))
539 if (bcmd & (1 << 12)) dw_count++; 557 dw_count++;
540 if (bcmd & (1 << 13)) dw_count++; 558 if (bcmd & (1 << 10))
541 if (bcmd & (1 << 14)) dw_count++; 559 dw_count++;
542 560 if (bcmd & (1 << 11))
543 while(buf < buf_end) { 561 dw_count++;
562 if (bcmd & (1 << 12))
563 dw_count++;
564 if (bcmd & (1 << 13))
565 dw_count++;
566 if (bcmd & (1 << 14))
567 dw_count++;
568
569 while (buf < buf_end) {
544 if (*buf == a_fire) { 570 if (*buf == a_fire) {
545 if (dev_priv->num_fire_offsets >= VIA_FIRE_BUF_SIZE) { 571 if (dev_priv->num_fire_offsets >=
572 VIA_FIRE_BUF_SIZE) {
546 DRM_ERROR("Fire offset buffer full.\n"); 573 DRM_ERROR("Fire offset buffer full.\n");
547 ret = 1; 574 ret = 1;
548 break; 575 break;
549 } 576 }
550 dev_priv->fire_offsets[dev_priv->num_fire_offsets++] = buf; 577 dev_priv->fire_offsets[dev_priv->
551 have_fire = 1; 578 num_fire_offsets++] =
579 buf;
580 have_fire = 1;
552 buf++; 581 buf++;
553 if (buf < buf_end && *buf == a_fire) 582 if (buf < buf_end && *buf == a_fire)
554 buf++; 583 buf++;
555 break; 584 break;
556 } 585 }
557 if ((*buf == HALCYON_HEADER2) || 586 if ((*buf == HALCYON_HEADER2) ||
558 ((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD)) { 587 ((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD)) {
559 DRM_ERROR("Missing Vertex Fire command, " 588 DRM_ERROR("Missing Vertex Fire command, "
560 "Stray Vertex Fire command or verifier " 589 "Stray Vertex Fire command or verifier "
@@ -576,18 +605,14 @@ via_check_prim_list(uint32_t const **buffer, const uint32_t *buf_end,
576 ret = 1; 605 ret = 1;
577 break; 606 break;
578 } 607 }
579 } 608 }
580 *buffer = buf; 609 *buffer = buf;
581 return ret; 610 return ret;
582} 611}
583 612
584
585
586
587
588static __inline__ verifier_state_t 613static __inline__ verifier_state_t
589via_check_header2( uint32_t const **buffer, const uint32_t *buf_end, 614via_check_header2(uint32_t const **buffer, const uint32_t * buf_end,
590 drm_via_state_t *hc_state) 615 drm_via_state_t * hc_state)
591{ 616{
592 uint32_t cmd; 617 uint32_t cmd;
593 int hz_mode; 618 int hz_mode;
@@ -595,17 +620,17 @@ via_check_header2( uint32_t const **buffer, const uint32_t *buf_end,
595 const uint32_t *buf = *buffer; 620 const uint32_t *buf = *buffer;
596 const hazard_t *hz_table; 621 const hazard_t *hz_table;
597 622
598
599 if ((buf_end - buf) < 2) { 623 if ((buf_end - buf) < 2) {
600 DRM_ERROR("Illegal termination of DMA HALCYON_HEADER2 sequence.\n"); 624 DRM_ERROR
625 ("Illegal termination of DMA HALCYON_HEADER2 sequence.\n");
601 return state_error; 626 return state_error;
602 } 627 }
603 buf++; 628 buf++;
604 cmd = (*buf++ & 0xFFFF0000) >> 16; 629 cmd = (*buf++ & 0xFFFF0000) >> 16;
605 630
606 switch(cmd) { 631 switch (cmd) {
607 case HC_ParaType_CmdVdata: 632 case HC_ParaType_CmdVdata:
608 if (via_check_prim_list(&buf, buf_end, hc_state )) 633 if (via_check_prim_list(&buf, buf_end, hc_state))
609 return state_error; 634 return state_error;
610 *buffer = buf; 635 *buffer = buf;
611 return state_command; 636 return state_command;
@@ -650,13 +675,13 @@ via_check_header2( uint32_t const **buffer, const uint32_t *buf_end,
650 */ 675 */
651 676
652 DRM_ERROR("Invalid or unimplemented HALCYON_HEADER2 " 677 DRM_ERROR("Invalid or unimplemented HALCYON_HEADER2 "
653 "DMA subcommand: 0x%x. Previous dword: 0x%x\n", 678 "DMA subcommand: 0x%x. Previous dword: 0x%x\n",
654 cmd, *(buf -2)); 679 cmd, *(buf - 2));
655 *buffer = buf; 680 *buffer = buf;
656 return state_error; 681 return state_error;
657 } 682 }
658 683
659 while(buf < buf_end) { 684 while (buf < buf_end) {
660 cmd = *buf++; 685 cmd = *buf++;
661 if ((hz = hz_table[cmd >> 24])) { 686 if ((hz = hz_table[cmd >> 24])) {
662 if ((hz_mode = investigate_hazard(cmd, hz, hc_state))) { 687 if ((hz_mode = investigate_hazard(cmd, hz, hc_state))) {
@@ -666,7 +691,7 @@ via_check_header2( uint32_t const **buffer, const uint32_t *buf_end,
666 } 691 }
667 return state_error; 692 return state_error;
668 } 693 }
669 } else if (hc_state->unfinished && 694 } else if (hc_state->unfinished &&
670 finish_current_sequence(hc_state)) { 695 finish_current_sequence(hc_state)) {
671 return state_error; 696 return state_error;
672 } 697 }
@@ -679,64 +704,65 @@ via_check_header2( uint32_t const **buffer, const uint32_t *buf_end,
679} 704}
680 705
681static __inline__ verifier_state_t 706static __inline__ verifier_state_t
682via_parse_header2( drm_via_private_t *dev_priv, uint32_t const **buffer, const uint32_t *buf_end, 707via_parse_header2(drm_via_private_t * dev_priv, uint32_t const **buffer,
683 int *fire_count) 708 const uint32_t * buf_end, int *fire_count)
684{ 709{
685 uint32_t cmd; 710 uint32_t cmd;
686 const uint32_t *buf = *buffer; 711 const uint32_t *buf = *buffer;
687 const uint32_t *next_fire; 712 const uint32_t *next_fire;
688 int burst = 0; 713 int burst = 0;
689 714
690 next_fire = dev_priv->fire_offsets[*fire_count]; 715 next_fire = dev_priv->fire_offsets[*fire_count];
691 buf++; 716 buf++;
692 cmd = (*buf & 0xFFFF0000) >> 16; 717 cmd = (*buf & 0xFFFF0000) >> 16;
693 VIA_WRITE(HC_REG_TRANS_SET + HC_REG_BASE, *buf++); 718 VIA_WRITE(HC_REG_TRANS_SET + HC_REG_BASE, *buf++);
694 switch(cmd) { 719 switch (cmd) {
695 case HC_ParaType_CmdVdata: 720 case HC_ParaType_CmdVdata:
696 while ((buf < buf_end) && 721 while ((buf < buf_end) &&
697 (*fire_count < dev_priv->num_fire_offsets) && 722 (*fire_count < dev_priv->num_fire_offsets) &&
698 (*buf & HC_ACMD_MASK) == HC_ACMD_HCmdB ) { 723 (*buf & HC_ACMD_MASK) == HC_ACMD_HCmdB) {
699 while(buf <= next_fire) { 724 while (buf <= next_fire) {
700 VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE + (burst & 63), *buf++); 725 VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE +
726 (burst & 63), *buf++);
701 burst += 4; 727 burst += 4;
702 } 728 }
703 if ( ( buf < buf_end ) && ((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD)) 729 if ((buf < buf_end)
730 && ((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD))
704 buf++; 731 buf++;
705 732
706 if (++(*fire_count) < dev_priv->num_fire_offsets) 733 if (++(*fire_count) < dev_priv->num_fire_offsets)
707 next_fire = dev_priv->fire_offsets[*fire_count]; 734 next_fire = dev_priv->fire_offsets[*fire_count];
708 } 735 }
709 break; 736 break;
710 default: 737 default:
711 while(buf < buf_end) { 738 while (buf < buf_end) {
712 739
713 if ( *buf == HC_HEADER2 || 740 if (*buf == HC_HEADER2 ||
714 (*buf & HALCYON_HEADER1MASK) == HALCYON_HEADER1 || 741 (*buf & HALCYON_HEADER1MASK) == HALCYON_HEADER1 ||
715 (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5 || 742 (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5 ||
716 (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6 ) break; 743 (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6)
717 744 break;
718 VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE + (burst & 63), *buf++); 745
719 burst +=4; 746 VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE +
747 (burst & 63), *buf++);
748 burst += 4;
720 } 749 }
721 } 750 }
722 *buffer = buf; 751 *buffer = buf;
723 return state_command; 752 return state_command;
724} 753}
725 754
726 755static __inline__ int verify_mmio_address(uint32_t address)
727
728static __inline__ int
729verify_mmio_address( uint32_t address)
730{ 756{
731 if ((address > 0x3FF) && (address < 0xC00 )) { 757 if ((address > 0x3FF) && (address < 0xC00)) {
732 DRM_ERROR("Invalid VIDEO DMA command. " 758 DRM_ERROR("Invalid VIDEO DMA command. "
733 "Attempt to access 3D- or command burst area.\n"); 759 "Attempt to access 3D- or command burst area.\n");
734 return 1; 760 return 1;
735 } else if ((address > 0xCFF) && (address < 0x1300)) { 761 } else if ((address > 0xCFF) && (address < 0x1300)) {
736 DRM_ERROR("Invalid VIDEO DMA command. " 762 DRM_ERROR("Invalid VIDEO DMA command. "
737 "Attempt to access PCI DMA area.\n"); 763 "Attempt to access PCI DMA area.\n");
738 return 1; 764 return 1;
739 } else if (address > 0x13FF ) { 765 } else if (address > 0x13FF) {
740 DRM_ERROR("Invalid VIDEO DMA command. " 766 DRM_ERROR("Invalid VIDEO DMA command. "
741 "Attempt to access VGA registers.\n"); 767 "Attempt to access VGA registers.\n");
742 return 1; 768 return 1;
@@ -745,7 +771,8 @@ verify_mmio_address( uint32_t address)
745} 771}
746 772
747static __inline__ int 773static __inline__ int
748verify_video_tail( uint32_t const **buffer, const uint32_t *buf_end, uint32_t dwords) 774verify_video_tail(uint32_t const **buffer, const uint32_t * buf_end,
775 uint32_t dwords)
749{ 776{
750 const uint32_t *buf = *buffer; 777 const uint32_t *buf = *buffer;
751 778
@@ -762,10 +789,9 @@ verify_video_tail( uint32_t const **buffer, const uint32_t *buf_end, uint32_t dw
762 *buffer = buf; 789 *buffer = buf;
763 return 0; 790 return 0;
764} 791}
765
766 792
767static __inline__ verifier_state_t 793static __inline__ verifier_state_t
768via_check_header1( uint32_t const **buffer, const uint32_t *buf_end ) 794via_check_header1(uint32_t const **buffer, const uint32_t * buf_end)
769{ 795{
770 uint32_t cmd; 796 uint32_t cmd;
771 const uint32_t *buf = *buffer; 797 const uint32_t *buf = *buffer;
@@ -774,21 +800,21 @@ via_check_header1( uint32_t const **buffer, const uint32_t *buf_end )
774 while (buf < buf_end) { 800 while (buf < buf_end) {
775 cmd = *buf; 801 cmd = *buf;
776 if ((cmd > ((0x3FF >> 2) | HALCYON_HEADER1)) && 802 if ((cmd > ((0x3FF >> 2) | HALCYON_HEADER1)) &&
777 (cmd < ((0xC00 >> 2) | HALCYON_HEADER1))) { 803 (cmd < ((0xC00 >> 2) | HALCYON_HEADER1))) {
778 if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1) 804 if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1)
779 break; 805 break;
780 DRM_ERROR("Invalid HALCYON_HEADER1 command. " 806 DRM_ERROR("Invalid HALCYON_HEADER1 command. "
781 "Attempt to access 3D- or command burst area.\n"); 807 "Attempt to access 3D- or command burst area.\n");
782 ret = state_error; 808 ret = state_error;
783 break; 809 break;
784 } else if (cmd > ((0xCFF >> 2) | HALCYON_HEADER1)) { 810 } else if (cmd > ((0xCFF >> 2) | HALCYON_HEADER1)) {
785 if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1) 811 if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1)
786 break; 812 break;
787 DRM_ERROR("Invalid HALCYON_HEADER1 command. " 813 DRM_ERROR("Invalid HALCYON_HEADER1 command. "
788 "Attempt to access VGA registers.\n"); 814 "Attempt to access VGA registers.\n");
789 ret = state_error; 815 ret = state_error;
790 break; 816 break;
791 } else { 817 } else {
792 buf += 2; 818 buf += 2;
793 } 819 }
794 } 820 }
@@ -797,15 +823,17 @@ via_check_header1( uint32_t const **buffer, const uint32_t *buf_end )
797} 823}
798 824
799static __inline__ verifier_state_t 825static __inline__ verifier_state_t
800via_parse_header1( drm_via_private_t *dev_priv, uint32_t const **buffer, const uint32_t *buf_end ) 826via_parse_header1(drm_via_private_t * dev_priv, uint32_t const **buffer,
827 const uint32_t * buf_end)
801{ 828{
802 register uint32_t cmd; 829 register uint32_t cmd;
803 const uint32_t *buf = *buffer; 830 const uint32_t *buf = *buffer;
804 831
805 while (buf < buf_end) { 832 while (buf < buf_end) {
806 cmd = *buf; 833 cmd = *buf;
807 if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1) break; 834 if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1)
808 VIA_WRITE( (cmd & ~HALCYON_HEADER1MASK) << 2, *++buf); 835 break;
836 VIA_WRITE((cmd & ~HALCYON_HEADER1MASK) << 2, *++buf);
809 buf++; 837 buf++;
810 } 838 }
811 *buffer = buf; 839 *buffer = buf;
@@ -813,7 +841,7 @@ via_parse_header1( drm_via_private_t *dev_priv, uint32_t const **buffer, const u
813} 841}
814 842
815static __inline__ verifier_state_t 843static __inline__ verifier_state_t
816via_check_vheader5( uint32_t const **buffer, const uint32_t *buf_end ) 844via_check_vheader5(uint32_t const **buffer, const uint32_t * buf_end)
817{ 845{
818 uint32_t data; 846 uint32_t data;
819 const uint32_t *buf = *buffer; 847 const uint32_t *buf = *buffer;
@@ -836,41 +864,41 @@ via_check_vheader5( uint32_t const **buffer, const uint32_t *buf_end )
836 DRM_ERROR("Illegal header5 header data\n"); 864 DRM_ERROR("Illegal header5 header data\n");
837 return state_error; 865 return state_error;
838 } 866 }
839 if (eat_words(&buf, buf_end, data)) 867 if (eat_words(&buf, buf_end, data))
840 return state_error; 868 return state_error;
841 if ((data & 3) && verify_video_tail(&buf, buf_end, 4 - (data & 3))) 869 if ((data & 3) && verify_video_tail(&buf, buf_end, 4 - (data & 3)))
842 return state_error; 870 return state_error;
843 *buffer = buf; 871 *buffer = buf;
844 return state_command; 872 return state_command;
845 873
846} 874}
847 875
848static __inline__ verifier_state_t 876static __inline__ verifier_state_t
849via_parse_vheader5( drm_via_private_t *dev_priv, uint32_t const **buffer, const uint32_t *buf_end ) 877via_parse_vheader5(drm_via_private_t * dev_priv, uint32_t const **buffer,
878 const uint32_t * buf_end)
850{ 879{
851 uint32_t addr, count, i; 880 uint32_t addr, count, i;
852 const uint32_t *buf = *buffer; 881 const uint32_t *buf = *buffer;
853 882
854 addr = *buf++ & ~VIA_VIDEOMASK; 883 addr = *buf++ & ~VIA_VIDEOMASK;
855 i = count = *buf; 884 i = count = *buf;
856 buf += 3; 885 buf += 3;
857 while(i--) { 886 while (i--) {
858 VIA_WRITE(addr, *buf++); 887 VIA_WRITE(addr, *buf++);
859 } 888 }
860 if (count & 3) buf += 4 - (count & 3); 889 if (count & 3)
890 buf += 4 - (count & 3);
861 *buffer = buf; 891 *buffer = buf;
862 return state_command; 892 return state_command;
863} 893}
864
865 894
866static __inline__ verifier_state_t 895static __inline__ verifier_state_t
867via_check_vheader6( uint32_t const **buffer, const uint32_t *buf_end ) 896via_check_vheader6(uint32_t const **buffer, const uint32_t * buf_end)
868{ 897{
869 uint32_t data; 898 uint32_t data;
870 const uint32_t *buf = *buffer; 899 const uint32_t *buf = *buffer;
871 uint32_t i; 900 uint32_t i;
872 901
873
874 if (buf_end - buf < 4) { 902 if (buf_end - buf < 4) {
875 DRM_ERROR("Illegal termination of video header6 command\n"); 903 DRM_ERROR("Illegal termination of video header6 command\n");
876 return state_error; 904 return state_error;
@@ -889,7 +917,7 @@ via_check_vheader6( uint32_t const **buffer, const uint32_t *buf_end )
889 DRM_ERROR("Illegal termination of video header6 command\n"); 917 DRM_ERROR("Illegal termination of video header6 command\n");
890 return state_error; 918 return state_error;
891 } 919 }
892 for (i=0; i<data; ++i) { 920 for (i = 0; i < data; ++i) {
893 if (verify_mmio_address(*buf++)) 921 if (verify_mmio_address(*buf++))
894 return state_error; 922 return state_error;
895 buf++; 923 buf++;
@@ -899,42 +927,42 @@ via_check_vheader6( uint32_t const **buffer, const uint32_t *buf_end )
899 return state_error; 927 return state_error;
900 *buffer = buf; 928 *buffer = buf;
901 return state_command; 929 return state_command;
902} 930}
903 931
904static __inline__ verifier_state_t 932static __inline__ verifier_state_t
905via_parse_vheader6( drm_via_private_t *dev_priv, uint32_t const **buffer, const uint32_t *buf_end ) 933via_parse_vheader6(drm_via_private_t * dev_priv, uint32_t const **buffer,
934 const uint32_t * buf_end)
906{ 935{
907 936
908 uint32_t addr, count, i; 937 uint32_t addr, count, i;
909 const uint32_t *buf = *buffer; 938 const uint32_t *buf = *buffer;
910 939
911 i = count = *++buf; 940 i = count = *++buf;
912 buf += 3; 941 buf += 3;
913 while(i--) { 942 while (i--) {
914 addr = *buf++; 943 addr = *buf++;
915 VIA_WRITE(addr, *buf++); 944 VIA_WRITE(addr, *buf++);
916 } 945 }
917 count <<= 1; 946 count <<= 1;
918 if (count & 3) buf += 4 - (count & 3); 947 if (count & 3)
948 buf += 4 - (count & 3);
919 *buffer = buf; 949 *buffer = buf;
920 return state_command; 950 return state_command;
921} 951}
922
923
924 952
925int 953int
926via_verify_command_stream(const uint32_t * buf, unsigned int size, drm_device_t *dev, 954via_verify_command_stream(const uint32_t * buf, unsigned int size,
927 int agp) 955 drm_device_t * dev, int agp)
928{ 956{
929 957
930 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; 958 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
931 drm_via_state_t *hc_state = &dev_priv->hc_state; 959 drm_via_state_t *hc_state = &dev_priv->hc_state;
932 drm_via_state_t saved_state = *hc_state; 960 drm_via_state_t saved_state = *hc_state;
933 uint32_t cmd; 961 uint32_t cmd;
934 const uint32_t *buf_end = buf + ( size >> 2 ); 962 const uint32_t *buf_end = buf + (size >> 2);
935 verifier_state_t state = state_command; 963 verifier_state_t state = state_command;
936 int pro_group_a = dev_priv->pro_group_a; 964 int pro_group_a = dev_priv->pro_group_a;
937 965
938 hc_state->dev = dev; 966 hc_state->dev = dev;
939 hc_state->unfinished = no_sequence; 967 hc_state->unfinished = no_sequence;
940 hc_state->map_cache = NULL; 968 hc_state->map_cache = NULL;
@@ -946,38 +974,41 @@ via_verify_command_stream(const uint32_t * buf, unsigned int size, drm_device_t
946 974
947 switch (state) { 975 switch (state) {
948 case state_header2: 976 case state_header2:
949 state = via_check_header2( &buf, buf_end, hc_state ); 977 state = via_check_header2(&buf, buf_end, hc_state);
950 break; 978 break;
951 case state_header1: 979 case state_header1:
952 state = via_check_header1( &buf, buf_end ); 980 state = via_check_header1(&buf, buf_end);
953 break; 981 break;
954 case state_vheader5: 982 case state_vheader5:
955 state = via_check_vheader5( &buf, buf_end ); 983 state = via_check_vheader5(&buf, buf_end);
956 break; 984 break;
957 case state_vheader6: 985 case state_vheader6:
958 state = via_check_vheader6( &buf, buf_end ); 986 state = via_check_vheader6(&buf, buf_end);
959 break; 987 break;
960 case state_command: 988 case state_command:
961 if (HALCYON_HEADER2 == (cmd = *buf)) 989 if (HALCYON_HEADER2 == (cmd = *buf))
962 state = state_header2; 990 state = state_header2;
963 else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) 991 else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
964 state = state_header1; 992 state = state_header1;
965 else if (pro_group_a && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5) 993 else if (pro_group_a
994 && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5)
966 state = state_vheader5; 995 state = state_vheader5;
967 else if (pro_group_a && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6) 996 else if (pro_group_a
997 && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6)
968 state = state_vheader6; 998 state = state_vheader6;
969 else { 999 else {
970 DRM_ERROR("Invalid / Unimplemented DMA HEADER command. 0x%x\n", 1000 DRM_ERROR
971 cmd); 1001 ("Invalid / Unimplemented DMA HEADER command. 0x%x\n",
1002 cmd);
972 state = state_error; 1003 state = state_error;
973 } 1004 }
974 break; 1005 break;
975 case state_error: 1006 case state_error:
976 default: 1007 default:
977 *hc_state = saved_state; 1008 *hc_state = saved_state;
978 return DRM_ERR(EINVAL); 1009 return DRM_ERR(EINVAL);
979 } 1010 }
980 } 1011 }
981 if (state == state_error) { 1012 if (state == state_error) {
982 *hc_state = saved_state; 1013 *hc_state = saved_state;
983 return DRM_ERR(EINVAL); 1014 return DRM_ERR(EINVAL);
@@ -985,77 +1016,81 @@ via_verify_command_stream(const uint32_t * buf, unsigned int size, drm_device_t
985 return 0; 1016 return 0;
986} 1017}
987 1018
988int 1019int
989via_parse_command_stream(drm_device_t *dev, const uint32_t * buf, unsigned int size) 1020via_parse_command_stream(drm_device_t * dev, const uint32_t * buf,
1021 unsigned int size)
990{ 1022{
991 1023
992 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; 1024 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
993 uint32_t cmd; 1025 uint32_t cmd;
994 const uint32_t *buf_end = buf + ( size >> 2 ); 1026 const uint32_t *buf_end = buf + (size >> 2);
995 verifier_state_t state = state_command; 1027 verifier_state_t state = state_command;
996 int fire_count = 0; 1028 int fire_count = 0;
997 1029
998 while (buf < buf_end) { 1030 while (buf < buf_end) {
999 1031
1000 switch (state) { 1032 switch (state) {
1001 case state_header2: 1033 case state_header2:
1002 state = via_parse_header2( dev_priv, &buf, buf_end, &fire_count ); 1034 state =
1035 via_parse_header2(dev_priv, &buf, buf_end,
1036 &fire_count);
1003 break; 1037 break;
1004 case state_header1: 1038 case state_header1:
1005 state = via_parse_header1( dev_priv, &buf, buf_end ); 1039 state = via_parse_header1(dev_priv, &buf, buf_end);
1006 break; 1040 break;
1007 case state_vheader5: 1041 case state_vheader5:
1008 state = via_parse_vheader5( dev_priv, &buf, buf_end ); 1042 state = via_parse_vheader5(dev_priv, &buf, buf_end);
1009 break; 1043 break;
1010 case state_vheader6: 1044 case state_vheader6:
1011 state = via_parse_vheader6( dev_priv, &buf, buf_end ); 1045 state = via_parse_vheader6(dev_priv, &buf, buf_end);
1012 break; 1046 break;
1013 case state_command: 1047 case state_command:
1014 if (HALCYON_HEADER2 == (cmd = *buf)) 1048 if (HALCYON_HEADER2 == (cmd = *buf))
1015 state = state_header2; 1049 state = state_header2;
1016 else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) 1050 else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
1017 state = state_header1; 1051 state = state_header1;
1018 else if ((cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5) 1052 else if ((cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5)
1019 state = state_vheader5; 1053 state = state_vheader5;
1020 else if ((cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6) 1054 else if ((cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6)
1021 state = state_vheader6; 1055 state = state_vheader6;
1022 else { 1056 else {
1023 DRM_ERROR("Invalid / Unimplemented DMA HEADER command. 0x%x\n", 1057 DRM_ERROR
1024 cmd); 1058 ("Invalid / Unimplemented DMA HEADER command. 0x%x\n",
1059 cmd);
1025 state = state_error; 1060 state = state_error;
1026 } 1061 }
1027 break; 1062 break;
1028 case state_error: 1063 case state_error:
1029 default: 1064 default:
1030 return DRM_ERR(EINVAL); 1065 return DRM_ERR(EINVAL);
1031 } 1066 }
1032 } 1067 }
1033 if (state == state_error) { 1068 if (state == state_error) {
1034 return DRM_ERR(EINVAL); 1069 return DRM_ERR(EINVAL);
1035 } 1070 }
1036 return 0; 1071 return 0;
1037} 1072}
1038 1073
1039 1074static void
1040
1041static void
1042setup_hazard_table(hz_init_t init_table[], hazard_t table[], int size) 1075setup_hazard_table(hz_init_t init_table[], hazard_t table[], int size)
1043{ 1076{
1044 int i; 1077 int i;
1045 1078
1046 for(i=0; i<256; ++i) { 1079 for (i = 0; i < 256; ++i) {
1047 table[i] = forbidden_command; 1080 table[i] = forbidden_command;
1048 } 1081 }
1049 1082
1050 for(i=0; i<size; ++i) { 1083 for (i = 0; i < size; ++i) {
1051 table[init_table[i].code] = init_table[i].hz; 1084 table[init_table[i].code] = init_table[i].hz;
1052 } 1085 }
1053} 1086}
1054 1087
1055void 1088void via_init_command_verifier(void)
1056via_init_command_verifier( void )
1057{ 1089{
1058 setup_hazard_table(init_table1, table1, sizeof(init_table1) / sizeof(hz_init_t)); 1090 setup_hazard_table(init_table1, table1,
1059 setup_hazard_table(init_table2, table2, sizeof(init_table2) / sizeof(hz_init_t)); 1091 sizeof(init_table1) / sizeof(hz_init_t));
1060 setup_hazard_table(init_table3, table3, sizeof(init_table3) / sizeof(hz_init_t)); 1092 setup_hazard_table(init_table2, table2,
1093 sizeof(init_table2) / sizeof(hz_init_t));
1094 setup_hazard_table(init_table3, table3,
1095 sizeof(init_table3) / sizeof(hz_init_t));
1061} 1096}
diff --git a/drivers/char/drm/via_verifier.h b/drivers/char/drm/via_verifier.h
index a8e13592620f..eb4eda344345 100644
--- a/drivers/char/drm/via_verifier.h
+++ b/drivers/char/drm/via_verifier.h
@@ -26,23 +26,21 @@
26#ifndef _VIA_VERIFIER_H_ 26#ifndef _VIA_VERIFIER_H_
27#define _VIA_VERIFIER_H_ 27#define _VIA_VERIFIER_H_
28 28
29typedef enum{ 29typedef enum {
30 no_sequence = 0, 30 no_sequence = 0,
31 z_address, 31 z_address,
32 dest_address, 32 dest_address,
33 tex_address 33 tex_address
34}drm_via_sequence_t; 34} drm_via_sequence_t;
35 35
36 36typedef struct {
37
38typedef struct{
39 unsigned texture; 37 unsigned texture;
40 uint32_t z_addr; 38 uint32_t z_addr;
41 uint32_t d_addr; 39 uint32_t d_addr;
42 uint32_t t_addr[2][10]; 40 uint32_t t_addr[2][10];
43 uint32_t pitch[2][10]; 41 uint32_t pitch[2][10];
44 uint32_t height[2][10]; 42 uint32_t height[2][10];
45 uint32_t tex_level_lo[2]; 43 uint32_t tex_level_lo[2];
46 uint32_t tex_level_hi[2]; 44 uint32_t tex_level_hi[2];
47 uint32_t tex_palette_size[2]; 45 uint32_t tex_palette_size[2];
48 drm_via_sequence_t unfinished; 46 drm_via_sequence_t unfinished;
@@ -55,7 +53,7 @@ typedef struct{
55 const uint32_t *buf_start; 53 const uint32_t *buf_start;
56} drm_via_state_t; 54} drm_via_state_t;
57 55
58extern int via_verify_command_stream(const uint32_t * buf, unsigned int size, 56extern int via_verify_command_stream(const uint32_t * buf, unsigned int size,
59 drm_device_t *dev, int agp); 57 drm_device_t * dev, int agp);
60 58
61#endif 59#endif
diff --git a/drivers/char/drm/via_video.c b/drivers/char/drm/via_video.c
index 1e2d444587bf..7fab9fbdf424 100644
--- a/drivers/char/drm/via_video.c
+++ b/drivers/char/drm/via_video.c
@@ -29,8 +29,7 @@
29#include "via_drm.h" 29#include "via_drm.h"
30#include "via_drv.h" 30#include "via_drv.h"
31 31
32void 32void via_init_futex(drm_via_private_t * dev_priv)
33via_init_futex(drm_via_private_t *dev_priv)
34{ 33{
35 unsigned int i; 34 unsigned int i;
36 35
@@ -42,30 +41,28 @@ via_init_futex(drm_via_private_t *dev_priv)
42 } 41 }
43} 42}
44 43
45void 44void via_cleanup_futex(drm_via_private_t * dev_priv)
46via_cleanup_futex(drm_via_private_t *dev_priv)
47{ 45{
48} 46}
49 47
50void 48void via_release_futex(drm_via_private_t * dev_priv, int context)
51via_release_futex(drm_via_private_t *dev_priv, int context)
52{ 49{
53 unsigned int i; 50 unsigned int i;
54 volatile int *lock; 51 volatile int *lock;
55 52
56 for (i=0; i < VIA_NR_XVMC_LOCKS; ++i) { 53 for (i = 0; i < VIA_NR_XVMC_LOCKS; ++i) {
57 lock = (int *) XVMCLOCKPTR(dev_priv->sarea_priv, i); 54 lock = (int *)XVMCLOCKPTR(dev_priv->sarea_priv, i);
58 if ( (_DRM_LOCKING_CONTEXT( *lock ) == context)) { 55 if ((_DRM_LOCKING_CONTEXT(*lock) == context)) {
59 if (_DRM_LOCK_IS_HELD( *lock ) && (*lock & _DRM_LOCK_CONT)) { 56 if (_DRM_LOCK_IS_HELD(*lock)
60 DRM_WAKEUP( &(dev_priv->decoder_queue[i])); 57 && (*lock & _DRM_LOCK_CONT)) {
58 DRM_WAKEUP(&(dev_priv->decoder_queue[i]));
61 } 59 }
62 *lock = 0; 60 *lock = 0;
63 } 61 }
64 } 62 }
65} 63}
66 64
67int 65int via_decoder_futex(DRM_IOCTL_ARGS)
68via_decoder_futex(DRM_IOCTL_ARGS)
69{ 66{
70 DRM_DEVICE; 67 DRM_DEVICE;
71 drm_via_futex_t fx; 68 drm_via_futex_t fx;
@@ -95,4 +92,3 @@ via_decoder_futex(DRM_IOCTL_ARGS)
95 } 92 }
96 return 0; 93 return 0;
97} 94}
98
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 17:25:53 -0400