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authorMaciej Cencora <m.cencora@gmail.com>2008-02-19 06:32:45 -0500
committerDave Airlie <airlied@redhat.com>2008-02-19 18:35:42 -0500
commit60f92683943c5b7a85963b283d6f8a853aa09203 (patch)
tree0291f47cc073c218cdd393b99735d8c428c540af /drivers/char/drm
parent00e962c5408b9f2d0bebd2308673fe982cb9a5fe (diff)
drm/radeon: add initial rs690 support to drm.
This adds support for configuring the RS690 GART. Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/char/drm')
-rw-r--r--drivers/char/drm/drm_pciids.h1
-rw-r--r--drivers/char/drm/radeon_cp.c81
-rw-r--r--drivers/char/drm/radeon_drv.h38
3 files changed, 120 insertions, 0 deletions
diff --git a/drivers/char/drm/drm_pciids.h b/drivers/char/drm/drm_pciids.h
index f52468843678..5de6f8788b60 100644
--- a/drivers/char/drm/drm_pciids.h
+++ b/drivers/char/drm/drm_pciids.h
@@ -236,6 +236,7 @@
236 {0x1002, 0x7297, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ 236 {0x1002, 0x7297, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \
237 {0x1002, 0x7834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ 237 {0x1002, 0x7834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \
238 {0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 238 {0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
239 {0x1002, 0x791e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
239 {0, 0, 0} 240 {0, 0, 0}
240 241
241#define r128_PCI_IDS \ 242#define r128_PCI_IDS \
diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c
index 5dc799ab86b8..833abc7e55fb 100644
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@ -825,11 +825,19 @@ static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
825 return ret; 825 return ret;
826} 826}
827 827
828static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
829{
830 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
831 return RADEON_READ(RS690_MC_DATA);
832}
833
828u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) 834u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
829{ 835{
830 836
831 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 837 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
832 return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); 838 return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
839 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
840 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
833 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 841 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
834 return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); 842 return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
835 else 843 else
@@ -840,6 +848,8 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
840{ 848{
841 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 849 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
842 RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); 850 RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
851 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
852 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
843 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 853 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
844 RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); 854 RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
845 else 855 else
@@ -850,6 +860,8 @@ static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_lo
850{ 860{
851 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 861 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
852 RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); 862 RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
863 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
864 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
853 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 865 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
854 RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); 866 RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
855 else 867 else
@@ -1362,6 +1374,70 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
1362 } 1374 }
1363} 1375}
1364 1376
1377/* Enable or disable RS690 GART on the chip */
1378static void radeon_set_rs690gart(drm_radeon_private_t *dev_priv, int on)
1379{
1380 u32 temp;
1381
1382 if (on) {
1383 DRM_DEBUG("programming rs690 gart %08X %08lX %08X\n",
1384 dev_priv->gart_vm_start,
1385 (long)dev_priv->gart_info.bus_addr,
1386 dev_priv->gart_size);
1387
1388 temp = RS690_READ_MCIND(dev_priv, RS690_MC_MISC_CNTL);
1389 RS690_WRITE_MCIND(RS690_MC_MISC_CNTL, 0x5000);
1390
1391 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE,
1392 RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB);
1393
1394 temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_FEATURE_ID);
1395 RS690_WRITE_MCIND(RS690_MC_GART_FEATURE_ID, 0x42040800);
1396
1397 RS690_WRITE_MCIND(RS690_MC_GART_BASE,
1398 dev_priv->gart_info.bus_addr);
1399
1400 temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_MODE_CONTROL);
1401 RS690_WRITE_MCIND(RS690_MC_AGP_MODE_CONTROL, 0x01400000);
1402
1403 RS690_WRITE_MCIND(RS690_MC_AGP_BASE,
1404 (unsigned int)dev_priv->gart_vm_start);
1405
1406 dev_priv->gart_size = 32*1024*1024;
1407 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
1408 0xffff0000) | (dev_priv->gart_vm_start >> 16));
1409
1410 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp);
1411
1412 temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_SIZE);
1413 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE,
1414 RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB);
1415
1416 do {
1417 temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL);
1418 if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
1419 RS690_MC_GART_CLEAR_DONE)
1420 break;
1421 DRM_UDELAY(1);
1422 } while (1);
1423
1424 RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL,
1425 RS690_MC_GART_CC_CLEAR);
1426 do {
1427 temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL);
1428 if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
1429 RS690_MC_GART_CLEAR_DONE)
1430 break;
1431 DRM_UDELAY(1);
1432 } while (1);
1433
1434 RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL,
1435 RS690_MC_GART_CC_NO_CHANGE);
1436 } else {
1437 RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, RS690_MC_GART_DIS);
1438 }
1439}
1440
1365static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) 1441static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1366{ 1442{
1367 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); 1443 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
@@ -1396,6 +1472,11 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1396{ 1472{
1397 u32 tmp; 1473 u32 tmp;
1398 1474
1475 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
1476 radeon_set_rs690gart(dev_priv, on);
1477 return;
1478 }
1479
1399 if (dev_priv->flags & RADEON_IS_IGPGART) { 1480 if (dev_priv->flags & RADEON_IS_IGPGART) {
1400 radeon_set_igpgart(dev_priv, on); 1481 radeon_set_igpgart(dev_priv, on);
1401 return; 1482 return;
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h
index 4434332c79bc..173ae620223a 100644
--- a/drivers/char/drm/radeon_drv.h
+++ b/drivers/char/drm/radeon_drv.h
@@ -123,6 +123,7 @@ enum radeon_family {
123 CHIP_R420, 123 CHIP_R420,
124 CHIP_RV410, 124 CHIP_RV410,
125 CHIP_RS400, 125 CHIP_RS400,
126 CHIP_RS690,
126 CHIP_RV515, 127 CHIP_RV515,
127 CHIP_R520, 128 CHIP_R520,
128 CHIP_RV530, 129 CHIP_RV530,
@@ -467,6 +468,36 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
467#define RADEON_IGPGART_ENABLE 0x38 468#define RADEON_IGPGART_ENABLE 0x38
468#define RADEON_IGPGART_UNK_39 0x39 469#define RADEON_IGPGART_UNK_39 0x39
469 470
471#define RS690_MC_INDEX 0x78
472# define RS690_MC_INDEX_MASK 0x1ff
473# define RS690_MC_INDEX_WR_EN (1 << 9)
474# define RS690_MC_INDEX_WR_ACK 0x7f
475#define RS690_MC_DATA 0x7c
476
477#define RS690_MC_MISC_CNTL 0x18
478#define RS690_MC_GART_FEATURE_ID 0x2b
479#define RS690_MC_GART_BASE 0x2c
480#define RS690_MC_GART_CACHE_CNTL 0x2e
481# define RS690_MC_GART_CC_NO_CHANGE 0x0
482# define RS690_MC_GART_CC_CLEAR 0x1
483# define RS690_MC_GART_CLEAR_STATUS (1 << 1)
484# define RS690_MC_GART_CLEAR_DONE (0 << 1)
485# define RS690_MC_GART_CLEAR_PENDING (1 << 1)
486#define RS690_MC_AGP_SIZE 0x38
487# define RS690_MC_GART_DIS 0x0
488# define RS690_MC_GART_EN 0x1
489# define RS690_MC_AGP_SIZE_32MB (0 << 1)
490# define RS690_MC_AGP_SIZE_64MB (1 << 1)
491# define RS690_MC_AGP_SIZE_128MB (2 << 1)
492# define RS690_MC_AGP_SIZE_256MB (3 << 1)
493# define RS690_MC_AGP_SIZE_512MB (4 << 1)
494# define RS690_MC_AGP_SIZE_1GB (5 << 1)
495# define RS690_MC_AGP_SIZE_2GB (6 << 1)
496#define RS690_MC_AGP_MODE_CONTROL 0x39
497#define RS690_MC_FB_LOCATION 0x100
498#define RS690_MC_AGP_LOCATION 0x101
499#define RS690_MC_AGP_BASE 0x102
500
470#define R520_MC_IND_INDEX 0x70 501#define R520_MC_IND_INDEX 0x70
471#define R520_MC_IND_WR_EN (1<<24) 502#define R520_MC_IND_WR_EN (1<<24)
472#define R520_MC_IND_DATA 0x74 503#define R520_MC_IND_DATA 0x74
@@ -1076,6 +1107,13 @@ do { \
1076 RADEON_WRITE(R520_MC_IND_INDEX, 0); \ 1107 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1077 } while (0) 1108 } while (0)
1078 1109
1110#define RS690_WRITE_MCIND( addr, val ) \
1111do { \
1112 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1113 RADEON_WRITE(RS690_MC_DATA, val); \
1114 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1115} while (0)
1116
1079#define CP_PACKET0( reg, n ) \ 1117#define CP_PACKET0( reg, n ) \
1080 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1118 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1081#define CP_PACKET0_TABLE( reg, n ) \ 1119#define CP_PACKET0_TABLE( reg, n ) \