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authorRoland Scheidegger <sroland@tungstengraphics.com>2008-06-18 21:36:04 -0400
committerDave Airlie <airlied@redhat.com>2008-06-18 21:36:04 -0400
commit9156cf09f56150ed89f77eaa4c386a07789776a0 (patch)
tree39088281aa78ab6e3188dcd789e35ff726a056c0 /drivers/char/drm
parentc0beb2a723d69934a53f51a9d664c5b1dbbf634b (diff)
drm/radeon: fix texture uploads with large 3d textures (bug 13980)
Texture uploads could hit the blitter coordinate limit, adjust the texture offset when uploading the pieces. Make sure to check the end address of the upload too. Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/char/drm')
-rw-r--r--drivers/char/drm/radeon_state.c14
1 files changed, 11 insertions, 3 deletions
diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c
index eee135712403..11c146b49211 100644
--- a/drivers/char/drm/radeon_state.c
+++ b/drivers/char/drm/radeon_state.c
@@ -1662,7 +1662,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
1662 u32 height; 1662 u32 height;
1663 int i; 1663 int i;
1664 u32 texpitch, microtile; 1664 u32 texpitch, microtile;
1665 u32 offset; 1665 u32 offset, byte_offset;
1666 RING_LOCALS; 1666 RING_LOCALS;
1667 1667
1668 if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) { 1668 if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) {
@@ -1727,6 +1727,13 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
1727 } else 1727 } else
1728 microtile = 0; 1728 microtile = 0;
1729 1729
1730 /* this might fail for zero-sized uploads - are those illegal? */
1731 if (!radeon_check_offset(dev_priv, tex->offset + image->height *
1732 blit_width - 1)) {
1733 DRM_ERROR("Invalid final destination offset\n");
1734 return -EINVAL;
1735 }
1736
1730 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width); 1737 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
1731 1738
1732 do { 1739 do {
@@ -1840,6 +1847,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
1840 } 1847 }
1841 1848
1842#undef RADEON_COPY_MT 1849#undef RADEON_COPY_MT
1850 byte_offset = (image->y & ~2047) * blit_width;
1843 buf->file_priv = file_priv; 1851 buf->file_priv = file_priv;
1844 buf->used = size; 1852 buf->used = size;
1845 offset = dev_priv->gart_buffers_offset + buf->offset; 1853 offset = dev_priv->gart_buffers_offset + buf->offset;
@@ -1854,9 +1862,9 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
1854 RADEON_DP_SRC_SOURCE_MEMORY | 1862 RADEON_DP_SRC_SOURCE_MEMORY |
1855 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); 1863 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
1856 OUT_RING((spitch << 22) | (offset >> 10)); 1864 OUT_RING((spitch << 22) | (offset >> 10));
1857 OUT_RING((texpitch << 22) | (tex->offset >> 10)); 1865 OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10)));
1858 OUT_RING(0); 1866 OUT_RING(0);
1859 OUT_RING((image->x << 16) | image->y); 1867 OUT_RING((image->x << 16) | (image->y % 2048));
1860 OUT_RING((image->width << 16) | height); 1868 OUT_RING((image->width << 16) | height);
1861 RADEON_WAIT_UNTIL_2D_IDLE(); 1869 RADEON_WAIT_UNTIL_2D_IDLE();
1862 ADVANCE_RING(); 1870 ADVANCE_RING();